1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_clean_tx_ring(struct igb_ring *); 119 static void igb_clean_rx_ring(struct igb_ring *); 120 static void igb_set_rx_mode(struct net_device *); 121 static void igb_update_phy_info(struct timer_list *); 122 static void igb_watchdog(struct timer_list *); 123 static void igb_watchdog_task(struct work_struct *); 124 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 125 static void igb_get_stats64(struct net_device *dev, 126 struct rtnl_link_stats64 *stats); 127 static int igb_change_mtu(struct net_device *, int); 128 static int igb_set_mac(struct net_device *, void *); 129 static void igb_set_uta(struct igb_adapter *adapter, bool set); 130 static irqreturn_t igb_intr(int irq, void *); 131 static irqreturn_t igb_intr_msi(int irq, void *); 132 static irqreturn_t igb_msix_other(int irq, void *); 133 static irqreturn_t igb_msix_ring(int irq, void *); 134 #ifdef CONFIG_IGB_DCA 135 static void igb_update_dca(struct igb_q_vector *); 136 static void igb_setup_dca(struct igb_adapter *); 137 #endif /* CONFIG_IGB_DCA */ 138 static int igb_poll(struct napi_struct *, int); 139 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 140 static int igb_clean_rx_irq(struct igb_q_vector *, int); 141 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 142 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 143 static void igb_reset_task(struct work_struct *); 144 static void igb_vlan_mode(struct net_device *netdev, 145 netdev_features_t features); 146 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 147 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 148 static void igb_restore_vlan(struct igb_adapter *); 149 static void igb_rar_set_index(struct igb_adapter *, u32); 150 static void igb_ping_all_vfs(struct igb_adapter *); 151 static void igb_msg_task(struct igb_adapter *); 152 static void igb_vmm_control(struct igb_adapter *); 153 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 154 static void igb_flush_mac_table(struct igb_adapter *); 155 static int igb_available_rars(struct igb_adapter *, u8); 156 static void igb_set_default_mac_filter(struct igb_adapter *); 157 static int igb_uc_sync(struct net_device *, const unsigned char *); 158 static int igb_uc_unsync(struct net_device *, const unsigned char *); 159 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 160 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 161 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 162 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 163 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 164 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 169 struct ifla_vf_info *ivi); 170 static void igb_check_vf_rate_limit(struct igb_adapter *); 171 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 172 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 173 174 #ifdef CONFIG_PCI_IOV 175 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 176 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 177 #endif 178 179 #ifdef CONFIG_IGB_DCA 180 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 181 static struct notifier_block dca_notifier = { 182 .notifier_call = igb_notify_dca, 183 .next = NULL, 184 .priority = 0 185 }; 186 #endif 187 #ifdef CONFIG_PCI_IOV 188 static unsigned int max_vfs; 189 module_param(max_vfs, uint, 0444); 190 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 191 #endif /* CONFIG_PCI_IOV */ 192 193 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 194 pci_channel_state_t); 195 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 196 static void igb_io_resume(struct pci_dev *); 197 198 static const struct pci_error_handlers igb_err_handler = { 199 .error_detected = igb_io_error_detected, 200 .slot_reset = igb_io_slot_reset, 201 .resume = igb_io_resume, 202 }; 203 204 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 205 206 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 207 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 208 MODULE_LICENSE("GPL v2"); 209 210 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 211 static int debug = -1; 212 module_param(debug, int, 0); 213 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 214 215 struct igb_reg_info { 216 u32 ofs; 217 char *name; 218 }; 219 220 static const struct igb_reg_info igb_reg_info_tbl[] = { 221 222 /* General Registers */ 223 {E1000_CTRL, "CTRL"}, 224 {E1000_STATUS, "STATUS"}, 225 {E1000_CTRL_EXT, "CTRL_EXT"}, 226 227 /* Interrupt Registers */ 228 {E1000_ICR, "ICR"}, 229 230 /* RX Registers */ 231 {E1000_RCTL, "RCTL"}, 232 {E1000_RDLEN(0), "RDLEN"}, 233 {E1000_RDH(0), "RDH"}, 234 {E1000_RDT(0), "RDT"}, 235 {E1000_RXDCTL(0), "RXDCTL"}, 236 {E1000_RDBAL(0), "RDBAL"}, 237 {E1000_RDBAH(0), "RDBAH"}, 238 239 /* TX Registers */ 240 {E1000_TCTL, "TCTL"}, 241 {E1000_TDBAL(0), "TDBAL"}, 242 {E1000_TDBAH(0), "TDBAH"}, 243 {E1000_TDLEN(0), "TDLEN"}, 244 {E1000_TDH(0), "TDH"}, 245 {E1000_TDT(0), "TDT"}, 246 {E1000_TXDCTL(0), "TXDCTL"}, 247 {E1000_TDFH, "TDFH"}, 248 {E1000_TDFT, "TDFT"}, 249 {E1000_TDFHS, "TDFHS"}, 250 {E1000_TDFPC, "TDFPC"}, 251 252 /* List Terminator */ 253 {} 254 }; 255 256 /* igb_regdump - register printout routine */ 257 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 258 { 259 int n = 0; 260 char rname[16]; 261 u32 regs[8]; 262 263 switch (reginfo->ofs) { 264 case E1000_RDLEN(0): 265 for (n = 0; n < 4; n++) 266 regs[n] = rd32(E1000_RDLEN(n)); 267 break; 268 case E1000_RDH(0): 269 for (n = 0; n < 4; n++) 270 regs[n] = rd32(E1000_RDH(n)); 271 break; 272 case E1000_RDT(0): 273 for (n = 0; n < 4; n++) 274 regs[n] = rd32(E1000_RDT(n)); 275 break; 276 case E1000_RXDCTL(0): 277 for (n = 0; n < 4; n++) 278 regs[n] = rd32(E1000_RXDCTL(n)); 279 break; 280 case E1000_RDBAL(0): 281 for (n = 0; n < 4; n++) 282 regs[n] = rd32(E1000_RDBAL(n)); 283 break; 284 case E1000_RDBAH(0): 285 for (n = 0; n < 4; n++) 286 regs[n] = rd32(E1000_RDBAH(n)); 287 break; 288 case E1000_TDBAL(0): 289 for (n = 0; n < 4; n++) 290 regs[n] = rd32(E1000_TDBAL(n)); 291 break; 292 case E1000_TDBAH(0): 293 for (n = 0; n < 4; n++) 294 regs[n] = rd32(E1000_TDBAH(n)); 295 break; 296 case E1000_TDLEN(0): 297 for (n = 0; n < 4; n++) 298 regs[n] = rd32(E1000_TDLEN(n)); 299 break; 300 case E1000_TDH(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_TDH(n)); 303 break; 304 case E1000_TDT(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_TDT(n)); 307 break; 308 case E1000_TXDCTL(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_TXDCTL(n)); 311 break; 312 default: 313 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 314 return; 315 } 316 317 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 318 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 319 regs[2], regs[3]); 320 } 321 322 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 323 static void igb_dump(struct igb_adapter *adapter) 324 { 325 struct net_device *netdev = adapter->netdev; 326 struct e1000_hw *hw = &adapter->hw; 327 struct igb_reg_info *reginfo; 328 struct igb_ring *tx_ring; 329 union e1000_adv_tx_desc *tx_desc; 330 struct my_u0 { __le64 a; __le64 b; } *u0; 331 struct igb_ring *rx_ring; 332 union e1000_adv_rx_desc *rx_desc; 333 u32 staterr; 334 u16 i, n; 335 336 if (!netif_msg_hw(adapter)) 337 return; 338 339 /* Print netdevice Info */ 340 if (netdev) { 341 dev_info(&adapter->pdev->dev, "Net device Info\n"); 342 pr_info("Device Name state trans_start\n"); 343 pr_info("%-15s %016lX %016lX\n", netdev->name, 344 netdev->state, dev_trans_start(netdev)); 345 } 346 347 /* Print Registers */ 348 dev_info(&adapter->pdev->dev, "Register Dump\n"); 349 pr_info(" Register Name Value\n"); 350 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 351 reginfo->name; reginfo++) { 352 igb_regdump(hw, reginfo); 353 } 354 355 /* Print TX Ring Summary */ 356 if (!netdev || !netif_running(netdev)) 357 goto exit; 358 359 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 360 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 361 for (n = 0; n < adapter->num_tx_queues; n++) { 362 struct igb_tx_buffer *buffer_info; 363 tx_ring = adapter->tx_ring[n]; 364 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 365 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 366 n, tx_ring->next_to_use, tx_ring->next_to_clean, 367 (u64)dma_unmap_addr(buffer_info, dma), 368 dma_unmap_len(buffer_info, len), 369 buffer_info->next_to_watch, 370 (u64)buffer_info->time_stamp); 371 } 372 373 /* Print TX Rings */ 374 if (!netif_msg_tx_done(adapter)) 375 goto rx_ring_summary; 376 377 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 378 379 /* Transmit Descriptor Formats 380 * 381 * Advanced Transmit Descriptor 382 * +--------------------------------------------------------------+ 383 * 0 | Buffer Address [63:0] | 384 * +--------------------------------------------------------------+ 385 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 386 * +--------------------------------------------------------------+ 387 * 63 46 45 40 39 38 36 35 32 31 24 15 0 388 */ 389 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 tx_ring = adapter->tx_ring[n]; 392 pr_info("------------------------------------\n"); 393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 394 pr_info("------------------------------------\n"); 395 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 396 397 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 398 const char *next_desc; 399 struct igb_tx_buffer *buffer_info; 400 tx_desc = IGB_TX_DESC(tx_ring, i); 401 buffer_info = &tx_ring->tx_buffer_info[i]; 402 u0 = (struct my_u0 *)tx_desc; 403 if (i == tx_ring->next_to_use && 404 i == tx_ring->next_to_clean) 405 next_desc = " NTC/U"; 406 else if (i == tx_ring->next_to_use) 407 next_desc = " NTU"; 408 else if (i == tx_ring->next_to_clean) 409 next_desc = " NTC"; 410 else 411 next_desc = ""; 412 413 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 414 i, le64_to_cpu(u0->a), 415 le64_to_cpu(u0->b), 416 (u64)dma_unmap_addr(buffer_info, dma), 417 dma_unmap_len(buffer_info, len), 418 buffer_info->next_to_watch, 419 (u64)buffer_info->time_stamp, 420 buffer_info->skb, next_desc); 421 422 if (netif_msg_pktdata(adapter) && buffer_info->skb) 423 print_hex_dump(KERN_INFO, "", 424 DUMP_PREFIX_ADDRESS, 425 16, 1, buffer_info->skb->data, 426 dma_unmap_len(buffer_info, len), 427 true); 428 } 429 } 430 431 /* Print RX Rings Summary */ 432 rx_ring_summary: 433 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 434 pr_info("Queue [NTU] [NTC]\n"); 435 for (n = 0; n < adapter->num_rx_queues; n++) { 436 rx_ring = adapter->rx_ring[n]; 437 pr_info(" %5d %5X %5X\n", 438 n, rx_ring->next_to_use, rx_ring->next_to_clean); 439 } 440 441 /* Print RX Rings */ 442 if (!netif_msg_rx_status(adapter)) 443 goto exit; 444 445 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 446 447 /* Advanced Receive Descriptor (Read) Format 448 * 63 1 0 449 * +-----------------------------------------------------+ 450 * 0 | Packet Buffer Address [63:1] |A0/NSE| 451 * +----------------------------------------------+------+ 452 * 8 | Header Buffer Address [63:1] | DD | 453 * +-----------------------------------------------------+ 454 * 455 * 456 * Advanced Receive Descriptor (Write-Back) Format 457 * 458 * 63 48 47 32 31 30 21 20 17 16 4 3 0 459 * +------------------------------------------------------+ 460 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 461 * | Checksum Ident | | | | Type | Type | 462 * +------------------------------------------------------+ 463 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 464 * +------------------------------------------------------+ 465 * 63 48 47 32 31 20 19 0 466 */ 467 468 for (n = 0; n < adapter->num_rx_queues; n++) { 469 rx_ring = adapter->rx_ring[n]; 470 pr_info("------------------------------------\n"); 471 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 472 pr_info("------------------------------------\n"); 473 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 474 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 475 476 for (i = 0; i < rx_ring->count; i++) { 477 const char *next_desc; 478 struct igb_rx_buffer *buffer_info; 479 buffer_info = &rx_ring->rx_buffer_info[i]; 480 rx_desc = IGB_RX_DESC(rx_ring, i); 481 u0 = (struct my_u0 *)rx_desc; 482 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 483 484 if (i == rx_ring->next_to_use) 485 next_desc = " NTU"; 486 else if (i == rx_ring->next_to_clean) 487 next_desc = " NTC"; 488 else 489 next_desc = ""; 490 491 if (staterr & E1000_RXD_STAT_DD) { 492 /* Descriptor Done */ 493 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 494 "RWB", i, 495 le64_to_cpu(u0->a), 496 le64_to_cpu(u0->b), 497 next_desc); 498 } else { 499 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 500 "R ", i, 501 le64_to_cpu(u0->a), 502 le64_to_cpu(u0->b), 503 (u64)buffer_info->dma, 504 next_desc); 505 506 if (netif_msg_pktdata(adapter) && 507 buffer_info->dma && buffer_info->page) { 508 print_hex_dump(KERN_INFO, "", 509 DUMP_PREFIX_ADDRESS, 510 16, 1, 511 page_address(buffer_info->page) + 512 buffer_info->page_offset, 513 igb_rx_bufsz(rx_ring), true); 514 } 515 } 516 } 517 } 518 519 exit: 520 return; 521 } 522 523 /** 524 * igb_get_i2c_data - Reads the I2C SDA data bit 525 * @data: opaque pointer to adapter struct 526 * 527 * Returns the I2C data bit value 528 **/ 529 static int igb_get_i2c_data(void *data) 530 { 531 struct igb_adapter *adapter = (struct igb_adapter *)data; 532 struct e1000_hw *hw = &adapter->hw; 533 s32 i2cctl = rd32(E1000_I2CPARAMS); 534 535 return !!(i2cctl & E1000_I2C_DATA_IN); 536 } 537 538 /** 539 * igb_set_i2c_data - Sets the I2C data bit 540 * @data: pointer to hardware structure 541 * @state: I2C data value (0 or 1) to set 542 * 543 * Sets the I2C data bit 544 **/ 545 static void igb_set_i2c_data(void *data, int state) 546 { 547 struct igb_adapter *adapter = (struct igb_adapter *)data; 548 struct e1000_hw *hw = &adapter->hw; 549 s32 i2cctl = rd32(E1000_I2CPARAMS); 550 551 if (state) { 552 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 553 } else { 554 i2cctl &= ~E1000_I2C_DATA_OE_N; 555 i2cctl &= ~E1000_I2C_DATA_OUT; 556 } 557 558 wr32(E1000_I2CPARAMS, i2cctl); 559 wrfl(); 560 } 561 562 /** 563 * igb_set_i2c_clk - Sets the I2C SCL clock 564 * @data: pointer to hardware structure 565 * @state: state to set clock 566 * 567 * Sets the I2C clock line to state 568 **/ 569 static void igb_set_i2c_clk(void *data, int state) 570 { 571 struct igb_adapter *adapter = (struct igb_adapter *)data; 572 struct e1000_hw *hw = &adapter->hw; 573 s32 i2cctl = rd32(E1000_I2CPARAMS); 574 575 if (state) { 576 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 577 } else { 578 i2cctl &= ~E1000_I2C_CLK_OUT; 579 i2cctl &= ~E1000_I2C_CLK_OE_N; 580 } 581 wr32(E1000_I2CPARAMS, i2cctl); 582 wrfl(); 583 } 584 585 /** 586 * igb_get_i2c_clk - Gets the I2C SCL clock state 587 * @data: pointer to hardware structure 588 * 589 * Gets the I2C clock state 590 **/ 591 static int igb_get_i2c_clk(void *data) 592 { 593 struct igb_adapter *adapter = (struct igb_adapter *)data; 594 struct e1000_hw *hw = &adapter->hw; 595 s32 i2cctl = rd32(E1000_I2CPARAMS); 596 597 return !!(i2cctl & E1000_I2C_CLK_IN); 598 } 599 600 static const struct i2c_algo_bit_data igb_i2c_algo = { 601 .setsda = igb_set_i2c_data, 602 .setscl = igb_set_i2c_clk, 603 .getsda = igb_get_i2c_data, 604 .getscl = igb_get_i2c_clk, 605 .udelay = 5, 606 .timeout = 20, 607 }; 608 609 /** 610 * igb_get_hw_dev - return device 611 * @hw: pointer to hardware structure 612 * 613 * used by hardware layer to print debugging information 614 **/ 615 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 616 { 617 struct igb_adapter *adapter = hw->back; 618 return adapter->netdev; 619 } 620 621 static struct pci_driver igb_driver; 622 623 /** 624 * igb_init_module - Driver Registration Routine 625 * 626 * igb_init_module is the first routine called when the driver is 627 * loaded. All it does is register with the PCI subsystem. 628 **/ 629 static int __init igb_init_module(void) 630 { 631 int ret; 632 633 pr_info("%s\n", igb_driver_string); 634 pr_info("%s\n", igb_copyright); 635 636 #ifdef CONFIG_IGB_DCA 637 dca_register_notify(&dca_notifier); 638 #endif 639 ret = pci_register_driver(&igb_driver); 640 return ret; 641 } 642 643 module_init(igb_init_module); 644 645 /** 646 * igb_exit_module - Driver Exit Cleanup Routine 647 * 648 * igb_exit_module is called just before the driver is removed 649 * from memory. 650 **/ 651 static void __exit igb_exit_module(void) 652 { 653 #ifdef CONFIG_IGB_DCA 654 dca_unregister_notify(&dca_notifier); 655 #endif 656 pci_unregister_driver(&igb_driver); 657 } 658 659 module_exit(igb_exit_module); 660 661 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 662 /** 663 * igb_cache_ring_register - Descriptor ring to register mapping 664 * @adapter: board private structure to initialize 665 * 666 * Once we know the feature-set enabled for the device, we'll cache 667 * the register offset the descriptor ring is assigned to. 668 **/ 669 static void igb_cache_ring_register(struct igb_adapter *adapter) 670 { 671 int i = 0, j = 0; 672 u32 rbase_offset = adapter->vfs_allocated_count; 673 674 switch (adapter->hw.mac.type) { 675 case e1000_82576: 676 /* The queues are allocated for virtualization such that VF 0 677 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 678 * In order to avoid collision we start at the first free queue 679 * and continue consuming queues in the same sequence 680 */ 681 if (adapter->vfs_allocated_count) { 682 for (; i < adapter->rss_queues; i++) 683 adapter->rx_ring[i]->reg_idx = rbase_offset + 684 Q_IDX_82576(i); 685 } 686 fallthrough; 687 case e1000_82575: 688 case e1000_82580: 689 case e1000_i350: 690 case e1000_i354: 691 case e1000_i210: 692 case e1000_i211: 693 default: 694 for (; i < adapter->num_rx_queues; i++) 695 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 696 for (; j < adapter->num_tx_queues; j++) 697 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 698 break; 699 } 700 } 701 702 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 703 { 704 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 705 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 706 u32 value = 0; 707 708 if (E1000_REMOVED(hw_addr)) 709 return ~value; 710 711 value = readl(&hw_addr[reg]); 712 713 /* reads should not return all F's */ 714 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 715 struct net_device *netdev = igb->netdev; 716 hw->hw_addr = NULL; 717 netdev_err(netdev, "PCIe link lost\n"); 718 WARN(pci_device_is_present(igb->pdev), 719 "igb: Failed to read reg 0x%x!\n", reg); 720 } 721 722 return value; 723 } 724 725 /** 726 * igb_write_ivar - configure ivar for given MSI-X vector 727 * @hw: pointer to the HW structure 728 * @msix_vector: vector number we are allocating to a given ring 729 * @index: row index of IVAR register to write within IVAR table 730 * @offset: column offset of in IVAR, should be multiple of 8 731 * 732 * This function is intended to handle the writing of the IVAR register 733 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 734 * each containing an cause allocation for an Rx and Tx ring, and a 735 * variable number of rows depending on the number of queues supported. 736 **/ 737 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 738 int index, int offset) 739 { 740 u32 ivar = array_rd32(E1000_IVAR0, index); 741 742 /* clear any bits that are currently set */ 743 ivar &= ~((u32)0xFF << offset); 744 745 /* write vector and valid bit */ 746 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 747 748 array_wr32(E1000_IVAR0, index, ivar); 749 } 750 751 #define IGB_N0_QUEUE -1 752 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 753 { 754 struct igb_adapter *adapter = q_vector->adapter; 755 struct e1000_hw *hw = &adapter->hw; 756 int rx_queue = IGB_N0_QUEUE; 757 int tx_queue = IGB_N0_QUEUE; 758 u32 msixbm = 0; 759 760 if (q_vector->rx.ring) 761 rx_queue = q_vector->rx.ring->reg_idx; 762 if (q_vector->tx.ring) 763 tx_queue = q_vector->tx.ring->reg_idx; 764 765 switch (hw->mac.type) { 766 case e1000_82575: 767 /* The 82575 assigns vectors using a bitmask, which matches the 768 * bitmask for the EICR/EIMS/EIMC registers. To assign one 769 * or more queues to a vector, we write the appropriate bits 770 * into the MSIXBM register for that vector. 771 */ 772 if (rx_queue > IGB_N0_QUEUE) 773 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 774 if (tx_queue > IGB_N0_QUEUE) 775 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 776 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 777 msixbm |= E1000_EIMS_OTHER; 778 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 779 q_vector->eims_value = msixbm; 780 break; 781 case e1000_82576: 782 /* 82576 uses a table that essentially consists of 2 columns 783 * with 8 rows. The ordering is column-major so we use the 784 * lower 3 bits as the row index, and the 4th bit as the 785 * column offset. 786 */ 787 if (rx_queue > IGB_N0_QUEUE) 788 igb_write_ivar(hw, msix_vector, 789 rx_queue & 0x7, 790 (rx_queue & 0x8) << 1); 791 if (tx_queue > IGB_N0_QUEUE) 792 igb_write_ivar(hw, msix_vector, 793 tx_queue & 0x7, 794 ((tx_queue & 0x8) << 1) + 8); 795 q_vector->eims_value = BIT(msix_vector); 796 break; 797 case e1000_82580: 798 case e1000_i350: 799 case e1000_i354: 800 case e1000_i210: 801 case e1000_i211: 802 /* On 82580 and newer adapters the scheme is similar to 82576 803 * however instead of ordering column-major we have things 804 * ordered row-major. So we traverse the table by using 805 * bit 0 as the column offset, and the remaining bits as the 806 * row index. 807 */ 808 if (rx_queue > IGB_N0_QUEUE) 809 igb_write_ivar(hw, msix_vector, 810 rx_queue >> 1, 811 (rx_queue & 0x1) << 4); 812 if (tx_queue > IGB_N0_QUEUE) 813 igb_write_ivar(hw, msix_vector, 814 tx_queue >> 1, 815 ((tx_queue & 0x1) << 4) + 8); 816 q_vector->eims_value = BIT(msix_vector); 817 break; 818 default: 819 BUG(); 820 break; 821 } 822 823 /* add q_vector eims value to global eims_enable_mask */ 824 adapter->eims_enable_mask |= q_vector->eims_value; 825 826 /* configure q_vector to set itr on first interrupt */ 827 q_vector->set_itr = 1; 828 } 829 830 /** 831 * igb_configure_msix - Configure MSI-X hardware 832 * @adapter: board private structure to initialize 833 * 834 * igb_configure_msix sets up the hardware to properly 835 * generate MSI-X interrupts. 836 **/ 837 static void igb_configure_msix(struct igb_adapter *adapter) 838 { 839 u32 tmp; 840 int i, vector = 0; 841 struct e1000_hw *hw = &adapter->hw; 842 843 adapter->eims_enable_mask = 0; 844 845 /* set vector for other causes, i.e. link changes */ 846 switch (hw->mac.type) { 847 case e1000_82575: 848 tmp = rd32(E1000_CTRL_EXT); 849 /* enable MSI-X PBA support*/ 850 tmp |= E1000_CTRL_EXT_PBA_CLR; 851 852 /* Auto-Mask interrupts upon ICR read. */ 853 tmp |= E1000_CTRL_EXT_EIAME; 854 tmp |= E1000_CTRL_EXT_IRCA; 855 856 wr32(E1000_CTRL_EXT, tmp); 857 858 /* enable msix_other interrupt */ 859 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 860 adapter->eims_other = E1000_EIMS_OTHER; 861 862 break; 863 864 case e1000_82576: 865 case e1000_82580: 866 case e1000_i350: 867 case e1000_i354: 868 case e1000_i210: 869 case e1000_i211: 870 /* Turn on MSI-X capability first, or our settings 871 * won't stick. And it will take days to debug. 872 */ 873 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 874 E1000_GPIE_PBA | E1000_GPIE_EIAME | 875 E1000_GPIE_NSICR); 876 877 /* enable msix_other interrupt */ 878 adapter->eims_other = BIT(vector); 879 tmp = (vector++ | E1000_IVAR_VALID) << 8; 880 881 wr32(E1000_IVAR_MISC, tmp); 882 break; 883 default: 884 /* do nothing, since nothing else supports MSI-X */ 885 break; 886 } /* switch (hw->mac.type) */ 887 888 adapter->eims_enable_mask |= adapter->eims_other; 889 890 for (i = 0; i < adapter->num_q_vectors; i++) 891 igb_assign_vector(adapter->q_vector[i], vector++); 892 893 wrfl(); 894 } 895 896 /** 897 * igb_request_msix - Initialize MSI-X interrupts 898 * @adapter: board private structure to initialize 899 * 900 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 901 * kernel. 902 **/ 903 static int igb_request_msix(struct igb_adapter *adapter) 904 { 905 unsigned int num_q_vectors = adapter->num_q_vectors; 906 struct net_device *netdev = adapter->netdev; 907 int i, err = 0, vector = 0, free_vector = 0; 908 909 err = request_irq(adapter->msix_entries[vector].vector, 910 igb_msix_other, 0, netdev->name, adapter); 911 if (err) 912 goto err_out; 913 914 if (num_q_vectors > MAX_Q_VECTORS) { 915 num_q_vectors = MAX_Q_VECTORS; 916 dev_warn(&adapter->pdev->dev, 917 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 918 adapter->num_q_vectors, MAX_Q_VECTORS); 919 } 920 for (i = 0; i < num_q_vectors; i++) { 921 struct igb_q_vector *q_vector = adapter->q_vector[i]; 922 923 vector++; 924 925 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 926 927 if (q_vector->rx.ring && q_vector->tx.ring) 928 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 929 q_vector->rx.ring->queue_index); 930 else if (q_vector->tx.ring) 931 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 932 q_vector->tx.ring->queue_index); 933 else if (q_vector->rx.ring) 934 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else 937 sprintf(q_vector->name, "%s-unused", netdev->name); 938 939 err = request_irq(adapter->msix_entries[vector].vector, 940 igb_msix_ring, 0, q_vector->name, 941 q_vector); 942 if (err) 943 goto err_free; 944 } 945 946 igb_configure_msix(adapter); 947 return 0; 948 949 err_free: 950 /* free already assigned IRQs */ 951 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 952 953 vector--; 954 for (i = 0; i < vector; i++) { 955 free_irq(adapter->msix_entries[free_vector++].vector, 956 adapter->q_vector[i]); 957 } 958 err_out: 959 return err; 960 } 961 962 /** 963 * igb_free_q_vector - Free memory allocated for specific interrupt vector 964 * @adapter: board private structure to initialize 965 * @v_idx: Index of vector to be freed 966 * 967 * This function frees the memory allocated to the q_vector. 968 **/ 969 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 970 { 971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 972 973 adapter->q_vector[v_idx] = NULL; 974 975 /* igb_get_stats64() might access the rings on this vector, 976 * we must wait a grace period before freeing it. 977 */ 978 if (q_vector) 979 kfree_rcu(q_vector, rcu); 980 } 981 982 /** 983 * igb_reset_q_vector - Reset config for interrupt vector 984 * @adapter: board private structure to initialize 985 * @v_idx: Index of vector to be reset 986 * 987 * If NAPI is enabled it will delete any references to the 988 * NAPI struct. This is preparation for igb_free_q_vector. 989 **/ 990 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 991 { 992 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 993 994 /* Coming from igb_set_interrupt_capability, the vectors are not yet 995 * allocated. So, q_vector is NULL so we should stop here. 996 */ 997 if (!q_vector) 998 return; 999 1000 if (q_vector->tx.ring) 1001 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1002 1003 if (q_vector->rx.ring) 1004 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1005 1006 netif_napi_del(&q_vector->napi); 1007 1008 } 1009 1010 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1011 { 1012 int v_idx = adapter->num_q_vectors; 1013 1014 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1015 pci_disable_msix(adapter->pdev); 1016 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1017 pci_disable_msi(adapter->pdev); 1018 1019 while (v_idx--) 1020 igb_reset_q_vector(adapter, v_idx); 1021 } 1022 1023 /** 1024 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1025 * @adapter: board private structure to initialize 1026 * 1027 * This function frees the memory allocated to the q_vectors. In addition if 1028 * NAPI is enabled it will delete any references to the NAPI struct prior 1029 * to freeing the q_vector. 1030 **/ 1031 static void igb_free_q_vectors(struct igb_adapter *adapter) 1032 { 1033 int v_idx = adapter->num_q_vectors; 1034 1035 adapter->num_tx_queues = 0; 1036 adapter->num_rx_queues = 0; 1037 adapter->num_q_vectors = 0; 1038 1039 while (v_idx--) { 1040 igb_reset_q_vector(adapter, v_idx); 1041 igb_free_q_vector(adapter, v_idx); 1042 } 1043 } 1044 1045 /** 1046 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1050 * MSI-X interrupts allocated. 1051 */ 1052 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1053 { 1054 igb_free_q_vectors(adapter); 1055 igb_reset_interrupt_capability(adapter); 1056 } 1057 1058 /** 1059 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1060 * @adapter: board private structure to initialize 1061 * @msix: boolean value of MSIX capability 1062 * 1063 * Attempt to configure interrupts using the best available 1064 * capabilities of the hardware and kernel. 1065 **/ 1066 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1067 { 1068 int err; 1069 int numvecs, i; 1070 1071 if (!msix) 1072 goto msi_only; 1073 adapter->flags |= IGB_FLAG_HAS_MSIX; 1074 1075 /* Number of supported queues. */ 1076 adapter->num_rx_queues = adapter->rss_queues; 1077 if (adapter->vfs_allocated_count) 1078 adapter->num_tx_queues = 1; 1079 else 1080 adapter->num_tx_queues = adapter->rss_queues; 1081 1082 /* start with one vector for every Rx queue */ 1083 numvecs = adapter->num_rx_queues; 1084 1085 /* if Tx handler is separate add 1 for every Tx queue */ 1086 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1087 numvecs += adapter->num_tx_queues; 1088 1089 /* store the number of vectors reserved for queues */ 1090 adapter->num_q_vectors = numvecs; 1091 1092 /* add 1 vector for link status interrupts */ 1093 numvecs++; 1094 for (i = 0; i < numvecs; i++) 1095 adapter->msix_entries[i].entry = i; 1096 1097 err = pci_enable_msix_range(adapter->pdev, 1098 adapter->msix_entries, 1099 numvecs, 1100 numvecs); 1101 if (err > 0) 1102 return; 1103 1104 igb_reset_interrupt_capability(adapter); 1105 1106 /* If we can't do MSI-X, try MSI */ 1107 msi_only: 1108 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1109 #ifdef CONFIG_PCI_IOV 1110 /* disable SR-IOV for non MSI-X configurations */ 1111 if (adapter->vf_data) { 1112 struct e1000_hw *hw = &adapter->hw; 1113 /* disable iov and allow time for transactions to clear */ 1114 pci_disable_sriov(adapter->pdev); 1115 msleep(500); 1116 1117 kfree(adapter->vf_mac_list); 1118 adapter->vf_mac_list = NULL; 1119 kfree(adapter->vf_data); 1120 adapter->vf_data = NULL; 1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1122 wrfl(); 1123 msleep(100); 1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1125 } 1126 #endif 1127 adapter->vfs_allocated_count = 0; 1128 adapter->rss_queues = 1; 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1130 adapter->num_rx_queues = 1; 1131 adapter->num_tx_queues = 1; 1132 adapter->num_q_vectors = 1; 1133 if (!pci_enable_msi(adapter->pdev)) 1134 adapter->flags |= IGB_FLAG_HAS_MSI; 1135 } 1136 1137 static void igb_add_ring(struct igb_ring *ring, 1138 struct igb_ring_container *head) 1139 { 1140 head->ring = ring; 1141 head->count++; 1142 } 1143 1144 /** 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1146 * @adapter: board private structure to initialize 1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1148 * @v_idx: index of vector in adapter struct 1149 * @txr_count: total number of Tx rings to allocate 1150 * @txr_idx: index of first Tx ring to allocate 1151 * @rxr_count: total number of Rx rings to allocate 1152 * @rxr_idx: index of first Rx ring to allocate 1153 * 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1155 **/ 1156 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1157 int v_count, int v_idx, 1158 int txr_count, int txr_idx, 1159 int rxr_count, int rxr_idx) 1160 { 1161 struct igb_q_vector *q_vector; 1162 struct igb_ring *ring; 1163 int ring_count; 1164 size_t size; 1165 1166 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1167 if (txr_count > 1 || rxr_count > 1) 1168 return -ENOMEM; 1169 1170 ring_count = txr_count + rxr_count; 1171 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1172 1173 /* allocate q_vector and rings */ 1174 q_vector = adapter->q_vector[v_idx]; 1175 if (!q_vector) { 1176 q_vector = kzalloc(size, GFP_KERNEL); 1177 } else if (size > ksize(q_vector)) { 1178 struct igb_q_vector *new_q_vector; 1179 1180 new_q_vector = kzalloc(size, GFP_KERNEL); 1181 if (new_q_vector) 1182 kfree_rcu(q_vector, rcu); 1183 q_vector = new_q_vector; 1184 } else { 1185 memset(q_vector, 0, size); 1186 } 1187 if (!q_vector) 1188 return -ENOMEM; 1189 1190 /* initialize NAPI */ 1191 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1192 1193 /* tie q_vector and adapter together */ 1194 adapter->q_vector[v_idx] = q_vector; 1195 q_vector->adapter = adapter; 1196 1197 /* initialize work limits */ 1198 q_vector->tx.work_limit = adapter->tx_work_limit; 1199 1200 /* initialize ITR configuration */ 1201 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1202 q_vector->itr_val = IGB_START_ITR; 1203 1204 /* initialize pointer to rings */ 1205 ring = q_vector->ring; 1206 1207 /* intialize ITR */ 1208 if (rxr_count) { 1209 /* rx or rx/tx vector */ 1210 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1211 q_vector->itr_val = adapter->rx_itr_setting; 1212 } else { 1213 /* tx only vector */ 1214 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1215 q_vector->itr_val = adapter->tx_itr_setting; 1216 } 1217 1218 if (txr_count) { 1219 /* assign generic ring traits */ 1220 ring->dev = &adapter->pdev->dev; 1221 ring->netdev = adapter->netdev; 1222 1223 /* configure backlink on ring */ 1224 ring->q_vector = q_vector; 1225 1226 /* update q_vector Tx values */ 1227 igb_add_ring(ring, &q_vector->tx); 1228 1229 /* For 82575, context index must be unique per ring. */ 1230 if (adapter->hw.mac.type == e1000_82575) 1231 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1232 1233 /* apply Tx specific ring traits */ 1234 ring->count = adapter->tx_ring_count; 1235 ring->queue_index = txr_idx; 1236 1237 ring->cbs_enable = false; 1238 ring->idleslope = 0; 1239 ring->sendslope = 0; 1240 ring->hicredit = 0; 1241 ring->locredit = 0; 1242 1243 u64_stats_init(&ring->tx_syncp); 1244 u64_stats_init(&ring->tx_syncp2); 1245 1246 /* assign ring to adapter */ 1247 adapter->tx_ring[txr_idx] = ring; 1248 1249 /* push pointer to next ring */ 1250 ring++; 1251 } 1252 1253 if (rxr_count) { 1254 /* assign generic ring traits */ 1255 ring->dev = &adapter->pdev->dev; 1256 ring->netdev = adapter->netdev; 1257 1258 /* configure backlink on ring */ 1259 ring->q_vector = q_vector; 1260 1261 /* update q_vector Rx values */ 1262 igb_add_ring(ring, &q_vector->rx); 1263 1264 /* set flag indicating ring supports SCTP checksum offload */ 1265 if (adapter->hw.mac.type >= e1000_82576) 1266 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1267 1268 /* On i350, i354, i210, and i211, loopback VLAN packets 1269 * have the tag byte-swapped. 1270 */ 1271 if (adapter->hw.mac.type >= e1000_i350) 1272 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1273 1274 /* apply Rx specific ring traits */ 1275 ring->count = adapter->rx_ring_count; 1276 ring->queue_index = rxr_idx; 1277 1278 u64_stats_init(&ring->rx_syncp); 1279 1280 /* assign ring to adapter */ 1281 adapter->rx_ring[rxr_idx] = ring; 1282 } 1283 1284 return 0; 1285 } 1286 1287 1288 /** 1289 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1290 * @adapter: board private structure to initialize 1291 * 1292 * We allocate one q_vector per queue interrupt. If allocation fails we 1293 * return -ENOMEM. 1294 **/ 1295 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1296 { 1297 int q_vectors = adapter->num_q_vectors; 1298 int rxr_remaining = adapter->num_rx_queues; 1299 int txr_remaining = adapter->num_tx_queues; 1300 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1301 int err; 1302 1303 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1304 for (; rxr_remaining; v_idx++) { 1305 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1306 0, 0, 1, rxr_idx); 1307 1308 if (err) 1309 goto err_out; 1310 1311 /* update counts and index */ 1312 rxr_remaining--; 1313 rxr_idx++; 1314 } 1315 } 1316 1317 for (; v_idx < q_vectors; v_idx++) { 1318 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1319 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1320 1321 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1322 tqpv, txr_idx, rqpv, rxr_idx); 1323 1324 if (err) 1325 goto err_out; 1326 1327 /* update counts and index */ 1328 rxr_remaining -= rqpv; 1329 txr_remaining -= tqpv; 1330 rxr_idx++; 1331 txr_idx++; 1332 } 1333 1334 return 0; 1335 1336 err_out: 1337 adapter->num_tx_queues = 0; 1338 adapter->num_rx_queues = 0; 1339 adapter->num_q_vectors = 0; 1340 1341 while (v_idx--) 1342 igb_free_q_vector(adapter, v_idx); 1343 1344 return -ENOMEM; 1345 } 1346 1347 /** 1348 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1349 * @adapter: board private structure to initialize 1350 * @msix: boolean value of MSIX capability 1351 * 1352 * This function initializes the interrupts and allocates all of the queues. 1353 **/ 1354 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1355 { 1356 struct pci_dev *pdev = adapter->pdev; 1357 int err; 1358 1359 igb_set_interrupt_capability(adapter, msix); 1360 1361 err = igb_alloc_q_vectors(adapter); 1362 if (err) { 1363 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1364 goto err_alloc_q_vectors; 1365 } 1366 1367 igb_cache_ring_register(adapter); 1368 1369 return 0; 1370 1371 err_alloc_q_vectors: 1372 igb_reset_interrupt_capability(adapter); 1373 return err; 1374 } 1375 1376 /** 1377 * igb_request_irq - initialize interrupts 1378 * @adapter: board private structure to initialize 1379 * 1380 * Attempts to configure interrupts using the best available 1381 * capabilities of the hardware and kernel. 1382 **/ 1383 static int igb_request_irq(struct igb_adapter *adapter) 1384 { 1385 struct net_device *netdev = adapter->netdev; 1386 struct pci_dev *pdev = adapter->pdev; 1387 int err = 0; 1388 1389 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1390 err = igb_request_msix(adapter); 1391 if (!err) 1392 goto request_done; 1393 /* fall back to MSI */ 1394 igb_free_all_tx_resources(adapter); 1395 igb_free_all_rx_resources(adapter); 1396 1397 igb_clear_interrupt_scheme(adapter); 1398 err = igb_init_interrupt_scheme(adapter, false); 1399 if (err) 1400 goto request_done; 1401 1402 igb_setup_all_tx_resources(adapter); 1403 igb_setup_all_rx_resources(adapter); 1404 igb_configure(adapter); 1405 } 1406 1407 igb_assign_vector(adapter->q_vector[0], 0); 1408 1409 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1410 err = request_irq(pdev->irq, igb_intr_msi, 0, 1411 netdev->name, adapter); 1412 if (!err) 1413 goto request_done; 1414 1415 /* fall back to legacy interrupts */ 1416 igb_reset_interrupt_capability(adapter); 1417 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1418 } 1419 1420 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1421 netdev->name, adapter); 1422 1423 if (err) 1424 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1425 err); 1426 1427 request_done: 1428 return err; 1429 } 1430 1431 static void igb_free_irq(struct igb_adapter *adapter) 1432 { 1433 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1434 int vector = 0, i; 1435 1436 free_irq(adapter->msix_entries[vector++].vector, adapter); 1437 1438 for (i = 0; i < adapter->num_q_vectors; i++) 1439 free_irq(adapter->msix_entries[vector++].vector, 1440 adapter->q_vector[i]); 1441 } else { 1442 free_irq(adapter->pdev->irq, adapter); 1443 } 1444 } 1445 1446 /** 1447 * igb_irq_disable - Mask off interrupt generation on the NIC 1448 * @adapter: board private structure 1449 **/ 1450 static void igb_irq_disable(struct igb_adapter *adapter) 1451 { 1452 struct e1000_hw *hw = &adapter->hw; 1453 1454 /* we need to be careful when disabling interrupts. The VFs are also 1455 * mapped into these registers and so clearing the bits can cause 1456 * issues on the VF drivers so we only need to clear what we set 1457 */ 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1459 u32 regval = rd32(E1000_EIAM); 1460 1461 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1462 wr32(E1000_EIMC, adapter->eims_enable_mask); 1463 regval = rd32(E1000_EIAC); 1464 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1465 } 1466 1467 wr32(E1000_IAM, 0); 1468 wr32(E1000_IMC, ~0); 1469 wrfl(); 1470 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1471 int i; 1472 1473 for (i = 0; i < adapter->num_q_vectors; i++) 1474 synchronize_irq(adapter->msix_entries[i].vector); 1475 } else { 1476 synchronize_irq(adapter->pdev->irq); 1477 } 1478 } 1479 1480 /** 1481 * igb_irq_enable - Enable default interrupt generation settings 1482 * @adapter: board private structure 1483 **/ 1484 static void igb_irq_enable(struct igb_adapter *adapter) 1485 { 1486 struct e1000_hw *hw = &adapter->hw; 1487 1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1489 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1490 u32 regval = rd32(E1000_EIAC); 1491 1492 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1493 regval = rd32(E1000_EIAM); 1494 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1495 wr32(E1000_EIMS, adapter->eims_enable_mask); 1496 if (adapter->vfs_allocated_count) { 1497 wr32(E1000_MBVFIMR, 0xFF); 1498 ims |= E1000_IMS_VMMB; 1499 } 1500 wr32(E1000_IMS, ims); 1501 } else { 1502 wr32(E1000_IMS, IMS_ENABLE_MASK | 1503 E1000_IMS_DRSTA); 1504 wr32(E1000_IAM, IMS_ENABLE_MASK | 1505 E1000_IMS_DRSTA); 1506 } 1507 } 1508 1509 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1510 { 1511 struct e1000_hw *hw = &adapter->hw; 1512 u16 pf_id = adapter->vfs_allocated_count; 1513 u16 vid = adapter->hw.mng_cookie.vlan_id; 1514 u16 old_vid = adapter->mng_vlan_id; 1515 1516 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1517 /* add VID to filter table */ 1518 igb_vfta_set(hw, vid, pf_id, true, true); 1519 adapter->mng_vlan_id = vid; 1520 } else { 1521 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1522 } 1523 1524 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1525 (vid != old_vid) && 1526 !test_bit(old_vid, adapter->active_vlans)) { 1527 /* remove VID from filter table */ 1528 igb_vfta_set(hw, vid, pf_id, false, true); 1529 } 1530 } 1531 1532 /** 1533 * igb_release_hw_control - release control of the h/w to f/w 1534 * @adapter: address of board private structure 1535 * 1536 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1537 * For ASF and Pass Through versions of f/w this means that the 1538 * driver is no longer loaded. 1539 **/ 1540 static void igb_release_hw_control(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u32 ctrl_ext; 1544 1545 /* Let firmware take over control of h/w */ 1546 ctrl_ext = rd32(E1000_CTRL_EXT); 1547 wr32(E1000_CTRL_EXT, 1548 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1549 } 1550 1551 /** 1552 * igb_get_hw_control - get control of the h/w from f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that 1557 * the driver is loaded. 1558 **/ 1559 static void igb_get_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware know the driver has taken over */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1571 { 1572 struct net_device *netdev = adapter->netdev; 1573 struct e1000_hw *hw = &adapter->hw; 1574 1575 WARN_ON(hw->mac.type != e1000_i210); 1576 1577 if (enable) 1578 adapter->flags |= IGB_FLAG_FQTSS; 1579 else 1580 adapter->flags &= ~IGB_FLAG_FQTSS; 1581 1582 if (netif_running(netdev)) 1583 schedule_work(&adapter->reset_task); 1584 } 1585 1586 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1587 { 1588 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1589 } 1590 1591 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1592 enum tx_queue_prio prio) 1593 { 1594 u32 val; 1595 1596 WARN_ON(hw->mac.type != e1000_i210); 1597 WARN_ON(queue < 0 || queue > 4); 1598 1599 val = rd32(E1000_I210_TXDCTL(queue)); 1600 1601 if (prio == TX_QUEUE_PRIO_HIGH) 1602 val |= E1000_TXDCTL_PRIORITY; 1603 else 1604 val &= ~E1000_TXDCTL_PRIORITY; 1605 1606 wr32(E1000_I210_TXDCTL(queue), val); 1607 } 1608 1609 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1610 { 1611 u32 val; 1612 1613 WARN_ON(hw->mac.type != e1000_i210); 1614 WARN_ON(queue < 0 || queue > 1); 1615 1616 val = rd32(E1000_I210_TQAVCC(queue)); 1617 1618 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1619 val |= E1000_TQAVCC_QUEUEMODE; 1620 else 1621 val &= ~E1000_TQAVCC_QUEUEMODE; 1622 1623 wr32(E1000_I210_TQAVCC(queue), val); 1624 } 1625 1626 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1627 { 1628 int i; 1629 1630 for (i = 0; i < adapter->num_tx_queues; i++) { 1631 if (adapter->tx_ring[i]->cbs_enable) 1632 return true; 1633 } 1634 1635 return false; 1636 } 1637 1638 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1639 { 1640 int i; 1641 1642 for (i = 0; i < adapter->num_tx_queues; i++) { 1643 if (adapter->tx_ring[i]->launchtime_enable) 1644 return true; 1645 } 1646 1647 return false; 1648 } 1649 1650 /** 1651 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1652 * @adapter: pointer to adapter struct 1653 * @queue: queue number 1654 * 1655 * Configure CBS and Launchtime for a given hardware queue. 1656 * Parameters are retrieved from the correct Tx ring, so 1657 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1658 * for setting those correctly prior to this function being called. 1659 **/ 1660 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1661 { 1662 struct net_device *netdev = adapter->netdev; 1663 struct e1000_hw *hw = &adapter->hw; 1664 struct igb_ring *ring; 1665 u32 tqavcc, tqavctrl; 1666 u16 value; 1667 1668 WARN_ON(hw->mac.type != e1000_i210); 1669 WARN_ON(queue < 0 || queue > 1); 1670 ring = adapter->tx_ring[queue]; 1671 1672 /* If any of the Qav features is enabled, configure queues as SR and 1673 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1674 * as SP. 1675 */ 1676 if (ring->cbs_enable || ring->launchtime_enable) { 1677 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1678 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1679 } else { 1680 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1681 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1682 } 1683 1684 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1685 if (ring->cbs_enable || queue == 0) { 1686 /* i210 does not allow the queue 0 to be in the Strict 1687 * Priority mode while the Qav mode is enabled, so, 1688 * instead of disabling strict priority mode, we give 1689 * queue 0 the maximum of credits possible. 1690 * 1691 * See section 8.12.19 of the i210 datasheet, "Note: 1692 * Queue0 QueueMode must be set to 1b when 1693 * TransmitMode is set to Qav." 1694 */ 1695 if (queue == 0 && !ring->cbs_enable) { 1696 /* max "linkspeed" idleslope in kbps */ 1697 ring->idleslope = 1000000; 1698 ring->hicredit = ETH_FRAME_LEN; 1699 } 1700 1701 /* Always set data transfer arbitration to credit-based 1702 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1703 * the queues. 1704 */ 1705 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1706 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1707 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1708 1709 /* According to i210 datasheet section 7.2.7.7, we should set 1710 * the 'idleSlope' field from TQAVCC register following the 1711 * equation: 1712 * 1713 * For 100 Mbps link speed: 1714 * 1715 * value = BW * 0x7735 * 0.2 (E1) 1716 * 1717 * For 1000Mbps link speed: 1718 * 1719 * value = BW * 0x7735 * 2 (E2) 1720 * 1721 * E1 and E2 can be merged into one equation as shown below. 1722 * Note that 'link-speed' is in Mbps. 1723 * 1724 * value = BW * 0x7735 * 2 * link-speed 1725 * -------------- (E3) 1726 * 1000 1727 * 1728 * 'BW' is the percentage bandwidth out of full link speed 1729 * which can be found with the following equation. Note that 1730 * idleSlope here is the parameter from this function which 1731 * is in kbps. 1732 * 1733 * BW = idleSlope 1734 * ----------------- (E4) 1735 * link-speed * 1000 1736 * 1737 * That said, we can come up with a generic equation to 1738 * calculate the value we should set it TQAVCC register by 1739 * replacing 'BW' in E3 by E4. The resulting equation is: 1740 * 1741 * value = idleSlope * 0x7735 * 2 * link-speed 1742 * ----------------- -------------- (E5) 1743 * link-speed * 1000 1000 1744 * 1745 * 'link-speed' is present in both sides of the fraction so 1746 * it is canceled out. The final equation is the following: 1747 * 1748 * value = idleSlope * 61034 1749 * ----------------- (E6) 1750 * 1000000 1751 * 1752 * NOTE: For i210, given the above, we can see that idleslope 1753 * is represented in 16.38431 kbps units by the value at 1754 * the TQAVCC register (1Gbps / 61034), which reduces 1755 * the granularity for idleslope increments. 1756 * For instance, if you want to configure a 2576kbps 1757 * idleslope, the value to be written on the register 1758 * would have to be 157.23. If rounded down, you end 1759 * up with less bandwidth available than originally 1760 * required (~2572 kbps). If rounded up, you end up 1761 * with a higher bandwidth (~2589 kbps). Below the 1762 * approach we take is to always round up the 1763 * calculated value, so the resulting bandwidth might 1764 * be slightly higher for some configurations. 1765 */ 1766 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1767 1768 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1769 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1770 tqavcc |= value; 1771 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1772 1773 wr32(E1000_I210_TQAVHC(queue), 1774 0x80000000 + ring->hicredit * 0x7735); 1775 } else { 1776 1777 /* Set idleSlope to zero. */ 1778 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1779 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1780 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1781 1782 /* Set hiCredit to zero. */ 1783 wr32(E1000_I210_TQAVHC(queue), 0); 1784 1785 /* If CBS is not enabled for any queues anymore, then return to 1786 * the default state of Data Transmission Arbitration on 1787 * TQAVCTRL. 1788 */ 1789 if (!is_any_cbs_enabled(adapter)) { 1790 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1791 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1792 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1793 } 1794 } 1795 1796 /* If LaunchTime is enabled, set DataTranTIM. */ 1797 if (ring->launchtime_enable) { 1798 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1799 * for any of the SR queues, and configure fetchtime delta. 1800 * XXX NOTE: 1801 * - LaunchTime will be enabled for all SR queues. 1802 * - A fixed offset can be added relative to the launch 1803 * time of all packets if configured at reg LAUNCH_OS0. 1804 * We are keeping it as 0 for now (default value). 1805 */ 1806 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1807 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1808 E1000_TQAVCTRL_FETCHTIME_DELTA; 1809 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1810 } else { 1811 /* If Launchtime is not enabled for any SR queues anymore, 1812 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1813 * effectively disabling Launchtime. 1814 */ 1815 if (!is_any_txtime_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1818 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1824 * CBS are not configurable by software so we don't do any 'controller 1825 * configuration' in respect to these parameters. 1826 */ 1827 1828 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1829 ring->cbs_enable ? "enabled" : "disabled", 1830 ring->launchtime_enable ? "enabled" : "disabled", 1831 queue, 1832 ring->idleslope, ring->sendslope, 1833 ring->hicredit, ring->locredit); 1834 } 1835 1836 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1837 bool enable) 1838 { 1839 struct igb_ring *ring; 1840 1841 if (queue < 0 || queue > adapter->num_tx_queues) 1842 return -EINVAL; 1843 1844 ring = adapter->tx_ring[queue]; 1845 ring->launchtime_enable = enable; 1846 1847 return 0; 1848 } 1849 1850 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1851 bool enable, int idleslope, int sendslope, 1852 int hicredit, int locredit) 1853 { 1854 struct igb_ring *ring; 1855 1856 if (queue < 0 || queue > adapter->num_tx_queues) 1857 return -EINVAL; 1858 1859 ring = adapter->tx_ring[queue]; 1860 1861 ring->cbs_enable = enable; 1862 ring->idleslope = idleslope; 1863 ring->sendslope = sendslope; 1864 ring->hicredit = hicredit; 1865 ring->locredit = locredit; 1866 1867 return 0; 1868 } 1869 1870 /** 1871 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1872 * @adapter: pointer to adapter struct 1873 * 1874 * Configure TQAVCTRL register switching the controller's Tx mode 1875 * if FQTSS mode is enabled or disabled. Additionally, will issue 1876 * a call to igb_config_tx_modes() per queue so any previously saved 1877 * Tx parameters are applied. 1878 **/ 1879 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1880 { 1881 struct net_device *netdev = adapter->netdev; 1882 struct e1000_hw *hw = &adapter->hw; 1883 u32 val; 1884 1885 /* Only i210 controller supports changing the transmission mode. */ 1886 if (hw->mac.type != e1000_i210) 1887 return; 1888 1889 if (is_fqtss_enabled(adapter)) { 1890 int i, max_queue; 1891 1892 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1893 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1894 * so SP queues wait for SR ones. 1895 */ 1896 val = rd32(E1000_I210_TQAVCTRL); 1897 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1898 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1899 wr32(E1000_I210_TQAVCTRL, val); 1900 1901 /* Configure Tx and Rx packet buffers sizes as described in 1902 * i210 datasheet section 7.2.7.7. 1903 */ 1904 val = rd32(E1000_TXPBS); 1905 val &= ~I210_TXPBSIZE_MASK; 1906 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1907 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1908 wr32(E1000_TXPBS, val); 1909 1910 val = rd32(E1000_RXPBS); 1911 val &= ~I210_RXPBSIZE_MASK; 1912 val |= I210_RXPBSIZE_PB_30KB; 1913 wr32(E1000_RXPBS, val); 1914 1915 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1916 * register should not exceed the buffer size programmed in 1917 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1918 * so according to the datasheet we should set MAX_TPKT_SIZE to 1919 * 4kB / 64. 1920 * 1921 * However, when we do so, no frame from queue 2 and 3 are 1922 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1923 * or _equal_ to the buffer size programmed in TXPBS. For this 1924 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1925 */ 1926 val = (4096 - 1) / 64; 1927 wr32(E1000_I210_DTXMXPKTSZ, val); 1928 1929 /* Since FQTSS mode is enabled, apply any CBS configuration 1930 * previously set. If no previous CBS configuration has been 1931 * done, then the initial configuration is applied, which means 1932 * CBS is disabled. 1933 */ 1934 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1935 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1936 1937 for (i = 0; i < max_queue; i++) { 1938 igb_config_tx_modes(adapter, i); 1939 } 1940 } else { 1941 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1942 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1943 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1944 1945 val = rd32(E1000_I210_TQAVCTRL); 1946 /* According to Section 8.12.21, the other flags we've set when 1947 * enabling FQTSS are not relevant when disabling FQTSS so we 1948 * don't set they here. 1949 */ 1950 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1951 wr32(E1000_I210_TQAVCTRL, val); 1952 } 1953 1954 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1955 "enabled" : "disabled"); 1956 } 1957 1958 /** 1959 * igb_configure - configure the hardware for RX and TX 1960 * @adapter: private board structure 1961 **/ 1962 static void igb_configure(struct igb_adapter *adapter) 1963 { 1964 struct net_device *netdev = adapter->netdev; 1965 int i; 1966 1967 igb_get_hw_control(adapter); 1968 igb_set_rx_mode(netdev); 1969 igb_setup_tx_mode(adapter); 1970 1971 igb_restore_vlan(adapter); 1972 1973 igb_setup_tctl(adapter); 1974 igb_setup_mrqc(adapter); 1975 igb_setup_rctl(adapter); 1976 1977 igb_nfc_filter_restore(adapter); 1978 igb_configure_tx(adapter); 1979 igb_configure_rx(adapter); 1980 1981 igb_rx_fifo_flush_82575(&adapter->hw); 1982 1983 /* call igb_desc_unused which always leaves 1984 * at least 1 descriptor unused to make sure 1985 * next_to_use != next_to_clean 1986 */ 1987 for (i = 0; i < adapter->num_rx_queues; i++) { 1988 struct igb_ring *ring = adapter->rx_ring[i]; 1989 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1990 } 1991 } 1992 1993 /** 1994 * igb_power_up_link - Power up the phy/serdes link 1995 * @adapter: address of board private structure 1996 **/ 1997 void igb_power_up_link(struct igb_adapter *adapter) 1998 { 1999 igb_reset_phy(&adapter->hw); 2000 2001 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2002 igb_power_up_phy_copper(&adapter->hw); 2003 else 2004 igb_power_up_serdes_link_82575(&adapter->hw); 2005 2006 igb_setup_link(&adapter->hw); 2007 } 2008 2009 /** 2010 * igb_power_down_link - Power down the phy/serdes link 2011 * @adapter: address of board private structure 2012 */ 2013 static void igb_power_down_link(struct igb_adapter *adapter) 2014 { 2015 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2016 igb_power_down_phy_copper_82575(&adapter->hw); 2017 else 2018 igb_shutdown_serdes_link_82575(&adapter->hw); 2019 } 2020 2021 /** 2022 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2023 * @adapter: address of the board private structure 2024 **/ 2025 static void igb_check_swap_media(struct igb_adapter *adapter) 2026 { 2027 struct e1000_hw *hw = &adapter->hw; 2028 u32 ctrl_ext, connsw; 2029 bool swap_now = false; 2030 2031 ctrl_ext = rd32(E1000_CTRL_EXT); 2032 connsw = rd32(E1000_CONNSW); 2033 2034 /* need to live swap if current media is copper and we have fiber/serdes 2035 * to go to. 2036 */ 2037 2038 if ((hw->phy.media_type == e1000_media_type_copper) && 2039 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2040 swap_now = true; 2041 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2042 !(connsw & E1000_CONNSW_SERDESD)) { 2043 /* copper signal takes time to appear */ 2044 if (adapter->copper_tries < 4) { 2045 adapter->copper_tries++; 2046 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2047 wr32(E1000_CONNSW, connsw); 2048 return; 2049 } else { 2050 adapter->copper_tries = 0; 2051 if ((connsw & E1000_CONNSW_PHYSD) && 2052 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2053 swap_now = true; 2054 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2055 wr32(E1000_CONNSW, connsw); 2056 } 2057 } 2058 } 2059 2060 if (!swap_now) 2061 return; 2062 2063 switch (hw->phy.media_type) { 2064 case e1000_media_type_copper: 2065 netdev_info(adapter->netdev, 2066 "MAS: changing media to fiber/serdes\n"); 2067 ctrl_ext |= 2068 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2069 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2070 adapter->copper_tries = 0; 2071 break; 2072 case e1000_media_type_internal_serdes: 2073 case e1000_media_type_fiber: 2074 netdev_info(adapter->netdev, 2075 "MAS: changing media to copper\n"); 2076 ctrl_ext &= 2077 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2078 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2079 break; 2080 default: 2081 /* shouldn't get here during regular operation */ 2082 netdev_err(adapter->netdev, 2083 "AMS: Invalid media type found, returning\n"); 2084 break; 2085 } 2086 wr32(E1000_CTRL_EXT, ctrl_ext); 2087 } 2088 2089 /** 2090 * igb_up - Open the interface and prepare it to handle traffic 2091 * @adapter: board private structure 2092 **/ 2093 int igb_up(struct igb_adapter *adapter) 2094 { 2095 struct e1000_hw *hw = &adapter->hw; 2096 int i; 2097 2098 /* hardware has been reset, we need to reload some things */ 2099 igb_configure(adapter); 2100 2101 clear_bit(__IGB_DOWN, &adapter->state); 2102 2103 for (i = 0; i < adapter->num_q_vectors; i++) 2104 napi_enable(&(adapter->q_vector[i]->napi)); 2105 2106 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2107 igb_configure_msix(adapter); 2108 else 2109 igb_assign_vector(adapter->q_vector[0], 0); 2110 2111 /* Clear any pending interrupts. */ 2112 rd32(E1000_TSICR); 2113 rd32(E1000_ICR); 2114 igb_irq_enable(adapter); 2115 2116 /* notify VFs that reset has been completed */ 2117 if (adapter->vfs_allocated_count) { 2118 u32 reg_data = rd32(E1000_CTRL_EXT); 2119 2120 reg_data |= E1000_CTRL_EXT_PFRSTD; 2121 wr32(E1000_CTRL_EXT, reg_data); 2122 } 2123 2124 netif_tx_start_all_queues(adapter->netdev); 2125 2126 /* start the watchdog. */ 2127 hw->mac.get_link_status = 1; 2128 schedule_work(&adapter->watchdog_task); 2129 2130 if ((adapter->flags & IGB_FLAG_EEE) && 2131 (!hw->dev_spec._82575.eee_disable)) 2132 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2133 2134 return 0; 2135 } 2136 2137 void igb_down(struct igb_adapter *adapter) 2138 { 2139 struct net_device *netdev = adapter->netdev; 2140 struct e1000_hw *hw = &adapter->hw; 2141 u32 tctl, rctl; 2142 int i; 2143 2144 /* signal that we're down so the interrupt handler does not 2145 * reschedule our watchdog timer 2146 */ 2147 set_bit(__IGB_DOWN, &adapter->state); 2148 2149 /* disable receives in the hardware */ 2150 rctl = rd32(E1000_RCTL); 2151 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2152 /* flush and sleep below */ 2153 2154 igb_nfc_filter_exit(adapter); 2155 2156 netif_carrier_off(netdev); 2157 netif_tx_stop_all_queues(netdev); 2158 2159 /* disable transmits in the hardware */ 2160 tctl = rd32(E1000_TCTL); 2161 tctl &= ~E1000_TCTL_EN; 2162 wr32(E1000_TCTL, tctl); 2163 /* flush both disables and wait for them to finish */ 2164 wrfl(); 2165 usleep_range(10000, 11000); 2166 2167 igb_irq_disable(adapter); 2168 2169 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2170 2171 for (i = 0; i < adapter->num_q_vectors; i++) { 2172 if (adapter->q_vector[i]) { 2173 napi_synchronize(&adapter->q_vector[i]->napi); 2174 napi_disable(&adapter->q_vector[i]->napi); 2175 } 2176 } 2177 2178 del_timer_sync(&adapter->watchdog_timer); 2179 del_timer_sync(&adapter->phy_info_timer); 2180 2181 /* record the stats before reset*/ 2182 spin_lock(&adapter->stats64_lock); 2183 igb_update_stats(adapter); 2184 spin_unlock(&adapter->stats64_lock); 2185 2186 adapter->link_speed = 0; 2187 adapter->link_duplex = 0; 2188 2189 if (!pci_channel_offline(adapter->pdev)) 2190 igb_reset(adapter); 2191 2192 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2193 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2194 2195 igb_clean_all_tx_rings(adapter); 2196 igb_clean_all_rx_rings(adapter); 2197 #ifdef CONFIG_IGB_DCA 2198 2199 /* since we reset the hardware DCA settings were cleared */ 2200 igb_setup_dca(adapter); 2201 #endif 2202 } 2203 2204 void igb_reinit_locked(struct igb_adapter *adapter) 2205 { 2206 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2207 usleep_range(1000, 2000); 2208 igb_down(adapter); 2209 igb_up(adapter); 2210 clear_bit(__IGB_RESETTING, &adapter->state); 2211 } 2212 2213 /** igb_enable_mas - Media Autosense re-enable after swap 2214 * 2215 * @adapter: adapter struct 2216 **/ 2217 static void igb_enable_mas(struct igb_adapter *adapter) 2218 { 2219 struct e1000_hw *hw = &adapter->hw; 2220 u32 connsw = rd32(E1000_CONNSW); 2221 2222 /* configure for SerDes media detect */ 2223 if ((hw->phy.media_type == e1000_media_type_copper) && 2224 (!(connsw & E1000_CONNSW_SERDESD))) { 2225 connsw |= E1000_CONNSW_ENRGSRC; 2226 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2227 wr32(E1000_CONNSW, connsw); 2228 wrfl(); 2229 } 2230 } 2231 2232 #ifdef CONFIG_IGB_HWMON 2233 /** 2234 * igb_set_i2c_bb - Init I2C interface 2235 * @hw: pointer to hardware structure 2236 **/ 2237 static void igb_set_i2c_bb(struct e1000_hw *hw) 2238 { 2239 u32 ctrl_ext; 2240 s32 i2cctl; 2241 2242 ctrl_ext = rd32(E1000_CTRL_EXT); 2243 ctrl_ext |= E1000_CTRL_I2C_ENA; 2244 wr32(E1000_CTRL_EXT, ctrl_ext); 2245 wrfl(); 2246 2247 i2cctl = rd32(E1000_I2CPARAMS); 2248 i2cctl |= E1000_I2CBB_EN 2249 | E1000_I2C_CLK_OE_N 2250 | E1000_I2C_DATA_OE_N; 2251 wr32(E1000_I2CPARAMS, i2cctl); 2252 wrfl(); 2253 } 2254 #endif 2255 2256 void igb_reset(struct igb_adapter *adapter) 2257 { 2258 struct pci_dev *pdev = adapter->pdev; 2259 struct e1000_hw *hw = &adapter->hw; 2260 struct e1000_mac_info *mac = &hw->mac; 2261 struct e1000_fc_info *fc = &hw->fc; 2262 u32 pba, hwm; 2263 2264 /* Repartition Pba for greater than 9k mtu 2265 * To take effect CTRL.RST is required. 2266 */ 2267 switch (mac->type) { 2268 case e1000_i350: 2269 case e1000_i354: 2270 case e1000_82580: 2271 pba = rd32(E1000_RXPBS); 2272 pba = igb_rxpbs_adjust_82580(pba); 2273 break; 2274 case e1000_82576: 2275 pba = rd32(E1000_RXPBS); 2276 pba &= E1000_RXPBS_SIZE_MASK_82576; 2277 break; 2278 case e1000_82575: 2279 case e1000_i210: 2280 case e1000_i211: 2281 default: 2282 pba = E1000_PBA_34K; 2283 break; 2284 } 2285 2286 if (mac->type == e1000_82575) { 2287 u32 min_rx_space, min_tx_space, needed_tx_space; 2288 2289 /* write Rx PBA so that hardware can report correct Tx PBA */ 2290 wr32(E1000_PBA, pba); 2291 2292 /* To maintain wire speed transmits, the Tx FIFO should be 2293 * large enough to accommodate two full transmit packets, 2294 * rounded up to the next 1KB and expressed in KB. Likewise, 2295 * the Rx FIFO should be large enough to accommodate at least 2296 * one full receive packet and is similarly rounded up and 2297 * expressed in KB. 2298 */ 2299 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2300 2301 /* The Tx FIFO also stores 16 bytes of information about the Tx 2302 * but don't include Ethernet FCS because hardware appends it. 2303 * We only need to round down to the nearest 512 byte block 2304 * count since the value we care about is 2 frames, not 1. 2305 */ 2306 min_tx_space = adapter->max_frame_size; 2307 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2308 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2309 2310 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2311 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2312 2313 /* If current Tx allocation is less than the min Tx FIFO size, 2314 * and the min Tx FIFO size is less than the current Rx FIFO 2315 * allocation, take space away from current Rx allocation. 2316 */ 2317 if (needed_tx_space < pba) { 2318 pba -= needed_tx_space; 2319 2320 /* if short on Rx space, Rx wins and must trump Tx 2321 * adjustment 2322 */ 2323 if (pba < min_rx_space) 2324 pba = min_rx_space; 2325 } 2326 2327 /* adjust PBA for jumbo frames */ 2328 wr32(E1000_PBA, pba); 2329 } 2330 2331 /* flow control settings 2332 * The high water mark must be low enough to fit one full frame 2333 * after transmitting the pause frame. As such we must have enough 2334 * space to allow for us to complete our current transmit and then 2335 * receive the frame that is in progress from the link partner. 2336 * Set it to: 2337 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2338 */ 2339 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2340 2341 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2342 fc->low_water = fc->high_water - 16; 2343 fc->pause_time = 0xFFFF; 2344 fc->send_xon = 1; 2345 fc->current_mode = fc->requested_mode; 2346 2347 /* disable receive for all VFs and wait one second */ 2348 if (adapter->vfs_allocated_count) { 2349 int i; 2350 2351 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2352 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2353 2354 /* ping all the active vfs to let them know we are going down */ 2355 igb_ping_all_vfs(adapter); 2356 2357 /* disable transmits and receives */ 2358 wr32(E1000_VFRE, 0); 2359 wr32(E1000_VFTE, 0); 2360 } 2361 2362 /* Allow time for pending master requests to run */ 2363 hw->mac.ops.reset_hw(hw); 2364 wr32(E1000_WUC, 0); 2365 2366 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2367 /* need to resetup here after media swap */ 2368 adapter->ei.get_invariants(hw); 2369 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2370 } 2371 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2372 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2373 igb_enable_mas(adapter); 2374 } 2375 if (hw->mac.ops.init_hw(hw)) 2376 dev_err(&pdev->dev, "Hardware Error\n"); 2377 2378 /* RAR registers were cleared during init_hw, clear mac table */ 2379 igb_flush_mac_table(adapter); 2380 __dev_uc_unsync(adapter->netdev, NULL); 2381 2382 /* Recover default RAR entry */ 2383 igb_set_default_mac_filter(adapter); 2384 2385 /* Flow control settings reset on hardware reset, so guarantee flow 2386 * control is off when forcing speed. 2387 */ 2388 if (!hw->mac.autoneg) 2389 igb_force_mac_fc(hw); 2390 2391 igb_init_dmac(adapter, pba); 2392 #ifdef CONFIG_IGB_HWMON 2393 /* Re-initialize the thermal sensor on i350 devices. */ 2394 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2395 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2396 /* If present, re-initialize the external thermal sensor 2397 * interface. 2398 */ 2399 if (adapter->ets) 2400 igb_set_i2c_bb(hw); 2401 mac->ops.init_thermal_sensor_thresh(hw); 2402 } 2403 } 2404 #endif 2405 /* Re-establish EEE setting */ 2406 if (hw->phy.media_type == e1000_media_type_copper) { 2407 switch (mac->type) { 2408 case e1000_i350: 2409 case e1000_i210: 2410 case e1000_i211: 2411 igb_set_eee_i350(hw, true, true); 2412 break; 2413 case e1000_i354: 2414 igb_set_eee_i354(hw, true, true); 2415 break; 2416 default: 2417 break; 2418 } 2419 } 2420 if (!netif_running(adapter->netdev)) 2421 igb_power_down_link(adapter); 2422 2423 igb_update_mng_vlan(adapter); 2424 2425 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2426 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2427 2428 /* Re-enable PTP, where applicable. */ 2429 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2430 igb_ptp_reset(adapter); 2431 2432 igb_get_phy_info(hw); 2433 } 2434 2435 static netdev_features_t igb_fix_features(struct net_device *netdev, 2436 netdev_features_t features) 2437 { 2438 /* Since there is no support for separate Rx/Tx vlan accel 2439 * enable/disable make sure Tx flag is always in same state as Rx. 2440 */ 2441 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2442 features |= NETIF_F_HW_VLAN_CTAG_TX; 2443 else 2444 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2445 2446 return features; 2447 } 2448 2449 static int igb_set_features(struct net_device *netdev, 2450 netdev_features_t features) 2451 { 2452 netdev_features_t changed = netdev->features ^ features; 2453 struct igb_adapter *adapter = netdev_priv(netdev); 2454 2455 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2456 igb_vlan_mode(netdev, features); 2457 2458 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2459 return 0; 2460 2461 if (!(features & NETIF_F_NTUPLE)) { 2462 struct hlist_node *node2; 2463 struct igb_nfc_filter *rule; 2464 2465 spin_lock(&adapter->nfc_lock); 2466 hlist_for_each_entry_safe(rule, node2, 2467 &adapter->nfc_filter_list, nfc_node) { 2468 igb_erase_filter(adapter, rule); 2469 hlist_del(&rule->nfc_node); 2470 kfree(rule); 2471 } 2472 spin_unlock(&adapter->nfc_lock); 2473 adapter->nfc_filter_count = 0; 2474 } 2475 2476 netdev->features = features; 2477 2478 if (netif_running(netdev)) 2479 igb_reinit_locked(adapter); 2480 else 2481 igb_reset(adapter); 2482 2483 return 1; 2484 } 2485 2486 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2487 struct net_device *dev, 2488 const unsigned char *addr, u16 vid, 2489 u16 flags, 2490 struct netlink_ext_ack *extack) 2491 { 2492 /* guarantee we can provide a unique filter for the unicast address */ 2493 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2494 struct igb_adapter *adapter = netdev_priv(dev); 2495 int vfn = adapter->vfs_allocated_count; 2496 2497 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2498 return -ENOMEM; 2499 } 2500 2501 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2502 } 2503 2504 #define IGB_MAX_MAC_HDR_LEN 127 2505 #define IGB_MAX_NETWORK_HDR_LEN 511 2506 2507 static netdev_features_t 2508 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2509 netdev_features_t features) 2510 { 2511 unsigned int network_hdr_len, mac_hdr_len; 2512 2513 /* Make certain the headers can be described by a context descriptor */ 2514 mac_hdr_len = skb_network_offset(skb); 2515 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2516 return features & ~(NETIF_F_HW_CSUM | 2517 NETIF_F_SCTP_CRC | 2518 NETIF_F_GSO_UDP_L4 | 2519 NETIF_F_HW_VLAN_CTAG_TX | 2520 NETIF_F_TSO | 2521 NETIF_F_TSO6); 2522 2523 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2524 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2525 return features & ~(NETIF_F_HW_CSUM | 2526 NETIF_F_SCTP_CRC | 2527 NETIF_F_GSO_UDP_L4 | 2528 NETIF_F_TSO | 2529 NETIF_F_TSO6); 2530 2531 /* We can only support IPV4 TSO in tunnels if we can mangle the 2532 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2533 */ 2534 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2535 features &= ~NETIF_F_TSO; 2536 2537 return features; 2538 } 2539 2540 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2541 { 2542 if (!is_fqtss_enabled(adapter)) { 2543 enable_fqtss(adapter, true); 2544 return; 2545 } 2546 2547 igb_config_tx_modes(adapter, queue); 2548 2549 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2550 enable_fqtss(adapter, false); 2551 } 2552 2553 static int igb_offload_cbs(struct igb_adapter *adapter, 2554 struct tc_cbs_qopt_offload *qopt) 2555 { 2556 struct e1000_hw *hw = &adapter->hw; 2557 int err; 2558 2559 /* CBS offloading is only supported by i210 controller. */ 2560 if (hw->mac.type != e1000_i210) 2561 return -EOPNOTSUPP; 2562 2563 /* CBS offloading is only supported by queue 0 and queue 1. */ 2564 if (qopt->queue < 0 || qopt->queue > 1) 2565 return -EINVAL; 2566 2567 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2568 qopt->idleslope, qopt->sendslope, 2569 qopt->hicredit, qopt->locredit); 2570 if (err) 2571 return err; 2572 2573 igb_offload_apply(adapter, qopt->queue); 2574 2575 return 0; 2576 } 2577 2578 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2579 #define VLAN_PRIO_FULL_MASK (0x07) 2580 2581 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2582 struct flow_cls_offload *f, 2583 int traffic_class, 2584 struct igb_nfc_filter *input) 2585 { 2586 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2587 struct flow_dissector *dissector = rule->match.dissector; 2588 struct netlink_ext_ack *extack = f->common.extack; 2589 2590 if (dissector->used_keys & 2591 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2592 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2593 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2594 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2595 NL_SET_ERR_MSG_MOD(extack, 2596 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2597 return -EOPNOTSUPP; 2598 } 2599 2600 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2601 struct flow_match_eth_addrs match; 2602 2603 flow_rule_match_eth_addrs(rule, &match); 2604 if (!is_zero_ether_addr(match.mask->dst)) { 2605 if (!is_broadcast_ether_addr(match.mask->dst)) { 2606 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2607 return -EINVAL; 2608 } 2609 2610 input->filter.match_flags |= 2611 IGB_FILTER_FLAG_DST_MAC_ADDR; 2612 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2613 } 2614 2615 if (!is_zero_ether_addr(match.mask->src)) { 2616 if (!is_broadcast_ether_addr(match.mask->src)) { 2617 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2618 return -EINVAL; 2619 } 2620 2621 input->filter.match_flags |= 2622 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2623 ether_addr_copy(input->filter.src_addr, match.key->src); 2624 } 2625 } 2626 2627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2628 struct flow_match_basic match; 2629 2630 flow_rule_match_basic(rule, &match); 2631 if (match.mask->n_proto) { 2632 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2633 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2634 return -EINVAL; 2635 } 2636 2637 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2638 input->filter.etype = match.key->n_proto; 2639 } 2640 } 2641 2642 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2643 struct flow_match_vlan match; 2644 2645 flow_rule_match_vlan(rule, &match); 2646 if (match.mask->vlan_priority) { 2647 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2648 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2649 return -EINVAL; 2650 } 2651 2652 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2653 input->filter.vlan_tci = 2654 (__force __be16)match.key->vlan_priority; 2655 } 2656 } 2657 2658 input->action = traffic_class; 2659 input->cookie = f->cookie; 2660 2661 return 0; 2662 } 2663 2664 static int igb_configure_clsflower(struct igb_adapter *adapter, 2665 struct flow_cls_offload *cls_flower) 2666 { 2667 struct netlink_ext_ack *extack = cls_flower->common.extack; 2668 struct igb_nfc_filter *filter, *f; 2669 int err, tc; 2670 2671 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2672 if (tc < 0) { 2673 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2674 return -EINVAL; 2675 } 2676 2677 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2678 if (!filter) 2679 return -ENOMEM; 2680 2681 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2682 if (err < 0) 2683 goto err_parse; 2684 2685 spin_lock(&adapter->nfc_lock); 2686 2687 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2688 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2689 err = -EEXIST; 2690 NL_SET_ERR_MSG_MOD(extack, 2691 "This filter is already set in ethtool"); 2692 goto err_locked; 2693 } 2694 } 2695 2696 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2697 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2698 err = -EEXIST; 2699 NL_SET_ERR_MSG_MOD(extack, 2700 "This filter is already set in cls_flower"); 2701 goto err_locked; 2702 } 2703 } 2704 2705 err = igb_add_filter(adapter, filter); 2706 if (err < 0) { 2707 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2708 goto err_locked; 2709 } 2710 2711 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2712 2713 spin_unlock(&adapter->nfc_lock); 2714 2715 return 0; 2716 2717 err_locked: 2718 spin_unlock(&adapter->nfc_lock); 2719 2720 err_parse: 2721 kfree(filter); 2722 2723 return err; 2724 } 2725 2726 static int igb_delete_clsflower(struct igb_adapter *adapter, 2727 struct flow_cls_offload *cls_flower) 2728 { 2729 struct igb_nfc_filter *filter; 2730 int err; 2731 2732 spin_lock(&adapter->nfc_lock); 2733 2734 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2735 if (filter->cookie == cls_flower->cookie) 2736 break; 2737 2738 if (!filter) { 2739 err = -ENOENT; 2740 goto out; 2741 } 2742 2743 err = igb_erase_filter(adapter, filter); 2744 if (err < 0) 2745 goto out; 2746 2747 hlist_del(&filter->nfc_node); 2748 kfree(filter); 2749 2750 out: 2751 spin_unlock(&adapter->nfc_lock); 2752 2753 return err; 2754 } 2755 2756 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2757 struct flow_cls_offload *cls_flower) 2758 { 2759 switch (cls_flower->command) { 2760 case FLOW_CLS_REPLACE: 2761 return igb_configure_clsflower(adapter, cls_flower); 2762 case FLOW_CLS_DESTROY: 2763 return igb_delete_clsflower(adapter, cls_flower); 2764 case FLOW_CLS_STATS: 2765 return -EOPNOTSUPP; 2766 default: 2767 return -EOPNOTSUPP; 2768 } 2769 } 2770 2771 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2772 void *cb_priv) 2773 { 2774 struct igb_adapter *adapter = cb_priv; 2775 2776 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2777 return -EOPNOTSUPP; 2778 2779 switch (type) { 2780 case TC_SETUP_CLSFLOWER: 2781 return igb_setup_tc_cls_flower(adapter, type_data); 2782 2783 default: 2784 return -EOPNOTSUPP; 2785 } 2786 } 2787 2788 static int igb_offload_txtime(struct igb_adapter *adapter, 2789 struct tc_etf_qopt_offload *qopt) 2790 { 2791 struct e1000_hw *hw = &adapter->hw; 2792 int err; 2793 2794 /* Launchtime offloading is only supported by i210 controller. */ 2795 if (hw->mac.type != e1000_i210) 2796 return -EOPNOTSUPP; 2797 2798 /* Launchtime offloading is only supported by queues 0 and 1. */ 2799 if (qopt->queue < 0 || qopt->queue > 1) 2800 return -EINVAL; 2801 2802 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2803 if (err) 2804 return err; 2805 2806 igb_offload_apply(adapter, qopt->queue); 2807 2808 return 0; 2809 } 2810 2811 static int igb_tc_query_caps(struct igb_adapter *adapter, 2812 struct tc_query_caps_base *base) 2813 { 2814 switch (base->type) { 2815 case TC_SETUP_QDISC_TAPRIO: { 2816 struct tc_taprio_caps *caps = base->caps; 2817 2818 caps->broken_mqprio = true; 2819 2820 return 0; 2821 } 2822 default: 2823 return -EOPNOTSUPP; 2824 } 2825 } 2826 2827 static LIST_HEAD(igb_block_cb_list); 2828 2829 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2830 void *type_data) 2831 { 2832 struct igb_adapter *adapter = netdev_priv(dev); 2833 2834 switch (type) { 2835 case TC_QUERY_CAPS: 2836 return igb_tc_query_caps(adapter, type_data); 2837 case TC_SETUP_QDISC_CBS: 2838 return igb_offload_cbs(adapter, type_data); 2839 case TC_SETUP_BLOCK: 2840 return flow_block_cb_setup_simple(type_data, 2841 &igb_block_cb_list, 2842 igb_setup_tc_block_cb, 2843 adapter, adapter, true); 2844 2845 case TC_SETUP_QDISC_ETF: 2846 return igb_offload_txtime(adapter, type_data); 2847 2848 default: 2849 return -EOPNOTSUPP; 2850 } 2851 } 2852 2853 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2854 { 2855 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2856 struct igb_adapter *adapter = netdev_priv(dev); 2857 struct bpf_prog *prog = bpf->prog, *old_prog; 2858 bool running = netif_running(dev); 2859 bool need_reset; 2860 2861 /* verify igb ring attributes are sufficient for XDP */ 2862 for (i = 0; i < adapter->num_rx_queues; i++) { 2863 struct igb_ring *ring = adapter->rx_ring[i]; 2864 2865 if (frame_size > igb_rx_bufsz(ring)) { 2866 NL_SET_ERR_MSG_MOD(bpf->extack, 2867 "The RX buffer size is too small for the frame size"); 2868 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2869 igb_rx_bufsz(ring), frame_size); 2870 return -EINVAL; 2871 } 2872 } 2873 2874 old_prog = xchg(&adapter->xdp_prog, prog); 2875 need_reset = (!!prog != !!old_prog); 2876 2877 /* device is up and bpf is added/removed, must setup the RX queues */ 2878 if (need_reset && running) { 2879 igb_close(dev); 2880 } else { 2881 for (i = 0; i < adapter->num_rx_queues; i++) 2882 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2883 adapter->xdp_prog); 2884 } 2885 2886 if (old_prog) 2887 bpf_prog_put(old_prog); 2888 2889 /* bpf is just replaced, RXQ and MTU are already setup */ 2890 if (!need_reset) { 2891 return 0; 2892 } else { 2893 if (prog) 2894 xdp_features_set_redirect_target(dev, true); 2895 else 2896 xdp_features_clear_redirect_target(dev); 2897 } 2898 2899 if (running) 2900 igb_open(dev); 2901 2902 return 0; 2903 } 2904 2905 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2906 { 2907 switch (xdp->command) { 2908 case XDP_SETUP_PROG: 2909 return igb_xdp_setup(dev, xdp); 2910 default: 2911 return -EINVAL; 2912 } 2913 } 2914 2915 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2916 { 2917 /* Force memory writes to complete before letting h/w know there 2918 * are new descriptors to fetch. 2919 */ 2920 wmb(); 2921 writel(ring->next_to_use, ring->tail); 2922 } 2923 2924 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2925 { 2926 unsigned int r_idx = smp_processor_id(); 2927 2928 if (r_idx >= adapter->num_tx_queues) 2929 r_idx = r_idx % adapter->num_tx_queues; 2930 2931 return adapter->tx_ring[r_idx]; 2932 } 2933 2934 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2935 { 2936 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2937 int cpu = smp_processor_id(); 2938 struct igb_ring *tx_ring; 2939 struct netdev_queue *nq; 2940 u32 ret; 2941 2942 if (unlikely(!xdpf)) 2943 return IGB_XDP_CONSUMED; 2944 2945 /* During program transitions its possible adapter->xdp_prog is assigned 2946 * but ring has not been configured yet. In this case simply abort xmit. 2947 */ 2948 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2949 if (unlikely(!tx_ring)) 2950 return IGB_XDP_CONSUMED; 2951 2952 nq = txring_txq(tx_ring); 2953 __netif_tx_lock(nq, cpu); 2954 /* Avoid transmit queue timeout since we share it with the slow path */ 2955 txq_trans_cond_update(nq); 2956 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2957 __netif_tx_unlock(nq); 2958 2959 return ret; 2960 } 2961 2962 static int igb_xdp_xmit(struct net_device *dev, int n, 2963 struct xdp_frame **frames, u32 flags) 2964 { 2965 struct igb_adapter *adapter = netdev_priv(dev); 2966 int cpu = smp_processor_id(); 2967 struct igb_ring *tx_ring; 2968 struct netdev_queue *nq; 2969 int nxmit = 0; 2970 int i; 2971 2972 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2973 return -ENETDOWN; 2974 2975 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2976 return -EINVAL; 2977 2978 /* During program transitions its possible adapter->xdp_prog is assigned 2979 * but ring has not been configured yet. In this case simply abort xmit. 2980 */ 2981 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2982 if (unlikely(!tx_ring)) 2983 return -ENXIO; 2984 2985 nq = txring_txq(tx_ring); 2986 __netif_tx_lock(nq, cpu); 2987 2988 /* Avoid transmit queue timeout since we share it with the slow path */ 2989 txq_trans_cond_update(nq); 2990 2991 for (i = 0; i < n; i++) { 2992 struct xdp_frame *xdpf = frames[i]; 2993 int err; 2994 2995 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2996 if (err != IGB_XDP_TX) 2997 break; 2998 nxmit++; 2999 } 3000 3001 __netif_tx_unlock(nq); 3002 3003 if (unlikely(flags & XDP_XMIT_FLUSH)) 3004 igb_xdp_ring_update_tail(tx_ring); 3005 3006 return nxmit; 3007 } 3008 3009 static const struct net_device_ops igb_netdev_ops = { 3010 .ndo_open = igb_open, 3011 .ndo_stop = igb_close, 3012 .ndo_start_xmit = igb_xmit_frame, 3013 .ndo_get_stats64 = igb_get_stats64, 3014 .ndo_set_rx_mode = igb_set_rx_mode, 3015 .ndo_set_mac_address = igb_set_mac, 3016 .ndo_change_mtu = igb_change_mtu, 3017 .ndo_eth_ioctl = igb_ioctl, 3018 .ndo_tx_timeout = igb_tx_timeout, 3019 .ndo_validate_addr = eth_validate_addr, 3020 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3021 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3022 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3023 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3024 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3025 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3026 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3027 .ndo_get_vf_config = igb_ndo_get_vf_config, 3028 .ndo_fix_features = igb_fix_features, 3029 .ndo_set_features = igb_set_features, 3030 .ndo_fdb_add = igb_ndo_fdb_add, 3031 .ndo_features_check = igb_features_check, 3032 .ndo_setup_tc = igb_setup_tc, 3033 .ndo_bpf = igb_xdp, 3034 .ndo_xdp_xmit = igb_xdp_xmit, 3035 }; 3036 3037 /** 3038 * igb_set_fw_version - Configure version string for ethtool 3039 * @adapter: adapter struct 3040 **/ 3041 void igb_set_fw_version(struct igb_adapter *adapter) 3042 { 3043 struct e1000_hw *hw = &adapter->hw; 3044 struct e1000_fw_version fw; 3045 3046 igb_get_fw_version(hw, &fw); 3047 3048 switch (hw->mac.type) { 3049 case e1000_i210: 3050 case e1000_i211: 3051 if (!(igb_get_flash_presence_i210(hw))) { 3052 snprintf(adapter->fw_version, 3053 sizeof(adapter->fw_version), 3054 "%2d.%2d-%d", 3055 fw.invm_major, fw.invm_minor, 3056 fw.invm_img_type); 3057 break; 3058 } 3059 fallthrough; 3060 default: 3061 /* if option rom is valid, display its version too */ 3062 if (fw.or_valid) { 3063 snprintf(adapter->fw_version, 3064 sizeof(adapter->fw_version), 3065 "%d.%d, 0x%08x, %d.%d.%d", 3066 fw.eep_major, fw.eep_minor, fw.etrack_id, 3067 fw.or_major, fw.or_build, fw.or_patch); 3068 /* no option rom */ 3069 } else if (fw.etrack_id != 0X0000) { 3070 snprintf(adapter->fw_version, 3071 sizeof(adapter->fw_version), 3072 "%d.%d, 0x%08x", 3073 fw.eep_major, fw.eep_minor, fw.etrack_id); 3074 } else { 3075 snprintf(adapter->fw_version, 3076 sizeof(adapter->fw_version), 3077 "%d.%d.%d", 3078 fw.eep_major, fw.eep_minor, fw.eep_build); 3079 } 3080 break; 3081 } 3082 } 3083 3084 /** 3085 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3086 * 3087 * @adapter: adapter struct 3088 **/ 3089 static void igb_init_mas(struct igb_adapter *adapter) 3090 { 3091 struct e1000_hw *hw = &adapter->hw; 3092 u16 eeprom_data; 3093 3094 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3095 switch (hw->bus.func) { 3096 case E1000_FUNC_0: 3097 if (eeprom_data & IGB_MAS_ENABLE_0) { 3098 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3099 netdev_info(adapter->netdev, 3100 "MAS: Enabling Media Autosense for port %d\n", 3101 hw->bus.func); 3102 } 3103 break; 3104 case E1000_FUNC_1: 3105 if (eeprom_data & IGB_MAS_ENABLE_1) { 3106 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3107 netdev_info(adapter->netdev, 3108 "MAS: Enabling Media Autosense for port %d\n", 3109 hw->bus.func); 3110 } 3111 break; 3112 case E1000_FUNC_2: 3113 if (eeprom_data & IGB_MAS_ENABLE_2) { 3114 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3115 netdev_info(adapter->netdev, 3116 "MAS: Enabling Media Autosense for port %d\n", 3117 hw->bus.func); 3118 } 3119 break; 3120 case E1000_FUNC_3: 3121 if (eeprom_data & IGB_MAS_ENABLE_3) { 3122 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3123 netdev_info(adapter->netdev, 3124 "MAS: Enabling Media Autosense for port %d\n", 3125 hw->bus.func); 3126 } 3127 break; 3128 default: 3129 /* Shouldn't get here */ 3130 netdev_err(adapter->netdev, 3131 "MAS: Invalid port configuration, returning\n"); 3132 break; 3133 } 3134 } 3135 3136 /** 3137 * igb_init_i2c - Init I2C interface 3138 * @adapter: pointer to adapter structure 3139 **/ 3140 static s32 igb_init_i2c(struct igb_adapter *adapter) 3141 { 3142 s32 status = 0; 3143 3144 /* I2C interface supported on i350 devices */ 3145 if (adapter->hw.mac.type != e1000_i350) 3146 return 0; 3147 3148 /* Initialize the i2c bus which is controlled by the registers. 3149 * This bus will use the i2c_algo_bit structure that implements 3150 * the protocol through toggling of the 4 bits in the register. 3151 */ 3152 adapter->i2c_adap.owner = THIS_MODULE; 3153 adapter->i2c_algo = igb_i2c_algo; 3154 adapter->i2c_algo.data = adapter; 3155 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3156 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3157 strscpy(adapter->i2c_adap.name, "igb BB", 3158 sizeof(adapter->i2c_adap.name)); 3159 status = i2c_bit_add_bus(&adapter->i2c_adap); 3160 return status; 3161 } 3162 3163 /** 3164 * igb_probe - Device Initialization Routine 3165 * @pdev: PCI device information struct 3166 * @ent: entry in igb_pci_tbl 3167 * 3168 * Returns 0 on success, negative on failure 3169 * 3170 * igb_probe initializes an adapter identified by a pci_dev structure. 3171 * The OS initialization, configuring of the adapter private structure, 3172 * and a hardware reset occur. 3173 **/ 3174 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3175 { 3176 struct net_device *netdev; 3177 struct igb_adapter *adapter; 3178 struct e1000_hw *hw; 3179 u16 eeprom_data = 0; 3180 s32 ret_val; 3181 static int global_quad_port_a; /* global quad port a indication */ 3182 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3183 u8 part_str[E1000_PBANUM_LENGTH]; 3184 int err; 3185 3186 /* Catch broken hardware that put the wrong VF device ID in 3187 * the PCIe SR-IOV capability. 3188 */ 3189 if (pdev->is_virtfn) { 3190 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3191 pci_name(pdev), pdev->vendor, pdev->device); 3192 return -EINVAL; 3193 } 3194 3195 err = pci_enable_device_mem(pdev); 3196 if (err) 3197 return err; 3198 3199 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3200 if (err) { 3201 dev_err(&pdev->dev, 3202 "No usable DMA configuration, aborting\n"); 3203 goto err_dma; 3204 } 3205 3206 err = pci_request_mem_regions(pdev, igb_driver_name); 3207 if (err) 3208 goto err_pci_reg; 3209 3210 pci_set_master(pdev); 3211 pci_save_state(pdev); 3212 3213 err = -ENOMEM; 3214 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3215 IGB_MAX_TX_QUEUES); 3216 if (!netdev) 3217 goto err_alloc_etherdev; 3218 3219 SET_NETDEV_DEV(netdev, &pdev->dev); 3220 3221 pci_set_drvdata(pdev, netdev); 3222 adapter = netdev_priv(netdev); 3223 adapter->netdev = netdev; 3224 adapter->pdev = pdev; 3225 hw = &adapter->hw; 3226 hw->back = adapter; 3227 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3228 3229 err = -EIO; 3230 adapter->io_addr = pci_iomap(pdev, 0, 0); 3231 if (!adapter->io_addr) 3232 goto err_ioremap; 3233 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3234 hw->hw_addr = adapter->io_addr; 3235 3236 netdev->netdev_ops = &igb_netdev_ops; 3237 igb_set_ethtool_ops(netdev); 3238 netdev->watchdog_timeo = 5 * HZ; 3239 3240 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3241 3242 netdev->mem_start = pci_resource_start(pdev, 0); 3243 netdev->mem_end = pci_resource_end(pdev, 0); 3244 3245 /* PCI config space info */ 3246 hw->vendor_id = pdev->vendor; 3247 hw->device_id = pdev->device; 3248 hw->revision_id = pdev->revision; 3249 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3250 hw->subsystem_device_id = pdev->subsystem_device; 3251 3252 /* Copy the default MAC, PHY and NVM function pointers */ 3253 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3254 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3255 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3256 /* Initialize skew-specific constants */ 3257 err = ei->get_invariants(hw); 3258 if (err) 3259 goto err_sw_init; 3260 3261 /* setup the private structure */ 3262 err = igb_sw_init(adapter); 3263 if (err) 3264 goto err_sw_init; 3265 3266 igb_get_bus_info_pcie(hw); 3267 3268 hw->phy.autoneg_wait_to_complete = false; 3269 3270 /* Copper options */ 3271 if (hw->phy.media_type == e1000_media_type_copper) { 3272 hw->phy.mdix = AUTO_ALL_MODES; 3273 hw->phy.disable_polarity_correction = false; 3274 hw->phy.ms_type = e1000_ms_hw_default; 3275 } 3276 3277 if (igb_check_reset_block(hw)) 3278 dev_info(&pdev->dev, 3279 "PHY reset is blocked due to SOL/IDER session.\n"); 3280 3281 /* features is initialized to 0 in allocation, it might have bits 3282 * set by igb_sw_init so we should use an or instead of an 3283 * assignment. 3284 */ 3285 netdev->features |= NETIF_F_SG | 3286 NETIF_F_TSO | 3287 NETIF_F_TSO6 | 3288 NETIF_F_RXHASH | 3289 NETIF_F_RXCSUM | 3290 NETIF_F_HW_CSUM; 3291 3292 if (hw->mac.type >= e1000_82576) 3293 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3294 3295 if (hw->mac.type >= e1000_i350) 3296 netdev->features |= NETIF_F_HW_TC; 3297 3298 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3299 NETIF_F_GSO_GRE_CSUM | \ 3300 NETIF_F_GSO_IPXIP4 | \ 3301 NETIF_F_GSO_IPXIP6 | \ 3302 NETIF_F_GSO_UDP_TUNNEL | \ 3303 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3304 3305 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3306 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3307 3308 /* copy netdev features into list of user selectable features */ 3309 netdev->hw_features |= netdev->features | 3310 NETIF_F_HW_VLAN_CTAG_RX | 3311 NETIF_F_HW_VLAN_CTAG_TX | 3312 NETIF_F_RXALL; 3313 3314 if (hw->mac.type >= e1000_i350) 3315 netdev->hw_features |= NETIF_F_NTUPLE; 3316 3317 netdev->features |= NETIF_F_HIGHDMA; 3318 3319 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3320 netdev->mpls_features |= NETIF_F_HW_CSUM; 3321 netdev->hw_enc_features |= netdev->vlan_features; 3322 3323 /* set this bit last since it cannot be part of vlan_features */ 3324 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3325 NETIF_F_HW_VLAN_CTAG_RX | 3326 NETIF_F_HW_VLAN_CTAG_TX; 3327 3328 netdev->priv_flags |= IFF_SUPP_NOFCS; 3329 3330 netdev->priv_flags |= IFF_UNICAST_FLT; 3331 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3332 3333 /* MTU range: 68 - 9216 */ 3334 netdev->min_mtu = ETH_MIN_MTU; 3335 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3336 3337 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3338 3339 /* before reading the NVM, reset the controller to put the device in a 3340 * known good starting state 3341 */ 3342 hw->mac.ops.reset_hw(hw); 3343 3344 /* make sure the NVM is good , i211/i210 parts can have special NVM 3345 * that doesn't contain a checksum 3346 */ 3347 switch (hw->mac.type) { 3348 case e1000_i210: 3349 case e1000_i211: 3350 if (igb_get_flash_presence_i210(hw)) { 3351 if (hw->nvm.ops.validate(hw) < 0) { 3352 dev_err(&pdev->dev, 3353 "The NVM Checksum Is Not Valid\n"); 3354 err = -EIO; 3355 goto err_eeprom; 3356 } 3357 } 3358 break; 3359 default: 3360 if (hw->nvm.ops.validate(hw) < 0) { 3361 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3362 err = -EIO; 3363 goto err_eeprom; 3364 } 3365 break; 3366 } 3367 3368 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3369 /* copy the MAC address out of the NVM */ 3370 if (hw->mac.ops.read_mac_addr(hw)) 3371 dev_err(&pdev->dev, "NVM Read Error\n"); 3372 } 3373 3374 eth_hw_addr_set(netdev, hw->mac.addr); 3375 3376 if (!is_valid_ether_addr(netdev->dev_addr)) { 3377 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3378 err = -EIO; 3379 goto err_eeprom; 3380 } 3381 3382 igb_set_default_mac_filter(adapter); 3383 3384 /* get firmware version for ethtool -i */ 3385 igb_set_fw_version(adapter); 3386 3387 /* configure RXPBSIZE and TXPBSIZE */ 3388 if (hw->mac.type == e1000_i210) { 3389 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3390 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3391 } 3392 3393 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3394 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3395 3396 INIT_WORK(&adapter->reset_task, igb_reset_task); 3397 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3398 3399 /* Initialize link properties that are user-changeable */ 3400 adapter->fc_autoneg = true; 3401 hw->mac.autoneg = true; 3402 hw->phy.autoneg_advertised = 0x2f; 3403 3404 hw->fc.requested_mode = e1000_fc_default; 3405 hw->fc.current_mode = e1000_fc_default; 3406 3407 igb_validate_mdi_setting(hw); 3408 3409 /* By default, support wake on port A */ 3410 if (hw->bus.func == 0) 3411 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3412 3413 /* Check the NVM for wake support on non-port A ports */ 3414 if (hw->mac.type >= e1000_82580) 3415 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3416 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3417 &eeprom_data); 3418 else if (hw->bus.func == 1) 3419 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3420 3421 if (eeprom_data & IGB_EEPROM_APME) 3422 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3423 3424 /* now that we have the eeprom settings, apply the special cases where 3425 * the eeprom may be wrong or the board simply won't support wake on 3426 * lan on a particular port 3427 */ 3428 switch (pdev->device) { 3429 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3430 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3431 break; 3432 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3433 case E1000_DEV_ID_82576_FIBER: 3434 case E1000_DEV_ID_82576_SERDES: 3435 /* Wake events only supported on port A for dual fiber 3436 * regardless of eeprom setting 3437 */ 3438 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3439 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3440 break; 3441 case E1000_DEV_ID_82576_QUAD_COPPER: 3442 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3443 /* if quad port adapter, disable WoL on all but port A */ 3444 if (global_quad_port_a != 0) 3445 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3446 else 3447 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3448 /* Reset for multiple quad port adapters */ 3449 if (++global_quad_port_a == 4) 3450 global_quad_port_a = 0; 3451 break; 3452 default: 3453 /* If the device can't wake, don't set software support */ 3454 if (!device_can_wakeup(&adapter->pdev->dev)) 3455 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3456 } 3457 3458 /* initialize the wol settings based on the eeprom settings */ 3459 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3460 adapter->wol |= E1000_WUFC_MAG; 3461 3462 /* Some vendors want WoL disabled by default, but still supported */ 3463 if ((hw->mac.type == e1000_i350) && 3464 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3465 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3466 adapter->wol = 0; 3467 } 3468 3469 /* Some vendors want the ability to Use the EEPROM setting as 3470 * enable/disable only, and not for capability 3471 */ 3472 if (((hw->mac.type == e1000_i350) || 3473 (hw->mac.type == e1000_i354)) && 3474 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3475 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3476 adapter->wol = 0; 3477 } 3478 if (hw->mac.type == e1000_i350) { 3479 if (((pdev->subsystem_device == 0x5001) || 3480 (pdev->subsystem_device == 0x5002)) && 3481 (hw->bus.func == 0)) { 3482 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3483 adapter->wol = 0; 3484 } 3485 if (pdev->subsystem_device == 0x1F52) 3486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3487 } 3488 3489 device_set_wakeup_enable(&adapter->pdev->dev, 3490 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3491 3492 /* reset the hardware with the new settings */ 3493 igb_reset(adapter); 3494 3495 /* Init the I2C interface */ 3496 err = igb_init_i2c(adapter); 3497 if (err) { 3498 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3499 goto err_eeprom; 3500 } 3501 3502 /* let the f/w know that the h/w is now under the control of the 3503 * driver. 3504 */ 3505 igb_get_hw_control(adapter); 3506 3507 strcpy(netdev->name, "eth%d"); 3508 err = register_netdev(netdev); 3509 if (err) 3510 goto err_register; 3511 3512 /* carrier off reporting is important to ethtool even BEFORE open */ 3513 netif_carrier_off(netdev); 3514 3515 #ifdef CONFIG_IGB_DCA 3516 if (dca_add_requester(&pdev->dev) == 0) { 3517 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3518 dev_info(&pdev->dev, "DCA enabled\n"); 3519 igb_setup_dca(adapter); 3520 } 3521 3522 #endif 3523 #ifdef CONFIG_IGB_HWMON 3524 /* Initialize the thermal sensor on i350 devices. */ 3525 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3526 u16 ets_word; 3527 3528 /* Read the NVM to determine if this i350 device supports an 3529 * external thermal sensor. 3530 */ 3531 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3532 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3533 adapter->ets = true; 3534 else 3535 adapter->ets = false; 3536 /* Only enable I2C bit banging if an external thermal 3537 * sensor is supported. 3538 */ 3539 if (adapter->ets) 3540 igb_set_i2c_bb(hw); 3541 hw->mac.ops.init_thermal_sensor_thresh(hw); 3542 if (igb_sysfs_init(adapter)) 3543 dev_err(&pdev->dev, 3544 "failed to allocate sysfs resources\n"); 3545 } else { 3546 adapter->ets = false; 3547 } 3548 #endif 3549 /* Check if Media Autosense is enabled */ 3550 adapter->ei = *ei; 3551 if (hw->dev_spec._82575.mas_capable) 3552 igb_init_mas(adapter); 3553 3554 /* do hw tstamp init after resetting */ 3555 igb_ptp_init(adapter); 3556 3557 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3558 /* print bus type/speed/width info, not applicable to i354 */ 3559 if (hw->mac.type != e1000_i354) { 3560 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3561 netdev->name, 3562 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3563 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3564 "unknown"), 3565 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3566 "Width x4" : 3567 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3568 "Width x2" : 3569 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3570 "Width x1" : "unknown"), netdev->dev_addr); 3571 } 3572 3573 if ((hw->mac.type == e1000_82576 && 3574 rd32(E1000_EECD) & E1000_EECD_PRES) || 3575 (hw->mac.type >= e1000_i210 || 3576 igb_get_flash_presence_i210(hw))) { 3577 ret_val = igb_read_part_string(hw, part_str, 3578 E1000_PBANUM_LENGTH); 3579 } else { 3580 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3581 } 3582 3583 if (ret_val) 3584 strcpy(part_str, "Unknown"); 3585 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3586 dev_info(&pdev->dev, 3587 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3588 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3589 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3590 adapter->num_rx_queues, adapter->num_tx_queues); 3591 if (hw->phy.media_type == e1000_media_type_copper) { 3592 switch (hw->mac.type) { 3593 case e1000_i350: 3594 case e1000_i210: 3595 case e1000_i211: 3596 /* Enable EEE for internal copper PHY devices */ 3597 err = igb_set_eee_i350(hw, true, true); 3598 if ((!err) && 3599 (!hw->dev_spec._82575.eee_disable)) { 3600 adapter->eee_advert = 3601 MDIO_EEE_100TX | MDIO_EEE_1000T; 3602 adapter->flags |= IGB_FLAG_EEE; 3603 } 3604 break; 3605 case e1000_i354: 3606 if ((rd32(E1000_CTRL_EXT) & 3607 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3608 err = igb_set_eee_i354(hw, true, true); 3609 if ((!err) && 3610 (!hw->dev_spec._82575.eee_disable)) { 3611 adapter->eee_advert = 3612 MDIO_EEE_100TX | MDIO_EEE_1000T; 3613 adapter->flags |= IGB_FLAG_EEE; 3614 } 3615 } 3616 break; 3617 default: 3618 break; 3619 } 3620 } 3621 3622 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3623 3624 pm_runtime_put_noidle(&pdev->dev); 3625 return 0; 3626 3627 err_register: 3628 igb_release_hw_control(adapter); 3629 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3630 err_eeprom: 3631 if (!igb_check_reset_block(hw)) 3632 igb_reset_phy(hw); 3633 3634 if (hw->flash_address) 3635 iounmap(hw->flash_address); 3636 err_sw_init: 3637 kfree(adapter->mac_table); 3638 kfree(adapter->shadow_vfta); 3639 igb_clear_interrupt_scheme(adapter); 3640 #ifdef CONFIG_PCI_IOV 3641 igb_disable_sriov(pdev, false); 3642 #endif 3643 pci_iounmap(pdev, adapter->io_addr); 3644 err_ioremap: 3645 free_netdev(netdev); 3646 err_alloc_etherdev: 3647 pci_release_mem_regions(pdev); 3648 err_pci_reg: 3649 err_dma: 3650 pci_disable_device(pdev); 3651 return err; 3652 } 3653 3654 #ifdef CONFIG_PCI_IOV 3655 static int igb_sriov_reinit(struct pci_dev *dev) 3656 { 3657 struct net_device *netdev = pci_get_drvdata(dev); 3658 struct igb_adapter *adapter = netdev_priv(netdev); 3659 struct pci_dev *pdev = adapter->pdev; 3660 3661 rtnl_lock(); 3662 3663 if (netif_running(netdev)) 3664 igb_close(netdev); 3665 else 3666 igb_reset(adapter); 3667 3668 igb_clear_interrupt_scheme(adapter); 3669 3670 igb_init_queue_configuration(adapter); 3671 3672 if (igb_init_interrupt_scheme(adapter, true)) { 3673 rtnl_unlock(); 3674 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3675 return -ENOMEM; 3676 } 3677 3678 if (netif_running(netdev)) 3679 igb_open(netdev); 3680 3681 rtnl_unlock(); 3682 3683 return 0; 3684 } 3685 3686 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3687 { 3688 struct net_device *netdev = pci_get_drvdata(pdev); 3689 struct igb_adapter *adapter = netdev_priv(netdev); 3690 struct e1000_hw *hw = &adapter->hw; 3691 unsigned long flags; 3692 3693 /* reclaim resources allocated to VFs */ 3694 if (adapter->vf_data) { 3695 /* disable iov and allow time for transactions to clear */ 3696 if (pci_vfs_assigned(pdev)) { 3697 dev_warn(&pdev->dev, 3698 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3699 return -EPERM; 3700 } else { 3701 pci_disable_sriov(pdev); 3702 msleep(500); 3703 } 3704 spin_lock_irqsave(&adapter->vfs_lock, flags); 3705 kfree(adapter->vf_mac_list); 3706 adapter->vf_mac_list = NULL; 3707 kfree(adapter->vf_data); 3708 adapter->vf_data = NULL; 3709 adapter->vfs_allocated_count = 0; 3710 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3711 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3712 wrfl(); 3713 msleep(100); 3714 dev_info(&pdev->dev, "IOV Disabled\n"); 3715 3716 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3717 adapter->flags |= IGB_FLAG_DMAC; 3718 } 3719 3720 return reinit ? igb_sriov_reinit(pdev) : 0; 3721 } 3722 3723 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3724 { 3725 struct net_device *netdev = pci_get_drvdata(pdev); 3726 struct igb_adapter *adapter = netdev_priv(netdev); 3727 int old_vfs = pci_num_vf(pdev); 3728 struct vf_mac_filter *mac_list; 3729 int err = 0; 3730 int num_vf_mac_filters, i; 3731 3732 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3733 err = -EPERM; 3734 goto out; 3735 } 3736 if (!num_vfs) 3737 goto out; 3738 3739 if (old_vfs) { 3740 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3741 old_vfs, max_vfs); 3742 adapter->vfs_allocated_count = old_vfs; 3743 } else 3744 adapter->vfs_allocated_count = num_vfs; 3745 3746 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3747 sizeof(struct vf_data_storage), GFP_KERNEL); 3748 3749 /* if allocation failed then we do not support SR-IOV */ 3750 if (!adapter->vf_data) { 3751 adapter->vfs_allocated_count = 0; 3752 err = -ENOMEM; 3753 goto out; 3754 } 3755 3756 /* Due to the limited number of RAR entries calculate potential 3757 * number of MAC filters available for the VFs. Reserve entries 3758 * for PF default MAC, PF MAC filters and at least one RAR entry 3759 * for each VF for VF MAC. 3760 */ 3761 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3762 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3763 adapter->vfs_allocated_count); 3764 3765 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3766 sizeof(struct vf_mac_filter), 3767 GFP_KERNEL); 3768 3769 mac_list = adapter->vf_mac_list; 3770 INIT_LIST_HEAD(&adapter->vf_macs.l); 3771 3772 if (adapter->vf_mac_list) { 3773 /* Initialize list of VF MAC filters */ 3774 for (i = 0; i < num_vf_mac_filters; i++) { 3775 mac_list->vf = -1; 3776 mac_list->free = true; 3777 list_add(&mac_list->l, &adapter->vf_macs.l); 3778 mac_list++; 3779 } 3780 } else { 3781 /* If we could not allocate memory for the VF MAC filters 3782 * we can continue without this feature but warn user. 3783 */ 3784 dev_err(&pdev->dev, 3785 "Unable to allocate memory for VF MAC filter list\n"); 3786 } 3787 3788 dev_info(&pdev->dev, "%d VFs allocated\n", 3789 adapter->vfs_allocated_count); 3790 for (i = 0; i < adapter->vfs_allocated_count; i++) 3791 igb_vf_configure(adapter, i); 3792 3793 /* DMA Coalescing is not supported in IOV mode. */ 3794 adapter->flags &= ~IGB_FLAG_DMAC; 3795 3796 if (reinit) { 3797 err = igb_sriov_reinit(pdev); 3798 if (err) 3799 goto err_out; 3800 } 3801 3802 /* only call pci_enable_sriov() if no VFs are allocated already */ 3803 if (!old_vfs) { 3804 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3805 if (err) 3806 goto err_out; 3807 } 3808 3809 goto out; 3810 3811 err_out: 3812 kfree(adapter->vf_mac_list); 3813 adapter->vf_mac_list = NULL; 3814 kfree(adapter->vf_data); 3815 adapter->vf_data = NULL; 3816 adapter->vfs_allocated_count = 0; 3817 out: 3818 return err; 3819 } 3820 3821 #endif 3822 /** 3823 * igb_remove_i2c - Cleanup I2C interface 3824 * @adapter: pointer to adapter structure 3825 **/ 3826 static void igb_remove_i2c(struct igb_adapter *adapter) 3827 { 3828 /* free the adapter bus structure */ 3829 i2c_del_adapter(&adapter->i2c_adap); 3830 } 3831 3832 /** 3833 * igb_remove - Device Removal Routine 3834 * @pdev: PCI device information struct 3835 * 3836 * igb_remove is called by the PCI subsystem to alert the driver 3837 * that it should release a PCI device. The could be caused by a 3838 * Hot-Plug event, or because the driver is going to be removed from 3839 * memory. 3840 **/ 3841 static void igb_remove(struct pci_dev *pdev) 3842 { 3843 struct net_device *netdev = pci_get_drvdata(pdev); 3844 struct igb_adapter *adapter = netdev_priv(netdev); 3845 struct e1000_hw *hw = &adapter->hw; 3846 3847 pm_runtime_get_noresume(&pdev->dev); 3848 #ifdef CONFIG_IGB_HWMON 3849 igb_sysfs_exit(adapter); 3850 #endif 3851 igb_remove_i2c(adapter); 3852 igb_ptp_stop(adapter); 3853 /* The watchdog timer may be rescheduled, so explicitly 3854 * disable watchdog from being rescheduled. 3855 */ 3856 set_bit(__IGB_DOWN, &adapter->state); 3857 del_timer_sync(&adapter->watchdog_timer); 3858 del_timer_sync(&adapter->phy_info_timer); 3859 3860 cancel_work_sync(&adapter->reset_task); 3861 cancel_work_sync(&adapter->watchdog_task); 3862 3863 #ifdef CONFIG_IGB_DCA 3864 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3865 dev_info(&pdev->dev, "DCA disabled\n"); 3866 dca_remove_requester(&pdev->dev); 3867 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3868 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3869 } 3870 #endif 3871 3872 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3873 * would have already happened in close and is redundant. 3874 */ 3875 igb_release_hw_control(adapter); 3876 3877 #ifdef CONFIG_PCI_IOV 3878 igb_disable_sriov(pdev, false); 3879 #endif 3880 3881 unregister_netdev(netdev); 3882 3883 igb_clear_interrupt_scheme(adapter); 3884 3885 pci_iounmap(pdev, adapter->io_addr); 3886 if (hw->flash_address) 3887 iounmap(hw->flash_address); 3888 pci_release_mem_regions(pdev); 3889 3890 kfree(adapter->mac_table); 3891 kfree(adapter->shadow_vfta); 3892 free_netdev(netdev); 3893 3894 pci_disable_device(pdev); 3895 } 3896 3897 /** 3898 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3899 * @adapter: board private structure to initialize 3900 * 3901 * This function initializes the vf specific data storage and then attempts to 3902 * allocate the VFs. The reason for ordering it this way is because it is much 3903 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3904 * the memory for the VFs. 3905 **/ 3906 static void igb_probe_vfs(struct igb_adapter *adapter) 3907 { 3908 #ifdef CONFIG_PCI_IOV 3909 struct pci_dev *pdev = adapter->pdev; 3910 struct e1000_hw *hw = &adapter->hw; 3911 3912 /* Virtualization features not supported on i210 and 82580 family. */ 3913 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3914 (hw->mac.type == e1000_82580)) 3915 return; 3916 3917 /* Of the below we really only want the effect of getting 3918 * IGB_FLAG_HAS_MSIX set (if available), without which 3919 * igb_enable_sriov() has no effect. 3920 */ 3921 igb_set_interrupt_capability(adapter, true); 3922 igb_reset_interrupt_capability(adapter); 3923 3924 pci_sriov_set_totalvfs(pdev, 7); 3925 igb_enable_sriov(pdev, max_vfs, false); 3926 3927 #endif /* CONFIG_PCI_IOV */ 3928 } 3929 3930 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3931 { 3932 struct e1000_hw *hw = &adapter->hw; 3933 unsigned int max_rss_queues; 3934 3935 /* Determine the maximum number of RSS queues supported. */ 3936 switch (hw->mac.type) { 3937 case e1000_i211: 3938 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3939 break; 3940 case e1000_82575: 3941 case e1000_i210: 3942 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3943 break; 3944 case e1000_i350: 3945 /* I350 cannot do RSS and SR-IOV at the same time */ 3946 if (!!adapter->vfs_allocated_count) { 3947 max_rss_queues = 1; 3948 break; 3949 } 3950 fallthrough; 3951 case e1000_82576: 3952 if (!!adapter->vfs_allocated_count) { 3953 max_rss_queues = 2; 3954 break; 3955 } 3956 fallthrough; 3957 case e1000_82580: 3958 case e1000_i354: 3959 default: 3960 max_rss_queues = IGB_MAX_RX_QUEUES; 3961 break; 3962 } 3963 3964 return max_rss_queues; 3965 } 3966 3967 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3968 { 3969 u32 max_rss_queues; 3970 3971 max_rss_queues = igb_get_max_rss_queues(adapter); 3972 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3973 3974 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3975 } 3976 3977 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3978 const u32 max_rss_queues) 3979 { 3980 struct e1000_hw *hw = &adapter->hw; 3981 3982 /* Determine if we need to pair queues. */ 3983 switch (hw->mac.type) { 3984 case e1000_82575: 3985 case e1000_i211: 3986 /* Device supports enough interrupts without queue pairing. */ 3987 break; 3988 case e1000_82576: 3989 case e1000_82580: 3990 case e1000_i350: 3991 case e1000_i354: 3992 case e1000_i210: 3993 default: 3994 /* If rss_queues > half of max_rss_queues, pair the queues in 3995 * order to conserve interrupts due to limited supply. 3996 */ 3997 if (adapter->rss_queues > (max_rss_queues / 2)) 3998 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3999 else 4000 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4001 break; 4002 } 4003 } 4004 4005 /** 4006 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4007 * @adapter: board private structure to initialize 4008 * 4009 * igb_sw_init initializes the Adapter private data structure. 4010 * Fields are initialized based on PCI device information and 4011 * OS network device settings (MTU size). 4012 **/ 4013 static int igb_sw_init(struct igb_adapter *adapter) 4014 { 4015 struct e1000_hw *hw = &adapter->hw; 4016 struct net_device *netdev = adapter->netdev; 4017 struct pci_dev *pdev = adapter->pdev; 4018 4019 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4020 4021 /* set default ring sizes */ 4022 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4023 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4024 4025 /* set default ITR values */ 4026 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4027 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4028 4029 /* set default work limits */ 4030 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4031 4032 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4033 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4034 4035 spin_lock_init(&adapter->nfc_lock); 4036 spin_lock_init(&adapter->stats64_lock); 4037 4038 /* init spinlock to avoid concurrency of VF resources */ 4039 spin_lock_init(&adapter->vfs_lock); 4040 #ifdef CONFIG_PCI_IOV 4041 switch (hw->mac.type) { 4042 case e1000_82576: 4043 case e1000_i350: 4044 if (max_vfs > 7) { 4045 dev_warn(&pdev->dev, 4046 "Maximum of 7 VFs per PF, using max\n"); 4047 max_vfs = adapter->vfs_allocated_count = 7; 4048 } else 4049 adapter->vfs_allocated_count = max_vfs; 4050 if (adapter->vfs_allocated_count) 4051 dev_warn(&pdev->dev, 4052 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4053 break; 4054 default: 4055 break; 4056 } 4057 #endif /* CONFIG_PCI_IOV */ 4058 4059 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4060 adapter->flags |= IGB_FLAG_HAS_MSIX; 4061 4062 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4063 sizeof(struct igb_mac_addr), 4064 GFP_KERNEL); 4065 if (!adapter->mac_table) 4066 return -ENOMEM; 4067 4068 igb_probe_vfs(adapter); 4069 4070 igb_init_queue_configuration(adapter); 4071 4072 /* Setup and initialize a copy of the hw vlan table array */ 4073 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4074 GFP_KERNEL); 4075 if (!adapter->shadow_vfta) 4076 return -ENOMEM; 4077 4078 /* This call may decrease the number of queues */ 4079 if (igb_init_interrupt_scheme(adapter, true)) { 4080 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4081 return -ENOMEM; 4082 } 4083 4084 /* Explicitly disable IRQ since the NIC can be in any state. */ 4085 igb_irq_disable(adapter); 4086 4087 if (hw->mac.type >= e1000_i350) 4088 adapter->flags &= ~IGB_FLAG_DMAC; 4089 4090 set_bit(__IGB_DOWN, &adapter->state); 4091 return 0; 4092 } 4093 4094 /** 4095 * __igb_open - Called when a network interface is made active 4096 * @netdev: network interface device structure 4097 * @resuming: indicates whether we are in a resume call 4098 * 4099 * Returns 0 on success, negative value on failure 4100 * 4101 * The open entry point is called when a network interface is made 4102 * active by the system (IFF_UP). At this point all resources needed 4103 * for transmit and receive operations are allocated, the interrupt 4104 * handler is registered with the OS, the watchdog timer is started, 4105 * and the stack is notified that the interface is ready. 4106 **/ 4107 static int __igb_open(struct net_device *netdev, bool resuming) 4108 { 4109 struct igb_adapter *adapter = netdev_priv(netdev); 4110 struct e1000_hw *hw = &adapter->hw; 4111 struct pci_dev *pdev = adapter->pdev; 4112 int err; 4113 int i; 4114 4115 /* disallow open during test */ 4116 if (test_bit(__IGB_TESTING, &adapter->state)) { 4117 WARN_ON(resuming); 4118 return -EBUSY; 4119 } 4120 4121 if (!resuming) 4122 pm_runtime_get_sync(&pdev->dev); 4123 4124 netif_carrier_off(netdev); 4125 4126 /* allocate transmit descriptors */ 4127 err = igb_setup_all_tx_resources(adapter); 4128 if (err) 4129 goto err_setup_tx; 4130 4131 /* allocate receive descriptors */ 4132 err = igb_setup_all_rx_resources(adapter); 4133 if (err) 4134 goto err_setup_rx; 4135 4136 igb_power_up_link(adapter); 4137 4138 /* before we allocate an interrupt, we must be ready to handle it. 4139 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4140 * as soon as we call pci_request_irq, so we have to setup our 4141 * clean_rx handler before we do so. 4142 */ 4143 igb_configure(adapter); 4144 4145 err = igb_request_irq(adapter); 4146 if (err) 4147 goto err_req_irq; 4148 4149 /* Notify the stack of the actual queue counts. */ 4150 err = netif_set_real_num_tx_queues(adapter->netdev, 4151 adapter->num_tx_queues); 4152 if (err) 4153 goto err_set_queues; 4154 4155 err = netif_set_real_num_rx_queues(adapter->netdev, 4156 adapter->num_rx_queues); 4157 if (err) 4158 goto err_set_queues; 4159 4160 /* From here on the code is the same as igb_up() */ 4161 clear_bit(__IGB_DOWN, &adapter->state); 4162 4163 for (i = 0; i < adapter->num_q_vectors; i++) 4164 napi_enable(&(adapter->q_vector[i]->napi)); 4165 4166 /* Clear any pending interrupts. */ 4167 rd32(E1000_TSICR); 4168 rd32(E1000_ICR); 4169 4170 igb_irq_enable(adapter); 4171 4172 /* notify VFs that reset has been completed */ 4173 if (adapter->vfs_allocated_count) { 4174 u32 reg_data = rd32(E1000_CTRL_EXT); 4175 4176 reg_data |= E1000_CTRL_EXT_PFRSTD; 4177 wr32(E1000_CTRL_EXT, reg_data); 4178 } 4179 4180 netif_tx_start_all_queues(netdev); 4181 4182 if (!resuming) 4183 pm_runtime_put(&pdev->dev); 4184 4185 /* start the watchdog. */ 4186 hw->mac.get_link_status = 1; 4187 schedule_work(&adapter->watchdog_task); 4188 4189 return 0; 4190 4191 err_set_queues: 4192 igb_free_irq(adapter); 4193 err_req_irq: 4194 igb_release_hw_control(adapter); 4195 igb_power_down_link(adapter); 4196 igb_free_all_rx_resources(adapter); 4197 err_setup_rx: 4198 igb_free_all_tx_resources(adapter); 4199 err_setup_tx: 4200 igb_reset(adapter); 4201 if (!resuming) 4202 pm_runtime_put(&pdev->dev); 4203 4204 return err; 4205 } 4206 4207 int igb_open(struct net_device *netdev) 4208 { 4209 return __igb_open(netdev, false); 4210 } 4211 4212 /** 4213 * __igb_close - Disables a network interface 4214 * @netdev: network interface device structure 4215 * @suspending: indicates we are in a suspend call 4216 * 4217 * Returns 0, this is not allowed to fail 4218 * 4219 * The close entry point is called when an interface is de-activated 4220 * by the OS. The hardware is still under the driver's control, but 4221 * needs to be disabled. A global MAC reset is issued to stop the 4222 * hardware, and all transmit and receive resources are freed. 4223 **/ 4224 static int __igb_close(struct net_device *netdev, bool suspending) 4225 { 4226 struct igb_adapter *adapter = netdev_priv(netdev); 4227 struct pci_dev *pdev = adapter->pdev; 4228 4229 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4230 4231 if (!suspending) 4232 pm_runtime_get_sync(&pdev->dev); 4233 4234 igb_down(adapter); 4235 igb_free_irq(adapter); 4236 4237 igb_free_all_tx_resources(adapter); 4238 igb_free_all_rx_resources(adapter); 4239 4240 if (!suspending) 4241 pm_runtime_put_sync(&pdev->dev); 4242 return 0; 4243 } 4244 4245 int igb_close(struct net_device *netdev) 4246 { 4247 if (netif_device_present(netdev) || netdev->dismantle) 4248 return __igb_close(netdev, false); 4249 return 0; 4250 } 4251 4252 /** 4253 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4254 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4255 * 4256 * Return 0 on success, negative on failure 4257 **/ 4258 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4259 { 4260 struct device *dev = tx_ring->dev; 4261 int size; 4262 4263 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4264 4265 tx_ring->tx_buffer_info = vmalloc(size); 4266 if (!tx_ring->tx_buffer_info) 4267 goto err; 4268 4269 /* round up to nearest 4K */ 4270 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4271 tx_ring->size = ALIGN(tx_ring->size, 4096); 4272 4273 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4274 &tx_ring->dma, GFP_KERNEL); 4275 if (!tx_ring->desc) 4276 goto err; 4277 4278 tx_ring->next_to_use = 0; 4279 tx_ring->next_to_clean = 0; 4280 4281 return 0; 4282 4283 err: 4284 vfree(tx_ring->tx_buffer_info); 4285 tx_ring->tx_buffer_info = NULL; 4286 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4287 return -ENOMEM; 4288 } 4289 4290 /** 4291 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4292 * (Descriptors) for all queues 4293 * @adapter: board private structure 4294 * 4295 * Return 0 on success, negative on failure 4296 **/ 4297 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4298 { 4299 struct pci_dev *pdev = adapter->pdev; 4300 int i, err = 0; 4301 4302 for (i = 0; i < adapter->num_tx_queues; i++) { 4303 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4304 if (err) { 4305 dev_err(&pdev->dev, 4306 "Allocation for Tx Queue %u failed\n", i); 4307 for (i--; i >= 0; i--) 4308 igb_free_tx_resources(adapter->tx_ring[i]); 4309 break; 4310 } 4311 } 4312 4313 return err; 4314 } 4315 4316 /** 4317 * igb_setup_tctl - configure the transmit control registers 4318 * @adapter: Board private structure 4319 **/ 4320 void igb_setup_tctl(struct igb_adapter *adapter) 4321 { 4322 struct e1000_hw *hw = &adapter->hw; 4323 u32 tctl; 4324 4325 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4326 wr32(E1000_TXDCTL(0), 0); 4327 4328 /* Program the Transmit Control Register */ 4329 tctl = rd32(E1000_TCTL); 4330 tctl &= ~E1000_TCTL_CT; 4331 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4332 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4333 4334 igb_config_collision_dist(hw); 4335 4336 /* Enable transmits */ 4337 tctl |= E1000_TCTL_EN; 4338 4339 wr32(E1000_TCTL, tctl); 4340 } 4341 4342 /** 4343 * igb_configure_tx_ring - Configure transmit ring after Reset 4344 * @adapter: board private structure 4345 * @ring: tx ring to configure 4346 * 4347 * Configure a transmit ring after a reset. 4348 **/ 4349 void igb_configure_tx_ring(struct igb_adapter *adapter, 4350 struct igb_ring *ring) 4351 { 4352 struct e1000_hw *hw = &adapter->hw; 4353 u32 txdctl = 0; 4354 u64 tdba = ring->dma; 4355 int reg_idx = ring->reg_idx; 4356 4357 wr32(E1000_TDLEN(reg_idx), 4358 ring->count * sizeof(union e1000_adv_tx_desc)); 4359 wr32(E1000_TDBAL(reg_idx), 4360 tdba & 0x00000000ffffffffULL); 4361 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4362 4363 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4364 wr32(E1000_TDH(reg_idx), 0); 4365 writel(0, ring->tail); 4366 4367 txdctl |= IGB_TX_PTHRESH; 4368 txdctl |= IGB_TX_HTHRESH << 8; 4369 txdctl |= IGB_TX_WTHRESH << 16; 4370 4371 /* reinitialize tx_buffer_info */ 4372 memset(ring->tx_buffer_info, 0, 4373 sizeof(struct igb_tx_buffer) * ring->count); 4374 4375 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4376 wr32(E1000_TXDCTL(reg_idx), txdctl); 4377 } 4378 4379 /** 4380 * igb_configure_tx - Configure transmit Unit after Reset 4381 * @adapter: board private structure 4382 * 4383 * Configure the Tx unit of the MAC after a reset. 4384 **/ 4385 static void igb_configure_tx(struct igb_adapter *adapter) 4386 { 4387 struct e1000_hw *hw = &adapter->hw; 4388 int i; 4389 4390 /* disable the queues */ 4391 for (i = 0; i < adapter->num_tx_queues; i++) 4392 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4393 4394 wrfl(); 4395 usleep_range(10000, 20000); 4396 4397 for (i = 0; i < adapter->num_tx_queues; i++) 4398 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4399 } 4400 4401 /** 4402 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4403 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4404 * 4405 * Returns 0 on success, negative on failure 4406 **/ 4407 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4408 { 4409 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4410 struct device *dev = rx_ring->dev; 4411 int size, res; 4412 4413 /* XDP RX-queue info */ 4414 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4415 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4416 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4417 rx_ring->queue_index, 0); 4418 if (res < 0) { 4419 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4420 rx_ring->queue_index); 4421 return res; 4422 } 4423 4424 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4425 4426 rx_ring->rx_buffer_info = vmalloc(size); 4427 if (!rx_ring->rx_buffer_info) 4428 goto err; 4429 4430 /* Round up to nearest 4K */ 4431 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4432 rx_ring->size = ALIGN(rx_ring->size, 4096); 4433 4434 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4435 &rx_ring->dma, GFP_KERNEL); 4436 if (!rx_ring->desc) 4437 goto err; 4438 4439 rx_ring->next_to_alloc = 0; 4440 rx_ring->next_to_clean = 0; 4441 rx_ring->next_to_use = 0; 4442 4443 rx_ring->xdp_prog = adapter->xdp_prog; 4444 4445 return 0; 4446 4447 err: 4448 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4449 vfree(rx_ring->rx_buffer_info); 4450 rx_ring->rx_buffer_info = NULL; 4451 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4452 return -ENOMEM; 4453 } 4454 4455 /** 4456 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4457 * (Descriptors) for all queues 4458 * @adapter: board private structure 4459 * 4460 * Return 0 on success, negative on failure 4461 **/ 4462 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4463 { 4464 struct pci_dev *pdev = adapter->pdev; 4465 int i, err = 0; 4466 4467 for (i = 0; i < adapter->num_rx_queues; i++) { 4468 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4469 if (err) { 4470 dev_err(&pdev->dev, 4471 "Allocation for Rx Queue %u failed\n", i); 4472 for (i--; i >= 0; i--) 4473 igb_free_rx_resources(adapter->rx_ring[i]); 4474 break; 4475 } 4476 } 4477 4478 return err; 4479 } 4480 4481 /** 4482 * igb_setup_mrqc - configure the multiple receive queue control registers 4483 * @adapter: Board private structure 4484 **/ 4485 static void igb_setup_mrqc(struct igb_adapter *adapter) 4486 { 4487 struct e1000_hw *hw = &adapter->hw; 4488 u32 mrqc, rxcsum; 4489 u32 j, num_rx_queues; 4490 u32 rss_key[10]; 4491 4492 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4493 for (j = 0; j < 10; j++) 4494 wr32(E1000_RSSRK(j), rss_key[j]); 4495 4496 num_rx_queues = adapter->rss_queues; 4497 4498 switch (hw->mac.type) { 4499 case e1000_82576: 4500 /* 82576 supports 2 RSS queues for SR-IOV */ 4501 if (adapter->vfs_allocated_count) 4502 num_rx_queues = 2; 4503 break; 4504 default: 4505 break; 4506 } 4507 4508 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4509 for (j = 0; j < IGB_RETA_SIZE; j++) 4510 adapter->rss_indir_tbl[j] = 4511 (j * num_rx_queues) / IGB_RETA_SIZE; 4512 adapter->rss_indir_tbl_init = num_rx_queues; 4513 } 4514 igb_write_rss_indir_tbl(adapter); 4515 4516 /* Disable raw packet checksumming so that RSS hash is placed in 4517 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4518 * offloads as they are enabled by default 4519 */ 4520 rxcsum = rd32(E1000_RXCSUM); 4521 rxcsum |= E1000_RXCSUM_PCSD; 4522 4523 if (adapter->hw.mac.type >= e1000_82576) 4524 /* Enable Receive Checksum Offload for SCTP */ 4525 rxcsum |= E1000_RXCSUM_CRCOFL; 4526 4527 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4528 wr32(E1000_RXCSUM, rxcsum); 4529 4530 /* Generate RSS hash based on packet types, TCP/UDP 4531 * port numbers and/or IPv4/v6 src and dst addresses 4532 */ 4533 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4534 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4535 E1000_MRQC_RSS_FIELD_IPV6 | 4536 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4537 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4538 4539 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4540 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4541 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4542 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4543 4544 /* If VMDq is enabled then we set the appropriate mode for that, else 4545 * we default to RSS so that an RSS hash is calculated per packet even 4546 * if we are only using one queue 4547 */ 4548 if (adapter->vfs_allocated_count) { 4549 if (hw->mac.type > e1000_82575) { 4550 /* Set the default pool for the PF's first queue */ 4551 u32 vtctl = rd32(E1000_VT_CTL); 4552 4553 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4554 E1000_VT_CTL_DISABLE_DEF_POOL); 4555 vtctl |= adapter->vfs_allocated_count << 4556 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4557 wr32(E1000_VT_CTL, vtctl); 4558 } 4559 if (adapter->rss_queues > 1) 4560 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4561 else 4562 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4563 } else { 4564 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4565 } 4566 igb_vmm_control(adapter); 4567 4568 wr32(E1000_MRQC, mrqc); 4569 } 4570 4571 /** 4572 * igb_setup_rctl - configure the receive control registers 4573 * @adapter: Board private structure 4574 **/ 4575 void igb_setup_rctl(struct igb_adapter *adapter) 4576 { 4577 struct e1000_hw *hw = &adapter->hw; 4578 u32 rctl; 4579 4580 rctl = rd32(E1000_RCTL); 4581 4582 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4583 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4584 4585 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4586 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4587 4588 /* enable stripping of CRC. It's unlikely this will break BMC 4589 * redirection as it did with e1000. Newer features require 4590 * that the HW strips the CRC. 4591 */ 4592 rctl |= E1000_RCTL_SECRC; 4593 4594 /* disable store bad packets and clear size bits. */ 4595 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4596 4597 /* enable LPE to allow for reception of jumbo frames */ 4598 rctl |= E1000_RCTL_LPE; 4599 4600 /* disable queue 0 to prevent tail write w/o re-config */ 4601 wr32(E1000_RXDCTL(0), 0); 4602 4603 /* Attention!!! For SR-IOV PF driver operations you must enable 4604 * queue drop for all VF and PF queues to prevent head of line blocking 4605 * if an un-trusted VF does not provide descriptors to hardware. 4606 */ 4607 if (adapter->vfs_allocated_count) { 4608 /* set all queue drop enable bits */ 4609 wr32(E1000_QDE, ALL_QUEUES); 4610 } 4611 4612 /* This is useful for sniffing bad packets. */ 4613 if (adapter->netdev->features & NETIF_F_RXALL) { 4614 /* UPE and MPE will be handled by normal PROMISC logic 4615 * in e1000e_set_rx_mode 4616 */ 4617 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4618 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4619 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4620 4621 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4622 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4623 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4624 * and that breaks VLANs. 4625 */ 4626 } 4627 4628 wr32(E1000_RCTL, rctl); 4629 } 4630 4631 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4632 int vfn) 4633 { 4634 struct e1000_hw *hw = &adapter->hw; 4635 u32 vmolr; 4636 4637 if (size > MAX_JUMBO_FRAME_SIZE) 4638 size = MAX_JUMBO_FRAME_SIZE; 4639 4640 vmolr = rd32(E1000_VMOLR(vfn)); 4641 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4642 vmolr |= size | E1000_VMOLR_LPE; 4643 wr32(E1000_VMOLR(vfn), vmolr); 4644 4645 return 0; 4646 } 4647 4648 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4649 int vfn, bool enable) 4650 { 4651 struct e1000_hw *hw = &adapter->hw; 4652 u32 val, reg; 4653 4654 if (hw->mac.type < e1000_82576) 4655 return; 4656 4657 if (hw->mac.type == e1000_i350) 4658 reg = E1000_DVMOLR(vfn); 4659 else 4660 reg = E1000_VMOLR(vfn); 4661 4662 val = rd32(reg); 4663 if (enable) 4664 val |= E1000_VMOLR_STRVLAN; 4665 else 4666 val &= ~(E1000_VMOLR_STRVLAN); 4667 wr32(reg, val); 4668 } 4669 4670 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4671 int vfn, bool aupe) 4672 { 4673 struct e1000_hw *hw = &adapter->hw; 4674 u32 vmolr; 4675 4676 /* This register exists only on 82576 and newer so if we are older then 4677 * we should exit and do nothing 4678 */ 4679 if (hw->mac.type < e1000_82576) 4680 return; 4681 4682 vmolr = rd32(E1000_VMOLR(vfn)); 4683 if (aupe) 4684 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4685 else 4686 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4687 4688 /* clear all bits that might not be set */ 4689 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4690 4691 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4692 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4693 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4694 * multicast packets 4695 */ 4696 if (vfn <= adapter->vfs_allocated_count) 4697 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4698 4699 wr32(E1000_VMOLR(vfn), vmolr); 4700 } 4701 4702 /** 4703 * igb_setup_srrctl - configure the split and replication receive control 4704 * registers 4705 * @adapter: Board private structure 4706 * @ring: receive ring to be configured 4707 **/ 4708 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4709 { 4710 struct e1000_hw *hw = &adapter->hw; 4711 int reg_idx = ring->reg_idx; 4712 u32 srrctl = 0; 4713 4714 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4715 if (ring_uses_large_buffer(ring)) 4716 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4717 else 4718 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4719 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4720 if (hw->mac.type >= e1000_82580) 4721 srrctl |= E1000_SRRCTL_TIMESTAMP; 4722 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4723 * queues and rx flow control is disabled 4724 */ 4725 if (adapter->vfs_allocated_count || 4726 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4727 adapter->num_rx_queues > 1)) 4728 srrctl |= E1000_SRRCTL_DROP_EN; 4729 4730 wr32(E1000_SRRCTL(reg_idx), srrctl); 4731 } 4732 4733 /** 4734 * igb_configure_rx_ring - Configure a receive ring after Reset 4735 * @adapter: board private structure 4736 * @ring: receive ring to be configured 4737 * 4738 * Configure the Rx unit of the MAC after a reset. 4739 **/ 4740 void igb_configure_rx_ring(struct igb_adapter *adapter, 4741 struct igb_ring *ring) 4742 { 4743 struct e1000_hw *hw = &adapter->hw; 4744 union e1000_adv_rx_desc *rx_desc; 4745 u64 rdba = ring->dma; 4746 int reg_idx = ring->reg_idx; 4747 u32 rxdctl = 0; 4748 4749 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4750 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4751 MEM_TYPE_PAGE_SHARED, NULL)); 4752 4753 /* disable the queue */ 4754 wr32(E1000_RXDCTL(reg_idx), 0); 4755 4756 /* Set DMA base address registers */ 4757 wr32(E1000_RDBAL(reg_idx), 4758 rdba & 0x00000000ffffffffULL); 4759 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4760 wr32(E1000_RDLEN(reg_idx), 4761 ring->count * sizeof(union e1000_adv_rx_desc)); 4762 4763 /* initialize head and tail */ 4764 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4765 wr32(E1000_RDH(reg_idx), 0); 4766 writel(0, ring->tail); 4767 4768 /* set descriptor configuration */ 4769 igb_setup_srrctl(adapter, ring); 4770 4771 /* set filtering for VMDQ pools */ 4772 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4773 4774 rxdctl |= IGB_RX_PTHRESH; 4775 rxdctl |= IGB_RX_HTHRESH << 8; 4776 rxdctl |= IGB_RX_WTHRESH << 16; 4777 4778 /* initialize rx_buffer_info */ 4779 memset(ring->rx_buffer_info, 0, 4780 sizeof(struct igb_rx_buffer) * ring->count); 4781 4782 /* initialize Rx descriptor 0 */ 4783 rx_desc = IGB_RX_DESC(ring, 0); 4784 rx_desc->wb.upper.length = 0; 4785 4786 /* enable receive descriptor fetching */ 4787 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4788 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4789 } 4790 4791 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4792 struct igb_ring *rx_ring) 4793 { 4794 #if (PAGE_SIZE < 8192) 4795 struct e1000_hw *hw = &adapter->hw; 4796 #endif 4797 4798 /* set build_skb and buffer size flags */ 4799 clear_ring_build_skb_enabled(rx_ring); 4800 clear_ring_uses_large_buffer(rx_ring); 4801 4802 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4803 return; 4804 4805 set_ring_build_skb_enabled(rx_ring); 4806 4807 #if (PAGE_SIZE < 8192) 4808 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4809 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4810 set_ring_uses_large_buffer(rx_ring); 4811 #endif 4812 } 4813 4814 /** 4815 * igb_configure_rx - Configure receive Unit after Reset 4816 * @adapter: board private structure 4817 * 4818 * Configure the Rx unit of the MAC after a reset. 4819 **/ 4820 static void igb_configure_rx(struct igb_adapter *adapter) 4821 { 4822 int i; 4823 4824 /* set the correct pool for the PF default MAC address in entry 0 */ 4825 igb_set_default_mac_filter(adapter); 4826 4827 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4828 * the Base and Length of the Rx Descriptor Ring 4829 */ 4830 for (i = 0; i < adapter->num_rx_queues; i++) { 4831 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4832 4833 igb_set_rx_buffer_len(adapter, rx_ring); 4834 igb_configure_rx_ring(adapter, rx_ring); 4835 } 4836 } 4837 4838 /** 4839 * igb_free_tx_resources - Free Tx Resources per Queue 4840 * @tx_ring: Tx descriptor ring for a specific queue 4841 * 4842 * Free all transmit software resources 4843 **/ 4844 void igb_free_tx_resources(struct igb_ring *tx_ring) 4845 { 4846 igb_clean_tx_ring(tx_ring); 4847 4848 vfree(tx_ring->tx_buffer_info); 4849 tx_ring->tx_buffer_info = NULL; 4850 4851 /* if not set, then don't free */ 4852 if (!tx_ring->desc) 4853 return; 4854 4855 dma_free_coherent(tx_ring->dev, tx_ring->size, 4856 tx_ring->desc, tx_ring->dma); 4857 4858 tx_ring->desc = NULL; 4859 } 4860 4861 /** 4862 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4863 * @adapter: board private structure 4864 * 4865 * Free all transmit software resources 4866 **/ 4867 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4868 { 4869 int i; 4870 4871 for (i = 0; i < adapter->num_tx_queues; i++) 4872 if (adapter->tx_ring[i]) 4873 igb_free_tx_resources(adapter->tx_ring[i]); 4874 } 4875 4876 /** 4877 * igb_clean_tx_ring - Free Tx Buffers 4878 * @tx_ring: ring to be cleaned 4879 **/ 4880 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4881 { 4882 u16 i = tx_ring->next_to_clean; 4883 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4884 4885 while (i != tx_ring->next_to_use) { 4886 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4887 4888 /* Free all the Tx ring sk_buffs or xdp frames */ 4889 if (tx_buffer->type == IGB_TYPE_SKB) 4890 dev_kfree_skb_any(tx_buffer->skb); 4891 else 4892 xdp_return_frame(tx_buffer->xdpf); 4893 4894 /* unmap skb header data */ 4895 dma_unmap_single(tx_ring->dev, 4896 dma_unmap_addr(tx_buffer, dma), 4897 dma_unmap_len(tx_buffer, len), 4898 DMA_TO_DEVICE); 4899 4900 /* check for eop_desc to determine the end of the packet */ 4901 eop_desc = tx_buffer->next_to_watch; 4902 tx_desc = IGB_TX_DESC(tx_ring, i); 4903 4904 /* unmap remaining buffers */ 4905 while (tx_desc != eop_desc) { 4906 tx_buffer++; 4907 tx_desc++; 4908 i++; 4909 if (unlikely(i == tx_ring->count)) { 4910 i = 0; 4911 tx_buffer = tx_ring->tx_buffer_info; 4912 tx_desc = IGB_TX_DESC(tx_ring, 0); 4913 } 4914 4915 /* unmap any remaining paged data */ 4916 if (dma_unmap_len(tx_buffer, len)) 4917 dma_unmap_page(tx_ring->dev, 4918 dma_unmap_addr(tx_buffer, dma), 4919 dma_unmap_len(tx_buffer, len), 4920 DMA_TO_DEVICE); 4921 } 4922 4923 tx_buffer->next_to_watch = NULL; 4924 4925 /* move us one more past the eop_desc for start of next pkt */ 4926 tx_buffer++; 4927 i++; 4928 if (unlikely(i == tx_ring->count)) { 4929 i = 0; 4930 tx_buffer = tx_ring->tx_buffer_info; 4931 } 4932 } 4933 4934 /* reset BQL for queue */ 4935 netdev_tx_reset_queue(txring_txq(tx_ring)); 4936 4937 /* reset next_to_use and next_to_clean */ 4938 tx_ring->next_to_use = 0; 4939 tx_ring->next_to_clean = 0; 4940 } 4941 4942 /** 4943 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4944 * @adapter: board private structure 4945 **/ 4946 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4947 { 4948 int i; 4949 4950 for (i = 0; i < adapter->num_tx_queues; i++) 4951 if (adapter->tx_ring[i]) 4952 igb_clean_tx_ring(adapter->tx_ring[i]); 4953 } 4954 4955 /** 4956 * igb_free_rx_resources - Free Rx Resources 4957 * @rx_ring: ring to clean the resources from 4958 * 4959 * Free all receive software resources 4960 **/ 4961 void igb_free_rx_resources(struct igb_ring *rx_ring) 4962 { 4963 igb_clean_rx_ring(rx_ring); 4964 4965 rx_ring->xdp_prog = NULL; 4966 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4967 vfree(rx_ring->rx_buffer_info); 4968 rx_ring->rx_buffer_info = NULL; 4969 4970 /* if not set, then don't free */ 4971 if (!rx_ring->desc) 4972 return; 4973 4974 dma_free_coherent(rx_ring->dev, rx_ring->size, 4975 rx_ring->desc, rx_ring->dma); 4976 4977 rx_ring->desc = NULL; 4978 } 4979 4980 /** 4981 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4982 * @adapter: board private structure 4983 * 4984 * Free all receive software resources 4985 **/ 4986 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4987 { 4988 int i; 4989 4990 for (i = 0; i < adapter->num_rx_queues; i++) 4991 if (adapter->rx_ring[i]) 4992 igb_free_rx_resources(adapter->rx_ring[i]); 4993 } 4994 4995 /** 4996 * igb_clean_rx_ring - Free Rx Buffers per Queue 4997 * @rx_ring: ring to free buffers from 4998 **/ 4999 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5000 { 5001 u16 i = rx_ring->next_to_clean; 5002 5003 dev_kfree_skb(rx_ring->skb); 5004 rx_ring->skb = NULL; 5005 5006 /* Free all the Rx ring sk_buffs */ 5007 while (i != rx_ring->next_to_alloc) { 5008 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5009 5010 /* Invalidate cache lines that may have been written to by 5011 * device so that we avoid corrupting memory. 5012 */ 5013 dma_sync_single_range_for_cpu(rx_ring->dev, 5014 buffer_info->dma, 5015 buffer_info->page_offset, 5016 igb_rx_bufsz(rx_ring), 5017 DMA_FROM_DEVICE); 5018 5019 /* free resources associated with mapping */ 5020 dma_unmap_page_attrs(rx_ring->dev, 5021 buffer_info->dma, 5022 igb_rx_pg_size(rx_ring), 5023 DMA_FROM_DEVICE, 5024 IGB_RX_DMA_ATTR); 5025 __page_frag_cache_drain(buffer_info->page, 5026 buffer_info->pagecnt_bias); 5027 5028 i++; 5029 if (i == rx_ring->count) 5030 i = 0; 5031 } 5032 5033 rx_ring->next_to_alloc = 0; 5034 rx_ring->next_to_clean = 0; 5035 rx_ring->next_to_use = 0; 5036 } 5037 5038 /** 5039 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5040 * @adapter: board private structure 5041 **/ 5042 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5043 { 5044 int i; 5045 5046 for (i = 0; i < adapter->num_rx_queues; i++) 5047 if (adapter->rx_ring[i]) 5048 igb_clean_rx_ring(adapter->rx_ring[i]); 5049 } 5050 5051 /** 5052 * igb_set_mac - Change the Ethernet Address of the NIC 5053 * @netdev: network interface device structure 5054 * @p: pointer to an address structure 5055 * 5056 * Returns 0 on success, negative on failure 5057 **/ 5058 static int igb_set_mac(struct net_device *netdev, void *p) 5059 { 5060 struct igb_adapter *adapter = netdev_priv(netdev); 5061 struct e1000_hw *hw = &adapter->hw; 5062 struct sockaddr *addr = p; 5063 5064 if (!is_valid_ether_addr(addr->sa_data)) 5065 return -EADDRNOTAVAIL; 5066 5067 eth_hw_addr_set(netdev, addr->sa_data); 5068 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5069 5070 /* set the correct pool for the new PF MAC address in entry 0 */ 5071 igb_set_default_mac_filter(adapter); 5072 5073 return 0; 5074 } 5075 5076 /** 5077 * igb_write_mc_addr_list - write multicast addresses to MTA 5078 * @netdev: network interface device structure 5079 * 5080 * Writes multicast address list to the MTA hash table. 5081 * Returns: -ENOMEM on failure 5082 * 0 on no addresses written 5083 * X on writing X addresses to MTA 5084 **/ 5085 static int igb_write_mc_addr_list(struct net_device *netdev) 5086 { 5087 struct igb_adapter *adapter = netdev_priv(netdev); 5088 struct e1000_hw *hw = &adapter->hw; 5089 struct netdev_hw_addr *ha; 5090 u8 *mta_list; 5091 int i; 5092 5093 if (netdev_mc_empty(netdev)) { 5094 /* nothing to program, so clear mc list */ 5095 igb_update_mc_addr_list(hw, NULL, 0); 5096 igb_restore_vf_multicasts(adapter); 5097 return 0; 5098 } 5099 5100 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5101 if (!mta_list) 5102 return -ENOMEM; 5103 5104 /* The shared function expects a packed array of only addresses. */ 5105 i = 0; 5106 netdev_for_each_mc_addr(ha, netdev) 5107 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5108 5109 igb_update_mc_addr_list(hw, mta_list, i); 5110 kfree(mta_list); 5111 5112 return netdev_mc_count(netdev); 5113 } 5114 5115 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5116 { 5117 struct e1000_hw *hw = &adapter->hw; 5118 u32 i, pf_id; 5119 5120 switch (hw->mac.type) { 5121 case e1000_i210: 5122 case e1000_i211: 5123 case e1000_i350: 5124 /* VLAN filtering needed for VLAN prio filter */ 5125 if (adapter->netdev->features & NETIF_F_NTUPLE) 5126 break; 5127 fallthrough; 5128 case e1000_82576: 5129 case e1000_82580: 5130 case e1000_i354: 5131 /* VLAN filtering needed for pool filtering */ 5132 if (adapter->vfs_allocated_count) 5133 break; 5134 fallthrough; 5135 default: 5136 return 1; 5137 } 5138 5139 /* We are already in VLAN promisc, nothing to do */ 5140 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5141 return 0; 5142 5143 if (!adapter->vfs_allocated_count) 5144 goto set_vfta; 5145 5146 /* Add PF to all active pools */ 5147 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5148 5149 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5150 u32 vlvf = rd32(E1000_VLVF(i)); 5151 5152 vlvf |= BIT(pf_id); 5153 wr32(E1000_VLVF(i), vlvf); 5154 } 5155 5156 set_vfta: 5157 /* Set all bits in the VLAN filter table array */ 5158 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5159 hw->mac.ops.write_vfta(hw, i, ~0U); 5160 5161 /* Set flag so we don't redo unnecessary work */ 5162 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5163 5164 return 0; 5165 } 5166 5167 #define VFTA_BLOCK_SIZE 8 5168 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5169 { 5170 struct e1000_hw *hw = &adapter->hw; 5171 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5172 u32 vid_start = vfta_offset * 32; 5173 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5174 u32 i, vid, word, bits, pf_id; 5175 5176 /* guarantee that we don't scrub out management VLAN */ 5177 vid = adapter->mng_vlan_id; 5178 if (vid >= vid_start && vid < vid_end) 5179 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5180 5181 if (!adapter->vfs_allocated_count) 5182 goto set_vfta; 5183 5184 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5185 5186 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5187 u32 vlvf = rd32(E1000_VLVF(i)); 5188 5189 /* pull VLAN ID from VLVF */ 5190 vid = vlvf & VLAN_VID_MASK; 5191 5192 /* only concern ourselves with a certain range */ 5193 if (vid < vid_start || vid >= vid_end) 5194 continue; 5195 5196 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5197 /* record VLAN ID in VFTA */ 5198 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5199 5200 /* if PF is part of this then continue */ 5201 if (test_bit(vid, adapter->active_vlans)) 5202 continue; 5203 } 5204 5205 /* remove PF from the pool */ 5206 bits = ~BIT(pf_id); 5207 bits &= rd32(E1000_VLVF(i)); 5208 wr32(E1000_VLVF(i), bits); 5209 } 5210 5211 set_vfta: 5212 /* extract values from active_vlans and write back to VFTA */ 5213 for (i = VFTA_BLOCK_SIZE; i--;) { 5214 vid = (vfta_offset + i) * 32; 5215 word = vid / BITS_PER_LONG; 5216 bits = vid % BITS_PER_LONG; 5217 5218 vfta[i] |= adapter->active_vlans[word] >> bits; 5219 5220 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5221 } 5222 } 5223 5224 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5225 { 5226 u32 i; 5227 5228 /* We are not in VLAN promisc, nothing to do */ 5229 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5230 return; 5231 5232 /* Set flag so we don't redo unnecessary work */ 5233 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5234 5235 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5236 igb_scrub_vfta(adapter, i); 5237 } 5238 5239 /** 5240 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5241 * @netdev: network interface device structure 5242 * 5243 * The set_rx_mode entry point is called whenever the unicast or multicast 5244 * address lists or the network interface flags are updated. This routine is 5245 * responsible for configuring the hardware for proper unicast, multicast, 5246 * promiscuous mode, and all-multi behavior. 5247 **/ 5248 static void igb_set_rx_mode(struct net_device *netdev) 5249 { 5250 struct igb_adapter *adapter = netdev_priv(netdev); 5251 struct e1000_hw *hw = &adapter->hw; 5252 unsigned int vfn = adapter->vfs_allocated_count; 5253 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5254 int count; 5255 5256 /* Check for Promiscuous and All Multicast modes */ 5257 if (netdev->flags & IFF_PROMISC) { 5258 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5259 vmolr |= E1000_VMOLR_MPME; 5260 5261 /* enable use of UTA filter to force packets to default pool */ 5262 if (hw->mac.type == e1000_82576) 5263 vmolr |= E1000_VMOLR_ROPE; 5264 } else { 5265 if (netdev->flags & IFF_ALLMULTI) { 5266 rctl |= E1000_RCTL_MPE; 5267 vmolr |= E1000_VMOLR_MPME; 5268 } else { 5269 /* Write addresses to the MTA, if the attempt fails 5270 * then we should just turn on promiscuous mode so 5271 * that we can at least receive multicast traffic 5272 */ 5273 count = igb_write_mc_addr_list(netdev); 5274 if (count < 0) { 5275 rctl |= E1000_RCTL_MPE; 5276 vmolr |= E1000_VMOLR_MPME; 5277 } else if (count) { 5278 vmolr |= E1000_VMOLR_ROMPE; 5279 } 5280 } 5281 } 5282 5283 /* Write addresses to available RAR registers, if there is not 5284 * sufficient space to store all the addresses then enable 5285 * unicast promiscuous mode 5286 */ 5287 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5288 rctl |= E1000_RCTL_UPE; 5289 vmolr |= E1000_VMOLR_ROPE; 5290 } 5291 5292 /* enable VLAN filtering by default */ 5293 rctl |= E1000_RCTL_VFE; 5294 5295 /* disable VLAN filtering for modes that require it */ 5296 if ((netdev->flags & IFF_PROMISC) || 5297 (netdev->features & NETIF_F_RXALL)) { 5298 /* if we fail to set all rules then just clear VFE */ 5299 if (igb_vlan_promisc_enable(adapter)) 5300 rctl &= ~E1000_RCTL_VFE; 5301 } else { 5302 igb_vlan_promisc_disable(adapter); 5303 } 5304 5305 /* update state of unicast, multicast, and VLAN filtering modes */ 5306 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5307 E1000_RCTL_VFE); 5308 wr32(E1000_RCTL, rctl); 5309 5310 #if (PAGE_SIZE < 8192) 5311 if (!adapter->vfs_allocated_count) { 5312 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5313 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5314 } 5315 #endif 5316 wr32(E1000_RLPML, rlpml); 5317 5318 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5319 * the VMOLR to enable the appropriate modes. Without this workaround 5320 * we will have issues with VLAN tag stripping not being done for frames 5321 * that are only arriving because we are the default pool 5322 */ 5323 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5324 return; 5325 5326 /* set UTA to appropriate mode */ 5327 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5328 5329 vmolr |= rd32(E1000_VMOLR(vfn)) & 5330 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5331 5332 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5333 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5334 #if (PAGE_SIZE < 8192) 5335 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5336 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5337 else 5338 #endif 5339 vmolr |= MAX_JUMBO_FRAME_SIZE; 5340 vmolr |= E1000_VMOLR_LPE; 5341 5342 wr32(E1000_VMOLR(vfn), vmolr); 5343 5344 igb_restore_vf_multicasts(adapter); 5345 } 5346 5347 static void igb_check_wvbr(struct igb_adapter *adapter) 5348 { 5349 struct e1000_hw *hw = &adapter->hw; 5350 u32 wvbr = 0; 5351 5352 switch (hw->mac.type) { 5353 case e1000_82576: 5354 case e1000_i350: 5355 wvbr = rd32(E1000_WVBR); 5356 if (!wvbr) 5357 return; 5358 break; 5359 default: 5360 break; 5361 } 5362 5363 adapter->wvbr |= wvbr; 5364 } 5365 5366 #define IGB_STAGGERED_QUEUE_OFFSET 8 5367 5368 static void igb_spoof_check(struct igb_adapter *adapter) 5369 { 5370 int j; 5371 5372 if (!adapter->wvbr) 5373 return; 5374 5375 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5376 if (adapter->wvbr & BIT(j) || 5377 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5378 dev_warn(&adapter->pdev->dev, 5379 "Spoof event(s) detected on VF %d\n", j); 5380 adapter->wvbr &= 5381 ~(BIT(j) | 5382 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5383 } 5384 } 5385 } 5386 5387 /* Need to wait a few seconds after link up to get diagnostic information from 5388 * the phy 5389 */ 5390 static void igb_update_phy_info(struct timer_list *t) 5391 { 5392 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5393 igb_get_phy_info(&adapter->hw); 5394 } 5395 5396 /** 5397 * igb_has_link - check shared code for link and determine up/down 5398 * @adapter: pointer to driver private info 5399 **/ 5400 bool igb_has_link(struct igb_adapter *adapter) 5401 { 5402 struct e1000_hw *hw = &adapter->hw; 5403 bool link_active = false; 5404 5405 /* get_link_status is set on LSC (link status) interrupt or 5406 * rx sequence error interrupt. get_link_status will stay 5407 * false until the e1000_check_for_link establishes link 5408 * for copper adapters ONLY 5409 */ 5410 switch (hw->phy.media_type) { 5411 case e1000_media_type_copper: 5412 if (!hw->mac.get_link_status) 5413 return true; 5414 fallthrough; 5415 case e1000_media_type_internal_serdes: 5416 hw->mac.ops.check_for_link(hw); 5417 link_active = !hw->mac.get_link_status; 5418 break; 5419 default: 5420 case e1000_media_type_unknown: 5421 break; 5422 } 5423 5424 if (((hw->mac.type == e1000_i210) || 5425 (hw->mac.type == e1000_i211)) && 5426 (hw->phy.id == I210_I_PHY_ID)) { 5427 if (!netif_carrier_ok(adapter->netdev)) { 5428 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5429 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5430 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5431 adapter->link_check_timeout = jiffies; 5432 } 5433 } 5434 5435 return link_active; 5436 } 5437 5438 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5439 { 5440 bool ret = false; 5441 u32 ctrl_ext, thstat; 5442 5443 /* check for thermal sensor event on i350 copper only */ 5444 if (hw->mac.type == e1000_i350) { 5445 thstat = rd32(E1000_THSTAT); 5446 ctrl_ext = rd32(E1000_CTRL_EXT); 5447 5448 if ((hw->phy.media_type == e1000_media_type_copper) && 5449 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5450 ret = !!(thstat & event); 5451 } 5452 5453 return ret; 5454 } 5455 5456 /** 5457 * igb_check_lvmmc - check for malformed packets received 5458 * and indicated in LVMMC register 5459 * @adapter: pointer to adapter 5460 **/ 5461 static void igb_check_lvmmc(struct igb_adapter *adapter) 5462 { 5463 struct e1000_hw *hw = &adapter->hw; 5464 u32 lvmmc; 5465 5466 lvmmc = rd32(E1000_LVMMC); 5467 if (lvmmc) { 5468 if (unlikely(net_ratelimit())) { 5469 netdev_warn(adapter->netdev, 5470 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5471 lvmmc); 5472 } 5473 } 5474 } 5475 5476 /** 5477 * igb_watchdog - Timer Call-back 5478 * @t: pointer to timer_list containing our private info pointer 5479 **/ 5480 static void igb_watchdog(struct timer_list *t) 5481 { 5482 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5483 /* Do the rest outside of interrupt context */ 5484 schedule_work(&adapter->watchdog_task); 5485 } 5486 5487 static void igb_watchdog_task(struct work_struct *work) 5488 { 5489 struct igb_adapter *adapter = container_of(work, 5490 struct igb_adapter, 5491 watchdog_task); 5492 struct e1000_hw *hw = &adapter->hw; 5493 struct e1000_phy_info *phy = &hw->phy; 5494 struct net_device *netdev = adapter->netdev; 5495 u32 link; 5496 int i; 5497 u32 connsw; 5498 u16 phy_data, retry_count = 20; 5499 5500 link = igb_has_link(adapter); 5501 5502 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5503 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5504 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5505 else 5506 link = false; 5507 } 5508 5509 /* Force link down if we have fiber to swap to */ 5510 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5511 if (hw->phy.media_type == e1000_media_type_copper) { 5512 connsw = rd32(E1000_CONNSW); 5513 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5514 link = 0; 5515 } 5516 } 5517 if (link) { 5518 /* Perform a reset if the media type changed. */ 5519 if (hw->dev_spec._82575.media_changed) { 5520 hw->dev_spec._82575.media_changed = false; 5521 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5522 igb_reset(adapter); 5523 } 5524 /* Cancel scheduled suspend requests. */ 5525 pm_runtime_resume(netdev->dev.parent); 5526 5527 if (!netif_carrier_ok(netdev)) { 5528 u32 ctrl; 5529 5530 hw->mac.ops.get_speed_and_duplex(hw, 5531 &adapter->link_speed, 5532 &adapter->link_duplex); 5533 5534 ctrl = rd32(E1000_CTRL); 5535 /* Links status message must follow this format */ 5536 netdev_info(netdev, 5537 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5538 netdev->name, 5539 adapter->link_speed, 5540 adapter->link_duplex == FULL_DUPLEX ? 5541 "Full" : "Half", 5542 (ctrl & E1000_CTRL_TFCE) && 5543 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5544 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5545 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5546 5547 /* disable EEE if enabled */ 5548 if ((adapter->flags & IGB_FLAG_EEE) && 5549 (adapter->link_duplex == HALF_DUPLEX)) { 5550 dev_info(&adapter->pdev->dev, 5551 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5552 adapter->hw.dev_spec._82575.eee_disable = true; 5553 adapter->flags &= ~IGB_FLAG_EEE; 5554 } 5555 5556 /* check if SmartSpeed worked */ 5557 igb_check_downshift(hw); 5558 if (phy->speed_downgraded) 5559 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5560 5561 /* check for thermal sensor event */ 5562 if (igb_thermal_sensor_event(hw, 5563 E1000_THSTAT_LINK_THROTTLE)) 5564 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5565 5566 /* adjust timeout factor according to speed/duplex */ 5567 adapter->tx_timeout_factor = 1; 5568 switch (adapter->link_speed) { 5569 case SPEED_10: 5570 adapter->tx_timeout_factor = 14; 5571 break; 5572 case SPEED_100: 5573 /* maybe add some timeout factor ? */ 5574 break; 5575 } 5576 5577 if (adapter->link_speed != SPEED_1000 || 5578 !hw->phy.ops.read_reg) 5579 goto no_wait; 5580 5581 /* wait for Remote receiver status OK */ 5582 retry_read_status: 5583 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5584 &phy_data)) { 5585 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5586 retry_count) { 5587 msleep(100); 5588 retry_count--; 5589 goto retry_read_status; 5590 } else if (!retry_count) { 5591 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5592 } 5593 } else { 5594 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5595 } 5596 no_wait: 5597 netif_carrier_on(netdev); 5598 5599 igb_ping_all_vfs(adapter); 5600 igb_check_vf_rate_limit(adapter); 5601 5602 /* link state has changed, schedule phy info update */ 5603 if (!test_bit(__IGB_DOWN, &adapter->state)) 5604 mod_timer(&adapter->phy_info_timer, 5605 round_jiffies(jiffies + 2 * HZ)); 5606 } 5607 } else { 5608 if (netif_carrier_ok(netdev)) { 5609 adapter->link_speed = 0; 5610 adapter->link_duplex = 0; 5611 5612 /* check for thermal sensor event */ 5613 if (igb_thermal_sensor_event(hw, 5614 E1000_THSTAT_PWR_DOWN)) { 5615 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5616 } 5617 5618 /* Links status message must follow this format */ 5619 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5620 netdev->name); 5621 netif_carrier_off(netdev); 5622 5623 igb_ping_all_vfs(adapter); 5624 5625 /* link state has changed, schedule phy info update */ 5626 if (!test_bit(__IGB_DOWN, &adapter->state)) 5627 mod_timer(&adapter->phy_info_timer, 5628 round_jiffies(jiffies + 2 * HZ)); 5629 5630 /* link is down, time to check for alternate media */ 5631 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5632 igb_check_swap_media(adapter); 5633 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5634 schedule_work(&adapter->reset_task); 5635 /* return immediately */ 5636 return; 5637 } 5638 } 5639 pm_schedule_suspend(netdev->dev.parent, 5640 MSEC_PER_SEC * 5); 5641 5642 /* also check for alternate media here */ 5643 } else if (!netif_carrier_ok(netdev) && 5644 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5645 igb_check_swap_media(adapter); 5646 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5647 schedule_work(&adapter->reset_task); 5648 /* return immediately */ 5649 return; 5650 } 5651 } 5652 } 5653 5654 spin_lock(&adapter->stats64_lock); 5655 igb_update_stats(adapter); 5656 spin_unlock(&adapter->stats64_lock); 5657 5658 for (i = 0; i < adapter->num_tx_queues; i++) { 5659 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5660 if (!netif_carrier_ok(netdev)) { 5661 /* We've lost link, so the controller stops DMA, 5662 * but we've got queued Tx work that's never going 5663 * to get done, so reset controller to flush Tx. 5664 * (Do the reset outside of interrupt context). 5665 */ 5666 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5667 adapter->tx_timeout_count++; 5668 schedule_work(&adapter->reset_task); 5669 /* return immediately since reset is imminent */ 5670 return; 5671 } 5672 } 5673 5674 /* Force detection of hung controller every watchdog period */ 5675 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5676 } 5677 5678 /* Cause software interrupt to ensure Rx ring is cleaned */ 5679 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5680 u32 eics = 0; 5681 5682 for (i = 0; i < adapter->num_q_vectors; i++) 5683 eics |= adapter->q_vector[i]->eims_value; 5684 wr32(E1000_EICS, eics); 5685 } else { 5686 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5687 } 5688 5689 igb_spoof_check(adapter); 5690 igb_ptp_rx_hang(adapter); 5691 igb_ptp_tx_hang(adapter); 5692 5693 /* Check LVMMC register on i350/i354 only */ 5694 if ((adapter->hw.mac.type == e1000_i350) || 5695 (adapter->hw.mac.type == e1000_i354)) 5696 igb_check_lvmmc(adapter); 5697 5698 /* Reset the timer */ 5699 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5700 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5701 mod_timer(&adapter->watchdog_timer, 5702 round_jiffies(jiffies + HZ)); 5703 else 5704 mod_timer(&adapter->watchdog_timer, 5705 round_jiffies(jiffies + 2 * HZ)); 5706 } 5707 } 5708 5709 enum latency_range { 5710 lowest_latency = 0, 5711 low_latency = 1, 5712 bulk_latency = 2, 5713 latency_invalid = 255 5714 }; 5715 5716 /** 5717 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5718 * @q_vector: pointer to q_vector 5719 * 5720 * Stores a new ITR value based on strictly on packet size. This 5721 * algorithm is less sophisticated than that used in igb_update_itr, 5722 * due to the difficulty of synchronizing statistics across multiple 5723 * receive rings. The divisors and thresholds used by this function 5724 * were determined based on theoretical maximum wire speed and testing 5725 * data, in order to minimize response time while increasing bulk 5726 * throughput. 5727 * This functionality is controlled by ethtool's coalescing settings. 5728 * NOTE: This function is called only when operating in a multiqueue 5729 * receive environment. 5730 **/ 5731 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5732 { 5733 int new_val = q_vector->itr_val; 5734 int avg_wire_size = 0; 5735 struct igb_adapter *adapter = q_vector->adapter; 5736 unsigned int packets; 5737 5738 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5739 * ints/sec - ITR timer value of 120 ticks. 5740 */ 5741 if (adapter->link_speed != SPEED_1000) { 5742 new_val = IGB_4K_ITR; 5743 goto set_itr_val; 5744 } 5745 5746 packets = q_vector->rx.total_packets; 5747 if (packets) 5748 avg_wire_size = q_vector->rx.total_bytes / packets; 5749 5750 packets = q_vector->tx.total_packets; 5751 if (packets) 5752 avg_wire_size = max_t(u32, avg_wire_size, 5753 q_vector->tx.total_bytes / packets); 5754 5755 /* if avg_wire_size isn't set no work was done */ 5756 if (!avg_wire_size) 5757 goto clear_counts; 5758 5759 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5760 avg_wire_size += 24; 5761 5762 /* Don't starve jumbo frames */ 5763 avg_wire_size = min(avg_wire_size, 3000); 5764 5765 /* Give a little boost to mid-size frames */ 5766 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5767 new_val = avg_wire_size / 3; 5768 else 5769 new_val = avg_wire_size / 2; 5770 5771 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5772 if (new_val < IGB_20K_ITR && 5773 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5774 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5775 new_val = IGB_20K_ITR; 5776 5777 set_itr_val: 5778 if (new_val != q_vector->itr_val) { 5779 q_vector->itr_val = new_val; 5780 q_vector->set_itr = 1; 5781 } 5782 clear_counts: 5783 q_vector->rx.total_bytes = 0; 5784 q_vector->rx.total_packets = 0; 5785 q_vector->tx.total_bytes = 0; 5786 q_vector->tx.total_packets = 0; 5787 } 5788 5789 /** 5790 * igb_update_itr - update the dynamic ITR value based on statistics 5791 * @q_vector: pointer to q_vector 5792 * @ring_container: ring info to update the itr for 5793 * 5794 * Stores a new ITR value based on packets and byte 5795 * counts during the last interrupt. The advantage of per interrupt 5796 * computation is faster updates and more accurate ITR for the current 5797 * traffic pattern. Constants in this function were computed 5798 * based on theoretical maximum wire speed and thresholds were set based 5799 * on testing data as well as attempting to minimize response time 5800 * while increasing bulk throughput. 5801 * This functionality is controlled by ethtool's coalescing settings. 5802 * NOTE: These calculations are only valid when operating in a single- 5803 * queue environment. 5804 **/ 5805 static void igb_update_itr(struct igb_q_vector *q_vector, 5806 struct igb_ring_container *ring_container) 5807 { 5808 unsigned int packets = ring_container->total_packets; 5809 unsigned int bytes = ring_container->total_bytes; 5810 u8 itrval = ring_container->itr; 5811 5812 /* no packets, exit with status unchanged */ 5813 if (packets == 0) 5814 return; 5815 5816 switch (itrval) { 5817 case lowest_latency: 5818 /* handle TSO and jumbo frames */ 5819 if (bytes/packets > 8000) 5820 itrval = bulk_latency; 5821 else if ((packets < 5) && (bytes > 512)) 5822 itrval = low_latency; 5823 break; 5824 case low_latency: /* 50 usec aka 20000 ints/s */ 5825 if (bytes > 10000) { 5826 /* this if handles the TSO accounting */ 5827 if (bytes/packets > 8000) 5828 itrval = bulk_latency; 5829 else if ((packets < 10) || ((bytes/packets) > 1200)) 5830 itrval = bulk_latency; 5831 else if ((packets > 35)) 5832 itrval = lowest_latency; 5833 } else if (bytes/packets > 2000) { 5834 itrval = bulk_latency; 5835 } else if (packets <= 2 && bytes < 512) { 5836 itrval = lowest_latency; 5837 } 5838 break; 5839 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5840 if (bytes > 25000) { 5841 if (packets > 35) 5842 itrval = low_latency; 5843 } else if (bytes < 1500) { 5844 itrval = low_latency; 5845 } 5846 break; 5847 } 5848 5849 /* clear work counters since we have the values we need */ 5850 ring_container->total_bytes = 0; 5851 ring_container->total_packets = 0; 5852 5853 /* write updated itr to ring container */ 5854 ring_container->itr = itrval; 5855 } 5856 5857 static void igb_set_itr(struct igb_q_vector *q_vector) 5858 { 5859 struct igb_adapter *adapter = q_vector->adapter; 5860 u32 new_itr = q_vector->itr_val; 5861 u8 current_itr = 0; 5862 5863 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5864 if (adapter->link_speed != SPEED_1000) { 5865 current_itr = 0; 5866 new_itr = IGB_4K_ITR; 5867 goto set_itr_now; 5868 } 5869 5870 igb_update_itr(q_vector, &q_vector->tx); 5871 igb_update_itr(q_vector, &q_vector->rx); 5872 5873 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5874 5875 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5876 if (current_itr == lowest_latency && 5877 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5878 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5879 current_itr = low_latency; 5880 5881 switch (current_itr) { 5882 /* counts and packets in update_itr are dependent on these numbers */ 5883 case lowest_latency: 5884 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5885 break; 5886 case low_latency: 5887 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5888 break; 5889 case bulk_latency: 5890 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5891 break; 5892 default: 5893 break; 5894 } 5895 5896 set_itr_now: 5897 if (new_itr != q_vector->itr_val) { 5898 /* this attempts to bias the interrupt rate towards Bulk 5899 * by adding intermediate steps when interrupt rate is 5900 * increasing 5901 */ 5902 new_itr = new_itr > q_vector->itr_val ? 5903 max((new_itr * q_vector->itr_val) / 5904 (new_itr + (q_vector->itr_val >> 2)), 5905 new_itr) : new_itr; 5906 /* Don't write the value here; it resets the adapter's 5907 * internal timer, and causes us to delay far longer than 5908 * we should between interrupts. Instead, we write the ITR 5909 * value at the beginning of the next interrupt so the timing 5910 * ends up being correct. 5911 */ 5912 q_vector->itr_val = new_itr; 5913 q_vector->set_itr = 1; 5914 } 5915 } 5916 5917 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5918 struct igb_tx_buffer *first, 5919 u32 vlan_macip_lens, u32 type_tucmd, 5920 u32 mss_l4len_idx) 5921 { 5922 struct e1000_adv_tx_context_desc *context_desc; 5923 u16 i = tx_ring->next_to_use; 5924 struct timespec64 ts; 5925 5926 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5927 5928 i++; 5929 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5930 5931 /* set bits to identify this as an advanced context descriptor */ 5932 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5933 5934 /* For 82575, context index must be unique per ring. */ 5935 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5936 mss_l4len_idx |= tx_ring->reg_idx << 4; 5937 5938 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5939 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5940 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5941 5942 /* We assume there is always a valid tx time available. Invalid times 5943 * should have been handled by the upper layers. 5944 */ 5945 if (tx_ring->launchtime_enable) { 5946 ts = ktime_to_timespec64(first->skb->tstamp); 5947 skb_txtime_consumed(first->skb); 5948 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5949 } else { 5950 context_desc->seqnum_seed = 0; 5951 } 5952 } 5953 5954 static int igb_tso(struct igb_ring *tx_ring, 5955 struct igb_tx_buffer *first, 5956 u8 *hdr_len) 5957 { 5958 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5959 struct sk_buff *skb = first->skb; 5960 union { 5961 struct iphdr *v4; 5962 struct ipv6hdr *v6; 5963 unsigned char *hdr; 5964 } ip; 5965 union { 5966 struct tcphdr *tcp; 5967 struct udphdr *udp; 5968 unsigned char *hdr; 5969 } l4; 5970 u32 paylen, l4_offset; 5971 int err; 5972 5973 if (skb->ip_summed != CHECKSUM_PARTIAL) 5974 return 0; 5975 5976 if (!skb_is_gso(skb)) 5977 return 0; 5978 5979 err = skb_cow_head(skb, 0); 5980 if (err < 0) 5981 return err; 5982 5983 ip.hdr = skb_network_header(skb); 5984 l4.hdr = skb_checksum_start(skb); 5985 5986 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5987 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5988 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5989 5990 /* initialize outer IP header fields */ 5991 if (ip.v4->version == 4) { 5992 unsigned char *csum_start = skb_checksum_start(skb); 5993 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5994 5995 /* IP header will have to cancel out any data that 5996 * is not a part of the outer IP header 5997 */ 5998 ip.v4->check = csum_fold(csum_partial(trans_start, 5999 csum_start - trans_start, 6000 0)); 6001 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6002 6003 ip.v4->tot_len = 0; 6004 first->tx_flags |= IGB_TX_FLAGS_TSO | 6005 IGB_TX_FLAGS_CSUM | 6006 IGB_TX_FLAGS_IPV4; 6007 } else { 6008 ip.v6->payload_len = 0; 6009 first->tx_flags |= IGB_TX_FLAGS_TSO | 6010 IGB_TX_FLAGS_CSUM; 6011 } 6012 6013 /* determine offset of inner transport header */ 6014 l4_offset = l4.hdr - skb->data; 6015 6016 /* remove payload length from inner checksum */ 6017 paylen = skb->len - l4_offset; 6018 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6019 /* compute length of segmentation header */ 6020 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6021 csum_replace_by_diff(&l4.tcp->check, 6022 (__force __wsum)htonl(paylen)); 6023 } else { 6024 /* compute length of segmentation header */ 6025 *hdr_len = sizeof(*l4.udp) + l4_offset; 6026 csum_replace_by_diff(&l4.udp->check, 6027 (__force __wsum)htonl(paylen)); 6028 } 6029 6030 /* update gso size and bytecount with header size */ 6031 first->gso_segs = skb_shinfo(skb)->gso_segs; 6032 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6033 6034 /* MSS L4LEN IDX */ 6035 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6036 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6037 6038 /* VLAN MACLEN IPLEN */ 6039 vlan_macip_lens = l4.hdr - ip.hdr; 6040 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6041 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6042 6043 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6044 type_tucmd, mss_l4len_idx); 6045 6046 return 1; 6047 } 6048 6049 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6050 { 6051 struct sk_buff *skb = first->skb; 6052 u32 vlan_macip_lens = 0; 6053 u32 type_tucmd = 0; 6054 6055 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6056 csum_failed: 6057 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6058 !tx_ring->launchtime_enable) 6059 return; 6060 goto no_csum; 6061 } 6062 6063 switch (skb->csum_offset) { 6064 case offsetof(struct tcphdr, check): 6065 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6066 fallthrough; 6067 case offsetof(struct udphdr, check): 6068 break; 6069 case offsetof(struct sctphdr, checksum): 6070 /* validate that this is actually an SCTP request */ 6071 if (skb_csum_is_sctp(skb)) { 6072 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6073 break; 6074 } 6075 fallthrough; 6076 default: 6077 skb_checksum_help(skb); 6078 goto csum_failed; 6079 } 6080 6081 /* update TX checksum flag */ 6082 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6083 vlan_macip_lens = skb_checksum_start_offset(skb) - 6084 skb_network_offset(skb); 6085 no_csum: 6086 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6087 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6088 6089 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6090 } 6091 6092 #define IGB_SET_FLAG(_input, _flag, _result) \ 6093 ((_flag <= _result) ? \ 6094 ((u32)(_input & _flag) * (_result / _flag)) : \ 6095 ((u32)(_input & _flag) / (_flag / _result))) 6096 6097 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6098 { 6099 /* set type for advanced descriptor with frame checksum insertion */ 6100 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6101 E1000_ADVTXD_DCMD_DEXT | 6102 E1000_ADVTXD_DCMD_IFCS; 6103 6104 /* set HW vlan bit if vlan is present */ 6105 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6106 (E1000_ADVTXD_DCMD_VLE)); 6107 6108 /* set segmentation bits for TSO */ 6109 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6110 (E1000_ADVTXD_DCMD_TSE)); 6111 6112 /* set timestamp bit if present */ 6113 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6114 (E1000_ADVTXD_MAC_TSTAMP)); 6115 6116 /* insert frame checksum */ 6117 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6118 6119 return cmd_type; 6120 } 6121 6122 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6123 union e1000_adv_tx_desc *tx_desc, 6124 u32 tx_flags, unsigned int paylen) 6125 { 6126 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6127 6128 /* 82575 requires a unique index per ring */ 6129 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6130 olinfo_status |= tx_ring->reg_idx << 4; 6131 6132 /* insert L4 checksum */ 6133 olinfo_status |= IGB_SET_FLAG(tx_flags, 6134 IGB_TX_FLAGS_CSUM, 6135 (E1000_TXD_POPTS_TXSM << 8)); 6136 6137 /* insert IPv4 checksum */ 6138 olinfo_status |= IGB_SET_FLAG(tx_flags, 6139 IGB_TX_FLAGS_IPV4, 6140 (E1000_TXD_POPTS_IXSM << 8)); 6141 6142 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6143 } 6144 6145 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6146 { 6147 struct net_device *netdev = tx_ring->netdev; 6148 6149 netif_stop_subqueue(netdev, tx_ring->queue_index); 6150 6151 /* Herbert's original patch had: 6152 * smp_mb__after_netif_stop_queue(); 6153 * but since that doesn't exist yet, just open code it. 6154 */ 6155 smp_mb(); 6156 6157 /* We need to check again in a case another CPU has just 6158 * made room available. 6159 */ 6160 if (igb_desc_unused(tx_ring) < size) 6161 return -EBUSY; 6162 6163 /* A reprieve! */ 6164 netif_wake_subqueue(netdev, tx_ring->queue_index); 6165 6166 u64_stats_update_begin(&tx_ring->tx_syncp2); 6167 tx_ring->tx_stats.restart_queue2++; 6168 u64_stats_update_end(&tx_ring->tx_syncp2); 6169 6170 return 0; 6171 } 6172 6173 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6174 { 6175 if (igb_desc_unused(tx_ring) >= size) 6176 return 0; 6177 return __igb_maybe_stop_tx(tx_ring, size); 6178 } 6179 6180 static int igb_tx_map(struct igb_ring *tx_ring, 6181 struct igb_tx_buffer *first, 6182 const u8 hdr_len) 6183 { 6184 struct sk_buff *skb = first->skb; 6185 struct igb_tx_buffer *tx_buffer; 6186 union e1000_adv_tx_desc *tx_desc; 6187 skb_frag_t *frag; 6188 dma_addr_t dma; 6189 unsigned int data_len, size; 6190 u32 tx_flags = first->tx_flags; 6191 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6192 u16 i = tx_ring->next_to_use; 6193 6194 tx_desc = IGB_TX_DESC(tx_ring, i); 6195 6196 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6197 6198 size = skb_headlen(skb); 6199 data_len = skb->data_len; 6200 6201 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6202 6203 tx_buffer = first; 6204 6205 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6206 if (dma_mapping_error(tx_ring->dev, dma)) 6207 goto dma_error; 6208 6209 /* record length, and DMA address */ 6210 dma_unmap_len_set(tx_buffer, len, size); 6211 dma_unmap_addr_set(tx_buffer, dma, dma); 6212 6213 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6214 6215 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6216 tx_desc->read.cmd_type_len = 6217 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6218 6219 i++; 6220 tx_desc++; 6221 if (i == tx_ring->count) { 6222 tx_desc = IGB_TX_DESC(tx_ring, 0); 6223 i = 0; 6224 } 6225 tx_desc->read.olinfo_status = 0; 6226 6227 dma += IGB_MAX_DATA_PER_TXD; 6228 size -= IGB_MAX_DATA_PER_TXD; 6229 6230 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6231 } 6232 6233 if (likely(!data_len)) 6234 break; 6235 6236 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6237 6238 i++; 6239 tx_desc++; 6240 if (i == tx_ring->count) { 6241 tx_desc = IGB_TX_DESC(tx_ring, 0); 6242 i = 0; 6243 } 6244 tx_desc->read.olinfo_status = 0; 6245 6246 size = skb_frag_size(frag); 6247 data_len -= size; 6248 6249 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6250 size, DMA_TO_DEVICE); 6251 6252 tx_buffer = &tx_ring->tx_buffer_info[i]; 6253 } 6254 6255 /* write last descriptor with RS and EOP bits */ 6256 cmd_type |= size | IGB_TXD_DCMD; 6257 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6258 6259 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6260 6261 /* set the timestamp */ 6262 first->time_stamp = jiffies; 6263 6264 skb_tx_timestamp(skb); 6265 6266 /* Force memory writes to complete before letting h/w know there 6267 * are new descriptors to fetch. (Only applicable for weak-ordered 6268 * memory model archs, such as IA-64). 6269 * 6270 * We also need this memory barrier to make certain all of the 6271 * status bits have been updated before next_to_watch is written. 6272 */ 6273 dma_wmb(); 6274 6275 /* set next_to_watch value indicating a packet is present */ 6276 first->next_to_watch = tx_desc; 6277 6278 i++; 6279 if (i == tx_ring->count) 6280 i = 0; 6281 6282 tx_ring->next_to_use = i; 6283 6284 /* Make sure there is space in the ring for the next send. */ 6285 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6286 6287 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6288 writel(i, tx_ring->tail); 6289 } 6290 return 0; 6291 6292 dma_error: 6293 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6294 tx_buffer = &tx_ring->tx_buffer_info[i]; 6295 6296 /* clear dma mappings for failed tx_buffer_info map */ 6297 while (tx_buffer != first) { 6298 if (dma_unmap_len(tx_buffer, len)) 6299 dma_unmap_page(tx_ring->dev, 6300 dma_unmap_addr(tx_buffer, dma), 6301 dma_unmap_len(tx_buffer, len), 6302 DMA_TO_DEVICE); 6303 dma_unmap_len_set(tx_buffer, len, 0); 6304 6305 if (i-- == 0) 6306 i += tx_ring->count; 6307 tx_buffer = &tx_ring->tx_buffer_info[i]; 6308 } 6309 6310 if (dma_unmap_len(tx_buffer, len)) 6311 dma_unmap_single(tx_ring->dev, 6312 dma_unmap_addr(tx_buffer, dma), 6313 dma_unmap_len(tx_buffer, len), 6314 DMA_TO_DEVICE); 6315 dma_unmap_len_set(tx_buffer, len, 0); 6316 6317 dev_kfree_skb_any(tx_buffer->skb); 6318 tx_buffer->skb = NULL; 6319 6320 tx_ring->next_to_use = i; 6321 6322 return -1; 6323 } 6324 6325 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6326 struct igb_ring *tx_ring, 6327 struct xdp_frame *xdpf) 6328 { 6329 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6330 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6331 u16 count, i, index = tx_ring->next_to_use; 6332 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6333 struct igb_tx_buffer *tx_buffer = tx_head; 6334 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6335 u32 len = xdpf->len, cmd_type, olinfo_status; 6336 void *data = xdpf->data; 6337 6338 count = TXD_USE_COUNT(len); 6339 for (i = 0; i < nr_frags; i++) 6340 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6341 6342 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6343 return IGB_XDP_CONSUMED; 6344 6345 i = 0; 6346 /* record the location of the first descriptor for this packet */ 6347 tx_head->bytecount = xdp_get_frame_len(xdpf); 6348 tx_head->type = IGB_TYPE_XDP; 6349 tx_head->gso_segs = 1; 6350 tx_head->xdpf = xdpf; 6351 6352 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6353 /* 82575 requires a unique index per ring */ 6354 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6355 olinfo_status |= tx_ring->reg_idx << 4; 6356 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6357 6358 for (;;) { 6359 dma_addr_t dma; 6360 6361 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6362 if (dma_mapping_error(tx_ring->dev, dma)) 6363 goto unmap; 6364 6365 /* record length, and DMA address */ 6366 dma_unmap_len_set(tx_buffer, len, len); 6367 dma_unmap_addr_set(tx_buffer, dma, dma); 6368 6369 /* put descriptor type bits */ 6370 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6371 E1000_ADVTXD_DCMD_IFCS | len; 6372 6373 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6374 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6375 6376 tx_buffer->protocol = 0; 6377 6378 if (++index == tx_ring->count) 6379 index = 0; 6380 6381 if (i == nr_frags) 6382 break; 6383 6384 tx_buffer = &tx_ring->tx_buffer_info[index]; 6385 tx_desc = IGB_TX_DESC(tx_ring, index); 6386 tx_desc->read.olinfo_status = 0; 6387 6388 data = skb_frag_address(&sinfo->frags[i]); 6389 len = skb_frag_size(&sinfo->frags[i]); 6390 i++; 6391 } 6392 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6393 6394 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6395 /* set the timestamp */ 6396 tx_head->time_stamp = jiffies; 6397 6398 /* Avoid any potential race with xdp_xmit and cleanup */ 6399 smp_wmb(); 6400 6401 /* set next_to_watch value indicating a packet is present */ 6402 tx_head->next_to_watch = tx_desc; 6403 tx_ring->next_to_use = index; 6404 6405 /* Make sure there is space in the ring for the next send. */ 6406 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6407 6408 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6409 writel(index, tx_ring->tail); 6410 6411 return IGB_XDP_TX; 6412 6413 unmap: 6414 for (;;) { 6415 tx_buffer = &tx_ring->tx_buffer_info[index]; 6416 if (dma_unmap_len(tx_buffer, len)) 6417 dma_unmap_page(tx_ring->dev, 6418 dma_unmap_addr(tx_buffer, dma), 6419 dma_unmap_len(tx_buffer, len), 6420 DMA_TO_DEVICE); 6421 dma_unmap_len_set(tx_buffer, len, 0); 6422 if (tx_buffer == tx_head) 6423 break; 6424 6425 if (!index) 6426 index += tx_ring->count; 6427 index--; 6428 } 6429 6430 return IGB_XDP_CONSUMED; 6431 } 6432 6433 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6434 struct igb_ring *tx_ring) 6435 { 6436 struct igb_tx_buffer *first; 6437 int tso; 6438 u32 tx_flags = 0; 6439 unsigned short f; 6440 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6441 __be16 protocol = vlan_get_protocol(skb); 6442 u8 hdr_len = 0; 6443 6444 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6445 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6446 * + 2 desc gap to keep tail from touching head, 6447 * + 1 desc for context descriptor, 6448 * otherwise try next time 6449 */ 6450 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6451 count += TXD_USE_COUNT(skb_frag_size( 6452 &skb_shinfo(skb)->frags[f])); 6453 6454 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6455 /* this is a hard error */ 6456 return NETDEV_TX_BUSY; 6457 } 6458 6459 /* record the location of the first descriptor for this packet */ 6460 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6461 first->type = IGB_TYPE_SKB; 6462 first->skb = skb; 6463 first->bytecount = skb->len; 6464 first->gso_segs = 1; 6465 6466 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6467 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6468 6469 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6470 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6471 &adapter->state)) { 6472 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6473 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6474 6475 adapter->ptp_tx_skb = skb_get(skb); 6476 adapter->ptp_tx_start = jiffies; 6477 if (adapter->hw.mac.type == e1000_82576) 6478 schedule_work(&adapter->ptp_tx_work); 6479 } else { 6480 adapter->tx_hwtstamp_skipped++; 6481 } 6482 } 6483 6484 if (skb_vlan_tag_present(skb)) { 6485 tx_flags |= IGB_TX_FLAGS_VLAN; 6486 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6487 } 6488 6489 /* record initial flags and protocol */ 6490 first->tx_flags = tx_flags; 6491 first->protocol = protocol; 6492 6493 tso = igb_tso(tx_ring, first, &hdr_len); 6494 if (tso < 0) 6495 goto out_drop; 6496 else if (!tso) 6497 igb_tx_csum(tx_ring, first); 6498 6499 if (igb_tx_map(tx_ring, first, hdr_len)) 6500 goto cleanup_tx_tstamp; 6501 6502 return NETDEV_TX_OK; 6503 6504 out_drop: 6505 dev_kfree_skb_any(first->skb); 6506 first->skb = NULL; 6507 cleanup_tx_tstamp: 6508 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6509 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6510 6511 dev_kfree_skb_any(adapter->ptp_tx_skb); 6512 adapter->ptp_tx_skb = NULL; 6513 if (adapter->hw.mac.type == e1000_82576) 6514 cancel_work_sync(&adapter->ptp_tx_work); 6515 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6516 } 6517 6518 return NETDEV_TX_OK; 6519 } 6520 6521 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6522 struct sk_buff *skb) 6523 { 6524 unsigned int r_idx = skb->queue_mapping; 6525 6526 if (r_idx >= adapter->num_tx_queues) 6527 r_idx = r_idx % adapter->num_tx_queues; 6528 6529 return adapter->tx_ring[r_idx]; 6530 } 6531 6532 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6533 struct net_device *netdev) 6534 { 6535 struct igb_adapter *adapter = netdev_priv(netdev); 6536 6537 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6538 * in order to meet this minimum size requirement. 6539 */ 6540 if (skb_put_padto(skb, 17)) 6541 return NETDEV_TX_OK; 6542 6543 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6544 } 6545 6546 /** 6547 * igb_tx_timeout - Respond to a Tx Hang 6548 * @netdev: network interface device structure 6549 * @txqueue: number of the Tx queue that hung (unused) 6550 **/ 6551 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6552 { 6553 struct igb_adapter *adapter = netdev_priv(netdev); 6554 struct e1000_hw *hw = &adapter->hw; 6555 6556 /* Do the reset outside of interrupt context */ 6557 adapter->tx_timeout_count++; 6558 6559 if (hw->mac.type >= e1000_82580) 6560 hw->dev_spec._82575.global_device_reset = true; 6561 6562 schedule_work(&adapter->reset_task); 6563 wr32(E1000_EICS, 6564 (adapter->eims_enable_mask & ~adapter->eims_other)); 6565 } 6566 6567 static void igb_reset_task(struct work_struct *work) 6568 { 6569 struct igb_adapter *adapter; 6570 adapter = container_of(work, struct igb_adapter, reset_task); 6571 6572 rtnl_lock(); 6573 /* If we're already down or resetting, just bail */ 6574 if (test_bit(__IGB_DOWN, &adapter->state) || 6575 test_bit(__IGB_RESETTING, &adapter->state)) { 6576 rtnl_unlock(); 6577 return; 6578 } 6579 6580 igb_dump(adapter); 6581 netdev_err(adapter->netdev, "Reset adapter\n"); 6582 igb_reinit_locked(adapter); 6583 rtnl_unlock(); 6584 } 6585 6586 /** 6587 * igb_get_stats64 - Get System Network Statistics 6588 * @netdev: network interface device structure 6589 * @stats: rtnl_link_stats64 pointer 6590 **/ 6591 static void igb_get_stats64(struct net_device *netdev, 6592 struct rtnl_link_stats64 *stats) 6593 { 6594 struct igb_adapter *adapter = netdev_priv(netdev); 6595 6596 spin_lock(&adapter->stats64_lock); 6597 igb_update_stats(adapter); 6598 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6599 spin_unlock(&adapter->stats64_lock); 6600 } 6601 6602 /** 6603 * igb_change_mtu - Change the Maximum Transfer Unit 6604 * @netdev: network interface device structure 6605 * @new_mtu: new value for maximum frame size 6606 * 6607 * Returns 0 on success, negative on failure 6608 **/ 6609 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6610 { 6611 struct igb_adapter *adapter = netdev_priv(netdev); 6612 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6613 6614 if (adapter->xdp_prog) { 6615 int i; 6616 6617 for (i = 0; i < adapter->num_rx_queues; i++) { 6618 struct igb_ring *ring = adapter->rx_ring[i]; 6619 6620 if (max_frame > igb_rx_bufsz(ring)) { 6621 netdev_warn(adapter->netdev, 6622 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6623 max_frame); 6624 return -EINVAL; 6625 } 6626 } 6627 } 6628 6629 /* adjust max frame to be at least the size of a standard frame */ 6630 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6631 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6632 6633 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6634 usleep_range(1000, 2000); 6635 6636 /* igb_down has a dependency on max_frame_size */ 6637 adapter->max_frame_size = max_frame; 6638 6639 if (netif_running(netdev)) 6640 igb_down(adapter); 6641 6642 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6643 netdev->mtu, new_mtu); 6644 netdev->mtu = new_mtu; 6645 6646 if (netif_running(netdev)) 6647 igb_up(adapter); 6648 else 6649 igb_reset(adapter); 6650 6651 clear_bit(__IGB_RESETTING, &adapter->state); 6652 6653 return 0; 6654 } 6655 6656 /** 6657 * igb_update_stats - Update the board statistics counters 6658 * @adapter: board private structure 6659 **/ 6660 void igb_update_stats(struct igb_adapter *adapter) 6661 { 6662 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6663 struct e1000_hw *hw = &adapter->hw; 6664 struct pci_dev *pdev = adapter->pdev; 6665 u32 reg, mpc; 6666 int i; 6667 u64 bytes, packets; 6668 unsigned int start; 6669 u64 _bytes, _packets; 6670 6671 /* Prevent stats update while adapter is being reset, or if the pci 6672 * connection is down. 6673 */ 6674 if (adapter->link_speed == 0) 6675 return; 6676 if (pci_channel_offline(pdev)) 6677 return; 6678 6679 bytes = 0; 6680 packets = 0; 6681 6682 rcu_read_lock(); 6683 for (i = 0; i < adapter->num_rx_queues; i++) { 6684 struct igb_ring *ring = adapter->rx_ring[i]; 6685 u32 rqdpc = rd32(E1000_RQDPC(i)); 6686 if (hw->mac.type >= e1000_i210) 6687 wr32(E1000_RQDPC(i), 0); 6688 6689 if (rqdpc) { 6690 ring->rx_stats.drops += rqdpc; 6691 net_stats->rx_fifo_errors += rqdpc; 6692 } 6693 6694 do { 6695 start = u64_stats_fetch_begin(&ring->rx_syncp); 6696 _bytes = ring->rx_stats.bytes; 6697 _packets = ring->rx_stats.packets; 6698 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6699 bytes += _bytes; 6700 packets += _packets; 6701 } 6702 6703 net_stats->rx_bytes = bytes; 6704 net_stats->rx_packets = packets; 6705 6706 bytes = 0; 6707 packets = 0; 6708 for (i = 0; i < adapter->num_tx_queues; i++) { 6709 struct igb_ring *ring = adapter->tx_ring[i]; 6710 do { 6711 start = u64_stats_fetch_begin(&ring->tx_syncp); 6712 _bytes = ring->tx_stats.bytes; 6713 _packets = ring->tx_stats.packets; 6714 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6715 bytes += _bytes; 6716 packets += _packets; 6717 } 6718 net_stats->tx_bytes = bytes; 6719 net_stats->tx_packets = packets; 6720 rcu_read_unlock(); 6721 6722 /* read stats registers */ 6723 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6724 adapter->stats.gprc += rd32(E1000_GPRC); 6725 adapter->stats.gorc += rd32(E1000_GORCL); 6726 rd32(E1000_GORCH); /* clear GORCL */ 6727 adapter->stats.bprc += rd32(E1000_BPRC); 6728 adapter->stats.mprc += rd32(E1000_MPRC); 6729 adapter->stats.roc += rd32(E1000_ROC); 6730 6731 adapter->stats.prc64 += rd32(E1000_PRC64); 6732 adapter->stats.prc127 += rd32(E1000_PRC127); 6733 adapter->stats.prc255 += rd32(E1000_PRC255); 6734 adapter->stats.prc511 += rd32(E1000_PRC511); 6735 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6736 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6737 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6738 adapter->stats.sec += rd32(E1000_SEC); 6739 6740 mpc = rd32(E1000_MPC); 6741 adapter->stats.mpc += mpc; 6742 net_stats->rx_fifo_errors += mpc; 6743 adapter->stats.scc += rd32(E1000_SCC); 6744 adapter->stats.ecol += rd32(E1000_ECOL); 6745 adapter->stats.mcc += rd32(E1000_MCC); 6746 adapter->stats.latecol += rd32(E1000_LATECOL); 6747 adapter->stats.dc += rd32(E1000_DC); 6748 adapter->stats.rlec += rd32(E1000_RLEC); 6749 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6750 adapter->stats.xontxc += rd32(E1000_XONTXC); 6751 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6752 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6753 adapter->stats.fcruc += rd32(E1000_FCRUC); 6754 adapter->stats.gptc += rd32(E1000_GPTC); 6755 adapter->stats.gotc += rd32(E1000_GOTCL); 6756 rd32(E1000_GOTCH); /* clear GOTCL */ 6757 adapter->stats.rnbc += rd32(E1000_RNBC); 6758 adapter->stats.ruc += rd32(E1000_RUC); 6759 adapter->stats.rfc += rd32(E1000_RFC); 6760 adapter->stats.rjc += rd32(E1000_RJC); 6761 adapter->stats.tor += rd32(E1000_TORH); 6762 adapter->stats.tot += rd32(E1000_TOTH); 6763 adapter->stats.tpr += rd32(E1000_TPR); 6764 6765 adapter->stats.ptc64 += rd32(E1000_PTC64); 6766 adapter->stats.ptc127 += rd32(E1000_PTC127); 6767 adapter->stats.ptc255 += rd32(E1000_PTC255); 6768 adapter->stats.ptc511 += rd32(E1000_PTC511); 6769 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6770 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6771 6772 adapter->stats.mptc += rd32(E1000_MPTC); 6773 adapter->stats.bptc += rd32(E1000_BPTC); 6774 6775 adapter->stats.tpt += rd32(E1000_TPT); 6776 adapter->stats.colc += rd32(E1000_COLC); 6777 6778 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6779 /* read internal phy specific stats */ 6780 reg = rd32(E1000_CTRL_EXT); 6781 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6782 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6783 6784 /* this stat has invalid values on i210/i211 */ 6785 if ((hw->mac.type != e1000_i210) && 6786 (hw->mac.type != e1000_i211)) 6787 adapter->stats.tncrs += rd32(E1000_TNCRS); 6788 } 6789 6790 adapter->stats.tsctc += rd32(E1000_TSCTC); 6791 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6792 6793 adapter->stats.iac += rd32(E1000_IAC); 6794 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6795 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6796 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6797 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6798 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6799 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6800 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6801 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6802 6803 /* Fill out the OS statistics structure */ 6804 net_stats->multicast = adapter->stats.mprc; 6805 net_stats->collisions = adapter->stats.colc; 6806 6807 /* Rx Errors */ 6808 6809 /* RLEC on some newer hardware can be incorrect so build 6810 * our own version based on RUC and ROC 6811 */ 6812 net_stats->rx_errors = adapter->stats.rxerrc + 6813 adapter->stats.crcerrs + adapter->stats.algnerrc + 6814 adapter->stats.ruc + adapter->stats.roc + 6815 adapter->stats.cexterr; 6816 net_stats->rx_length_errors = adapter->stats.ruc + 6817 adapter->stats.roc; 6818 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6819 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6820 net_stats->rx_missed_errors = adapter->stats.mpc; 6821 6822 /* Tx Errors */ 6823 net_stats->tx_errors = adapter->stats.ecol + 6824 adapter->stats.latecol; 6825 net_stats->tx_aborted_errors = adapter->stats.ecol; 6826 net_stats->tx_window_errors = adapter->stats.latecol; 6827 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6828 6829 /* Tx Dropped needs to be maintained elsewhere */ 6830 6831 /* Management Stats */ 6832 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6833 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6834 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6835 6836 /* OS2BMC Stats */ 6837 reg = rd32(E1000_MANC); 6838 if (reg & E1000_MANC_EN_BMC2OS) { 6839 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6840 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6841 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6842 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6843 } 6844 } 6845 6846 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6847 { 6848 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6849 struct e1000_hw *hw = &adapter->hw; 6850 struct timespec64 ts; 6851 u32 tsauxc; 6852 6853 if (pin < 0 || pin >= IGB_N_SDP) 6854 return; 6855 6856 spin_lock(&adapter->tmreg_lock); 6857 6858 if (hw->mac.type == e1000_82580 || 6859 hw->mac.type == e1000_i354 || 6860 hw->mac.type == e1000_i350) { 6861 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6862 u32 systiml, systimh, level_mask, level, rem; 6863 u64 systim, now; 6864 6865 /* read systim registers in sequence */ 6866 rd32(E1000_SYSTIMR); 6867 systiml = rd32(E1000_SYSTIML); 6868 systimh = rd32(E1000_SYSTIMH); 6869 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6870 now = timecounter_cyc2time(&adapter->tc, systim); 6871 6872 if (pin < 2) { 6873 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6874 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6875 } else { 6876 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6877 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6878 } 6879 6880 div_u64_rem(now, ns, &rem); 6881 systim = systim + (ns - rem); 6882 6883 /* synchronize pin level with rising/falling edges */ 6884 div_u64_rem(now, ns << 1, &rem); 6885 if (rem < ns) { 6886 /* first half of period */ 6887 if (level == 0) { 6888 /* output is already low, skip this period */ 6889 systim += ns; 6890 pr_notice("igb: periodic output on %s missed falling edge\n", 6891 adapter->sdp_config[pin].name); 6892 } 6893 } else { 6894 /* second half of period */ 6895 if (level == 1) { 6896 /* output is already high, skip this period */ 6897 systim += ns; 6898 pr_notice("igb: periodic output on %s missed rising edge\n", 6899 adapter->sdp_config[pin].name); 6900 } 6901 } 6902 6903 /* for this chip family tv_sec is the upper part of the binary value, 6904 * so not seconds 6905 */ 6906 ts.tv_nsec = (u32)systim; 6907 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6908 } else { 6909 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6910 adapter->perout[tsintr_tt].period); 6911 } 6912 6913 /* u32 conversion of tv_sec is safe until y2106 */ 6914 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6915 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6916 tsauxc = rd32(E1000_TSAUXC); 6917 tsauxc |= TSAUXC_EN_TT0; 6918 wr32(E1000_TSAUXC, tsauxc); 6919 adapter->perout[tsintr_tt].start = ts; 6920 6921 spin_unlock(&adapter->tmreg_lock); 6922 } 6923 6924 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6925 { 6926 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6927 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6928 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6929 struct e1000_hw *hw = &adapter->hw; 6930 struct ptp_clock_event event; 6931 struct timespec64 ts; 6932 unsigned long flags; 6933 6934 if (pin < 0 || pin >= IGB_N_SDP) 6935 return; 6936 6937 if (hw->mac.type == e1000_82580 || 6938 hw->mac.type == e1000_i354 || 6939 hw->mac.type == e1000_i350) { 6940 u64 ns = rd32(auxstmpl); 6941 6942 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 6943 spin_lock_irqsave(&adapter->tmreg_lock, flags); 6944 ns = timecounter_cyc2time(&adapter->tc, ns); 6945 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 6946 ts = ns_to_timespec64(ns); 6947 } else { 6948 ts.tv_nsec = rd32(auxstmpl); 6949 ts.tv_sec = rd32(auxstmph); 6950 } 6951 6952 event.type = PTP_CLOCK_EXTTS; 6953 event.index = tsintr_tt; 6954 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6955 ptp_clock_event(adapter->ptp_clock, &event); 6956 } 6957 6958 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6959 { 6960 struct e1000_hw *hw = &adapter->hw; 6961 u32 tsicr = rd32(E1000_TSICR); 6962 struct ptp_clock_event event; 6963 6964 if (tsicr & TSINTR_SYS_WRAP) { 6965 event.type = PTP_CLOCK_PPS; 6966 if (adapter->ptp_caps.pps) 6967 ptp_clock_event(adapter->ptp_clock, &event); 6968 } 6969 6970 if (tsicr & E1000_TSICR_TXTS) { 6971 /* retrieve hardware timestamp */ 6972 schedule_work(&adapter->ptp_tx_work); 6973 } 6974 6975 if (tsicr & TSINTR_TT0) 6976 igb_perout(adapter, 0); 6977 6978 if (tsicr & TSINTR_TT1) 6979 igb_perout(adapter, 1); 6980 6981 if (tsicr & TSINTR_AUTT0) 6982 igb_extts(adapter, 0); 6983 6984 if (tsicr & TSINTR_AUTT1) 6985 igb_extts(adapter, 1); 6986 } 6987 6988 static irqreturn_t igb_msix_other(int irq, void *data) 6989 { 6990 struct igb_adapter *adapter = data; 6991 struct e1000_hw *hw = &adapter->hw; 6992 u32 icr = rd32(E1000_ICR); 6993 /* reading ICR causes bit 31 of EICR to be cleared */ 6994 6995 if (icr & E1000_ICR_DRSTA) 6996 schedule_work(&adapter->reset_task); 6997 6998 if (icr & E1000_ICR_DOUTSYNC) { 6999 /* HW is reporting DMA is out of sync */ 7000 adapter->stats.doosync++; 7001 /* The DMA Out of Sync is also indication of a spoof event 7002 * in IOV mode. Check the Wrong VM Behavior register to 7003 * see if it is really a spoof event. 7004 */ 7005 igb_check_wvbr(adapter); 7006 } 7007 7008 /* Check for a mailbox event */ 7009 if (icr & E1000_ICR_VMMB) 7010 igb_msg_task(adapter); 7011 7012 if (icr & E1000_ICR_LSC) { 7013 hw->mac.get_link_status = 1; 7014 /* guard against interrupt when we're going down */ 7015 if (!test_bit(__IGB_DOWN, &adapter->state)) 7016 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7017 } 7018 7019 if (icr & E1000_ICR_TS) 7020 igb_tsync_interrupt(adapter); 7021 7022 wr32(E1000_EIMS, adapter->eims_other); 7023 7024 return IRQ_HANDLED; 7025 } 7026 7027 static void igb_write_itr(struct igb_q_vector *q_vector) 7028 { 7029 struct igb_adapter *adapter = q_vector->adapter; 7030 u32 itr_val = q_vector->itr_val & 0x7FFC; 7031 7032 if (!q_vector->set_itr) 7033 return; 7034 7035 if (!itr_val) 7036 itr_val = 0x4; 7037 7038 if (adapter->hw.mac.type == e1000_82575) 7039 itr_val |= itr_val << 16; 7040 else 7041 itr_val |= E1000_EITR_CNT_IGNR; 7042 7043 writel(itr_val, q_vector->itr_register); 7044 q_vector->set_itr = 0; 7045 } 7046 7047 static irqreturn_t igb_msix_ring(int irq, void *data) 7048 { 7049 struct igb_q_vector *q_vector = data; 7050 7051 /* Write the ITR value calculated from the previous interrupt. */ 7052 igb_write_itr(q_vector); 7053 7054 napi_schedule(&q_vector->napi); 7055 7056 return IRQ_HANDLED; 7057 } 7058 7059 #ifdef CONFIG_IGB_DCA 7060 static void igb_update_tx_dca(struct igb_adapter *adapter, 7061 struct igb_ring *tx_ring, 7062 int cpu) 7063 { 7064 struct e1000_hw *hw = &adapter->hw; 7065 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7066 7067 if (hw->mac.type != e1000_82575) 7068 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7069 7070 /* We can enable relaxed ordering for reads, but not writes when 7071 * DCA is enabled. This is due to a known issue in some chipsets 7072 * which will cause the DCA tag to be cleared. 7073 */ 7074 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7075 E1000_DCA_TXCTRL_DATA_RRO_EN | 7076 E1000_DCA_TXCTRL_DESC_DCA_EN; 7077 7078 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7079 } 7080 7081 static void igb_update_rx_dca(struct igb_adapter *adapter, 7082 struct igb_ring *rx_ring, 7083 int cpu) 7084 { 7085 struct e1000_hw *hw = &adapter->hw; 7086 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7087 7088 if (hw->mac.type != e1000_82575) 7089 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7090 7091 /* We can enable relaxed ordering for reads, but not writes when 7092 * DCA is enabled. This is due to a known issue in some chipsets 7093 * which will cause the DCA tag to be cleared. 7094 */ 7095 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7096 E1000_DCA_RXCTRL_DESC_DCA_EN; 7097 7098 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7099 } 7100 7101 static void igb_update_dca(struct igb_q_vector *q_vector) 7102 { 7103 struct igb_adapter *adapter = q_vector->adapter; 7104 int cpu = get_cpu(); 7105 7106 if (q_vector->cpu == cpu) 7107 goto out_no_update; 7108 7109 if (q_vector->tx.ring) 7110 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7111 7112 if (q_vector->rx.ring) 7113 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7114 7115 q_vector->cpu = cpu; 7116 out_no_update: 7117 put_cpu(); 7118 } 7119 7120 static void igb_setup_dca(struct igb_adapter *adapter) 7121 { 7122 struct e1000_hw *hw = &adapter->hw; 7123 int i; 7124 7125 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7126 return; 7127 7128 /* Always use CB2 mode, difference is masked in the CB driver. */ 7129 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7130 7131 for (i = 0; i < adapter->num_q_vectors; i++) { 7132 adapter->q_vector[i]->cpu = -1; 7133 igb_update_dca(adapter->q_vector[i]); 7134 } 7135 } 7136 7137 static int __igb_notify_dca(struct device *dev, void *data) 7138 { 7139 struct net_device *netdev = dev_get_drvdata(dev); 7140 struct igb_adapter *adapter = netdev_priv(netdev); 7141 struct pci_dev *pdev = adapter->pdev; 7142 struct e1000_hw *hw = &adapter->hw; 7143 unsigned long event = *(unsigned long *)data; 7144 7145 switch (event) { 7146 case DCA_PROVIDER_ADD: 7147 /* if already enabled, don't do it again */ 7148 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7149 break; 7150 if (dca_add_requester(dev) == 0) { 7151 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7152 dev_info(&pdev->dev, "DCA enabled\n"); 7153 igb_setup_dca(adapter); 7154 break; 7155 } 7156 fallthrough; /* since DCA is disabled. */ 7157 case DCA_PROVIDER_REMOVE: 7158 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7159 /* without this a class_device is left 7160 * hanging around in the sysfs model 7161 */ 7162 dca_remove_requester(dev); 7163 dev_info(&pdev->dev, "DCA disabled\n"); 7164 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7165 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7166 } 7167 break; 7168 } 7169 7170 return 0; 7171 } 7172 7173 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7174 void *p) 7175 { 7176 int ret_val; 7177 7178 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7179 __igb_notify_dca); 7180 7181 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7182 } 7183 #endif /* CONFIG_IGB_DCA */ 7184 7185 #ifdef CONFIG_PCI_IOV 7186 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7187 { 7188 unsigned char mac_addr[ETH_ALEN]; 7189 7190 eth_zero_addr(mac_addr); 7191 igb_set_vf_mac(adapter, vf, mac_addr); 7192 7193 /* By default spoof check is enabled for all VFs */ 7194 adapter->vf_data[vf].spoofchk_enabled = true; 7195 7196 /* By default VFs are not trusted */ 7197 adapter->vf_data[vf].trusted = false; 7198 7199 return 0; 7200 } 7201 7202 #endif 7203 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7204 { 7205 struct e1000_hw *hw = &adapter->hw; 7206 u32 ping; 7207 int i; 7208 7209 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7210 ping = E1000_PF_CONTROL_MSG; 7211 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7212 ping |= E1000_VT_MSGTYPE_CTS; 7213 igb_write_mbx(hw, &ping, 1, i); 7214 } 7215 } 7216 7217 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7218 { 7219 struct e1000_hw *hw = &adapter->hw; 7220 u32 vmolr = rd32(E1000_VMOLR(vf)); 7221 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7222 7223 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7224 IGB_VF_FLAG_MULTI_PROMISC); 7225 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7226 7227 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7228 vmolr |= E1000_VMOLR_MPME; 7229 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7230 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7231 } else { 7232 /* if we have hashes and we are clearing a multicast promisc 7233 * flag we need to write the hashes to the MTA as this step 7234 * was previously skipped 7235 */ 7236 if (vf_data->num_vf_mc_hashes > 30) { 7237 vmolr |= E1000_VMOLR_MPME; 7238 } else if (vf_data->num_vf_mc_hashes) { 7239 int j; 7240 7241 vmolr |= E1000_VMOLR_ROMPE; 7242 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7243 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7244 } 7245 } 7246 7247 wr32(E1000_VMOLR(vf), vmolr); 7248 7249 /* there are flags left unprocessed, likely not supported */ 7250 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7251 return -EINVAL; 7252 7253 return 0; 7254 } 7255 7256 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7257 u32 *msgbuf, u32 vf) 7258 { 7259 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7260 u16 *hash_list = (u16 *)&msgbuf[1]; 7261 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7262 int i; 7263 7264 /* salt away the number of multicast addresses assigned 7265 * to this VF for later use to restore when the PF multi cast 7266 * list changes 7267 */ 7268 vf_data->num_vf_mc_hashes = n; 7269 7270 /* only up to 30 hash values supported */ 7271 if (n > 30) 7272 n = 30; 7273 7274 /* store the hashes for later use */ 7275 for (i = 0; i < n; i++) 7276 vf_data->vf_mc_hashes[i] = hash_list[i]; 7277 7278 /* Flush and reset the mta with the new values */ 7279 igb_set_rx_mode(adapter->netdev); 7280 7281 return 0; 7282 } 7283 7284 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7285 { 7286 struct e1000_hw *hw = &adapter->hw; 7287 struct vf_data_storage *vf_data; 7288 int i, j; 7289 7290 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7291 u32 vmolr = rd32(E1000_VMOLR(i)); 7292 7293 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7294 7295 vf_data = &adapter->vf_data[i]; 7296 7297 if ((vf_data->num_vf_mc_hashes > 30) || 7298 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7299 vmolr |= E1000_VMOLR_MPME; 7300 } else if (vf_data->num_vf_mc_hashes) { 7301 vmolr |= E1000_VMOLR_ROMPE; 7302 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7303 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7304 } 7305 wr32(E1000_VMOLR(i), vmolr); 7306 } 7307 } 7308 7309 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7310 { 7311 struct e1000_hw *hw = &adapter->hw; 7312 u32 pool_mask, vlvf_mask, i; 7313 7314 /* create mask for VF and other pools */ 7315 pool_mask = E1000_VLVF_POOLSEL_MASK; 7316 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7317 7318 /* drop PF from pool bits */ 7319 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7320 adapter->vfs_allocated_count); 7321 7322 /* Find the vlan filter for this id */ 7323 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7324 u32 vlvf = rd32(E1000_VLVF(i)); 7325 u32 vfta_mask, vid, vfta; 7326 7327 /* remove the vf from the pool */ 7328 if (!(vlvf & vlvf_mask)) 7329 continue; 7330 7331 /* clear out bit from VLVF */ 7332 vlvf ^= vlvf_mask; 7333 7334 /* if other pools are present, just remove ourselves */ 7335 if (vlvf & pool_mask) 7336 goto update_vlvfb; 7337 7338 /* if PF is present, leave VFTA */ 7339 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7340 goto update_vlvf; 7341 7342 vid = vlvf & E1000_VLVF_VLANID_MASK; 7343 vfta_mask = BIT(vid % 32); 7344 7345 /* clear bit from VFTA */ 7346 vfta = adapter->shadow_vfta[vid / 32]; 7347 if (vfta & vfta_mask) 7348 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7349 update_vlvf: 7350 /* clear pool selection enable */ 7351 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7352 vlvf &= E1000_VLVF_POOLSEL_MASK; 7353 else 7354 vlvf = 0; 7355 update_vlvfb: 7356 /* clear pool bits */ 7357 wr32(E1000_VLVF(i), vlvf); 7358 } 7359 } 7360 7361 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7362 { 7363 u32 vlvf; 7364 int idx; 7365 7366 /* short cut the special case */ 7367 if (vlan == 0) 7368 return 0; 7369 7370 /* Search for the VLAN id in the VLVF entries */ 7371 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7372 vlvf = rd32(E1000_VLVF(idx)); 7373 if ((vlvf & VLAN_VID_MASK) == vlan) 7374 break; 7375 } 7376 7377 return idx; 7378 } 7379 7380 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7381 { 7382 struct e1000_hw *hw = &adapter->hw; 7383 u32 bits, pf_id; 7384 int idx; 7385 7386 idx = igb_find_vlvf_entry(hw, vid); 7387 if (!idx) 7388 return; 7389 7390 /* See if any other pools are set for this VLAN filter 7391 * entry other than the PF. 7392 */ 7393 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7394 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7395 bits &= rd32(E1000_VLVF(idx)); 7396 7397 /* Disable the filter so this falls into the default pool. */ 7398 if (!bits) { 7399 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7400 wr32(E1000_VLVF(idx), BIT(pf_id)); 7401 else 7402 wr32(E1000_VLVF(idx), 0); 7403 } 7404 } 7405 7406 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7407 bool add, u32 vf) 7408 { 7409 int pf_id = adapter->vfs_allocated_count; 7410 struct e1000_hw *hw = &adapter->hw; 7411 int err; 7412 7413 /* If VLAN overlaps with one the PF is currently monitoring make 7414 * sure that we are able to allocate a VLVF entry. This may be 7415 * redundant but it guarantees PF will maintain visibility to 7416 * the VLAN. 7417 */ 7418 if (add && test_bit(vid, adapter->active_vlans)) { 7419 err = igb_vfta_set(hw, vid, pf_id, true, false); 7420 if (err) 7421 return err; 7422 } 7423 7424 err = igb_vfta_set(hw, vid, vf, add, false); 7425 7426 if (add && !err) 7427 return err; 7428 7429 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7430 * we may need to drop the PF pool bit in order to allow us to free 7431 * up the VLVF resources. 7432 */ 7433 if (test_bit(vid, adapter->active_vlans) || 7434 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7435 igb_update_pf_vlvf(adapter, vid); 7436 7437 return err; 7438 } 7439 7440 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7441 { 7442 struct e1000_hw *hw = &adapter->hw; 7443 7444 if (vid) 7445 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7446 else 7447 wr32(E1000_VMVIR(vf), 0); 7448 } 7449 7450 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7451 u16 vlan, u8 qos) 7452 { 7453 int err; 7454 7455 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7456 if (err) 7457 return err; 7458 7459 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7460 igb_set_vmolr(adapter, vf, !vlan); 7461 7462 /* revoke access to previous VLAN */ 7463 if (vlan != adapter->vf_data[vf].pf_vlan) 7464 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7465 false, vf); 7466 7467 adapter->vf_data[vf].pf_vlan = vlan; 7468 adapter->vf_data[vf].pf_qos = qos; 7469 igb_set_vf_vlan_strip(adapter, vf, true); 7470 dev_info(&adapter->pdev->dev, 7471 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7472 if (test_bit(__IGB_DOWN, &adapter->state)) { 7473 dev_warn(&adapter->pdev->dev, 7474 "The VF VLAN has been set, but the PF device is not up.\n"); 7475 dev_warn(&adapter->pdev->dev, 7476 "Bring the PF device up before attempting to use the VF device.\n"); 7477 } 7478 7479 return err; 7480 } 7481 7482 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7483 { 7484 /* Restore tagless access via VLAN 0 */ 7485 igb_set_vf_vlan(adapter, 0, true, vf); 7486 7487 igb_set_vmvir(adapter, 0, vf); 7488 igb_set_vmolr(adapter, vf, true); 7489 7490 /* Remove any PF assigned VLAN */ 7491 if (adapter->vf_data[vf].pf_vlan) 7492 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7493 false, vf); 7494 7495 adapter->vf_data[vf].pf_vlan = 0; 7496 adapter->vf_data[vf].pf_qos = 0; 7497 igb_set_vf_vlan_strip(adapter, vf, false); 7498 7499 return 0; 7500 } 7501 7502 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7503 u16 vlan, u8 qos, __be16 vlan_proto) 7504 { 7505 struct igb_adapter *adapter = netdev_priv(netdev); 7506 7507 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7508 return -EINVAL; 7509 7510 if (vlan_proto != htons(ETH_P_8021Q)) 7511 return -EPROTONOSUPPORT; 7512 7513 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7514 igb_disable_port_vlan(adapter, vf); 7515 } 7516 7517 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7518 { 7519 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7520 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7521 int ret; 7522 7523 if (adapter->vf_data[vf].pf_vlan) 7524 return -1; 7525 7526 /* VLAN 0 is a special case, don't allow it to be removed */ 7527 if (!vid && !add) 7528 return 0; 7529 7530 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7531 if (!ret) 7532 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7533 return ret; 7534 } 7535 7536 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7537 { 7538 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7539 7540 /* clear flags - except flag that indicates PF has set the MAC */ 7541 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7542 vf_data->last_nack = jiffies; 7543 7544 /* reset vlans for device */ 7545 igb_clear_vf_vfta(adapter, vf); 7546 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7547 igb_set_vmvir(adapter, vf_data->pf_vlan | 7548 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7549 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7550 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7551 7552 /* reset multicast table array for vf */ 7553 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7554 7555 /* Flush and reset the mta with the new values */ 7556 igb_set_rx_mode(adapter->netdev); 7557 } 7558 7559 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7560 { 7561 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7562 7563 /* clear mac address as we were hotplug removed/added */ 7564 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7565 eth_zero_addr(vf_mac); 7566 7567 /* process remaining reset events */ 7568 igb_vf_reset(adapter, vf); 7569 } 7570 7571 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7572 { 7573 struct e1000_hw *hw = &adapter->hw; 7574 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7575 u32 reg, msgbuf[3] = {}; 7576 u8 *addr = (u8 *)(&msgbuf[1]); 7577 7578 /* process all the same items cleared in a function level reset */ 7579 igb_vf_reset(adapter, vf); 7580 7581 /* set vf mac address */ 7582 igb_set_vf_mac(adapter, vf, vf_mac); 7583 7584 /* enable transmit and receive for vf */ 7585 reg = rd32(E1000_VFTE); 7586 wr32(E1000_VFTE, reg | BIT(vf)); 7587 reg = rd32(E1000_VFRE); 7588 wr32(E1000_VFRE, reg | BIT(vf)); 7589 7590 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7591 7592 /* reply to reset with ack and vf mac address */ 7593 if (!is_zero_ether_addr(vf_mac)) { 7594 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7595 memcpy(addr, vf_mac, ETH_ALEN); 7596 } else { 7597 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7598 } 7599 igb_write_mbx(hw, msgbuf, 3, vf); 7600 } 7601 7602 static void igb_flush_mac_table(struct igb_adapter *adapter) 7603 { 7604 struct e1000_hw *hw = &adapter->hw; 7605 int i; 7606 7607 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7608 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7609 eth_zero_addr(adapter->mac_table[i].addr); 7610 adapter->mac_table[i].queue = 0; 7611 igb_rar_set_index(adapter, i); 7612 } 7613 } 7614 7615 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7616 { 7617 struct e1000_hw *hw = &adapter->hw; 7618 /* do not count rar entries reserved for VFs MAC addresses */ 7619 int rar_entries = hw->mac.rar_entry_count - 7620 adapter->vfs_allocated_count; 7621 int i, count = 0; 7622 7623 for (i = 0; i < rar_entries; i++) { 7624 /* do not count default entries */ 7625 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7626 continue; 7627 7628 /* do not count "in use" entries for different queues */ 7629 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7630 (adapter->mac_table[i].queue != queue)) 7631 continue; 7632 7633 count++; 7634 } 7635 7636 return count; 7637 } 7638 7639 /* Set default MAC address for the PF in the first RAR entry */ 7640 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7641 { 7642 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7643 7644 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7645 mac_table->queue = adapter->vfs_allocated_count; 7646 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7647 7648 igb_rar_set_index(adapter, 0); 7649 } 7650 7651 /* If the filter to be added and an already existing filter express 7652 * the same address and address type, it should be possible to only 7653 * override the other configurations, for example the queue to steer 7654 * traffic. 7655 */ 7656 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7657 const u8 *addr, const u8 flags) 7658 { 7659 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7660 return true; 7661 7662 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7663 (flags & IGB_MAC_STATE_SRC_ADDR)) 7664 return false; 7665 7666 if (!ether_addr_equal(addr, entry->addr)) 7667 return false; 7668 7669 return true; 7670 } 7671 7672 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7673 * 'flags' is used to indicate what kind of match is made, match is by 7674 * default for the destination address, if matching by source address 7675 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7676 */ 7677 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7678 const u8 *addr, const u8 queue, 7679 const u8 flags) 7680 { 7681 struct e1000_hw *hw = &adapter->hw; 7682 int rar_entries = hw->mac.rar_entry_count - 7683 adapter->vfs_allocated_count; 7684 int i; 7685 7686 if (is_zero_ether_addr(addr)) 7687 return -EINVAL; 7688 7689 /* Search for the first empty entry in the MAC table. 7690 * Do not touch entries at the end of the table reserved for the VF MAC 7691 * addresses. 7692 */ 7693 for (i = 0; i < rar_entries; i++) { 7694 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7695 addr, flags)) 7696 continue; 7697 7698 ether_addr_copy(adapter->mac_table[i].addr, addr); 7699 adapter->mac_table[i].queue = queue; 7700 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7701 7702 igb_rar_set_index(adapter, i); 7703 return i; 7704 } 7705 7706 return -ENOSPC; 7707 } 7708 7709 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7710 const u8 queue) 7711 { 7712 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7713 } 7714 7715 /* Remove a MAC filter for 'addr' directing matching traffic to 7716 * 'queue', 'flags' is used to indicate what kind of match need to be 7717 * removed, match is by default for the destination address, if 7718 * matching by source address is to be removed the flag 7719 * IGB_MAC_STATE_SRC_ADDR can be used. 7720 */ 7721 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7722 const u8 *addr, const u8 queue, 7723 const u8 flags) 7724 { 7725 struct e1000_hw *hw = &adapter->hw; 7726 int rar_entries = hw->mac.rar_entry_count - 7727 adapter->vfs_allocated_count; 7728 int i; 7729 7730 if (is_zero_ether_addr(addr)) 7731 return -EINVAL; 7732 7733 /* Search for matching entry in the MAC table based on given address 7734 * and queue. Do not touch entries at the end of the table reserved 7735 * for the VF MAC addresses. 7736 */ 7737 for (i = 0; i < rar_entries; i++) { 7738 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7739 continue; 7740 if ((adapter->mac_table[i].state & flags) != flags) 7741 continue; 7742 if (adapter->mac_table[i].queue != queue) 7743 continue; 7744 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7745 continue; 7746 7747 /* When a filter for the default address is "deleted", 7748 * we return it to its initial configuration 7749 */ 7750 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7751 adapter->mac_table[i].state = 7752 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7753 adapter->mac_table[i].queue = 7754 adapter->vfs_allocated_count; 7755 } else { 7756 adapter->mac_table[i].state = 0; 7757 adapter->mac_table[i].queue = 0; 7758 eth_zero_addr(adapter->mac_table[i].addr); 7759 } 7760 7761 igb_rar_set_index(adapter, i); 7762 return 0; 7763 } 7764 7765 return -ENOENT; 7766 } 7767 7768 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7769 const u8 queue) 7770 { 7771 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7772 } 7773 7774 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7775 const u8 *addr, u8 queue, u8 flags) 7776 { 7777 struct e1000_hw *hw = &adapter->hw; 7778 7779 /* In theory, this should be supported on 82575 as well, but 7780 * that part wasn't easily accessible during development. 7781 */ 7782 if (hw->mac.type != e1000_i210) 7783 return -EOPNOTSUPP; 7784 7785 return igb_add_mac_filter_flags(adapter, addr, queue, 7786 IGB_MAC_STATE_QUEUE_STEERING | flags); 7787 } 7788 7789 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7790 const u8 *addr, u8 queue, u8 flags) 7791 { 7792 return igb_del_mac_filter_flags(adapter, addr, queue, 7793 IGB_MAC_STATE_QUEUE_STEERING | flags); 7794 } 7795 7796 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7797 { 7798 struct igb_adapter *adapter = netdev_priv(netdev); 7799 int ret; 7800 7801 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7802 7803 return min_t(int, ret, 0); 7804 } 7805 7806 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7807 { 7808 struct igb_adapter *adapter = netdev_priv(netdev); 7809 7810 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7811 7812 return 0; 7813 } 7814 7815 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7816 const u32 info, const u8 *addr) 7817 { 7818 struct pci_dev *pdev = adapter->pdev; 7819 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7820 struct vf_mac_filter *entry; 7821 bool found = false; 7822 int ret = 0; 7823 7824 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7825 !vf_data->trusted) { 7826 dev_warn(&pdev->dev, 7827 "VF %d requested MAC filter but is administratively denied\n", 7828 vf); 7829 return -EINVAL; 7830 } 7831 if (!is_valid_ether_addr(addr)) { 7832 dev_warn(&pdev->dev, 7833 "VF %d attempted to set invalid MAC filter\n", 7834 vf); 7835 return -EINVAL; 7836 } 7837 7838 switch (info) { 7839 case E1000_VF_MAC_FILTER_CLR: 7840 /* remove all unicast MAC filters related to the current VF */ 7841 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7842 if (entry->vf == vf) { 7843 entry->vf = -1; 7844 entry->free = true; 7845 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7846 } 7847 } 7848 break; 7849 case E1000_VF_MAC_FILTER_ADD: 7850 /* try to find empty slot in the list */ 7851 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7852 if (entry->free) { 7853 found = true; 7854 break; 7855 } 7856 } 7857 7858 if (found) { 7859 entry->free = false; 7860 entry->vf = vf; 7861 ether_addr_copy(entry->vf_mac, addr); 7862 7863 ret = igb_add_mac_filter(adapter, addr, vf); 7864 ret = min_t(int, ret, 0); 7865 } else { 7866 ret = -ENOSPC; 7867 } 7868 7869 if (ret == -ENOSPC) 7870 dev_warn(&pdev->dev, 7871 "VF %d has requested MAC filter but there is no space for it\n", 7872 vf); 7873 break; 7874 default: 7875 ret = -EINVAL; 7876 break; 7877 } 7878 7879 return ret; 7880 } 7881 7882 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7883 { 7884 struct pci_dev *pdev = adapter->pdev; 7885 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7886 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7887 7888 /* The VF MAC Address is stored in a packed array of bytes 7889 * starting at the second 32 bit word of the msg array 7890 */ 7891 unsigned char *addr = (unsigned char *)&msg[1]; 7892 int ret = 0; 7893 7894 if (!info) { 7895 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7896 !vf_data->trusted) { 7897 dev_warn(&pdev->dev, 7898 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7899 vf); 7900 return -EINVAL; 7901 } 7902 7903 if (!is_valid_ether_addr(addr)) { 7904 dev_warn(&pdev->dev, 7905 "VF %d attempted to set invalid MAC\n", 7906 vf); 7907 return -EINVAL; 7908 } 7909 7910 ret = igb_set_vf_mac(adapter, vf, addr); 7911 } else { 7912 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7913 } 7914 7915 return ret; 7916 } 7917 7918 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7919 { 7920 struct e1000_hw *hw = &adapter->hw; 7921 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7922 u32 msg = E1000_VT_MSGTYPE_NACK; 7923 7924 /* if device isn't clear to send it shouldn't be reading either */ 7925 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7926 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7927 igb_write_mbx(hw, &msg, 1, vf); 7928 vf_data->last_nack = jiffies; 7929 } 7930 } 7931 7932 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7933 { 7934 struct pci_dev *pdev = adapter->pdev; 7935 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7936 struct e1000_hw *hw = &adapter->hw; 7937 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7938 s32 retval; 7939 7940 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7941 7942 if (retval) { 7943 /* if receive failed revoke VF CTS stats and restart init */ 7944 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7945 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7946 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7947 goto unlock; 7948 goto out; 7949 } 7950 7951 /* this is a message we already processed, do nothing */ 7952 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7953 goto unlock; 7954 7955 /* until the vf completes a reset it should not be 7956 * allowed to start any configuration. 7957 */ 7958 if (msgbuf[0] == E1000_VF_RESET) { 7959 /* unlocks mailbox */ 7960 igb_vf_reset_msg(adapter, vf); 7961 return; 7962 } 7963 7964 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7965 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7966 goto unlock; 7967 retval = -1; 7968 goto out; 7969 } 7970 7971 switch ((msgbuf[0] & 0xFFFF)) { 7972 case E1000_VF_SET_MAC_ADDR: 7973 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7974 break; 7975 case E1000_VF_SET_PROMISC: 7976 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7977 break; 7978 case E1000_VF_SET_MULTICAST: 7979 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7980 break; 7981 case E1000_VF_SET_LPE: 7982 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7983 break; 7984 case E1000_VF_SET_VLAN: 7985 retval = -1; 7986 if (vf_data->pf_vlan) 7987 dev_warn(&pdev->dev, 7988 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7989 vf); 7990 else 7991 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7992 break; 7993 default: 7994 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7995 retval = -1; 7996 break; 7997 } 7998 7999 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8000 out: 8001 /* notify the VF of the results of what it sent us */ 8002 if (retval) 8003 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8004 else 8005 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8006 8007 /* unlocks mailbox */ 8008 igb_write_mbx(hw, msgbuf, 1, vf); 8009 return; 8010 8011 unlock: 8012 igb_unlock_mbx(hw, vf); 8013 } 8014 8015 static void igb_msg_task(struct igb_adapter *adapter) 8016 { 8017 struct e1000_hw *hw = &adapter->hw; 8018 unsigned long flags; 8019 u32 vf; 8020 8021 spin_lock_irqsave(&adapter->vfs_lock, flags); 8022 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8023 /* process any reset requests */ 8024 if (!igb_check_for_rst(hw, vf)) 8025 igb_vf_reset_event(adapter, vf); 8026 8027 /* process any messages pending */ 8028 if (!igb_check_for_msg(hw, vf)) 8029 igb_rcv_msg_from_vf(adapter, vf); 8030 8031 /* process any acks */ 8032 if (!igb_check_for_ack(hw, vf)) 8033 igb_rcv_ack_from_vf(adapter, vf); 8034 } 8035 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8036 } 8037 8038 /** 8039 * igb_set_uta - Set unicast filter table address 8040 * @adapter: board private structure 8041 * @set: boolean indicating if we are setting or clearing bits 8042 * 8043 * The unicast table address is a register array of 32-bit registers. 8044 * The table is meant to be used in a way similar to how the MTA is used 8045 * however due to certain limitations in the hardware it is necessary to 8046 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8047 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8048 **/ 8049 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8050 { 8051 struct e1000_hw *hw = &adapter->hw; 8052 u32 uta = set ? ~0 : 0; 8053 int i; 8054 8055 /* we only need to do this if VMDq is enabled */ 8056 if (!adapter->vfs_allocated_count) 8057 return; 8058 8059 for (i = hw->mac.uta_reg_count; i--;) 8060 array_wr32(E1000_UTA, i, uta); 8061 } 8062 8063 /** 8064 * igb_intr_msi - Interrupt Handler 8065 * @irq: interrupt number 8066 * @data: pointer to a network interface device structure 8067 **/ 8068 static irqreturn_t igb_intr_msi(int irq, void *data) 8069 { 8070 struct igb_adapter *adapter = data; 8071 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8072 struct e1000_hw *hw = &adapter->hw; 8073 /* read ICR disables interrupts using IAM */ 8074 u32 icr = rd32(E1000_ICR); 8075 8076 igb_write_itr(q_vector); 8077 8078 if (icr & E1000_ICR_DRSTA) 8079 schedule_work(&adapter->reset_task); 8080 8081 if (icr & E1000_ICR_DOUTSYNC) { 8082 /* HW is reporting DMA is out of sync */ 8083 adapter->stats.doosync++; 8084 } 8085 8086 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8087 hw->mac.get_link_status = 1; 8088 if (!test_bit(__IGB_DOWN, &adapter->state)) 8089 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8090 } 8091 8092 if (icr & E1000_ICR_TS) 8093 igb_tsync_interrupt(adapter); 8094 8095 napi_schedule(&q_vector->napi); 8096 8097 return IRQ_HANDLED; 8098 } 8099 8100 /** 8101 * igb_intr - Legacy Interrupt Handler 8102 * @irq: interrupt number 8103 * @data: pointer to a network interface device structure 8104 **/ 8105 static irqreturn_t igb_intr(int irq, void *data) 8106 { 8107 struct igb_adapter *adapter = data; 8108 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8109 struct e1000_hw *hw = &adapter->hw; 8110 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8111 * need for the IMC write 8112 */ 8113 u32 icr = rd32(E1000_ICR); 8114 8115 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8116 * not set, then the adapter didn't send an interrupt 8117 */ 8118 if (!(icr & E1000_ICR_INT_ASSERTED)) 8119 return IRQ_NONE; 8120 8121 igb_write_itr(q_vector); 8122 8123 if (icr & E1000_ICR_DRSTA) 8124 schedule_work(&adapter->reset_task); 8125 8126 if (icr & E1000_ICR_DOUTSYNC) { 8127 /* HW is reporting DMA is out of sync */ 8128 adapter->stats.doosync++; 8129 } 8130 8131 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8132 hw->mac.get_link_status = 1; 8133 /* guard against interrupt when we're going down */ 8134 if (!test_bit(__IGB_DOWN, &adapter->state)) 8135 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8136 } 8137 8138 if (icr & E1000_ICR_TS) 8139 igb_tsync_interrupt(adapter); 8140 8141 napi_schedule(&q_vector->napi); 8142 8143 return IRQ_HANDLED; 8144 } 8145 8146 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8147 { 8148 struct igb_adapter *adapter = q_vector->adapter; 8149 struct e1000_hw *hw = &adapter->hw; 8150 8151 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8152 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8153 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8154 igb_set_itr(q_vector); 8155 else 8156 igb_update_ring_itr(q_vector); 8157 } 8158 8159 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8160 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8161 wr32(E1000_EIMS, q_vector->eims_value); 8162 else 8163 igb_irq_enable(adapter); 8164 } 8165 } 8166 8167 /** 8168 * igb_poll - NAPI Rx polling callback 8169 * @napi: napi polling structure 8170 * @budget: count of how many packets we should handle 8171 **/ 8172 static int igb_poll(struct napi_struct *napi, int budget) 8173 { 8174 struct igb_q_vector *q_vector = container_of(napi, 8175 struct igb_q_vector, 8176 napi); 8177 bool clean_complete = true; 8178 int work_done = 0; 8179 8180 #ifdef CONFIG_IGB_DCA 8181 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8182 igb_update_dca(q_vector); 8183 #endif 8184 if (q_vector->tx.ring) 8185 clean_complete = igb_clean_tx_irq(q_vector, budget); 8186 8187 if (q_vector->rx.ring) { 8188 int cleaned = igb_clean_rx_irq(q_vector, budget); 8189 8190 work_done += cleaned; 8191 if (cleaned >= budget) 8192 clean_complete = false; 8193 } 8194 8195 /* If all work not completed, return budget and keep polling */ 8196 if (!clean_complete) 8197 return budget; 8198 8199 /* Exit the polling mode, but don't re-enable interrupts if stack might 8200 * poll us due to busy-polling 8201 */ 8202 if (likely(napi_complete_done(napi, work_done))) 8203 igb_ring_irq_enable(q_vector); 8204 8205 return work_done; 8206 } 8207 8208 /** 8209 * igb_clean_tx_irq - Reclaim resources after transmit completes 8210 * @q_vector: pointer to q_vector containing needed info 8211 * @napi_budget: Used to determine if we are in netpoll 8212 * 8213 * returns true if ring is completely cleaned 8214 **/ 8215 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8216 { 8217 struct igb_adapter *adapter = q_vector->adapter; 8218 struct igb_ring *tx_ring = q_vector->tx.ring; 8219 struct igb_tx_buffer *tx_buffer; 8220 union e1000_adv_tx_desc *tx_desc; 8221 unsigned int total_bytes = 0, total_packets = 0; 8222 unsigned int budget = q_vector->tx.work_limit; 8223 unsigned int i = tx_ring->next_to_clean; 8224 8225 if (test_bit(__IGB_DOWN, &adapter->state)) 8226 return true; 8227 8228 tx_buffer = &tx_ring->tx_buffer_info[i]; 8229 tx_desc = IGB_TX_DESC(tx_ring, i); 8230 i -= tx_ring->count; 8231 8232 do { 8233 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8234 8235 /* if next_to_watch is not set then there is no work pending */ 8236 if (!eop_desc) 8237 break; 8238 8239 /* prevent any other reads prior to eop_desc */ 8240 smp_rmb(); 8241 8242 /* if DD is not set pending work has not been completed */ 8243 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8244 break; 8245 8246 /* clear next_to_watch to prevent false hangs */ 8247 tx_buffer->next_to_watch = NULL; 8248 8249 /* update the statistics for this packet */ 8250 total_bytes += tx_buffer->bytecount; 8251 total_packets += tx_buffer->gso_segs; 8252 8253 /* free the skb */ 8254 if (tx_buffer->type == IGB_TYPE_SKB) 8255 napi_consume_skb(tx_buffer->skb, napi_budget); 8256 else 8257 xdp_return_frame(tx_buffer->xdpf); 8258 8259 /* unmap skb header data */ 8260 dma_unmap_single(tx_ring->dev, 8261 dma_unmap_addr(tx_buffer, dma), 8262 dma_unmap_len(tx_buffer, len), 8263 DMA_TO_DEVICE); 8264 8265 /* clear tx_buffer data */ 8266 dma_unmap_len_set(tx_buffer, len, 0); 8267 8268 /* clear last DMA location and unmap remaining buffers */ 8269 while (tx_desc != eop_desc) { 8270 tx_buffer++; 8271 tx_desc++; 8272 i++; 8273 if (unlikely(!i)) { 8274 i -= tx_ring->count; 8275 tx_buffer = tx_ring->tx_buffer_info; 8276 tx_desc = IGB_TX_DESC(tx_ring, 0); 8277 } 8278 8279 /* unmap any remaining paged data */ 8280 if (dma_unmap_len(tx_buffer, len)) { 8281 dma_unmap_page(tx_ring->dev, 8282 dma_unmap_addr(tx_buffer, dma), 8283 dma_unmap_len(tx_buffer, len), 8284 DMA_TO_DEVICE); 8285 dma_unmap_len_set(tx_buffer, len, 0); 8286 } 8287 } 8288 8289 /* move us one more past the eop_desc for start of next pkt */ 8290 tx_buffer++; 8291 tx_desc++; 8292 i++; 8293 if (unlikely(!i)) { 8294 i -= tx_ring->count; 8295 tx_buffer = tx_ring->tx_buffer_info; 8296 tx_desc = IGB_TX_DESC(tx_ring, 0); 8297 } 8298 8299 /* issue prefetch for next Tx descriptor */ 8300 prefetch(tx_desc); 8301 8302 /* update budget accounting */ 8303 budget--; 8304 } while (likely(budget)); 8305 8306 netdev_tx_completed_queue(txring_txq(tx_ring), 8307 total_packets, total_bytes); 8308 i += tx_ring->count; 8309 tx_ring->next_to_clean = i; 8310 u64_stats_update_begin(&tx_ring->tx_syncp); 8311 tx_ring->tx_stats.bytes += total_bytes; 8312 tx_ring->tx_stats.packets += total_packets; 8313 u64_stats_update_end(&tx_ring->tx_syncp); 8314 q_vector->tx.total_bytes += total_bytes; 8315 q_vector->tx.total_packets += total_packets; 8316 8317 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8318 struct e1000_hw *hw = &adapter->hw; 8319 8320 /* Detect a transmit hang in hardware, this serializes the 8321 * check with the clearing of time_stamp and movement of i 8322 */ 8323 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8324 if (tx_buffer->next_to_watch && 8325 time_after(jiffies, tx_buffer->time_stamp + 8326 (adapter->tx_timeout_factor * HZ)) && 8327 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8328 8329 /* detected Tx unit hang */ 8330 dev_err(tx_ring->dev, 8331 "Detected Tx Unit Hang\n" 8332 " Tx Queue <%d>\n" 8333 " TDH <%x>\n" 8334 " TDT <%x>\n" 8335 " next_to_use <%x>\n" 8336 " next_to_clean <%x>\n" 8337 "buffer_info[next_to_clean]\n" 8338 " time_stamp <%lx>\n" 8339 " next_to_watch <%p>\n" 8340 " jiffies <%lx>\n" 8341 " desc.status <%x>\n", 8342 tx_ring->queue_index, 8343 rd32(E1000_TDH(tx_ring->reg_idx)), 8344 readl(tx_ring->tail), 8345 tx_ring->next_to_use, 8346 tx_ring->next_to_clean, 8347 tx_buffer->time_stamp, 8348 tx_buffer->next_to_watch, 8349 jiffies, 8350 tx_buffer->next_to_watch->wb.status); 8351 netif_stop_subqueue(tx_ring->netdev, 8352 tx_ring->queue_index); 8353 8354 /* we are about to reset, no point in enabling stuff */ 8355 return true; 8356 } 8357 } 8358 8359 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8360 if (unlikely(total_packets && 8361 netif_carrier_ok(tx_ring->netdev) && 8362 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8363 /* Make sure that anybody stopping the queue after this 8364 * sees the new next_to_clean. 8365 */ 8366 smp_mb(); 8367 if (__netif_subqueue_stopped(tx_ring->netdev, 8368 tx_ring->queue_index) && 8369 !(test_bit(__IGB_DOWN, &adapter->state))) { 8370 netif_wake_subqueue(tx_ring->netdev, 8371 tx_ring->queue_index); 8372 8373 u64_stats_update_begin(&tx_ring->tx_syncp); 8374 tx_ring->tx_stats.restart_queue++; 8375 u64_stats_update_end(&tx_ring->tx_syncp); 8376 } 8377 } 8378 8379 return !!budget; 8380 } 8381 8382 /** 8383 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8384 * @rx_ring: rx descriptor ring to store buffers on 8385 * @old_buff: donor buffer to have page reused 8386 * 8387 * Synchronizes page for reuse by the adapter 8388 **/ 8389 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8390 struct igb_rx_buffer *old_buff) 8391 { 8392 struct igb_rx_buffer *new_buff; 8393 u16 nta = rx_ring->next_to_alloc; 8394 8395 new_buff = &rx_ring->rx_buffer_info[nta]; 8396 8397 /* update, and store next to alloc */ 8398 nta++; 8399 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8400 8401 /* Transfer page from old buffer to new buffer. 8402 * Move each member individually to avoid possible store 8403 * forwarding stalls. 8404 */ 8405 new_buff->dma = old_buff->dma; 8406 new_buff->page = old_buff->page; 8407 new_buff->page_offset = old_buff->page_offset; 8408 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8409 } 8410 8411 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8412 int rx_buf_pgcnt) 8413 { 8414 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8415 struct page *page = rx_buffer->page; 8416 8417 /* avoid re-using remote and pfmemalloc pages */ 8418 if (!dev_page_is_reusable(page)) 8419 return false; 8420 8421 #if (PAGE_SIZE < 8192) 8422 /* if we are only owner of page we can reuse it */ 8423 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8424 return false; 8425 #else 8426 #define IGB_LAST_OFFSET \ 8427 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8428 8429 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8430 return false; 8431 #endif 8432 8433 /* If we have drained the page fragment pool we need to update 8434 * the pagecnt_bias and page count so that we fully restock the 8435 * number of references the driver holds. 8436 */ 8437 if (unlikely(pagecnt_bias == 1)) { 8438 page_ref_add(page, USHRT_MAX - 1); 8439 rx_buffer->pagecnt_bias = USHRT_MAX; 8440 } 8441 8442 return true; 8443 } 8444 8445 /** 8446 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8447 * @rx_ring: rx descriptor ring to transact packets on 8448 * @rx_buffer: buffer containing page to add 8449 * @skb: sk_buff to place the data into 8450 * @size: size of buffer to be added 8451 * 8452 * This function will add the data contained in rx_buffer->page to the skb. 8453 **/ 8454 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8455 struct igb_rx_buffer *rx_buffer, 8456 struct sk_buff *skb, 8457 unsigned int size) 8458 { 8459 #if (PAGE_SIZE < 8192) 8460 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8461 #else 8462 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8463 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8464 SKB_DATA_ALIGN(size); 8465 #endif 8466 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8467 rx_buffer->page_offset, size, truesize); 8468 #if (PAGE_SIZE < 8192) 8469 rx_buffer->page_offset ^= truesize; 8470 #else 8471 rx_buffer->page_offset += truesize; 8472 #endif 8473 } 8474 8475 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8476 struct igb_rx_buffer *rx_buffer, 8477 struct xdp_buff *xdp, 8478 ktime_t timestamp) 8479 { 8480 #if (PAGE_SIZE < 8192) 8481 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8482 #else 8483 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8484 xdp->data_hard_start); 8485 #endif 8486 unsigned int size = xdp->data_end - xdp->data; 8487 unsigned int headlen; 8488 struct sk_buff *skb; 8489 8490 /* prefetch first cache line of first page */ 8491 net_prefetch(xdp->data); 8492 8493 /* allocate a skb to store the frags */ 8494 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8495 if (unlikely(!skb)) 8496 return NULL; 8497 8498 if (timestamp) 8499 skb_hwtstamps(skb)->hwtstamp = timestamp; 8500 8501 /* Determine available headroom for copy */ 8502 headlen = size; 8503 if (headlen > IGB_RX_HDR_LEN) 8504 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8505 8506 /* align pull length to size of long to optimize memcpy performance */ 8507 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8508 8509 /* update all of the pointers */ 8510 size -= headlen; 8511 if (size) { 8512 skb_add_rx_frag(skb, 0, rx_buffer->page, 8513 (xdp->data + headlen) - page_address(rx_buffer->page), 8514 size, truesize); 8515 #if (PAGE_SIZE < 8192) 8516 rx_buffer->page_offset ^= truesize; 8517 #else 8518 rx_buffer->page_offset += truesize; 8519 #endif 8520 } else { 8521 rx_buffer->pagecnt_bias++; 8522 } 8523 8524 return skb; 8525 } 8526 8527 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8528 struct igb_rx_buffer *rx_buffer, 8529 struct xdp_buff *xdp, 8530 ktime_t timestamp) 8531 { 8532 #if (PAGE_SIZE < 8192) 8533 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8534 #else 8535 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8536 SKB_DATA_ALIGN(xdp->data_end - 8537 xdp->data_hard_start); 8538 #endif 8539 unsigned int metasize = xdp->data - xdp->data_meta; 8540 struct sk_buff *skb; 8541 8542 /* prefetch first cache line of first page */ 8543 net_prefetch(xdp->data_meta); 8544 8545 /* build an skb around the page buffer */ 8546 skb = napi_build_skb(xdp->data_hard_start, truesize); 8547 if (unlikely(!skb)) 8548 return NULL; 8549 8550 /* update pointers within the skb to store the data */ 8551 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8552 __skb_put(skb, xdp->data_end - xdp->data); 8553 8554 if (metasize) 8555 skb_metadata_set(skb, metasize); 8556 8557 if (timestamp) 8558 skb_hwtstamps(skb)->hwtstamp = timestamp; 8559 8560 /* update buffer offset */ 8561 #if (PAGE_SIZE < 8192) 8562 rx_buffer->page_offset ^= truesize; 8563 #else 8564 rx_buffer->page_offset += truesize; 8565 #endif 8566 8567 return skb; 8568 } 8569 8570 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8571 struct igb_ring *rx_ring, 8572 struct xdp_buff *xdp) 8573 { 8574 int err, result = IGB_XDP_PASS; 8575 struct bpf_prog *xdp_prog; 8576 u32 act; 8577 8578 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8579 8580 if (!xdp_prog) 8581 goto xdp_out; 8582 8583 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8584 8585 act = bpf_prog_run_xdp(xdp_prog, xdp); 8586 switch (act) { 8587 case XDP_PASS: 8588 break; 8589 case XDP_TX: 8590 result = igb_xdp_xmit_back(adapter, xdp); 8591 if (result == IGB_XDP_CONSUMED) 8592 goto out_failure; 8593 break; 8594 case XDP_REDIRECT: 8595 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8596 if (err) 8597 goto out_failure; 8598 result = IGB_XDP_REDIR; 8599 break; 8600 default: 8601 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8602 fallthrough; 8603 case XDP_ABORTED: 8604 out_failure: 8605 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8606 fallthrough; 8607 case XDP_DROP: 8608 result = IGB_XDP_CONSUMED; 8609 break; 8610 } 8611 xdp_out: 8612 return ERR_PTR(-result); 8613 } 8614 8615 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8616 unsigned int size) 8617 { 8618 unsigned int truesize; 8619 8620 #if (PAGE_SIZE < 8192) 8621 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8622 #else 8623 truesize = ring_uses_build_skb(rx_ring) ? 8624 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8625 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8626 SKB_DATA_ALIGN(size); 8627 #endif 8628 return truesize; 8629 } 8630 8631 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8632 struct igb_rx_buffer *rx_buffer, 8633 unsigned int size) 8634 { 8635 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8636 #if (PAGE_SIZE < 8192) 8637 rx_buffer->page_offset ^= truesize; 8638 #else 8639 rx_buffer->page_offset += truesize; 8640 #endif 8641 } 8642 8643 static inline void igb_rx_checksum(struct igb_ring *ring, 8644 union e1000_adv_rx_desc *rx_desc, 8645 struct sk_buff *skb) 8646 { 8647 skb_checksum_none_assert(skb); 8648 8649 /* Ignore Checksum bit is set */ 8650 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8651 return; 8652 8653 /* Rx checksum disabled via ethtool */ 8654 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8655 return; 8656 8657 /* TCP/UDP checksum error bit is set */ 8658 if (igb_test_staterr(rx_desc, 8659 E1000_RXDEXT_STATERR_TCPE | 8660 E1000_RXDEXT_STATERR_IPE)) { 8661 /* work around errata with sctp packets where the TCPE aka 8662 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8663 * packets, (aka let the stack check the crc32c) 8664 */ 8665 if (!((skb->len == 60) && 8666 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8667 u64_stats_update_begin(&ring->rx_syncp); 8668 ring->rx_stats.csum_err++; 8669 u64_stats_update_end(&ring->rx_syncp); 8670 } 8671 /* let the stack verify checksum errors */ 8672 return; 8673 } 8674 /* It must be a TCP or UDP packet with a valid checksum */ 8675 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8676 E1000_RXD_STAT_UDPCS)) 8677 skb->ip_summed = CHECKSUM_UNNECESSARY; 8678 8679 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8680 le32_to_cpu(rx_desc->wb.upper.status_error)); 8681 } 8682 8683 static inline void igb_rx_hash(struct igb_ring *ring, 8684 union e1000_adv_rx_desc *rx_desc, 8685 struct sk_buff *skb) 8686 { 8687 if (ring->netdev->features & NETIF_F_RXHASH) 8688 skb_set_hash(skb, 8689 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8690 PKT_HASH_TYPE_L3); 8691 } 8692 8693 /** 8694 * igb_is_non_eop - process handling of non-EOP buffers 8695 * @rx_ring: Rx ring being processed 8696 * @rx_desc: Rx descriptor for current buffer 8697 * 8698 * This function updates next to clean. If the buffer is an EOP buffer 8699 * this function exits returning false, otherwise it will place the 8700 * sk_buff in the next buffer to be chained and return true indicating 8701 * that this is in fact a non-EOP buffer. 8702 **/ 8703 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8704 union e1000_adv_rx_desc *rx_desc) 8705 { 8706 u32 ntc = rx_ring->next_to_clean + 1; 8707 8708 /* fetch, update, and store next to clean */ 8709 ntc = (ntc < rx_ring->count) ? ntc : 0; 8710 rx_ring->next_to_clean = ntc; 8711 8712 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8713 8714 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8715 return false; 8716 8717 return true; 8718 } 8719 8720 /** 8721 * igb_cleanup_headers - Correct corrupted or empty headers 8722 * @rx_ring: rx descriptor ring packet is being transacted on 8723 * @rx_desc: pointer to the EOP Rx descriptor 8724 * @skb: pointer to current skb being fixed 8725 * 8726 * Address the case where we are pulling data in on pages only 8727 * and as such no data is present in the skb header. 8728 * 8729 * In addition if skb is not at least 60 bytes we need to pad it so that 8730 * it is large enough to qualify as a valid Ethernet frame. 8731 * 8732 * Returns true if an error was encountered and skb was freed. 8733 **/ 8734 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8735 union e1000_adv_rx_desc *rx_desc, 8736 struct sk_buff *skb) 8737 { 8738 /* XDP packets use error pointer so abort at this point */ 8739 if (IS_ERR(skb)) 8740 return true; 8741 8742 if (unlikely((igb_test_staterr(rx_desc, 8743 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8744 struct net_device *netdev = rx_ring->netdev; 8745 if (!(netdev->features & NETIF_F_RXALL)) { 8746 dev_kfree_skb_any(skb); 8747 return true; 8748 } 8749 } 8750 8751 /* if eth_skb_pad returns an error the skb was freed */ 8752 if (eth_skb_pad(skb)) 8753 return true; 8754 8755 return false; 8756 } 8757 8758 /** 8759 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8760 * @rx_ring: rx descriptor ring packet is being transacted on 8761 * @rx_desc: pointer to the EOP Rx descriptor 8762 * @skb: pointer to current skb being populated 8763 * 8764 * This function checks the ring, descriptor, and packet information in 8765 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8766 * other fields within the skb. 8767 **/ 8768 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8769 union e1000_adv_rx_desc *rx_desc, 8770 struct sk_buff *skb) 8771 { 8772 struct net_device *dev = rx_ring->netdev; 8773 8774 igb_rx_hash(rx_ring, rx_desc, skb); 8775 8776 igb_rx_checksum(rx_ring, rx_desc, skb); 8777 8778 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8779 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8780 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8781 8782 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8783 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8784 u16 vid; 8785 8786 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8787 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8788 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8789 else 8790 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8791 8792 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8793 } 8794 8795 skb_record_rx_queue(skb, rx_ring->queue_index); 8796 8797 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8798 } 8799 8800 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8801 { 8802 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8803 } 8804 8805 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8806 const unsigned int size, int *rx_buf_pgcnt) 8807 { 8808 struct igb_rx_buffer *rx_buffer; 8809 8810 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8811 *rx_buf_pgcnt = 8812 #if (PAGE_SIZE < 8192) 8813 page_count(rx_buffer->page); 8814 #else 8815 0; 8816 #endif 8817 prefetchw(rx_buffer->page); 8818 8819 /* we are reusing so sync this buffer for CPU use */ 8820 dma_sync_single_range_for_cpu(rx_ring->dev, 8821 rx_buffer->dma, 8822 rx_buffer->page_offset, 8823 size, 8824 DMA_FROM_DEVICE); 8825 8826 rx_buffer->pagecnt_bias--; 8827 8828 return rx_buffer; 8829 } 8830 8831 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8832 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8833 { 8834 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8835 /* hand second half of page back to the ring */ 8836 igb_reuse_rx_page(rx_ring, rx_buffer); 8837 } else { 8838 /* We are not reusing the buffer so unmap it and free 8839 * any references we are holding to it 8840 */ 8841 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8842 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8843 IGB_RX_DMA_ATTR); 8844 __page_frag_cache_drain(rx_buffer->page, 8845 rx_buffer->pagecnt_bias); 8846 } 8847 8848 /* clear contents of rx_buffer */ 8849 rx_buffer->page = NULL; 8850 } 8851 8852 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8853 { 8854 struct igb_adapter *adapter = q_vector->adapter; 8855 struct igb_ring *rx_ring = q_vector->rx.ring; 8856 struct sk_buff *skb = rx_ring->skb; 8857 unsigned int total_bytes = 0, total_packets = 0; 8858 u16 cleaned_count = igb_desc_unused(rx_ring); 8859 unsigned int xdp_xmit = 0; 8860 struct xdp_buff xdp; 8861 u32 frame_sz = 0; 8862 int rx_buf_pgcnt; 8863 8864 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8865 #if (PAGE_SIZE < 8192) 8866 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8867 #endif 8868 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8869 8870 while (likely(total_packets < budget)) { 8871 union e1000_adv_rx_desc *rx_desc; 8872 struct igb_rx_buffer *rx_buffer; 8873 ktime_t timestamp = 0; 8874 int pkt_offset = 0; 8875 unsigned int size; 8876 void *pktbuf; 8877 8878 /* return some buffers to hardware, one at a time is too slow */ 8879 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8880 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8881 cleaned_count = 0; 8882 } 8883 8884 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8885 size = le16_to_cpu(rx_desc->wb.upper.length); 8886 if (!size) 8887 break; 8888 8889 /* This memory barrier is needed to keep us from reading 8890 * any other fields out of the rx_desc until we know the 8891 * descriptor has been written back 8892 */ 8893 dma_rmb(); 8894 8895 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8896 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8897 8898 /* pull rx packet timestamp if available and valid */ 8899 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8900 int ts_hdr_len; 8901 8902 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8903 pktbuf, ×tamp); 8904 8905 pkt_offset += ts_hdr_len; 8906 size -= ts_hdr_len; 8907 } 8908 8909 /* retrieve a buffer from the ring */ 8910 if (!skb) { 8911 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8912 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8913 8914 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8915 xdp_buff_clear_frags_flag(&xdp); 8916 #if (PAGE_SIZE > 4096) 8917 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8918 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8919 #endif 8920 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8921 } 8922 8923 if (IS_ERR(skb)) { 8924 unsigned int xdp_res = -PTR_ERR(skb); 8925 8926 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8927 xdp_xmit |= xdp_res; 8928 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8929 } else { 8930 rx_buffer->pagecnt_bias++; 8931 } 8932 total_packets++; 8933 total_bytes += size; 8934 } else if (skb) 8935 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8936 else if (ring_uses_build_skb(rx_ring)) 8937 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8938 timestamp); 8939 else 8940 skb = igb_construct_skb(rx_ring, rx_buffer, 8941 &xdp, timestamp); 8942 8943 /* exit if we failed to retrieve a buffer */ 8944 if (!skb) { 8945 rx_ring->rx_stats.alloc_failed++; 8946 rx_buffer->pagecnt_bias++; 8947 break; 8948 } 8949 8950 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8951 cleaned_count++; 8952 8953 /* fetch next buffer in frame if non-eop */ 8954 if (igb_is_non_eop(rx_ring, rx_desc)) 8955 continue; 8956 8957 /* verify the packet layout is correct */ 8958 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8959 skb = NULL; 8960 continue; 8961 } 8962 8963 /* probably a little skewed due to removing CRC */ 8964 total_bytes += skb->len; 8965 8966 /* populate checksum, timestamp, VLAN, and protocol */ 8967 igb_process_skb_fields(rx_ring, rx_desc, skb); 8968 8969 napi_gro_receive(&q_vector->napi, skb); 8970 8971 /* reset skb pointer */ 8972 skb = NULL; 8973 8974 /* update budget accounting */ 8975 total_packets++; 8976 } 8977 8978 /* place incomplete frames back on ring for completion */ 8979 rx_ring->skb = skb; 8980 8981 if (xdp_xmit & IGB_XDP_REDIR) 8982 xdp_do_flush(); 8983 8984 if (xdp_xmit & IGB_XDP_TX) { 8985 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8986 8987 igb_xdp_ring_update_tail(tx_ring); 8988 } 8989 8990 u64_stats_update_begin(&rx_ring->rx_syncp); 8991 rx_ring->rx_stats.packets += total_packets; 8992 rx_ring->rx_stats.bytes += total_bytes; 8993 u64_stats_update_end(&rx_ring->rx_syncp); 8994 q_vector->rx.total_packets += total_packets; 8995 q_vector->rx.total_bytes += total_bytes; 8996 8997 if (cleaned_count) 8998 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8999 9000 return total_packets; 9001 } 9002 9003 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9004 struct igb_rx_buffer *bi) 9005 { 9006 struct page *page = bi->page; 9007 dma_addr_t dma; 9008 9009 /* since we are recycling buffers we should seldom need to alloc */ 9010 if (likely(page)) 9011 return true; 9012 9013 /* alloc new page for storage */ 9014 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9015 if (unlikely(!page)) { 9016 rx_ring->rx_stats.alloc_failed++; 9017 return false; 9018 } 9019 9020 /* map page for use */ 9021 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9022 igb_rx_pg_size(rx_ring), 9023 DMA_FROM_DEVICE, 9024 IGB_RX_DMA_ATTR); 9025 9026 /* if mapping failed free memory back to system since 9027 * there isn't much point in holding memory we can't use 9028 */ 9029 if (dma_mapping_error(rx_ring->dev, dma)) { 9030 __free_pages(page, igb_rx_pg_order(rx_ring)); 9031 9032 rx_ring->rx_stats.alloc_failed++; 9033 return false; 9034 } 9035 9036 bi->dma = dma; 9037 bi->page = page; 9038 bi->page_offset = igb_rx_offset(rx_ring); 9039 page_ref_add(page, USHRT_MAX - 1); 9040 bi->pagecnt_bias = USHRT_MAX; 9041 9042 return true; 9043 } 9044 9045 /** 9046 * igb_alloc_rx_buffers - Replace used receive buffers 9047 * @rx_ring: rx descriptor ring to allocate new receive buffers 9048 * @cleaned_count: count of buffers to allocate 9049 **/ 9050 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9051 { 9052 union e1000_adv_rx_desc *rx_desc; 9053 struct igb_rx_buffer *bi; 9054 u16 i = rx_ring->next_to_use; 9055 u16 bufsz; 9056 9057 /* nothing to do */ 9058 if (!cleaned_count) 9059 return; 9060 9061 rx_desc = IGB_RX_DESC(rx_ring, i); 9062 bi = &rx_ring->rx_buffer_info[i]; 9063 i -= rx_ring->count; 9064 9065 bufsz = igb_rx_bufsz(rx_ring); 9066 9067 do { 9068 if (!igb_alloc_mapped_page(rx_ring, bi)) 9069 break; 9070 9071 /* sync the buffer for use by the device */ 9072 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9073 bi->page_offset, bufsz, 9074 DMA_FROM_DEVICE); 9075 9076 /* Refresh the desc even if buffer_addrs didn't change 9077 * because each write-back erases this info. 9078 */ 9079 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9080 9081 rx_desc++; 9082 bi++; 9083 i++; 9084 if (unlikely(!i)) { 9085 rx_desc = IGB_RX_DESC(rx_ring, 0); 9086 bi = rx_ring->rx_buffer_info; 9087 i -= rx_ring->count; 9088 } 9089 9090 /* clear the length for the next_to_use descriptor */ 9091 rx_desc->wb.upper.length = 0; 9092 9093 cleaned_count--; 9094 } while (cleaned_count); 9095 9096 i += rx_ring->count; 9097 9098 if (rx_ring->next_to_use != i) { 9099 /* record the next descriptor to use */ 9100 rx_ring->next_to_use = i; 9101 9102 /* update next to alloc since we have filled the ring */ 9103 rx_ring->next_to_alloc = i; 9104 9105 /* Force memory writes to complete before letting h/w 9106 * know there are new descriptors to fetch. (Only 9107 * applicable for weak-ordered memory model archs, 9108 * such as IA-64). 9109 */ 9110 dma_wmb(); 9111 writel(i, rx_ring->tail); 9112 } 9113 } 9114 9115 /** 9116 * igb_mii_ioctl - 9117 * @netdev: pointer to netdev struct 9118 * @ifr: interface structure 9119 * @cmd: ioctl command to execute 9120 **/ 9121 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9122 { 9123 struct igb_adapter *adapter = netdev_priv(netdev); 9124 struct mii_ioctl_data *data = if_mii(ifr); 9125 9126 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9127 return -EOPNOTSUPP; 9128 9129 switch (cmd) { 9130 case SIOCGMIIPHY: 9131 data->phy_id = adapter->hw.phy.addr; 9132 break; 9133 case SIOCGMIIREG: 9134 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9135 &data->val_out)) 9136 return -EIO; 9137 break; 9138 case SIOCSMIIREG: 9139 default: 9140 return -EOPNOTSUPP; 9141 } 9142 return 0; 9143 } 9144 9145 /** 9146 * igb_ioctl - 9147 * @netdev: pointer to netdev struct 9148 * @ifr: interface structure 9149 * @cmd: ioctl command to execute 9150 **/ 9151 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9152 { 9153 switch (cmd) { 9154 case SIOCGMIIPHY: 9155 case SIOCGMIIREG: 9156 case SIOCSMIIREG: 9157 return igb_mii_ioctl(netdev, ifr, cmd); 9158 case SIOCGHWTSTAMP: 9159 return igb_ptp_get_ts_config(netdev, ifr); 9160 case SIOCSHWTSTAMP: 9161 return igb_ptp_set_ts_config(netdev, ifr); 9162 default: 9163 return -EOPNOTSUPP; 9164 } 9165 } 9166 9167 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9168 { 9169 struct igb_adapter *adapter = hw->back; 9170 9171 pci_read_config_word(adapter->pdev, reg, value); 9172 } 9173 9174 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9175 { 9176 struct igb_adapter *adapter = hw->back; 9177 9178 pci_write_config_word(adapter->pdev, reg, *value); 9179 } 9180 9181 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9182 { 9183 struct igb_adapter *adapter = hw->back; 9184 9185 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9186 return -E1000_ERR_CONFIG; 9187 9188 return 0; 9189 } 9190 9191 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9192 { 9193 struct igb_adapter *adapter = hw->back; 9194 9195 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9196 return -E1000_ERR_CONFIG; 9197 9198 return 0; 9199 } 9200 9201 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9202 { 9203 struct igb_adapter *adapter = netdev_priv(netdev); 9204 struct e1000_hw *hw = &adapter->hw; 9205 u32 ctrl, rctl; 9206 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9207 9208 if (enable) { 9209 /* enable VLAN tag insert/strip */ 9210 ctrl = rd32(E1000_CTRL); 9211 ctrl |= E1000_CTRL_VME; 9212 wr32(E1000_CTRL, ctrl); 9213 9214 /* Disable CFI check */ 9215 rctl = rd32(E1000_RCTL); 9216 rctl &= ~E1000_RCTL_CFIEN; 9217 wr32(E1000_RCTL, rctl); 9218 } else { 9219 /* disable VLAN tag insert/strip */ 9220 ctrl = rd32(E1000_CTRL); 9221 ctrl &= ~E1000_CTRL_VME; 9222 wr32(E1000_CTRL, ctrl); 9223 } 9224 9225 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9226 } 9227 9228 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9229 __be16 proto, u16 vid) 9230 { 9231 struct igb_adapter *adapter = netdev_priv(netdev); 9232 struct e1000_hw *hw = &adapter->hw; 9233 int pf_id = adapter->vfs_allocated_count; 9234 9235 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9236 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9237 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9238 9239 set_bit(vid, adapter->active_vlans); 9240 9241 return 0; 9242 } 9243 9244 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9245 __be16 proto, u16 vid) 9246 { 9247 struct igb_adapter *adapter = netdev_priv(netdev); 9248 int pf_id = adapter->vfs_allocated_count; 9249 struct e1000_hw *hw = &adapter->hw; 9250 9251 /* remove VID from filter table */ 9252 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9253 igb_vfta_set(hw, vid, pf_id, false, true); 9254 9255 clear_bit(vid, adapter->active_vlans); 9256 9257 return 0; 9258 } 9259 9260 static void igb_restore_vlan(struct igb_adapter *adapter) 9261 { 9262 u16 vid = 1; 9263 9264 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9265 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9266 9267 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9268 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9269 } 9270 9271 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9272 { 9273 struct pci_dev *pdev = adapter->pdev; 9274 struct e1000_mac_info *mac = &adapter->hw.mac; 9275 9276 mac->autoneg = 0; 9277 9278 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9279 * for the switch() below to work 9280 */ 9281 if ((spd & 1) || (dplx & ~1)) 9282 goto err_inval; 9283 9284 /* Fiber NIC's only allow 1000 gbps Full duplex 9285 * and 100Mbps Full duplex for 100baseFx sfp 9286 */ 9287 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9288 switch (spd + dplx) { 9289 case SPEED_10 + DUPLEX_HALF: 9290 case SPEED_10 + DUPLEX_FULL: 9291 case SPEED_100 + DUPLEX_HALF: 9292 goto err_inval; 9293 default: 9294 break; 9295 } 9296 } 9297 9298 switch (spd + dplx) { 9299 case SPEED_10 + DUPLEX_HALF: 9300 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9301 break; 9302 case SPEED_10 + DUPLEX_FULL: 9303 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9304 break; 9305 case SPEED_100 + DUPLEX_HALF: 9306 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9307 break; 9308 case SPEED_100 + DUPLEX_FULL: 9309 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9310 break; 9311 case SPEED_1000 + DUPLEX_FULL: 9312 mac->autoneg = 1; 9313 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9314 break; 9315 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9316 default: 9317 goto err_inval; 9318 } 9319 9320 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9321 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9322 9323 return 0; 9324 9325 err_inval: 9326 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9327 return -EINVAL; 9328 } 9329 9330 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9331 bool runtime) 9332 { 9333 struct net_device *netdev = pci_get_drvdata(pdev); 9334 struct igb_adapter *adapter = netdev_priv(netdev); 9335 struct e1000_hw *hw = &adapter->hw; 9336 u32 ctrl, rctl, status; 9337 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9338 bool wake; 9339 9340 rtnl_lock(); 9341 netif_device_detach(netdev); 9342 9343 if (netif_running(netdev)) 9344 __igb_close(netdev, true); 9345 9346 igb_ptp_suspend(adapter); 9347 9348 igb_clear_interrupt_scheme(adapter); 9349 rtnl_unlock(); 9350 9351 status = rd32(E1000_STATUS); 9352 if (status & E1000_STATUS_LU) 9353 wufc &= ~E1000_WUFC_LNKC; 9354 9355 if (wufc) { 9356 igb_setup_rctl(adapter); 9357 igb_set_rx_mode(netdev); 9358 9359 /* turn on all-multi mode if wake on multicast is enabled */ 9360 if (wufc & E1000_WUFC_MC) { 9361 rctl = rd32(E1000_RCTL); 9362 rctl |= E1000_RCTL_MPE; 9363 wr32(E1000_RCTL, rctl); 9364 } 9365 9366 ctrl = rd32(E1000_CTRL); 9367 ctrl |= E1000_CTRL_ADVD3WUC; 9368 wr32(E1000_CTRL, ctrl); 9369 9370 /* Allow time for pending master requests to run */ 9371 igb_disable_pcie_master(hw); 9372 9373 wr32(E1000_WUC, E1000_WUC_PME_EN); 9374 wr32(E1000_WUFC, wufc); 9375 } else { 9376 wr32(E1000_WUC, 0); 9377 wr32(E1000_WUFC, 0); 9378 } 9379 9380 wake = wufc || adapter->en_mng_pt; 9381 if (!wake) 9382 igb_power_down_link(adapter); 9383 else 9384 igb_power_up_link(adapter); 9385 9386 if (enable_wake) 9387 *enable_wake = wake; 9388 9389 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9390 * would have already happened in close and is redundant. 9391 */ 9392 igb_release_hw_control(adapter); 9393 9394 pci_disable_device(pdev); 9395 9396 return 0; 9397 } 9398 9399 static void igb_deliver_wake_packet(struct net_device *netdev) 9400 { 9401 struct igb_adapter *adapter = netdev_priv(netdev); 9402 struct e1000_hw *hw = &adapter->hw; 9403 struct sk_buff *skb; 9404 u32 wupl; 9405 9406 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9407 9408 /* WUPM stores only the first 128 bytes of the wake packet. 9409 * Read the packet only if we have the whole thing. 9410 */ 9411 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9412 return; 9413 9414 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9415 if (!skb) 9416 return; 9417 9418 skb_put(skb, wupl); 9419 9420 /* Ensure reads are 32-bit aligned */ 9421 wupl = roundup(wupl, 4); 9422 9423 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9424 9425 skb->protocol = eth_type_trans(skb, netdev); 9426 netif_rx(skb); 9427 } 9428 9429 static int igb_suspend(struct device *dev) 9430 { 9431 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9432 } 9433 9434 static int __igb_resume(struct device *dev, bool rpm) 9435 { 9436 struct pci_dev *pdev = to_pci_dev(dev); 9437 struct net_device *netdev = pci_get_drvdata(pdev); 9438 struct igb_adapter *adapter = netdev_priv(netdev); 9439 struct e1000_hw *hw = &adapter->hw; 9440 u32 err, val; 9441 9442 pci_set_power_state(pdev, PCI_D0); 9443 pci_restore_state(pdev); 9444 pci_save_state(pdev); 9445 9446 if (!pci_device_is_present(pdev)) 9447 return -ENODEV; 9448 err = pci_enable_device_mem(pdev); 9449 if (err) { 9450 dev_err(&pdev->dev, 9451 "igb: Cannot enable PCI device from suspend\n"); 9452 return err; 9453 } 9454 pci_set_master(pdev); 9455 9456 pci_enable_wake(pdev, PCI_D3hot, 0); 9457 pci_enable_wake(pdev, PCI_D3cold, 0); 9458 9459 if (igb_init_interrupt_scheme(adapter, true)) { 9460 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9461 return -ENOMEM; 9462 } 9463 9464 igb_reset(adapter); 9465 9466 /* let the f/w know that the h/w is now under the control of the 9467 * driver. 9468 */ 9469 igb_get_hw_control(adapter); 9470 9471 val = rd32(E1000_WUS); 9472 if (val & WAKE_PKT_WUS) 9473 igb_deliver_wake_packet(netdev); 9474 9475 wr32(E1000_WUS, ~0); 9476 9477 if (!rpm) 9478 rtnl_lock(); 9479 if (!err && netif_running(netdev)) 9480 err = __igb_open(netdev, true); 9481 9482 if (!err) 9483 netif_device_attach(netdev); 9484 if (!rpm) 9485 rtnl_unlock(); 9486 9487 return err; 9488 } 9489 9490 static int igb_resume(struct device *dev) 9491 { 9492 return __igb_resume(dev, false); 9493 } 9494 9495 static int igb_runtime_idle(struct device *dev) 9496 { 9497 struct net_device *netdev = dev_get_drvdata(dev); 9498 struct igb_adapter *adapter = netdev_priv(netdev); 9499 9500 if (!igb_has_link(adapter)) 9501 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9502 9503 return -EBUSY; 9504 } 9505 9506 static int igb_runtime_suspend(struct device *dev) 9507 { 9508 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9509 } 9510 9511 static int igb_runtime_resume(struct device *dev) 9512 { 9513 return __igb_resume(dev, true); 9514 } 9515 9516 static void igb_shutdown(struct pci_dev *pdev) 9517 { 9518 bool wake; 9519 9520 __igb_shutdown(pdev, &wake, 0); 9521 9522 if (system_state == SYSTEM_POWER_OFF) { 9523 pci_wake_from_d3(pdev, wake); 9524 pci_set_power_state(pdev, PCI_D3hot); 9525 } 9526 } 9527 9528 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9529 { 9530 #ifdef CONFIG_PCI_IOV 9531 int err; 9532 9533 if (num_vfs == 0) { 9534 return igb_disable_sriov(dev, true); 9535 } else { 9536 err = igb_enable_sriov(dev, num_vfs, true); 9537 return err ? err : num_vfs; 9538 } 9539 #endif 9540 return 0; 9541 } 9542 9543 /** 9544 * igb_io_error_detected - called when PCI error is detected 9545 * @pdev: Pointer to PCI device 9546 * @state: The current pci connection state 9547 * 9548 * This function is called after a PCI bus error affecting 9549 * this device has been detected. 9550 **/ 9551 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9552 pci_channel_state_t state) 9553 { 9554 struct net_device *netdev = pci_get_drvdata(pdev); 9555 struct igb_adapter *adapter = netdev_priv(netdev); 9556 9557 if (state == pci_channel_io_normal) { 9558 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9559 return PCI_ERS_RESULT_CAN_RECOVER; 9560 } 9561 9562 netif_device_detach(netdev); 9563 9564 if (state == pci_channel_io_perm_failure) 9565 return PCI_ERS_RESULT_DISCONNECT; 9566 9567 if (netif_running(netdev)) 9568 igb_down(adapter); 9569 pci_disable_device(pdev); 9570 9571 /* Request a slot reset. */ 9572 return PCI_ERS_RESULT_NEED_RESET; 9573 } 9574 9575 /** 9576 * igb_io_slot_reset - called after the pci bus has been reset. 9577 * @pdev: Pointer to PCI device 9578 * 9579 * Restart the card from scratch, as if from a cold-boot. Implementation 9580 * resembles the first-half of the __igb_resume routine. 9581 **/ 9582 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9583 { 9584 struct net_device *netdev = pci_get_drvdata(pdev); 9585 struct igb_adapter *adapter = netdev_priv(netdev); 9586 struct e1000_hw *hw = &adapter->hw; 9587 pci_ers_result_t result; 9588 9589 if (pci_enable_device_mem(pdev)) { 9590 dev_err(&pdev->dev, 9591 "Cannot re-enable PCI device after reset.\n"); 9592 result = PCI_ERS_RESULT_DISCONNECT; 9593 } else { 9594 pci_set_master(pdev); 9595 pci_restore_state(pdev); 9596 pci_save_state(pdev); 9597 9598 pci_enable_wake(pdev, PCI_D3hot, 0); 9599 pci_enable_wake(pdev, PCI_D3cold, 0); 9600 9601 /* In case of PCI error, adapter lose its HW address 9602 * so we should re-assign it here. 9603 */ 9604 hw->hw_addr = adapter->io_addr; 9605 9606 igb_reset(adapter); 9607 wr32(E1000_WUS, ~0); 9608 result = PCI_ERS_RESULT_RECOVERED; 9609 } 9610 9611 return result; 9612 } 9613 9614 /** 9615 * igb_io_resume - called when traffic can start flowing again. 9616 * @pdev: Pointer to PCI device 9617 * 9618 * This callback is called when the error recovery driver tells us that 9619 * its OK to resume normal operation. Implementation resembles the 9620 * second-half of the __igb_resume routine. 9621 */ 9622 static void igb_io_resume(struct pci_dev *pdev) 9623 { 9624 struct net_device *netdev = pci_get_drvdata(pdev); 9625 struct igb_adapter *adapter = netdev_priv(netdev); 9626 9627 if (netif_running(netdev)) { 9628 if (igb_up(adapter)) { 9629 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9630 return; 9631 } 9632 } 9633 9634 netif_device_attach(netdev); 9635 9636 /* let the f/w know that the h/w is now under the control of the 9637 * driver. 9638 */ 9639 igb_get_hw_control(adapter); 9640 } 9641 9642 /** 9643 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9644 * @adapter: Pointer to adapter structure 9645 * @index: Index of the RAR entry which need to be synced with MAC table 9646 **/ 9647 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9648 { 9649 struct e1000_hw *hw = &adapter->hw; 9650 u32 rar_low, rar_high; 9651 u8 *addr = adapter->mac_table[index].addr; 9652 9653 /* HW expects these to be in network order when they are plugged 9654 * into the registers which are little endian. In order to guarantee 9655 * that ordering we need to do an leXX_to_cpup here in order to be 9656 * ready for the byteswap that occurs with writel 9657 */ 9658 rar_low = le32_to_cpup((__le32 *)(addr)); 9659 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9660 9661 /* Indicate to hardware the Address is Valid. */ 9662 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9663 if (is_valid_ether_addr(addr)) 9664 rar_high |= E1000_RAH_AV; 9665 9666 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9667 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9668 9669 switch (hw->mac.type) { 9670 case e1000_82575: 9671 case e1000_i210: 9672 if (adapter->mac_table[index].state & 9673 IGB_MAC_STATE_QUEUE_STEERING) 9674 rar_high |= E1000_RAH_QSEL_ENABLE; 9675 9676 rar_high |= E1000_RAH_POOL_1 * 9677 adapter->mac_table[index].queue; 9678 break; 9679 default: 9680 rar_high |= E1000_RAH_POOL_1 << 9681 adapter->mac_table[index].queue; 9682 break; 9683 } 9684 } 9685 9686 wr32(E1000_RAL(index), rar_low); 9687 wrfl(); 9688 wr32(E1000_RAH(index), rar_high); 9689 wrfl(); 9690 } 9691 9692 static int igb_set_vf_mac(struct igb_adapter *adapter, 9693 int vf, unsigned char *mac_addr) 9694 { 9695 struct e1000_hw *hw = &adapter->hw; 9696 /* VF MAC addresses start at end of receive addresses and moves 9697 * towards the first, as a result a collision should not be possible 9698 */ 9699 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9700 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9701 9702 ether_addr_copy(vf_mac_addr, mac_addr); 9703 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9704 adapter->mac_table[rar_entry].queue = vf; 9705 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9706 igb_rar_set_index(adapter, rar_entry); 9707 9708 return 0; 9709 } 9710 9711 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9712 { 9713 struct igb_adapter *adapter = netdev_priv(netdev); 9714 9715 if (vf >= adapter->vfs_allocated_count) 9716 return -EINVAL; 9717 9718 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9719 * flag and allows to overwrite the MAC via VF netdev. This 9720 * is necessary to allow libvirt a way to restore the original 9721 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9722 * down a VM. 9723 */ 9724 if (is_zero_ether_addr(mac)) { 9725 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9726 dev_info(&adapter->pdev->dev, 9727 "remove administratively set MAC on VF %d\n", 9728 vf); 9729 } else if (is_valid_ether_addr(mac)) { 9730 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9731 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9732 mac, vf); 9733 dev_info(&adapter->pdev->dev, 9734 "Reload the VF driver to make this change effective."); 9735 /* Generate additional warning if PF is down */ 9736 if (test_bit(__IGB_DOWN, &adapter->state)) { 9737 dev_warn(&adapter->pdev->dev, 9738 "The VF MAC address has been set, but the PF device is not up.\n"); 9739 dev_warn(&adapter->pdev->dev, 9740 "Bring the PF device up before attempting to use the VF device.\n"); 9741 } 9742 } else { 9743 return -EINVAL; 9744 } 9745 return igb_set_vf_mac(adapter, vf, mac); 9746 } 9747 9748 static int igb_link_mbps(int internal_link_speed) 9749 { 9750 switch (internal_link_speed) { 9751 case SPEED_100: 9752 return 100; 9753 case SPEED_1000: 9754 return 1000; 9755 default: 9756 return 0; 9757 } 9758 } 9759 9760 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9761 int link_speed) 9762 { 9763 int rf_dec, rf_int; 9764 u32 bcnrc_val; 9765 9766 if (tx_rate != 0) { 9767 /* Calculate the rate factor values to set */ 9768 rf_int = link_speed / tx_rate; 9769 rf_dec = (link_speed - (rf_int * tx_rate)); 9770 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9771 tx_rate; 9772 9773 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9774 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9775 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9776 } else { 9777 bcnrc_val = 0; 9778 } 9779 9780 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9781 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9782 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9783 */ 9784 wr32(E1000_RTTBCNRM, 0x14); 9785 wr32(E1000_RTTBCNRC, bcnrc_val); 9786 } 9787 9788 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9789 { 9790 int actual_link_speed, i; 9791 bool reset_rate = false; 9792 9793 /* VF TX rate limit was not set or not supported */ 9794 if ((adapter->vf_rate_link_speed == 0) || 9795 (adapter->hw.mac.type != e1000_82576)) 9796 return; 9797 9798 actual_link_speed = igb_link_mbps(adapter->link_speed); 9799 if (actual_link_speed != adapter->vf_rate_link_speed) { 9800 reset_rate = true; 9801 adapter->vf_rate_link_speed = 0; 9802 dev_info(&adapter->pdev->dev, 9803 "Link speed has been changed. VF Transmit rate is disabled\n"); 9804 } 9805 9806 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9807 if (reset_rate) 9808 adapter->vf_data[i].tx_rate = 0; 9809 9810 igb_set_vf_rate_limit(&adapter->hw, i, 9811 adapter->vf_data[i].tx_rate, 9812 actual_link_speed); 9813 } 9814 } 9815 9816 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9817 int min_tx_rate, int max_tx_rate) 9818 { 9819 struct igb_adapter *adapter = netdev_priv(netdev); 9820 struct e1000_hw *hw = &adapter->hw; 9821 int actual_link_speed; 9822 9823 if (hw->mac.type != e1000_82576) 9824 return -EOPNOTSUPP; 9825 9826 if (min_tx_rate) 9827 return -EINVAL; 9828 9829 actual_link_speed = igb_link_mbps(adapter->link_speed); 9830 if ((vf >= adapter->vfs_allocated_count) || 9831 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9832 (max_tx_rate < 0) || 9833 (max_tx_rate > actual_link_speed)) 9834 return -EINVAL; 9835 9836 adapter->vf_rate_link_speed = actual_link_speed; 9837 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9838 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9839 9840 return 0; 9841 } 9842 9843 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9844 bool setting) 9845 { 9846 struct igb_adapter *adapter = netdev_priv(netdev); 9847 struct e1000_hw *hw = &adapter->hw; 9848 u32 reg_val, reg_offset; 9849 9850 if (!adapter->vfs_allocated_count) 9851 return -EOPNOTSUPP; 9852 9853 if (vf >= adapter->vfs_allocated_count) 9854 return -EINVAL; 9855 9856 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9857 reg_val = rd32(reg_offset); 9858 if (setting) 9859 reg_val |= (BIT(vf) | 9860 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9861 else 9862 reg_val &= ~(BIT(vf) | 9863 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9864 wr32(reg_offset, reg_val); 9865 9866 adapter->vf_data[vf].spoofchk_enabled = setting; 9867 return 0; 9868 } 9869 9870 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9871 { 9872 struct igb_adapter *adapter = netdev_priv(netdev); 9873 9874 if (vf >= adapter->vfs_allocated_count) 9875 return -EINVAL; 9876 if (adapter->vf_data[vf].trusted == setting) 9877 return 0; 9878 9879 adapter->vf_data[vf].trusted = setting; 9880 9881 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9882 vf, setting ? "" : "not "); 9883 return 0; 9884 } 9885 9886 static int igb_ndo_get_vf_config(struct net_device *netdev, 9887 int vf, struct ifla_vf_info *ivi) 9888 { 9889 struct igb_adapter *adapter = netdev_priv(netdev); 9890 if (vf >= adapter->vfs_allocated_count) 9891 return -EINVAL; 9892 ivi->vf = vf; 9893 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9894 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9895 ivi->min_tx_rate = 0; 9896 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9897 ivi->qos = adapter->vf_data[vf].pf_qos; 9898 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9899 ivi->trusted = adapter->vf_data[vf].trusted; 9900 return 0; 9901 } 9902 9903 static void igb_vmm_control(struct igb_adapter *adapter) 9904 { 9905 struct e1000_hw *hw = &adapter->hw; 9906 u32 reg; 9907 9908 switch (hw->mac.type) { 9909 case e1000_82575: 9910 case e1000_i210: 9911 case e1000_i211: 9912 case e1000_i354: 9913 default: 9914 /* replication is not supported for 82575 */ 9915 return; 9916 case e1000_82576: 9917 /* notify HW that the MAC is adding vlan tags */ 9918 reg = rd32(E1000_DTXCTL); 9919 reg |= E1000_DTXCTL_VLAN_ADDED; 9920 wr32(E1000_DTXCTL, reg); 9921 fallthrough; 9922 case e1000_82580: 9923 /* enable replication vlan tag stripping */ 9924 reg = rd32(E1000_RPLOLR); 9925 reg |= E1000_RPLOLR_STRVLAN; 9926 wr32(E1000_RPLOLR, reg); 9927 fallthrough; 9928 case e1000_i350: 9929 /* none of the above registers are supported by i350 */ 9930 break; 9931 } 9932 9933 if (adapter->vfs_allocated_count) { 9934 igb_vmdq_set_loopback_pf(hw, true); 9935 igb_vmdq_set_replication_pf(hw, true); 9936 igb_vmdq_set_anti_spoofing_pf(hw, true, 9937 adapter->vfs_allocated_count); 9938 } else { 9939 igb_vmdq_set_loopback_pf(hw, false); 9940 igb_vmdq_set_replication_pf(hw, false); 9941 } 9942 } 9943 9944 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9945 { 9946 struct e1000_hw *hw = &adapter->hw; 9947 u32 dmac_thr; 9948 u16 hwm; 9949 u32 reg; 9950 9951 if (hw->mac.type > e1000_82580) { 9952 if (adapter->flags & IGB_FLAG_DMAC) { 9953 /* force threshold to 0. */ 9954 wr32(E1000_DMCTXTH, 0); 9955 9956 /* DMA Coalescing high water mark needs to be greater 9957 * than the Rx threshold. Set hwm to PBA - max frame 9958 * size in 16B units, capping it at PBA - 6KB. 9959 */ 9960 hwm = 64 * (pba - 6); 9961 reg = rd32(E1000_FCRTC); 9962 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9963 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 9964 wr32(E1000_FCRTC, reg); 9965 9966 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9967 * frame size, capping it at PBA - 10KB. 9968 */ 9969 dmac_thr = pba - 10; 9970 reg = rd32(E1000_DMACR); 9971 reg &= ~E1000_DMACR_DMACTHR_MASK; 9972 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 9973 9974 /* transition to L0x or L1 if available..*/ 9975 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9976 9977 /* watchdog timer= +-1000 usec in 32usec intervals */ 9978 reg |= (1000 >> 5); 9979 9980 /* Disable BMC-to-OS Watchdog Enable */ 9981 if (hw->mac.type != e1000_i354) 9982 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9983 wr32(E1000_DMACR, reg); 9984 9985 /* no lower threshold to disable 9986 * coalescing(smart fifb)-UTRESH=0 9987 */ 9988 wr32(E1000_DMCRTRH, 0); 9989 9990 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9991 9992 wr32(E1000_DMCTLX, reg); 9993 9994 /* free space in tx packet buffer to wake from 9995 * DMA coal 9996 */ 9997 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9998 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9999 } 10000 10001 if (hw->mac.type >= e1000_i210 || 10002 (adapter->flags & IGB_FLAG_DMAC)) { 10003 reg = rd32(E1000_PCIEMISC); 10004 reg |= E1000_PCIEMISC_LX_DECISION; 10005 wr32(E1000_PCIEMISC, reg); 10006 } /* endif adapter->dmac is not disabled */ 10007 } else if (hw->mac.type == e1000_82580) { 10008 u32 reg = rd32(E1000_PCIEMISC); 10009 10010 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10011 wr32(E1000_DMACR, 0); 10012 } 10013 } 10014 10015 /** 10016 * igb_read_i2c_byte - Reads 8 bit word over I2C 10017 * @hw: pointer to hardware structure 10018 * @byte_offset: byte offset to read 10019 * @dev_addr: device address 10020 * @data: value read 10021 * 10022 * Performs byte read operation over I2C interface at 10023 * a specified device address. 10024 **/ 10025 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10026 u8 dev_addr, u8 *data) 10027 { 10028 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10029 struct i2c_client *this_client = adapter->i2c_client; 10030 s32 status; 10031 u16 swfw_mask = 0; 10032 10033 if (!this_client) 10034 return E1000_ERR_I2C; 10035 10036 swfw_mask = E1000_SWFW_PHY0_SM; 10037 10038 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10039 return E1000_ERR_SWFW_SYNC; 10040 10041 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10042 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10043 10044 if (status < 0) 10045 return E1000_ERR_I2C; 10046 else { 10047 *data = status; 10048 return 0; 10049 } 10050 } 10051 10052 /** 10053 * igb_write_i2c_byte - Writes 8 bit word over I2C 10054 * @hw: pointer to hardware structure 10055 * @byte_offset: byte offset to write 10056 * @dev_addr: device address 10057 * @data: value to write 10058 * 10059 * Performs byte write operation over I2C interface at 10060 * a specified device address. 10061 **/ 10062 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10063 u8 dev_addr, u8 data) 10064 { 10065 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10066 struct i2c_client *this_client = adapter->i2c_client; 10067 s32 status; 10068 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10069 10070 if (!this_client) 10071 return E1000_ERR_I2C; 10072 10073 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10074 return E1000_ERR_SWFW_SYNC; 10075 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10076 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10077 10078 if (status) 10079 return E1000_ERR_I2C; 10080 else 10081 return 0; 10082 10083 } 10084 10085 int igb_reinit_queues(struct igb_adapter *adapter) 10086 { 10087 struct net_device *netdev = adapter->netdev; 10088 struct pci_dev *pdev = adapter->pdev; 10089 int err = 0; 10090 10091 if (netif_running(netdev)) 10092 igb_close(netdev); 10093 10094 igb_reset_interrupt_capability(adapter); 10095 10096 if (igb_init_interrupt_scheme(adapter, true)) { 10097 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10098 return -ENOMEM; 10099 } 10100 10101 if (netif_running(netdev)) 10102 err = igb_open(netdev); 10103 10104 return err; 10105 } 10106 10107 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10108 { 10109 struct igb_nfc_filter *rule; 10110 10111 spin_lock(&adapter->nfc_lock); 10112 10113 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10114 igb_erase_filter(adapter, rule); 10115 10116 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10117 igb_erase_filter(adapter, rule); 10118 10119 spin_unlock(&adapter->nfc_lock); 10120 } 10121 10122 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10123 { 10124 struct igb_nfc_filter *rule; 10125 10126 spin_lock(&adapter->nfc_lock); 10127 10128 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10129 igb_add_filter(adapter, rule); 10130 10131 spin_unlock(&adapter->nfc_lock); 10132 } 10133 10134 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10135 igb_runtime_suspend, igb_runtime_resume, 10136 igb_runtime_idle); 10137 10138 static struct pci_driver igb_driver = { 10139 .name = igb_driver_name, 10140 .id_table = igb_pci_tbl, 10141 .probe = igb_probe, 10142 .remove = igb_remove, 10143 .driver.pm = pm_ptr(&igb_pm_ops), 10144 .shutdown = igb_shutdown, 10145 .sriov_configure = igb_pci_sriov_configure, 10146 .err_handler = &igb_err_handler 10147 }; 10148 10149 /* igb_main.c */ 10150