1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 4 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 170 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 171 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 172 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 173 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 174 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 180 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 181 182 #ifdef CONFIG_PCI_IOV 183 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185 static int igb_disable_sriov(struct pci_dev *dev); 186 static int igb_pci_disable_sriov(struct pci_dev *dev); 187 #endif 188 189 #ifdef CONFIG_PM 190 #ifdef CONFIG_PM_SLEEP 191 static int igb_suspend(struct device *); 192 #endif 193 static int igb_resume(struct device *); 194 static int igb_runtime_suspend(struct device *dev); 195 static int igb_runtime_resume(struct device *dev); 196 static int igb_runtime_idle(struct device *dev); 197 static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201 }; 202 #endif 203 static void igb_shutdown(struct pci_dev *); 204 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205 #ifdef CONFIG_IGB_DCA 206 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207 static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211 }; 212 #endif 213 #ifdef CONFIG_NET_POLL_CONTROLLER 214 /* for netdump / net console */ 215 static void igb_netpoll(struct net_device *); 216 #endif 217 #ifdef CONFIG_PCI_IOV 218 static unsigned int max_vfs; 219 module_param(max_vfs, uint, 0); 220 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 221 #endif /* CONFIG_PCI_IOV */ 222 223 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 224 pci_channel_state_t); 225 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 226 static void igb_io_resume(struct pci_dev *); 227 228 static const struct pci_error_handlers igb_err_handler = { 229 .error_detected = igb_io_error_detected, 230 .slot_reset = igb_io_slot_reset, 231 .resume = igb_io_resume, 232 }; 233 234 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 235 236 static struct pci_driver igb_driver = { 237 .name = igb_driver_name, 238 .id_table = igb_pci_tbl, 239 .probe = igb_probe, 240 .remove = igb_remove, 241 #ifdef CONFIG_PM 242 .driver.pm = &igb_pm_ops, 243 #endif 244 .shutdown = igb_shutdown, 245 .sriov_configure = igb_pci_sriov_configure, 246 .err_handler = &igb_err_handler 247 }; 248 249 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 250 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 251 MODULE_LICENSE("GPL"); 252 MODULE_VERSION(DRV_VERSION); 253 254 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 255 static int debug = -1; 256 module_param(debug, int, 0); 257 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 258 259 struct igb_reg_info { 260 u32 ofs; 261 char *name; 262 }; 263 264 static const struct igb_reg_info igb_reg_info_tbl[] = { 265 266 /* General Registers */ 267 {E1000_CTRL, "CTRL"}, 268 {E1000_STATUS, "STATUS"}, 269 {E1000_CTRL_EXT, "CTRL_EXT"}, 270 271 /* Interrupt Registers */ 272 {E1000_ICR, "ICR"}, 273 274 /* RX Registers */ 275 {E1000_RCTL, "RCTL"}, 276 {E1000_RDLEN(0), "RDLEN"}, 277 {E1000_RDH(0), "RDH"}, 278 {E1000_RDT(0), "RDT"}, 279 {E1000_RXDCTL(0), "RXDCTL"}, 280 {E1000_RDBAL(0), "RDBAL"}, 281 {E1000_RDBAH(0), "RDBAH"}, 282 283 /* TX Registers */ 284 {E1000_TCTL, "TCTL"}, 285 {E1000_TDBAL(0), "TDBAL"}, 286 {E1000_TDBAH(0), "TDBAH"}, 287 {E1000_TDLEN(0), "TDLEN"}, 288 {E1000_TDH(0), "TDH"}, 289 {E1000_TDT(0), "TDT"}, 290 {E1000_TXDCTL(0), "TXDCTL"}, 291 {E1000_TDFH, "TDFH"}, 292 {E1000_TDFT, "TDFT"}, 293 {E1000_TDFHS, "TDFHS"}, 294 {E1000_TDFPC, "TDFPC"}, 295 296 /* List Terminator */ 297 {} 298 }; 299 300 /* igb_regdump - register printout routine */ 301 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 302 { 303 int n = 0; 304 char rname[16]; 305 u32 regs[8]; 306 307 switch (reginfo->ofs) { 308 case E1000_RDLEN(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDLEN(n)); 311 break; 312 case E1000_RDH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDH(n)); 315 break; 316 case E1000_RDT(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDT(n)); 319 break; 320 case E1000_RXDCTL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RXDCTL(n)); 323 break; 324 case E1000_RDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_RDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAH(n)); 331 break; 332 case E1000_TDBAL(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_RDBAL(n)); 335 break; 336 case E1000_TDBAH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDBAH(n)); 339 break; 340 case E1000_TDLEN(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDLEN(n)); 343 break; 344 case E1000_TDH(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDH(n)); 347 break; 348 case E1000_TDT(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TDT(n)); 351 break; 352 case E1000_TXDCTL(0): 353 for (n = 0; n < 4; n++) 354 regs[n] = rd32(E1000_TXDCTL(n)); 355 break; 356 default: 357 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 358 return; 359 } 360 361 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 362 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 363 regs[2], regs[3]); 364 } 365 366 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 367 static void igb_dump(struct igb_adapter *adapter) 368 { 369 struct net_device *netdev = adapter->netdev; 370 struct e1000_hw *hw = &adapter->hw; 371 struct igb_reg_info *reginfo; 372 struct igb_ring *tx_ring; 373 union e1000_adv_tx_desc *tx_desc; 374 struct my_u0 { u64 a; u64 b; } *u0; 375 struct igb_ring *rx_ring; 376 union e1000_adv_rx_desc *rx_desc; 377 u32 staterr; 378 u16 i, n; 379 380 if (!netif_msg_hw(adapter)) 381 return; 382 383 /* Print netdevice Info */ 384 if (netdev) { 385 dev_info(&adapter->pdev->dev, "Net device Info\n"); 386 pr_info("Device Name state trans_start last_rx\n"); 387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 388 netdev->state, dev_trans_start(netdev), netdev->last_rx); 389 } 390 391 /* Print Registers */ 392 dev_info(&adapter->pdev->dev, "Register Dump\n"); 393 pr_info(" Register Name Value\n"); 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 395 reginfo->name; reginfo++) { 396 igb_regdump(hw, reginfo); 397 } 398 399 /* Print TX Ring Summary */ 400 if (!netdev || !netif_running(netdev)) 401 goto exit; 402 403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 405 for (n = 0; n < adapter->num_tx_queues; n++) { 406 struct igb_tx_buffer *buffer_info; 407 tx_ring = adapter->tx_ring[n]; 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 410 n, tx_ring->next_to_use, tx_ring->next_to_clean, 411 (u64)dma_unmap_addr(buffer_info, dma), 412 dma_unmap_len(buffer_info, len), 413 buffer_info->next_to_watch, 414 (u64)buffer_info->time_stamp); 415 } 416 417 /* Print TX Rings */ 418 if (!netif_msg_tx_done(adapter)) 419 goto rx_ring_summary; 420 421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 422 423 /* Transmit Descriptor Formats 424 * 425 * Advanced Transmit Descriptor 426 * +--------------------------------------------------------------+ 427 * 0 | Buffer Address [63:0] | 428 * +--------------------------------------------------------------+ 429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 430 * +--------------------------------------------------------------+ 431 * 63 46 45 40 39 38 36 35 32 31 24 15 0 432 */ 433 434 for (n = 0; n < adapter->num_tx_queues; n++) { 435 tx_ring = adapter->tx_ring[n]; 436 pr_info("------------------------------------\n"); 437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 438 pr_info("------------------------------------\n"); 439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 440 441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 442 const char *next_desc; 443 struct igb_tx_buffer *buffer_info; 444 tx_desc = IGB_TX_DESC(tx_ring, i); 445 buffer_info = &tx_ring->tx_buffer_info[i]; 446 u0 = (struct my_u0 *)tx_desc; 447 if (i == tx_ring->next_to_use && 448 i == tx_ring->next_to_clean) 449 next_desc = " NTC/U"; 450 else if (i == tx_ring->next_to_use) 451 next_desc = " NTU"; 452 else if (i == tx_ring->next_to_clean) 453 next_desc = " NTC"; 454 else 455 next_desc = ""; 456 457 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 458 i, le64_to_cpu(u0->a), 459 le64_to_cpu(u0->b), 460 (u64)dma_unmap_addr(buffer_info, dma), 461 dma_unmap_len(buffer_info, len), 462 buffer_info->next_to_watch, 463 (u64)buffer_info->time_stamp, 464 buffer_info->skb, next_desc); 465 466 if (netif_msg_pktdata(adapter) && buffer_info->skb) 467 print_hex_dump(KERN_INFO, "", 468 DUMP_PREFIX_ADDRESS, 469 16, 1, buffer_info->skb->data, 470 dma_unmap_len(buffer_info, len), 471 true); 472 } 473 } 474 475 /* Print RX Rings Summary */ 476 rx_ring_summary: 477 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 478 pr_info("Queue [NTU] [NTC]\n"); 479 for (n = 0; n < adapter->num_rx_queues; n++) { 480 rx_ring = adapter->rx_ring[n]; 481 pr_info(" %5d %5X %5X\n", 482 n, rx_ring->next_to_use, rx_ring->next_to_clean); 483 } 484 485 /* Print RX Rings */ 486 if (!netif_msg_rx_status(adapter)) 487 goto exit; 488 489 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 490 491 /* Advanced Receive Descriptor (Read) Format 492 * 63 1 0 493 * +-----------------------------------------------------+ 494 * 0 | Packet Buffer Address [63:1] |A0/NSE| 495 * +----------------------------------------------+------+ 496 * 8 | Header Buffer Address [63:1] | DD | 497 * +-----------------------------------------------------+ 498 * 499 * 500 * Advanced Receive Descriptor (Write-Back) Format 501 * 502 * 63 48 47 32 31 30 21 20 17 16 4 3 0 503 * +------------------------------------------------------+ 504 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 505 * | Checksum Ident | | | | Type | Type | 506 * +------------------------------------------------------+ 507 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 508 * +------------------------------------------------------+ 509 * 63 48 47 32 31 20 19 0 510 */ 511 512 for (n = 0; n < adapter->num_rx_queues; n++) { 513 rx_ring = adapter->rx_ring[n]; 514 pr_info("------------------------------------\n"); 515 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 516 pr_info("------------------------------------\n"); 517 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 IGB_RX_BUFSZ, true); 558 } 559 } 560 } 561 } 562 563 exit: 564 return; 565 } 566 567 /** 568 * igb_get_i2c_data - Reads the I2C SDA data bit 569 * @hw: pointer to hardware structure 570 * @i2cctl: Current value of I2CCTL register 571 * 572 * Returns the I2C data bit value 573 **/ 574 static int igb_get_i2c_data(void *data) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 return !!(i2cctl & E1000_I2C_DATA_IN); 581 } 582 583 /** 584 * igb_set_i2c_data - Sets the I2C data bit 585 * @data: pointer to hardware structure 586 * @state: I2C data value (0 or 1) to set 587 * 588 * Sets the I2C data bit 589 **/ 590 static void igb_set_i2c_data(void *data, int state) 591 { 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 if (state) 597 i2cctl |= E1000_I2C_DATA_OUT; 598 else 599 i2cctl &= ~E1000_I2C_DATA_OUT; 600 601 i2cctl &= ~E1000_I2C_DATA_OE_N; 602 i2cctl |= E1000_I2C_CLK_OE_N; 603 wr32(E1000_I2CPARAMS, i2cctl); 604 wrfl(); 605 606 } 607 608 /** 609 * igb_set_i2c_clk - Sets the I2C SCL clock 610 * @data: pointer to hardware structure 611 * @state: state to set clock 612 * 613 * Sets the I2C clock line to state 614 **/ 615 static void igb_set_i2c_clk(void *data, int state) 616 { 617 struct igb_adapter *adapter = (struct igb_adapter *)data; 618 struct e1000_hw *hw = &adapter->hw; 619 s32 i2cctl = rd32(E1000_I2CPARAMS); 620 621 if (state) { 622 i2cctl |= E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } else { 625 i2cctl &= ~E1000_I2C_CLK_OUT; 626 i2cctl &= ~E1000_I2C_CLK_OE_N; 627 } 628 wr32(E1000_I2CPARAMS, i2cctl); 629 wrfl(); 630 } 631 632 /** 633 * igb_get_i2c_clk - Gets the I2C SCL clock state 634 * @data: pointer to hardware structure 635 * 636 * Gets the I2C clock state 637 **/ 638 static int igb_get_i2c_clk(void *data) 639 { 640 struct igb_adapter *adapter = (struct igb_adapter *)data; 641 struct e1000_hw *hw = &adapter->hw; 642 s32 i2cctl = rd32(E1000_I2CPARAMS); 643 644 return !!(i2cctl & E1000_I2C_CLK_IN); 645 } 646 647 static const struct i2c_algo_bit_data igb_i2c_algo = { 648 .setsda = igb_set_i2c_data, 649 .setscl = igb_set_i2c_clk, 650 .getsda = igb_get_i2c_data, 651 .getscl = igb_get_i2c_clk, 652 .udelay = 5, 653 .timeout = 20, 654 }; 655 656 /** 657 * igb_get_hw_dev - return device 658 * @hw: pointer to hardware structure 659 * 660 * used by hardware layer to print debugging information 661 **/ 662 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 663 { 664 struct igb_adapter *adapter = hw->back; 665 return adapter->netdev; 666 } 667 668 /** 669 * igb_init_module - Driver Registration Routine 670 * 671 * igb_init_module is the first routine called when the driver is 672 * loaded. All it does is register with the PCI subsystem. 673 **/ 674 static int __init igb_init_module(void) 675 { 676 int ret; 677 678 pr_info("%s - version %s\n", 679 igb_driver_string, igb_driver_version); 680 pr_info("%s\n", igb_copyright); 681 682 #ifdef CONFIG_IGB_DCA 683 dca_register_notify(&dca_notifier); 684 #endif 685 ret = pci_register_driver(&igb_driver); 686 return ret; 687 } 688 689 module_init(igb_init_module); 690 691 /** 692 * igb_exit_module - Driver Exit Cleanup Routine 693 * 694 * igb_exit_module is called just before the driver is removed 695 * from memory. 696 **/ 697 static void __exit igb_exit_module(void) 698 { 699 #ifdef CONFIG_IGB_DCA 700 dca_unregister_notify(&dca_notifier); 701 #endif 702 pci_unregister_driver(&igb_driver); 703 } 704 705 module_exit(igb_exit_module); 706 707 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 708 /** 709 * igb_cache_ring_register - Descriptor ring to register mapping 710 * @adapter: board private structure to initialize 711 * 712 * Once we know the feature-set enabled for the device, we'll cache 713 * the register offset the descriptor ring is assigned to. 714 **/ 715 static void igb_cache_ring_register(struct igb_adapter *adapter) 716 { 717 int i = 0, j = 0; 718 u32 rbase_offset = adapter->vfs_allocated_count; 719 720 switch (adapter->hw.mac.type) { 721 case e1000_82576: 722 /* The queues are allocated for virtualization such that VF 0 723 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 724 * In order to avoid collision we start at the first free queue 725 * and continue consuming queues in the same sequence 726 */ 727 if (adapter->vfs_allocated_count) { 728 for (; i < adapter->rss_queues; i++) 729 adapter->rx_ring[i]->reg_idx = rbase_offset + 730 Q_IDX_82576(i); 731 } 732 /* Fall through */ 733 case e1000_82575: 734 case e1000_82580: 735 case e1000_i350: 736 case e1000_i354: 737 case e1000_i210: 738 case e1000_i211: 739 /* Fall through */ 740 default: 741 for (; i < adapter->num_rx_queues; i++) 742 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 743 for (; j < adapter->num_tx_queues; j++) 744 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 745 break; 746 } 747 } 748 749 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 750 { 751 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 752 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 753 u32 value = 0; 754 755 if (E1000_REMOVED(hw_addr)) 756 return ~value; 757 758 value = readl(&hw_addr[reg]); 759 760 /* reads should not return all F's */ 761 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 762 struct net_device *netdev = igb->netdev; 763 hw->hw_addr = NULL; 764 netif_device_detach(netdev); 765 netdev_err(netdev, "PCIe link lost, device now detached\n"); 766 } 767 768 return value; 769 } 770 771 /** 772 * igb_write_ivar - configure ivar for given MSI-X vector 773 * @hw: pointer to the HW structure 774 * @msix_vector: vector number we are allocating to a given ring 775 * @index: row index of IVAR register to write within IVAR table 776 * @offset: column offset of in IVAR, should be multiple of 8 777 * 778 * This function is intended to handle the writing of the IVAR register 779 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 780 * each containing an cause allocation for an Rx and Tx ring, and a 781 * variable number of rows depending on the number of queues supported. 782 **/ 783 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 784 int index, int offset) 785 { 786 u32 ivar = array_rd32(E1000_IVAR0, index); 787 788 /* clear any bits that are currently set */ 789 ivar &= ~((u32)0xFF << offset); 790 791 /* write vector and valid bit */ 792 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 793 794 array_wr32(E1000_IVAR0, index, ivar); 795 } 796 797 #define IGB_N0_QUEUE -1 798 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 799 { 800 struct igb_adapter *adapter = q_vector->adapter; 801 struct e1000_hw *hw = &adapter->hw; 802 int rx_queue = IGB_N0_QUEUE; 803 int tx_queue = IGB_N0_QUEUE; 804 u32 msixbm = 0; 805 806 if (q_vector->rx.ring) 807 rx_queue = q_vector->rx.ring->reg_idx; 808 if (q_vector->tx.ring) 809 tx_queue = q_vector->tx.ring->reg_idx; 810 811 switch (hw->mac.type) { 812 case e1000_82575: 813 /* The 82575 assigns vectors using a bitmask, which matches the 814 * bitmask for the EICR/EIMS/EIMC registers. To assign one 815 * or more queues to a vector, we write the appropriate bits 816 * into the MSIXBM register for that vector. 817 */ 818 if (rx_queue > IGB_N0_QUEUE) 819 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 820 if (tx_queue > IGB_N0_QUEUE) 821 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 822 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 823 msixbm |= E1000_EIMS_OTHER; 824 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 825 q_vector->eims_value = msixbm; 826 break; 827 case e1000_82576: 828 /* 82576 uses a table that essentially consists of 2 columns 829 * with 8 rows. The ordering is column-major so we use the 830 * lower 3 bits as the row index, and the 4th bit as the 831 * column offset. 832 */ 833 if (rx_queue > IGB_N0_QUEUE) 834 igb_write_ivar(hw, msix_vector, 835 rx_queue & 0x7, 836 (rx_queue & 0x8) << 1); 837 if (tx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 tx_queue & 0x7, 840 ((tx_queue & 0x8) << 1) + 8); 841 q_vector->eims_value = BIT(msix_vector); 842 break; 843 case e1000_82580: 844 case e1000_i350: 845 case e1000_i354: 846 case e1000_i210: 847 case e1000_i211: 848 /* On 82580 and newer adapters the scheme is similar to 82576 849 * however instead of ordering column-major we have things 850 * ordered row-major. So we traverse the table by using 851 * bit 0 as the column offset, and the remaining bits as the 852 * row index. 853 */ 854 if (rx_queue > IGB_N0_QUEUE) 855 igb_write_ivar(hw, msix_vector, 856 rx_queue >> 1, 857 (rx_queue & 0x1) << 4); 858 if (tx_queue > IGB_N0_QUEUE) 859 igb_write_ivar(hw, msix_vector, 860 tx_queue >> 1, 861 ((tx_queue & 0x1) << 4) + 8); 862 q_vector->eims_value = BIT(msix_vector); 863 break; 864 default: 865 BUG(); 866 break; 867 } 868 869 /* add q_vector eims value to global eims_enable_mask */ 870 adapter->eims_enable_mask |= q_vector->eims_value; 871 872 /* configure q_vector to set itr on first interrupt */ 873 q_vector->set_itr = 1; 874 } 875 876 /** 877 * igb_configure_msix - Configure MSI-X hardware 878 * @adapter: board private structure to initialize 879 * 880 * igb_configure_msix sets up the hardware to properly 881 * generate MSI-X interrupts. 882 **/ 883 static void igb_configure_msix(struct igb_adapter *adapter) 884 { 885 u32 tmp; 886 int i, vector = 0; 887 struct e1000_hw *hw = &adapter->hw; 888 889 adapter->eims_enable_mask = 0; 890 891 /* set vector for other causes, i.e. link changes */ 892 switch (hw->mac.type) { 893 case e1000_82575: 894 tmp = rd32(E1000_CTRL_EXT); 895 /* enable MSI-X PBA support*/ 896 tmp |= E1000_CTRL_EXT_PBA_CLR; 897 898 /* Auto-Mask interrupts upon ICR read. */ 899 tmp |= E1000_CTRL_EXT_EIAME; 900 tmp |= E1000_CTRL_EXT_IRCA; 901 902 wr32(E1000_CTRL_EXT, tmp); 903 904 /* enable msix_other interrupt */ 905 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 906 adapter->eims_other = E1000_EIMS_OTHER; 907 908 break; 909 910 case e1000_82576: 911 case e1000_82580: 912 case e1000_i350: 913 case e1000_i354: 914 case e1000_i210: 915 case e1000_i211: 916 /* Turn on MSI-X capability first, or our settings 917 * won't stick. And it will take days to debug. 918 */ 919 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 920 E1000_GPIE_PBA | E1000_GPIE_EIAME | 921 E1000_GPIE_NSICR); 922 923 /* enable msix_other interrupt */ 924 adapter->eims_other = BIT(vector); 925 tmp = (vector++ | E1000_IVAR_VALID) << 8; 926 927 wr32(E1000_IVAR_MISC, tmp); 928 break; 929 default: 930 /* do nothing, since nothing else supports MSI-X */ 931 break; 932 } /* switch (hw->mac.type) */ 933 934 adapter->eims_enable_mask |= adapter->eims_other; 935 936 for (i = 0; i < adapter->num_q_vectors; i++) 937 igb_assign_vector(adapter->q_vector[i], vector++); 938 939 wrfl(); 940 } 941 942 /** 943 * igb_request_msix - Initialize MSI-X interrupts 944 * @adapter: board private structure to initialize 945 * 946 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 947 * kernel. 948 **/ 949 static int igb_request_msix(struct igb_adapter *adapter) 950 { 951 struct net_device *netdev = adapter->netdev; 952 int i, err = 0, vector = 0, free_vector = 0; 953 954 err = request_irq(adapter->msix_entries[vector].vector, 955 igb_msix_other, 0, netdev->name, adapter); 956 if (err) 957 goto err_out; 958 959 for (i = 0; i < adapter->num_q_vectors; i++) { 960 struct igb_q_vector *q_vector = adapter->q_vector[i]; 961 962 vector++; 963 964 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 965 966 if (q_vector->rx.ring && q_vector->tx.ring) 967 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 968 q_vector->rx.ring->queue_index); 969 else if (q_vector->tx.ring) 970 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 971 q_vector->tx.ring->queue_index); 972 else if (q_vector->rx.ring) 973 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 974 q_vector->rx.ring->queue_index); 975 else 976 sprintf(q_vector->name, "%s-unused", netdev->name); 977 978 err = request_irq(adapter->msix_entries[vector].vector, 979 igb_msix_ring, 0, q_vector->name, 980 q_vector); 981 if (err) 982 goto err_free; 983 } 984 985 igb_configure_msix(adapter); 986 return 0; 987 988 err_free: 989 /* free already assigned IRQs */ 990 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 991 992 vector--; 993 for (i = 0; i < vector; i++) { 994 free_irq(adapter->msix_entries[free_vector++].vector, 995 adapter->q_vector[i]); 996 } 997 err_out: 998 return err; 999 } 1000 1001 /** 1002 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1003 * @adapter: board private structure to initialize 1004 * @v_idx: Index of vector to be freed 1005 * 1006 * This function frees the memory allocated to the q_vector. 1007 **/ 1008 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1009 { 1010 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1011 1012 adapter->q_vector[v_idx] = NULL; 1013 1014 /* igb_get_stats64() might access the rings on this vector, 1015 * we must wait a grace period before freeing it. 1016 */ 1017 if (q_vector) 1018 kfree_rcu(q_vector, rcu); 1019 } 1020 1021 /** 1022 * igb_reset_q_vector - Reset config for interrupt vector 1023 * @adapter: board private structure to initialize 1024 * @v_idx: Index of vector to be reset 1025 * 1026 * If NAPI is enabled it will delete any references to the 1027 * NAPI struct. This is preparation for igb_free_q_vector. 1028 **/ 1029 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1030 { 1031 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1032 1033 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1034 * allocated. So, q_vector is NULL so we should stop here. 1035 */ 1036 if (!q_vector) 1037 return; 1038 1039 if (q_vector->tx.ring) 1040 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1041 1042 if (q_vector->rx.ring) 1043 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1044 1045 netif_napi_del(&q_vector->napi); 1046 1047 } 1048 1049 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1050 { 1051 int v_idx = adapter->num_q_vectors; 1052 1053 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1054 pci_disable_msix(adapter->pdev); 1055 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1056 pci_disable_msi(adapter->pdev); 1057 1058 while (v_idx--) 1059 igb_reset_q_vector(adapter, v_idx); 1060 } 1061 1062 /** 1063 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1064 * @adapter: board private structure to initialize 1065 * 1066 * This function frees the memory allocated to the q_vectors. In addition if 1067 * NAPI is enabled it will delete any references to the NAPI struct prior 1068 * to freeing the q_vector. 1069 **/ 1070 static void igb_free_q_vectors(struct igb_adapter *adapter) 1071 { 1072 int v_idx = adapter->num_q_vectors; 1073 1074 adapter->num_tx_queues = 0; 1075 adapter->num_rx_queues = 0; 1076 adapter->num_q_vectors = 0; 1077 1078 while (v_idx--) { 1079 igb_reset_q_vector(adapter, v_idx); 1080 igb_free_q_vector(adapter, v_idx); 1081 } 1082 } 1083 1084 /** 1085 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1086 * @adapter: board private structure to initialize 1087 * 1088 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1089 * MSI-X interrupts allocated. 1090 */ 1091 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1092 { 1093 igb_free_q_vectors(adapter); 1094 igb_reset_interrupt_capability(adapter); 1095 } 1096 1097 /** 1098 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1099 * @adapter: board private structure to initialize 1100 * @msix: boolean value of MSIX capability 1101 * 1102 * Attempt to configure interrupts using the best available 1103 * capabilities of the hardware and kernel. 1104 **/ 1105 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1106 { 1107 int err; 1108 int numvecs, i; 1109 1110 if (!msix) 1111 goto msi_only; 1112 adapter->flags |= IGB_FLAG_HAS_MSIX; 1113 1114 /* Number of supported queues. */ 1115 adapter->num_rx_queues = adapter->rss_queues; 1116 if (adapter->vfs_allocated_count) 1117 adapter->num_tx_queues = 1; 1118 else 1119 adapter->num_tx_queues = adapter->rss_queues; 1120 1121 /* start with one vector for every Rx queue */ 1122 numvecs = adapter->num_rx_queues; 1123 1124 /* if Tx handler is separate add 1 for every Tx queue */ 1125 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1126 numvecs += adapter->num_tx_queues; 1127 1128 /* store the number of vectors reserved for queues */ 1129 adapter->num_q_vectors = numvecs; 1130 1131 /* add 1 vector for link status interrupts */ 1132 numvecs++; 1133 for (i = 0; i < numvecs; i++) 1134 adapter->msix_entries[i].entry = i; 1135 1136 err = pci_enable_msix_range(adapter->pdev, 1137 adapter->msix_entries, 1138 numvecs, 1139 numvecs); 1140 if (err > 0) 1141 return; 1142 1143 igb_reset_interrupt_capability(adapter); 1144 1145 /* If we can't do MSI-X, try MSI */ 1146 msi_only: 1147 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1148 #ifdef CONFIG_PCI_IOV 1149 /* disable SR-IOV for non MSI-X configurations */ 1150 if (adapter->vf_data) { 1151 struct e1000_hw *hw = &adapter->hw; 1152 /* disable iov and allow time for transactions to clear */ 1153 pci_disable_sriov(adapter->pdev); 1154 msleep(500); 1155 1156 kfree(adapter->vf_data); 1157 adapter->vf_data = NULL; 1158 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1159 wrfl(); 1160 msleep(100); 1161 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1162 } 1163 #endif 1164 adapter->vfs_allocated_count = 0; 1165 adapter->rss_queues = 1; 1166 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1167 adapter->num_rx_queues = 1; 1168 adapter->num_tx_queues = 1; 1169 adapter->num_q_vectors = 1; 1170 if (!pci_enable_msi(adapter->pdev)) 1171 adapter->flags |= IGB_FLAG_HAS_MSI; 1172 } 1173 1174 static void igb_add_ring(struct igb_ring *ring, 1175 struct igb_ring_container *head) 1176 { 1177 head->ring = ring; 1178 head->count++; 1179 } 1180 1181 /** 1182 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1183 * @adapter: board private structure to initialize 1184 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1185 * @v_idx: index of vector in adapter struct 1186 * @txr_count: total number of Tx rings to allocate 1187 * @txr_idx: index of first Tx ring to allocate 1188 * @rxr_count: total number of Rx rings to allocate 1189 * @rxr_idx: index of first Rx ring to allocate 1190 * 1191 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1192 **/ 1193 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1194 int v_count, int v_idx, 1195 int txr_count, int txr_idx, 1196 int rxr_count, int rxr_idx) 1197 { 1198 struct igb_q_vector *q_vector; 1199 struct igb_ring *ring; 1200 int ring_count, size; 1201 1202 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1203 if (txr_count > 1 || rxr_count > 1) 1204 return -ENOMEM; 1205 1206 ring_count = txr_count + rxr_count; 1207 size = sizeof(struct igb_q_vector) + 1208 (sizeof(struct igb_ring) * ring_count); 1209 1210 /* allocate q_vector and rings */ 1211 q_vector = adapter->q_vector[v_idx]; 1212 if (!q_vector) { 1213 q_vector = kzalloc(size, GFP_KERNEL); 1214 } else if (size > ksize(q_vector)) { 1215 kfree_rcu(q_vector, rcu); 1216 q_vector = kzalloc(size, GFP_KERNEL); 1217 } else { 1218 memset(q_vector, 0, size); 1219 } 1220 if (!q_vector) 1221 return -ENOMEM; 1222 1223 /* initialize NAPI */ 1224 netif_napi_add(adapter->netdev, &q_vector->napi, 1225 igb_poll, 64); 1226 1227 /* tie q_vector and adapter together */ 1228 adapter->q_vector[v_idx] = q_vector; 1229 q_vector->adapter = adapter; 1230 1231 /* initialize work limits */ 1232 q_vector->tx.work_limit = adapter->tx_work_limit; 1233 1234 /* initialize ITR configuration */ 1235 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1236 q_vector->itr_val = IGB_START_ITR; 1237 1238 /* initialize pointer to rings */ 1239 ring = q_vector->ring; 1240 1241 /* intialize ITR */ 1242 if (rxr_count) { 1243 /* rx or rx/tx vector */ 1244 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1245 q_vector->itr_val = adapter->rx_itr_setting; 1246 } else { 1247 /* tx only vector */ 1248 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1249 q_vector->itr_val = adapter->tx_itr_setting; 1250 } 1251 1252 if (txr_count) { 1253 /* assign generic ring traits */ 1254 ring->dev = &adapter->pdev->dev; 1255 ring->netdev = adapter->netdev; 1256 1257 /* configure backlink on ring */ 1258 ring->q_vector = q_vector; 1259 1260 /* update q_vector Tx values */ 1261 igb_add_ring(ring, &q_vector->tx); 1262 1263 /* For 82575, context index must be unique per ring. */ 1264 if (adapter->hw.mac.type == e1000_82575) 1265 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1266 1267 /* apply Tx specific ring traits */ 1268 ring->count = adapter->tx_ring_count; 1269 ring->queue_index = txr_idx; 1270 1271 u64_stats_init(&ring->tx_syncp); 1272 u64_stats_init(&ring->tx_syncp2); 1273 1274 /* assign ring to adapter */ 1275 adapter->tx_ring[txr_idx] = ring; 1276 1277 /* push pointer to next ring */ 1278 ring++; 1279 } 1280 1281 if (rxr_count) { 1282 /* assign generic ring traits */ 1283 ring->dev = &adapter->pdev->dev; 1284 ring->netdev = adapter->netdev; 1285 1286 /* configure backlink on ring */ 1287 ring->q_vector = q_vector; 1288 1289 /* update q_vector Rx values */ 1290 igb_add_ring(ring, &q_vector->rx); 1291 1292 /* set flag indicating ring supports SCTP checksum offload */ 1293 if (adapter->hw.mac.type >= e1000_82576) 1294 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1295 1296 /* On i350, i354, i210, and i211, loopback VLAN packets 1297 * have the tag byte-swapped. 1298 */ 1299 if (adapter->hw.mac.type >= e1000_i350) 1300 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1301 1302 /* apply Rx specific ring traits */ 1303 ring->count = adapter->rx_ring_count; 1304 ring->queue_index = rxr_idx; 1305 1306 u64_stats_init(&ring->rx_syncp); 1307 1308 /* assign ring to adapter */ 1309 adapter->rx_ring[rxr_idx] = ring; 1310 } 1311 1312 return 0; 1313 } 1314 1315 1316 /** 1317 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1318 * @adapter: board private structure to initialize 1319 * 1320 * We allocate one q_vector per queue interrupt. If allocation fails we 1321 * return -ENOMEM. 1322 **/ 1323 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1324 { 1325 int q_vectors = adapter->num_q_vectors; 1326 int rxr_remaining = adapter->num_rx_queues; 1327 int txr_remaining = adapter->num_tx_queues; 1328 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1329 int err; 1330 1331 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1332 for (; rxr_remaining; v_idx++) { 1333 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1334 0, 0, 1, rxr_idx); 1335 1336 if (err) 1337 goto err_out; 1338 1339 /* update counts and index */ 1340 rxr_remaining--; 1341 rxr_idx++; 1342 } 1343 } 1344 1345 for (; v_idx < q_vectors; v_idx++) { 1346 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1347 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1348 1349 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1350 tqpv, txr_idx, rqpv, rxr_idx); 1351 1352 if (err) 1353 goto err_out; 1354 1355 /* update counts and index */ 1356 rxr_remaining -= rqpv; 1357 txr_remaining -= tqpv; 1358 rxr_idx++; 1359 txr_idx++; 1360 } 1361 1362 return 0; 1363 1364 err_out: 1365 adapter->num_tx_queues = 0; 1366 adapter->num_rx_queues = 0; 1367 adapter->num_q_vectors = 0; 1368 1369 while (v_idx--) 1370 igb_free_q_vector(adapter, v_idx); 1371 1372 return -ENOMEM; 1373 } 1374 1375 /** 1376 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1377 * @adapter: board private structure to initialize 1378 * @msix: boolean value of MSIX capability 1379 * 1380 * This function initializes the interrupts and allocates all of the queues. 1381 **/ 1382 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1383 { 1384 struct pci_dev *pdev = adapter->pdev; 1385 int err; 1386 1387 igb_set_interrupt_capability(adapter, msix); 1388 1389 err = igb_alloc_q_vectors(adapter); 1390 if (err) { 1391 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1392 goto err_alloc_q_vectors; 1393 } 1394 1395 igb_cache_ring_register(adapter); 1396 1397 return 0; 1398 1399 err_alloc_q_vectors: 1400 igb_reset_interrupt_capability(adapter); 1401 return err; 1402 } 1403 1404 /** 1405 * igb_request_irq - initialize interrupts 1406 * @adapter: board private structure to initialize 1407 * 1408 * Attempts to configure interrupts using the best available 1409 * capabilities of the hardware and kernel. 1410 **/ 1411 static int igb_request_irq(struct igb_adapter *adapter) 1412 { 1413 struct net_device *netdev = adapter->netdev; 1414 struct pci_dev *pdev = adapter->pdev; 1415 int err = 0; 1416 1417 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1418 err = igb_request_msix(adapter); 1419 if (!err) 1420 goto request_done; 1421 /* fall back to MSI */ 1422 igb_free_all_tx_resources(adapter); 1423 igb_free_all_rx_resources(adapter); 1424 1425 igb_clear_interrupt_scheme(adapter); 1426 err = igb_init_interrupt_scheme(adapter, false); 1427 if (err) 1428 goto request_done; 1429 1430 igb_setup_all_tx_resources(adapter); 1431 igb_setup_all_rx_resources(adapter); 1432 igb_configure(adapter); 1433 } 1434 1435 igb_assign_vector(adapter->q_vector[0], 0); 1436 1437 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1438 err = request_irq(pdev->irq, igb_intr_msi, 0, 1439 netdev->name, adapter); 1440 if (!err) 1441 goto request_done; 1442 1443 /* fall back to legacy interrupts */ 1444 igb_reset_interrupt_capability(adapter); 1445 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1446 } 1447 1448 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1449 netdev->name, adapter); 1450 1451 if (err) 1452 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1453 err); 1454 1455 request_done: 1456 return err; 1457 } 1458 1459 static void igb_free_irq(struct igb_adapter *adapter) 1460 { 1461 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1462 int vector = 0, i; 1463 1464 free_irq(adapter->msix_entries[vector++].vector, adapter); 1465 1466 for (i = 0; i < adapter->num_q_vectors; i++) 1467 free_irq(adapter->msix_entries[vector++].vector, 1468 adapter->q_vector[i]); 1469 } else { 1470 free_irq(adapter->pdev->irq, adapter); 1471 } 1472 } 1473 1474 /** 1475 * igb_irq_disable - Mask off interrupt generation on the NIC 1476 * @adapter: board private structure 1477 **/ 1478 static void igb_irq_disable(struct igb_adapter *adapter) 1479 { 1480 struct e1000_hw *hw = &adapter->hw; 1481 1482 /* we need to be careful when disabling interrupts. The VFs are also 1483 * mapped into these registers and so clearing the bits can cause 1484 * issues on the VF drivers so we only need to clear what we set 1485 */ 1486 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1487 u32 regval = rd32(E1000_EIAM); 1488 1489 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1490 wr32(E1000_EIMC, adapter->eims_enable_mask); 1491 regval = rd32(E1000_EIAC); 1492 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1493 } 1494 1495 wr32(E1000_IAM, 0); 1496 wr32(E1000_IMC, ~0); 1497 wrfl(); 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 int i; 1500 1501 for (i = 0; i < adapter->num_q_vectors; i++) 1502 synchronize_irq(adapter->msix_entries[i].vector); 1503 } else { 1504 synchronize_irq(adapter->pdev->irq); 1505 } 1506 } 1507 1508 /** 1509 * igb_irq_enable - Enable default interrupt generation settings 1510 * @adapter: board private structure 1511 **/ 1512 static void igb_irq_enable(struct igb_adapter *adapter) 1513 { 1514 struct e1000_hw *hw = &adapter->hw; 1515 1516 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1517 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1518 u32 regval = rd32(E1000_EIAC); 1519 1520 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1521 regval = rd32(E1000_EIAM); 1522 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1523 wr32(E1000_EIMS, adapter->eims_enable_mask); 1524 if (adapter->vfs_allocated_count) { 1525 wr32(E1000_MBVFIMR, 0xFF); 1526 ims |= E1000_IMS_VMMB; 1527 } 1528 wr32(E1000_IMS, ims); 1529 } else { 1530 wr32(E1000_IMS, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 wr32(E1000_IAM, IMS_ENABLE_MASK | 1533 E1000_IMS_DRSTA); 1534 } 1535 } 1536 1537 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1538 { 1539 struct e1000_hw *hw = &adapter->hw; 1540 u16 pf_id = adapter->vfs_allocated_count; 1541 u16 vid = adapter->hw.mng_cookie.vlan_id; 1542 u16 old_vid = adapter->mng_vlan_id; 1543 1544 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1545 /* add VID to filter table */ 1546 igb_vfta_set(hw, vid, pf_id, true, true); 1547 adapter->mng_vlan_id = vid; 1548 } else { 1549 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1550 } 1551 1552 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1553 (vid != old_vid) && 1554 !test_bit(old_vid, adapter->active_vlans)) { 1555 /* remove VID from filter table */ 1556 igb_vfta_set(hw, vid, pf_id, false, true); 1557 } 1558 } 1559 1560 /** 1561 * igb_release_hw_control - release control of the h/w to f/w 1562 * @adapter: address of board private structure 1563 * 1564 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1565 * For ASF and Pass Through versions of f/w this means that the 1566 * driver is no longer loaded. 1567 **/ 1568 static void igb_release_hw_control(struct igb_adapter *adapter) 1569 { 1570 struct e1000_hw *hw = &adapter->hw; 1571 u32 ctrl_ext; 1572 1573 /* Let firmware take over control of h/w */ 1574 ctrl_ext = rd32(E1000_CTRL_EXT); 1575 wr32(E1000_CTRL_EXT, 1576 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1577 } 1578 1579 /** 1580 * igb_get_hw_control - get control of the h/w from f/w 1581 * @adapter: address of board private structure 1582 * 1583 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1584 * For ASF and Pass Through versions of f/w this means that 1585 * the driver is loaded. 1586 **/ 1587 static void igb_get_hw_control(struct igb_adapter *adapter) 1588 { 1589 struct e1000_hw *hw = &adapter->hw; 1590 u32 ctrl_ext; 1591 1592 /* Let firmware know the driver has taken over */ 1593 ctrl_ext = rd32(E1000_CTRL_EXT); 1594 wr32(E1000_CTRL_EXT, 1595 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1596 } 1597 1598 /** 1599 * igb_configure - configure the hardware for RX and TX 1600 * @adapter: private board structure 1601 **/ 1602 static void igb_configure(struct igb_adapter *adapter) 1603 { 1604 struct net_device *netdev = adapter->netdev; 1605 int i; 1606 1607 igb_get_hw_control(adapter); 1608 igb_set_rx_mode(netdev); 1609 1610 igb_restore_vlan(adapter); 1611 1612 igb_setup_tctl(adapter); 1613 igb_setup_mrqc(adapter); 1614 igb_setup_rctl(adapter); 1615 1616 igb_nfc_filter_restore(adapter); 1617 igb_configure_tx(adapter); 1618 igb_configure_rx(adapter); 1619 1620 igb_rx_fifo_flush_82575(&adapter->hw); 1621 1622 /* call igb_desc_unused which always leaves 1623 * at least 1 descriptor unused to make sure 1624 * next_to_use != next_to_clean 1625 */ 1626 for (i = 0; i < adapter->num_rx_queues; i++) { 1627 struct igb_ring *ring = adapter->rx_ring[i]; 1628 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1629 } 1630 } 1631 1632 /** 1633 * igb_power_up_link - Power up the phy/serdes link 1634 * @adapter: address of board private structure 1635 **/ 1636 void igb_power_up_link(struct igb_adapter *adapter) 1637 { 1638 igb_reset_phy(&adapter->hw); 1639 1640 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1641 igb_power_up_phy_copper(&adapter->hw); 1642 else 1643 igb_power_up_serdes_link_82575(&adapter->hw); 1644 1645 igb_setup_link(&adapter->hw); 1646 } 1647 1648 /** 1649 * igb_power_down_link - Power down the phy/serdes link 1650 * @adapter: address of board private structure 1651 */ 1652 static void igb_power_down_link(struct igb_adapter *adapter) 1653 { 1654 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1655 igb_power_down_phy_copper_82575(&adapter->hw); 1656 else 1657 igb_shutdown_serdes_link_82575(&adapter->hw); 1658 } 1659 1660 /** 1661 * Detect and switch function for Media Auto Sense 1662 * @adapter: address of the board private structure 1663 **/ 1664 static void igb_check_swap_media(struct igb_adapter *adapter) 1665 { 1666 struct e1000_hw *hw = &adapter->hw; 1667 u32 ctrl_ext, connsw; 1668 bool swap_now = false; 1669 1670 ctrl_ext = rd32(E1000_CTRL_EXT); 1671 connsw = rd32(E1000_CONNSW); 1672 1673 /* need to live swap if current media is copper and we have fiber/serdes 1674 * to go to. 1675 */ 1676 1677 if ((hw->phy.media_type == e1000_media_type_copper) && 1678 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1679 swap_now = true; 1680 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1681 /* copper signal takes time to appear */ 1682 if (adapter->copper_tries < 4) { 1683 adapter->copper_tries++; 1684 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1685 wr32(E1000_CONNSW, connsw); 1686 return; 1687 } else { 1688 adapter->copper_tries = 0; 1689 if ((connsw & E1000_CONNSW_PHYSD) && 1690 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1691 swap_now = true; 1692 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1693 wr32(E1000_CONNSW, connsw); 1694 } 1695 } 1696 } 1697 1698 if (!swap_now) 1699 return; 1700 1701 switch (hw->phy.media_type) { 1702 case e1000_media_type_copper: 1703 netdev_info(adapter->netdev, 1704 "MAS: changing media to fiber/serdes\n"); 1705 ctrl_ext |= 1706 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1707 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1708 adapter->copper_tries = 0; 1709 break; 1710 case e1000_media_type_internal_serdes: 1711 case e1000_media_type_fiber: 1712 netdev_info(adapter->netdev, 1713 "MAS: changing media to copper\n"); 1714 ctrl_ext &= 1715 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1716 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1717 break; 1718 default: 1719 /* shouldn't get here during regular operation */ 1720 netdev_err(adapter->netdev, 1721 "AMS: Invalid media type found, returning\n"); 1722 break; 1723 } 1724 wr32(E1000_CTRL_EXT, ctrl_ext); 1725 } 1726 1727 /** 1728 * igb_up - Open the interface and prepare it to handle traffic 1729 * @adapter: board private structure 1730 **/ 1731 int igb_up(struct igb_adapter *adapter) 1732 { 1733 struct e1000_hw *hw = &adapter->hw; 1734 int i; 1735 1736 /* hardware has been reset, we need to reload some things */ 1737 igb_configure(adapter); 1738 1739 clear_bit(__IGB_DOWN, &adapter->state); 1740 1741 for (i = 0; i < adapter->num_q_vectors; i++) 1742 napi_enable(&(adapter->q_vector[i]->napi)); 1743 1744 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1745 igb_configure_msix(adapter); 1746 else 1747 igb_assign_vector(adapter->q_vector[0], 0); 1748 1749 /* Clear any pending interrupts. */ 1750 rd32(E1000_ICR); 1751 igb_irq_enable(adapter); 1752 1753 /* notify VFs that reset has been completed */ 1754 if (adapter->vfs_allocated_count) { 1755 u32 reg_data = rd32(E1000_CTRL_EXT); 1756 1757 reg_data |= E1000_CTRL_EXT_PFRSTD; 1758 wr32(E1000_CTRL_EXT, reg_data); 1759 } 1760 1761 netif_tx_start_all_queues(adapter->netdev); 1762 1763 /* start the watchdog. */ 1764 hw->mac.get_link_status = 1; 1765 schedule_work(&adapter->watchdog_task); 1766 1767 if ((adapter->flags & IGB_FLAG_EEE) && 1768 (!hw->dev_spec._82575.eee_disable)) 1769 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1770 1771 return 0; 1772 } 1773 1774 void igb_down(struct igb_adapter *adapter) 1775 { 1776 struct net_device *netdev = adapter->netdev; 1777 struct e1000_hw *hw = &adapter->hw; 1778 u32 tctl, rctl; 1779 int i; 1780 1781 /* signal that we're down so the interrupt handler does not 1782 * reschedule our watchdog timer 1783 */ 1784 set_bit(__IGB_DOWN, &adapter->state); 1785 1786 /* disable receives in the hardware */ 1787 rctl = rd32(E1000_RCTL); 1788 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1789 /* flush and sleep below */ 1790 1791 netif_carrier_off(netdev); 1792 netif_tx_stop_all_queues(netdev); 1793 1794 /* disable transmits in the hardware */ 1795 tctl = rd32(E1000_TCTL); 1796 tctl &= ~E1000_TCTL_EN; 1797 wr32(E1000_TCTL, tctl); 1798 /* flush both disables and wait for them to finish */ 1799 wrfl(); 1800 usleep_range(10000, 11000); 1801 1802 igb_irq_disable(adapter); 1803 1804 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1805 1806 for (i = 0; i < adapter->num_q_vectors; i++) { 1807 if (adapter->q_vector[i]) { 1808 napi_synchronize(&adapter->q_vector[i]->napi); 1809 napi_disable(&adapter->q_vector[i]->napi); 1810 } 1811 } 1812 1813 del_timer_sync(&adapter->watchdog_timer); 1814 del_timer_sync(&adapter->phy_info_timer); 1815 1816 /* record the stats before reset*/ 1817 spin_lock(&adapter->stats64_lock); 1818 igb_update_stats(adapter, &adapter->stats64); 1819 spin_unlock(&adapter->stats64_lock); 1820 1821 adapter->link_speed = 0; 1822 adapter->link_duplex = 0; 1823 1824 if (!pci_channel_offline(adapter->pdev)) 1825 igb_reset(adapter); 1826 1827 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1828 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1829 1830 igb_clean_all_tx_rings(adapter); 1831 igb_clean_all_rx_rings(adapter); 1832 #ifdef CONFIG_IGB_DCA 1833 1834 /* since we reset the hardware DCA settings were cleared */ 1835 igb_setup_dca(adapter); 1836 #endif 1837 } 1838 1839 void igb_reinit_locked(struct igb_adapter *adapter) 1840 { 1841 WARN_ON(in_interrupt()); 1842 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1843 usleep_range(1000, 2000); 1844 igb_down(adapter); 1845 igb_up(adapter); 1846 clear_bit(__IGB_RESETTING, &adapter->state); 1847 } 1848 1849 /** igb_enable_mas - Media Autosense re-enable after swap 1850 * 1851 * @adapter: adapter struct 1852 **/ 1853 static void igb_enable_mas(struct igb_adapter *adapter) 1854 { 1855 struct e1000_hw *hw = &adapter->hw; 1856 u32 connsw = rd32(E1000_CONNSW); 1857 1858 /* configure for SerDes media detect */ 1859 if ((hw->phy.media_type == e1000_media_type_copper) && 1860 (!(connsw & E1000_CONNSW_SERDESD))) { 1861 connsw |= E1000_CONNSW_ENRGSRC; 1862 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1863 wr32(E1000_CONNSW, connsw); 1864 wrfl(); 1865 } 1866 } 1867 1868 void igb_reset(struct igb_adapter *adapter) 1869 { 1870 struct pci_dev *pdev = adapter->pdev; 1871 struct e1000_hw *hw = &adapter->hw; 1872 struct e1000_mac_info *mac = &hw->mac; 1873 struct e1000_fc_info *fc = &hw->fc; 1874 u32 pba, hwm; 1875 1876 /* Repartition Pba for greater than 9k mtu 1877 * To take effect CTRL.RST is required. 1878 */ 1879 switch (mac->type) { 1880 case e1000_i350: 1881 case e1000_i354: 1882 case e1000_82580: 1883 pba = rd32(E1000_RXPBS); 1884 pba = igb_rxpbs_adjust_82580(pba); 1885 break; 1886 case e1000_82576: 1887 pba = rd32(E1000_RXPBS); 1888 pba &= E1000_RXPBS_SIZE_MASK_82576; 1889 break; 1890 case e1000_82575: 1891 case e1000_i210: 1892 case e1000_i211: 1893 default: 1894 pba = E1000_PBA_34K; 1895 break; 1896 } 1897 1898 if (mac->type == e1000_82575) { 1899 u32 min_rx_space, min_tx_space, needed_tx_space; 1900 1901 /* write Rx PBA so that hardware can report correct Tx PBA */ 1902 wr32(E1000_PBA, pba); 1903 1904 /* To maintain wire speed transmits, the Tx FIFO should be 1905 * large enough to accommodate two full transmit packets, 1906 * rounded up to the next 1KB and expressed in KB. Likewise, 1907 * the Rx FIFO should be large enough to accommodate at least 1908 * one full receive packet and is similarly rounded up and 1909 * expressed in KB. 1910 */ 1911 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1912 1913 /* The Tx FIFO also stores 16 bytes of information about the Tx 1914 * but don't include Ethernet FCS because hardware appends it. 1915 * We only need to round down to the nearest 512 byte block 1916 * count since the value we care about is 2 frames, not 1. 1917 */ 1918 min_tx_space = adapter->max_frame_size; 1919 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1920 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1921 1922 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1923 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1924 1925 /* If current Tx allocation is less than the min Tx FIFO size, 1926 * and the min Tx FIFO size is less than the current Rx FIFO 1927 * allocation, take space away from current Rx allocation. 1928 */ 1929 if (needed_tx_space < pba) { 1930 pba -= needed_tx_space; 1931 1932 /* if short on Rx space, Rx wins and must trump Tx 1933 * adjustment 1934 */ 1935 if (pba < min_rx_space) 1936 pba = min_rx_space; 1937 } 1938 1939 /* adjust PBA for jumbo frames */ 1940 wr32(E1000_PBA, pba); 1941 } 1942 1943 /* flow control settings 1944 * The high water mark must be low enough to fit one full frame 1945 * after transmitting the pause frame. As such we must have enough 1946 * space to allow for us to complete our current transmit and then 1947 * receive the frame that is in progress from the link partner. 1948 * Set it to: 1949 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1950 */ 1951 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1952 1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1954 fc->low_water = fc->high_water - 16; 1955 fc->pause_time = 0xFFFF; 1956 fc->send_xon = 1; 1957 fc->current_mode = fc->requested_mode; 1958 1959 /* disable receive for all VFs and wait one second */ 1960 if (adapter->vfs_allocated_count) { 1961 int i; 1962 1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1965 1966 /* ping all the active vfs to let them know we are going down */ 1967 igb_ping_all_vfs(adapter); 1968 1969 /* disable transmits and receives */ 1970 wr32(E1000_VFRE, 0); 1971 wr32(E1000_VFTE, 0); 1972 } 1973 1974 /* Allow time for pending master requests to run */ 1975 hw->mac.ops.reset_hw(hw); 1976 wr32(E1000_WUC, 0); 1977 1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1979 /* need to resetup here after media swap */ 1980 adapter->ei.get_invariants(hw); 1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1982 } 1983 if ((mac->type == e1000_82575) && 1984 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1985 igb_enable_mas(adapter); 1986 } 1987 if (hw->mac.ops.init_hw(hw)) 1988 dev_err(&pdev->dev, "Hardware Error\n"); 1989 1990 /* Flow control settings reset on hardware reset, so guarantee flow 1991 * control is off when forcing speed. 1992 */ 1993 if (!hw->mac.autoneg) 1994 igb_force_mac_fc(hw); 1995 1996 igb_init_dmac(adapter, pba); 1997 #ifdef CONFIG_IGB_HWMON 1998 /* Re-initialize the thermal sensor on i350 devices. */ 1999 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2000 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2001 /* If present, re-initialize the external thermal sensor 2002 * interface. 2003 */ 2004 if (adapter->ets) 2005 mac->ops.init_thermal_sensor_thresh(hw); 2006 } 2007 } 2008 #endif 2009 /* Re-establish EEE setting */ 2010 if (hw->phy.media_type == e1000_media_type_copper) { 2011 switch (mac->type) { 2012 case e1000_i350: 2013 case e1000_i210: 2014 case e1000_i211: 2015 igb_set_eee_i350(hw, true, true); 2016 break; 2017 case e1000_i354: 2018 igb_set_eee_i354(hw, true, true); 2019 break; 2020 default: 2021 break; 2022 } 2023 } 2024 if (!netif_running(adapter->netdev)) 2025 igb_power_down_link(adapter); 2026 2027 igb_update_mng_vlan(adapter); 2028 2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2031 2032 /* Re-enable PTP, where applicable. */ 2033 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2034 igb_ptp_reset(adapter); 2035 2036 igb_get_phy_info(hw); 2037 } 2038 2039 static netdev_features_t igb_fix_features(struct net_device *netdev, 2040 netdev_features_t features) 2041 { 2042 /* Since there is no support for separate Rx/Tx vlan accel 2043 * enable/disable make sure Tx flag is always in same state as Rx. 2044 */ 2045 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2046 features |= NETIF_F_HW_VLAN_CTAG_TX; 2047 else 2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2049 2050 return features; 2051 } 2052 2053 static int igb_set_features(struct net_device *netdev, 2054 netdev_features_t features) 2055 { 2056 netdev_features_t changed = netdev->features ^ features; 2057 struct igb_adapter *adapter = netdev_priv(netdev); 2058 2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2060 igb_vlan_mode(netdev, features); 2061 2062 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2063 return 0; 2064 2065 if (!(features & NETIF_F_NTUPLE)) { 2066 struct hlist_node *node2; 2067 struct igb_nfc_filter *rule; 2068 2069 spin_lock(&adapter->nfc_lock); 2070 hlist_for_each_entry_safe(rule, node2, 2071 &adapter->nfc_filter_list, nfc_node) { 2072 igb_erase_filter(adapter, rule); 2073 hlist_del(&rule->nfc_node); 2074 kfree(rule); 2075 } 2076 spin_unlock(&adapter->nfc_lock); 2077 adapter->nfc_filter_count = 0; 2078 } 2079 2080 netdev->features = features; 2081 2082 if (netif_running(netdev)) 2083 igb_reinit_locked(adapter); 2084 else 2085 igb_reset(adapter); 2086 2087 return 0; 2088 } 2089 2090 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2091 struct net_device *dev, 2092 const unsigned char *addr, u16 vid, 2093 u16 flags) 2094 { 2095 /* guarantee we can provide a unique filter for the unicast address */ 2096 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2097 struct igb_adapter *adapter = netdev_priv(dev); 2098 struct e1000_hw *hw = &adapter->hw; 2099 int vfn = adapter->vfs_allocated_count; 2100 int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 2101 2102 if (netdev_uc_count(dev) >= rar_entries) 2103 return -ENOMEM; 2104 } 2105 2106 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2107 } 2108 2109 #define IGB_MAX_MAC_HDR_LEN 127 2110 #define IGB_MAX_NETWORK_HDR_LEN 511 2111 2112 static netdev_features_t 2113 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2114 netdev_features_t features) 2115 { 2116 unsigned int network_hdr_len, mac_hdr_len; 2117 2118 /* Make certain the headers can be described by a context descriptor */ 2119 mac_hdr_len = skb_network_header(skb) - skb->data; 2120 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2121 return features & ~(NETIF_F_HW_CSUM | 2122 NETIF_F_SCTP_CRC | 2123 NETIF_F_HW_VLAN_CTAG_TX | 2124 NETIF_F_TSO | 2125 NETIF_F_TSO6); 2126 2127 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2128 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2129 return features & ~(NETIF_F_HW_CSUM | 2130 NETIF_F_SCTP_CRC | 2131 NETIF_F_TSO | 2132 NETIF_F_TSO6); 2133 2134 /* We can only support IPV4 TSO in tunnels if we can mangle the 2135 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2136 */ 2137 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2138 features &= ~NETIF_F_TSO; 2139 2140 return features; 2141 } 2142 2143 static const struct net_device_ops igb_netdev_ops = { 2144 .ndo_open = igb_open, 2145 .ndo_stop = igb_close, 2146 .ndo_start_xmit = igb_xmit_frame, 2147 .ndo_get_stats64 = igb_get_stats64, 2148 .ndo_set_rx_mode = igb_set_rx_mode, 2149 .ndo_set_mac_address = igb_set_mac, 2150 .ndo_change_mtu = igb_change_mtu, 2151 .ndo_do_ioctl = igb_ioctl, 2152 .ndo_tx_timeout = igb_tx_timeout, 2153 .ndo_validate_addr = eth_validate_addr, 2154 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2155 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2156 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2157 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2158 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2159 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2160 .ndo_get_vf_config = igb_ndo_get_vf_config, 2161 #ifdef CONFIG_NET_POLL_CONTROLLER 2162 .ndo_poll_controller = igb_netpoll, 2163 #endif 2164 .ndo_fix_features = igb_fix_features, 2165 .ndo_set_features = igb_set_features, 2166 .ndo_fdb_add = igb_ndo_fdb_add, 2167 .ndo_features_check = igb_features_check, 2168 }; 2169 2170 /** 2171 * igb_set_fw_version - Configure version string for ethtool 2172 * @adapter: adapter struct 2173 **/ 2174 void igb_set_fw_version(struct igb_adapter *adapter) 2175 { 2176 struct e1000_hw *hw = &adapter->hw; 2177 struct e1000_fw_version fw; 2178 2179 igb_get_fw_version(hw, &fw); 2180 2181 switch (hw->mac.type) { 2182 case e1000_i210: 2183 case e1000_i211: 2184 if (!(igb_get_flash_presence_i210(hw))) { 2185 snprintf(adapter->fw_version, 2186 sizeof(adapter->fw_version), 2187 "%2d.%2d-%d", 2188 fw.invm_major, fw.invm_minor, 2189 fw.invm_img_type); 2190 break; 2191 } 2192 /* fall through */ 2193 default: 2194 /* if option is rom valid, display its version too */ 2195 if (fw.or_valid) { 2196 snprintf(adapter->fw_version, 2197 sizeof(adapter->fw_version), 2198 "%d.%d, 0x%08x, %d.%d.%d", 2199 fw.eep_major, fw.eep_minor, fw.etrack_id, 2200 fw.or_major, fw.or_build, fw.or_patch); 2201 /* no option rom */ 2202 } else if (fw.etrack_id != 0X0000) { 2203 snprintf(adapter->fw_version, 2204 sizeof(adapter->fw_version), 2205 "%d.%d, 0x%08x", 2206 fw.eep_major, fw.eep_minor, fw.etrack_id); 2207 } else { 2208 snprintf(adapter->fw_version, 2209 sizeof(adapter->fw_version), 2210 "%d.%d.%d", 2211 fw.eep_major, fw.eep_minor, fw.eep_build); 2212 } 2213 break; 2214 } 2215 } 2216 2217 /** 2218 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2219 * 2220 * @adapter: adapter struct 2221 **/ 2222 static void igb_init_mas(struct igb_adapter *adapter) 2223 { 2224 struct e1000_hw *hw = &adapter->hw; 2225 u16 eeprom_data; 2226 2227 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2228 switch (hw->bus.func) { 2229 case E1000_FUNC_0: 2230 if (eeprom_data & IGB_MAS_ENABLE_0) { 2231 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2232 netdev_info(adapter->netdev, 2233 "MAS: Enabling Media Autosense for port %d\n", 2234 hw->bus.func); 2235 } 2236 break; 2237 case E1000_FUNC_1: 2238 if (eeprom_data & IGB_MAS_ENABLE_1) { 2239 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2240 netdev_info(adapter->netdev, 2241 "MAS: Enabling Media Autosense for port %d\n", 2242 hw->bus.func); 2243 } 2244 break; 2245 case E1000_FUNC_2: 2246 if (eeprom_data & IGB_MAS_ENABLE_2) { 2247 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2248 netdev_info(adapter->netdev, 2249 "MAS: Enabling Media Autosense for port %d\n", 2250 hw->bus.func); 2251 } 2252 break; 2253 case E1000_FUNC_3: 2254 if (eeprom_data & IGB_MAS_ENABLE_3) { 2255 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2256 netdev_info(adapter->netdev, 2257 "MAS: Enabling Media Autosense for port %d\n", 2258 hw->bus.func); 2259 } 2260 break; 2261 default: 2262 /* Shouldn't get here */ 2263 netdev_err(adapter->netdev, 2264 "MAS: Invalid port configuration, returning\n"); 2265 break; 2266 } 2267 } 2268 2269 /** 2270 * igb_init_i2c - Init I2C interface 2271 * @adapter: pointer to adapter structure 2272 **/ 2273 static s32 igb_init_i2c(struct igb_adapter *adapter) 2274 { 2275 s32 status = 0; 2276 2277 /* I2C interface supported on i350 devices */ 2278 if (adapter->hw.mac.type != e1000_i350) 2279 return 0; 2280 2281 /* Initialize the i2c bus which is controlled by the registers. 2282 * This bus will use the i2c_algo_bit structue that implements 2283 * the protocol through toggling of the 4 bits in the register. 2284 */ 2285 adapter->i2c_adap.owner = THIS_MODULE; 2286 adapter->i2c_algo = igb_i2c_algo; 2287 adapter->i2c_algo.data = adapter; 2288 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2289 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2290 strlcpy(adapter->i2c_adap.name, "igb BB", 2291 sizeof(adapter->i2c_adap.name)); 2292 status = i2c_bit_add_bus(&adapter->i2c_adap); 2293 return status; 2294 } 2295 2296 /** 2297 * igb_probe - Device Initialization Routine 2298 * @pdev: PCI device information struct 2299 * @ent: entry in igb_pci_tbl 2300 * 2301 * Returns 0 on success, negative on failure 2302 * 2303 * igb_probe initializes an adapter identified by a pci_dev structure. 2304 * The OS initialization, configuring of the adapter private structure, 2305 * and a hardware reset occur. 2306 **/ 2307 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2308 { 2309 struct net_device *netdev; 2310 struct igb_adapter *adapter; 2311 struct e1000_hw *hw; 2312 u16 eeprom_data = 0; 2313 s32 ret_val; 2314 static int global_quad_port_a; /* global quad port a indication */ 2315 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2316 int err, pci_using_dac; 2317 u8 part_str[E1000_PBANUM_LENGTH]; 2318 2319 /* Catch broken hardware that put the wrong VF device ID in 2320 * the PCIe SR-IOV capability. 2321 */ 2322 if (pdev->is_virtfn) { 2323 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2324 pci_name(pdev), pdev->vendor, pdev->device); 2325 return -EINVAL; 2326 } 2327 2328 err = pci_enable_device_mem(pdev); 2329 if (err) 2330 return err; 2331 2332 pci_using_dac = 0; 2333 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2334 if (!err) { 2335 pci_using_dac = 1; 2336 } else { 2337 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2338 if (err) { 2339 dev_err(&pdev->dev, 2340 "No usable DMA configuration, aborting\n"); 2341 goto err_dma; 2342 } 2343 } 2344 2345 err = pci_request_mem_regions(pdev, igb_driver_name); 2346 if (err) 2347 goto err_pci_reg; 2348 2349 pci_enable_pcie_error_reporting(pdev); 2350 2351 pci_set_master(pdev); 2352 pci_save_state(pdev); 2353 2354 err = -ENOMEM; 2355 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2356 IGB_MAX_TX_QUEUES); 2357 if (!netdev) 2358 goto err_alloc_etherdev; 2359 2360 SET_NETDEV_DEV(netdev, &pdev->dev); 2361 2362 pci_set_drvdata(pdev, netdev); 2363 adapter = netdev_priv(netdev); 2364 adapter->netdev = netdev; 2365 adapter->pdev = pdev; 2366 hw = &adapter->hw; 2367 hw->back = adapter; 2368 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2369 2370 err = -EIO; 2371 adapter->io_addr = pci_iomap(pdev, 0, 0); 2372 if (!adapter->io_addr) 2373 goto err_ioremap; 2374 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2375 hw->hw_addr = adapter->io_addr; 2376 2377 netdev->netdev_ops = &igb_netdev_ops; 2378 igb_set_ethtool_ops(netdev); 2379 netdev->watchdog_timeo = 5 * HZ; 2380 2381 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2382 2383 netdev->mem_start = pci_resource_start(pdev, 0); 2384 netdev->mem_end = pci_resource_end(pdev, 0); 2385 2386 /* PCI config space info */ 2387 hw->vendor_id = pdev->vendor; 2388 hw->device_id = pdev->device; 2389 hw->revision_id = pdev->revision; 2390 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2391 hw->subsystem_device_id = pdev->subsystem_device; 2392 2393 /* Copy the default MAC, PHY and NVM function pointers */ 2394 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2395 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2396 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2397 /* Initialize skew-specific constants */ 2398 err = ei->get_invariants(hw); 2399 if (err) 2400 goto err_sw_init; 2401 2402 /* setup the private structure */ 2403 err = igb_sw_init(adapter); 2404 if (err) 2405 goto err_sw_init; 2406 2407 igb_get_bus_info_pcie(hw); 2408 2409 hw->phy.autoneg_wait_to_complete = false; 2410 2411 /* Copper options */ 2412 if (hw->phy.media_type == e1000_media_type_copper) { 2413 hw->phy.mdix = AUTO_ALL_MODES; 2414 hw->phy.disable_polarity_correction = false; 2415 hw->phy.ms_type = e1000_ms_hw_default; 2416 } 2417 2418 if (igb_check_reset_block(hw)) 2419 dev_info(&pdev->dev, 2420 "PHY reset is blocked due to SOL/IDER session.\n"); 2421 2422 /* features is initialized to 0 in allocation, it might have bits 2423 * set by igb_sw_init so we should use an or instead of an 2424 * assignment. 2425 */ 2426 netdev->features |= NETIF_F_SG | 2427 NETIF_F_TSO | 2428 NETIF_F_TSO6 | 2429 NETIF_F_RXHASH | 2430 NETIF_F_RXCSUM | 2431 NETIF_F_HW_CSUM; 2432 2433 if (hw->mac.type >= e1000_82576) 2434 netdev->features |= NETIF_F_SCTP_CRC; 2435 2436 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2437 NETIF_F_GSO_GRE_CSUM | \ 2438 NETIF_F_GSO_IPXIP4 | \ 2439 NETIF_F_GSO_IPXIP6 | \ 2440 NETIF_F_GSO_UDP_TUNNEL | \ 2441 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2442 2443 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2444 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2445 2446 /* copy netdev features into list of user selectable features */ 2447 netdev->hw_features |= netdev->features | 2448 NETIF_F_HW_VLAN_CTAG_RX | 2449 NETIF_F_HW_VLAN_CTAG_TX | 2450 NETIF_F_RXALL; 2451 2452 if (hw->mac.type >= e1000_i350) 2453 netdev->hw_features |= NETIF_F_NTUPLE; 2454 2455 if (pci_using_dac) 2456 netdev->features |= NETIF_F_HIGHDMA; 2457 2458 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2459 netdev->mpls_features |= NETIF_F_HW_CSUM; 2460 netdev->hw_enc_features |= netdev->vlan_features; 2461 2462 /* set this bit last since it cannot be part of vlan_features */ 2463 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2464 NETIF_F_HW_VLAN_CTAG_RX | 2465 NETIF_F_HW_VLAN_CTAG_TX; 2466 2467 netdev->priv_flags |= IFF_SUPP_NOFCS; 2468 2469 netdev->priv_flags |= IFF_UNICAST_FLT; 2470 2471 /* MTU range: 68 - 9216 */ 2472 netdev->min_mtu = ETH_MIN_MTU; 2473 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2474 2475 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2476 2477 /* before reading the NVM, reset the controller to put the device in a 2478 * known good starting state 2479 */ 2480 hw->mac.ops.reset_hw(hw); 2481 2482 /* make sure the NVM is good , i211/i210 parts can have special NVM 2483 * that doesn't contain a checksum 2484 */ 2485 switch (hw->mac.type) { 2486 case e1000_i210: 2487 case e1000_i211: 2488 if (igb_get_flash_presence_i210(hw)) { 2489 if (hw->nvm.ops.validate(hw) < 0) { 2490 dev_err(&pdev->dev, 2491 "The NVM Checksum Is Not Valid\n"); 2492 err = -EIO; 2493 goto err_eeprom; 2494 } 2495 } 2496 break; 2497 default: 2498 if (hw->nvm.ops.validate(hw) < 0) { 2499 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2500 err = -EIO; 2501 goto err_eeprom; 2502 } 2503 break; 2504 } 2505 2506 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2507 /* copy the MAC address out of the NVM */ 2508 if (hw->mac.ops.read_mac_addr(hw)) 2509 dev_err(&pdev->dev, "NVM Read Error\n"); 2510 } 2511 2512 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2513 2514 if (!is_valid_ether_addr(netdev->dev_addr)) { 2515 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2516 err = -EIO; 2517 goto err_eeprom; 2518 } 2519 2520 /* get firmware version for ethtool -i */ 2521 igb_set_fw_version(adapter); 2522 2523 /* configure RXPBSIZE and TXPBSIZE */ 2524 if (hw->mac.type == e1000_i210) { 2525 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2526 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2527 } 2528 2529 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2530 (unsigned long) adapter); 2531 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2532 (unsigned long) adapter); 2533 2534 INIT_WORK(&adapter->reset_task, igb_reset_task); 2535 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2536 2537 /* Initialize link properties that are user-changeable */ 2538 adapter->fc_autoneg = true; 2539 hw->mac.autoneg = true; 2540 hw->phy.autoneg_advertised = 0x2f; 2541 2542 hw->fc.requested_mode = e1000_fc_default; 2543 hw->fc.current_mode = e1000_fc_default; 2544 2545 igb_validate_mdi_setting(hw); 2546 2547 /* By default, support wake on port A */ 2548 if (hw->bus.func == 0) 2549 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2550 2551 /* Check the NVM for wake support on non-port A ports */ 2552 if (hw->mac.type >= e1000_82580) 2553 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2554 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2555 &eeprom_data); 2556 else if (hw->bus.func == 1) 2557 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2558 2559 if (eeprom_data & IGB_EEPROM_APME) 2560 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2561 2562 /* now that we have the eeprom settings, apply the special cases where 2563 * the eeprom may be wrong or the board simply won't support wake on 2564 * lan on a particular port 2565 */ 2566 switch (pdev->device) { 2567 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2568 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2569 break; 2570 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2571 case E1000_DEV_ID_82576_FIBER: 2572 case E1000_DEV_ID_82576_SERDES: 2573 /* Wake events only supported on port A for dual fiber 2574 * regardless of eeprom setting 2575 */ 2576 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2577 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2578 break; 2579 case E1000_DEV_ID_82576_QUAD_COPPER: 2580 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2581 /* if quad port adapter, disable WoL on all but port A */ 2582 if (global_quad_port_a != 0) 2583 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2584 else 2585 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2586 /* Reset for multiple quad port adapters */ 2587 if (++global_quad_port_a == 4) 2588 global_quad_port_a = 0; 2589 break; 2590 default: 2591 /* If the device can't wake, don't set software support */ 2592 if (!device_can_wakeup(&adapter->pdev->dev)) 2593 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2594 } 2595 2596 /* initialize the wol settings based on the eeprom settings */ 2597 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2598 adapter->wol |= E1000_WUFC_MAG; 2599 2600 /* Some vendors want WoL disabled by default, but still supported */ 2601 if ((hw->mac.type == e1000_i350) && 2602 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2603 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2604 adapter->wol = 0; 2605 } 2606 2607 /* Some vendors want the ability to Use the EEPROM setting as 2608 * enable/disable only, and not for capability 2609 */ 2610 if (((hw->mac.type == e1000_i350) || 2611 (hw->mac.type == e1000_i354)) && 2612 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2613 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2614 adapter->wol = 0; 2615 } 2616 if (hw->mac.type == e1000_i350) { 2617 if (((pdev->subsystem_device == 0x5001) || 2618 (pdev->subsystem_device == 0x5002)) && 2619 (hw->bus.func == 0)) { 2620 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2621 adapter->wol = 0; 2622 } 2623 if (pdev->subsystem_device == 0x1F52) 2624 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2625 } 2626 2627 device_set_wakeup_enable(&adapter->pdev->dev, 2628 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2629 2630 /* reset the hardware with the new settings */ 2631 igb_reset(adapter); 2632 2633 /* Init the I2C interface */ 2634 err = igb_init_i2c(adapter); 2635 if (err) { 2636 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2637 goto err_eeprom; 2638 } 2639 2640 /* let the f/w know that the h/w is now under the control of the 2641 * driver. 2642 */ 2643 igb_get_hw_control(adapter); 2644 2645 strcpy(netdev->name, "eth%d"); 2646 err = register_netdev(netdev); 2647 if (err) 2648 goto err_register; 2649 2650 /* carrier off reporting is important to ethtool even BEFORE open */ 2651 netif_carrier_off(netdev); 2652 2653 #ifdef CONFIG_IGB_DCA 2654 if (dca_add_requester(&pdev->dev) == 0) { 2655 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2656 dev_info(&pdev->dev, "DCA enabled\n"); 2657 igb_setup_dca(adapter); 2658 } 2659 2660 #endif 2661 #ifdef CONFIG_IGB_HWMON 2662 /* Initialize the thermal sensor on i350 devices. */ 2663 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2664 u16 ets_word; 2665 2666 /* Read the NVM to determine if this i350 device supports an 2667 * external thermal sensor. 2668 */ 2669 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2670 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2671 adapter->ets = true; 2672 else 2673 adapter->ets = false; 2674 if (igb_sysfs_init(adapter)) 2675 dev_err(&pdev->dev, 2676 "failed to allocate sysfs resources\n"); 2677 } else { 2678 adapter->ets = false; 2679 } 2680 #endif 2681 /* Check if Media Autosense is enabled */ 2682 adapter->ei = *ei; 2683 if (hw->dev_spec._82575.mas_capable) 2684 igb_init_mas(adapter); 2685 2686 /* do hw tstamp init after resetting */ 2687 igb_ptp_init(adapter); 2688 2689 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2690 /* print bus type/speed/width info, not applicable to i354 */ 2691 if (hw->mac.type != e1000_i354) { 2692 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2693 netdev->name, 2694 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2695 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2696 "unknown"), 2697 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2698 "Width x4" : 2699 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2700 "Width x2" : 2701 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2702 "Width x1" : "unknown"), netdev->dev_addr); 2703 } 2704 2705 if ((hw->mac.type >= e1000_i210 || 2706 igb_get_flash_presence_i210(hw))) { 2707 ret_val = igb_read_part_string(hw, part_str, 2708 E1000_PBANUM_LENGTH); 2709 } else { 2710 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2711 } 2712 2713 if (ret_val) 2714 strcpy(part_str, "Unknown"); 2715 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2716 dev_info(&pdev->dev, 2717 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2718 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2719 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2720 adapter->num_rx_queues, adapter->num_tx_queues); 2721 if (hw->phy.media_type == e1000_media_type_copper) { 2722 switch (hw->mac.type) { 2723 case e1000_i350: 2724 case e1000_i210: 2725 case e1000_i211: 2726 /* Enable EEE for internal copper PHY devices */ 2727 err = igb_set_eee_i350(hw, true, true); 2728 if ((!err) && 2729 (!hw->dev_spec._82575.eee_disable)) { 2730 adapter->eee_advert = 2731 MDIO_EEE_100TX | MDIO_EEE_1000T; 2732 adapter->flags |= IGB_FLAG_EEE; 2733 } 2734 break; 2735 case e1000_i354: 2736 if ((rd32(E1000_CTRL_EXT) & 2737 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2738 err = igb_set_eee_i354(hw, true, true); 2739 if ((!err) && 2740 (!hw->dev_spec._82575.eee_disable)) { 2741 adapter->eee_advert = 2742 MDIO_EEE_100TX | MDIO_EEE_1000T; 2743 adapter->flags |= IGB_FLAG_EEE; 2744 } 2745 } 2746 break; 2747 default: 2748 break; 2749 } 2750 } 2751 pm_runtime_put_noidle(&pdev->dev); 2752 return 0; 2753 2754 err_register: 2755 igb_release_hw_control(adapter); 2756 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2757 err_eeprom: 2758 if (!igb_check_reset_block(hw)) 2759 igb_reset_phy(hw); 2760 2761 if (hw->flash_address) 2762 iounmap(hw->flash_address); 2763 err_sw_init: 2764 kfree(adapter->shadow_vfta); 2765 igb_clear_interrupt_scheme(adapter); 2766 #ifdef CONFIG_PCI_IOV 2767 igb_disable_sriov(pdev); 2768 #endif 2769 pci_iounmap(pdev, adapter->io_addr); 2770 err_ioremap: 2771 free_netdev(netdev); 2772 err_alloc_etherdev: 2773 pci_release_mem_regions(pdev); 2774 err_pci_reg: 2775 err_dma: 2776 pci_disable_device(pdev); 2777 return err; 2778 } 2779 2780 #ifdef CONFIG_PCI_IOV 2781 static int igb_disable_sriov(struct pci_dev *pdev) 2782 { 2783 struct net_device *netdev = pci_get_drvdata(pdev); 2784 struct igb_adapter *adapter = netdev_priv(netdev); 2785 struct e1000_hw *hw = &adapter->hw; 2786 2787 /* reclaim resources allocated to VFs */ 2788 if (adapter->vf_data) { 2789 /* disable iov and allow time for transactions to clear */ 2790 if (pci_vfs_assigned(pdev)) { 2791 dev_warn(&pdev->dev, 2792 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2793 return -EPERM; 2794 } else { 2795 pci_disable_sriov(pdev); 2796 msleep(500); 2797 } 2798 2799 kfree(adapter->vf_data); 2800 adapter->vf_data = NULL; 2801 adapter->vfs_allocated_count = 0; 2802 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2803 wrfl(); 2804 msleep(100); 2805 dev_info(&pdev->dev, "IOV Disabled\n"); 2806 2807 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2808 adapter->flags |= IGB_FLAG_DMAC; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2815 { 2816 struct net_device *netdev = pci_get_drvdata(pdev); 2817 struct igb_adapter *adapter = netdev_priv(netdev); 2818 int old_vfs = pci_num_vf(pdev); 2819 int err = 0; 2820 int i; 2821 2822 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2823 err = -EPERM; 2824 goto out; 2825 } 2826 if (!num_vfs) 2827 goto out; 2828 2829 if (old_vfs) { 2830 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2831 old_vfs, max_vfs); 2832 adapter->vfs_allocated_count = old_vfs; 2833 } else 2834 adapter->vfs_allocated_count = num_vfs; 2835 2836 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2837 sizeof(struct vf_data_storage), GFP_KERNEL); 2838 2839 /* if allocation failed then we do not support SR-IOV */ 2840 if (!adapter->vf_data) { 2841 adapter->vfs_allocated_count = 0; 2842 dev_err(&pdev->dev, 2843 "Unable to allocate memory for VF Data Storage\n"); 2844 err = -ENOMEM; 2845 goto out; 2846 } 2847 2848 /* only call pci_enable_sriov() if no VFs are allocated already */ 2849 if (!old_vfs) { 2850 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2851 if (err) 2852 goto err_out; 2853 } 2854 dev_info(&pdev->dev, "%d VFs allocated\n", 2855 adapter->vfs_allocated_count); 2856 for (i = 0; i < adapter->vfs_allocated_count; i++) 2857 igb_vf_configure(adapter, i); 2858 2859 /* DMA Coalescing is not supported in IOV mode. */ 2860 adapter->flags &= ~IGB_FLAG_DMAC; 2861 goto out; 2862 2863 err_out: 2864 kfree(adapter->vf_data); 2865 adapter->vf_data = NULL; 2866 adapter->vfs_allocated_count = 0; 2867 out: 2868 return err; 2869 } 2870 2871 #endif 2872 /** 2873 * igb_remove_i2c - Cleanup I2C interface 2874 * @adapter: pointer to adapter structure 2875 **/ 2876 static void igb_remove_i2c(struct igb_adapter *adapter) 2877 { 2878 /* free the adapter bus structure */ 2879 i2c_del_adapter(&adapter->i2c_adap); 2880 } 2881 2882 /** 2883 * igb_remove - Device Removal Routine 2884 * @pdev: PCI device information struct 2885 * 2886 * igb_remove is called by the PCI subsystem to alert the driver 2887 * that it should release a PCI device. The could be caused by a 2888 * Hot-Plug event, or because the driver is going to be removed from 2889 * memory. 2890 **/ 2891 static void igb_remove(struct pci_dev *pdev) 2892 { 2893 struct net_device *netdev = pci_get_drvdata(pdev); 2894 struct igb_adapter *adapter = netdev_priv(netdev); 2895 struct e1000_hw *hw = &adapter->hw; 2896 2897 pm_runtime_get_noresume(&pdev->dev); 2898 #ifdef CONFIG_IGB_HWMON 2899 igb_sysfs_exit(adapter); 2900 #endif 2901 igb_remove_i2c(adapter); 2902 igb_ptp_stop(adapter); 2903 /* The watchdog timer may be rescheduled, so explicitly 2904 * disable watchdog from being rescheduled. 2905 */ 2906 set_bit(__IGB_DOWN, &adapter->state); 2907 del_timer_sync(&adapter->watchdog_timer); 2908 del_timer_sync(&adapter->phy_info_timer); 2909 2910 cancel_work_sync(&adapter->reset_task); 2911 cancel_work_sync(&adapter->watchdog_task); 2912 2913 #ifdef CONFIG_IGB_DCA 2914 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2915 dev_info(&pdev->dev, "DCA disabled\n"); 2916 dca_remove_requester(&pdev->dev); 2917 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2918 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2919 } 2920 #endif 2921 2922 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2923 * would have already happened in close and is redundant. 2924 */ 2925 igb_release_hw_control(adapter); 2926 2927 #ifdef CONFIG_PCI_IOV 2928 igb_disable_sriov(pdev); 2929 #endif 2930 2931 unregister_netdev(netdev); 2932 2933 igb_clear_interrupt_scheme(adapter); 2934 2935 pci_iounmap(pdev, adapter->io_addr); 2936 if (hw->flash_address) 2937 iounmap(hw->flash_address); 2938 pci_release_mem_regions(pdev); 2939 2940 kfree(adapter->shadow_vfta); 2941 free_netdev(netdev); 2942 2943 pci_disable_pcie_error_reporting(pdev); 2944 2945 pci_disable_device(pdev); 2946 } 2947 2948 /** 2949 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2950 * @adapter: board private structure to initialize 2951 * 2952 * This function initializes the vf specific data storage and then attempts to 2953 * allocate the VFs. The reason for ordering it this way is because it is much 2954 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2955 * the memory for the VFs. 2956 **/ 2957 static void igb_probe_vfs(struct igb_adapter *adapter) 2958 { 2959 #ifdef CONFIG_PCI_IOV 2960 struct pci_dev *pdev = adapter->pdev; 2961 struct e1000_hw *hw = &adapter->hw; 2962 2963 /* Virtualization features not supported on i210 family. */ 2964 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2965 return; 2966 2967 /* Of the below we really only want the effect of getting 2968 * IGB_FLAG_HAS_MSIX set (if available), without which 2969 * igb_enable_sriov() has no effect. 2970 */ 2971 igb_set_interrupt_capability(adapter, true); 2972 igb_reset_interrupt_capability(adapter); 2973 2974 pci_sriov_set_totalvfs(pdev, 7); 2975 igb_enable_sriov(pdev, max_vfs); 2976 2977 #endif /* CONFIG_PCI_IOV */ 2978 } 2979 2980 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2981 { 2982 struct e1000_hw *hw = &adapter->hw; 2983 u32 max_rss_queues; 2984 2985 /* Determine the maximum number of RSS queues supported. */ 2986 switch (hw->mac.type) { 2987 case e1000_i211: 2988 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2989 break; 2990 case e1000_82575: 2991 case e1000_i210: 2992 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2993 break; 2994 case e1000_i350: 2995 /* I350 cannot do RSS and SR-IOV at the same time */ 2996 if (!!adapter->vfs_allocated_count) { 2997 max_rss_queues = 1; 2998 break; 2999 } 3000 /* fall through */ 3001 case e1000_82576: 3002 if (!!adapter->vfs_allocated_count) { 3003 max_rss_queues = 2; 3004 break; 3005 } 3006 /* fall through */ 3007 case e1000_82580: 3008 case e1000_i354: 3009 default: 3010 max_rss_queues = IGB_MAX_RX_QUEUES; 3011 break; 3012 } 3013 3014 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3015 3016 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3017 } 3018 3019 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3020 const u32 max_rss_queues) 3021 { 3022 struct e1000_hw *hw = &adapter->hw; 3023 3024 /* Determine if we need to pair queues. */ 3025 switch (hw->mac.type) { 3026 case e1000_82575: 3027 case e1000_i211: 3028 /* Device supports enough interrupts without queue pairing. */ 3029 break; 3030 case e1000_82576: 3031 case e1000_82580: 3032 case e1000_i350: 3033 case e1000_i354: 3034 case e1000_i210: 3035 default: 3036 /* If rss_queues > half of max_rss_queues, pair the queues in 3037 * order to conserve interrupts due to limited supply. 3038 */ 3039 if (adapter->rss_queues > (max_rss_queues / 2)) 3040 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3041 else 3042 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3043 break; 3044 } 3045 } 3046 3047 /** 3048 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3049 * @adapter: board private structure to initialize 3050 * 3051 * igb_sw_init initializes the Adapter private data structure. 3052 * Fields are initialized based on PCI device information and 3053 * OS network device settings (MTU size). 3054 **/ 3055 static int igb_sw_init(struct igb_adapter *adapter) 3056 { 3057 struct e1000_hw *hw = &adapter->hw; 3058 struct net_device *netdev = adapter->netdev; 3059 struct pci_dev *pdev = adapter->pdev; 3060 3061 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3062 3063 /* set default ring sizes */ 3064 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3065 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3066 3067 /* set default ITR values */ 3068 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3069 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3070 3071 /* set default work limits */ 3072 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3073 3074 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3075 VLAN_HLEN; 3076 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3077 3078 spin_lock_init(&adapter->nfc_lock); 3079 spin_lock_init(&adapter->stats64_lock); 3080 #ifdef CONFIG_PCI_IOV 3081 switch (hw->mac.type) { 3082 case e1000_82576: 3083 case e1000_i350: 3084 if (max_vfs > 7) { 3085 dev_warn(&pdev->dev, 3086 "Maximum of 7 VFs per PF, using max\n"); 3087 max_vfs = adapter->vfs_allocated_count = 7; 3088 } else 3089 adapter->vfs_allocated_count = max_vfs; 3090 if (adapter->vfs_allocated_count) 3091 dev_warn(&pdev->dev, 3092 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3093 break; 3094 default: 3095 break; 3096 } 3097 #endif /* CONFIG_PCI_IOV */ 3098 3099 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3100 adapter->flags |= IGB_FLAG_HAS_MSIX; 3101 3102 igb_probe_vfs(adapter); 3103 3104 igb_init_queue_configuration(adapter); 3105 3106 /* Setup and initialize a copy of the hw vlan table array */ 3107 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3108 GFP_ATOMIC); 3109 3110 /* This call may decrease the number of queues */ 3111 if (igb_init_interrupt_scheme(adapter, true)) { 3112 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3113 return -ENOMEM; 3114 } 3115 3116 /* Explicitly disable IRQ since the NIC can be in any state. */ 3117 igb_irq_disable(adapter); 3118 3119 if (hw->mac.type >= e1000_i350) 3120 adapter->flags &= ~IGB_FLAG_DMAC; 3121 3122 set_bit(__IGB_DOWN, &adapter->state); 3123 return 0; 3124 } 3125 3126 /** 3127 * igb_open - Called when a network interface is made active 3128 * @netdev: network interface device structure 3129 * 3130 * Returns 0 on success, negative value on failure 3131 * 3132 * The open entry point is called when a network interface is made 3133 * active by the system (IFF_UP). At this point all resources needed 3134 * for transmit and receive operations are allocated, the interrupt 3135 * handler is registered with the OS, the watchdog timer is started, 3136 * and the stack is notified that the interface is ready. 3137 **/ 3138 static int __igb_open(struct net_device *netdev, bool resuming) 3139 { 3140 struct igb_adapter *adapter = netdev_priv(netdev); 3141 struct e1000_hw *hw = &adapter->hw; 3142 struct pci_dev *pdev = adapter->pdev; 3143 int err; 3144 int i; 3145 3146 /* disallow open during test */ 3147 if (test_bit(__IGB_TESTING, &adapter->state)) { 3148 WARN_ON(resuming); 3149 return -EBUSY; 3150 } 3151 3152 if (!resuming) 3153 pm_runtime_get_sync(&pdev->dev); 3154 3155 netif_carrier_off(netdev); 3156 3157 /* allocate transmit descriptors */ 3158 err = igb_setup_all_tx_resources(adapter); 3159 if (err) 3160 goto err_setup_tx; 3161 3162 /* allocate receive descriptors */ 3163 err = igb_setup_all_rx_resources(adapter); 3164 if (err) 3165 goto err_setup_rx; 3166 3167 igb_power_up_link(adapter); 3168 3169 /* before we allocate an interrupt, we must be ready to handle it. 3170 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3171 * as soon as we call pci_request_irq, so we have to setup our 3172 * clean_rx handler before we do so. 3173 */ 3174 igb_configure(adapter); 3175 3176 err = igb_request_irq(adapter); 3177 if (err) 3178 goto err_req_irq; 3179 3180 /* Notify the stack of the actual queue counts. */ 3181 err = netif_set_real_num_tx_queues(adapter->netdev, 3182 adapter->num_tx_queues); 3183 if (err) 3184 goto err_set_queues; 3185 3186 err = netif_set_real_num_rx_queues(adapter->netdev, 3187 adapter->num_rx_queues); 3188 if (err) 3189 goto err_set_queues; 3190 3191 /* From here on the code is the same as igb_up() */ 3192 clear_bit(__IGB_DOWN, &adapter->state); 3193 3194 for (i = 0; i < adapter->num_q_vectors; i++) 3195 napi_enable(&(adapter->q_vector[i]->napi)); 3196 3197 /* Clear any pending interrupts. */ 3198 rd32(E1000_ICR); 3199 3200 igb_irq_enable(adapter); 3201 3202 /* notify VFs that reset has been completed */ 3203 if (adapter->vfs_allocated_count) { 3204 u32 reg_data = rd32(E1000_CTRL_EXT); 3205 3206 reg_data |= E1000_CTRL_EXT_PFRSTD; 3207 wr32(E1000_CTRL_EXT, reg_data); 3208 } 3209 3210 netif_tx_start_all_queues(netdev); 3211 3212 if (!resuming) 3213 pm_runtime_put(&pdev->dev); 3214 3215 /* start the watchdog. */ 3216 hw->mac.get_link_status = 1; 3217 schedule_work(&adapter->watchdog_task); 3218 3219 return 0; 3220 3221 err_set_queues: 3222 igb_free_irq(adapter); 3223 err_req_irq: 3224 igb_release_hw_control(adapter); 3225 igb_power_down_link(adapter); 3226 igb_free_all_rx_resources(adapter); 3227 err_setup_rx: 3228 igb_free_all_tx_resources(adapter); 3229 err_setup_tx: 3230 igb_reset(adapter); 3231 if (!resuming) 3232 pm_runtime_put(&pdev->dev); 3233 3234 return err; 3235 } 3236 3237 int igb_open(struct net_device *netdev) 3238 { 3239 return __igb_open(netdev, false); 3240 } 3241 3242 /** 3243 * igb_close - Disables a network interface 3244 * @netdev: network interface device structure 3245 * 3246 * Returns 0, this is not allowed to fail 3247 * 3248 * The close entry point is called when an interface is de-activated 3249 * by the OS. The hardware is still under the driver's control, but 3250 * needs to be disabled. A global MAC reset is issued to stop the 3251 * hardware, and all transmit and receive resources are freed. 3252 **/ 3253 static int __igb_close(struct net_device *netdev, bool suspending) 3254 { 3255 struct igb_adapter *adapter = netdev_priv(netdev); 3256 struct pci_dev *pdev = adapter->pdev; 3257 3258 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3259 3260 if (!suspending) 3261 pm_runtime_get_sync(&pdev->dev); 3262 3263 igb_down(adapter); 3264 igb_free_irq(adapter); 3265 3266 igb_nfc_filter_exit(adapter); 3267 3268 igb_free_all_tx_resources(adapter); 3269 igb_free_all_rx_resources(adapter); 3270 3271 if (!suspending) 3272 pm_runtime_put_sync(&pdev->dev); 3273 return 0; 3274 } 3275 3276 int igb_close(struct net_device *netdev) 3277 { 3278 return __igb_close(netdev, false); 3279 } 3280 3281 /** 3282 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3283 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3284 * 3285 * Return 0 on success, negative on failure 3286 **/ 3287 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3288 { 3289 struct device *dev = tx_ring->dev; 3290 int size; 3291 3292 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3293 3294 tx_ring->tx_buffer_info = vzalloc(size); 3295 if (!tx_ring->tx_buffer_info) 3296 goto err; 3297 3298 /* round up to nearest 4K */ 3299 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3300 tx_ring->size = ALIGN(tx_ring->size, 4096); 3301 3302 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3303 &tx_ring->dma, GFP_KERNEL); 3304 if (!tx_ring->desc) 3305 goto err; 3306 3307 tx_ring->next_to_use = 0; 3308 tx_ring->next_to_clean = 0; 3309 3310 return 0; 3311 3312 err: 3313 vfree(tx_ring->tx_buffer_info); 3314 tx_ring->tx_buffer_info = NULL; 3315 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3316 return -ENOMEM; 3317 } 3318 3319 /** 3320 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3321 * (Descriptors) for all queues 3322 * @adapter: board private structure 3323 * 3324 * Return 0 on success, negative on failure 3325 **/ 3326 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3327 { 3328 struct pci_dev *pdev = adapter->pdev; 3329 int i, err = 0; 3330 3331 for (i = 0; i < adapter->num_tx_queues; i++) { 3332 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3333 if (err) { 3334 dev_err(&pdev->dev, 3335 "Allocation for Tx Queue %u failed\n", i); 3336 for (i--; i >= 0; i--) 3337 igb_free_tx_resources(adapter->tx_ring[i]); 3338 break; 3339 } 3340 } 3341 3342 return err; 3343 } 3344 3345 /** 3346 * igb_setup_tctl - configure the transmit control registers 3347 * @adapter: Board private structure 3348 **/ 3349 void igb_setup_tctl(struct igb_adapter *adapter) 3350 { 3351 struct e1000_hw *hw = &adapter->hw; 3352 u32 tctl; 3353 3354 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3355 wr32(E1000_TXDCTL(0), 0); 3356 3357 /* Program the Transmit Control Register */ 3358 tctl = rd32(E1000_TCTL); 3359 tctl &= ~E1000_TCTL_CT; 3360 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3361 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3362 3363 igb_config_collision_dist(hw); 3364 3365 /* Enable transmits */ 3366 tctl |= E1000_TCTL_EN; 3367 3368 wr32(E1000_TCTL, tctl); 3369 } 3370 3371 /** 3372 * igb_configure_tx_ring - Configure transmit ring after Reset 3373 * @adapter: board private structure 3374 * @ring: tx ring to configure 3375 * 3376 * Configure a transmit ring after a reset. 3377 **/ 3378 void igb_configure_tx_ring(struct igb_adapter *adapter, 3379 struct igb_ring *ring) 3380 { 3381 struct e1000_hw *hw = &adapter->hw; 3382 u32 txdctl = 0; 3383 u64 tdba = ring->dma; 3384 int reg_idx = ring->reg_idx; 3385 3386 /* disable the queue */ 3387 wr32(E1000_TXDCTL(reg_idx), 0); 3388 wrfl(); 3389 mdelay(10); 3390 3391 wr32(E1000_TDLEN(reg_idx), 3392 ring->count * sizeof(union e1000_adv_tx_desc)); 3393 wr32(E1000_TDBAL(reg_idx), 3394 tdba & 0x00000000ffffffffULL); 3395 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3396 3397 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3398 wr32(E1000_TDH(reg_idx), 0); 3399 writel(0, ring->tail); 3400 3401 txdctl |= IGB_TX_PTHRESH; 3402 txdctl |= IGB_TX_HTHRESH << 8; 3403 txdctl |= IGB_TX_WTHRESH << 16; 3404 3405 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3406 wr32(E1000_TXDCTL(reg_idx), txdctl); 3407 } 3408 3409 /** 3410 * igb_configure_tx - Configure transmit Unit after Reset 3411 * @adapter: board private structure 3412 * 3413 * Configure the Tx unit of the MAC after a reset. 3414 **/ 3415 static void igb_configure_tx(struct igb_adapter *adapter) 3416 { 3417 int i; 3418 3419 for (i = 0; i < adapter->num_tx_queues; i++) 3420 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3421 } 3422 3423 /** 3424 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3425 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3426 * 3427 * Returns 0 on success, negative on failure 3428 **/ 3429 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3430 { 3431 struct device *dev = rx_ring->dev; 3432 int size; 3433 3434 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3435 3436 rx_ring->rx_buffer_info = vzalloc(size); 3437 if (!rx_ring->rx_buffer_info) 3438 goto err; 3439 3440 /* Round up to nearest 4K */ 3441 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3442 rx_ring->size = ALIGN(rx_ring->size, 4096); 3443 3444 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3445 &rx_ring->dma, GFP_KERNEL); 3446 if (!rx_ring->desc) 3447 goto err; 3448 3449 rx_ring->next_to_alloc = 0; 3450 rx_ring->next_to_clean = 0; 3451 rx_ring->next_to_use = 0; 3452 3453 return 0; 3454 3455 err: 3456 vfree(rx_ring->rx_buffer_info); 3457 rx_ring->rx_buffer_info = NULL; 3458 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3459 return -ENOMEM; 3460 } 3461 3462 /** 3463 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3464 * (Descriptors) for all queues 3465 * @adapter: board private structure 3466 * 3467 * Return 0 on success, negative on failure 3468 **/ 3469 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3470 { 3471 struct pci_dev *pdev = adapter->pdev; 3472 int i, err = 0; 3473 3474 for (i = 0; i < adapter->num_rx_queues; i++) { 3475 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3476 if (err) { 3477 dev_err(&pdev->dev, 3478 "Allocation for Rx Queue %u failed\n", i); 3479 for (i--; i >= 0; i--) 3480 igb_free_rx_resources(adapter->rx_ring[i]); 3481 break; 3482 } 3483 } 3484 3485 return err; 3486 } 3487 3488 /** 3489 * igb_setup_mrqc - configure the multiple receive queue control registers 3490 * @adapter: Board private structure 3491 **/ 3492 static void igb_setup_mrqc(struct igb_adapter *adapter) 3493 { 3494 struct e1000_hw *hw = &adapter->hw; 3495 u32 mrqc, rxcsum; 3496 u32 j, num_rx_queues; 3497 u32 rss_key[10]; 3498 3499 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3500 for (j = 0; j < 10; j++) 3501 wr32(E1000_RSSRK(j), rss_key[j]); 3502 3503 num_rx_queues = adapter->rss_queues; 3504 3505 switch (hw->mac.type) { 3506 case e1000_82576: 3507 /* 82576 supports 2 RSS queues for SR-IOV */ 3508 if (adapter->vfs_allocated_count) 3509 num_rx_queues = 2; 3510 break; 3511 default: 3512 break; 3513 } 3514 3515 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3516 for (j = 0; j < IGB_RETA_SIZE; j++) 3517 adapter->rss_indir_tbl[j] = 3518 (j * num_rx_queues) / IGB_RETA_SIZE; 3519 adapter->rss_indir_tbl_init = num_rx_queues; 3520 } 3521 igb_write_rss_indir_tbl(adapter); 3522 3523 /* Disable raw packet checksumming so that RSS hash is placed in 3524 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3525 * offloads as they are enabled by default 3526 */ 3527 rxcsum = rd32(E1000_RXCSUM); 3528 rxcsum |= E1000_RXCSUM_PCSD; 3529 3530 if (adapter->hw.mac.type >= e1000_82576) 3531 /* Enable Receive Checksum Offload for SCTP */ 3532 rxcsum |= E1000_RXCSUM_CRCOFL; 3533 3534 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3535 wr32(E1000_RXCSUM, rxcsum); 3536 3537 /* Generate RSS hash based on packet types, TCP/UDP 3538 * port numbers and/or IPv4/v6 src and dst addresses 3539 */ 3540 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3541 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3542 E1000_MRQC_RSS_FIELD_IPV6 | 3543 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3544 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3545 3546 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3547 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3548 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3549 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3550 3551 /* If VMDq is enabled then we set the appropriate mode for that, else 3552 * we default to RSS so that an RSS hash is calculated per packet even 3553 * if we are only using one queue 3554 */ 3555 if (adapter->vfs_allocated_count) { 3556 if (hw->mac.type > e1000_82575) { 3557 /* Set the default pool for the PF's first queue */ 3558 u32 vtctl = rd32(E1000_VT_CTL); 3559 3560 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3561 E1000_VT_CTL_DISABLE_DEF_POOL); 3562 vtctl |= adapter->vfs_allocated_count << 3563 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3564 wr32(E1000_VT_CTL, vtctl); 3565 } 3566 if (adapter->rss_queues > 1) 3567 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3568 else 3569 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3570 } else { 3571 if (hw->mac.type != e1000_i211) 3572 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3573 } 3574 igb_vmm_control(adapter); 3575 3576 wr32(E1000_MRQC, mrqc); 3577 } 3578 3579 /** 3580 * igb_setup_rctl - configure the receive control registers 3581 * @adapter: Board private structure 3582 **/ 3583 void igb_setup_rctl(struct igb_adapter *adapter) 3584 { 3585 struct e1000_hw *hw = &adapter->hw; 3586 u32 rctl; 3587 3588 rctl = rd32(E1000_RCTL); 3589 3590 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3591 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3592 3593 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3594 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3595 3596 /* enable stripping of CRC. It's unlikely this will break BMC 3597 * redirection as it did with e1000. Newer features require 3598 * that the HW strips the CRC. 3599 */ 3600 rctl |= E1000_RCTL_SECRC; 3601 3602 /* disable store bad packets and clear size bits. */ 3603 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3604 3605 /* enable LPE to allow for reception of jumbo frames */ 3606 rctl |= E1000_RCTL_LPE; 3607 3608 /* disable queue 0 to prevent tail write w/o re-config */ 3609 wr32(E1000_RXDCTL(0), 0); 3610 3611 /* Attention!!! For SR-IOV PF driver operations you must enable 3612 * queue drop for all VF and PF queues to prevent head of line blocking 3613 * if an un-trusted VF does not provide descriptors to hardware. 3614 */ 3615 if (adapter->vfs_allocated_count) { 3616 /* set all queue drop enable bits */ 3617 wr32(E1000_QDE, ALL_QUEUES); 3618 } 3619 3620 /* This is useful for sniffing bad packets. */ 3621 if (adapter->netdev->features & NETIF_F_RXALL) { 3622 /* UPE and MPE will be handled by normal PROMISC logic 3623 * in e1000e_set_rx_mode 3624 */ 3625 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3626 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3627 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3628 3629 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3630 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3631 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3632 * and that breaks VLANs. 3633 */ 3634 } 3635 3636 wr32(E1000_RCTL, rctl); 3637 } 3638 3639 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3640 int vfn) 3641 { 3642 struct e1000_hw *hw = &adapter->hw; 3643 u32 vmolr; 3644 3645 if (size > MAX_JUMBO_FRAME_SIZE) 3646 size = MAX_JUMBO_FRAME_SIZE; 3647 3648 vmolr = rd32(E1000_VMOLR(vfn)); 3649 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3650 vmolr |= size | E1000_VMOLR_LPE; 3651 wr32(E1000_VMOLR(vfn), vmolr); 3652 3653 return 0; 3654 } 3655 3656 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3657 int vfn, bool enable) 3658 { 3659 struct e1000_hw *hw = &adapter->hw; 3660 u32 val, reg; 3661 3662 if (hw->mac.type < e1000_82576) 3663 return; 3664 3665 if (hw->mac.type == e1000_i350) 3666 reg = E1000_DVMOLR(vfn); 3667 else 3668 reg = E1000_VMOLR(vfn); 3669 3670 val = rd32(reg); 3671 if (enable) 3672 val |= E1000_VMOLR_STRVLAN; 3673 else 3674 val &= ~(E1000_VMOLR_STRVLAN); 3675 wr32(reg, val); 3676 } 3677 3678 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3679 int vfn, bool aupe) 3680 { 3681 struct e1000_hw *hw = &adapter->hw; 3682 u32 vmolr; 3683 3684 /* This register exists only on 82576 and newer so if we are older then 3685 * we should exit and do nothing 3686 */ 3687 if (hw->mac.type < e1000_82576) 3688 return; 3689 3690 vmolr = rd32(E1000_VMOLR(vfn)); 3691 if (aupe) 3692 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3693 else 3694 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3695 3696 /* clear all bits that might not be set */ 3697 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3698 3699 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3700 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3701 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3702 * multicast packets 3703 */ 3704 if (vfn <= adapter->vfs_allocated_count) 3705 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3706 3707 wr32(E1000_VMOLR(vfn), vmolr); 3708 } 3709 3710 /** 3711 * igb_configure_rx_ring - Configure a receive ring after Reset 3712 * @adapter: board private structure 3713 * @ring: receive ring to be configured 3714 * 3715 * Configure the Rx unit of the MAC after a reset. 3716 **/ 3717 void igb_configure_rx_ring(struct igb_adapter *adapter, 3718 struct igb_ring *ring) 3719 { 3720 struct e1000_hw *hw = &adapter->hw; 3721 u64 rdba = ring->dma; 3722 int reg_idx = ring->reg_idx; 3723 u32 srrctl = 0, rxdctl = 0; 3724 3725 /* disable the queue */ 3726 wr32(E1000_RXDCTL(reg_idx), 0); 3727 3728 /* Set DMA base address registers */ 3729 wr32(E1000_RDBAL(reg_idx), 3730 rdba & 0x00000000ffffffffULL); 3731 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3732 wr32(E1000_RDLEN(reg_idx), 3733 ring->count * sizeof(union e1000_adv_rx_desc)); 3734 3735 /* initialize head and tail */ 3736 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3737 wr32(E1000_RDH(reg_idx), 0); 3738 writel(0, ring->tail); 3739 3740 /* set descriptor configuration */ 3741 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3742 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3743 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3744 if (hw->mac.type >= e1000_82580) 3745 srrctl |= E1000_SRRCTL_TIMESTAMP; 3746 /* Only set Drop Enable if we are supporting multiple queues */ 3747 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3748 srrctl |= E1000_SRRCTL_DROP_EN; 3749 3750 wr32(E1000_SRRCTL(reg_idx), srrctl); 3751 3752 /* set filtering for VMDQ pools */ 3753 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3754 3755 rxdctl |= IGB_RX_PTHRESH; 3756 rxdctl |= IGB_RX_HTHRESH << 8; 3757 rxdctl |= IGB_RX_WTHRESH << 16; 3758 3759 /* enable receive descriptor fetching */ 3760 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3761 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3762 } 3763 3764 /** 3765 * igb_configure_rx - Configure receive Unit after Reset 3766 * @adapter: board private structure 3767 * 3768 * Configure the Rx unit of the MAC after a reset. 3769 **/ 3770 static void igb_configure_rx(struct igb_adapter *adapter) 3771 { 3772 int i; 3773 3774 /* set the correct pool for the PF default MAC address in entry 0 */ 3775 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3776 adapter->vfs_allocated_count); 3777 3778 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3779 * the Base and Length of the Rx Descriptor Ring 3780 */ 3781 for (i = 0; i < adapter->num_rx_queues; i++) 3782 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3783 } 3784 3785 /** 3786 * igb_free_tx_resources - Free Tx Resources per Queue 3787 * @tx_ring: Tx descriptor ring for a specific queue 3788 * 3789 * Free all transmit software resources 3790 **/ 3791 void igb_free_tx_resources(struct igb_ring *tx_ring) 3792 { 3793 igb_clean_tx_ring(tx_ring); 3794 3795 vfree(tx_ring->tx_buffer_info); 3796 tx_ring->tx_buffer_info = NULL; 3797 3798 /* if not set, then don't free */ 3799 if (!tx_ring->desc) 3800 return; 3801 3802 dma_free_coherent(tx_ring->dev, tx_ring->size, 3803 tx_ring->desc, tx_ring->dma); 3804 3805 tx_ring->desc = NULL; 3806 } 3807 3808 /** 3809 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3810 * @adapter: board private structure 3811 * 3812 * Free all transmit software resources 3813 **/ 3814 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3815 { 3816 int i; 3817 3818 for (i = 0; i < adapter->num_tx_queues; i++) 3819 if (adapter->tx_ring[i]) 3820 igb_free_tx_resources(adapter->tx_ring[i]); 3821 } 3822 3823 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3824 struct igb_tx_buffer *tx_buffer) 3825 { 3826 if (tx_buffer->skb) { 3827 dev_kfree_skb_any(tx_buffer->skb); 3828 if (dma_unmap_len(tx_buffer, len)) 3829 dma_unmap_single(ring->dev, 3830 dma_unmap_addr(tx_buffer, dma), 3831 dma_unmap_len(tx_buffer, len), 3832 DMA_TO_DEVICE); 3833 } else if (dma_unmap_len(tx_buffer, len)) { 3834 dma_unmap_page(ring->dev, 3835 dma_unmap_addr(tx_buffer, dma), 3836 dma_unmap_len(tx_buffer, len), 3837 DMA_TO_DEVICE); 3838 } 3839 tx_buffer->next_to_watch = NULL; 3840 tx_buffer->skb = NULL; 3841 dma_unmap_len_set(tx_buffer, len, 0); 3842 /* buffer_info must be completely set up in the transmit path */ 3843 } 3844 3845 /** 3846 * igb_clean_tx_ring - Free Tx Buffers 3847 * @tx_ring: ring to be cleaned 3848 **/ 3849 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3850 { 3851 struct igb_tx_buffer *buffer_info; 3852 unsigned long size; 3853 u16 i; 3854 3855 if (!tx_ring->tx_buffer_info) 3856 return; 3857 /* Free all the Tx ring sk_buffs */ 3858 3859 for (i = 0; i < tx_ring->count; i++) { 3860 buffer_info = &tx_ring->tx_buffer_info[i]; 3861 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3862 } 3863 3864 netdev_tx_reset_queue(txring_txq(tx_ring)); 3865 3866 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3867 memset(tx_ring->tx_buffer_info, 0, size); 3868 3869 /* Zero out the descriptor ring */ 3870 memset(tx_ring->desc, 0, tx_ring->size); 3871 3872 tx_ring->next_to_use = 0; 3873 tx_ring->next_to_clean = 0; 3874 } 3875 3876 /** 3877 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3878 * @adapter: board private structure 3879 **/ 3880 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3881 { 3882 int i; 3883 3884 for (i = 0; i < adapter->num_tx_queues; i++) 3885 if (adapter->tx_ring[i]) 3886 igb_clean_tx_ring(adapter->tx_ring[i]); 3887 } 3888 3889 /** 3890 * igb_free_rx_resources - Free Rx Resources 3891 * @rx_ring: ring to clean the resources from 3892 * 3893 * Free all receive software resources 3894 **/ 3895 void igb_free_rx_resources(struct igb_ring *rx_ring) 3896 { 3897 igb_clean_rx_ring(rx_ring); 3898 3899 vfree(rx_ring->rx_buffer_info); 3900 rx_ring->rx_buffer_info = NULL; 3901 3902 /* if not set, then don't free */ 3903 if (!rx_ring->desc) 3904 return; 3905 3906 dma_free_coherent(rx_ring->dev, rx_ring->size, 3907 rx_ring->desc, rx_ring->dma); 3908 3909 rx_ring->desc = NULL; 3910 } 3911 3912 /** 3913 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3914 * @adapter: board private structure 3915 * 3916 * Free all receive software resources 3917 **/ 3918 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3919 { 3920 int i; 3921 3922 for (i = 0; i < adapter->num_rx_queues; i++) 3923 if (adapter->rx_ring[i]) 3924 igb_free_rx_resources(adapter->rx_ring[i]); 3925 } 3926 3927 /** 3928 * igb_clean_rx_ring - Free Rx Buffers per Queue 3929 * @rx_ring: ring to free buffers from 3930 **/ 3931 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3932 { 3933 unsigned long size; 3934 u16 i; 3935 3936 if (rx_ring->skb) 3937 dev_kfree_skb(rx_ring->skb); 3938 rx_ring->skb = NULL; 3939 3940 if (!rx_ring->rx_buffer_info) 3941 return; 3942 3943 /* Free all the Rx ring sk_buffs */ 3944 for (i = 0; i < rx_ring->count; i++) { 3945 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3946 3947 if (!buffer_info->page) 3948 continue; 3949 3950 dma_unmap_page(rx_ring->dev, 3951 buffer_info->dma, 3952 PAGE_SIZE, 3953 DMA_FROM_DEVICE); 3954 __free_page(buffer_info->page); 3955 3956 buffer_info->page = NULL; 3957 } 3958 3959 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3960 memset(rx_ring->rx_buffer_info, 0, size); 3961 3962 /* Zero out the descriptor ring */ 3963 memset(rx_ring->desc, 0, rx_ring->size); 3964 3965 rx_ring->next_to_alloc = 0; 3966 rx_ring->next_to_clean = 0; 3967 rx_ring->next_to_use = 0; 3968 } 3969 3970 /** 3971 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3972 * @adapter: board private structure 3973 **/ 3974 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3975 { 3976 int i; 3977 3978 for (i = 0; i < adapter->num_rx_queues; i++) 3979 if (adapter->rx_ring[i]) 3980 igb_clean_rx_ring(adapter->rx_ring[i]); 3981 } 3982 3983 /** 3984 * igb_set_mac - Change the Ethernet Address of the NIC 3985 * @netdev: network interface device structure 3986 * @p: pointer to an address structure 3987 * 3988 * Returns 0 on success, negative on failure 3989 **/ 3990 static int igb_set_mac(struct net_device *netdev, void *p) 3991 { 3992 struct igb_adapter *adapter = netdev_priv(netdev); 3993 struct e1000_hw *hw = &adapter->hw; 3994 struct sockaddr *addr = p; 3995 3996 if (!is_valid_ether_addr(addr->sa_data)) 3997 return -EADDRNOTAVAIL; 3998 3999 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4000 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4001 4002 /* set the correct pool for the new PF MAC address in entry 0 */ 4003 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 4004 adapter->vfs_allocated_count); 4005 4006 return 0; 4007 } 4008 4009 /** 4010 * igb_write_mc_addr_list - write multicast addresses to MTA 4011 * @netdev: network interface device structure 4012 * 4013 * Writes multicast address list to the MTA hash table. 4014 * Returns: -ENOMEM on failure 4015 * 0 on no addresses written 4016 * X on writing X addresses to MTA 4017 **/ 4018 static int igb_write_mc_addr_list(struct net_device *netdev) 4019 { 4020 struct igb_adapter *adapter = netdev_priv(netdev); 4021 struct e1000_hw *hw = &adapter->hw; 4022 struct netdev_hw_addr *ha; 4023 u8 *mta_list; 4024 int i; 4025 4026 if (netdev_mc_empty(netdev)) { 4027 /* nothing to program, so clear mc list */ 4028 igb_update_mc_addr_list(hw, NULL, 0); 4029 igb_restore_vf_multicasts(adapter); 4030 return 0; 4031 } 4032 4033 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4034 if (!mta_list) 4035 return -ENOMEM; 4036 4037 /* The shared function expects a packed array of only addresses. */ 4038 i = 0; 4039 netdev_for_each_mc_addr(ha, netdev) 4040 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4041 4042 igb_update_mc_addr_list(hw, mta_list, i); 4043 kfree(mta_list); 4044 4045 return netdev_mc_count(netdev); 4046 } 4047 4048 /** 4049 * igb_write_uc_addr_list - write unicast addresses to RAR table 4050 * @netdev: network interface device structure 4051 * 4052 * Writes unicast address list to the RAR table. 4053 * Returns: -ENOMEM on failure/insufficient address space 4054 * 0 on no addresses written 4055 * X on writing X addresses to the RAR table 4056 **/ 4057 static int igb_write_uc_addr_list(struct net_device *netdev) 4058 { 4059 struct igb_adapter *adapter = netdev_priv(netdev); 4060 struct e1000_hw *hw = &adapter->hw; 4061 unsigned int vfn = adapter->vfs_allocated_count; 4062 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 4063 int count = 0; 4064 4065 /* return ENOMEM indicating insufficient memory for addresses */ 4066 if (netdev_uc_count(netdev) > rar_entries) 4067 return -ENOMEM; 4068 4069 if (!netdev_uc_empty(netdev) && rar_entries) { 4070 struct netdev_hw_addr *ha; 4071 4072 netdev_for_each_uc_addr(ha, netdev) { 4073 if (!rar_entries) 4074 break; 4075 igb_rar_set_qsel(adapter, ha->addr, 4076 rar_entries--, 4077 vfn); 4078 count++; 4079 } 4080 } 4081 /* write the addresses in reverse order to avoid write combining */ 4082 for (; rar_entries > 0 ; rar_entries--) { 4083 wr32(E1000_RAH(rar_entries), 0); 4084 wr32(E1000_RAL(rar_entries), 0); 4085 } 4086 wrfl(); 4087 4088 return count; 4089 } 4090 4091 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4092 { 4093 struct e1000_hw *hw = &adapter->hw; 4094 u32 i, pf_id; 4095 4096 switch (hw->mac.type) { 4097 case e1000_i210: 4098 case e1000_i211: 4099 case e1000_i350: 4100 /* VLAN filtering needed for VLAN prio filter */ 4101 if (adapter->netdev->features & NETIF_F_NTUPLE) 4102 break; 4103 /* fall through */ 4104 case e1000_82576: 4105 case e1000_82580: 4106 case e1000_i354: 4107 /* VLAN filtering needed for pool filtering */ 4108 if (adapter->vfs_allocated_count) 4109 break; 4110 /* fall through */ 4111 default: 4112 return 1; 4113 } 4114 4115 /* We are already in VLAN promisc, nothing to do */ 4116 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4117 return 0; 4118 4119 if (!adapter->vfs_allocated_count) 4120 goto set_vfta; 4121 4122 /* Add PF to all active pools */ 4123 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4124 4125 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4126 u32 vlvf = rd32(E1000_VLVF(i)); 4127 4128 vlvf |= BIT(pf_id); 4129 wr32(E1000_VLVF(i), vlvf); 4130 } 4131 4132 set_vfta: 4133 /* Set all bits in the VLAN filter table array */ 4134 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4135 hw->mac.ops.write_vfta(hw, i, ~0U); 4136 4137 /* Set flag so we don't redo unnecessary work */ 4138 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4139 4140 return 0; 4141 } 4142 4143 #define VFTA_BLOCK_SIZE 8 4144 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4145 { 4146 struct e1000_hw *hw = &adapter->hw; 4147 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4148 u32 vid_start = vfta_offset * 32; 4149 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4150 u32 i, vid, word, bits, pf_id; 4151 4152 /* guarantee that we don't scrub out management VLAN */ 4153 vid = adapter->mng_vlan_id; 4154 if (vid >= vid_start && vid < vid_end) 4155 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4156 4157 if (!adapter->vfs_allocated_count) 4158 goto set_vfta; 4159 4160 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4161 4162 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4163 u32 vlvf = rd32(E1000_VLVF(i)); 4164 4165 /* pull VLAN ID from VLVF */ 4166 vid = vlvf & VLAN_VID_MASK; 4167 4168 /* only concern ourselves with a certain range */ 4169 if (vid < vid_start || vid >= vid_end) 4170 continue; 4171 4172 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4173 /* record VLAN ID in VFTA */ 4174 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4175 4176 /* if PF is part of this then continue */ 4177 if (test_bit(vid, adapter->active_vlans)) 4178 continue; 4179 } 4180 4181 /* remove PF from the pool */ 4182 bits = ~BIT(pf_id); 4183 bits &= rd32(E1000_VLVF(i)); 4184 wr32(E1000_VLVF(i), bits); 4185 } 4186 4187 set_vfta: 4188 /* extract values from active_vlans and write back to VFTA */ 4189 for (i = VFTA_BLOCK_SIZE; i--;) { 4190 vid = (vfta_offset + i) * 32; 4191 word = vid / BITS_PER_LONG; 4192 bits = vid % BITS_PER_LONG; 4193 4194 vfta[i] |= adapter->active_vlans[word] >> bits; 4195 4196 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4197 } 4198 } 4199 4200 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4201 { 4202 u32 i; 4203 4204 /* We are not in VLAN promisc, nothing to do */ 4205 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4206 return; 4207 4208 /* Set flag so we don't redo unnecessary work */ 4209 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4210 4211 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4212 igb_scrub_vfta(adapter, i); 4213 } 4214 4215 /** 4216 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4217 * @netdev: network interface device structure 4218 * 4219 * The set_rx_mode entry point is called whenever the unicast or multicast 4220 * address lists or the network interface flags are updated. This routine is 4221 * responsible for configuring the hardware for proper unicast, multicast, 4222 * promiscuous mode, and all-multi behavior. 4223 **/ 4224 static void igb_set_rx_mode(struct net_device *netdev) 4225 { 4226 struct igb_adapter *adapter = netdev_priv(netdev); 4227 struct e1000_hw *hw = &adapter->hw; 4228 unsigned int vfn = adapter->vfs_allocated_count; 4229 u32 rctl = 0, vmolr = 0; 4230 int count; 4231 4232 /* Check for Promiscuous and All Multicast modes */ 4233 if (netdev->flags & IFF_PROMISC) { 4234 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4235 vmolr |= E1000_VMOLR_MPME; 4236 4237 /* enable use of UTA filter to force packets to default pool */ 4238 if (hw->mac.type == e1000_82576) 4239 vmolr |= E1000_VMOLR_ROPE; 4240 } else { 4241 if (netdev->flags & IFF_ALLMULTI) { 4242 rctl |= E1000_RCTL_MPE; 4243 vmolr |= E1000_VMOLR_MPME; 4244 } else { 4245 /* Write addresses to the MTA, if the attempt fails 4246 * then we should just turn on promiscuous mode so 4247 * that we can at least receive multicast traffic 4248 */ 4249 count = igb_write_mc_addr_list(netdev); 4250 if (count < 0) { 4251 rctl |= E1000_RCTL_MPE; 4252 vmolr |= E1000_VMOLR_MPME; 4253 } else if (count) { 4254 vmolr |= E1000_VMOLR_ROMPE; 4255 } 4256 } 4257 } 4258 4259 /* Write addresses to available RAR registers, if there is not 4260 * sufficient space to store all the addresses then enable 4261 * unicast promiscuous mode 4262 */ 4263 count = igb_write_uc_addr_list(netdev); 4264 if (count < 0) { 4265 rctl |= E1000_RCTL_UPE; 4266 vmolr |= E1000_VMOLR_ROPE; 4267 } 4268 4269 /* enable VLAN filtering by default */ 4270 rctl |= E1000_RCTL_VFE; 4271 4272 /* disable VLAN filtering for modes that require it */ 4273 if ((netdev->flags & IFF_PROMISC) || 4274 (netdev->features & NETIF_F_RXALL)) { 4275 /* if we fail to set all rules then just clear VFE */ 4276 if (igb_vlan_promisc_enable(adapter)) 4277 rctl &= ~E1000_RCTL_VFE; 4278 } else { 4279 igb_vlan_promisc_disable(adapter); 4280 } 4281 4282 /* update state of unicast, multicast, and VLAN filtering modes */ 4283 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4284 E1000_RCTL_VFE); 4285 wr32(E1000_RCTL, rctl); 4286 4287 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4288 * the VMOLR to enable the appropriate modes. Without this workaround 4289 * we will have issues with VLAN tag stripping not being done for frames 4290 * that are only arriving because we are the default pool 4291 */ 4292 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4293 return; 4294 4295 /* set UTA to appropriate mode */ 4296 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4297 4298 vmolr |= rd32(E1000_VMOLR(vfn)) & 4299 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4300 4301 /* enable Rx jumbo frames, no need for restriction */ 4302 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4303 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE; 4304 4305 wr32(E1000_VMOLR(vfn), vmolr); 4306 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE); 4307 4308 igb_restore_vf_multicasts(adapter); 4309 } 4310 4311 static void igb_check_wvbr(struct igb_adapter *adapter) 4312 { 4313 struct e1000_hw *hw = &adapter->hw; 4314 u32 wvbr = 0; 4315 4316 switch (hw->mac.type) { 4317 case e1000_82576: 4318 case e1000_i350: 4319 wvbr = rd32(E1000_WVBR); 4320 if (!wvbr) 4321 return; 4322 break; 4323 default: 4324 break; 4325 } 4326 4327 adapter->wvbr |= wvbr; 4328 } 4329 4330 #define IGB_STAGGERED_QUEUE_OFFSET 8 4331 4332 static void igb_spoof_check(struct igb_adapter *adapter) 4333 { 4334 int j; 4335 4336 if (!adapter->wvbr) 4337 return; 4338 4339 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4340 if (adapter->wvbr & BIT(j) || 4341 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4342 dev_warn(&adapter->pdev->dev, 4343 "Spoof event(s) detected on VF %d\n", j); 4344 adapter->wvbr &= 4345 ~(BIT(j) | 4346 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4347 } 4348 } 4349 } 4350 4351 /* Need to wait a few seconds after link up to get diagnostic information from 4352 * the phy 4353 */ 4354 static void igb_update_phy_info(unsigned long data) 4355 { 4356 struct igb_adapter *adapter = (struct igb_adapter *) data; 4357 igb_get_phy_info(&adapter->hw); 4358 } 4359 4360 /** 4361 * igb_has_link - check shared code for link and determine up/down 4362 * @adapter: pointer to driver private info 4363 **/ 4364 bool igb_has_link(struct igb_adapter *adapter) 4365 { 4366 struct e1000_hw *hw = &adapter->hw; 4367 bool link_active = false; 4368 4369 /* get_link_status is set on LSC (link status) interrupt or 4370 * rx sequence error interrupt. get_link_status will stay 4371 * false until the e1000_check_for_link establishes link 4372 * for copper adapters ONLY 4373 */ 4374 switch (hw->phy.media_type) { 4375 case e1000_media_type_copper: 4376 if (!hw->mac.get_link_status) 4377 return true; 4378 case e1000_media_type_internal_serdes: 4379 hw->mac.ops.check_for_link(hw); 4380 link_active = !hw->mac.get_link_status; 4381 break; 4382 default: 4383 case e1000_media_type_unknown: 4384 break; 4385 } 4386 4387 if (((hw->mac.type == e1000_i210) || 4388 (hw->mac.type == e1000_i211)) && 4389 (hw->phy.id == I210_I_PHY_ID)) { 4390 if (!netif_carrier_ok(adapter->netdev)) { 4391 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4392 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4393 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4394 adapter->link_check_timeout = jiffies; 4395 } 4396 } 4397 4398 return link_active; 4399 } 4400 4401 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4402 { 4403 bool ret = false; 4404 u32 ctrl_ext, thstat; 4405 4406 /* check for thermal sensor event on i350 copper only */ 4407 if (hw->mac.type == e1000_i350) { 4408 thstat = rd32(E1000_THSTAT); 4409 ctrl_ext = rd32(E1000_CTRL_EXT); 4410 4411 if ((hw->phy.media_type == e1000_media_type_copper) && 4412 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4413 ret = !!(thstat & event); 4414 } 4415 4416 return ret; 4417 } 4418 4419 /** 4420 * igb_check_lvmmc - check for malformed packets received 4421 * and indicated in LVMMC register 4422 * @adapter: pointer to adapter 4423 **/ 4424 static void igb_check_lvmmc(struct igb_adapter *adapter) 4425 { 4426 struct e1000_hw *hw = &adapter->hw; 4427 u32 lvmmc; 4428 4429 lvmmc = rd32(E1000_LVMMC); 4430 if (lvmmc) { 4431 if (unlikely(net_ratelimit())) { 4432 netdev_warn(adapter->netdev, 4433 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4434 lvmmc); 4435 } 4436 } 4437 } 4438 4439 /** 4440 * igb_watchdog - Timer Call-back 4441 * @data: pointer to adapter cast into an unsigned long 4442 **/ 4443 static void igb_watchdog(unsigned long data) 4444 { 4445 struct igb_adapter *adapter = (struct igb_adapter *)data; 4446 /* Do the rest outside of interrupt context */ 4447 schedule_work(&adapter->watchdog_task); 4448 } 4449 4450 static void igb_watchdog_task(struct work_struct *work) 4451 { 4452 struct igb_adapter *adapter = container_of(work, 4453 struct igb_adapter, 4454 watchdog_task); 4455 struct e1000_hw *hw = &adapter->hw; 4456 struct e1000_phy_info *phy = &hw->phy; 4457 struct net_device *netdev = adapter->netdev; 4458 u32 link; 4459 int i; 4460 u32 connsw; 4461 u16 phy_data, retry_count = 20; 4462 4463 link = igb_has_link(adapter); 4464 4465 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4466 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4467 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4468 else 4469 link = false; 4470 } 4471 4472 /* Force link down if we have fiber to swap to */ 4473 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4474 if (hw->phy.media_type == e1000_media_type_copper) { 4475 connsw = rd32(E1000_CONNSW); 4476 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4477 link = 0; 4478 } 4479 } 4480 if (link) { 4481 /* Perform a reset if the media type changed. */ 4482 if (hw->dev_spec._82575.media_changed) { 4483 hw->dev_spec._82575.media_changed = false; 4484 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4485 igb_reset(adapter); 4486 } 4487 /* Cancel scheduled suspend requests. */ 4488 pm_runtime_resume(netdev->dev.parent); 4489 4490 if (!netif_carrier_ok(netdev)) { 4491 u32 ctrl; 4492 4493 hw->mac.ops.get_speed_and_duplex(hw, 4494 &adapter->link_speed, 4495 &adapter->link_duplex); 4496 4497 ctrl = rd32(E1000_CTRL); 4498 /* Links status message must follow this format */ 4499 netdev_info(netdev, 4500 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4501 netdev->name, 4502 adapter->link_speed, 4503 adapter->link_duplex == FULL_DUPLEX ? 4504 "Full" : "Half", 4505 (ctrl & E1000_CTRL_TFCE) && 4506 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4507 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4508 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4509 4510 /* disable EEE if enabled */ 4511 if ((adapter->flags & IGB_FLAG_EEE) && 4512 (adapter->link_duplex == HALF_DUPLEX)) { 4513 dev_info(&adapter->pdev->dev, 4514 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4515 adapter->hw.dev_spec._82575.eee_disable = true; 4516 adapter->flags &= ~IGB_FLAG_EEE; 4517 } 4518 4519 /* check if SmartSpeed worked */ 4520 igb_check_downshift(hw); 4521 if (phy->speed_downgraded) 4522 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4523 4524 /* check for thermal sensor event */ 4525 if (igb_thermal_sensor_event(hw, 4526 E1000_THSTAT_LINK_THROTTLE)) 4527 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4528 4529 /* adjust timeout factor according to speed/duplex */ 4530 adapter->tx_timeout_factor = 1; 4531 switch (adapter->link_speed) { 4532 case SPEED_10: 4533 adapter->tx_timeout_factor = 14; 4534 break; 4535 case SPEED_100: 4536 /* maybe add some timeout factor ? */ 4537 break; 4538 } 4539 4540 if (adapter->link_speed != SPEED_1000) 4541 goto no_wait; 4542 4543 /* wait for Remote receiver status OK */ 4544 retry_read_status: 4545 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4546 &phy_data)) { 4547 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4548 retry_count) { 4549 msleep(100); 4550 retry_count--; 4551 goto retry_read_status; 4552 } else if (!retry_count) { 4553 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4554 } 4555 } else { 4556 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4557 } 4558 no_wait: 4559 netif_carrier_on(netdev); 4560 4561 igb_ping_all_vfs(adapter); 4562 igb_check_vf_rate_limit(adapter); 4563 4564 /* link state has changed, schedule phy info update */ 4565 if (!test_bit(__IGB_DOWN, &adapter->state)) 4566 mod_timer(&adapter->phy_info_timer, 4567 round_jiffies(jiffies + 2 * HZ)); 4568 } 4569 } else { 4570 if (netif_carrier_ok(netdev)) { 4571 adapter->link_speed = 0; 4572 adapter->link_duplex = 0; 4573 4574 /* check for thermal sensor event */ 4575 if (igb_thermal_sensor_event(hw, 4576 E1000_THSTAT_PWR_DOWN)) { 4577 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4578 } 4579 4580 /* Links status message must follow this format */ 4581 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4582 netdev->name); 4583 netif_carrier_off(netdev); 4584 4585 igb_ping_all_vfs(adapter); 4586 4587 /* link state has changed, schedule phy info update */ 4588 if (!test_bit(__IGB_DOWN, &adapter->state)) 4589 mod_timer(&adapter->phy_info_timer, 4590 round_jiffies(jiffies + 2 * HZ)); 4591 4592 /* link is down, time to check for alternate media */ 4593 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4594 igb_check_swap_media(adapter); 4595 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4596 schedule_work(&adapter->reset_task); 4597 /* return immediately */ 4598 return; 4599 } 4600 } 4601 pm_schedule_suspend(netdev->dev.parent, 4602 MSEC_PER_SEC * 5); 4603 4604 /* also check for alternate media here */ 4605 } else if (!netif_carrier_ok(netdev) && 4606 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4607 igb_check_swap_media(adapter); 4608 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4609 schedule_work(&adapter->reset_task); 4610 /* return immediately */ 4611 return; 4612 } 4613 } 4614 } 4615 4616 spin_lock(&adapter->stats64_lock); 4617 igb_update_stats(adapter, &adapter->stats64); 4618 spin_unlock(&adapter->stats64_lock); 4619 4620 for (i = 0; i < adapter->num_tx_queues; i++) { 4621 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4622 if (!netif_carrier_ok(netdev)) { 4623 /* We've lost link, so the controller stops DMA, 4624 * but we've got queued Tx work that's never going 4625 * to get done, so reset controller to flush Tx. 4626 * (Do the reset outside of interrupt context). 4627 */ 4628 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4629 adapter->tx_timeout_count++; 4630 schedule_work(&adapter->reset_task); 4631 /* return immediately since reset is imminent */ 4632 return; 4633 } 4634 } 4635 4636 /* Force detection of hung controller every watchdog period */ 4637 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4638 } 4639 4640 /* Cause software interrupt to ensure Rx ring is cleaned */ 4641 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4642 u32 eics = 0; 4643 4644 for (i = 0; i < adapter->num_q_vectors; i++) 4645 eics |= adapter->q_vector[i]->eims_value; 4646 wr32(E1000_EICS, eics); 4647 } else { 4648 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4649 } 4650 4651 igb_spoof_check(adapter); 4652 igb_ptp_rx_hang(adapter); 4653 4654 /* Check LVMMC register on i350/i354 only */ 4655 if ((adapter->hw.mac.type == e1000_i350) || 4656 (adapter->hw.mac.type == e1000_i354)) 4657 igb_check_lvmmc(adapter); 4658 4659 /* Reset the timer */ 4660 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4661 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4662 mod_timer(&adapter->watchdog_timer, 4663 round_jiffies(jiffies + HZ)); 4664 else 4665 mod_timer(&adapter->watchdog_timer, 4666 round_jiffies(jiffies + 2 * HZ)); 4667 } 4668 } 4669 4670 enum latency_range { 4671 lowest_latency = 0, 4672 low_latency = 1, 4673 bulk_latency = 2, 4674 latency_invalid = 255 4675 }; 4676 4677 /** 4678 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4679 * @q_vector: pointer to q_vector 4680 * 4681 * Stores a new ITR value based on strictly on packet size. This 4682 * algorithm is less sophisticated than that used in igb_update_itr, 4683 * due to the difficulty of synchronizing statistics across multiple 4684 * receive rings. The divisors and thresholds used by this function 4685 * were determined based on theoretical maximum wire speed and testing 4686 * data, in order to minimize response time while increasing bulk 4687 * throughput. 4688 * This functionality is controlled by ethtool's coalescing settings. 4689 * NOTE: This function is called only when operating in a multiqueue 4690 * receive environment. 4691 **/ 4692 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4693 { 4694 int new_val = q_vector->itr_val; 4695 int avg_wire_size = 0; 4696 struct igb_adapter *adapter = q_vector->adapter; 4697 unsigned int packets; 4698 4699 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4700 * ints/sec - ITR timer value of 120 ticks. 4701 */ 4702 if (adapter->link_speed != SPEED_1000) { 4703 new_val = IGB_4K_ITR; 4704 goto set_itr_val; 4705 } 4706 4707 packets = q_vector->rx.total_packets; 4708 if (packets) 4709 avg_wire_size = q_vector->rx.total_bytes / packets; 4710 4711 packets = q_vector->tx.total_packets; 4712 if (packets) 4713 avg_wire_size = max_t(u32, avg_wire_size, 4714 q_vector->tx.total_bytes / packets); 4715 4716 /* if avg_wire_size isn't set no work was done */ 4717 if (!avg_wire_size) 4718 goto clear_counts; 4719 4720 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4721 avg_wire_size += 24; 4722 4723 /* Don't starve jumbo frames */ 4724 avg_wire_size = min(avg_wire_size, 3000); 4725 4726 /* Give a little boost to mid-size frames */ 4727 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4728 new_val = avg_wire_size / 3; 4729 else 4730 new_val = avg_wire_size / 2; 4731 4732 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4733 if (new_val < IGB_20K_ITR && 4734 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4735 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4736 new_val = IGB_20K_ITR; 4737 4738 set_itr_val: 4739 if (new_val != q_vector->itr_val) { 4740 q_vector->itr_val = new_val; 4741 q_vector->set_itr = 1; 4742 } 4743 clear_counts: 4744 q_vector->rx.total_bytes = 0; 4745 q_vector->rx.total_packets = 0; 4746 q_vector->tx.total_bytes = 0; 4747 q_vector->tx.total_packets = 0; 4748 } 4749 4750 /** 4751 * igb_update_itr - update the dynamic ITR value based on statistics 4752 * @q_vector: pointer to q_vector 4753 * @ring_container: ring info to update the itr for 4754 * 4755 * Stores a new ITR value based on packets and byte 4756 * counts during the last interrupt. The advantage of per interrupt 4757 * computation is faster updates and more accurate ITR for the current 4758 * traffic pattern. Constants in this function were computed 4759 * based on theoretical maximum wire speed and thresholds were set based 4760 * on testing data as well as attempting to minimize response time 4761 * while increasing bulk throughput. 4762 * This functionality is controlled by ethtool's coalescing settings. 4763 * NOTE: These calculations are only valid when operating in a single- 4764 * queue environment. 4765 **/ 4766 static void igb_update_itr(struct igb_q_vector *q_vector, 4767 struct igb_ring_container *ring_container) 4768 { 4769 unsigned int packets = ring_container->total_packets; 4770 unsigned int bytes = ring_container->total_bytes; 4771 u8 itrval = ring_container->itr; 4772 4773 /* no packets, exit with status unchanged */ 4774 if (packets == 0) 4775 return; 4776 4777 switch (itrval) { 4778 case lowest_latency: 4779 /* handle TSO and jumbo frames */ 4780 if (bytes/packets > 8000) 4781 itrval = bulk_latency; 4782 else if ((packets < 5) && (bytes > 512)) 4783 itrval = low_latency; 4784 break; 4785 case low_latency: /* 50 usec aka 20000 ints/s */ 4786 if (bytes > 10000) { 4787 /* this if handles the TSO accounting */ 4788 if (bytes/packets > 8000) 4789 itrval = bulk_latency; 4790 else if ((packets < 10) || ((bytes/packets) > 1200)) 4791 itrval = bulk_latency; 4792 else if ((packets > 35)) 4793 itrval = lowest_latency; 4794 } else if (bytes/packets > 2000) { 4795 itrval = bulk_latency; 4796 } else if (packets <= 2 && bytes < 512) { 4797 itrval = lowest_latency; 4798 } 4799 break; 4800 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4801 if (bytes > 25000) { 4802 if (packets > 35) 4803 itrval = low_latency; 4804 } else if (bytes < 1500) { 4805 itrval = low_latency; 4806 } 4807 break; 4808 } 4809 4810 /* clear work counters since we have the values we need */ 4811 ring_container->total_bytes = 0; 4812 ring_container->total_packets = 0; 4813 4814 /* write updated itr to ring container */ 4815 ring_container->itr = itrval; 4816 } 4817 4818 static void igb_set_itr(struct igb_q_vector *q_vector) 4819 { 4820 struct igb_adapter *adapter = q_vector->adapter; 4821 u32 new_itr = q_vector->itr_val; 4822 u8 current_itr = 0; 4823 4824 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4825 if (adapter->link_speed != SPEED_1000) { 4826 current_itr = 0; 4827 new_itr = IGB_4K_ITR; 4828 goto set_itr_now; 4829 } 4830 4831 igb_update_itr(q_vector, &q_vector->tx); 4832 igb_update_itr(q_vector, &q_vector->rx); 4833 4834 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4835 4836 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4837 if (current_itr == lowest_latency && 4838 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4839 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4840 current_itr = low_latency; 4841 4842 switch (current_itr) { 4843 /* counts and packets in update_itr are dependent on these numbers */ 4844 case lowest_latency: 4845 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4846 break; 4847 case low_latency: 4848 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4849 break; 4850 case bulk_latency: 4851 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4852 break; 4853 default: 4854 break; 4855 } 4856 4857 set_itr_now: 4858 if (new_itr != q_vector->itr_val) { 4859 /* this attempts to bias the interrupt rate towards Bulk 4860 * by adding intermediate steps when interrupt rate is 4861 * increasing 4862 */ 4863 new_itr = new_itr > q_vector->itr_val ? 4864 max((new_itr * q_vector->itr_val) / 4865 (new_itr + (q_vector->itr_val >> 2)), 4866 new_itr) : new_itr; 4867 /* Don't write the value here; it resets the adapter's 4868 * internal timer, and causes us to delay far longer than 4869 * we should between interrupts. Instead, we write the ITR 4870 * value at the beginning of the next interrupt so the timing 4871 * ends up being correct. 4872 */ 4873 q_vector->itr_val = new_itr; 4874 q_vector->set_itr = 1; 4875 } 4876 } 4877 4878 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4879 u32 type_tucmd, u32 mss_l4len_idx) 4880 { 4881 struct e1000_adv_tx_context_desc *context_desc; 4882 u16 i = tx_ring->next_to_use; 4883 4884 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4885 4886 i++; 4887 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4888 4889 /* set bits to identify this as an advanced context descriptor */ 4890 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4891 4892 /* For 82575, context index must be unique per ring. */ 4893 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4894 mss_l4len_idx |= tx_ring->reg_idx << 4; 4895 4896 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4897 context_desc->seqnum_seed = 0; 4898 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4899 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4900 } 4901 4902 static int igb_tso(struct igb_ring *tx_ring, 4903 struct igb_tx_buffer *first, 4904 u8 *hdr_len) 4905 { 4906 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4907 struct sk_buff *skb = first->skb; 4908 union { 4909 struct iphdr *v4; 4910 struct ipv6hdr *v6; 4911 unsigned char *hdr; 4912 } ip; 4913 union { 4914 struct tcphdr *tcp; 4915 unsigned char *hdr; 4916 } l4; 4917 u32 paylen, l4_offset; 4918 int err; 4919 4920 if (skb->ip_summed != CHECKSUM_PARTIAL) 4921 return 0; 4922 4923 if (!skb_is_gso(skb)) 4924 return 0; 4925 4926 err = skb_cow_head(skb, 0); 4927 if (err < 0) 4928 return err; 4929 4930 ip.hdr = skb_network_header(skb); 4931 l4.hdr = skb_checksum_start(skb); 4932 4933 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4934 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4935 4936 /* initialize outer IP header fields */ 4937 if (ip.v4->version == 4) { 4938 /* IP header will have to cancel out any data that 4939 * is not a part of the outer IP header 4940 */ 4941 ip.v4->check = csum_fold(csum_add(lco_csum(skb), 4942 csum_unfold(l4.tcp->check))); 4943 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4944 4945 ip.v4->tot_len = 0; 4946 first->tx_flags |= IGB_TX_FLAGS_TSO | 4947 IGB_TX_FLAGS_CSUM | 4948 IGB_TX_FLAGS_IPV4; 4949 } else { 4950 ip.v6->payload_len = 0; 4951 first->tx_flags |= IGB_TX_FLAGS_TSO | 4952 IGB_TX_FLAGS_CSUM; 4953 } 4954 4955 /* determine offset of inner transport header */ 4956 l4_offset = l4.hdr - skb->data; 4957 4958 /* compute length of segmentation header */ 4959 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 4960 4961 /* remove payload length from inner checksum */ 4962 paylen = skb->len - l4_offset; 4963 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 4964 4965 /* update gso size and bytecount with header size */ 4966 first->gso_segs = skb_shinfo(skb)->gso_segs; 4967 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4968 4969 /* MSS L4LEN IDX */ 4970 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 4971 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4972 4973 /* VLAN MACLEN IPLEN */ 4974 vlan_macip_lens = l4.hdr - ip.hdr; 4975 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 4976 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4977 4978 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4979 4980 return 1; 4981 } 4982 4983 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 4984 { 4985 unsigned int offset = 0; 4986 4987 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 4988 4989 return offset == skb_checksum_start_offset(skb); 4990 } 4991 4992 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4993 { 4994 struct sk_buff *skb = first->skb; 4995 u32 vlan_macip_lens = 0; 4996 u32 type_tucmd = 0; 4997 4998 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4999 csum_failed: 5000 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5001 return; 5002 goto no_csum; 5003 } 5004 5005 switch (skb->csum_offset) { 5006 case offsetof(struct tcphdr, check): 5007 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5008 /* fall through */ 5009 case offsetof(struct udphdr, check): 5010 break; 5011 case offsetof(struct sctphdr, checksum): 5012 /* validate that this is actually an SCTP request */ 5013 if (((first->protocol == htons(ETH_P_IP)) && 5014 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5015 ((first->protocol == htons(ETH_P_IPV6)) && 5016 igb_ipv6_csum_is_sctp(skb))) { 5017 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5018 break; 5019 } 5020 default: 5021 skb_checksum_help(skb); 5022 goto csum_failed; 5023 } 5024 5025 /* update TX checksum flag */ 5026 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5027 vlan_macip_lens = skb_checksum_start_offset(skb) - 5028 skb_network_offset(skb); 5029 no_csum: 5030 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5031 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5032 5033 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5034 } 5035 5036 #define IGB_SET_FLAG(_input, _flag, _result) \ 5037 ((_flag <= _result) ? \ 5038 ((u32)(_input & _flag) * (_result / _flag)) : \ 5039 ((u32)(_input & _flag) / (_flag / _result))) 5040 5041 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5042 { 5043 /* set type for advanced descriptor with frame checksum insertion */ 5044 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5045 E1000_ADVTXD_DCMD_DEXT | 5046 E1000_ADVTXD_DCMD_IFCS; 5047 5048 /* set HW vlan bit if vlan is present */ 5049 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5050 (E1000_ADVTXD_DCMD_VLE)); 5051 5052 /* set segmentation bits for TSO */ 5053 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5054 (E1000_ADVTXD_DCMD_TSE)); 5055 5056 /* set timestamp bit if present */ 5057 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5058 (E1000_ADVTXD_MAC_TSTAMP)); 5059 5060 /* insert frame checksum */ 5061 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5062 5063 return cmd_type; 5064 } 5065 5066 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5067 union e1000_adv_tx_desc *tx_desc, 5068 u32 tx_flags, unsigned int paylen) 5069 { 5070 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5071 5072 /* 82575 requires a unique index per ring */ 5073 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5074 olinfo_status |= tx_ring->reg_idx << 4; 5075 5076 /* insert L4 checksum */ 5077 olinfo_status |= IGB_SET_FLAG(tx_flags, 5078 IGB_TX_FLAGS_CSUM, 5079 (E1000_TXD_POPTS_TXSM << 8)); 5080 5081 /* insert IPv4 checksum */ 5082 olinfo_status |= IGB_SET_FLAG(tx_flags, 5083 IGB_TX_FLAGS_IPV4, 5084 (E1000_TXD_POPTS_IXSM << 8)); 5085 5086 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5087 } 5088 5089 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5090 { 5091 struct net_device *netdev = tx_ring->netdev; 5092 5093 netif_stop_subqueue(netdev, tx_ring->queue_index); 5094 5095 /* Herbert's original patch had: 5096 * smp_mb__after_netif_stop_queue(); 5097 * but since that doesn't exist yet, just open code it. 5098 */ 5099 smp_mb(); 5100 5101 /* We need to check again in a case another CPU has just 5102 * made room available. 5103 */ 5104 if (igb_desc_unused(tx_ring) < size) 5105 return -EBUSY; 5106 5107 /* A reprieve! */ 5108 netif_wake_subqueue(netdev, tx_ring->queue_index); 5109 5110 u64_stats_update_begin(&tx_ring->tx_syncp2); 5111 tx_ring->tx_stats.restart_queue2++; 5112 u64_stats_update_end(&tx_ring->tx_syncp2); 5113 5114 return 0; 5115 } 5116 5117 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5118 { 5119 if (igb_desc_unused(tx_ring) >= size) 5120 return 0; 5121 return __igb_maybe_stop_tx(tx_ring, size); 5122 } 5123 5124 static void igb_tx_map(struct igb_ring *tx_ring, 5125 struct igb_tx_buffer *first, 5126 const u8 hdr_len) 5127 { 5128 struct sk_buff *skb = first->skb; 5129 struct igb_tx_buffer *tx_buffer; 5130 union e1000_adv_tx_desc *tx_desc; 5131 struct skb_frag_struct *frag; 5132 dma_addr_t dma; 5133 unsigned int data_len, size; 5134 u32 tx_flags = first->tx_flags; 5135 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5136 u16 i = tx_ring->next_to_use; 5137 5138 tx_desc = IGB_TX_DESC(tx_ring, i); 5139 5140 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5141 5142 size = skb_headlen(skb); 5143 data_len = skb->data_len; 5144 5145 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5146 5147 tx_buffer = first; 5148 5149 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5150 if (dma_mapping_error(tx_ring->dev, dma)) 5151 goto dma_error; 5152 5153 /* record length, and DMA address */ 5154 dma_unmap_len_set(tx_buffer, len, size); 5155 dma_unmap_addr_set(tx_buffer, dma, dma); 5156 5157 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5158 5159 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5160 tx_desc->read.cmd_type_len = 5161 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5162 5163 i++; 5164 tx_desc++; 5165 if (i == tx_ring->count) { 5166 tx_desc = IGB_TX_DESC(tx_ring, 0); 5167 i = 0; 5168 } 5169 tx_desc->read.olinfo_status = 0; 5170 5171 dma += IGB_MAX_DATA_PER_TXD; 5172 size -= IGB_MAX_DATA_PER_TXD; 5173 5174 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5175 } 5176 5177 if (likely(!data_len)) 5178 break; 5179 5180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5181 5182 i++; 5183 tx_desc++; 5184 if (i == tx_ring->count) { 5185 tx_desc = IGB_TX_DESC(tx_ring, 0); 5186 i = 0; 5187 } 5188 tx_desc->read.olinfo_status = 0; 5189 5190 size = skb_frag_size(frag); 5191 data_len -= size; 5192 5193 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5194 size, DMA_TO_DEVICE); 5195 5196 tx_buffer = &tx_ring->tx_buffer_info[i]; 5197 } 5198 5199 /* write last descriptor with RS and EOP bits */ 5200 cmd_type |= size | IGB_TXD_DCMD; 5201 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5202 5203 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5204 5205 /* set the timestamp */ 5206 first->time_stamp = jiffies; 5207 5208 /* Force memory writes to complete before letting h/w know there 5209 * are new descriptors to fetch. (Only applicable for weak-ordered 5210 * memory model archs, such as IA-64). 5211 * 5212 * We also need this memory barrier to make certain all of the 5213 * status bits have been updated before next_to_watch is written. 5214 */ 5215 wmb(); 5216 5217 /* set next_to_watch value indicating a packet is present */ 5218 first->next_to_watch = tx_desc; 5219 5220 i++; 5221 if (i == tx_ring->count) 5222 i = 0; 5223 5224 tx_ring->next_to_use = i; 5225 5226 /* Make sure there is space in the ring for the next send. */ 5227 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5228 5229 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5230 writel(i, tx_ring->tail); 5231 5232 /* we need this if more than one processor can write to our tail 5233 * at a time, it synchronizes IO on IA64/Altix systems 5234 */ 5235 mmiowb(); 5236 } 5237 return; 5238 5239 dma_error: 5240 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5241 5242 /* clear dma mappings for failed tx_buffer_info map */ 5243 for (;;) { 5244 tx_buffer = &tx_ring->tx_buffer_info[i]; 5245 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 5246 if (tx_buffer == first) 5247 break; 5248 if (i == 0) 5249 i = tx_ring->count; 5250 i--; 5251 } 5252 5253 tx_ring->next_to_use = i; 5254 } 5255 5256 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5257 struct igb_ring *tx_ring) 5258 { 5259 struct igb_tx_buffer *first; 5260 int tso; 5261 u32 tx_flags = 0; 5262 unsigned short f; 5263 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5264 __be16 protocol = vlan_get_protocol(skb); 5265 u8 hdr_len = 0; 5266 5267 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5268 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5269 * + 2 desc gap to keep tail from touching head, 5270 * + 1 desc for context descriptor, 5271 * otherwise try next time 5272 */ 5273 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5274 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5275 5276 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5277 /* this is a hard error */ 5278 return NETDEV_TX_BUSY; 5279 } 5280 5281 /* record the location of the first descriptor for this packet */ 5282 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5283 first->skb = skb; 5284 first->bytecount = skb->len; 5285 first->gso_segs = 1; 5286 5287 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5288 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5289 5290 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5291 &adapter->state)) { 5292 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5293 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5294 5295 adapter->ptp_tx_skb = skb_get(skb); 5296 adapter->ptp_tx_start = jiffies; 5297 if (adapter->hw.mac.type == e1000_82576) 5298 schedule_work(&adapter->ptp_tx_work); 5299 } 5300 } 5301 5302 skb_tx_timestamp(skb); 5303 5304 if (skb_vlan_tag_present(skb)) { 5305 tx_flags |= IGB_TX_FLAGS_VLAN; 5306 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5307 } 5308 5309 /* record initial flags and protocol */ 5310 first->tx_flags = tx_flags; 5311 first->protocol = protocol; 5312 5313 tso = igb_tso(tx_ring, first, &hdr_len); 5314 if (tso < 0) 5315 goto out_drop; 5316 else if (!tso) 5317 igb_tx_csum(tx_ring, first); 5318 5319 igb_tx_map(tx_ring, first, hdr_len); 5320 5321 return NETDEV_TX_OK; 5322 5323 out_drop: 5324 igb_unmap_and_free_tx_resource(tx_ring, first); 5325 5326 return NETDEV_TX_OK; 5327 } 5328 5329 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5330 struct sk_buff *skb) 5331 { 5332 unsigned int r_idx = skb->queue_mapping; 5333 5334 if (r_idx >= adapter->num_tx_queues) 5335 r_idx = r_idx % adapter->num_tx_queues; 5336 5337 return adapter->tx_ring[r_idx]; 5338 } 5339 5340 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5341 struct net_device *netdev) 5342 { 5343 struct igb_adapter *adapter = netdev_priv(netdev); 5344 5345 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5346 * in order to meet this minimum size requirement. 5347 */ 5348 if (skb_put_padto(skb, 17)) 5349 return NETDEV_TX_OK; 5350 5351 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5352 } 5353 5354 /** 5355 * igb_tx_timeout - Respond to a Tx Hang 5356 * @netdev: network interface device structure 5357 **/ 5358 static void igb_tx_timeout(struct net_device *netdev) 5359 { 5360 struct igb_adapter *adapter = netdev_priv(netdev); 5361 struct e1000_hw *hw = &adapter->hw; 5362 5363 /* Do the reset outside of interrupt context */ 5364 adapter->tx_timeout_count++; 5365 5366 if (hw->mac.type >= e1000_82580) 5367 hw->dev_spec._82575.global_device_reset = true; 5368 5369 schedule_work(&adapter->reset_task); 5370 wr32(E1000_EICS, 5371 (adapter->eims_enable_mask & ~adapter->eims_other)); 5372 } 5373 5374 static void igb_reset_task(struct work_struct *work) 5375 { 5376 struct igb_adapter *adapter; 5377 adapter = container_of(work, struct igb_adapter, reset_task); 5378 5379 igb_dump(adapter); 5380 netdev_err(adapter->netdev, "Reset adapter\n"); 5381 igb_reinit_locked(adapter); 5382 } 5383 5384 /** 5385 * igb_get_stats64 - Get System Network Statistics 5386 * @netdev: network interface device structure 5387 * @stats: rtnl_link_stats64 pointer 5388 **/ 5389 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5390 struct rtnl_link_stats64 *stats) 5391 { 5392 struct igb_adapter *adapter = netdev_priv(netdev); 5393 5394 spin_lock(&adapter->stats64_lock); 5395 igb_update_stats(adapter, &adapter->stats64); 5396 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5397 spin_unlock(&adapter->stats64_lock); 5398 5399 return stats; 5400 } 5401 5402 /** 5403 * igb_change_mtu - Change the Maximum Transfer Unit 5404 * @netdev: network interface device structure 5405 * @new_mtu: new value for maximum frame size 5406 * 5407 * Returns 0 on success, negative on failure 5408 **/ 5409 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5410 { 5411 struct igb_adapter *adapter = netdev_priv(netdev); 5412 struct pci_dev *pdev = adapter->pdev; 5413 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5414 5415 /* adjust max frame to be at least the size of a standard frame */ 5416 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5417 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5418 5419 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5420 usleep_range(1000, 2000); 5421 5422 /* igb_down has a dependency on max_frame_size */ 5423 adapter->max_frame_size = max_frame; 5424 5425 if (netif_running(netdev)) 5426 igb_down(adapter); 5427 5428 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5429 netdev->mtu, new_mtu); 5430 netdev->mtu = new_mtu; 5431 5432 if (netif_running(netdev)) 5433 igb_up(adapter); 5434 else 5435 igb_reset(adapter); 5436 5437 clear_bit(__IGB_RESETTING, &adapter->state); 5438 5439 return 0; 5440 } 5441 5442 /** 5443 * igb_update_stats - Update the board statistics counters 5444 * @adapter: board private structure 5445 **/ 5446 void igb_update_stats(struct igb_adapter *adapter, 5447 struct rtnl_link_stats64 *net_stats) 5448 { 5449 struct e1000_hw *hw = &adapter->hw; 5450 struct pci_dev *pdev = adapter->pdev; 5451 u32 reg, mpc; 5452 int i; 5453 u64 bytes, packets; 5454 unsigned int start; 5455 u64 _bytes, _packets; 5456 5457 /* Prevent stats update while adapter is being reset, or if the pci 5458 * connection is down. 5459 */ 5460 if (adapter->link_speed == 0) 5461 return; 5462 if (pci_channel_offline(pdev)) 5463 return; 5464 5465 bytes = 0; 5466 packets = 0; 5467 5468 rcu_read_lock(); 5469 for (i = 0; i < adapter->num_rx_queues; i++) { 5470 struct igb_ring *ring = adapter->rx_ring[i]; 5471 u32 rqdpc = rd32(E1000_RQDPC(i)); 5472 if (hw->mac.type >= e1000_i210) 5473 wr32(E1000_RQDPC(i), 0); 5474 5475 if (rqdpc) { 5476 ring->rx_stats.drops += rqdpc; 5477 net_stats->rx_fifo_errors += rqdpc; 5478 } 5479 5480 do { 5481 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5482 _bytes = ring->rx_stats.bytes; 5483 _packets = ring->rx_stats.packets; 5484 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5485 bytes += _bytes; 5486 packets += _packets; 5487 } 5488 5489 net_stats->rx_bytes = bytes; 5490 net_stats->rx_packets = packets; 5491 5492 bytes = 0; 5493 packets = 0; 5494 for (i = 0; i < adapter->num_tx_queues; i++) { 5495 struct igb_ring *ring = adapter->tx_ring[i]; 5496 do { 5497 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5498 _bytes = ring->tx_stats.bytes; 5499 _packets = ring->tx_stats.packets; 5500 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5501 bytes += _bytes; 5502 packets += _packets; 5503 } 5504 net_stats->tx_bytes = bytes; 5505 net_stats->tx_packets = packets; 5506 rcu_read_unlock(); 5507 5508 /* read stats registers */ 5509 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5510 adapter->stats.gprc += rd32(E1000_GPRC); 5511 adapter->stats.gorc += rd32(E1000_GORCL); 5512 rd32(E1000_GORCH); /* clear GORCL */ 5513 adapter->stats.bprc += rd32(E1000_BPRC); 5514 adapter->stats.mprc += rd32(E1000_MPRC); 5515 adapter->stats.roc += rd32(E1000_ROC); 5516 5517 adapter->stats.prc64 += rd32(E1000_PRC64); 5518 adapter->stats.prc127 += rd32(E1000_PRC127); 5519 adapter->stats.prc255 += rd32(E1000_PRC255); 5520 adapter->stats.prc511 += rd32(E1000_PRC511); 5521 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5522 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5523 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5524 adapter->stats.sec += rd32(E1000_SEC); 5525 5526 mpc = rd32(E1000_MPC); 5527 adapter->stats.mpc += mpc; 5528 net_stats->rx_fifo_errors += mpc; 5529 adapter->stats.scc += rd32(E1000_SCC); 5530 adapter->stats.ecol += rd32(E1000_ECOL); 5531 adapter->stats.mcc += rd32(E1000_MCC); 5532 adapter->stats.latecol += rd32(E1000_LATECOL); 5533 adapter->stats.dc += rd32(E1000_DC); 5534 adapter->stats.rlec += rd32(E1000_RLEC); 5535 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5536 adapter->stats.xontxc += rd32(E1000_XONTXC); 5537 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5538 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5539 adapter->stats.fcruc += rd32(E1000_FCRUC); 5540 adapter->stats.gptc += rd32(E1000_GPTC); 5541 adapter->stats.gotc += rd32(E1000_GOTCL); 5542 rd32(E1000_GOTCH); /* clear GOTCL */ 5543 adapter->stats.rnbc += rd32(E1000_RNBC); 5544 adapter->stats.ruc += rd32(E1000_RUC); 5545 adapter->stats.rfc += rd32(E1000_RFC); 5546 adapter->stats.rjc += rd32(E1000_RJC); 5547 adapter->stats.tor += rd32(E1000_TORH); 5548 adapter->stats.tot += rd32(E1000_TOTH); 5549 adapter->stats.tpr += rd32(E1000_TPR); 5550 5551 adapter->stats.ptc64 += rd32(E1000_PTC64); 5552 adapter->stats.ptc127 += rd32(E1000_PTC127); 5553 adapter->stats.ptc255 += rd32(E1000_PTC255); 5554 adapter->stats.ptc511 += rd32(E1000_PTC511); 5555 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5556 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5557 5558 adapter->stats.mptc += rd32(E1000_MPTC); 5559 adapter->stats.bptc += rd32(E1000_BPTC); 5560 5561 adapter->stats.tpt += rd32(E1000_TPT); 5562 adapter->stats.colc += rd32(E1000_COLC); 5563 5564 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5565 /* read internal phy specific stats */ 5566 reg = rd32(E1000_CTRL_EXT); 5567 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5568 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5569 5570 /* this stat has invalid values on i210/i211 */ 5571 if ((hw->mac.type != e1000_i210) && 5572 (hw->mac.type != e1000_i211)) 5573 adapter->stats.tncrs += rd32(E1000_TNCRS); 5574 } 5575 5576 adapter->stats.tsctc += rd32(E1000_TSCTC); 5577 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5578 5579 adapter->stats.iac += rd32(E1000_IAC); 5580 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5581 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5582 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5583 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5584 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5585 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5586 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5587 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5588 5589 /* Fill out the OS statistics structure */ 5590 net_stats->multicast = adapter->stats.mprc; 5591 net_stats->collisions = adapter->stats.colc; 5592 5593 /* Rx Errors */ 5594 5595 /* RLEC on some newer hardware can be incorrect so build 5596 * our own version based on RUC and ROC 5597 */ 5598 net_stats->rx_errors = adapter->stats.rxerrc + 5599 adapter->stats.crcerrs + adapter->stats.algnerrc + 5600 adapter->stats.ruc + adapter->stats.roc + 5601 adapter->stats.cexterr; 5602 net_stats->rx_length_errors = adapter->stats.ruc + 5603 adapter->stats.roc; 5604 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5605 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5606 net_stats->rx_missed_errors = adapter->stats.mpc; 5607 5608 /* Tx Errors */ 5609 net_stats->tx_errors = adapter->stats.ecol + 5610 adapter->stats.latecol; 5611 net_stats->tx_aborted_errors = adapter->stats.ecol; 5612 net_stats->tx_window_errors = adapter->stats.latecol; 5613 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5614 5615 /* Tx Dropped needs to be maintained elsewhere */ 5616 5617 /* Management Stats */ 5618 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5619 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5620 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5621 5622 /* OS2BMC Stats */ 5623 reg = rd32(E1000_MANC); 5624 if (reg & E1000_MANC_EN_BMC2OS) { 5625 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5626 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5627 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5628 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5629 } 5630 } 5631 5632 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5633 { 5634 struct e1000_hw *hw = &adapter->hw; 5635 struct ptp_clock_event event; 5636 struct timespec64 ts; 5637 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5638 5639 if (tsicr & TSINTR_SYS_WRAP) { 5640 event.type = PTP_CLOCK_PPS; 5641 if (adapter->ptp_caps.pps) 5642 ptp_clock_event(adapter->ptp_clock, &event); 5643 else 5644 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5645 ack |= TSINTR_SYS_WRAP; 5646 } 5647 5648 if (tsicr & E1000_TSICR_TXTS) { 5649 /* retrieve hardware timestamp */ 5650 schedule_work(&adapter->ptp_tx_work); 5651 ack |= E1000_TSICR_TXTS; 5652 } 5653 5654 if (tsicr & TSINTR_TT0) { 5655 spin_lock(&adapter->tmreg_lock); 5656 ts = timespec64_add(adapter->perout[0].start, 5657 adapter->perout[0].period); 5658 /* u32 conversion of tv_sec is safe until y2106 */ 5659 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5660 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5661 tsauxc = rd32(E1000_TSAUXC); 5662 tsauxc |= TSAUXC_EN_TT0; 5663 wr32(E1000_TSAUXC, tsauxc); 5664 adapter->perout[0].start = ts; 5665 spin_unlock(&adapter->tmreg_lock); 5666 ack |= TSINTR_TT0; 5667 } 5668 5669 if (tsicr & TSINTR_TT1) { 5670 spin_lock(&adapter->tmreg_lock); 5671 ts = timespec64_add(adapter->perout[1].start, 5672 adapter->perout[1].period); 5673 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5674 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5675 tsauxc = rd32(E1000_TSAUXC); 5676 tsauxc |= TSAUXC_EN_TT1; 5677 wr32(E1000_TSAUXC, tsauxc); 5678 adapter->perout[1].start = ts; 5679 spin_unlock(&adapter->tmreg_lock); 5680 ack |= TSINTR_TT1; 5681 } 5682 5683 if (tsicr & TSINTR_AUTT0) { 5684 nsec = rd32(E1000_AUXSTMPL0); 5685 sec = rd32(E1000_AUXSTMPH0); 5686 event.type = PTP_CLOCK_EXTTS; 5687 event.index = 0; 5688 event.timestamp = sec * 1000000000ULL + nsec; 5689 ptp_clock_event(adapter->ptp_clock, &event); 5690 ack |= TSINTR_AUTT0; 5691 } 5692 5693 if (tsicr & TSINTR_AUTT1) { 5694 nsec = rd32(E1000_AUXSTMPL1); 5695 sec = rd32(E1000_AUXSTMPH1); 5696 event.type = PTP_CLOCK_EXTTS; 5697 event.index = 1; 5698 event.timestamp = sec * 1000000000ULL + nsec; 5699 ptp_clock_event(adapter->ptp_clock, &event); 5700 ack |= TSINTR_AUTT1; 5701 } 5702 5703 /* acknowledge the interrupts */ 5704 wr32(E1000_TSICR, ack); 5705 } 5706 5707 static irqreturn_t igb_msix_other(int irq, void *data) 5708 { 5709 struct igb_adapter *adapter = data; 5710 struct e1000_hw *hw = &adapter->hw; 5711 u32 icr = rd32(E1000_ICR); 5712 /* reading ICR causes bit 31 of EICR to be cleared */ 5713 5714 if (icr & E1000_ICR_DRSTA) 5715 schedule_work(&adapter->reset_task); 5716 5717 if (icr & E1000_ICR_DOUTSYNC) { 5718 /* HW is reporting DMA is out of sync */ 5719 adapter->stats.doosync++; 5720 /* The DMA Out of Sync is also indication of a spoof event 5721 * in IOV mode. Check the Wrong VM Behavior register to 5722 * see if it is really a spoof event. 5723 */ 5724 igb_check_wvbr(adapter); 5725 } 5726 5727 /* Check for a mailbox event */ 5728 if (icr & E1000_ICR_VMMB) 5729 igb_msg_task(adapter); 5730 5731 if (icr & E1000_ICR_LSC) { 5732 hw->mac.get_link_status = 1; 5733 /* guard against interrupt when we're going down */ 5734 if (!test_bit(__IGB_DOWN, &adapter->state)) 5735 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5736 } 5737 5738 if (icr & E1000_ICR_TS) 5739 igb_tsync_interrupt(adapter); 5740 5741 wr32(E1000_EIMS, adapter->eims_other); 5742 5743 return IRQ_HANDLED; 5744 } 5745 5746 static void igb_write_itr(struct igb_q_vector *q_vector) 5747 { 5748 struct igb_adapter *adapter = q_vector->adapter; 5749 u32 itr_val = q_vector->itr_val & 0x7FFC; 5750 5751 if (!q_vector->set_itr) 5752 return; 5753 5754 if (!itr_val) 5755 itr_val = 0x4; 5756 5757 if (adapter->hw.mac.type == e1000_82575) 5758 itr_val |= itr_val << 16; 5759 else 5760 itr_val |= E1000_EITR_CNT_IGNR; 5761 5762 writel(itr_val, q_vector->itr_register); 5763 q_vector->set_itr = 0; 5764 } 5765 5766 static irqreturn_t igb_msix_ring(int irq, void *data) 5767 { 5768 struct igb_q_vector *q_vector = data; 5769 5770 /* Write the ITR value calculated from the previous interrupt. */ 5771 igb_write_itr(q_vector); 5772 5773 napi_schedule(&q_vector->napi); 5774 5775 return IRQ_HANDLED; 5776 } 5777 5778 #ifdef CONFIG_IGB_DCA 5779 static void igb_update_tx_dca(struct igb_adapter *adapter, 5780 struct igb_ring *tx_ring, 5781 int cpu) 5782 { 5783 struct e1000_hw *hw = &adapter->hw; 5784 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5785 5786 if (hw->mac.type != e1000_82575) 5787 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5788 5789 /* We can enable relaxed ordering for reads, but not writes when 5790 * DCA is enabled. This is due to a known issue in some chipsets 5791 * which will cause the DCA tag to be cleared. 5792 */ 5793 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5794 E1000_DCA_TXCTRL_DATA_RRO_EN | 5795 E1000_DCA_TXCTRL_DESC_DCA_EN; 5796 5797 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5798 } 5799 5800 static void igb_update_rx_dca(struct igb_adapter *adapter, 5801 struct igb_ring *rx_ring, 5802 int cpu) 5803 { 5804 struct e1000_hw *hw = &adapter->hw; 5805 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5806 5807 if (hw->mac.type != e1000_82575) 5808 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5809 5810 /* We can enable relaxed ordering for reads, but not writes when 5811 * DCA is enabled. This is due to a known issue in some chipsets 5812 * which will cause the DCA tag to be cleared. 5813 */ 5814 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5815 E1000_DCA_RXCTRL_DESC_DCA_EN; 5816 5817 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5818 } 5819 5820 static void igb_update_dca(struct igb_q_vector *q_vector) 5821 { 5822 struct igb_adapter *adapter = q_vector->adapter; 5823 int cpu = get_cpu(); 5824 5825 if (q_vector->cpu == cpu) 5826 goto out_no_update; 5827 5828 if (q_vector->tx.ring) 5829 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5830 5831 if (q_vector->rx.ring) 5832 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5833 5834 q_vector->cpu = cpu; 5835 out_no_update: 5836 put_cpu(); 5837 } 5838 5839 static void igb_setup_dca(struct igb_adapter *adapter) 5840 { 5841 struct e1000_hw *hw = &adapter->hw; 5842 int i; 5843 5844 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5845 return; 5846 5847 /* Always use CB2 mode, difference is masked in the CB driver. */ 5848 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5849 5850 for (i = 0; i < adapter->num_q_vectors; i++) { 5851 adapter->q_vector[i]->cpu = -1; 5852 igb_update_dca(adapter->q_vector[i]); 5853 } 5854 } 5855 5856 static int __igb_notify_dca(struct device *dev, void *data) 5857 { 5858 struct net_device *netdev = dev_get_drvdata(dev); 5859 struct igb_adapter *adapter = netdev_priv(netdev); 5860 struct pci_dev *pdev = adapter->pdev; 5861 struct e1000_hw *hw = &adapter->hw; 5862 unsigned long event = *(unsigned long *)data; 5863 5864 switch (event) { 5865 case DCA_PROVIDER_ADD: 5866 /* if already enabled, don't do it again */ 5867 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5868 break; 5869 if (dca_add_requester(dev) == 0) { 5870 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5871 dev_info(&pdev->dev, "DCA enabled\n"); 5872 igb_setup_dca(adapter); 5873 break; 5874 } 5875 /* Fall Through since DCA is disabled. */ 5876 case DCA_PROVIDER_REMOVE: 5877 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5878 /* without this a class_device is left 5879 * hanging around in the sysfs model 5880 */ 5881 dca_remove_requester(dev); 5882 dev_info(&pdev->dev, "DCA disabled\n"); 5883 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5884 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5885 } 5886 break; 5887 } 5888 5889 return 0; 5890 } 5891 5892 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5893 void *p) 5894 { 5895 int ret_val; 5896 5897 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5898 __igb_notify_dca); 5899 5900 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5901 } 5902 #endif /* CONFIG_IGB_DCA */ 5903 5904 #ifdef CONFIG_PCI_IOV 5905 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5906 { 5907 unsigned char mac_addr[ETH_ALEN]; 5908 5909 eth_zero_addr(mac_addr); 5910 igb_set_vf_mac(adapter, vf, mac_addr); 5911 5912 /* By default spoof check is enabled for all VFs */ 5913 adapter->vf_data[vf].spoofchk_enabled = true; 5914 5915 return 0; 5916 } 5917 5918 #endif 5919 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5920 { 5921 struct e1000_hw *hw = &adapter->hw; 5922 u32 ping; 5923 int i; 5924 5925 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5926 ping = E1000_PF_CONTROL_MSG; 5927 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5928 ping |= E1000_VT_MSGTYPE_CTS; 5929 igb_write_mbx(hw, &ping, 1, i); 5930 } 5931 } 5932 5933 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5934 { 5935 struct e1000_hw *hw = &adapter->hw; 5936 u32 vmolr = rd32(E1000_VMOLR(vf)); 5937 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5938 5939 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5940 IGB_VF_FLAG_MULTI_PROMISC); 5941 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5942 5943 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5944 vmolr |= E1000_VMOLR_MPME; 5945 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5946 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5947 } else { 5948 /* if we have hashes and we are clearing a multicast promisc 5949 * flag we need to write the hashes to the MTA as this step 5950 * was previously skipped 5951 */ 5952 if (vf_data->num_vf_mc_hashes > 30) { 5953 vmolr |= E1000_VMOLR_MPME; 5954 } else if (vf_data->num_vf_mc_hashes) { 5955 int j; 5956 5957 vmolr |= E1000_VMOLR_ROMPE; 5958 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5959 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5960 } 5961 } 5962 5963 wr32(E1000_VMOLR(vf), vmolr); 5964 5965 /* there are flags left unprocessed, likely not supported */ 5966 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5967 return -EINVAL; 5968 5969 return 0; 5970 } 5971 5972 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5973 u32 *msgbuf, u32 vf) 5974 { 5975 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5976 u16 *hash_list = (u16 *)&msgbuf[1]; 5977 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5978 int i; 5979 5980 /* salt away the number of multicast addresses assigned 5981 * to this VF for later use to restore when the PF multi cast 5982 * list changes 5983 */ 5984 vf_data->num_vf_mc_hashes = n; 5985 5986 /* only up to 30 hash values supported */ 5987 if (n > 30) 5988 n = 30; 5989 5990 /* store the hashes for later use */ 5991 for (i = 0; i < n; i++) 5992 vf_data->vf_mc_hashes[i] = hash_list[i]; 5993 5994 /* Flush and reset the mta with the new values */ 5995 igb_set_rx_mode(adapter->netdev); 5996 5997 return 0; 5998 } 5999 6000 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6001 { 6002 struct e1000_hw *hw = &adapter->hw; 6003 struct vf_data_storage *vf_data; 6004 int i, j; 6005 6006 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6007 u32 vmolr = rd32(E1000_VMOLR(i)); 6008 6009 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6010 6011 vf_data = &adapter->vf_data[i]; 6012 6013 if ((vf_data->num_vf_mc_hashes > 30) || 6014 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6015 vmolr |= E1000_VMOLR_MPME; 6016 } else if (vf_data->num_vf_mc_hashes) { 6017 vmolr |= E1000_VMOLR_ROMPE; 6018 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6019 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6020 } 6021 wr32(E1000_VMOLR(i), vmolr); 6022 } 6023 } 6024 6025 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6026 { 6027 struct e1000_hw *hw = &adapter->hw; 6028 u32 pool_mask, vlvf_mask, i; 6029 6030 /* create mask for VF and other pools */ 6031 pool_mask = E1000_VLVF_POOLSEL_MASK; 6032 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6033 6034 /* drop PF from pool bits */ 6035 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6036 adapter->vfs_allocated_count); 6037 6038 /* Find the vlan filter for this id */ 6039 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6040 u32 vlvf = rd32(E1000_VLVF(i)); 6041 u32 vfta_mask, vid, vfta; 6042 6043 /* remove the vf from the pool */ 6044 if (!(vlvf & vlvf_mask)) 6045 continue; 6046 6047 /* clear out bit from VLVF */ 6048 vlvf ^= vlvf_mask; 6049 6050 /* if other pools are present, just remove ourselves */ 6051 if (vlvf & pool_mask) 6052 goto update_vlvfb; 6053 6054 /* if PF is present, leave VFTA */ 6055 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6056 goto update_vlvf; 6057 6058 vid = vlvf & E1000_VLVF_VLANID_MASK; 6059 vfta_mask = BIT(vid % 32); 6060 6061 /* clear bit from VFTA */ 6062 vfta = adapter->shadow_vfta[vid / 32]; 6063 if (vfta & vfta_mask) 6064 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6065 update_vlvf: 6066 /* clear pool selection enable */ 6067 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6068 vlvf &= E1000_VLVF_POOLSEL_MASK; 6069 else 6070 vlvf = 0; 6071 update_vlvfb: 6072 /* clear pool bits */ 6073 wr32(E1000_VLVF(i), vlvf); 6074 } 6075 } 6076 6077 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6078 { 6079 u32 vlvf; 6080 int idx; 6081 6082 /* short cut the special case */ 6083 if (vlan == 0) 6084 return 0; 6085 6086 /* Search for the VLAN id in the VLVF entries */ 6087 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6088 vlvf = rd32(E1000_VLVF(idx)); 6089 if ((vlvf & VLAN_VID_MASK) == vlan) 6090 break; 6091 } 6092 6093 return idx; 6094 } 6095 6096 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6097 { 6098 struct e1000_hw *hw = &adapter->hw; 6099 u32 bits, pf_id; 6100 int idx; 6101 6102 idx = igb_find_vlvf_entry(hw, vid); 6103 if (!idx) 6104 return; 6105 6106 /* See if any other pools are set for this VLAN filter 6107 * entry other than the PF. 6108 */ 6109 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6110 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6111 bits &= rd32(E1000_VLVF(idx)); 6112 6113 /* Disable the filter so this falls into the default pool. */ 6114 if (!bits) { 6115 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6116 wr32(E1000_VLVF(idx), BIT(pf_id)); 6117 else 6118 wr32(E1000_VLVF(idx), 0); 6119 } 6120 } 6121 6122 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6123 bool add, u32 vf) 6124 { 6125 int pf_id = adapter->vfs_allocated_count; 6126 struct e1000_hw *hw = &adapter->hw; 6127 int err; 6128 6129 /* If VLAN overlaps with one the PF is currently monitoring make 6130 * sure that we are able to allocate a VLVF entry. This may be 6131 * redundant but it guarantees PF will maintain visibility to 6132 * the VLAN. 6133 */ 6134 if (add && test_bit(vid, adapter->active_vlans)) { 6135 err = igb_vfta_set(hw, vid, pf_id, true, false); 6136 if (err) 6137 return err; 6138 } 6139 6140 err = igb_vfta_set(hw, vid, vf, add, false); 6141 6142 if (add && !err) 6143 return err; 6144 6145 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6146 * we may need to drop the PF pool bit in order to allow us to free 6147 * up the VLVF resources. 6148 */ 6149 if (test_bit(vid, adapter->active_vlans) || 6150 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6151 igb_update_pf_vlvf(adapter, vid); 6152 6153 return err; 6154 } 6155 6156 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6157 { 6158 struct e1000_hw *hw = &adapter->hw; 6159 6160 if (vid) 6161 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6162 else 6163 wr32(E1000_VMVIR(vf), 0); 6164 } 6165 6166 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6167 u16 vlan, u8 qos) 6168 { 6169 int err; 6170 6171 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6172 if (err) 6173 return err; 6174 6175 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6176 igb_set_vmolr(adapter, vf, !vlan); 6177 6178 /* revoke access to previous VLAN */ 6179 if (vlan != adapter->vf_data[vf].pf_vlan) 6180 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6181 false, vf); 6182 6183 adapter->vf_data[vf].pf_vlan = vlan; 6184 adapter->vf_data[vf].pf_qos = qos; 6185 igb_set_vf_vlan_strip(adapter, vf, true); 6186 dev_info(&adapter->pdev->dev, 6187 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6188 if (test_bit(__IGB_DOWN, &adapter->state)) { 6189 dev_warn(&adapter->pdev->dev, 6190 "The VF VLAN has been set, but the PF device is not up.\n"); 6191 dev_warn(&adapter->pdev->dev, 6192 "Bring the PF device up before attempting to use the VF device.\n"); 6193 } 6194 6195 return err; 6196 } 6197 6198 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6199 { 6200 /* Restore tagless access via VLAN 0 */ 6201 igb_set_vf_vlan(adapter, 0, true, vf); 6202 6203 igb_set_vmvir(adapter, 0, vf); 6204 igb_set_vmolr(adapter, vf, true); 6205 6206 /* Remove any PF assigned VLAN */ 6207 if (adapter->vf_data[vf].pf_vlan) 6208 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6209 false, vf); 6210 6211 adapter->vf_data[vf].pf_vlan = 0; 6212 adapter->vf_data[vf].pf_qos = 0; 6213 igb_set_vf_vlan_strip(adapter, vf, false); 6214 6215 return 0; 6216 } 6217 6218 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6219 u16 vlan, u8 qos, __be16 vlan_proto) 6220 { 6221 struct igb_adapter *adapter = netdev_priv(netdev); 6222 6223 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6224 return -EINVAL; 6225 6226 if (vlan_proto != htons(ETH_P_8021Q)) 6227 return -EPROTONOSUPPORT; 6228 6229 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6230 igb_disable_port_vlan(adapter, vf); 6231 } 6232 6233 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6234 { 6235 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6236 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6237 int ret; 6238 6239 if (adapter->vf_data[vf].pf_vlan) 6240 return -1; 6241 6242 /* VLAN 0 is a special case, don't allow it to be removed */ 6243 if (!vid && !add) 6244 return 0; 6245 6246 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6247 if (!ret) 6248 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6249 return ret; 6250 } 6251 6252 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6253 { 6254 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6255 6256 /* clear flags - except flag that indicates PF has set the MAC */ 6257 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6258 vf_data->last_nack = jiffies; 6259 6260 /* reset vlans for device */ 6261 igb_clear_vf_vfta(adapter, vf); 6262 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6263 igb_set_vmvir(adapter, vf_data->pf_vlan | 6264 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6265 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6266 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6267 6268 /* reset multicast table array for vf */ 6269 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6270 6271 /* Flush and reset the mta with the new values */ 6272 igb_set_rx_mode(adapter->netdev); 6273 } 6274 6275 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6276 { 6277 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6278 6279 /* clear mac address as we were hotplug removed/added */ 6280 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6281 eth_zero_addr(vf_mac); 6282 6283 /* process remaining reset events */ 6284 igb_vf_reset(adapter, vf); 6285 } 6286 6287 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6288 { 6289 struct e1000_hw *hw = &adapter->hw; 6290 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6291 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6292 u32 reg, msgbuf[3]; 6293 u8 *addr = (u8 *)(&msgbuf[1]); 6294 6295 /* process all the same items cleared in a function level reset */ 6296 igb_vf_reset(adapter, vf); 6297 6298 /* set vf mac address */ 6299 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6300 6301 /* enable transmit and receive for vf */ 6302 reg = rd32(E1000_VFTE); 6303 wr32(E1000_VFTE, reg | BIT(vf)); 6304 reg = rd32(E1000_VFRE); 6305 wr32(E1000_VFRE, reg | BIT(vf)); 6306 6307 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6308 6309 /* reply to reset with ack and vf mac address */ 6310 if (!is_zero_ether_addr(vf_mac)) { 6311 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6312 memcpy(addr, vf_mac, ETH_ALEN); 6313 } else { 6314 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6315 } 6316 igb_write_mbx(hw, msgbuf, 3, vf); 6317 } 6318 6319 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6320 { 6321 /* The VF MAC Address is stored in a packed array of bytes 6322 * starting at the second 32 bit word of the msg array 6323 */ 6324 unsigned char *addr = (char *)&msg[1]; 6325 int err = -1; 6326 6327 if (is_valid_ether_addr(addr)) 6328 err = igb_set_vf_mac(adapter, vf, addr); 6329 6330 return err; 6331 } 6332 6333 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6334 { 6335 struct e1000_hw *hw = &adapter->hw; 6336 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6337 u32 msg = E1000_VT_MSGTYPE_NACK; 6338 6339 /* if device isn't clear to send it shouldn't be reading either */ 6340 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6341 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6342 igb_write_mbx(hw, &msg, 1, vf); 6343 vf_data->last_nack = jiffies; 6344 } 6345 } 6346 6347 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6348 { 6349 struct pci_dev *pdev = adapter->pdev; 6350 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6351 struct e1000_hw *hw = &adapter->hw; 6352 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6353 s32 retval; 6354 6355 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6356 6357 if (retval) { 6358 /* if receive failed revoke VF CTS stats and restart init */ 6359 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6360 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6361 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6362 return; 6363 goto out; 6364 } 6365 6366 /* this is a message we already processed, do nothing */ 6367 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6368 return; 6369 6370 /* until the vf completes a reset it should not be 6371 * allowed to start any configuration. 6372 */ 6373 if (msgbuf[0] == E1000_VF_RESET) { 6374 igb_vf_reset_msg(adapter, vf); 6375 return; 6376 } 6377 6378 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6379 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6380 return; 6381 retval = -1; 6382 goto out; 6383 } 6384 6385 switch ((msgbuf[0] & 0xFFFF)) { 6386 case E1000_VF_SET_MAC_ADDR: 6387 retval = -EINVAL; 6388 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6389 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6390 else 6391 dev_warn(&pdev->dev, 6392 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6393 vf); 6394 break; 6395 case E1000_VF_SET_PROMISC: 6396 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6397 break; 6398 case E1000_VF_SET_MULTICAST: 6399 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6400 break; 6401 case E1000_VF_SET_LPE: 6402 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6403 break; 6404 case E1000_VF_SET_VLAN: 6405 retval = -1; 6406 if (vf_data->pf_vlan) 6407 dev_warn(&pdev->dev, 6408 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6409 vf); 6410 else 6411 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6412 break; 6413 default: 6414 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6415 retval = -1; 6416 break; 6417 } 6418 6419 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6420 out: 6421 /* notify the VF of the results of what it sent us */ 6422 if (retval) 6423 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6424 else 6425 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6426 6427 igb_write_mbx(hw, msgbuf, 1, vf); 6428 } 6429 6430 static void igb_msg_task(struct igb_adapter *adapter) 6431 { 6432 struct e1000_hw *hw = &adapter->hw; 6433 u32 vf; 6434 6435 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6436 /* process any reset requests */ 6437 if (!igb_check_for_rst(hw, vf)) 6438 igb_vf_reset_event(adapter, vf); 6439 6440 /* process any messages pending */ 6441 if (!igb_check_for_msg(hw, vf)) 6442 igb_rcv_msg_from_vf(adapter, vf); 6443 6444 /* process any acks */ 6445 if (!igb_check_for_ack(hw, vf)) 6446 igb_rcv_ack_from_vf(adapter, vf); 6447 } 6448 } 6449 6450 /** 6451 * igb_set_uta - Set unicast filter table address 6452 * @adapter: board private structure 6453 * @set: boolean indicating if we are setting or clearing bits 6454 * 6455 * The unicast table address is a register array of 32-bit registers. 6456 * The table is meant to be used in a way similar to how the MTA is used 6457 * however due to certain limitations in the hardware it is necessary to 6458 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6459 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6460 **/ 6461 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6462 { 6463 struct e1000_hw *hw = &adapter->hw; 6464 u32 uta = set ? ~0 : 0; 6465 int i; 6466 6467 /* we only need to do this if VMDq is enabled */ 6468 if (!adapter->vfs_allocated_count) 6469 return; 6470 6471 for (i = hw->mac.uta_reg_count; i--;) 6472 array_wr32(E1000_UTA, i, uta); 6473 } 6474 6475 /** 6476 * igb_intr_msi - Interrupt Handler 6477 * @irq: interrupt number 6478 * @data: pointer to a network interface device structure 6479 **/ 6480 static irqreturn_t igb_intr_msi(int irq, void *data) 6481 { 6482 struct igb_adapter *adapter = data; 6483 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6484 struct e1000_hw *hw = &adapter->hw; 6485 /* read ICR disables interrupts using IAM */ 6486 u32 icr = rd32(E1000_ICR); 6487 6488 igb_write_itr(q_vector); 6489 6490 if (icr & E1000_ICR_DRSTA) 6491 schedule_work(&adapter->reset_task); 6492 6493 if (icr & E1000_ICR_DOUTSYNC) { 6494 /* HW is reporting DMA is out of sync */ 6495 adapter->stats.doosync++; 6496 } 6497 6498 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6499 hw->mac.get_link_status = 1; 6500 if (!test_bit(__IGB_DOWN, &adapter->state)) 6501 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6502 } 6503 6504 if (icr & E1000_ICR_TS) 6505 igb_tsync_interrupt(adapter); 6506 6507 napi_schedule(&q_vector->napi); 6508 6509 return IRQ_HANDLED; 6510 } 6511 6512 /** 6513 * igb_intr - Legacy Interrupt Handler 6514 * @irq: interrupt number 6515 * @data: pointer to a network interface device structure 6516 **/ 6517 static irqreturn_t igb_intr(int irq, void *data) 6518 { 6519 struct igb_adapter *adapter = data; 6520 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6521 struct e1000_hw *hw = &adapter->hw; 6522 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6523 * need for the IMC write 6524 */ 6525 u32 icr = rd32(E1000_ICR); 6526 6527 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6528 * not set, then the adapter didn't send an interrupt 6529 */ 6530 if (!(icr & E1000_ICR_INT_ASSERTED)) 6531 return IRQ_NONE; 6532 6533 igb_write_itr(q_vector); 6534 6535 if (icr & E1000_ICR_DRSTA) 6536 schedule_work(&adapter->reset_task); 6537 6538 if (icr & E1000_ICR_DOUTSYNC) { 6539 /* HW is reporting DMA is out of sync */ 6540 adapter->stats.doosync++; 6541 } 6542 6543 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6544 hw->mac.get_link_status = 1; 6545 /* guard against interrupt when we're going down */ 6546 if (!test_bit(__IGB_DOWN, &adapter->state)) 6547 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6548 } 6549 6550 if (icr & E1000_ICR_TS) 6551 igb_tsync_interrupt(adapter); 6552 6553 napi_schedule(&q_vector->napi); 6554 6555 return IRQ_HANDLED; 6556 } 6557 6558 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6559 { 6560 struct igb_adapter *adapter = q_vector->adapter; 6561 struct e1000_hw *hw = &adapter->hw; 6562 6563 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6564 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6565 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6566 igb_set_itr(q_vector); 6567 else 6568 igb_update_ring_itr(q_vector); 6569 } 6570 6571 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6572 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6573 wr32(E1000_EIMS, q_vector->eims_value); 6574 else 6575 igb_irq_enable(adapter); 6576 } 6577 } 6578 6579 /** 6580 * igb_poll - NAPI Rx polling callback 6581 * @napi: napi polling structure 6582 * @budget: count of how many packets we should handle 6583 **/ 6584 static int igb_poll(struct napi_struct *napi, int budget) 6585 { 6586 struct igb_q_vector *q_vector = container_of(napi, 6587 struct igb_q_vector, 6588 napi); 6589 bool clean_complete = true; 6590 int work_done = 0; 6591 6592 #ifdef CONFIG_IGB_DCA 6593 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6594 igb_update_dca(q_vector); 6595 #endif 6596 if (q_vector->tx.ring) 6597 clean_complete = igb_clean_tx_irq(q_vector, budget); 6598 6599 if (q_vector->rx.ring) { 6600 int cleaned = igb_clean_rx_irq(q_vector, budget); 6601 6602 work_done += cleaned; 6603 if (cleaned >= budget) 6604 clean_complete = false; 6605 } 6606 6607 /* If all work not completed, return budget and keep polling */ 6608 if (!clean_complete) 6609 return budget; 6610 6611 /* If not enough Rx work done, exit the polling mode */ 6612 napi_complete_done(napi, work_done); 6613 igb_ring_irq_enable(q_vector); 6614 6615 return 0; 6616 } 6617 6618 /** 6619 * igb_clean_tx_irq - Reclaim resources after transmit completes 6620 * @q_vector: pointer to q_vector containing needed info 6621 * @napi_budget: Used to determine if we are in netpoll 6622 * 6623 * returns true if ring is completely cleaned 6624 **/ 6625 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6626 { 6627 struct igb_adapter *adapter = q_vector->adapter; 6628 struct igb_ring *tx_ring = q_vector->tx.ring; 6629 struct igb_tx_buffer *tx_buffer; 6630 union e1000_adv_tx_desc *tx_desc; 6631 unsigned int total_bytes = 0, total_packets = 0; 6632 unsigned int budget = q_vector->tx.work_limit; 6633 unsigned int i = tx_ring->next_to_clean; 6634 6635 if (test_bit(__IGB_DOWN, &adapter->state)) 6636 return true; 6637 6638 tx_buffer = &tx_ring->tx_buffer_info[i]; 6639 tx_desc = IGB_TX_DESC(tx_ring, i); 6640 i -= tx_ring->count; 6641 6642 do { 6643 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6644 6645 /* if next_to_watch is not set then there is no work pending */ 6646 if (!eop_desc) 6647 break; 6648 6649 /* prevent any other reads prior to eop_desc */ 6650 read_barrier_depends(); 6651 6652 /* if DD is not set pending work has not been completed */ 6653 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6654 break; 6655 6656 /* clear next_to_watch to prevent false hangs */ 6657 tx_buffer->next_to_watch = NULL; 6658 6659 /* update the statistics for this packet */ 6660 total_bytes += tx_buffer->bytecount; 6661 total_packets += tx_buffer->gso_segs; 6662 6663 /* free the skb */ 6664 napi_consume_skb(tx_buffer->skb, napi_budget); 6665 6666 /* unmap skb header data */ 6667 dma_unmap_single(tx_ring->dev, 6668 dma_unmap_addr(tx_buffer, dma), 6669 dma_unmap_len(tx_buffer, len), 6670 DMA_TO_DEVICE); 6671 6672 /* clear tx_buffer data */ 6673 tx_buffer->skb = NULL; 6674 dma_unmap_len_set(tx_buffer, len, 0); 6675 6676 /* clear last DMA location and unmap remaining buffers */ 6677 while (tx_desc != eop_desc) { 6678 tx_buffer++; 6679 tx_desc++; 6680 i++; 6681 if (unlikely(!i)) { 6682 i -= tx_ring->count; 6683 tx_buffer = tx_ring->tx_buffer_info; 6684 tx_desc = IGB_TX_DESC(tx_ring, 0); 6685 } 6686 6687 /* unmap any remaining paged data */ 6688 if (dma_unmap_len(tx_buffer, len)) { 6689 dma_unmap_page(tx_ring->dev, 6690 dma_unmap_addr(tx_buffer, dma), 6691 dma_unmap_len(tx_buffer, len), 6692 DMA_TO_DEVICE); 6693 dma_unmap_len_set(tx_buffer, len, 0); 6694 } 6695 } 6696 6697 /* move us one more past the eop_desc for start of next pkt */ 6698 tx_buffer++; 6699 tx_desc++; 6700 i++; 6701 if (unlikely(!i)) { 6702 i -= tx_ring->count; 6703 tx_buffer = tx_ring->tx_buffer_info; 6704 tx_desc = IGB_TX_DESC(tx_ring, 0); 6705 } 6706 6707 /* issue prefetch for next Tx descriptor */ 6708 prefetch(tx_desc); 6709 6710 /* update budget accounting */ 6711 budget--; 6712 } while (likely(budget)); 6713 6714 netdev_tx_completed_queue(txring_txq(tx_ring), 6715 total_packets, total_bytes); 6716 i += tx_ring->count; 6717 tx_ring->next_to_clean = i; 6718 u64_stats_update_begin(&tx_ring->tx_syncp); 6719 tx_ring->tx_stats.bytes += total_bytes; 6720 tx_ring->tx_stats.packets += total_packets; 6721 u64_stats_update_end(&tx_ring->tx_syncp); 6722 q_vector->tx.total_bytes += total_bytes; 6723 q_vector->tx.total_packets += total_packets; 6724 6725 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6726 struct e1000_hw *hw = &adapter->hw; 6727 6728 /* Detect a transmit hang in hardware, this serializes the 6729 * check with the clearing of time_stamp and movement of i 6730 */ 6731 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6732 if (tx_buffer->next_to_watch && 6733 time_after(jiffies, tx_buffer->time_stamp + 6734 (adapter->tx_timeout_factor * HZ)) && 6735 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6736 6737 /* detected Tx unit hang */ 6738 dev_err(tx_ring->dev, 6739 "Detected Tx Unit Hang\n" 6740 " Tx Queue <%d>\n" 6741 " TDH <%x>\n" 6742 " TDT <%x>\n" 6743 " next_to_use <%x>\n" 6744 " next_to_clean <%x>\n" 6745 "buffer_info[next_to_clean]\n" 6746 " time_stamp <%lx>\n" 6747 " next_to_watch <%p>\n" 6748 " jiffies <%lx>\n" 6749 " desc.status <%x>\n", 6750 tx_ring->queue_index, 6751 rd32(E1000_TDH(tx_ring->reg_idx)), 6752 readl(tx_ring->tail), 6753 tx_ring->next_to_use, 6754 tx_ring->next_to_clean, 6755 tx_buffer->time_stamp, 6756 tx_buffer->next_to_watch, 6757 jiffies, 6758 tx_buffer->next_to_watch->wb.status); 6759 netif_stop_subqueue(tx_ring->netdev, 6760 tx_ring->queue_index); 6761 6762 /* we are about to reset, no point in enabling stuff */ 6763 return true; 6764 } 6765 } 6766 6767 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6768 if (unlikely(total_packets && 6769 netif_carrier_ok(tx_ring->netdev) && 6770 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6771 /* Make sure that anybody stopping the queue after this 6772 * sees the new next_to_clean. 6773 */ 6774 smp_mb(); 6775 if (__netif_subqueue_stopped(tx_ring->netdev, 6776 tx_ring->queue_index) && 6777 !(test_bit(__IGB_DOWN, &adapter->state))) { 6778 netif_wake_subqueue(tx_ring->netdev, 6779 tx_ring->queue_index); 6780 6781 u64_stats_update_begin(&tx_ring->tx_syncp); 6782 tx_ring->tx_stats.restart_queue++; 6783 u64_stats_update_end(&tx_ring->tx_syncp); 6784 } 6785 } 6786 6787 return !!budget; 6788 } 6789 6790 /** 6791 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6792 * @rx_ring: rx descriptor ring to store buffers on 6793 * @old_buff: donor buffer to have page reused 6794 * 6795 * Synchronizes page for reuse by the adapter 6796 **/ 6797 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6798 struct igb_rx_buffer *old_buff) 6799 { 6800 struct igb_rx_buffer *new_buff; 6801 u16 nta = rx_ring->next_to_alloc; 6802 6803 new_buff = &rx_ring->rx_buffer_info[nta]; 6804 6805 /* update, and store next to alloc */ 6806 nta++; 6807 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6808 6809 /* transfer page from old buffer to new buffer */ 6810 *new_buff = *old_buff; 6811 6812 /* sync the buffer for use by the device */ 6813 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6814 old_buff->page_offset, 6815 IGB_RX_BUFSZ, 6816 DMA_FROM_DEVICE); 6817 } 6818 6819 static inline bool igb_page_is_reserved(struct page *page) 6820 { 6821 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 6822 } 6823 6824 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6825 struct page *page, 6826 unsigned int truesize) 6827 { 6828 /* avoid re-using remote pages */ 6829 if (unlikely(igb_page_is_reserved(page))) 6830 return false; 6831 6832 #if (PAGE_SIZE < 8192) 6833 /* if we are only owner of page we can reuse it */ 6834 if (unlikely(page_count(page) != 1)) 6835 return false; 6836 6837 /* flip page offset to other buffer */ 6838 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6839 #else 6840 /* move offset up to the next cache line */ 6841 rx_buffer->page_offset += truesize; 6842 6843 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6844 return false; 6845 #endif 6846 6847 /* Even if we own the page, we are not allowed to use atomic_set() 6848 * This would break get_page_unless_zero() users. 6849 */ 6850 page_ref_inc(page); 6851 6852 return true; 6853 } 6854 6855 /** 6856 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6857 * @rx_ring: rx descriptor ring to transact packets on 6858 * @rx_buffer: buffer containing page to add 6859 * @rx_desc: descriptor containing length of buffer written by hardware 6860 * @skb: sk_buff to place the data into 6861 * 6862 * This function will add the data contained in rx_buffer->page to the skb. 6863 * This is done either through a direct copy if the data in the buffer is 6864 * less than the skb header size, otherwise it will just attach the page as 6865 * a frag to the skb. 6866 * 6867 * The function will then update the page offset if necessary and return 6868 * true if the buffer can be reused by the adapter. 6869 **/ 6870 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6871 struct igb_rx_buffer *rx_buffer, 6872 unsigned int size, 6873 union e1000_adv_rx_desc *rx_desc, 6874 struct sk_buff *skb) 6875 { 6876 struct page *page = rx_buffer->page; 6877 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6878 #if (PAGE_SIZE < 8192) 6879 unsigned int truesize = IGB_RX_BUFSZ; 6880 #else 6881 unsigned int truesize = SKB_DATA_ALIGN(size); 6882 #endif 6883 unsigned int pull_len; 6884 6885 if (unlikely(skb_is_nonlinear(skb))) 6886 goto add_tail_frag; 6887 6888 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 6889 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6890 va += IGB_TS_HDR_LEN; 6891 size -= IGB_TS_HDR_LEN; 6892 } 6893 6894 if (likely(size <= IGB_RX_HDR_LEN)) { 6895 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6896 6897 /* page is not reserved, we can reuse buffer as-is */ 6898 if (likely(!igb_page_is_reserved(page))) 6899 return true; 6900 6901 /* this page cannot be reused so discard it */ 6902 __free_page(page); 6903 return false; 6904 } 6905 6906 /* we need the header to contain the greater of either ETH_HLEN or 6907 * 60 bytes if the skb->len is less than 60 for skb_pad. 6908 */ 6909 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6910 6911 /* align pull length to size of long to optimize memcpy performance */ 6912 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 6913 6914 /* update all of the pointers */ 6915 va += pull_len; 6916 size -= pull_len; 6917 6918 add_tail_frag: 6919 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6920 (unsigned long)va & ~PAGE_MASK, size, truesize); 6921 6922 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6923 } 6924 6925 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6926 union e1000_adv_rx_desc *rx_desc, 6927 struct sk_buff *skb) 6928 { 6929 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6930 struct igb_rx_buffer *rx_buffer; 6931 struct page *page; 6932 6933 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6934 page = rx_buffer->page; 6935 prefetchw(page); 6936 6937 if (likely(!skb)) { 6938 void *page_addr = page_address(page) + 6939 rx_buffer->page_offset; 6940 6941 /* prefetch first cache line of first page */ 6942 prefetch(page_addr); 6943 #if L1_CACHE_BYTES < 128 6944 prefetch(page_addr + L1_CACHE_BYTES); 6945 #endif 6946 6947 /* allocate a skb to store the frags */ 6948 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6949 if (unlikely(!skb)) { 6950 rx_ring->rx_stats.alloc_failed++; 6951 return NULL; 6952 } 6953 6954 /* we will be copying header into skb->data in 6955 * pskb_may_pull so it is in our interest to prefetch 6956 * it now to avoid a possible cache miss 6957 */ 6958 prefetchw(skb->data); 6959 } 6960 6961 /* we are reusing so sync this buffer for CPU use */ 6962 dma_sync_single_range_for_cpu(rx_ring->dev, 6963 rx_buffer->dma, 6964 rx_buffer->page_offset, 6965 size, 6966 DMA_FROM_DEVICE); 6967 6968 /* pull page into skb */ 6969 if (igb_add_rx_frag(rx_ring, rx_buffer, size, rx_desc, skb)) { 6970 /* hand second half of page back to the ring */ 6971 igb_reuse_rx_page(rx_ring, rx_buffer); 6972 } else { 6973 /* we are not reusing the buffer so unmap it */ 6974 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6975 PAGE_SIZE, DMA_FROM_DEVICE); 6976 } 6977 6978 /* clear contents of rx_buffer */ 6979 rx_buffer->page = NULL; 6980 6981 return skb; 6982 } 6983 6984 static inline void igb_rx_checksum(struct igb_ring *ring, 6985 union e1000_adv_rx_desc *rx_desc, 6986 struct sk_buff *skb) 6987 { 6988 skb_checksum_none_assert(skb); 6989 6990 /* Ignore Checksum bit is set */ 6991 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6992 return; 6993 6994 /* Rx checksum disabled via ethtool */ 6995 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6996 return; 6997 6998 /* TCP/UDP checksum error bit is set */ 6999 if (igb_test_staterr(rx_desc, 7000 E1000_RXDEXT_STATERR_TCPE | 7001 E1000_RXDEXT_STATERR_IPE)) { 7002 /* work around errata with sctp packets where the TCPE aka 7003 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7004 * packets, (aka let the stack check the crc32c) 7005 */ 7006 if (!((skb->len == 60) && 7007 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7008 u64_stats_update_begin(&ring->rx_syncp); 7009 ring->rx_stats.csum_err++; 7010 u64_stats_update_end(&ring->rx_syncp); 7011 } 7012 /* let the stack verify checksum errors */ 7013 return; 7014 } 7015 /* It must be a TCP or UDP packet with a valid checksum */ 7016 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7017 E1000_RXD_STAT_UDPCS)) 7018 skb->ip_summed = CHECKSUM_UNNECESSARY; 7019 7020 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7021 le32_to_cpu(rx_desc->wb.upper.status_error)); 7022 } 7023 7024 static inline void igb_rx_hash(struct igb_ring *ring, 7025 union e1000_adv_rx_desc *rx_desc, 7026 struct sk_buff *skb) 7027 { 7028 if (ring->netdev->features & NETIF_F_RXHASH) 7029 skb_set_hash(skb, 7030 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7031 PKT_HASH_TYPE_L3); 7032 } 7033 7034 /** 7035 * igb_is_non_eop - process handling of non-EOP buffers 7036 * @rx_ring: Rx ring being processed 7037 * @rx_desc: Rx descriptor for current buffer 7038 * @skb: current socket buffer containing buffer in progress 7039 * 7040 * This function updates next to clean. If the buffer is an EOP buffer 7041 * this function exits returning false, otherwise it will place the 7042 * sk_buff in the next buffer to be chained and return true indicating 7043 * that this is in fact a non-EOP buffer. 7044 **/ 7045 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7046 union e1000_adv_rx_desc *rx_desc) 7047 { 7048 u32 ntc = rx_ring->next_to_clean + 1; 7049 7050 /* fetch, update, and store next to clean */ 7051 ntc = (ntc < rx_ring->count) ? ntc : 0; 7052 rx_ring->next_to_clean = ntc; 7053 7054 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7055 7056 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7057 return false; 7058 7059 return true; 7060 } 7061 7062 /** 7063 * igb_cleanup_headers - Correct corrupted or empty headers 7064 * @rx_ring: rx descriptor ring packet is being transacted on 7065 * @rx_desc: pointer to the EOP Rx descriptor 7066 * @skb: pointer to current skb being fixed 7067 * 7068 * Address the case where we are pulling data in on pages only 7069 * and as such no data is present in the skb header. 7070 * 7071 * In addition if skb is not at least 60 bytes we need to pad it so that 7072 * it is large enough to qualify as a valid Ethernet frame. 7073 * 7074 * Returns true if an error was encountered and skb was freed. 7075 **/ 7076 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7077 union e1000_adv_rx_desc *rx_desc, 7078 struct sk_buff *skb) 7079 { 7080 if (unlikely((igb_test_staterr(rx_desc, 7081 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7082 struct net_device *netdev = rx_ring->netdev; 7083 if (!(netdev->features & NETIF_F_RXALL)) { 7084 dev_kfree_skb_any(skb); 7085 return true; 7086 } 7087 } 7088 7089 /* if eth_skb_pad returns an error the skb was freed */ 7090 if (eth_skb_pad(skb)) 7091 return true; 7092 7093 return false; 7094 } 7095 7096 /** 7097 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7098 * @rx_ring: rx descriptor ring packet is being transacted on 7099 * @rx_desc: pointer to the EOP Rx descriptor 7100 * @skb: pointer to current skb being populated 7101 * 7102 * This function checks the ring, descriptor, and packet information in 7103 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7104 * other fields within the skb. 7105 **/ 7106 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7107 union e1000_adv_rx_desc *rx_desc, 7108 struct sk_buff *skb) 7109 { 7110 struct net_device *dev = rx_ring->netdev; 7111 7112 igb_rx_hash(rx_ring, rx_desc, skb); 7113 7114 igb_rx_checksum(rx_ring, rx_desc, skb); 7115 7116 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7117 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7118 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7119 7120 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7121 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7122 u16 vid; 7123 7124 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7125 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7126 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7127 else 7128 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7129 7130 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7131 } 7132 7133 skb_record_rx_queue(skb, rx_ring->queue_index); 7134 7135 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7136 } 7137 7138 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7139 { 7140 struct igb_ring *rx_ring = q_vector->rx.ring; 7141 struct sk_buff *skb = rx_ring->skb; 7142 unsigned int total_bytes = 0, total_packets = 0; 7143 u16 cleaned_count = igb_desc_unused(rx_ring); 7144 7145 while (likely(total_packets < budget)) { 7146 union e1000_adv_rx_desc *rx_desc; 7147 7148 /* return some buffers to hardware, one at a time is too slow */ 7149 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7150 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7151 cleaned_count = 0; 7152 } 7153 7154 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7155 7156 if (!rx_desc->wb.upper.status_error) 7157 break; 7158 7159 /* This memory barrier is needed to keep us from reading 7160 * any other fields out of the rx_desc until we know the 7161 * descriptor has been written back 7162 */ 7163 dma_rmb(); 7164 7165 /* retrieve a buffer from the ring */ 7166 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7167 7168 /* exit if we failed to retrieve a buffer */ 7169 if (!skb) 7170 break; 7171 7172 cleaned_count++; 7173 7174 /* fetch next buffer in frame if non-eop */ 7175 if (igb_is_non_eop(rx_ring, rx_desc)) 7176 continue; 7177 7178 /* verify the packet layout is correct */ 7179 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7180 skb = NULL; 7181 continue; 7182 } 7183 7184 /* probably a little skewed due to removing CRC */ 7185 total_bytes += skb->len; 7186 7187 /* populate checksum, timestamp, VLAN, and protocol */ 7188 igb_process_skb_fields(rx_ring, rx_desc, skb); 7189 7190 napi_gro_receive(&q_vector->napi, skb); 7191 7192 /* reset skb pointer */ 7193 skb = NULL; 7194 7195 /* update budget accounting */ 7196 total_packets++; 7197 } 7198 7199 /* place incomplete frames back on ring for completion */ 7200 rx_ring->skb = skb; 7201 7202 u64_stats_update_begin(&rx_ring->rx_syncp); 7203 rx_ring->rx_stats.packets += total_packets; 7204 rx_ring->rx_stats.bytes += total_bytes; 7205 u64_stats_update_end(&rx_ring->rx_syncp); 7206 q_vector->rx.total_packets += total_packets; 7207 q_vector->rx.total_bytes += total_bytes; 7208 7209 if (cleaned_count) 7210 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7211 7212 return total_packets; 7213 } 7214 7215 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7216 struct igb_rx_buffer *bi) 7217 { 7218 struct page *page = bi->page; 7219 dma_addr_t dma; 7220 7221 /* since we are recycling buffers we should seldom need to alloc */ 7222 if (likely(page)) 7223 return true; 7224 7225 /* alloc new page for storage */ 7226 page = dev_alloc_page(); 7227 if (unlikely(!page)) { 7228 rx_ring->rx_stats.alloc_failed++; 7229 return false; 7230 } 7231 7232 /* map page for use */ 7233 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7234 7235 /* if mapping failed free memory back to system since 7236 * there isn't much point in holding memory we can't use 7237 */ 7238 if (dma_mapping_error(rx_ring->dev, dma)) { 7239 __free_page(page); 7240 7241 rx_ring->rx_stats.alloc_failed++; 7242 return false; 7243 } 7244 7245 bi->dma = dma; 7246 bi->page = page; 7247 bi->page_offset = 0; 7248 7249 return true; 7250 } 7251 7252 /** 7253 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7254 * @adapter: address of board private structure 7255 **/ 7256 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7257 { 7258 union e1000_adv_rx_desc *rx_desc; 7259 struct igb_rx_buffer *bi; 7260 u16 i = rx_ring->next_to_use; 7261 7262 /* nothing to do */ 7263 if (!cleaned_count) 7264 return; 7265 7266 rx_desc = IGB_RX_DESC(rx_ring, i); 7267 bi = &rx_ring->rx_buffer_info[i]; 7268 i -= rx_ring->count; 7269 7270 do { 7271 if (!igb_alloc_mapped_page(rx_ring, bi)) 7272 break; 7273 7274 /* Refresh the desc even if buffer_addrs didn't change 7275 * because each write-back erases this info. 7276 */ 7277 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7278 7279 rx_desc++; 7280 bi++; 7281 i++; 7282 if (unlikely(!i)) { 7283 rx_desc = IGB_RX_DESC(rx_ring, 0); 7284 bi = rx_ring->rx_buffer_info; 7285 i -= rx_ring->count; 7286 } 7287 7288 /* clear the status bits for the next_to_use descriptor */ 7289 rx_desc->wb.upper.status_error = 0; 7290 7291 cleaned_count--; 7292 } while (cleaned_count); 7293 7294 i += rx_ring->count; 7295 7296 if (rx_ring->next_to_use != i) { 7297 /* record the next descriptor to use */ 7298 rx_ring->next_to_use = i; 7299 7300 /* update next to alloc since we have filled the ring */ 7301 rx_ring->next_to_alloc = i; 7302 7303 /* Force memory writes to complete before letting h/w 7304 * know there are new descriptors to fetch. (Only 7305 * applicable for weak-ordered memory model archs, 7306 * such as IA-64). 7307 */ 7308 wmb(); 7309 writel(i, rx_ring->tail); 7310 } 7311 } 7312 7313 /** 7314 * igb_mii_ioctl - 7315 * @netdev: 7316 * @ifreq: 7317 * @cmd: 7318 **/ 7319 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7320 { 7321 struct igb_adapter *adapter = netdev_priv(netdev); 7322 struct mii_ioctl_data *data = if_mii(ifr); 7323 7324 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7325 return -EOPNOTSUPP; 7326 7327 switch (cmd) { 7328 case SIOCGMIIPHY: 7329 data->phy_id = adapter->hw.phy.addr; 7330 break; 7331 case SIOCGMIIREG: 7332 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7333 &data->val_out)) 7334 return -EIO; 7335 break; 7336 case SIOCSMIIREG: 7337 default: 7338 return -EOPNOTSUPP; 7339 } 7340 return 0; 7341 } 7342 7343 /** 7344 * igb_ioctl - 7345 * @netdev: 7346 * @ifreq: 7347 * @cmd: 7348 **/ 7349 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7350 { 7351 switch (cmd) { 7352 case SIOCGMIIPHY: 7353 case SIOCGMIIREG: 7354 case SIOCSMIIREG: 7355 return igb_mii_ioctl(netdev, ifr, cmd); 7356 case SIOCGHWTSTAMP: 7357 return igb_ptp_get_ts_config(netdev, ifr); 7358 case SIOCSHWTSTAMP: 7359 return igb_ptp_set_ts_config(netdev, ifr); 7360 default: 7361 return -EOPNOTSUPP; 7362 } 7363 } 7364 7365 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7366 { 7367 struct igb_adapter *adapter = hw->back; 7368 7369 pci_read_config_word(adapter->pdev, reg, value); 7370 } 7371 7372 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7373 { 7374 struct igb_adapter *adapter = hw->back; 7375 7376 pci_write_config_word(adapter->pdev, reg, *value); 7377 } 7378 7379 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7380 { 7381 struct igb_adapter *adapter = hw->back; 7382 7383 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7384 return -E1000_ERR_CONFIG; 7385 7386 return 0; 7387 } 7388 7389 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7390 { 7391 struct igb_adapter *adapter = hw->back; 7392 7393 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7394 return -E1000_ERR_CONFIG; 7395 7396 return 0; 7397 } 7398 7399 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7400 { 7401 struct igb_adapter *adapter = netdev_priv(netdev); 7402 struct e1000_hw *hw = &adapter->hw; 7403 u32 ctrl, rctl; 7404 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7405 7406 if (enable) { 7407 /* enable VLAN tag insert/strip */ 7408 ctrl = rd32(E1000_CTRL); 7409 ctrl |= E1000_CTRL_VME; 7410 wr32(E1000_CTRL, ctrl); 7411 7412 /* Disable CFI check */ 7413 rctl = rd32(E1000_RCTL); 7414 rctl &= ~E1000_RCTL_CFIEN; 7415 wr32(E1000_RCTL, rctl); 7416 } else { 7417 /* disable VLAN tag insert/strip */ 7418 ctrl = rd32(E1000_CTRL); 7419 ctrl &= ~E1000_CTRL_VME; 7420 wr32(E1000_CTRL, ctrl); 7421 } 7422 7423 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7424 } 7425 7426 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7427 __be16 proto, u16 vid) 7428 { 7429 struct igb_adapter *adapter = netdev_priv(netdev); 7430 struct e1000_hw *hw = &adapter->hw; 7431 int pf_id = adapter->vfs_allocated_count; 7432 7433 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7434 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7435 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7436 7437 set_bit(vid, adapter->active_vlans); 7438 7439 return 0; 7440 } 7441 7442 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7443 __be16 proto, u16 vid) 7444 { 7445 struct igb_adapter *adapter = netdev_priv(netdev); 7446 int pf_id = adapter->vfs_allocated_count; 7447 struct e1000_hw *hw = &adapter->hw; 7448 7449 /* remove VID from filter table */ 7450 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7451 igb_vfta_set(hw, vid, pf_id, false, true); 7452 7453 clear_bit(vid, adapter->active_vlans); 7454 7455 return 0; 7456 } 7457 7458 static void igb_restore_vlan(struct igb_adapter *adapter) 7459 { 7460 u16 vid = 1; 7461 7462 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7463 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7464 7465 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7466 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7467 } 7468 7469 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7470 { 7471 struct pci_dev *pdev = adapter->pdev; 7472 struct e1000_mac_info *mac = &adapter->hw.mac; 7473 7474 mac->autoneg = 0; 7475 7476 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7477 * for the switch() below to work 7478 */ 7479 if ((spd & 1) || (dplx & ~1)) 7480 goto err_inval; 7481 7482 /* Fiber NIC's only allow 1000 gbps Full duplex 7483 * and 100Mbps Full duplex for 100baseFx sfp 7484 */ 7485 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7486 switch (spd + dplx) { 7487 case SPEED_10 + DUPLEX_HALF: 7488 case SPEED_10 + DUPLEX_FULL: 7489 case SPEED_100 + DUPLEX_HALF: 7490 goto err_inval; 7491 default: 7492 break; 7493 } 7494 } 7495 7496 switch (spd + dplx) { 7497 case SPEED_10 + DUPLEX_HALF: 7498 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7499 break; 7500 case SPEED_10 + DUPLEX_FULL: 7501 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7502 break; 7503 case SPEED_100 + DUPLEX_HALF: 7504 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7505 break; 7506 case SPEED_100 + DUPLEX_FULL: 7507 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7508 break; 7509 case SPEED_1000 + DUPLEX_FULL: 7510 mac->autoneg = 1; 7511 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7512 break; 7513 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7514 default: 7515 goto err_inval; 7516 } 7517 7518 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7519 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7520 7521 return 0; 7522 7523 err_inval: 7524 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7525 return -EINVAL; 7526 } 7527 7528 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7529 bool runtime) 7530 { 7531 struct net_device *netdev = pci_get_drvdata(pdev); 7532 struct igb_adapter *adapter = netdev_priv(netdev); 7533 struct e1000_hw *hw = &adapter->hw; 7534 u32 ctrl, rctl, status; 7535 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7536 #ifdef CONFIG_PM 7537 int retval = 0; 7538 #endif 7539 7540 netif_device_detach(netdev); 7541 7542 if (netif_running(netdev)) 7543 __igb_close(netdev, true); 7544 7545 igb_ptp_suspend(adapter); 7546 7547 igb_clear_interrupt_scheme(adapter); 7548 7549 #ifdef CONFIG_PM 7550 retval = pci_save_state(pdev); 7551 if (retval) 7552 return retval; 7553 #endif 7554 7555 status = rd32(E1000_STATUS); 7556 if (status & E1000_STATUS_LU) 7557 wufc &= ~E1000_WUFC_LNKC; 7558 7559 if (wufc) { 7560 igb_setup_rctl(adapter); 7561 igb_set_rx_mode(netdev); 7562 7563 /* turn on all-multi mode if wake on multicast is enabled */ 7564 if (wufc & E1000_WUFC_MC) { 7565 rctl = rd32(E1000_RCTL); 7566 rctl |= E1000_RCTL_MPE; 7567 wr32(E1000_RCTL, rctl); 7568 } 7569 7570 ctrl = rd32(E1000_CTRL); 7571 /* advertise wake from D3Cold */ 7572 #define E1000_CTRL_ADVD3WUC 0x00100000 7573 /* phy power management enable */ 7574 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7575 ctrl |= E1000_CTRL_ADVD3WUC; 7576 wr32(E1000_CTRL, ctrl); 7577 7578 /* Allow time for pending master requests to run */ 7579 igb_disable_pcie_master(hw); 7580 7581 wr32(E1000_WUC, E1000_WUC_PME_EN); 7582 wr32(E1000_WUFC, wufc); 7583 } else { 7584 wr32(E1000_WUC, 0); 7585 wr32(E1000_WUFC, 0); 7586 } 7587 7588 *enable_wake = wufc || adapter->en_mng_pt; 7589 if (!*enable_wake) 7590 igb_power_down_link(adapter); 7591 else 7592 igb_power_up_link(adapter); 7593 7594 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7595 * would have already happened in close and is redundant. 7596 */ 7597 igb_release_hw_control(adapter); 7598 7599 pci_disable_device(pdev); 7600 7601 return 0; 7602 } 7603 7604 #ifdef CONFIG_PM 7605 #ifdef CONFIG_PM_SLEEP 7606 static int igb_suspend(struct device *dev) 7607 { 7608 int retval; 7609 bool wake; 7610 struct pci_dev *pdev = to_pci_dev(dev); 7611 7612 retval = __igb_shutdown(pdev, &wake, 0); 7613 if (retval) 7614 return retval; 7615 7616 if (wake) { 7617 pci_prepare_to_sleep(pdev); 7618 } else { 7619 pci_wake_from_d3(pdev, false); 7620 pci_set_power_state(pdev, PCI_D3hot); 7621 } 7622 7623 return 0; 7624 } 7625 #endif /* CONFIG_PM_SLEEP */ 7626 7627 static int igb_resume(struct device *dev) 7628 { 7629 struct pci_dev *pdev = to_pci_dev(dev); 7630 struct net_device *netdev = pci_get_drvdata(pdev); 7631 struct igb_adapter *adapter = netdev_priv(netdev); 7632 struct e1000_hw *hw = &adapter->hw; 7633 u32 err; 7634 7635 pci_set_power_state(pdev, PCI_D0); 7636 pci_restore_state(pdev); 7637 pci_save_state(pdev); 7638 7639 if (!pci_device_is_present(pdev)) 7640 return -ENODEV; 7641 err = pci_enable_device_mem(pdev); 7642 if (err) { 7643 dev_err(&pdev->dev, 7644 "igb: Cannot enable PCI device from suspend\n"); 7645 return err; 7646 } 7647 pci_set_master(pdev); 7648 7649 pci_enable_wake(pdev, PCI_D3hot, 0); 7650 pci_enable_wake(pdev, PCI_D3cold, 0); 7651 7652 if (igb_init_interrupt_scheme(adapter, true)) { 7653 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7654 return -ENOMEM; 7655 } 7656 7657 igb_reset(adapter); 7658 7659 /* let the f/w know that the h/w is now under the control of the 7660 * driver. 7661 */ 7662 igb_get_hw_control(adapter); 7663 7664 wr32(E1000_WUS, ~0); 7665 7666 if (netdev->flags & IFF_UP) { 7667 rtnl_lock(); 7668 err = __igb_open(netdev, true); 7669 rtnl_unlock(); 7670 if (err) 7671 return err; 7672 } 7673 7674 netif_device_attach(netdev); 7675 return 0; 7676 } 7677 7678 static int igb_runtime_idle(struct device *dev) 7679 { 7680 struct pci_dev *pdev = to_pci_dev(dev); 7681 struct net_device *netdev = pci_get_drvdata(pdev); 7682 struct igb_adapter *adapter = netdev_priv(netdev); 7683 7684 if (!igb_has_link(adapter)) 7685 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7686 7687 return -EBUSY; 7688 } 7689 7690 static int igb_runtime_suspend(struct device *dev) 7691 { 7692 struct pci_dev *pdev = to_pci_dev(dev); 7693 int retval; 7694 bool wake; 7695 7696 retval = __igb_shutdown(pdev, &wake, 1); 7697 if (retval) 7698 return retval; 7699 7700 if (wake) { 7701 pci_prepare_to_sleep(pdev); 7702 } else { 7703 pci_wake_from_d3(pdev, false); 7704 pci_set_power_state(pdev, PCI_D3hot); 7705 } 7706 7707 return 0; 7708 } 7709 7710 static int igb_runtime_resume(struct device *dev) 7711 { 7712 return igb_resume(dev); 7713 } 7714 #endif /* CONFIG_PM */ 7715 7716 static void igb_shutdown(struct pci_dev *pdev) 7717 { 7718 bool wake; 7719 7720 __igb_shutdown(pdev, &wake, 0); 7721 7722 if (system_state == SYSTEM_POWER_OFF) { 7723 pci_wake_from_d3(pdev, wake); 7724 pci_set_power_state(pdev, PCI_D3hot); 7725 } 7726 } 7727 7728 #ifdef CONFIG_PCI_IOV 7729 static int igb_sriov_reinit(struct pci_dev *dev) 7730 { 7731 struct net_device *netdev = pci_get_drvdata(dev); 7732 struct igb_adapter *adapter = netdev_priv(netdev); 7733 struct pci_dev *pdev = adapter->pdev; 7734 7735 rtnl_lock(); 7736 7737 if (netif_running(netdev)) 7738 igb_close(netdev); 7739 else 7740 igb_reset(adapter); 7741 7742 igb_clear_interrupt_scheme(adapter); 7743 7744 igb_init_queue_configuration(adapter); 7745 7746 if (igb_init_interrupt_scheme(adapter, true)) { 7747 rtnl_unlock(); 7748 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7749 return -ENOMEM; 7750 } 7751 7752 if (netif_running(netdev)) 7753 igb_open(netdev); 7754 7755 rtnl_unlock(); 7756 7757 return 0; 7758 } 7759 7760 static int igb_pci_disable_sriov(struct pci_dev *dev) 7761 { 7762 int err = igb_disable_sriov(dev); 7763 7764 if (!err) 7765 err = igb_sriov_reinit(dev); 7766 7767 return err; 7768 } 7769 7770 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7771 { 7772 int err = igb_enable_sriov(dev, num_vfs); 7773 7774 if (err) 7775 goto out; 7776 7777 err = igb_sriov_reinit(dev); 7778 if (!err) 7779 return num_vfs; 7780 7781 out: 7782 return err; 7783 } 7784 7785 #endif 7786 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7787 { 7788 #ifdef CONFIG_PCI_IOV 7789 if (num_vfs == 0) 7790 return igb_pci_disable_sriov(dev); 7791 else 7792 return igb_pci_enable_sriov(dev, num_vfs); 7793 #endif 7794 return 0; 7795 } 7796 7797 #ifdef CONFIG_NET_POLL_CONTROLLER 7798 /* Polling 'interrupt' - used by things like netconsole to send skbs 7799 * without having to re-enable interrupts. It's not called while 7800 * the interrupt routine is executing. 7801 */ 7802 static void igb_netpoll(struct net_device *netdev) 7803 { 7804 struct igb_adapter *adapter = netdev_priv(netdev); 7805 struct e1000_hw *hw = &adapter->hw; 7806 struct igb_q_vector *q_vector; 7807 int i; 7808 7809 for (i = 0; i < adapter->num_q_vectors; i++) { 7810 q_vector = adapter->q_vector[i]; 7811 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7812 wr32(E1000_EIMC, q_vector->eims_value); 7813 else 7814 igb_irq_disable(adapter); 7815 napi_schedule(&q_vector->napi); 7816 } 7817 } 7818 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7819 7820 /** 7821 * igb_io_error_detected - called when PCI error is detected 7822 * @pdev: Pointer to PCI device 7823 * @state: The current pci connection state 7824 * 7825 * This function is called after a PCI bus error affecting 7826 * this device has been detected. 7827 **/ 7828 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7829 pci_channel_state_t state) 7830 { 7831 struct net_device *netdev = pci_get_drvdata(pdev); 7832 struct igb_adapter *adapter = netdev_priv(netdev); 7833 7834 netif_device_detach(netdev); 7835 7836 if (state == pci_channel_io_perm_failure) 7837 return PCI_ERS_RESULT_DISCONNECT; 7838 7839 if (netif_running(netdev)) 7840 igb_down(adapter); 7841 pci_disable_device(pdev); 7842 7843 /* Request a slot slot reset. */ 7844 return PCI_ERS_RESULT_NEED_RESET; 7845 } 7846 7847 /** 7848 * igb_io_slot_reset - called after the pci bus has been reset. 7849 * @pdev: Pointer to PCI device 7850 * 7851 * Restart the card from scratch, as if from a cold-boot. Implementation 7852 * resembles the first-half of the igb_resume routine. 7853 **/ 7854 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7855 { 7856 struct net_device *netdev = pci_get_drvdata(pdev); 7857 struct igb_adapter *adapter = netdev_priv(netdev); 7858 struct e1000_hw *hw = &adapter->hw; 7859 pci_ers_result_t result; 7860 int err; 7861 7862 if (pci_enable_device_mem(pdev)) { 7863 dev_err(&pdev->dev, 7864 "Cannot re-enable PCI device after reset.\n"); 7865 result = PCI_ERS_RESULT_DISCONNECT; 7866 } else { 7867 pci_set_master(pdev); 7868 pci_restore_state(pdev); 7869 pci_save_state(pdev); 7870 7871 pci_enable_wake(pdev, PCI_D3hot, 0); 7872 pci_enable_wake(pdev, PCI_D3cold, 0); 7873 7874 igb_reset(adapter); 7875 wr32(E1000_WUS, ~0); 7876 result = PCI_ERS_RESULT_RECOVERED; 7877 } 7878 7879 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7880 if (err) { 7881 dev_err(&pdev->dev, 7882 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7883 err); 7884 /* non-fatal, continue */ 7885 } 7886 7887 return result; 7888 } 7889 7890 /** 7891 * igb_io_resume - called when traffic can start flowing again. 7892 * @pdev: Pointer to PCI device 7893 * 7894 * This callback is called when the error recovery driver tells us that 7895 * its OK to resume normal operation. Implementation resembles the 7896 * second-half of the igb_resume routine. 7897 */ 7898 static void igb_io_resume(struct pci_dev *pdev) 7899 { 7900 struct net_device *netdev = pci_get_drvdata(pdev); 7901 struct igb_adapter *adapter = netdev_priv(netdev); 7902 7903 if (netif_running(netdev)) { 7904 if (igb_up(adapter)) { 7905 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7906 return; 7907 } 7908 } 7909 7910 netif_device_attach(netdev); 7911 7912 /* let the f/w know that the h/w is now under the control of the 7913 * driver. 7914 */ 7915 igb_get_hw_control(adapter); 7916 } 7917 7918 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7919 u8 qsel) 7920 { 7921 struct e1000_hw *hw = &adapter->hw; 7922 u32 rar_low, rar_high; 7923 7924 /* HW expects these to be in network order when they are plugged 7925 * into the registers which are little endian. In order to guarantee 7926 * that ordering we need to do an leXX_to_cpup here in order to be 7927 * ready for the byteswap that occurs with writel 7928 */ 7929 rar_low = le32_to_cpup((__le32 *)(addr)); 7930 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 7931 7932 /* Indicate to hardware the Address is Valid. */ 7933 rar_high |= E1000_RAH_AV; 7934 7935 if (hw->mac.type == e1000_82575) 7936 rar_high |= E1000_RAH_POOL_1 * qsel; 7937 else 7938 rar_high |= E1000_RAH_POOL_1 << qsel; 7939 7940 wr32(E1000_RAL(index), rar_low); 7941 wrfl(); 7942 wr32(E1000_RAH(index), rar_high); 7943 wrfl(); 7944 } 7945 7946 static int igb_set_vf_mac(struct igb_adapter *adapter, 7947 int vf, unsigned char *mac_addr) 7948 { 7949 struct e1000_hw *hw = &adapter->hw; 7950 /* VF MAC addresses start at end of receive addresses and moves 7951 * towards the first, as a result a collision should not be possible 7952 */ 7953 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7954 7955 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7956 7957 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7958 7959 return 0; 7960 } 7961 7962 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7963 { 7964 struct igb_adapter *adapter = netdev_priv(netdev); 7965 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7966 return -EINVAL; 7967 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7968 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7969 dev_info(&adapter->pdev->dev, 7970 "Reload the VF driver to make this change effective."); 7971 if (test_bit(__IGB_DOWN, &adapter->state)) { 7972 dev_warn(&adapter->pdev->dev, 7973 "The VF MAC address has been set, but the PF device is not up.\n"); 7974 dev_warn(&adapter->pdev->dev, 7975 "Bring the PF device up before attempting to use the VF device.\n"); 7976 } 7977 return igb_set_vf_mac(adapter, vf, mac); 7978 } 7979 7980 static int igb_link_mbps(int internal_link_speed) 7981 { 7982 switch (internal_link_speed) { 7983 case SPEED_100: 7984 return 100; 7985 case SPEED_1000: 7986 return 1000; 7987 default: 7988 return 0; 7989 } 7990 } 7991 7992 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7993 int link_speed) 7994 { 7995 int rf_dec, rf_int; 7996 u32 bcnrc_val; 7997 7998 if (tx_rate != 0) { 7999 /* Calculate the rate factor values to set */ 8000 rf_int = link_speed / tx_rate; 8001 rf_dec = (link_speed - (rf_int * tx_rate)); 8002 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8003 tx_rate; 8004 8005 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8006 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8007 E1000_RTTBCNRC_RF_INT_MASK); 8008 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8009 } else { 8010 bcnrc_val = 0; 8011 } 8012 8013 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8014 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8015 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8016 */ 8017 wr32(E1000_RTTBCNRM, 0x14); 8018 wr32(E1000_RTTBCNRC, bcnrc_val); 8019 } 8020 8021 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8022 { 8023 int actual_link_speed, i; 8024 bool reset_rate = false; 8025 8026 /* VF TX rate limit was not set or not supported */ 8027 if ((adapter->vf_rate_link_speed == 0) || 8028 (adapter->hw.mac.type != e1000_82576)) 8029 return; 8030 8031 actual_link_speed = igb_link_mbps(adapter->link_speed); 8032 if (actual_link_speed != adapter->vf_rate_link_speed) { 8033 reset_rate = true; 8034 adapter->vf_rate_link_speed = 0; 8035 dev_info(&adapter->pdev->dev, 8036 "Link speed has been changed. VF Transmit rate is disabled\n"); 8037 } 8038 8039 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8040 if (reset_rate) 8041 adapter->vf_data[i].tx_rate = 0; 8042 8043 igb_set_vf_rate_limit(&adapter->hw, i, 8044 adapter->vf_data[i].tx_rate, 8045 actual_link_speed); 8046 } 8047 } 8048 8049 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8050 int min_tx_rate, int max_tx_rate) 8051 { 8052 struct igb_adapter *adapter = netdev_priv(netdev); 8053 struct e1000_hw *hw = &adapter->hw; 8054 int actual_link_speed; 8055 8056 if (hw->mac.type != e1000_82576) 8057 return -EOPNOTSUPP; 8058 8059 if (min_tx_rate) 8060 return -EINVAL; 8061 8062 actual_link_speed = igb_link_mbps(adapter->link_speed); 8063 if ((vf >= adapter->vfs_allocated_count) || 8064 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8065 (max_tx_rate < 0) || 8066 (max_tx_rate > actual_link_speed)) 8067 return -EINVAL; 8068 8069 adapter->vf_rate_link_speed = actual_link_speed; 8070 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8071 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8072 8073 return 0; 8074 } 8075 8076 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8077 bool setting) 8078 { 8079 struct igb_adapter *adapter = netdev_priv(netdev); 8080 struct e1000_hw *hw = &adapter->hw; 8081 u32 reg_val, reg_offset; 8082 8083 if (!adapter->vfs_allocated_count) 8084 return -EOPNOTSUPP; 8085 8086 if (vf >= adapter->vfs_allocated_count) 8087 return -EINVAL; 8088 8089 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8090 reg_val = rd32(reg_offset); 8091 if (setting) 8092 reg_val |= (BIT(vf) | 8093 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8094 else 8095 reg_val &= ~(BIT(vf) | 8096 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8097 wr32(reg_offset, reg_val); 8098 8099 adapter->vf_data[vf].spoofchk_enabled = setting; 8100 return 0; 8101 } 8102 8103 static int igb_ndo_get_vf_config(struct net_device *netdev, 8104 int vf, struct ifla_vf_info *ivi) 8105 { 8106 struct igb_adapter *adapter = netdev_priv(netdev); 8107 if (vf >= adapter->vfs_allocated_count) 8108 return -EINVAL; 8109 ivi->vf = vf; 8110 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8111 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8112 ivi->min_tx_rate = 0; 8113 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8114 ivi->qos = adapter->vf_data[vf].pf_qos; 8115 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8116 return 0; 8117 } 8118 8119 static void igb_vmm_control(struct igb_adapter *adapter) 8120 { 8121 struct e1000_hw *hw = &adapter->hw; 8122 u32 reg; 8123 8124 switch (hw->mac.type) { 8125 case e1000_82575: 8126 case e1000_i210: 8127 case e1000_i211: 8128 case e1000_i354: 8129 default: 8130 /* replication is not supported for 82575 */ 8131 return; 8132 case e1000_82576: 8133 /* notify HW that the MAC is adding vlan tags */ 8134 reg = rd32(E1000_DTXCTL); 8135 reg |= E1000_DTXCTL_VLAN_ADDED; 8136 wr32(E1000_DTXCTL, reg); 8137 /* Fall through */ 8138 case e1000_82580: 8139 /* enable replication vlan tag stripping */ 8140 reg = rd32(E1000_RPLOLR); 8141 reg |= E1000_RPLOLR_STRVLAN; 8142 wr32(E1000_RPLOLR, reg); 8143 /* Fall through */ 8144 case e1000_i350: 8145 /* none of the above registers are supported by i350 */ 8146 break; 8147 } 8148 8149 if (adapter->vfs_allocated_count) { 8150 igb_vmdq_set_loopback_pf(hw, true); 8151 igb_vmdq_set_replication_pf(hw, true); 8152 igb_vmdq_set_anti_spoofing_pf(hw, true, 8153 adapter->vfs_allocated_count); 8154 } else { 8155 igb_vmdq_set_loopback_pf(hw, false); 8156 igb_vmdq_set_replication_pf(hw, false); 8157 } 8158 } 8159 8160 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8161 { 8162 struct e1000_hw *hw = &adapter->hw; 8163 u32 dmac_thr; 8164 u16 hwm; 8165 8166 if (hw->mac.type > e1000_82580) { 8167 if (adapter->flags & IGB_FLAG_DMAC) { 8168 u32 reg; 8169 8170 /* force threshold to 0. */ 8171 wr32(E1000_DMCTXTH, 0); 8172 8173 /* DMA Coalescing high water mark needs to be greater 8174 * than the Rx threshold. Set hwm to PBA - max frame 8175 * size in 16B units, capping it at PBA - 6KB. 8176 */ 8177 hwm = 64 * (pba - 6); 8178 reg = rd32(E1000_FCRTC); 8179 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8180 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8181 & E1000_FCRTC_RTH_COAL_MASK); 8182 wr32(E1000_FCRTC, reg); 8183 8184 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8185 * frame size, capping it at PBA - 10KB. 8186 */ 8187 dmac_thr = pba - 10; 8188 reg = rd32(E1000_DMACR); 8189 reg &= ~E1000_DMACR_DMACTHR_MASK; 8190 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8191 & E1000_DMACR_DMACTHR_MASK); 8192 8193 /* transition to L0x or L1 if available..*/ 8194 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8195 8196 /* watchdog timer= +-1000 usec in 32usec intervals */ 8197 reg |= (1000 >> 5); 8198 8199 /* Disable BMC-to-OS Watchdog Enable */ 8200 if (hw->mac.type != e1000_i354) 8201 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8202 8203 wr32(E1000_DMACR, reg); 8204 8205 /* no lower threshold to disable 8206 * coalescing(smart fifb)-UTRESH=0 8207 */ 8208 wr32(E1000_DMCRTRH, 0); 8209 8210 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8211 8212 wr32(E1000_DMCTLX, reg); 8213 8214 /* free space in tx packet buffer to wake from 8215 * DMA coal 8216 */ 8217 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8218 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8219 8220 /* make low power state decision controlled 8221 * by DMA coal 8222 */ 8223 reg = rd32(E1000_PCIEMISC); 8224 reg &= ~E1000_PCIEMISC_LX_DECISION; 8225 wr32(E1000_PCIEMISC, reg); 8226 } /* endif adapter->dmac is not disabled */ 8227 } else if (hw->mac.type == e1000_82580) { 8228 u32 reg = rd32(E1000_PCIEMISC); 8229 8230 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8231 wr32(E1000_DMACR, 0); 8232 } 8233 } 8234 8235 /** 8236 * igb_read_i2c_byte - Reads 8 bit word over I2C 8237 * @hw: pointer to hardware structure 8238 * @byte_offset: byte offset to read 8239 * @dev_addr: device address 8240 * @data: value read 8241 * 8242 * Performs byte read operation over I2C interface at 8243 * a specified device address. 8244 **/ 8245 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8246 u8 dev_addr, u8 *data) 8247 { 8248 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8249 struct i2c_client *this_client = adapter->i2c_client; 8250 s32 status; 8251 u16 swfw_mask = 0; 8252 8253 if (!this_client) 8254 return E1000_ERR_I2C; 8255 8256 swfw_mask = E1000_SWFW_PHY0_SM; 8257 8258 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8259 return E1000_ERR_SWFW_SYNC; 8260 8261 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8262 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8263 8264 if (status < 0) 8265 return E1000_ERR_I2C; 8266 else { 8267 *data = status; 8268 return 0; 8269 } 8270 } 8271 8272 /** 8273 * igb_write_i2c_byte - Writes 8 bit word over I2C 8274 * @hw: pointer to hardware structure 8275 * @byte_offset: byte offset to write 8276 * @dev_addr: device address 8277 * @data: value to write 8278 * 8279 * Performs byte write operation over I2C interface at 8280 * a specified device address. 8281 **/ 8282 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8283 u8 dev_addr, u8 data) 8284 { 8285 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8286 struct i2c_client *this_client = adapter->i2c_client; 8287 s32 status; 8288 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8289 8290 if (!this_client) 8291 return E1000_ERR_I2C; 8292 8293 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8294 return E1000_ERR_SWFW_SYNC; 8295 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8296 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8297 8298 if (status) 8299 return E1000_ERR_I2C; 8300 else 8301 return 0; 8302 8303 } 8304 8305 int igb_reinit_queues(struct igb_adapter *adapter) 8306 { 8307 struct net_device *netdev = adapter->netdev; 8308 struct pci_dev *pdev = adapter->pdev; 8309 int err = 0; 8310 8311 if (netif_running(netdev)) 8312 igb_close(netdev); 8313 8314 igb_reset_interrupt_capability(adapter); 8315 8316 if (igb_init_interrupt_scheme(adapter, true)) { 8317 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8318 return -ENOMEM; 8319 } 8320 8321 if (netif_running(netdev)) 8322 err = igb_open(netdev); 8323 8324 return err; 8325 } 8326 8327 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 8328 { 8329 struct igb_nfc_filter *rule; 8330 8331 spin_lock(&adapter->nfc_lock); 8332 8333 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8334 igb_erase_filter(adapter, rule); 8335 8336 spin_unlock(&adapter->nfc_lock); 8337 } 8338 8339 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 8340 { 8341 struct igb_nfc_filter *rule; 8342 8343 spin_lock(&adapter->nfc_lock); 8344 8345 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8346 igb_add_filter(adapter, rule); 8347 8348 spin_unlock(&adapter->nfc_lock); 8349 } 8350 /* igb_main.c */ 8351