1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = struct_size(q_vector, ring, ring_count); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 kfree_rcu(q_vector, rcu); 1206 q_vector = kzalloc(size, GFP_KERNEL); 1207 } else { 1208 memset(q_vector, 0, size); 1209 } 1210 if (!q_vector) 1211 return -ENOMEM; 1212 1213 /* initialize NAPI */ 1214 netif_napi_add(adapter->netdev, &q_vector->napi, 1215 igb_poll, 64); 1216 1217 /* tie q_vector and adapter together */ 1218 adapter->q_vector[v_idx] = q_vector; 1219 q_vector->adapter = adapter; 1220 1221 /* initialize work limits */ 1222 q_vector->tx.work_limit = adapter->tx_work_limit; 1223 1224 /* initialize ITR configuration */ 1225 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1226 q_vector->itr_val = IGB_START_ITR; 1227 1228 /* initialize pointer to rings */ 1229 ring = q_vector->ring; 1230 1231 /* intialize ITR */ 1232 if (rxr_count) { 1233 /* rx or rx/tx vector */ 1234 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1235 q_vector->itr_val = adapter->rx_itr_setting; 1236 } else { 1237 /* tx only vector */ 1238 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1239 q_vector->itr_val = adapter->tx_itr_setting; 1240 } 1241 1242 if (txr_count) { 1243 /* assign generic ring traits */ 1244 ring->dev = &adapter->pdev->dev; 1245 ring->netdev = adapter->netdev; 1246 1247 /* configure backlink on ring */ 1248 ring->q_vector = q_vector; 1249 1250 /* update q_vector Tx values */ 1251 igb_add_ring(ring, &q_vector->tx); 1252 1253 /* For 82575, context index must be unique per ring. */ 1254 if (adapter->hw.mac.type == e1000_82575) 1255 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1256 1257 /* apply Tx specific ring traits */ 1258 ring->count = adapter->tx_ring_count; 1259 ring->queue_index = txr_idx; 1260 1261 ring->cbs_enable = false; 1262 ring->idleslope = 0; 1263 ring->sendslope = 0; 1264 ring->hicredit = 0; 1265 ring->locredit = 0; 1266 1267 u64_stats_init(&ring->tx_syncp); 1268 u64_stats_init(&ring->tx_syncp2); 1269 1270 /* assign ring to adapter */ 1271 adapter->tx_ring[txr_idx] = ring; 1272 1273 /* push pointer to next ring */ 1274 ring++; 1275 } 1276 1277 if (rxr_count) { 1278 /* assign generic ring traits */ 1279 ring->dev = &adapter->pdev->dev; 1280 ring->netdev = adapter->netdev; 1281 1282 /* configure backlink on ring */ 1283 ring->q_vector = q_vector; 1284 1285 /* update q_vector Rx values */ 1286 igb_add_ring(ring, &q_vector->rx); 1287 1288 /* set flag indicating ring supports SCTP checksum offload */ 1289 if (adapter->hw.mac.type >= e1000_82576) 1290 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1291 1292 /* On i350, i354, i210, and i211, loopback VLAN packets 1293 * have the tag byte-swapped. 1294 */ 1295 if (adapter->hw.mac.type >= e1000_i350) 1296 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1297 1298 /* apply Rx specific ring traits */ 1299 ring->count = adapter->rx_ring_count; 1300 ring->queue_index = rxr_idx; 1301 1302 u64_stats_init(&ring->rx_syncp); 1303 1304 /* assign ring to adapter */ 1305 adapter->rx_ring[rxr_idx] = ring; 1306 } 1307 1308 return 0; 1309 } 1310 1311 1312 /** 1313 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1314 * @adapter: board private structure to initialize 1315 * 1316 * We allocate one q_vector per queue interrupt. If allocation fails we 1317 * return -ENOMEM. 1318 **/ 1319 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1320 { 1321 int q_vectors = adapter->num_q_vectors; 1322 int rxr_remaining = adapter->num_rx_queues; 1323 int txr_remaining = adapter->num_tx_queues; 1324 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1325 int err; 1326 1327 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1328 for (; rxr_remaining; v_idx++) { 1329 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1330 0, 0, 1, rxr_idx); 1331 1332 if (err) 1333 goto err_out; 1334 1335 /* update counts and index */ 1336 rxr_remaining--; 1337 rxr_idx++; 1338 } 1339 } 1340 1341 for (; v_idx < q_vectors; v_idx++) { 1342 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1343 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1344 1345 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1346 tqpv, txr_idx, rqpv, rxr_idx); 1347 1348 if (err) 1349 goto err_out; 1350 1351 /* update counts and index */ 1352 rxr_remaining -= rqpv; 1353 txr_remaining -= tqpv; 1354 rxr_idx++; 1355 txr_idx++; 1356 } 1357 1358 return 0; 1359 1360 err_out: 1361 adapter->num_tx_queues = 0; 1362 adapter->num_rx_queues = 0; 1363 adapter->num_q_vectors = 0; 1364 1365 while (v_idx--) 1366 igb_free_q_vector(adapter, v_idx); 1367 1368 return -ENOMEM; 1369 } 1370 1371 /** 1372 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1373 * @adapter: board private structure to initialize 1374 * @msix: boolean value of MSIX capability 1375 * 1376 * This function initializes the interrupts and allocates all of the queues. 1377 **/ 1378 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1379 { 1380 struct pci_dev *pdev = adapter->pdev; 1381 int err; 1382 1383 igb_set_interrupt_capability(adapter, msix); 1384 1385 err = igb_alloc_q_vectors(adapter); 1386 if (err) { 1387 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1388 goto err_alloc_q_vectors; 1389 } 1390 1391 igb_cache_ring_register(adapter); 1392 1393 return 0; 1394 1395 err_alloc_q_vectors: 1396 igb_reset_interrupt_capability(adapter); 1397 return err; 1398 } 1399 1400 /** 1401 * igb_request_irq - initialize interrupts 1402 * @adapter: board private structure to initialize 1403 * 1404 * Attempts to configure interrupts using the best available 1405 * capabilities of the hardware and kernel. 1406 **/ 1407 static int igb_request_irq(struct igb_adapter *adapter) 1408 { 1409 struct net_device *netdev = adapter->netdev; 1410 struct pci_dev *pdev = adapter->pdev; 1411 int err = 0; 1412 1413 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1414 err = igb_request_msix(adapter); 1415 if (!err) 1416 goto request_done; 1417 /* fall back to MSI */ 1418 igb_free_all_tx_resources(adapter); 1419 igb_free_all_rx_resources(adapter); 1420 1421 igb_clear_interrupt_scheme(adapter); 1422 err = igb_init_interrupt_scheme(adapter, false); 1423 if (err) 1424 goto request_done; 1425 1426 igb_setup_all_tx_resources(adapter); 1427 igb_setup_all_rx_resources(adapter); 1428 igb_configure(adapter); 1429 } 1430 1431 igb_assign_vector(adapter->q_vector[0], 0); 1432 1433 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1434 err = request_irq(pdev->irq, igb_intr_msi, 0, 1435 netdev->name, adapter); 1436 if (!err) 1437 goto request_done; 1438 1439 /* fall back to legacy interrupts */ 1440 igb_reset_interrupt_capability(adapter); 1441 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1442 } 1443 1444 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1445 netdev->name, adapter); 1446 1447 if (err) 1448 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1449 err); 1450 1451 request_done: 1452 return err; 1453 } 1454 1455 static void igb_free_irq(struct igb_adapter *adapter) 1456 { 1457 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1458 int vector = 0, i; 1459 1460 free_irq(adapter->msix_entries[vector++].vector, adapter); 1461 1462 for (i = 0; i < adapter->num_q_vectors; i++) 1463 free_irq(adapter->msix_entries[vector++].vector, 1464 adapter->q_vector[i]); 1465 } else { 1466 free_irq(adapter->pdev->irq, adapter); 1467 } 1468 } 1469 1470 /** 1471 * igb_irq_disable - Mask off interrupt generation on the NIC 1472 * @adapter: board private structure 1473 **/ 1474 static void igb_irq_disable(struct igb_adapter *adapter) 1475 { 1476 struct e1000_hw *hw = &adapter->hw; 1477 1478 /* we need to be careful when disabling interrupts. The VFs are also 1479 * mapped into these registers and so clearing the bits can cause 1480 * issues on the VF drivers so we only need to clear what we set 1481 */ 1482 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1483 u32 regval = rd32(E1000_EIAM); 1484 1485 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1486 wr32(E1000_EIMC, adapter->eims_enable_mask); 1487 regval = rd32(E1000_EIAC); 1488 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1489 } 1490 1491 wr32(E1000_IAM, 0); 1492 wr32(E1000_IMC, ~0); 1493 wrfl(); 1494 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1495 int i; 1496 1497 for (i = 0; i < adapter->num_q_vectors; i++) 1498 synchronize_irq(adapter->msix_entries[i].vector); 1499 } else { 1500 synchronize_irq(adapter->pdev->irq); 1501 } 1502 } 1503 1504 /** 1505 * igb_irq_enable - Enable default interrupt generation settings 1506 * @adapter: board private structure 1507 **/ 1508 static void igb_irq_enable(struct igb_adapter *adapter) 1509 { 1510 struct e1000_hw *hw = &adapter->hw; 1511 1512 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1513 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1514 u32 regval = rd32(E1000_EIAC); 1515 1516 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1517 regval = rd32(E1000_EIAM); 1518 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1519 wr32(E1000_EIMS, adapter->eims_enable_mask); 1520 if (adapter->vfs_allocated_count) { 1521 wr32(E1000_MBVFIMR, 0xFF); 1522 ims |= E1000_IMS_VMMB; 1523 } 1524 wr32(E1000_IMS, ims); 1525 } else { 1526 wr32(E1000_IMS, IMS_ENABLE_MASK | 1527 E1000_IMS_DRSTA); 1528 wr32(E1000_IAM, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 } 1531 } 1532 1533 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1534 { 1535 struct e1000_hw *hw = &adapter->hw; 1536 u16 pf_id = adapter->vfs_allocated_count; 1537 u16 vid = adapter->hw.mng_cookie.vlan_id; 1538 u16 old_vid = adapter->mng_vlan_id; 1539 1540 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1541 /* add VID to filter table */ 1542 igb_vfta_set(hw, vid, pf_id, true, true); 1543 adapter->mng_vlan_id = vid; 1544 } else { 1545 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1546 } 1547 1548 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1549 (vid != old_vid) && 1550 !test_bit(old_vid, adapter->active_vlans)) { 1551 /* remove VID from filter table */ 1552 igb_vfta_set(hw, vid, pf_id, false, true); 1553 } 1554 } 1555 1556 /** 1557 * igb_release_hw_control - release control of the h/w to f/w 1558 * @adapter: address of board private structure 1559 * 1560 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1561 * For ASF and Pass Through versions of f/w this means that the 1562 * driver is no longer loaded. 1563 **/ 1564 static void igb_release_hw_control(struct igb_adapter *adapter) 1565 { 1566 struct e1000_hw *hw = &adapter->hw; 1567 u32 ctrl_ext; 1568 1569 /* Let firmware take over control of h/w */ 1570 ctrl_ext = rd32(E1000_CTRL_EXT); 1571 wr32(E1000_CTRL_EXT, 1572 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1573 } 1574 1575 /** 1576 * igb_get_hw_control - get control of the h/w from f/w 1577 * @adapter: address of board private structure 1578 * 1579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1580 * For ASF and Pass Through versions of f/w this means that 1581 * the driver is loaded. 1582 **/ 1583 static void igb_get_hw_control(struct igb_adapter *adapter) 1584 { 1585 struct e1000_hw *hw = &adapter->hw; 1586 u32 ctrl_ext; 1587 1588 /* Let firmware know the driver has taken over */ 1589 ctrl_ext = rd32(E1000_CTRL_EXT); 1590 wr32(E1000_CTRL_EXT, 1591 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1592 } 1593 1594 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1595 { 1596 struct net_device *netdev = adapter->netdev; 1597 struct e1000_hw *hw = &adapter->hw; 1598 1599 WARN_ON(hw->mac.type != e1000_i210); 1600 1601 if (enable) 1602 adapter->flags |= IGB_FLAG_FQTSS; 1603 else 1604 adapter->flags &= ~IGB_FLAG_FQTSS; 1605 1606 if (netif_running(netdev)) 1607 schedule_work(&adapter->reset_task); 1608 } 1609 1610 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1611 { 1612 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1613 } 1614 1615 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1616 enum tx_queue_prio prio) 1617 { 1618 u32 val; 1619 1620 WARN_ON(hw->mac.type != e1000_i210); 1621 WARN_ON(queue < 0 || queue > 4); 1622 1623 val = rd32(E1000_I210_TXDCTL(queue)); 1624 1625 if (prio == TX_QUEUE_PRIO_HIGH) 1626 val |= E1000_TXDCTL_PRIORITY; 1627 else 1628 val &= ~E1000_TXDCTL_PRIORITY; 1629 1630 wr32(E1000_I210_TXDCTL(queue), val); 1631 } 1632 1633 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1634 { 1635 u32 val; 1636 1637 WARN_ON(hw->mac.type != e1000_i210); 1638 WARN_ON(queue < 0 || queue > 1); 1639 1640 val = rd32(E1000_I210_TQAVCC(queue)); 1641 1642 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1643 val |= E1000_TQAVCC_QUEUEMODE; 1644 else 1645 val &= ~E1000_TQAVCC_QUEUEMODE; 1646 1647 wr32(E1000_I210_TQAVCC(queue), val); 1648 } 1649 1650 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1651 { 1652 int i; 1653 1654 for (i = 0; i < adapter->num_tx_queues; i++) { 1655 if (adapter->tx_ring[i]->cbs_enable) 1656 return true; 1657 } 1658 1659 return false; 1660 } 1661 1662 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1663 { 1664 int i; 1665 1666 for (i = 0; i < adapter->num_tx_queues; i++) { 1667 if (adapter->tx_ring[i]->launchtime_enable) 1668 return true; 1669 } 1670 1671 return false; 1672 } 1673 1674 /** 1675 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1676 * @adapter: pointer to adapter struct 1677 * @queue: queue number 1678 * 1679 * Configure CBS and Launchtime for a given hardware queue. 1680 * Parameters are retrieved from the correct Tx ring, so 1681 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1682 * for setting those correctly prior to this function being called. 1683 **/ 1684 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1685 { 1686 struct net_device *netdev = adapter->netdev; 1687 struct e1000_hw *hw = &adapter->hw; 1688 struct igb_ring *ring; 1689 u32 tqavcc, tqavctrl; 1690 u16 value; 1691 1692 WARN_ON(hw->mac.type != e1000_i210); 1693 WARN_ON(queue < 0 || queue > 1); 1694 ring = adapter->tx_ring[queue]; 1695 1696 /* If any of the Qav features is enabled, configure queues as SR and 1697 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1698 * as SP. 1699 */ 1700 if (ring->cbs_enable || ring->launchtime_enable) { 1701 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1702 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1703 } else { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1706 } 1707 1708 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1709 if (ring->cbs_enable || queue == 0) { 1710 /* i210 does not allow the queue 0 to be in the Strict 1711 * Priority mode while the Qav mode is enabled, so, 1712 * instead of disabling strict priority mode, we give 1713 * queue 0 the maximum of credits possible. 1714 * 1715 * See section 8.12.19 of the i210 datasheet, "Note: 1716 * Queue0 QueueMode must be set to 1b when 1717 * TransmitMode is set to Qav." 1718 */ 1719 if (queue == 0 && !ring->cbs_enable) { 1720 /* max "linkspeed" idleslope in kbps */ 1721 ring->idleslope = 1000000; 1722 ring->hicredit = ETH_FRAME_LEN; 1723 } 1724 1725 /* Always set data transfer arbitration to credit-based 1726 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1727 * the queues. 1728 */ 1729 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1730 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1731 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1732 1733 /* According to i210 datasheet section 7.2.7.7, we should set 1734 * the 'idleSlope' field from TQAVCC register following the 1735 * equation: 1736 * 1737 * For 100 Mbps link speed: 1738 * 1739 * value = BW * 0x7735 * 0.2 (E1) 1740 * 1741 * For 1000Mbps link speed: 1742 * 1743 * value = BW * 0x7735 * 2 (E2) 1744 * 1745 * E1 and E2 can be merged into one equation as shown below. 1746 * Note that 'link-speed' is in Mbps. 1747 * 1748 * value = BW * 0x7735 * 2 * link-speed 1749 * -------------- (E3) 1750 * 1000 1751 * 1752 * 'BW' is the percentage bandwidth out of full link speed 1753 * which can be found with the following equation. Note that 1754 * idleSlope here is the parameter from this function which 1755 * is in kbps. 1756 * 1757 * BW = idleSlope 1758 * ----------------- (E4) 1759 * link-speed * 1000 1760 * 1761 * That said, we can come up with a generic equation to 1762 * calculate the value we should set it TQAVCC register by 1763 * replacing 'BW' in E3 by E4. The resulting equation is: 1764 * 1765 * value = idleSlope * 0x7735 * 2 * link-speed 1766 * ----------------- -------------- (E5) 1767 * link-speed * 1000 1000 1768 * 1769 * 'link-speed' is present in both sides of the fraction so 1770 * it is canceled out. The final equation is the following: 1771 * 1772 * value = idleSlope * 61034 1773 * ----------------- (E6) 1774 * 1000000 1775 * 1776 * NOTE: For i210, given the above, we can see that idleslope 1777 * is represented in 16.38431 kbps units by the value at 1778 * the TQAVCC register (1Gbps / 61034), which reduces 1779 * the granularity for idleslope increments. 1780 * For instance, if you want to configure a 2576kbps 1781 * idleslope, the value to be written on the register 1782 * would have to be 157.23. If rounded down, you end 1783 * up with less bandwidth available than originally 1784 * required (~2572 kbps). If rounded up, you end up 1785 * with a higher bandwidth (~2589 kbps). Below the 1786 * approach we take is to always round up the 1787 * calculated value, so the resulting bandwidth might 1788 * be slightly higher for some configurations. 1789 */ 1790 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1791 1792 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1793 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1794 tqavcc |= value; 1795 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1796 1797 wr32(E1000_I210_TQAVHC(queue), 1798 0x80000000 + ring->hicredit * 0x7735); 1799 } else { 1800 1801 /* Set idleSlope to zero. */ 1802 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1803 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1804 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1805 1806 /* Set hiCredit to zero. */ 1807 wr32(E1000_I210_TQAVHC(queue), 0); 1808 1809 /* If CBS is not enabled for any queues anymore, then return to 1810 * the default state of Data Transmission Arbitration on 1811 * TQAVCTRL. 1812 */ 1813 if (!is_any_cbs_enabled(adapter)) { 1814 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1815 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1816 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1817 } 1818 } 1819 1820 /* If LaunchTime is enabled, set DataTranTIM. */ 1821 if (ring->launchtime_enable) { 1822 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1823 * for any of the SR queues, and configure fetchtime delta. 1824 * XXX NOTE: 1825 * - LaunchTime will be enabled for all SR queues. 1826 * - A fixed offset can be added relative to the launch 1827 * time of all packets if configured at reg LAUNCH_OS0. 1828 * We are keeping it as 0 for now (default value). 1829 */ 1830 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1831 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1832 E1000_TQAVCTRL_FETCHTIME_DELTA; 1833 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1834 } else { 1835 /* If Launchtime is not enabled for any SR queues anymore, 1836 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1837 * effectively disabling Launchtime. 1838 */ 1839 if (!is_any_txtime_enabled(adapter)) { 1840 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1841 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1842 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1843 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1844 } 1845 } 1846 1847 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1848 * CBS are not configurable by software so we don't do any 'controller 1849 * configuration' in respect to these parameters. 1850 */ 1851 1852 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1853 ring->cbs_enable ? "enabled" : "disabled", 1854 ring->launchtime_enable ? "enabled" : "disabled", 1855 queue, 1856 ring->idleslope, ring->sendslope, 1857 ring->hicredit, ring->locredit); 1858 } 1859 1860 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1861 bool enable) 1862 { 1863 struct igb_ring *ring; 1864 1865 if (queue < 0 || queue > adapter->num_tx_queues) 1866 return -EINVAL; 1867 1868 ring = adapter->tx_ring[queue]; 1869 ring->launchtime_enable = enable; 1870 1871 return 0; 1872 } 1873 1874 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1875 bool enable, int idleslope, int sendslope, 1876 int hicredit, int locredit) 1877 { 1878 struct igb_ring *ring; 1879 1880 if (queue < 0 || queue > adapter->num_tx_queues) 1881 return -EINVAL; 1882 1883 ring = adapter->tx_ring[queue]; 1884 1885 ring->cbs_enable = enable; 1886 ring->idleslope = idleslope; 1887 ring->sendslope = sendslope; 1888 ring->hicredit = hicredit; 1889 ring->locredit = locredit; 1890 1891 return 0; 1892 } 1893 1894 /** 1895 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1896 * @adapter: pointer to adapter struct 1897 * 1898 * Configure TQAVCTRL register switching the controller's Tx mode 1899 * if FQTSS mode is enabled or disabled. Additionally, will issue 1900 * a call to igb_config_tx_modes() per queue so any previously saved 1901 * Tx parameters are applied. 1902 **/ 1903 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1904 { 1905 struct net_device *netdev = adapter->netdev; 1906 struct e1000_hw *hw = &adapter->hw; 1907 u32 val; 1908 1909 /* Only i210 controller supports changing the transmission mode. */ 1910 if (hw->mac.type != e1000_i210) 1911 return; 1912 1913 if (is_fqtss_enabled(adapter)) { 1914 int i, max_queue; 1915 1916 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1917 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1918 * so SP queues wait for SR ones. 1919 */ 1920 val = rd32(E1000_I210_TQAVCTRL); 1921 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1922 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1923 wr32(E1000_I210_TQAVCTRL, val); 1924 1925 /* Configure Tx and Rx packet buffers sizes as described in 1926 * i210 datasheet section 7.2.7.7. 1927 */ 1928 val = rd32(E1000_TXPBS); 1929 val &= ~I210_TXPBSIZE_MASK; 1930 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1931 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1932 wr32(E1000_TXPBS, val); 1933 1934 val = rd32(E1000_RXPBS); 1935 val &= ~I210_RXPBSIZE_MASK; 1936 val |= I210_RXPBSIZE_PB_30KB; 1937 wr32(E1000_RXPBS, val); 1938 1939 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1940 * register should not exceed the buffer size programmed in 1941 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1942 * so according to the datasheet we should set MAX_TPKT_SIZE to 1943 * 4kB / 64. 1944 * 1945 * However, when we do so, no frame from queue 2 and 3 are 1946 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1947 * or _equal_ to the buffer size programmed in TXPBS. For this 1948 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1949 */ 1950 val = (4096 - 1) / 64; 1951 wr32(E1000_I210_DTXMXPKTSZ, val); 1952 1953 /* Since FQTSS mode is enabled, apply any CBS configuration 1954 * previously set. If no previous CBS configuration has been 1955 * done, then the initial configuration is applied, which means 1956 * CBS is disabled. 1957 */ 1958 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1959 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1960 1961 for (i = 0; i < max_queue; i++) { 1962 igb_config_tx_modes(adapter, i); 1963 } 1964 } else { 1965 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1966 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1967 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1968 1969 val = rd32(E1000_I210_TQAVCTRL); 1970 /* According to Section 8.12.21, the other flags we've set when 1971 * enabling FQTSS are not relevant when disabling FQTSS so we 1972 * don't set they here. 1973 */ 1974 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1975 wr32(E1000_I210_TQAVCTRL, val); 1976 } 1977 1978 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1979 "enabled" : "disabled"); 1980 } 1981 1982 /** 1983 * igb_configure - configure the hardware for RX and TX 1984 * @adapter: private board structure 1985 **/ 1986 static void igb_configure(struct igb_adapter *adapter) 1987 { 1988 struct net_device *netdev = adapter->netdev; 1989 int i; 1990 1991 igb_get_hw_control(adapter); 1992 igb_set_rx_mode(netdev); 1993 igb_setup_tx_mode(adapter); 1994 1995 igb_restore_vlan(adapter); 1996 1997 igb_setup_tctl(adapter); 1998 igb_setup_mrqc(adapter); 1999 igb_setup_rctl(adapter); 2000 2001 igb_nfc_filter_restore(adapter); 2002 igb_configure_tx(adapter); 2003 igb_configure_rx(adapter); 2004 2005 igb_rx_fifo_flush_82575(&adapter->hw); 2006 2007 /* call igb_desc_unused which always leaves 2008 * at least 1 descriptor unused to make sure 2009 * next_to_use != next_to_clean 2010 */ 2011 for (i = 0; i < adapter->num_rx_queues; i++) { 2012 struct igb_ring *ring = adapter->rx_ring[i]; 2013 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2014 } 2015 } 2016 2017 /** 2018 * igb_power_up_link - Power up the phy/serdes link 2019 * @adapter: address of board private structure 2020 **/ 2021 void igb_power_up_link(struct igb_adapter *adapter) 2022 { 2023 igb_reset_phy(&adapter->hw); 2024 2025 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2026 igb_power_up_phy_copper(&adapter->hw); 2027 else 2028 igb_power_up_serdes_link_82575(&adapter->hw); 2029 2030 igb_setup_link(&adapter->hw); 2031 } 2032 2033 /** 2034 * igb_power_down_link - Power down the phy/serdes link 2035 * @adapter: address of board private structure 2036 */ 2037 static void igb_power_down_link(struct igb_adapter *adapter) 2038 { 2039 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2040 igb_power_down_phy_copper_82575(&adapter->hw); 2041 else 2042 igb_shutdown_serdes_link_82575(&adapter->hw); 2043 } 2044 2045 /** 2046 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2047 * @adapter: address of the board private structure 2048 **/ 2049 static void igb_check_swap_media(struct igb_adapter *adapter) 2050 { 2051 struct e1000_hw *hw = &adapter->hw; 2052 u32 ctrl_ext, connsw; 2053 bool swap_now = false; 2054 2055 ctrl_ext = rd32(E1000_CTRL_EXT); 2056 connsw = rd32(E1000_CONNSW); 2057 2058 /* need to live swap if current media is copper and we have fiber/serdes 2059 * to go to. 2060 */ 2061 2062 if ((hw->phy.media_type == e1000_media_type_copper) && 2063 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2064 swap_now = true; 2065 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2066 !(connsw & E1000_CONNSW_SERDESD)) { 2067 /* copper signal takes time to appear */ 2068 if (adapter->copper_tries < 4) { 2069 adapter->copper_tries++; 2070 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2071 wr32(E1000_CONNSW, connsw); 2072 return; 2073 } else { 2074 adapter->copper_tries = 0; 2075 if ((connsw & E1000_CONNSW_PHYSD) && 2076 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2077 swap_now = true; 2078 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2079 wr32(E1000_CONNSW, connsw); 2080 } 2081 } 2082 } 2083 2084 if (!swap_now) 2085 return; 2086 2087 switch (hw->phy.media_type) { 2088 case e1000_media_type_copper: 2089 netdev_info(adapter->netdev, 2090 "MAS: changing media to fiber/serdes\n"); 2091 ctrl_ext |= 2092 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2093 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2094 adapter->copper_tries = 0; 2095 break; 2096 case e1000_media_type_internal_serdes: 2097 case e1000_media_type_fiber: 2098 netdev_info(adapter->netdev, 2099 "MAS: changing media to copper\n"); 2100 ctrl_ext &= 2101 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2102 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2103 break; 2104 default: 2105 /* shouldn't get here during regular operation */ 2106 netdev_err(adapter->netdev, 2107 "AMS: Invalid media type found, returning\n"); 2108 break; 2109 } 2110 wr32(E1000_CTRL_EXT, ctrl_ext); 2111 } 2112 2113 /** 2114 * igb_up - Open the interface and prepare it to handle traffic 2115 * @adapter: board private structure 2116 **/ 2117 int igb_up(struct igb_adapter *adapter) 2118 { 2119 struct e1000_hw *hw = &adapter->hw; 2120 int i; 2121 2122 /* hardware has been reset, we need to reload some things */ 2123 igb_configure(adapter); 2124 2125 clear_bit(__IGB_DOWN, &adapter->state); 2126 2127 for (i = 0; i < adapter->num_q_vectors; i++) 2128 napi_enable(&(adapter->q_vector[i]->napi)); 2129 2130 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2131 igb_configure_msix(adapter); 2132 else 2133 igb_assign_vector(adapter->q_vector[0], 0); 2134 2135 /* Clear any pending interrupts. */ 2136 rd32(E1000_TSICR); 2137 rd32(E1000_ICR); 2138 igb_irq_enable(adapter); 2139 2140 /* notify VFs that reset has been completed */ 2141 if (adapter->vfs_allocated_count) { 2142 u32 reg_data = rd32(E1000_CTRL_EXT); 2143 2144 reg_data |= E1000_CTRL_EXT_PFRSTD; 2145 wr32(E1000_CTRL_EXT, reg_data); 2146 } 2147 2148 netif_tx_start_all_queues(adapter->netdev); 2149 2150 /* start the watchdog. */ 2151 hw->mac.get_link_status = 1; 2152 schedule_work(&adapter->watchdog_task); 2153 2154 if ((adapter->flags & IGB_FLAG_EEE) && 2155 (!hw->dev_spec._82575.eee_disable)) 2156 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2157 2158 return 0; 2159 } 2160 2161 void igb_down(struct igb_adapter *adapter) 2162 { 2163 struct net_device *netdev = adapter->netdev; 2164 struct e1000_hw *hw = &adapter->hw; 2165 u32 tctl, rctl; 2166 int i; 2167 2168 /* signal that we're down so the interrupt handler does not 2169 * reschedule our watchdog timer 2170 */ 2171 set_bit(__IGB_DOWN, &adapter->state); 2172 2173 /* disable receives in the hardware */ 2174 rctl = rd32(E1000_RCTL); 2175 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2176 /* flush and sleep below */ 2177 2178 igb_nfc_filter_exit(adapter); 2179 2180 netif_carrier_off(netdev); 2181 netif_tx_stop_all_queues(netdev); 2182 2183 /* disable transmits in the hardware */ 2184 tctl = rd32(E1000_TCTL); 2185 tctl &= ~E1000_TCTL_EN; 2186 wr32(E1000_TCTL, tctl); 2187 /* flush both disables and wait for them to finish */ 2188 wrfl(); 2189 usleep_range(10000, 11000); 2190 2191 igb_irq_disable(adapter); 2192 2193 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2194 2195 for (i = 0; i < adapter->num_q_vectors; i++) { 2196 if (adapter->q_vector[i]) { 2197 napi_synchronize(&adapter->q_vector[i]->napi); 2198 napi_disable(&adapter->q_vector[i]->napi); 2199 } 2200 } 2201 2202 del_timer_sync(&adapter->watchdog_timer); 2203 del_timer_sync(&adapter->phy_info_timer); 2204 2205 /* record the stats before reset*/ 2206 spin_lock(&adapter->stats64_lock); 2207 igb_update_stats(adapter); 2208 spin_unlock(&adapter->stats64_lock); 2209 2210 adapter->link_speed = 0; 2211 adapter->link_duplex = 0; 2212 2213 if (!pci_channel_offline(adapter->pdev)) 2214 igb_reset(adapter); 2215 2216 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2217 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2218 2219 igb_clean_all_tx_rings(adapter); 2220 igb_clean_all_rx_rings(adapter); 2221 #ifdef CONFIG_IGB_DCA 2222 2223 /* since we reset the hardware DCA settings were cleared */ 2224 igb_setup_dca(adapter); 2225 #endif 2226 } 2227 2228 void igb_reinit_locked(struct igb_adapter *adapter) 2229 { 2230 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2231 usleep_range(1000, 2000); 2232 igb_down(adapter); 2233 igb_up(adapter); 2234 clear_bit(__IGB_RESETTING, &adapter->state); 2235 } 2236 2237 /** igb_enable_mas - Media Autosense re-enable after swap 2238 * 2239 * @adapter: adapter struct 2240 **/ 2241 static void igb_enable_mas(struct igb_adapter *adapter) 2242 { 2243 struct e1000_hw *hw = &adapter->hw; 2244 u32 connsw = rd32(E1000_CONNSW); 2245 2246 /* configure for SerDes media detect */ 2247 if ((hw->phy.media_type == e1000_media_type_copper) && 2248 (!(connsw & E1000_CONNSW_SERDESD))) { 2249 connsw |= E1000_CONNSW_ENRGSRC; 2250 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2251 wr32(E1000_CONNSW, connsw); 2252 wrfl(); 2253 } 2254 } 2255 2256 void igb_reset(struct igb_adapter *adapter) 2257 { 2258 struct pci_dev *pdev = adapter->pdev; 2259 struct e1000_hw *hw = &adapter->hw; 2260 struct e1000_mac_info *mac = &hw->mac; 2261 struct e1000_fc_info *fc = &hw->fc; 2262 u32 pba, hwm; 2263 2264 /* Repartition Pba for greater than 9k mtu 2265 * To take effect CTRL.RST is required. 2266 */ 2267 switch (mac->type) { 2268 case e1000_i350: 2269 case e1000_i354: 2270 case e1000_82580: 2271 pba = rd32(E1000_RXPBS); 2272 pba = igb_rxpbs_adjust_82580(pba); 2273 break; 2274 case e1000_82576: 2275 pba = rd32(E1000_RXPBS); 2276 pba &= E1000_RXPBS_SIZE_MASK_82576; 2277 break; 2278 case e1000_82575: 2279 case e1000_i210: 2280 case e1000_i211: 2281 default: 2282 pba = E1000_PBA_34K; 2283 break; 2284 } 2285 2286 if (mac->type == e1000_82575) { 2287 u32 min_rx_space, min_tx_space, needed_tx_space; 2288 2289 /* write Rx PBA so that hardware can report correct Tx PBA */ 2290 wr32(E1000_PBA, pba); 2291 2292 /* To maintain wire speed transmits, the Tx FIFO should be 2293 * large enough to accommodate two full transmit packets, 2294 * rounded up to the next 1KB and expressed in KB. Likewise, 2295 * the Rx FIFO should be large enough to accommodate at least 2296 * one full receive packet and is similarly rounded up and 2297 * expressed in KB. 2298 */ 2299 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2300 2301 /* The Tx FIFO also stores 16 bytes of information about the Tx 2302 * but don't include Ethernet FCS because hardware appends it. 2303 * We only need to round down to the nearest 512 byte block 2304 * count since the value we care about is 2 frames, not 1. 2305 */ 2306 min_tx_space = adapter->max_frame_size; 2307 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2308 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2309 2310 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2311 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2312 2313 /* If current Tx allocation is less than the min Tx FIFO size, 2314 * and the min Tx FIFO size is less than the current Rx FIFO 2315 * allocation, take space away from current Rx allocation. 2316 */ 2317 if (needed_tx_space < pba) { 2318 pba -= needed_tx_space; 2319 2320 /* if short on Rx space, Rx wins and must trump Tx 2321 * adjustment 2322 */ 2323 if (pba < min_rx_space) 2324 pba = min_rx_space; 2325 } 2326 2327 /* adjust PBA for jumbo frames */ 2328 wr32(E1000_PBA, pba); 2329 } 2330 2331 /* flow control settings 2332 * The high water mark must be low enough to fit one full frame 2333 * after transmitting the pause frame. As such we must have enough 2334 * space to allow for us to complete our current transmit and then 2335 * receive the frame that is in progress from the link partner. 2336 * Set it to: 2337 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2338 */ 2339 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2340 2341 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2342 fc->low_water = fc->high_water - 16; 2343 fc->pause_time = 0xFFFF; 2344 fc->send_xon = 1; 2345 fc->current_mode = fc->requested_mode; 2346 2347 /* disable receive for all VFs and wait one second */ 2348 if (adapter->vfs_allocated_count) { 2349 int i; 2350 2351 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2352 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2353 2354 /* ping all the active vfs to let them know we are going down */ 2355 igb_ping_all_vfs(adapter); 2356 2357 /* disable transmits and receives */ 2358 wr32(E1000_VFRE, 0); 2359 wr32(E1000_VFTE, 0); 2360 } 2361 2362 /* Allow time for pending master requests to run */ 2363 hw->mac.ops.reset_hw(hw); 2364 wr32(E1000_WUC, 0); 2365 2366 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2367 /* need to resetup here after media swap */ 2368 adapter->ei.get_invariants(hw); 2369 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2370 } 2371 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2372 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2373 igb_enable_mas(adapter); 2374 } 2375 if (hw->mac.ops.init_hw(hw)) 2376 dev_err(&pdev->dev, "Hardware Error\n"); 2377 2378 /* RAR registers were cleared during init_hw, clear mac table */ 2379 igb_flush_mac_table(adapter); 2380 __dev_uc_unsync(adapter->netdev, NULL); 2381 2382 /* Recover default RAR entry */ 2383 igb_set_default_mac_filter(adapter); 2384 2385 /* Flow control settings reset on hardware reset, so guarantee flow 2386 * control is off when forcing speed. 2387 */ 2388 if (!hw->mac.autoneg) 2389 igb_force_mac_fc(hw); 2390 2391 igb_init_dmac(adapter, pba); 2392 #ifdef CONFIG_IGB_HWMON 2393 /* Re-initialize the thermal sensor on i350 devices. */ 2394 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2395 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2396 /* If present, re-initialize the external thermal sensor 2397 * interface. 2398 */ 2399 if (adapter->ets) 2400 mac->ops.init_thermal_sensor_thresh(hw); 2401 } 2402 } 2403 #endif 2404 /* Re-establish EEE setting */ 2405 if (hw->phy.media_type == e1000_media_type_copper) { 2406 switch (mac->type) { 2407 case e1000_i350: 2408 case e1000_i210: 2409 case e1000_i211: 2410 igb_set_eee_i350(hw, true, true); 2411 break; 2412 case e1000_i354: 2413 igb_set_eee_i354(hw, true, true); 2414 break; 2415 default: 2416 break; 2417 } 2418 } 2419 if (!netif_running(adapter->netdev)) 2420 igb_power_down_link(adapter); 2421 2422 igb_update_mng_vlan(adapter); 2423 2424 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2425 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2426 2427 /* Re-enable PTP, where applicable. */ 2428 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2429 igb_ptp_reset(adapter); 2430 2431 igb_get_phy_info(hw); 2432 } 2433 2434 static netdev_features_t igb_fix_features(struct net_device *netdev, 2435 netdev_features_t features) 2436 { 2437 /* Since there is no support for separate Rx/Tx vlan accel 2438 * enable/disable make sure Tx flag is always in same state as Rx. 2439 */ 2440 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2441 features |= NETIF_F_HW_VLAN_CTAG_TX; 2442 else 2443 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2444 2445 return features; 2446 } 2447 2448 static int igb_set_features(struct net_device *netdev, 2449 netdev_features_t features) 2450 { 2451 netdev_features_t changed = netdev->features ^ features; 2452 struct igb_adapter *adapter = netdev_priv(netdev); 2453 2454 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2455 igb_vlan_mode(netdev, features); 2456 2457 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2458 return 0; 2459 2460 if (!(features & NETIF_F_NTUPLE)) { 2461 struct hlist_node *node2; 2462 struct igb_nfc_filter *rule; 2463 2464 spin_lock(&adapter->nfc_lock); 2465 hlist_for_each_entry_safe(rule, node2, 2466 &adapter->nfc_filter_list, nfc_node) { 2467 igb_erase_filter(adapter, rule); 2468 hlist_del(&rule->nfc_node); 2469 kfree(rule); 2470 } 2471 spin_unlock(&adapter->nfc_lock); 2472 adapter->nfc_filter_count = 0; 2473 } 2474 2475 netdev->features = features; 2476 2477 if (netif_running(netdev)) 2478 igb_reinit_locked(adapter); 2479 else 2480 igb_reset(adapter); 2481 2482 return 1; 2483 } 2484 2485 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2486 struct net_device *dev, 2487 const unsigned char *addr, u16 vid, 2488 u16 flags, 2489 struct netlink_ext_ack *extack) 2490 { 2491 /* guarantee we can provide a unique filter for the unicast address */ 2492 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2493 struct igb_adapter *adapter = netdev_priv(dev); 2494 int vfn = adapter->vfs_allocated_count; 2495 2496 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2497 return -ENOMEM; 2498 } 2499 2500 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2501 } 2502 2503 #define IGB_MAX_MAC_HDR_LEN 127 2504 #define IGB_MAX_NETWORK_HDR_LEN 511 2505 2506 static netdev_features_t 2507 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2508 netdev_features_t features) 2509 { 2510 unsigned int network_hdr_len, mac_hdr_len; 2511 2512 /* Make certain the headers can be described by a context descriptor */ 2513 mac_hdr_len = skb_network_header(skb) - skb->data; 2514 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2515 return features & ~(NETIF_F_HW_CSUM | 2516 NETIF_F_SCTP_CRC | 2517 NETIF_F_GSO_UDP_L4 | 2518 NETIF_F_HW_VLAN_CTAG_TX | 2519 NETIF_F_TSO | 2520 NETIF_F_TSO6); 2521 2522 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2523 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2524 return features & ~(NETIF_F_HW_CSUM | 2525 NETIF_F_SCTP_CRC | 2526 NETIF_F_GSO_UDP_L4 | 2527 NETIF_F_TSO | 2528 NETIF_F_TSO6); 2529 2530 /* We can only support IPV4 TSO in tunnels if we can mangle the 2531 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2532 */ 2533 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2534 features &= ~NETIF_F_TSO; 2535 2536 return features; 2537 } 2538 2539 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2540 { 2541 if (!is_fqtss_enabled(adapter)) { 2542 enable_fqtss(adapter, true); 2543 return; 2544 } 2545 2546 igb_config_tx_modes(adapter, queue); 2547 2548 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2549 enable_fqtss(adapter, false); 2550 } 2551 2552 static int igb_offload_cbs(struct igb_adapter *adapter, 2553 struct tc_cbs_qopt_offload *qopt) 2554 { 2555 struct e1000_hw *hw = &adapter->hw; 2556 int err; 2557 2558 /* CBS offloading is only supported by i210 controller. */ 2559 if (hw->mac.type != e1000_i210) 2560 return -EOPNOTSUPP; 2561 2562 /* CBS offloading is only supported by queue 0 and queue 1. */ 2563 if (qopt->queue < 0 || qopt->queue > 1) 2564 return -EINVAL; 2565 2566 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2567 qopt->idleslope, qopt->sendslope, 2568 qopt->hicredit, qopt->locredit); 2569 if (err) 2570 return err; 2571 2572 igb_offload_apply(adapter, qopt->queue); 2573 2574 return 0; 2575 } 2576 2577 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2578 #define VLAN_PRIO_FULL_MASK (0x07) 2579 2580 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2581 struct flow_cls_offload *f, 2582 int traffic_class, 2583 struct igb_nfc_filter *input) 2584 { 2585 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2586 struct flow_dissector *dissector = rule->match.dissector; 2587 struct netlink_ext_ack *extack = f->common.extack; 2588 2589 if (dissector->used_keys & 2590 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2591 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2592 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2593 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2594 NL_SET_ERR_MSG_MOD(extack, 2595 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2600 struct flow_match_eth_addrs match; 2601 2602 flow_rule_match_eth_addrs(rule, &match); 2603 if (!is_zero_ether_addr(match.mask->dst)) { 2604 if (!is_broadcast_ether_addr(match.mask->dst)) { 2605 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2606 return -EINVAL; 2607 } 2608 2609 input->filter.match_flags |= 2610 IGB_FILTER_FLAG_DST_MAC_ADDR; 2611 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2612 } 2613 2614 if (!is_zero_ether_addr(match.mask->src)) { 2615 if (!is_broadcast_ether_addr(match.mask->src)) { 2616 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2617 return -EINVAL; 2618 } 2619 2620 input->filter.match_flags |= 2621 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2622 ether_addr_copy(input->filter.src_addr, match.key->src); 2623 } 2624 } 2625 2626 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2627 struct flow_match_basic match; 2628 2629 flow_rule_match_basic(rule, &match); 2630 if (match.mask->n_proto) { 2631 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2632 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2633 return -EINVAL; 2634 } 2635 2636 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2637 input->filter.etype = match.key->n_proto; 2638 } 2639 } 2640 2641 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2642 struct flow_match_vlan match; 2643 2644 flow_rule_match_vlan(rule, &match); 2645 if (match.mask->vlan_priority) { 2646 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2647 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2648 return -EINVAL; 2649 } 2650 2651 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2652 input->filter.vlan_tci = 2653 (__force __be16)match.key->vlan_priority; 2654 } 2655 } 2656 2657 input->action = traffic_class; 2658 input->cookie = f->cookie; 2659 2660 return 0; 2661 } 2662 2663 static int igb_configure_clsflower(struct igb_adapter *adapter, 2664 struct flow_cls_offload *cls_flower) 2665 { 2666 struct netlink_ext_ack *extack = cls_flower->common.extack; 2667 struct igb_nfc_filter *filter, *f; 2668 int err, tc; 2669 2670 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2671 if (tc < 0) { 2672 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2673 return -EINVAL; 2674 } 2675 2676 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2677 if (!filter) 2678 return -ENOMEM; 2679 2680 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2681 if (err < 0) 2682 goto err_parse; 2683 2684 spin_lock(&adapter->nfc_lock); 2685 2686 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2687 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2688 err = -EEXIST; 2689 NL_SET_ERR_MSG_MOD(extack, 2690 "This filter is already set in ethtool"); 2691 goto err_locked; 2692 } 2693 } 2694 2695 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2696 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2697 err = -EEXIST; 2698 NL_SET_ERR_MSG_MOD(extack, 2699 "This filter is already set in cls_flower"); 2700 goto err_locked; 2701 } 2702 } 2703 2704 err = igb_add_filter(adapter, filter); 2705 if (err < 0) { 2706 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2707 goto err_locked; 2708 } 2709 2710 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2711 2712 spin_unlock(&adapter->nfc_lock); 2713 2714 return 0; 2715 2716 err_locked: 2717 spin_unlock(&adapter->nfc_lock); 2718 2719 err_parse: 2720 kfree(filter); 2721 2722 return err; 2723 } 2724 2725 static int igb_delete_clsflower(struct igb_adapter *adapter, 2726 struct flow_cls_offload *cls_flower) 2727 { 2728 struct igb_nfc_filter *filter; 2729 int err; 2730 2731 spin_lock(&adapter->nfc_lock); 2732 2733 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2734 if (filter->cookie == cls_flower->cookie) 2735 break; 2736 2737 if (!filter) { 2738 err = -ENOENT; 2739 goto out; 2740 } 2741 2742 err = igb_erase_filter(adapter, filter); 2743 if (err < 0) 2744 goto out; 2745 2746 hlist_del(&filter->nfc_node); 2747 kfree(filter); 2748 2749 out: 2750 spin_unlock(&adapter->nfc_lock); 2751 2752 return err; 2753 } 2754 2755 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2756 struct flow_cls_offload *cls_flower) 2757 { 2758 switch (cls_flower->command) { 2759 case FLOW_CLS_REPLACE: 2760 return igb_configure_clsflower(adapter, cls_flower); 2761 case FLOW_CLS_DESTROY: 2762 return igb_delete_clsflower(adapter, cls_flower); 2763 case FLOW_CLS_STATS: 2764 return -EOPNOTSUPP; 2765 default: 2766 return -EOPNOTSUPP; 2767 } 2768 } 2769 2770 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2771 void *cb_priv) 2772 { 2773 struct igb_adapter *adapter = cb_priv; 2774 2775 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2776 return -EOPNOTSUPP; 2777 2778 switch (type) { 2779 case TC_SETUP_CLSFLOWER: 2780 return igb_setup_tc_cls_flower(adapter, type_data); 2781 2782 default: 2783 return -EOPNOTSUPP; 2784 } 2785 } 2786 2787 static int igb_offload_txtime(struct igb_adapter *adapter, 2788 struct tc_etf_qopt_offload *qopt) 2789 { 2790 struct e1000_hw *hw = &adapter->hw; 2791 int err; 2792 2793 /* Launchtime offloading is only supported by i210 controller. */ 2794 if (hw->mac.type != e1000_i210) 2795 return -EOPNOTSUPP; 2796 2797 /* Launchtime offloading is only supported by queues 0 and 1. */ 2798 if (qopt->queue < 0 || qopt->queue > 1) 2799 return -EINVAL; 2800 2801 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2802 if (err) 2803 return err; 2804 2805 igb_offload_apply(adapter, qopt->queue); 2806 2807 return 0; 2808 } 2809 2810 static LIST_HEAD(igb_block_cb_list); 2811 2812 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2813 void *type_data) 2814 { 2815 struct igb_adapter *adapter = netdev_priv(dev); 2816 2817 switch (type) { 2818 case TC_SETUP_QDISC_CBS: 2819 return igb_offload_cbs(adapter, type_data); 2820 case TC_SETUP_BLOCK: 2821 return flow_block_cb_setup_simple(type_data, 2822 &igb_block_cb_list, 2823 igb_setup_tc_block_cb, 2824 adapter, adapter, true); 2825 2826 case TC_SETUP_QDISC_ETF: 2827 return igb_offload_txtime(adapter, type_data); 2828 2829 default: 2830 return -EOPNOTSUPP; 2831 } 2832 } 2833 2834 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2835 { 2836 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2837 struct igb_adapter *adapter = netdev_priv(dev); 2838 struct bpf_prog *prog = bpf->prog, *old_prog; 2839 bool running = netif_running(dev); 2840 bool need_reset; 2841 2842 /* verify igb ring attributes are sufficient for XDP */ 2843 for (i = 0; i < adapter->num_rx_queues; i++) { 2844 struct igb_ring *ring = adapter->rx_ring[i]; 2845 2846 if (frame_size > igb_rx_bufsz(ring)) { 2847 NL_SET_ERR_MSG_MOD(bpf->extack, 2848 "The RX buffer size is too small for the frame size"); 2849 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2850 igb_rx_bufsz(ring), frame_size); 2851 return -EINVAL; 2852 } 2853 } 2854 2855 old_prog = xchg(&adapter->xdp_prog, prog); 2856 need_reset = (!!prog != !!old_prog); 2857 2858 /* device is up and bpf is added/removed, must setup the RX queues */ 2859 if (need_reset && running) { 2860 igb_close(dev); 2861 } else { 2862 for (i = 0; i < adapter->num_rx_queues; i++) 2863 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2864 adapter->xdp_prog); 2865 } 2866 2867 if (old_prog) 2868 bpf_prog_put(old_prog); 2869 2870 /* bpf is just replaced, RXQ and MTU are already setup */ 2871 if (!need_reset) 2872 return 0; 2873 2874 if (running) 2875 igb_open(dev); 2876 2877 return 0; 2878 } 2879 2880 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2881 { 2882 switch (xdp->command) { 2883 case XDP_SETUP_PROG: 2884 return igb_xdp_setup(dev, xdp); 2885 default: 2886 return -EINVAL; 2887 } 2888 } 2889 2890 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2891 { 2892 /* Force memory writes to complete before letting h/w know there 2893 * are new descriptors to fetch. 2894 */ 2895 wmb(); 2896 writel(ring->next_to_use, ring->tail); 2897 } 2898 2899 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2900 { 2901 unsigned int r_idx = smp_processor_id(); 2902 2903 if (r_idx >= adapter->num_tx_queues) 2904 r_idx = r_idx % adapter->num_tx_queues; 2905 2906 return adapter->tx_ring[r_idx]; 2907 } 2908 2909 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2910 { 2911 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2912 int cpu = smp_processor_id(); 2913 struct igb_ring *tx_ring; 2914 struct netdev_queue *nq; 2915 u32 ret; 2916 2917 if (unlikely(!xdpf)) 2918 return IGB_XDP_CONSUMED; 2919 2920 /* During program transitions its possible adapter->xdp_prog is assigned 2921 * but ring has not been configured yet. In this case simply abort xmit. 2922 */ 2923 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2924 if (unlikely(!tx_ring)) 2925 return IGB_XDP_CONSUMED; 2926 2927 nq = txring_txq(tx_ring); 2928 __netif_tx_lock(nq, cpu); 2929 /* Avoid transmit queue timeout since we share it with the slow path */ 2930 txq_trans_cond_update(nq); 2931 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2932 __netif_tx_unlock(nq); 2933 2934 return ret; 2935 } 2936 2937 static int igb_xdp_xmit(struct net_device *dev, int n, 2938 struct xdp_frame **frames, u32 flags) 2939 { 2940 struct igb_adapter *adapter = netdev_priv(dev); 2941 int cpu = smp_processor_id(); 2942 struct igb_ring *tx_ring; 2943 struct netdev_queue *nq; 2944 int nxmit = 0; 2945 int i; 2946 2947 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2948 return -ENETDOWN; 2949 2950 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2951 return -EINVAL; 2952 2953 /* During program transitions its possible adapter->xdp_prog is assigned 2954 * but ring has not been configured yet. In this case simply abort xmit. 2955 */ 2956 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2957 if (unlikely(!tx_ring)) 2958 return -ENXIO; 2959 2960 nq = txring_txq(tx_ring); 2961 __netif_tx_lock(nq, cpu); 2962 2963 /* Avoid transmit queue timeout since we share it with the slow path */ 2964 txq_trans_cond_update(nq); 2965 2966 for (i = 0; i < n; i++) { 2967 struct xdp_frame *xdpf = frames[i]; 2968 int err; 2969 2970 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2971 if (err != IGB_XDP_TX) 2972 break; 2973 nxmit++; 2974 } 2975 2976 __netif_tx_unlock(nq); 2977 2978 if (unlikely(flags & XDP_XMIT_FLUSH)) 2979 igb_xdp_ring_update_tail(tx_ring); 2980 2981 return nxmit; 2982 } 2983 2984 static const struct net_device_ops igb_netdev_ops = { 2985 .ndo_open = igb_open, 2986 .ndo_stop = igb_close, 2987 .ndo_start_xmit = igb_xmit_frame, 2988 .ndo_get_stats64 = igb_get_stats64, 2989 .ndo_set_rx_mode = igb_set_rx_mode, 2990 .ndo_set_mac_address = igb_set_mac, 2991 .ndo_change_mtu = igb_change_mtu, 2992 .ndo_eth_ioctl = igb_ioctl, 2993 .ndo_tx_timeout = igb_tx_timeout, 2994 .ndo_validate_addr = eth_validate_addr, 2995 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2996 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2997 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2998 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2999 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3000 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3001 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3002 .ndo_get_vf_config = igb_ndo_get_vf_config, 3003 .ndo_fix_features = igb_fix_features, 3004 .ndo_set_features = igb_set_features, 3005 .ndo_fdb_add = igb_ndo_fdb_add, 3006 .ndo_features_check = igb_features_check, 3007 .ndo_setup_tc = igb_setup_tc, 3008 .ndo_bpf = igb_xdp, 3009 .ndo_xdp_xmit = igb_xdp_xmit, 3010 }; 3011 3012 /** 3013 * igb_set_fw_version - Configure version string for ethtool 3014 * @adapter: adapter struct 3015 **/ 3016 void igb_set_fw_version(struct igb_adapter *adapter) 3017 { 3018 struct e1000_hw *hw = &adapter->hw; 3019 struct e1000_fw_version fw; 3020 3021 igb_get_fw_version(hw, &fw); 3022 3023 switch (hw->mac.type) { 3024 case e1000_i210: 3025 case e1000_i211: 3026 if (!(igb_get_flash_presence_i210(hw))) { 3027 snprintf(adapter->fw_version, 3028 sizeof(adapter->fw_version), 3029 "%2d.%2d-%d", 3030 fw.invm_major, fw.invm_minor, 3031 fw.invm_img_type); 3032 break; 3033 } 3034 fallthrough; 3035 default: 3036 /* if option is rom valid, display its version too */ 3037 if (fw.or_valid) { 3038 snprintf(adapter->fw_version, 3039 sizeof(adapter->fw_version), 3040 "%d.%d, 0x%08x, %d.%d.%d", 3041 fw.eep_major, fw.eep_minor, fw.etrack_id, 3042 fw.or_major, fw.or_build, fw.or_patch); 3043 /* no option rom */ 3044 } else if (fw.etrack_id != 0X0000) { 3045 snprintf(adapter->fw_version, 3046 sizeof(adapter->fw_version), 3047 "%d.%d, 0x%08x", 3048 fw.eep_major, fw.eep_minor, fw.etrack_id); 3049 } else { 3050 snprintf(adapter->fw_version, 3051 sizeof(adapter->fw_version), 3052 "%d.%d.%d", 3053 fw.eep_major, fw.eep_minor, fw.eep_build); 3054 } 3055 break; 3056 } 3057 } 3058 3059 /** 3060 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3061 * 3062 * @adapter: adapter struct 3063 **/ 3064 static void igb_init_mas(struct igb_adapter *adapter) 3065 { 3066 struct e1000_hw *hw = &adapter->hw; 3067 u16 eeprom_data; 3068 3069 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3070 switch (hw->bus.func) { 3071 case E1000_FUNC_0: 3072 if (eeprom_data & IGB_MAS_ENABLE_0) { 3073 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3074 netdev_info(adapter->netdev, 3075 "MAS: Enabling Media Autosense for port %d\n", 3076 hw->bus.func); 3077 } 3078 break; 3079 case E1000_FUNC_1: 3080 if (eeprom_data & IGB_MAS_ENABLE_1) { 3081 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3082 netdev_info(adapter->netdev, 3083 "MAS: Enabling Media Autosense for port %d\n", 3084 hw->bus.func); 3085 } 3086 break; 3087 case E1000_FUNC_2: 3088 if (eeprom_data & IGB_MAS_ENABLE_2) { 3089 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3090 netdev_info(adapter->netdev, 3091 "MAS: Enabling Media Autosense for port %d\n", 3092 hw->bus.func); 3093 } 3094 break; 3095 case E1000_FUNC_3: 3096 if (eeprom_data & IGB_MAS_ENABLE_3) { 3097 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3098 netdev_info(adapter->netdev, 3099 "MAS: Enabling Media Autosense for port %d\n", 3100 hw->bus.func); 3101 } 3102 break; 3103 default: 3104 /* Shouldn't get here */ 3105 netdev_err(adapter->netdev, 3106 "MAS: Invalid port configuration, returning\n"); 3107 break; 3108 } 3109 } 3110 3111 /** 3112 * igb_init_i2c - Init I2C interface 3113 * @adapter: pointer to adapter structure 3114 **/ 3115 static s32 igb_init_i2c(struct igb_adapter *adapter) 3116 { 3117 struct e1000_hw *hw = &adapter->hw; 3118 s32 status = 0; 3119 s32 i2cctl; 3120 3121 /* I2C interface supported on i350 devices */ 3122 if (adapter->hw.mac.type != e1000_i350) 3123 return 0; 3124 3125 i2cctl = rd32(E1000_I2CPARAMS); 3126 i2cctl |= E1000_I2CBB_EN 3127 | E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N 3128 | E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 3129 wr32(E1000_I2CPARAMS, i2cctl); 3130 wrfl(); 3131 3132 /* Initialize the i2c bus which is controlled by the registers. 3133 * This bus will use the i2c_algo_bit structure that implements 3134 * the protocol through toggling of the 4 bits in the register. 3135 */ 3136 adapter->i2c_adap.owner = THIS_MODULE; 3137 adapter->i2c_algo = igb_i2c_algo; 3138 adapter->i2c_algo.data = adapter; 3139 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3140 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3141 strlcpy(adapter->i2c_adap.name, "igb BB", 3142 sizeof(adapter->i2c_adap.name)); 3143 status = i2c_bit_add_bus(&adapter->i2c_adap); 3144 return status; 3145 } 3146 3147 /** 3148 * igb_probe - Device Initialization Routine 3149 * @pdev: PCI device information struct 3150 * @ent: entry in igb_pci_tbl 3151 * 3152 * Returns 0 on success, negative on failure 3153 * 3154 * igb_probe initializes an adapter identified by a pci_dev structure. 3155 * The OS initialization, configuring of the adapter private structure, 3156 * and a hardware reset occur. 3157 **/ 3158 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3159 { 3160 struct net_device *netdev; 3161 struct igb_adapter *adapter; 3162 struct e1000_hw *hw; 3163 u16 eeprom_data = 0; 3164 s32 ret_val; 3165 static int global_quad_port_a; /* global quad port a indication */ 3166 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3167 u8 part_str[E1000_PBANUM_LENGTH]; 3168 int err; 3169 3170 /* Catch broken hardware that put the wrong VF device ID in 3171 * the PCIe SR-IOV capability. 3172 */ 3173 if (pdev->is_virtfn) { 3174 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3175 pci_name(pdev), pdev->vendor, pdev->device); 3176 return -EINVAL; 3177 } 3178 3179 err = pci_enable_device_mem(pdev); 3180 if (err) 3181 return err; 3182 3183 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3184 if (err) { 3185 dev_err(&pdev->dev, 3186 "No usable DMA configuration, aborting\n"); 3187 goto err_dma; 3188 } 3189 3190 err = pci_request_mem_regions(pdev, igb_driver_name); 3191 if (err) 3192 goto err_pci_reg; 3193 3194 pci_enable_pcie_error_reporting(pdev); 3195 3196 pci_set_master(pdev); 3197 pci_save_state(pdev); 3198 3199 err = -ENOMEM; 3200 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3201 IGB_MAX_TX_QUEUES); 3202 if (!netdev) 3203 goto err_alloc_etherdev; 3204 3205 SET_NETDEV_DEV(netdev, &pdev->dev); 3206 3207 pci_set_drvdata(pdev, netdev); 3208 adapter = netdev_priv(netdev); 3209 adapter->netdev = netdev; 3210 adapter->pdev = pdev; 3211 hw = &adapter->hw; 3212 hw->back = adapter; 3213 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3214 3215 err = -EIO; 3216 adapter->io_addr = pci_iomap(pdev, 0, 0); 3217 if (!adapter->io_addr) 3218 goto err_ioremap; 3219 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3220 hw->hw_addr = adapter->io_addr; 3221 3222 netdev->netdev_ops = &igb_netdev_ops; 3223 igb_set_ethtool_ops(netdev); 3224 netdev->watchdog_timeo = 5 * HZ; 3225 3226 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3227 3228 netdev->mem_start = pci_resource_start(pdev, 0); 3229 netdev->mem_end = pci_resource_end(pdev, 0); 3230 3231 /* PCI config space info */ 3232 hw->vendor_id = pdev->vendor; 3233 hw->device_id = pdev->device; 3234 hw->revision_id = pdev->revision; 3235 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3236 hw->subsystem_device_id = pdev->subsystem_device; 3237 3238 /* Copy the default MAC, PHY and NVM function pointers */ 3239 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3240 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3241 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3242 /* Initialize skew-specific constants */ 3243 err = ei->get_invariants(hw); 3244 if (err) 3245 goto err_sw_init; 3246 3247 /* setup the private structure */ 3248 err = igb_sw_init(adapter); 3249 if (err) 3250 goto err_sw_init; 3251 3252 igb_get_bus_info_pcie(hw); 3253 3254 hw->phy.autoneg_wait_to_complete = false; 3255 3256 /* Copper options */ 3257 if (hw->phy.media_type == e1000_media_type_copper) { 3258 hw->phy.mdix = AUTO_ALL_MODES; 3259 hw->phy.disable_polarity_correction = false; 3260 hw->phy.ms_type = e1000_ms_hw_default; 3261 } 3262 3263 if (igb_check_reset_block(hw)) 3264 dev_info(&pdev->dev, 3265 "PHY reset is blocked due to SOL/IDER session.\n"); 3266 3267 /* features is initialized to 0 in allocation, it might have bits 3268 * set by igb_sw_init so we should use an or instead of an 3269 * assignment. 3270 */ 3271 netdev->features |= NETIF_F_SG | 3272 NETIF_F_TSO | 3273 NETIF_F_TSO6 | 3274 NETIF_F_RXHASH | 3275 NETIF_F_RXCSUM | 3276 NETIF_F_HW_CSUM; 3277 3278 if (hw->mac.type >= e1000_82576) 3279 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3280 3281 if (hw->mac.type >= e1000_i350) 3282 netdev->features |= NETIF_F_HW_TC; 3283 3284 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3285 NETIF_F_GSO_GRE_CSUM | \ 3286 NETIF_F_GSO_IPXIP4 | \ 3287 NETIF_F_GSO_IPXIP6 | \ 3288 NETIF_F_GSO_UDP_TUNNEL | \ 3289 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3290 3291 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3292 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3293 3294 /* copy netdev features into list of user selectable features */ 3295 netdev->hw_features |= netdev->features | 3296 NETIF_F_HW_VLAN_CTAG_RX | 3297 NETIF_F_HW_VLAN_CTAG_TX | 3298 NETIF_F_RXALL; 3299 3300 if (hw->mac.type >= e1000_i350) 3301 netdev->hw_features |= NETIF_F_NTUPLE; 3302 3303 netdev->features |= NETIF_F_HIGHDMA; 3304 3305 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3306 netdev->mpls_features |= NETIF_F_HW_CSUM; 3307 netdev->hw_enc_features |= netdev->vlan_features; 3308 3309 /* set this bit last since it cannot be part of vlan_features */ 3310 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3311 NETIF_F_HW_VLAN_CTAG_RX | 3312 NETIF_F_HW_VLAN_CTAG_TX; 3313 3314 netdev->priv_flags |= IFF_SUPP_NOFCS; 3315 3316 netdev->priv_flags |= IFF_UNICAST_FLT; 3317 3318 /* MTU range: 68 - 9216 */ 3319 netdev->min_mtu = ETH_MIN_MTU; 3320 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3321 3322 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3323 3324 /* before reading the NVM, reset the controller to put the device in a 3325 * known good starting state 3326 */ 3327 hw->mac.ops.reset_hw(hw); 3328 3329 /* make sure the NVM is good , i211/i210 parts can have special NVM 3330 * that doesn't contain a checksum 3331 */ 3332 switch (hw->mac.type) { 3333 case e1000_i210: 3334 case e1000_i211: 3335 if (igb_get_flash_presence_i210(hw)) { 3336 if (hw->nvm.ops.validate(hw) < 0) { 3337 dev_err(&pdev->dev, 3338 "The NVM Checksum Is Not Valid\n"); 3339 err = -EIO; 3340 goto err_eeprom; 3341 } 3342 } 3343 break; 3344 default: 3345 if (hw->nvm.ops.validate(hw) < 0) { 3346 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3347 err = -EIO; 3348 goto err_eeprom; 3349 } 3350 break; 3351 } 3352 3353 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3354 /* copy the MAC address out of the NVM */ 3355 if (hw->mac.ops.read_mac_addr(hw)) 3356 dev_err(&pdev->dev, "NVM Read Error\n"); 3357 } 3358 3359 eth_hw_addr_set(netdev, hw->mac.addr); 3360 3361 if (!is_valid_ether_addr(netdev->dev_addr)) { 3362 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3363 err = -EIO; 3364 goto err_eeprom; 3365 } 3366 3367 igb_set_default_mac_filter(adapter); 3368 3369 /* get firmware version for ethtool -i */ 3370 igb_set_fw_version(adapter); 3371 3372 /* configure RXPBSIZE and TXPBSIZE */ 3373 if (hw->mac.type == e1000_i210) { 3374 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3375 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3376 } 3377 3378 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3379 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3380 3381 INIT_WORK(&adapter->reset_task, igb_reset_task); 3382 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3383 3384 /* Initialize link properties that are user-changeable */ 3385 adapter->fc_autoneg = true; 3386 hw->mac.autoneg = true; 3387 hw->phy.autoneg_advertised = 0x2f; 3388 3389 hw->fc.requested_mode = e1000_fc_default; 3390 hw->fc.current_mode = e1000_fc_default; 3391 3392 igb_validate_mdi_setting(hw); 3393 3394 /* By default, support wake on port A */ 3395 if (hw->bus.func == 0) 3396 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3397 3398 /* Check the NVM for wake support on non-port A ports */ 3399 if (hw->mac.type >= e1000_82580) 3400 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3401 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3402 &eeprom_data); 3403 else if (hw->bus.func == 1) 3404 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3405 3406 if (eeprom_data & IGB_EEPROM_APME) 3407 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3408 3409 /* now that we have the eeprom settings, apply the special cases where 3410 * the eeprom may be wrong or the board simply won't support wake on 3411 * lan on a particular port 3412 */ 3413 switch (pdev->device) { 3414 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3415 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3416 break; 3417 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3418 case E1000_DEV_ID_82576_FIBER: 3419 case E1000_DEV_ID_82576_SERDES: 3420 /* Wake events only supported on port A for dual fiber 3421 * regardless of eeprom setting 3422 */ 3423 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3424 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3425 break; 3426 case E1000_DEV_ID_82576_QUAD_COPPER: 3427 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3428 /* if quad port adapter, disable WoL on all but port A */ 3429 if (global_quad_port_a != 0) 3430 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3431 else 3432 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3433 /* Reset for multiple quad port adapters */ 3434 if (++global_quad_port_a == 4) 3435 global_quad_port_a = 0; 3436 break; 3437 default: 3438 /* If the device can't wake, don't set software support */ 3439 if (!device_can_wakeup(&adapter->pdev->dev)) 3440 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3441 } 3442 3443 /* initialize the wol settings based on the eeprom settings */ 3444 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3445 adapter->wol |= E1000_WUFC_MAG; 3446 3447 /* Some vendors want WoL disabled by default, but still supported */ 3448 if ((hw->mac.type == e1000_i350) && 3449 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3450 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3451 adapter->wol = 0; 3452 } 3453 3454 /* Some vendors want the ability to Use the EEPROM setting as 3455 * enable/disable only, and not for capability 3456 */ 3457 if (((hw->mac.type == e1000_i350) || 3458 (hw->mac.type == e1000_i354)) && 3459 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3461 adapter->wol = 0; 3462 } 3463 if (hw->mac.type == e1000_i350) { 3464 if (((pdev->subsystem_device == 0x5001) || 3465 (pdev->subsystem_device == 0x5002)) && 3466 (hw->bus.func == 0)) { 3467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3468 adapter->wol = 0; 3469 } 3470 if (pdev->subsystem_device == 0x1F52) 3471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3472 } 3473 3474 device_set_wakeup_enable(&adapter->pdev->dev, 3475 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3476 3477 /* reset the hardware with the new settings */ 3478 igb_reset(adapter); 3479 3480 /* Init the I2C interface */ 3481 err = igb_init_i2c(adapter); 3482 if (err) { 3483 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3484 goto err_eeprom; 3485 } 3486 3487 /* let the f/w know that the h/w is now under the control of the 3488 * driver. 3489 */ 3490 igb_get_hw_control(adapter); 3491 3492 strcpy(netdev->name, "eth%d"); 3493 err = register_netdev(netdev); 3494 if (err) 3495 goto err_register; 3496 3497 /* carrier off reporting is important to ethtool even BEFORE open */ 3498 netif_carrier_off(netdev); 3499 3500 #ifdef CONFIG_IGB_DCA 3501 if (dca_add_requester(&pdev->dev) == 0) { 3502 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3503 dev_info(&pdev->dev, "DCA enabled\n"); 3504 igb_setup_dca(adapter); 3505 } 3506 3507 #endif 3508 #ifdef CONFIG_IGB_HWMON 3509 /* Initialize the thermal sensor on i350 devices. */ 3510 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3511 u16 ets_word; 3512 3513 /* Read the NVM to determine if this i350 device supports an 3514 * external thermal sensor. 3515 */ 3516 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3517 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3518 adapter->ets = true; 3519 else 3520 adapter->ets = false; 3521 if (igb_sysfs_init(adapter)) 3522 dev_err(&pdev->dev, 3523 "failed to allocate sysfs resources\n"); 3524 } else { 3525 adapter->ets = false; 3526 } 3527 #endif 3528 /* Check if Media Autosense is enabled */ 3529 adapter->ei = *ei; 3530 if (hw->dev_spec._82575.mas_capable) 3531 igb_init_mas(adapter); 3532 3533 /* do hw tstamp init after resetting */ 3534 igb_ptp_init(adapter); 3535 3536 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3537 /* print bus type/speed/width info, not applicable to i354 */ 3538 if (hw->mac.type != e1000_i354) { 3539 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3540 netdev->name, 3541 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3542 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3543 "unknown"), 3544 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3545 "Width x4" : 3546 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3547 "Width x2" : 3548 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3549 "Width x1" : "unknown"), netdev->dev_addr); 3550 } 3551 3552 if ((hw->mac.type == e1000_82576 && 3553 rd32(E1000_EECD) & E1000_EECD_PRES) || 3554 (hw->mac.type >= e1000_i210 || 3555 igb_get_flash_presence_i210(hw))) { 3556 ret_val = igb_read_part_string(hw, part_str, 3557 E1000_PBANUM_LENGTH); 3558 } else { 3559 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3560 } 3561 3562 if (ret_val) 3563 strcpy(part_str, "Unknown"); 3564 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3565 dev_info(&pdev->dev, 3566 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3567 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3568 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3569 adapter->num_rx_queues, adapter->num_tx_queues); 3570 if (hw->phy.media_type == e1000_media_type_copper) { 3571 switch (hw->mac.type) { 3572 case e1000_i350: 3573 case e1000_i210: 3574 case e1000_i211: 3575 /* Enable EEE for internal copper PHY devices */ 3576 err = igb_set_eee_i350(hw, true, true); 3577 if ((!err) && 3578 (!hw->dev_spec._82575.eee_disable)) { 3579 adapter->eee_advert = 3580 MDIO_EEE_100TX | MDIO_EEE_1000T; 3581 adapter->flags |= IGB_FLAG_EEE; 3582 } 3583 break; 3584 case e1000_i354: 3585 if ((rd32(E1000_CTRL_EXT) & 3586 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3587 err = igb_set_eee_i354(hw, true, true); 3588 if ((!err) && 3589 (!hw->dev_spec._82575.eee_disable)) { 3590 adapter->eee_advert = 3591 MDIO_EEE_100TX | MDIO_EEE_1000T; 3592 adapter->flags |= IGB_FLAG_EEE; 3593 } 3594 } 3595 break; 3596 default: 3597 break; 3598 } 3599 } 3600 3601 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3602 3603 pm_runtime_put_noidle(&pdev->dev); 3604 return 0; 3605 3606 err_register: 3607 igb_release_hw_control(adapter); 3608 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3609 err_eeprom: 3610 if (!igb_check_reset_block(hw)) 3611 igb_reset_phy(hw); 3612 3613 if (hw->flash_address) 3614 iounmap(hw->flash_address); 3615 err_sw_init: 3616 kfree(adapter->mac_table); 3617 kfree(adapter->shadow_vfta); 3618 igb_clear_interrupt_scheme(adapter); 3619 #ifdef CONFIG_PCI_IOV 3620 igb_disable_sriov(pdev); 3621 #endif 3622 pci_iounmap(pdev, adapter->io_addr); 3623 err_ioremap: 3624 free_netdev(netdev); 3625 err_alloc_etherdev: 3626 pci_disable_pcie_error_reporting(pdev); 3627 pci_release_mem_regions(pdev); 3628 err_pci_reg: 3629 err_dma: 3630 pci_disable_device(pdev); 3631 return err; 3632 } 3633 3634 #ifdef CONFIG_PCI_IOV 3635 static int igb_disable_sriov(struct pci_dev *pdev) 3636 { 3637 struct net_device *netdev = pci_get_drvdata(pdev); 3638 struct igb_adapter *adapter = netdev_priv(netdev); 3639 struct e1000_hw *hw = &adapter->hw; 3640 3641 /* reclaim resources allocated to VFs */ 3642 if (adapter->vf_data) { 3643 /* disable iov and allow time for transactions to clear */ 3644 if (pci_vfs_assigned(pdev)) { 3645 dev_warn(&pdev->dev, 3646 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3647 return -EPERM; 3648 } else { 3649 pci_disable_sriov(pdev); 3650 msleep(500); 3651 } 3652 3653 kfree(adapter->vf_mac_list); 3654 adapter->vf_mac_list = NULL; 3655 kfree(adapter->vf_data); 3656 adapter->vf_data = NULL; 3657 adapter->vfs_allocated_count = 0; 3658 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3659 wrfl(); 3660 msleep(100); 3661 dev_info(&pdev->dev, "IOV Disabled\n"); 3662 3663 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3664 adapter->flags |= IGB_FLAG_DMAC; 3665 } 3666 3667 return 0; 3668 } 3669 3670 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3671 { 3672 struct net_device *netdev = pci_get_drvdata(pdev); 3673 struct igb_adapter *adapter = netdev_priv(netdev); 3674 int old_vfs = pci_num_vf(pdev); 3675 struct vf_mac_filter *mac_list; 3676 int err = 0; 3677 int num_vf_mac_filters, i; 3678 3679 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3680 err = -EPERM; 3681 goto out; 3682 } 3683 if (!num_vfs) 3684 goto out; 3685 3686 if (old_vfs) { 3687 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3688 old_vfs, max_vfs); 3689 adapter->vfs_allocated_count = old_vfs; 3690 } else 3691 adapter->vfs_allocated_count = num_vfs; 3692 3693 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3694 sizeof(struct vf_data_storage), GFP_KERNEL); 3695 3696 /* if allocation failed then we do not support SR-IOV */ 3697 if (!adapter->vf_data) { 3698 adapter->vfs_allocated_count = 0; 3699 err = -ENOMEM; 3700 goto out; 3701 } 3702 3703 /* Due to the limited number of RAR entries calculate potential 3704 * number of MAC filters available for the VFs. Reserve entries 3705 * for PF default MAC, PF MAC filters and at least one RAR entry 3706 * for each VF for VF MAC. 3707 */ 3708 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3709 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3710 adapter->vfs_allocated_count); 3711 3712 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3713 sizeof(struct vf_mac_filter), 3714 GFP_KERNEL); 3715 3716 mac_list = adapter->vf_mac_list; 3717 INIT_LIST_HEAD(&adapter->vf_macs.l); 3718 3719 if (adapter->vf_mac_list) { 3720 /* Initialize list of VF MAC filters */ 3721 for (i = 0; i < num_vf_mac_filters; i++) { 3722 mac_list->vf = -1; 3723 mac_list->free = true; 3724 list_add(&mac_list->l, &adapter->vf_macs.l); 3725 mac_list++; 3726 } 3727 } else { 3728 /* If we could not allocate memory for the VF MAC filters 3729 * we can continue without this feature but warn user. 3730 */ 3731 dev_err(&pdev->dev, 3732 "Unable to allocate memory for VF MAC filter list\n"); 3733 } 3734 3735 /* only call pci_enable_sriov() if no VFs are allocated already */ 3736 if (!old_vfs) { 3737 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3738 if (err) 3739 goto err_out; 3740 } 3741 dev_info(&pdev->dev, "%d VFs allocated\n", 3742 adapter->vfs_allocated_count); 3743 for (i = 0; i < adapter->vfs_allocated_count; i++) 3744 igb_vf_configure(adapter, i); 3745 3746 /* DMA Coalescing is not supported in IOV mode. */ 3747 adapter->flags &= ~IGB_FLAG_DMAC; 3748 goto out; 3749 3750 err_out: 3751 kfree(adapter->vf_mac_list); 3752 adapter->vf_mac_list = NULL; 3753 kfree(adapter->vf_data); 3754 adapter->vf_data = NULL; 3755 adapter->vfs_allocated_count = 0; 3756 out: 3757 return err; 3758 } 3759 3760 #endif 3761 /** 3762 * igb_remove_i2c - Cleanup I2C interface 3763 * @adapter: pointer to adapter structure 3764 **/ 3765 static void igb_remove_i2c(struct igb_adapter *adapter) 3766 { 3767 /* free the adapter bus structure */ 3768 i2c_del_adapter(&adapter->i2c_adap); 3769 } 3770 3771 /** 3772 * igb_remove - Device Removal Routine 3773 * @pdev: PCI device information struct 3774 * 3775 * igb_remove is called by the PCI subsystem to alert the driver 3776 * that it should release a PCI device. The could be caused by a 3777 * Hot-Plug event, or because the driver is going to be removed from 3778 * memory. 3779 **/ 3780 static void igb_remove(struct pci_dev *pdev) 3781 { 3782 struct net_device *netdev = pci_get_drvdata(pdev); 3783 struct igb_adapter *adapter = netdev_priv(netdev); 3784 struct e1000_hw *hw = &adapter->hw; 3785 3786 pm_runtime_get_noresume(&pdev->dev); 3787 #ifdef CONFIG_IGB_HWMON 3788 igb_sysfs_exit(adapter); 3789 #endif 3790 igb_remove_i2c(adapter); 3791 igb_ptp_stop(adapter); 3792 /* The watchdog timer may be rescheduled, so explicitly 3793 * disable watchdog from being rescheduled. 3794 */ 3795 set_bit(__IGB_DOWN, &adapter->state); 3796 del_timer_sync(&adapter->watchdog_timer); 3797 del_timer_sync(&adapter->phy_info_timer); 3798 3799 cancel_work_sync(&adapter->reset_task); 3800 cancel_work_sync(&adapter->watchdog_task); 3801 3802 #ifdef CONFIG_IGB_DCA 3803 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3804 dev_info(&pdev->dev, "DCA disabled\n"); 3805 dca_remove_requester(&pdev->dev); 3806 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3807 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3808 } 3809 #endif 3810 3811 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3812 * would have already happened in close and is redundant. 3813 */ 3814 igb_release_hw_control(adapter); 3815 3816 #ifdef CONFIG_PCI_IOV 3817 igb_disable_sriov(pdev); 3818 #endif 3819 3820 unregister_netdev(netdev); 3821 3822 igb_clear_interrupt_scheme(adapter); 3823 3824 pci_iounmap(pdev, adapter->io_addr); 3825 if (hw->flash_address) 3826 iounmap(hw->flash_address); 3827 pci_release_mem_regions(pdev); 3828 3829 kfree(adapter->mac_table); 3830 kfree(adapter->shadow_vfta); 3831 free_netdev(netdev); 3832 3833 pci_disable_pcie_error_reporting(pdev); 3834 3835 pci_disable_device(pdev); 3836 } 3837 3838 /** 3839 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3840 * @adapter: board private structure to initialize 3841 * 3842 * This function initializes the vf specific data storage and then attempts to 3843 * allocate the VFs. The reason for ordering it this way is because it is much 3844 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3845 * the memory for the VFs. 3846 **/ 3847 static void igb_probe_vfs(struct igb_adapter *adapter) 3848 { 3849 #ifdef CONFIG_PCI_IOV 3850 struct pci_dev *pdev = adapter->pdev; 3851 struct e1000_hw *hw = &adapter->hw; 3852 3853 /* Virtualization features not supported on i210 family. */ 3854 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3855 return; 3856 3857 /* Of the below we really only want the effect of getting 3858 * IGB_FLAG_HAS_MSIX set (if available), without which 3859 * igb_enable_sriov() has no effect. 3860 */ 3861 igb_set_interrupt_capability(adapter, true); 3862 igb_reset_interrupt_capability(adapter); 3863 3864 pci_sriov_set_totalvfs(pdev, 7); 3865 igb_enable_sriov(pdev, max_vfs); 3866 3867 #endif /* CONFIG_PCI_IOV */ 3868 } 3869 3870 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3871 { 3872 struct e1000_hw *hw = &adapter->hw; 3873 unsigned int max_rss_queues; 3874 3875 /* Determine the maximum number of RSS queues supported. */ 3876 switch (hw->mac.type) { 3877 case e1000_i211: 3878 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3879 break; 3880 case e1000_82575: 3881 case e1000_i210: 3882 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3883 break; 3884 case e1000_i350: 3885 /* I350 cannot do RSS and SR-IOV at the same time */ 3886 if (!!adapter->vfs_allocated_count) { 3887 max_rss_queues = 1; 3888 break; 3889 } 3890 fallthrough; 3891 case e1000_82576: 3892 if (!!adapter->vfs_allocated_count) { 3893 max_rss_queues = 2; 3894 break; 3895 } 3896 fallthrough; 3897 case e1000_82580: 3898 case e1000_i354: 3899 default: 3900 max_rss_queues = IGB_MAX_RX_QUEUES; 3901 break; 3902 } 3903 3904 return max_rss_queues; 3905 } 3906 3907 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3908 { 3909 u32 max_rss_queues; 3910 3911 max_rss_queues = igb_get_max_rss_queues(adapter); 3912 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3913 3914 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3915 } 3916 3917 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3918 const u32 max_rss_queues) 3919 { 3920 struct e1000_hw *hw = &adapter->hw; 3921 3922 /* Determine if we need to pair queues. */ 3923 switch (hw->mac.type) { 3924 case e1000_82575: 3925 case e1000_i211: 3926 /* Device supports enough interrupts without queue pairing. */ 3927 break; 3928 case e1000_82576: 3929 case e1000_82580: 3930 case e1000_i350: 3931 case e1000_i354: 3932 case e1000_i210: 3933 default: 3934 /* If rss_queues > half of max_rss_queues, pair the queues in 3935 * order to conserve interrupts due to limited supply. 3936 */ 3937 if (adapter->rss_queues > (max_rss_queues / 2)) 3938 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3939 else 3940 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3941 break; 3942 } 3943 } 3944 3945 /** 3946 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3947 * @adapter: board private structure to initialize 3948 * 3949 * igb_sw_init initializes the Adapter private data structure. 3950 * Fields are initialized based on PCI device information and 3951 * OS network device settings (MTU size). 3952 **/ 3953 static int igb_sw_init(struct igb_adapter *adapter) 3954 { 3955 struct e1000_hw *hw = &adapter->hw; 3956 struct net_device *netdev = adapter->netdev; 3957 struct pci_dev *pdev = adapter->pdev; 3958 3959 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3960 3961 /* set default ring sizes */ 3962 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3963 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3964 3965 /* set default ITR values */ 3966 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3967 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3968 3969 /* set default work limits */ 3970 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3971 3972 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3973 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3974 3975 spin_lock_init(&adapter->nfc_lock); 3976 spin_lock_init(&adapter->stats64_lock); 3977 #ifdef CONFIG_PCI_IOV 3978 switch (hw->mac.type) { 3979 case e1000_82576: 3980 case e1000_i350: 3981 if (max_vfs > 7) { 3982 dev_warn(&pdev->dev, 3983 "Maximum of 7 VFs per PF, using max\n"); 3984 max_vfs = adapter->vfs_allocated_count = 7; 3985 } else 3986 adapter->vfs_allocated_count = max_vfs; 3987 if (adapter->vfs_allocated_count) 3988 dev_warn(&pdev->dev, 3989 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3990 break; 3991 default: 3992 break; 3993 } 3994 #endif /* CONFIG_PCI_IOV */ 3995 3996 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3997 adapter->flags |= IGB_FLAG_HAS_MSIX; 3998 3999 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4000 sizeof(struct igb_mac_addr), 4001 GFP_KERNEL); 4002 if (!adapter->mac_table) 4003 return -ENOMEM; 4004 4005 igb_probe_vfs(adapter); 4006 4007 igb_init_queue_configuration(adapter); 4008 4009 /* Setup and initialize a copy of the hw vlan table array */ 4010 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4011 GFP_KERNEL); 4012 if (!adapter->shadow_vfta) 4013 return -ENOMEM; 4014 4015 /* This call may decrease the number of queues */ 4016 if (igb_init_interrupt_scheme(adapter, true)) { 4017 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4018 return -ENOMEM; 4019 } 4020 4021 /* Explicitly disable IRQ since the NIC can be in any state. */ 4022 igb_irq_disable(adapter); 4023 4024 if (hw->mac.type >= e1000_i350) 4025 adapter->flags &= ~IGB_FLAG_DMAC; 4026 4027 set_bit(__IGB_DOWN, &adapter->state); 4028 return 0; 4029 } 4030 4031 /** 4032 * __igb_open - Called when a network interface is made active 4033 * @netdev: network interface device structure 4034 * @resuming: indicates whether we are in a resume call 4035 * 4036 * Returns 0 on success, negative value on failure 4037 * 4038 * The open entry point is called when a network interface is made 4039 * active by the system (IFF_UP). At this point all resources needed 4040 * for transmit and receive operations are allocated, the interrupt 4041 * handler is registered with the OS, the watchdog timer is started, 4042 * and the stack is notified that the interface is ready. 4043 **/ 4044 static int __igb_open(struct net_device *netdev, bool resuming) 4045 { 4046 struct igb_adapter *adapter = netdev_priv(netdev); 4047 struct e1000_hw *hw = &adapter->hw; 4048 struct pci_dev *pdev = adapter->pdev; 4049 int err; 4050 int i; 4051 4052 /* disallow open during test */ 4053 if (test_bit(__IGB_TESTING, &adapter->state)) { 4054 WARN_ON(resuming); 4055 return -EBUSY; 4056 } 4057 4058 if (!resuming) 4059 pm_runtime_get_sync(&pdev->dev); 4060 4061 netif_carrier_off(netdev); 4062 4063 /* allocate transmit descriptors */ 4064 err = igb_setup_all_tx_resources(adapter); 4065 if (err) 4066 goto err_setup_tx; 4067 4068 /* allocate receive descriptors */ 4069 err = igb_setup_all_rx_resources(adapter); 4070 if (err) 4071 goto err_setup_rx; 4072 4073 igb_power_up_link(adapter); 4074 4075 /* before we allocate an interrupt, we must be ready to handle it. 4076 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4077 * as soon as we call pci_request_irq, so we have to setup our 4078 * clean_rx handler before we do so. 4079 */ 4080 igb_configure(adapter); 4081 4082 err = igb_request_irq(adapter); 4083 if (err) 4084 goto err_req_irq; 4085 4086 /* Notify the stack of the actual queue counts. */ 4087 err = netif_set_real_num_tx_queues(adapter->netdev, 4088 adapter->num_tx_queues); 4089 if (err) 4090 goto err_set_queues; 4091 4092 err = netif_set_real_num_rx_queues(adapter->netdev, 4093 adapter->num_rx_queues); 4094 if (err) 4095 goto err_set_queues; 4096 4097 /* From here on the code is the same as igb_up() */ 4098 clear_bit(__IGB_DOWN, &adapter->state); 4099 4100 for (i = 0; i < adapter->num_q_vectors; i++) 4101 napi_enable(&(adapter->q_vector[i]->napi)); 4102 4103 /* Clear any pending interrupts. */ 4104 rd32(E1000_TSICR); 4105 rd32(E1000_ICR); 4106 4107 igb_irq_enable(adapter); 4108 4109 /* notify VFs that reset has been completed */ 4110 if (adapter->vfs_allocated_count) { 4111 u32 reg_data = rd32(E1000_CTRL_EXT); 4112 4113 reg_data |= E1000_CTRL_EXT_PFRSTD; 4114 wr32(E1000_CTRL_EXT, reg_data); 4115 } 4116 4117 netif_tx_start_all_queues(netdev); 4118 4119 if (!resuming) 4120 pm_runtime_put(&pdev->dev); 4121 4122 /* start the watchdog. */ 4123 hw->mac.get_link_status = 1; 4124 schedule_work(&adapter->watchdog_task); 4125 4126 return 0; 4127 4128 err_set_queues: 4129 igb_free_irq(adapter); 4130 err_req_irq: 4131 igb_release_hw_control(adapter); 4132 igb_power_down_link(adapter); 4133 igb_free_all_rx_resources(adapter); 4134 err_setup_rx: 4135 igb_free_all_tx_resources(adapter); 4136 err_setup_tx: 4137 igb_reset(adapter); 4138 if (!resuming) 4139 pm_runtime_put(&pdev->dev); 4140 4141 return err; 4142 } 4143 4144 int igb_open(struct net_device *netdev) 4145 { 4146 return __igb_open(netdev, false); 4147 } 4148 4149 /** 4150 * __igb_close - Disables a network interface 4151 * @netdev: network interface device structure 4152 * @suspending: indicates we are in a suspend call 4153 * 4154 * Returns 0, this is not allowed to fail 4155 * 4156 * The close entry point is called when an interface is de-activated 4157 * by the OS. The hardware is still under the driver's control, but 4158 * needs to be disabled. A global MAC reset is issued to stop the 4159 * hardware, and all transmit and receive resources are freed. 4160 **/ 4161 static int __igb_close(struct net_device *netdev, bool suspending) 4162 { 4163 struct igb_adapter *adapter = netdev_priv(netdev); 4164 struct pci_dev *pdev = adapter->pdev; 4165 4166 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4167 4168 if (!suspending) 4169 pm_runtime_get_sync(&pdev->dev); 4170 4171 igb_down(adapter); 4172 igb_free_irq(adapter); 4173 4174 igb_free_all_tx_resources(adapter); 4175 igb_free_all_rx_resources(adapter); 4176 4177 if (!suspending) 4178 pm_runtime_put_sync(&pdev->dev); 4179 return 0; 4180 } 4181 4182 int igb_close(struct net_device *netdev) 4183 { 4184 if (netif_device_present(netdev) || netdev->dismantle) 4185 return __igb_close(netdev, false); 4186 return 0; 4187 } 4188 4189 /** 4190 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4191 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4192 * 4193 * Return 0 on success, negative on failure 4194 **/ 4195 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4196 { 4197 struct device *dev = tx_ring->dev; 4198 int size; 4199 4200 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4201 4202 tx_ring->tx_buffer_info = vmalloc(size); 4203 if (!tx_ring->tx_buffer_info) 4204 goto err; 4205 4206 /* round up to nearest 4K */ 4207 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4208 tx_ring->size = ALIGN(tx_ring->size, 4096); 4209 4210 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4211 &tx_ring->dma, GFP_KERNEL); 4212 if (!tx_ring->desc) 4213 goto err; 4214 4215 tx_ring->next_to_use = 0; 4216 tx_ring->next_to_clean = 0; 4217 4218 return 0; 4219 4220 err: 4221 vfree(tx_ring->tx_buffer_info); 4222 tx_ring->tx_buffer_info = NULL; 4223 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4224 return -ENOMEM; 4225 } 4226 4227 /** 4228 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4229 * (Descriptors) for all queues 4230 * @adapter: board private structure 4231 * 4232 * Return 0 on success, negative on failure 4233 **/ 4234 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4235 { 4236 struct pci_dev *pdev = adapter->pdev; 4237 int i, err = 0; 4238 4239 for (i = 0; i < adapter->num_tx_queues; i++) { 4240 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4241 if (err) { 4242 dev_err(&pdev->dev, 4243 "Allocation for Tx Queue %u failed\n", i); 4244 for (i--; i >= 0; i--) 4245 igb_free_tx_resources(adapter->tx_ring[i]); 4246 break; 4247 } 4248 } 4249 4250 return err; 4251 } 4252 4253 /** 4254 * igb_setup_tctl - configure the transmit control registers 4255 * @adapter: Board private structure 4256 **/ 4257 void igb_setup_tctl(struct igb_adapter *adapter) 4258 { 4259 struct e1000_hw *hw = &adapter->hw; 4260 u32 tctl; 4261 4262 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4263 wr32(E1000_TXDCTL(0), 0); 4264 4265 /* Program the Transmit Control Register */ 4266 tctl = rd32(E1000_TCTL); 4267 tctl &= ~E1000_TCTL_CT; 4268 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4269 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4270 4271 igb_config_collision_dist(hw); 4272 4273 /* Enable transmits */ 4274 tctl |= E1000_TCTL_EN; 4275 4276 wr32(E1000_TCTL, tctl); 4277 } 4278 4279 /** 4280 * igb_configure_tx_ring - Configure transmit ring after Reset 4281 * @adapter: board private structure 4282 * @ring: tx ring to configure 4283 * 4284 * Configure a transmit ring after a reset. 4285 **/ 4286 void igb_configure_tx_ring(struct igb_adapter *adapter, 4287 struct igb_ring *ring) 4288 { 4289 struct e1000_hw *hw = &adapter->hw; 4290 u32 txdctl = 0; 4291 u64 tdba = ring->dma; 4292 int reg_idx = ring->reg_idx; 4293 4294 wr32(E1000_TDLEN(reg_idx), 4295 ring->count * sizeof(union e1000_adv_tx_desc)); 4296 wr32(E1000_TDBAL(reg_idx), 4297 tdba & 0x00000000ffffffffULL); 4298 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4299 4300 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4301 wr32(E1000_TDH(reg_idx), 0); 4302 writel(0, ring->tail); 4303 4304 txdctl |= IGB_TX_PTHRESH; 4305 txdctl |= IGB_TX_HTHRESH << 8; 4306 txdctl |= IGB_TX_WTHRESH << 16; 4307 4308 /* reinitialize tx_buffer_info */ 4309 memset(ring->tx_buffer_info, 0, 4310 sizeof(struct igb_tx_buffer) * ring->count); 4311 4312 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4313 wr32(E1000_TXDCTL(reg_idx), txdctl); 4314 } 4315 4316 /** 4317 * igb_configure_tx - Configure transmit Unit after Reset 4318 * @adapter: board private structure 4319 * 4320 * Configure the Tx unit of the MAC after a reset. 4321 **/ 4322 static void igb_configure_tx(struct igb_adapter *adapter) 4323 { 4324 struct e1000_hw *hw = &adapter->hw; 4325 int i; 4326 4327 /* disable the queues */ 4328 for (i = 0; i < adapter->num_tx_queues; i++) 4329 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4330 4331 wrfl(); 4332 usleep_range(10000, 20000); 4333 4334 for (i = 0; i < adapter->num_tx_queues; i++) 4335 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4336 } 4337 4338 /** 4339 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4340 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4341 * 4342 * Returns 0 on success, negative on failure 4343 **/ 4344 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4345 { 4346 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4347 struct device *dev = rx_ring->dev; 4348 int size; 4349 4350 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4351 4352 rx_ring->rx_buffer_info = vmalloc(size); 4353 if (!rx_ring->rx_buffer_info) 4354 goto err; 4355 4356 /* Round up to nearest 4K */ 4357 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4358 rx_ring->size = ALIGN(rx_ring->size, 4096); 4359 4360 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4361 &rx_ring->dma, GFP_KERNEL); 4362 if (!rx_ring->desc) 4363 goto err; 4364 4365 rx_ring->next_to_alloc = 0; 4366 rx_ring->next_to_clean = 0; 4367 rx_ring->next_to_use = 0; 4368 4369 rx_ring->xdp_prog = adapter->xdp_prog; 4370 4371 /* XDP RX-queue info */ 4372 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4373 rx_ring->queue_index, 0) < 0) 4374 goto err; 4375 4376 return 0; 4377 4378 err: 4379 vfree(rx_ring->rx_buffer_info); 4380 rx_ring->rx_buffer_info = NULL; 4381 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4382 return -ENOMEM; 4383 } 4384 4385 /** 4386 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4387 * (Descriptors) for all queues 4388 * @adapter: board private structure 4389 * 4390 * Return 0 on success, negative on failure 4391 **/ 4392 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4393 { 4394 struct pci_dev *pdev = adapter->pdev; 4395 int i, err = 0; 4396 4397 for (i = 0; i < adapter->num_rx_queues; i++) { 4398 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4399 if (err) { 4400 dev_err(&pdev->dev, 4401 "Allocation for Rx Queue %u failed\n", i); 4402 for (i--; i >= 0; i--) 4403 igb_free_rx_resources(adapter->rx_ring[i]); 4404 break; 4405 } 4406 } 4407 4408 return err; 4409 } 4410 4411 /** 4412 * igb_setup_mrqc - configure the multiple receive queue control registers 4413 * @adapter: Board private structure 4414 **/ 4415 static void igb_setup_mrqc(struct igb_adapter *adapter) 4416 { 4417 struct e1000_hw *hw = &adapter->hw; 4418 u32 mrqc, rxcsum; 4419 u32 j, num_rx_queues; 4420 u32 rss_key[10]; 4421 4422 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4423 for (j = 0; j < 10; j++) 4424 wr32(E1000_RSSRK(j), rss_key[j]); 4425 4426 num_rx_queues = adapter->rss_queues; 4427 4428 switch (hw->mac.type) { 4429 case e1000_82576: 4430 /* 82576 supports 2 RSS queues for SR-IOV */ 4431 if (adapter->vfs_allocated_count) 4432 num_rx_queues = 2; 4433 break; 4434 default: 4435 break; 4436 } 4437 4438 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4439 for (j = 0; j < IGB_RETA_SIZE; j++) 4440 adapter->rss_indir_tbl[j] = 4441 (j * num_rx_queues) / IGB_RETA_SIZE; 4442 adapter->rss_indir_tbl_init = num_rx_queues; 4443 } 4444 igb_write_rss_indir_tbl(adapter); 4445 4446 /* Disable raw packet checksumming so that RSS hash is placed in 4447 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4448 * offloads as they are enabled by default 4449 */ 4450 rxcsum = rd32(E1000_RXCSUM); 4451 rxcsum |= E1000_RXCSUM_PCSD; 4452 4453 if (adapter->hw.mac.type >= e1000_82576) 4454 /* Enable Receive Checksum Offload for SCTP */ 4455 rxcsum |= E1000_RXCSUM_CRCOFL; 4456 4457 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4458 wr32(E1000_RXCSUM, rxcsum); 4459 4460 /* Generate RSS hash based on packet types, TCP/UDP 4461 * port numbers and/or IPv4/v6 src and dst addresses 4462 */ 4463 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4464 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4465 E1000_MRQC_RSS_FIELD_IPV6 | 4466 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4467 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4468 4469 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4470 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4471 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4472 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4473 4474 /* If VMDq is enabled then we set the appropriate mode for that, else 4475 * we default to RSS so that an RSS hash is calculated per packet even 4476 * if we are only using one queue 4477 */ 4478 if (adapter->vfs_allocated_count) { 4479 if (hw->mac.type > e1000_82575) { 4480 /* Set the default pool for the PF's first queue */ 4481 u32 vtctl = rd32(E1000_VT_CTL); 4482 4483 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4484 E1000_VT_CTL_DISABLE_DEF_POOL); 4485 vtctl |= adapter->vfs_allocated_count << 4486 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4487 wr32(E1000_VT_CTL, vtctl); 4488 } 4489 if (adapter->rss_queues > 1) 4490 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4491 else 4492 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4493 } else { 4494 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4495 } 4496 igb_vmm_control(adapter); 4497 4498 wr32(E1000_MRQC, mrqc); 4499 } 4500 4501 /** 4502 * igb_setup_rctl - configure the receive control registers 4503 * @adapter: Board private structure 4504 **/ 4505 void igb_setup_rctl(struct igb_adapter *adapter) 4506 { 4507 struct e1000_hw *hw = &adapter->hw; 4508 u32 rctl; 4509 4510 rctl = rd32(E1000_RCTL); 4511 4512 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4513 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4514 4515 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4516 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4517 4518 /* enable stripping of CRC. It's unlikely this will break BMC 4519 * redirection as it did with e1000. Newer features require 4520 * that the HW strips the CRC. 4521 */ 4522 rctl |= E1000_RCTL_SECRC; 4523 4524 /* disable store bad packets and clear size bits. */ 4525 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4526 4527 /* enable LPE to allow for reception of jumbo frames */ 4528 rctl |= E1000_RCTL_LPE; 4529 4530 /* disable queue 0 to prevent tail write w/o re-config */ 4531 wr32(E1000_RXDCTL(0), 0); 4532 4533 /* Attention!!! For SR-IOV PF driver operations you must enable 4534 * queue drop for all VF and PF queues to prevent head of line blocking 4535 * if an un-trusted VF does not provide descriptors to hardware. 4536 */ 4537 if (adapter->vfs_allocated_count) { 4538 /* set all queue drop enable bits */ 4539 wr32(E1000_QDE, ALL_QUEUES); 4540 } 4541 4542 /* This is useful for sniffing bad packets. */ 4543 if (adapter->netdev->features & NETIF_F_RXALL) { 4544 /* UPE and MPE will be handled by normal PROMISC logic 4545 * in e1000e_set_rx_mode 4546 */ 4547 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4548 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4549 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4550 4551 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4552 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4553 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4554 * and that breaks VLANs. 4555 */ 4556 } 4557 4558 wr32(E1000_RCTL, rctl); 4559 } 4560 4561 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4562 int vfn) 4563 { 4564 struct e1000_hw *hw = &adapter->hw; 4565 u32 vmolr; 4566 4567 if (size > MAX_JUMBO_FRAME_SIZE) 4568 size = MAX_JUMBO_FRAME_SIZE; 4569 4570 vmolr = rd32(E1000_VMOLR(vfn)); 4571 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4572 vmolr |= size | E1000_VMOLR_LPE; 4573 wr32(E1000_VMOLR(vfn), vmolr); 4574 4575 return 0; 4576 } 4577 4578 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4579 int vfn, bool enable) 4580 { 4581 struct e1000_hw *hw = &adapter->hw; 4582 u32 val, reg; 4583 4584 if (hw->mac.type < e1000_82576) 4585 return; 4586 4587 if (hw->mac.type == e1000_i350) 4588 reg = E1000_DVMOLR(vfn); 4589 else 4590 reg = E1000_VMOLR(vfn); 4591 4592 val = rd32(reg); 4593 if (enable) 4594 val |= E1000_VMOLR_STRVLAN; 4595 else 4596 val &= ~(E1000_VMOLR_STRVLAN); 4597 wr32(reg, val); 4598 } 4599 4600 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4601 int vfn, bool aupe) 4602 { 4603 struct e1000_hw *hw = &adapter->hw; 4604 u32 vmolr; 4605 4606 /* This register exists only on 82576 and newer so if we are older then 4607 * we should exit and do nothing 4608 */ 4609 if (hw->mac.type < e1000_82576) 4610 return; 4611 4612 vmolr = rd32(E1000_VMOLR(vfn)); 4613 if (aupe) 4614 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4615 else 4616 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4617 4618 /* clear all bits that might not be set */ 4619 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4620 4621 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4622 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4623 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4624 * multicast packets 4625 */ 4626 if (vfn <= adapter->vfs_allocated_count) 4627 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4628 4629 wr32(E1000_VMOLR(vfn), vmolr); 4630 } 4631 4632 /** 4633 * igb_setup_srrctl - configure the split and replication receive control 4634 * registers 4635 * @adapter: Board private structure 4636 * @ring: receive ring to be configured 4637 **/ 4638 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4639 { 4640 struct e1000_hw *hw = &adapter->hw; 4641 int reg_idx = ring->reg_idx; 4642 u32 srrctl = 0; 4643 4644 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4645 if (ring_uses_large_buffer(ring)) 4646 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4647 else 4648 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4649 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4650 if (hw->mac.type >= e1000_82580) 4651 srrctl |= E1000_SRRCTL_TIMESTAMP; 4652 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4653 * queues and rx flow control is disabled 4654 */ 4655 if (adapter->vfs_allocated_count || 4656 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4657 adapter->num_rx_queues > 1)) 4658 srrctl |= E1000_SRRCTL_DROP_EN; 4659 4660 wr32(E1000_SRRCTL(reg_idx), srrctl); 4661 } 4662 4663 /** 4664 * igb_configure_rx_ring - Configure a receive ring after Reset 4665 * @adapter: board private structure 4666 * @ring: receive ring to be configured 4667 * 4668 * Configure the Rx unit of the MAC after a reset. 4669 **/ 4670 void igb_configure_rx_ring(struct igb_adapter *adapter, 4671 struct igb_ring *ring) 4672 { 4673 struct e1000_hw *hw = &adapter->hw; 4674 union e1000_adv_rx_desc *rx_desc; 4675 u64 rdba = ring->dma; 4676 int reg_idx = ring->reg_idx; 4677 u32 rxdctl = 0; 4678 4679 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4680 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4681 MEM_TYPE_PAGE_SHARED, NULL)); 4682 4683 /* disable the queue */ 4684 wr32(E1000_RXDCTL(reg_idx), 0); 4685 4686 /* Set DMA base address registers */ 4687 wr32(E1000_RDBAL(reg_idx), 4688 rdba & 0x00000000ffffffffULL); 4689 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4690 wr32(E1000_RDLEN(reg_idx), 4691 ring->count * sizeof(union e1000_adv_rx_desc)); 4692 4693 /* initialize head and tail */ 4694 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4695 wr32(E1000_RDH(reg_idx), 0); 4696 writel(0, ring->tail); 4697 4698 /* set descriptor configuration */ 4699 igb_setup_srrctl(adapter, ring); 4700 4701 /* set filtering for VMDQ pools */ 4702 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4703 4704 rxdctl |= IGB_RX_PTHRESH; 4705 rxdctl |= IGB_RX_HTHRESH << 8; 4706 rxdctl |= IGB_RX_WTHRESH << 16; 4707 4708 /* initialize rx_buffer_info */ 4709 memset(ring->rx_buffer_info, 0, 4710 sizeof(struct igb_rx_buffer) * ring->count); 4711 4712 /* initialize Rx descriptor 0 */ 4713 rx_desc = IGB_RX_DESC(ring, 0); 4714 rx_desc->wb.upper.length = 0; 4715 4716 /* enable receive descriptor fetching */ 4717 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4718 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4719 } 4720 4721 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4722 struct igb_ring *rx_ring) 4723 { 4724 /* set build_skb and buffer size flags */ 4725 clear_ring_build_skb_enabled(rx_ring); 4726 clear_ring_uses_large_buffer(rx_ring); 4727 4728 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4729 return; 4730 4731 set_ring_build_skb_enabled(rx_ring); 4732 4733 #if (PAGE_SIZE < 8192) 4734 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4735 return; 4736 4737 set_ring_uses_large_buffer(rx_ring); 4738 #endif 4739 } 4740 4741 /** 4742 * igb_configure_rx - Configure receive Unit after Reset 4743 * @adapter: board private structure 4744 * 4745 * Configure the Rx unit of the MAC after a reset. 4746 **/ 4747 static void igb_configure_rx(struct igb_adapter *adapter) 4748 { 4749 int i; 4750 4751 /* set the correct pool for the PF default MAC address in entry 0 */ 4752 igb_set_default_mac_filter(adapter); 4753 4754 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4755 * the Base and Length of the Rx Descriptor Ring 4756 */ 4757 for (i = 0; i < adapter->num_rx_queues; i++) { 4758 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4759 4760 igb_set_rx_buffer_len(adapter, rx_ring); 4761 igb_configure_rx_ring(adapter, rx_ring); 4762 } 4763 } 4764 4765 /** 4766 * igb_free_tx_resources - Free Tx Resources per Queue 4767 * @tx_ring: Tx descriptor ring for a specific queue 4768 * 4769 * Free all transmit software resources 4770 **/ 4771 void igb_free_tx_resources(struct igb_ring *tx_ring) 4772 { 4773 igb_clean_tx_ring(tx_ring); 4774 4775 vfree(tx_ring->tx_buffer_info); 4776 tx_ring->tx_buffer_info = NULL; 4777 4778 /* if not set, then don't free */ 4779 if (!tx_ring->desc) 4780 return; 4781 4782 dma_free_coherent(tx_ring->dev, tx_ring->size, 4783 tx_ring->desc, tx_ring->dma); 4784 4785 tx_ring->desc = NULL; 4786 } 4787 4788 /** 4789 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4790 * @adapter: board private structure 4791 * 4792 * Free all transmit software resources 4793 **/ 4794 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4795 { 4796 int i; 4797 4798 for (i = 0; i < adapter->num_tx_queues; i++) 4799 if (adapter->tx_ring[i]) 4800 igb_free_tx_resources(adapter->tx_ring[i]); 4801 } 4802 4803 /** 4804 * igb_clean_tx_ring - Free Tx Buffers 4805 * @tx_ring: ring to be cleaned 4806 **/ 4807 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4808 { 4809 u16 i = tx_ring->next_to_clean; 4810 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4811 4812 while (i != tx_ring->next_to_use) { 4813 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4814 4815 /* Free all the Tx ring sk_buffs */ 4816 dev_kfree_skb_any(tx_buffer->skb); 4817 4818 /* unmap skb header data */ 4819 dma_unmap_single(tx_ring->dev, 4820 dma_unmap_addr(tx_buffer, dma), 4821 dma_unmap_len(tx_buffer, len), 4822 DMA_TO_DEVICE); 4823 4824 /* check for eop_desc to determine the end of the packet */ 4825 eop_desc = tx_buffer->next_to_watch; 4826 tx_desc = IGB_TX_DESC(tx_ring, i); 4827 4828 /* unmap remaining buffers */ 4829 while (tx_desc != eop_desc) { 4830 tx_buffer++; 4831 tx_desc++; 4832 i++; 4833 if (unlikely(i == tx_ring->count)) { 4834 i = 0; 4835 tx_buffer = tx_ring->tx_buffer_info; 4836 tx_desc = IGB_TX_DESC(tx_ring, 0); 4837 } 4838 4839 /* unmap any remaining paged data */ 4840 if (dma_unmap_len(tx_buffer, len)) 4841 dma_unmap_page(tx_ring->dev, 4842 dma_unmap_addr(tx_buffer, dma), 4843 dma_unmap_len(tx_buffer, len), 4844 DMA_TO_DEVICE); 4845 } 4846 4847 tx_buffer->next_to_watch = NULL; 4848 4849 /* move us one more past the eop_desc for start of next pkt */ 4850 tx_buffer++; 4851 i++; 4852 if (unlikely(i == tx_ring->count)) { 4853 i = 0; 4854 tx_buffer = tx_ring->tx_buffer_info; 4855 } 4856 } 4857 4858 /* reset BQL for queue */ 4859 netdev_tx_reset_queue(txring_txq(tx_ring)); 4860 4861 /* reset next_to_use and next_to_clean */ 4862 tx_ring->next_to_use = 0; 4863 tx_ring->next_to_clean = 0; 4864 } 4865 4866 /** 4867 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4868 * @adapter: board private structure 4869 **/ 4870 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4871 { 4872 int i; 4873 4874 for (i = 0; i < adapter->num_tx_queues; i++) 4875 if (adapter->tx_ring[i]) 4876 igb_clean_tx_ring(adapter->tx_ring[i]); 4877 } 4878 4879 /** 4880 * igb_free_rx_resources - Free Rx Resources 4881 * @rx_ring: ring to clean the resources from 4882 * 4883 * Free all receive software resources 4884 **/ 4885 void igb_free_rx_resources(struct igb_ring *rx_ring) 4886 { 4887 igb_clean_rx_ring(rx_ring); 4888 4889 rx_ring->xdp_prog = NULL; 4890 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4891 vfree(rx_ring->rx_buffer_info); 4892 rx_ring->rx_buffer_info = NULL; 4893 4894 /* if not set, then don't free */ 4895 if (!rx_ring->desc) 4896 return; 4897 4898 dma_free_coherent(rx_ring->dev, rx_ring->size, 4899 rx_ring->desc, rx_ring->dma); 4900 4901 rx_ring->desc = NULL; 4902 } 4903 4904 /** 4905 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4906 * @adapter: board private structure 4907 * 4908 * Free all receive software resources 4909 **/ 4910 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4911 { 4912 int i; 4913 4914 for (i = 0; i < adapter->num_rx_queues; i++) 4915 if (adapter->rx_ring[i]) 4916 igb_free_rx_resources(adapter->rx_ring[i]); 4917 } 4918 4919 /** 4920 * igb_clean_rx_ring - Free Rx Buffers per Queue 4921 * @rx_ring: ring to free buffers from 4922 **/ 4923 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4924 { 4925 u16 i = rx_ring->next_to_clean; 4926 4927 dev_kfree_skb(rx_ring->skb); 4928 rx_ring->skb = NULL; 4929 4930 /* Free all the Rx ring sk_buffs */ 4931 while (i != rx_ring->next_to_alloc) { 4932 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4933 4934 /* Invalidate cache lines that may have been written to by 4935 * device so that we avoid corrupting memory. 4936 */ 4937 dma_sync_single_range_for_cpu(rx_ring->dev, 4938 buffer_info->dma, 4939 buffer_info->page_offset, 4940 igb_rx_bufsz(rx_ring), 4941 DMA_FROM_DEVICE); 4942 4943 /* free resources associated with mapping */ 4944 dma_unmap_page_attrs(rx_ring->dev, 4945 buffer_info->dma, 4946 igb_rx_pg_size(rx_ring), 4947 DMA_FROM_DEVICE, 4948 IGB_RX_DMA_ATTR); 4949 __page_frag_cache_drain(buffer_info->page, 4950 buffer_info->pagecnt_bias); 4951 4952 i++; 4953 if (i == rx_ring->count) 4954 i = 0; 4955 } 4956 4957 rx_ring->next_to_alloc = 0; 4958 rx_ring->next_to_clean = 0; 4959 rx_ring->next_to_use = 0; 4960 } 4961 4962 /** 4963 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4964 * @adapter: board private structure 4965 **/ 4966 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4967 { 4968 int i; 4969 4970 for (i = 0; i < adapter->num_rx_queues; i++) 4971 if (adapter->rx_ring[i]) 4972 igb_clean_rx_ring(adapter->rx_ring[i]); 4973 } 4974 4975 /** 4976 * igb_set_mac - Change the Ethernet Address of the NIC 4977 * @netdev: network interface device structure 4978 * @p: pointer to an address structure 4979 * 4980 * Returns 0 on success, negative on failure 4981 **/ 4982 static int igb_set_mac(struct net_device *netdev, void *p) 4983 { 4984 struct igb_adapter *adapter = netdev_priv(netdev); 4985 struct e1000_hw *hw = &adapter->hw; 4986 struct sockaddr *addr = p; 4987 4988 if (!is_valid_ether_addr(addr->sa_data)) 4989 return -EADDRNOTAVAIL; 4990 4991 eth_hw_addr_set(netdev, addr->sa_data); 4992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4993 4994 /* set the correct pool for the new PF MAC address in entry 0 */ 4995 igb_set_default_mac_filter(adapter); 4996 4997 return 0; 4998 } 4999 5000 /** 5001 * igb_write_mc_addr_list - write multicast addresses to MTA 5002 * @netdev: network interface device structure 5003 * 5004 * Writes multicast address list to the MTA hash table. 5005 * Returns: -ENOMEM on failure 5006 * 0 on no addresses written 5007 * X on writing X addresses to MTA 5008 **/ 5009 static int igb_write_mc_addr_list(struct net_device *netdev) 5010 { 5011 struct igb_adapter *adapter = netdev_priv(netdev); 5012 struct e1000_hw *hw = &adapter->hw; 5013 struct netdev_hw_addr *ha; 5014 u8 *mta_list; 5015 int i; 5016 5017 if (netdev_mc_empty(netdev)) { 5018 /* nothing to program, so clear mc list */ 5019 igb_update_mc_addr_list(hw, NULL, 0); 5020 igb_restore_vf_multicasts(adapter); 5021 return 0; 5022 } 5023 5024 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5025 if (!mta_list) 5026 return -ENOMEM; 5027 5028 /* The shared function expects a packed array of only addresses. */ 5029 i = 0; 5030 netdev_for_each_mc_addr(ha, netdev) 5031 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5032 5033 igb_update_mc_addr_list(hw, mta_list, i); 5034 kfree(mta_list); 5035 5036 return netdev_mc_count(netdev); 5037 } 5038 5039 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5040 { 5041 struct e1000_hw *hw = &adapter->hw; 5042 u32 i, pf_id; 5043 5044 switch (hw->mac.type) { 5045 case e1000_i210: 5046 case e1000_i211: 5047 case e1000_i350: 5048 /* VLAN filtering needed for VLAN prio filter */ 5049 if (adapter->netdev->features & NETIF_F_NTUPLE) 5050 break; 5051 fallthrough; 5052 case e1000_82576: 5053 case e1000_82580: 5054 case e1000_i354: 5055 /* VLAN filtering needed for pool filtering */ 5056 if (adapter->vfs_allocated_count) 5057 break; 5058 fallthrough; 5059 default: 5060 return 1; 5061 } 5062 5063 /* We are already in VLAN promisc, nothing to do */ 5064 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5065 return 0; 5066 5067 if (!adapter->vfs_allocated_count) 5068 goto set_vfta; 5069 5070 /* Add PF to all active pools */ 5071 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5072 5073 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5074 u32 vlvf = rd32(E1000_VLVF(i)); 5075 5076 vlvf |= BIT(pf_id); 5077 wr32(E1000_VLVF(i), vlvf); 5078 } 5079 5080 set_vfta: 5081 /* Set all bits in the VLAN filter table array */ 5082 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5083 hw->mac.ops.write_vfta(hw, i, ~0U); 5084 5085 /* Set flag so we don't redo unnecessary work */ 5086 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5087 5088 return 0; 5089 } 5090 5091 #define VFTA_BLOCK_SIZE 8 5092 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5093 { 5094 struct e1000_hw *hw = &adapter->hw; 5095 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5096 u32 vid_start = vfta_offset * 32; 5097 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5098 u32 i, vid, word, bits, pf_id; 5099 5100 /* guarantee that we don't scrub out management VLAN */ 5101 vid = adapter->mng_vlan_id; 5102 if (vid >= vid_start && vid < vid_end) 5103 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5104 5105 if (!adapter->vfs_allocated_count) 5106 goto set_vfta; 5107 5108 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5109 5110 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5111 u32 vlvf = rd32(E1000_VLVF(i)); 5112 5113 /* pull VLAN ID from VLVF */ 5114 vid = vlvf & VLAN_VID_MASK; 5115 5116 /* only concern ourselves with a certain range */ 5117 if (vid < vid_start || vid >= vid_end) 5118 continue; 5119 5120 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5121 /* record VLAN ID in VFTA */ 5122 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5123 5124 /* if PF is part of this then continue */ 5125 if (test_bit(vid, adapter->active_vlans)) 5126 continue; 5127 } 5128 5129 /* remove PF from the pool */ 5130 bits = ~BIT(pf_id); 5131 bits &= rd32(E1000_VLVF(i)); 5132 wr32(E1000_VLVF(i), bits); 5133 } 5134 5135 set_vfta: 5136 /* extract values from active_vlans and write back to VFTA */ 5137 for (i = VFTA_BLOCK_SIZE; i--;) { 5138 vid = (vfta_offset + i) * 32; 5139 word = vid / BITS_PER_LONG; 5140 bits = vid % BITS_PER_LONG; 5141 5142 vfta[i] |= adapter->active_vlans[word] >> bits; 5143 5144 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5145 } 5146 } 5147 5148 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5149 { 5150 u32 i; 5151 5152 /* We are not in VLAN promisc, nothing to do */ 5153 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5154 return; 5155 5156 /* Set flag so we don't redo unnecessary work */ 5157 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5158 5159 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5160 igb_scrub_vfta(adapter, i); 5161 } 5162 5163 /** 5164 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5165 * @netdev: network interface device structure 5166 * 5167 * The set_rx_mode entry point is called whenever the unicast or multicast 5168 * address lists or the network interface flags are updated. This routine is 5169 * responsible for configuring the hardware for proper unicast, multicast, 5170 * promiscuous mode, and all-multi behavior. 5171 **/ 5172 static void igb_set_rx_mode(struct net_device *netdev) 5173 { 5174 struct igb_adapter *adapter = netdev_priv(netdev); 5175 struct e1000_hw *hw = &adapter->hw; 5176 unsigned int vfn = adapter->vfs_allocated_count; 5177 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5178 int count; 5179 5180 /* Check for Promiscuous and All Multicast modes */ 5181 if (netdev->flags & IFF_PROMISC) { 5182 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5183 vmolr |= E1000_VMOLR_MPME; 5184 5185 /* enable use of UTA filter to force packets to default pool */ 5186 if (hw->mac.type == e1000_82576) 5187 vmolr |= E1000_VMOLR_ROPE; 5188 } else { 5189 if (netdev->flags & IFF_ALLMULTI) { 5190 rctl |= E1000_RCTL_MPE; 5191 vmolr |= E1000_VMOLR_MPME; 5192 } else { 5193 /* Write addresses to the MTA, if the attempt fails 5194 * then we should just turn on promiscuous mode so 5195 * that we can at least receive multicast traffic 5196 */ 5197 count = igb_write_mc_addr_list(netdev); 5198 if (count < 0) { 5199 rctl |= E1000_RCTL_MPE; 5200 vmolr |= E1000_VMOLR_MPME; 5201 } else if (count) { 5202 vmolr |= E1000_VMOLR_ROMPE; 5203 } 5204 } 5205 } 5206 5207 /* Write addresses to available RAR registers, if there is not 5208 * sufficient space to store all the addresses then enable 5209 * unicast promiscuous mode 5210 */ 5211 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5212 rctl |= E1000_RCTL_UPE; 5213 vmolr |= E1000_VMOLR_ROPE; 5214 } 5215 5216 /* enable VLAN filtering by default */ 5217 rctl |= E1000_RCTL_VFE; 5218 5219 /* disable VLAN filtering for modes that require it */ 5220 if ((netdev->flags & IFF_PROMISC) || 5221 (netdev->features & NETIF_F_RXALL)) { 5222 /* if we fail to set all rules then just clear VFE */ 5223 if (igb_vlan_promisc_enable(adapter)) 5224 rctl &= ~E1000_RCTL_VFE; 5225 } else { 5226 igb_vlan_promisc_disable(adapter); 5227 } 5228 5229 /* update state of unicast, multicast, and VLAN filtering modes */ 5230 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5231 E1000_RCTL_VFE); 5232 wr32(E1000_RCTL, rctl); 5233 5234 #if (PAGE_SIZE < 8192) 5235 if (!adapter->vfs_allocated_count) { 5236 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5237 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5238 } 5239 #endif 5240 wr32(E1000_RLPML, rlpml); 5241 5242 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5243 * the VMOLR to enable the appropriate modes. Without this workaround 5244 * we will have issues with VLAN tag stripping not being done for frames 5245 * that are only arriving because we are the default pool 5246 */ 5247 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5248 return; 5249 5250 /* set UTA to appropriate mode */ 5251 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5252 5253 vmolr |= rd32(E1000_VMOLR(vfn)) & 5254 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5255 5256 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5257 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5258 #if (PAGE_SIZE < 8192) 5259 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5260 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5261 else 5262 #endif 5263 vmolr |= MAX_JUMBO_FRAME_SIZE; 5264 vmolr |= E1000_VMOLR_LPE; 5265 5266 wr32(E1000_VMOLR(vfn), vmolr); 5267 5268 igb_restore_vf_multicasts(adapter); 5269 } 5270 5271 static void igb_check_wvbr(struct igb_adapter *adapter) 5272 { 5273 struct e1000_hw *hw = &adapter->hw; 5274 u32 wvbr = 0; 5275 5276 switch (hw->mac.type) { 5277 case e1000_82576: 5278 case e1000_i350: 5279 wvbr = rd32(E1000_WVBR); 5280 if (!wvbr) 5281 return; 5282 break; 5283 default: 5284 break; 5285 } 5286 5287 adapter->wvbr |= wvbr; 5288 } 5289 5290 #define IGB_STAGGERED_QUEUE_OFFSET 8 5291 5292 static void igb_spoof_check(struct igb_adapter *adapter) 5293 { 5294 int j; 5295 5296 if (!adapter->wvbr) 5297 return; 5298 5299 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5300 if (adapter->wvbr & BIT(j) || 5301 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5302 dev_warn(&adapter->pdev->dev, 5303 "Spoof event(s) detected on VF %d\n", j); 5304 adapter->wvbr &= 5305 ~(BIT(j) | 5306 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5307 } 5308 } 5309 } 5310 5311 /* Need to wait a few seconds after link up to get diagnostic information from 5312 * the phy 5313 */ 5314 static void igb_update_phy_info(struct timer_list *t) 5315 { 5316 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5317 igb_get_phy_info(&adapter->hw); 5318 } 5319 5320 /** 5321 * igb_has_link - check shared code for link and determine up/down 5322 * @adapter: pointer to driver private info 5323 **/ 5324 bool igb_has_link(struct igb_adapter *adapter) 5325 { 5326 struct e1000_hw *hw = &adapter->hw; 5327 bool link_active = false; 5328 5329 /* get_link_status is set on LSC (link status) interrupt or 5330 * rx sequence error interrupt. get_link_status will stay 5331 * false until the e1000_check_for_link establishes link 5332 * for copper adapters ONLY 5333 */ 5334 switch (hw->phy.media_type) { 5335 case e1000_media_type_copper: 5336 if (!hw->mac.get_link_status) 5337 return true; 5338 fallthrough; 5339 case e1000_media_type_internal_serdes: 5340 hw->mac.ops.check_for_link(hw); 5341 link_active = !hw->mac.get_link_status; 5342 break; 5343 default: 5344 case e1000_media_type_unknown: 5345 break; 5346 } 5347 5348 if (((hw->mac.type == e1000_i210) || 5349 (hw->mac.type == e1000_i211)) && 5350 (hw->phy.id == I210_I_PHY_ID)) { 5351 if (!netif_carrier_ok(adapter->netdev)) { 5352 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5353 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5354 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5355 adapter->link_check_timeout = jiffies; 5356 } 5357 } 5358 5359 return link_active; 5360 } 5361 5362 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5363 { 5364 bool ret = false; 5365 u32 ctrl_ext, thstat; 5366 5367 /* check for thermal sensor event on i350 copper only */ 5368 if (hw->mac.type == e1000_i350) { 5369 thstat = rd32(E1000_THSTAT); 5370 ctrl_ext = rd32(E1000_CTRL_EXT); 5371 5372 if ((hw->phy.media_type == e1000_media_type_copper) && 5373 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5374 ret = !!(thstat & event); 5375 } 5376 5377 return ret; 5378 } 5379 5380 /** 5381 * igb_check_lvmmc - check for malformed packets received 5382 * and indicated in LVMMC register 5383 * @adapter: pointer to adapter 5384 **/ 5385 static void igb_check_lvmmc(struct igb_adapter *adapter) 5386 { 5387 struct e1000_hw *hw = &adapter->hw; 5388 u32 lvmmc; 5389 5390 lvmmc = rd32(E1000_LVMMC); 5391 if (lvmmc) { 5392 if (unlikely(net_ratelimit())) { 5393 netdev_warn(adapter->netdev, 5394 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5395 lvmmc); 5396 } 5397 } 5398 } 5399 5400 /** 5401 * igb_watchdog - Timer Call-back 5402 * @t: pointer to timer_list containing our private info pointer 5403 **/ 5404 static void igb_watchdog(struct timer_list *t) 5405 { 5406 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5407 /* Do the rest outside of interrupt context */ 5408 schedule_work(&adapter->watchdog_task); 5409 } 5410 5411 static void igb_watchdog_task(struct work_struct *work) 5412 { 5413 struct igb_adapter *adapter = container_of(work, 5414 struct igb_adapter, 5415 watchdog_task); 5416 struct e1000_hw *hw = &adapter->hw; 5417 struct e1000_phy_info *phy = &hw->phy; 5418 struct net_device *netdev = adapter->netdev; 5419 u32 link; 5420 int i; 5421 u32 connsw; 5422 u16 phy_data, retry_count = 20; 5423 5424 link = igb_has_link(adapter); 5425 5426 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5427 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5428 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5429 else 5430 link = false; 5431 } 5432 5433 /* Force link down if we have fiber to swap to */ 5434 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5435 if (hw->phy.media_type == e1000_media_type_copper) { 5436 connsw = rd32(E1000_CONNSW); 5437 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5438 link = 0; 5439 } 5440 } 5441 if (link) { 5442 /* Perform a reset if the media type changed. */ 5443 if (hw->dev_spec._82575.media_changed) { 5444 hw->dev_spec._82575.media_changed = false; 5445 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5446 igb_reset(adapter); 5447 } 5448 /* Cancel scheduled suspend requests. */ 5449 pm_runtime_resume(netdev->dev.parent); 5450 5451 if (!netif_carrier_ok(netdev)) { 5452 u32 ctrl; 5453 5454 hw->mac.ops.get_speed_and_duplex(hw, 5455 &adapter->link_speed, 5456 &adapter->link_duplex); 5457 5458 ctrl = rd32(E1000_CTRL); 5459 /* Links status message must follow this format */ 5460 netdev_info(netdev, 5461 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5462 netdev->name, 5463 adapter->link_speed, 5464 adapter->link_duplex == FULL_DUPLEX ? 5465 "Full" : "Half", 5466 (ctrl & E1000_CTRL_TFCE) && 5467 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5468 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5469 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5470 5471 /* disable EEE if enabled */ 5472 if ((adapter->flags & IGB_FLAG_EEE) && 5473 (adapter->link_duplex == HALF_DUPLEX)) { 5474 dev_info(&adapter->pdev->dev, 5475 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5476 adapter->hw.dev_spec._82575.eee_disable = true; 5477 adapter->flags &= ~IGB_FLAG_EEE; 5478 } 5479 5480 /* check if SmartSpeed worked */ 5481 igb_check_downshift(hw); 5482 if (phy->speed_downgraded) 5483 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5484 5485 /* check for thermal sensor event */ 5486 if (igb_thermal_sensor_event(hw, 5487 E1000_THSTAT_LINK_THROTTLE)) 5488 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5489 5490 /* adjust timeout factor according to speed/duplex */ 5491 adapter->tx_timeout_factor = 1; 5492 switch (adapter->link_speed) { 5493 case SPEED_10: 5494 adapter->tx_timeout_factor = 14; 5495 break; 5496 case SPEED_100: 5497 /* maybe add some timeout factor ? */ 5498 break; 5499 } 5500 5501 if (adapter->link_speed != SPEED_1000) 5502 goto no_wait; 5503 5504 /* wait for Remote receiver status OK */ 5505 retry_read_status: 5506 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5507 &phy_data)) { 5508 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5509 retry_count) { 5510 msleep(100); 5511 retry_count--; 5512 goto retry_read_status; 5513 } else if (!retry_count) { 5514 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5515 } 5516 } else { 5517 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5518 } 5519 no_wait: 5520 netif_carrier_on(netdev); 5521 5522 igb_ping_all_vfs(adapter); 5523 igb_check_vf_rate_limit(adapter); 5524 5525 /* link state has changed, schedule phy info update */ 5526 if (!test_bit(__IGB_DOWN, &adapter->state)) 5527 mod_timer(&adapter->phy_info_timer, 5528 round_jiffies(jiffies + 2 * HZ)); 5529 } 5530 } else { 5531 if (netif_carrier_ok(netdev)) { 5532 adapter->link_speed = 0; 5533 adapter->link_duplex = 0; 5534 5535 /* check for thermal sensor event */ 5536 if (igb_thermal_sensor_event(hw, 5537 E1000_THSTAT_PWR_DOWN)) { 5538 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5539 } 5540 5541 /* Links status message must follow this format */ 5542 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5543 netdev->name); 5544 netif_carrier_off(netdev); 5545 5546 igb_ping_all_vfs(adapter); 5547 5548 /* link state has changed, schedule phy info update */ 5549 if (!test_bit(__IGB_DOWN, &adapter->state)) 5550 mod_timer(&adapter->phy_info_timer, 5551 round_jiffies(jiffies + 2 * HZ)); 5552 5553 /* link is down, time to check for alternate media */ 5554 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5555 igb_check_swap_media(adapter); 5556 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5557 schedule_work(&adapter->reset_task); 5558 /* return immediately */ 5559 return; 5560 } 5561 } 5562 pm_schedule_suspend(netdev->dev.parent, 5563 MSEC_PER_SEC * 5); 5564 5565 /* also check for alternate media here */ 5566 } else if (!netif_carrier_ok(netdev) && 5567 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5568 igb_check_swap_media(adapter); 5569 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5570 schedule_work(&adapter->reset_task); 5571 /* return immediately */ 5572 return; 5573 } 5574 } 5575 } 5576 5577 spin_lock(&adapter->stats64_lock); 5578 igb_update_stats(adapter); 5579 spin_unlock(&adapter->stats64_lock); 5580 5581 for (i = 0; i < adapter->num_tx_queues; i++) { 5582 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5583 if (!netif_carrier_ok(netdev)) { 5584 /* We've lost link, so the controller stops DMA, 5585 * but we've got queued Tx work that's never going 5586 * to get done, so reset controller to flush Tx. 5587 * (Do the reset outside of interrupt context). 5588 */ 5589 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5590 adapter->tx_timeout_count++; 5591 schedule_work(&adapter->reset_task); 5592 /* return immediately since reset is imminent */ 5593 return; 5594 } 5595 } 5596 5597 /* Force detection of hung controller every watchdog period */ 5598 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5599 } 5600 5601 /* Cause software interrupt to ensure Rx ring is cleaned */ 5602 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5603 u32 eics = 0; 5604 5605 for (i = 0; i < adapter->num_q_vectors; i++) 5606 eics |= adapter->q_vector[i]->eims_value; 5607 wr32(E1000_EICS, eics); 5608 } else { 5609 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5610 } 5611 5612 igb_spoof_check(adapter); 5613 igb_ptp_rx_hang(adapter); 5614 igb_ptp_tx_hang(adapter); 5615 5616 /* Check LVMMC register on i350/i354 only */ 5617 if ((adapter->hw.mac.type == e1000_i350) || 5618 (adapter->hw.mac.type == e1000_i354)) 5619 igb_check_lvmmc(adapter); 5620 5621 /* Reset the timer */ 5622 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5623 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5624 mod_timer(&adapter->watchdog_timer, 5625 round_jiffies(jiffies + HZ)); 5626 else 5627 mod_timer(&adapter->watchdog_timer, 5628 round_jiffies(jiffies + 2 * HZ)); 5629 } 5630 } 5631 5632 enum latency_range { 5633 lowest_latency = 0, 5634 low_latency = 1, 5635 bulk_latency = 2, 5636 latency_invalid = 255 5637 }; 5638 5639 /** 5640 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5641 * @q_vector: pointer to q_vector 5642 * 5643 * Stores a new ITR value based on strictly on packet size. This 5644 * algorithm is less sophisticated than that used in igb_update_itr, 5645 * due to the difficulty of synchronizing statistics across multiple 5646 * receive rings. The divisors and thresholds used by this function 5647 * were determined based on theoretical maximum wire speed and testing 5648 * data, in order to minimize response time while increasing bulk 5649 * throughput. 5650 * This functionality is controlled by ethtool's coalescing settings. 5651 * NOTE: This function is called only when operating in a multiqueue 5652 * receive environment. 5653 **/ 5654 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5655 { 5656 int new_val = q_vector->itr_val; 5657 int avg_wire_size = 0; 5658 struct igb_adapter *adapter = q_vector->adapter; 5659 unsigned int packets; 5660 5661 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5662 * ints/sec - ITR timer value of 120 ticks. 5663 */ 5664 if (adapter->link_speed != SPEED_1000) { 5665 new_val = IGB_4K_ITR; 5666 goto set_itr_val; 5667 } 5668 5669 packets = q_vector->rx.total_packets; 5670 if (packets) 5671 avg_wire_size = q_vector->rx.total_bytes / packets; 5672 5673 packets = q_vector->tx.total_packets; 5674 if (packets) 5675 avg_wire_size = max_t(u32, avg_wire_size, 5676 q_vector->tx.total_bytes / packets); 5677 5678 /* if avg_wire_size isn't set no work was done */ 5679 if (!avg_wire_size) 5680 goto clear_counts; 5681 5682 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5683 avg_wire_size += 24; 5684 5685 /* Don't starve jumbo frames */ 5686 avg_wire_size = min(avg_wire_size, 3000); 5687 5688 /* Give a little boost to mid-size frames */ 5689 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5690 new_val = avg_wire_size / 3; 5691 else 5692 new_val = avg_wire_size / 2; 5693 5694 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5695 if (new_val < IGB_20K_ITR && 5696 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5697 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5698 new_val = IGB_20K_ITR; 5699 5700 set_itr_val: 5701 if (new_val != q_vector->itr_val) { 5702 q_vector->itr_val = new_val; 5703 q_vector->set_itr = 1; 5704 } 5705 clear_counts: 5706 q_vector->rx.total_bytes = 0; 5707 q_vector->rx.total_packets = 0; 5708 q_vector->tx.total_bytes = 0; 5709 q_vector->tx.total_packets = 0; 5710 } 5711 5712 /** 5713 * igb_update_itr - update the dynamic ITR value based on statistics 5714 * @q_vector: pointer to q_vector 5715 * @ring_container: ring info to update the itr for 5716 * 5717 * Stores a new ITR value based on packets and byte 5718 * counts during the last interrupt. The advantage of per interrupt 5719 * computation is faster updates and more accurate ITR for the current 5720 * traffic pattern. Constants in this function were computed 5721 * based on theoretical maximum wire speed and thresholds were set based 5722 * on testing data as well as attempting to minimize response time 5723 * while increasing bulk throughput. 5724 * This functionality is controlled by ethtool's coalescing settings. 5725 * NOTE: These calculations are only valid when operating in a single- 5726 * queue environment. 5727 **/ 5728 static void igb_update_itr(struct igb_q_vector *q_vector, 5729 struct igb_ring_container *ring_container) 5730 { 5731 unsigned int packets = ring_container->total_packets; 5732 unsigned int bytes = ring_container->total_bytes; 5733 u8 itrval = ring_container->itr; 5734 5735 /* no packets, exit with status unchanged */ 5736 if (packets == 0) 5737 return; 5738 5739 switch (itrval) { 5740 case lowest_latency: 5741 /* handle TSO and jumbo frames */ 5742 if (bytes/packets > 8000) 5743 itrval = bulk_latency; 5744 else if ((packets < 5) && (bytes > 512)) 5745 itrval = low_latency; 5746 break; 5747 case low_latency: /* 50 usec aka 20000 ints/s */ 5748 if (bytes > 10000) { 5749 /* this if handles the TSO accounting */ 5750 if (bytes/packets > 8000) 5751 itrval = bulk_latency; 5752 else if ((packets < 10) || ((bytes/packets) > 1200)) 5753 itrval = bulk_latency; 5754 else if ((packets > 35)) 5755 itrval = lowest_latency; 5756 } else if (bytes/packets > 2000) { 5757 itrval = bulk_latency; 5758 } else if (packets <= 2 && bytes < 512) { 5759 itrval = lowest_latency; 5760 } 5761 break; 5762 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5763 if (bytes > 25000) { 5764 if (packets > 35) 5765 itrval = low_latency; 5766 } else if (bytes < 1500) { 5767 itrval = low_latency; 5768 } 5769 break; 5770 } 5771 5772 /* clear work counters since we have the values we need */ 5773 ring_container->total_bytes = 0; 5774 ring_container->total_packets = 0; 5775 5776 /* write updated itr to ring container */ 5777 ring_container->itr = itrval; 5778 } 5779 5780 static void igb_set_itr(struct igb_q_vector *q_vector) 5781 { 5782 struct igb_adapter *adapter = q_vector->adapter; 5783 u32 new_itr = q_vector->itr_val; 5784 u8 current_itr = 0; 5785 5786 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5787 if (adapter->link_speed != SPEED_1000) { 5788 current_itr = 0; 5789 new_itr = IGB_4K_ITR; 5790 goto set_itr_now; 5791 } 5792 5793 igb_update_itr(q_vector, &q_vector->tx); 5794 igb_update_itr(q_vector, &q_vector->rx); 5795 5796 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5797 5798 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5799 if (current_itr == lowest_latency && 5800 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5801 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5802 current_itr = low_latency; 5803 5804 switch (current_itr) { 5805 /* counts and packets in update_itr are dependent on these numbers */ 5806 case lowest_latency: 5807 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5808 break; 5809 case low_latency: 5810 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5811 break; 5812 case bulk_latency: 5813 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5814 break; 5815 default: 5816 break; 5817 } 5818 5819 set_itr_now: 5820 if (new_itr != q_vector->itr_val) { 5821 /* this attempts to bias the interrupt rate towards Bulk 5822 * by adding intermediate steps when interrupt rate is 5823 * increasing 5824 */ 5825 new_itr = new_itr > q_vector->itr_val ? 5826 max((new_itr * q_vector->itr_val) / 5827 (new_itr + (q_vector->itr_val >> 2)), 5828 new_itr) : new_itr; 5829 /* Don't write the value here; it resets the adapter's 5830 * internal timer, and causes us to delay far longer than 5831 * we should between interrupts. Instead, we write the ITR 5832 * value at the beginning of the next interrupt so the timing 5833 * ends up being correct. 5834 */ 5835 q_vector->itr_val = new_itr; 5836 q_vector->set_itr = 1; 5837 } 5838 } 5839 5840 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5841 struct igb_tx_buffer *first, 5842 u32 vlan_macip_lens, u32 type_tucmd, 5843 u32 mss_l4len_idx) 5844 { 5845 struct e1000_adv_tx_context_desc *context_desc; 5846 u16 i = tx_ring->next_to_use; 5847 struct timespec64 ts; 5848 5849 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5850 5851 i++; 5852 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5853 5854 /* set bits to identify this as an advanced context descriptor */ 5855 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5856 5857 /* For 82575, context index must be unique per ring. */ 5858 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5859 mss_l4len_idx |= tx_ring->reg_idx << 4; 5860 5861 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5862 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5863 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5864 5865 /* We assume there is always a valid tx time available. Invalid times 5866 * should have been handled by the upper layers. 5867 */ 5868 if (tx_ring->launchtime_enable) { 5869 ts = ktime_to_timespec64(first->skb->tstamp); 5870 skb_txtime_consumed(first->skb); 5871 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5872 } else { 5873 context_desc->seqnum_seed = 0; 5874 } 5875 } 5876 5877 static int igb_tso(struct igb_ring *tx_ring, 5878 struct igb_tx_buffer *first, 5879 u8 *hdr_len) 5880 { 5881 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5882 struct sk_buff *skb = first->skb; 5883 union { 5884 struct iphdr *v4; 5885 struct ipv6hdr *v6; 5886 unsigned char *hdr; 5887 } ip; 5888 union { 5889 struct tcphdr *tcp; 5890 struct udphdr *udp; 5891 unsigned char *hdr; 5892 } l4; 5893 u32 paylen, l4_offset; 5894 int err; 5895 5896 if (skb->ip_summed != CHECKSUM_PARTIAL) 5897 return 0; 5898 5899 if (!skb_is_gso(skb)) 5900 return 0; 5901 5902 err = skb_cow_head(skb, 0); 5903 if (err < 0) 5904 return err; 5905 5906 ip.hdr = skb_network_header(skb); 5907 l4.hdr = skb_checksum_start(skb); 5908 5909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5910 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5911 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5912 5913 /* initialize outer IP header fields */ 5914 if (ip.v4->version == 4) { 5915 unsigned char *csum_start = skb_checksum_start(skb); 5916 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5917 5918 /* IP header will have to cancel out any data that 5919 * is not a part of the outer IP header 5920 */ 5921 ip.v4->check = csum_fold(csum_partial(trans_start, 5922 csum_start - trans_start, 5923 0)); 5924 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5925 5926 ip.v4->tot_len = 0; 5927 first->tx_flags |= IGB_TX_FLAGS_TSO | 5928 IGB_TX_FLAGS_CSUM | 5929 IGB_TX_FLAGS_IPV4; 5930 } else { 5931 ip.v6->payload_len = 0; 5932 first->tx_flags |= IGB_TX_FLAGS_TSO | 5933 IGB_TX_FLAGS_CSUM; 5934 } 5935 5936 /* determine offset of inner transport header */ 5937 l4_offset = l4.hdr - skb->data; 5938 5939 /* remove payload length from inner checksum */ 5940 paylen = skb->len - l4_offset; 5941 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5942 /* compute length of segmentation header */ 5943 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5944 csum_replace_by_diff(&l4.tcp->check, 5945 (__force __wsum)htonl(paylen)); 5946 } else { 5947 /* compute length of segmentation header */ 5948 *hdr_len = sizeof(*l4.udp) + l4_offset; 5949 csum_replace_by_diff(&l4.udp->check, 5950 (__force __wsum)htonl(paylen)); 5951 } 5952 5953 /* update gso size and bytecount with header size */ 5954 first->gso_segs = skb_shinfo(skb)->gso_segs; 5955 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5956 5957 /* MSS L4LEN IDX */ 5958 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5959 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5960 5961 /* VLAN MACLEN IPLEN */ 5962 vlan_macip_lens = l4.hdr - ip.hdr; 5963 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5964 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5965 5966 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5967 type_tucmd, mss_l4len_idx); 5968 5969 return 1; 5970 } 5971 5972 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5973 { 5974 struct sk_buff *skb = first->skb; 5975 u32 vlan_macip_lens = 0; 5976 u32 type_tucmd = 0; 5977 5978 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5979 csum_failed: 5980 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5981 !tx_ring->launchtime_enable) 5982 return; 5983 goto no_csum; 5984 } 5985 5986 switch (skb->csum_offset) { 5987 case offsetof(struct tcphdr, check): 5988 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5989 fallthrough; 5990 case offsetof(struct udphdr, check): 5991 break; 5992 case offsetof(struct sctphdr, checksum): 5993 /* validate that this is actually an SCTP request */ 5994 if (skb_csum_is_sctp(skb)) { 5995 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5996 break; 5997 } 5998 fallthrough; 5999 default: 6000 skb_checksum_help(skb); 6001 goto csum_failed; 6002 } 6003 6004 /* update TX checksum flag */ 6005 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6006 vlan_macip_lens = skb_checksum_start_offset(skb) - 6007 skb_network_offset(skb); 6008 no_csum: 6009 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6010 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6011 6012 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6013 } 6014 6015 #define IGB_SET_FLAG(_input, _flag, _result) \ 6016 ((_flag <= _result) ? \ 6017 ((u32)(_input & _flag) * (_result / _flag)) : \ 6018 ((u32)(_input & _flag) / (_flag / _result))) 6019 6020 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6021 { 6022 /* set type for advanced descriptor with frame checksum insertion */ 6023 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6024 E1000_ADVTXD_DCMD_DEXT | 6025 E1000_ADVTXD_DCMD_IFCS; 6026 6027 /* set HW vlan bit if vlan is present */ 6028 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6029 (E1000_ADVTXD_DCMD_VLE)); 6030 6031 /* set segmentation bits for TSO */ 6032 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6033 (E1000_ADVTXD_DCMD_TSE)); 6034 6035 /* set timestamp bit if present */ 6036 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6037 (E1000_ADVTXD_MAC_TSTAMP)); 6038 6039 /* insert frame checksum */ 6040 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6041 6042 return cmd_type; 6043 } 6044 6045 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6046 union e1000_adv_tx_desc *tx_desc, 6047 u32 tx_flags, unsigned int paylen) 6048 { 6049 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6050 6051 /* 82575 requires a unique index per ring */ 6052 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6053 olinfo_status |= tx_ring->reg_idx << 4; 6054 6055 /* insert L4 checksum */ 6056 olinfo_status |= IGB_SET_FLAG(tx_flags, 6057 IGB_TX_FLAGS_CSUM, 6058 (E1000_TXD_POPTS_TXSM << 8)); 6059 6060 /* insert IPv4 checksum */ 6061 olinfo_status |= IGB_SET_FLAG(tx_flags, 6062 IGB_TX_FLAGS_IPV4, 6063 (E1000_TXD_POPTS_IXSM << 8)); 6064 6065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6066 } 6067 6068 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6069 { 6070 struct net_device *netdev = tx_ring->netdev; 6071 6072 netif_stop_subqueue(netdev, tx_ring->queue_index); 6073 6074 /* Herbert's original patch had: 6075 * smp_mb__after_netif_stop_queue(); 6076 * but since that doesn't exist yet, just open code it. 6077 */ 6078 smp_mb(); 6079 6080 /* We need to check again in a case another CPU has just 6081 * made room available. 6082 */ 6083 if (igb_desc_unused(tx_ring) < size) 6084 return -EBUSY; 6085 6086 /* A reprieve! */ 6087 netif_wake_subqueue(netdev, tx_ring->queue_index); 6088 6089 u64_stats_update_begin(&tx_ring->tx_syncp2); 6090 tx_ring->tx_stats.restart_queue2++; 6091 u64_stats_update_end(&tx_ring->tx_syncp2); 6092 6093 return 0; 6094 } 6095 6096 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6097 { 6098 if (igb_desc_unused(tx_ring) >= size) 6099 return 0; 6100 return __igb_maybe_stop_tx(tx_ring, size); 6101 } 6102 6103 static int igb_tx_map(struct igb_ring *tx_ring, 6104 struct igb_tx_buffer *first, 6105 const u8 hdr_len) 6106 { 6107 struct sk_buff *skb = first->skb; 6108 struct igb_tx_buffer *tx_buffer; 6109 union e1000_adv_tx_desc *tx_desc; 6110 skb_frag_t *frag; 6111 dma_addr_t dma; 6112 unsigned int data_len, size; 6113 u32 tx_flags = first->tx_flags; 6114 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6115 u16 i = tx_ring->next_to_use; 6116 6117 tx_desc = IGB_TX_DESC(tx_ring, i); 6118 6119 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6120 6121 size = skb_headlen(skb); 6122 data_len = skb->data_len; 6123 6124 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6125 6126 tx_buffer = first; 6127 6128 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6129 if (dma_mapping_error(tx_ring->dev, dma)) 6130 goto dma_error; 6131 6132 /* record length, and DMA address */ 6133 dma_unmap_len_set(tx_buffer, len, size); 6134 dma_unmap_addr_set(tx_buffer, dma, dma); 6135 6136 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6137 6138 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6139 tx_desc->read.cmd_type_len = 6140 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6141 6142 i++; 6143 tx_desc++; 6144 if (i == tx_ring->count) { 6145 tx_desc = IGB_TX_DESC(tx_ring, 0); 6146 i = 0; 6147 } 6148 tx_desc->read.olinfo_status = 0; 6149 6150 dma += IGB_MAX_DATA_PER_TXD; 6151 size -= IGB_MAX_DATA_PER_TXD; 6152 6153 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6154 } 6155 6156 if (likely(!data_len)) 6157 break; 6158 6159 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6160 6161 i++; 6162 tx_desc++; 6163 if (i == tx_ring->count) { 6164 tx_desc = IGB_TX_DESC(tx_ring, 0); 6165 i = 0; 6166 } 6167 tx_desc->read.olinfo_status = 0; 6168 6169 size = skb_frag_size(frag); 6170 data_len -= size; 6171 6172 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6173 size, DMA_TO_DEVICE); 6174 6175 tx_buffer = &tx_ring->tx_buffer_info[i]; 6176 } 6177 6178 /* write last descriptor with RS and EOP bits */ 6179 cmd_type |= size | IGB_TXD_DCMD; 6180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6181 6182 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6183 6184 /* set the timestamp */ 6185 first->time_stamp = jiffies; 6186 6187 skb_tx_timestamp(skb); 6188 6189 /* Force memory writes to complete before letting h/w know there 6190 * are new descriptors to fetch. (Only applicable for weak-ordered 6191 * memory model archs, such as IA-64). 6192 * 6193 * We also need this memory barrier to make certain all of the 6194 * status bits have been updated before next_to_watch is written. 6195 */ 6196 dma_wmb(); 6197 6198 /* set next_to_watch value indicating a packet is present */ 6199 first->next_to_watch = tx_desc; 6200 6201 i++; 6202 if (i == tx_ring->count) 6203 i = 0; 6204 6205 tx_ring->next_to_use = i; 6206 6207 /* Make sure there is space in the ring for the next send. */ 6208 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6209 6210 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6211 writel(i, tx_ring->tail); 6212 } 6213 return 0; 6214 6215 dma_error: 6216 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6217 tx_buffer = &tx_ring->tx_buffer_info[i]; 6218 6219 /* clear dma mappings for failed tx_buffer_info map */ 6220 while (tx_buffer != first) { 6221 if (dma_unmap_len(tx_buffer, len)) 6222 dma_unmap_page(tx_ring->dev, 6223 dma_unmap_addr(tx_buffer, dma), 6224 dma_unmap_len(tx_buffer, len), 6225 DMA_TO_DEVICE); 6226 dma_unmap_len_set(tx_buffer, len, 0); 6227 6228 if (i-- == 0) 6229 i += tx_ring->count; 6230 tx_buffer = &tx_ring->tx_buffer_info[i]; 6231 } 6232 6233 if (dma_unmap_len(tx_buffer, len)) 6234 dma_unmap_single(tx_ring->dev, 6235 dma_unmap_addr(tx_buffer, dma), 6236 dma_unmap_len(tx_buffer, len), 6237 DMA_TO_DEVICE); 6238 dma_unmap_len_set(tx_buffer, len, 0); 6239 6240 dev_kfree_skb_any(tx_buffer->skb); 6241 tx_buffer->skb = NULL; 6242 6243 tx_ring->next_to_use = i; 6244 6245 return -1; 6246 } 6247 6248 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6249 struct igb_ring *tx_ring, 6250 struct xdp_frame *xdpf) 6251 { 6252 union e1000_adv_tx_desc *tx_desc; 6253 u32 len, cmd_type, olinfo_status; 6254 struct igb_tx_buffer *tx_buffer; 6255 dma_addr_t dma; 6256 u16 i; 6257 6258 len = xdpf->len; 6259 6260 if (unlikely(!igb_desc_unused(tx_ring))) 6261 return IGB_XDP_CONSUMED; 6262 6263 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE); 6264 if (dma_mapping_error(tx_ring->dev, dma)) 6265 return IGB_XDP_CONSUMED; 6266 6267 /* record the location of the first descriptor for this packet */ 6268 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6269 tx_buffer->bytecount = len; 6270 tx_buffer->gso_segs = 1; 6271 tx_buffer->protocol = 0; 6272 6273 i = tx_ring->next_to_use; 6274 tx_desc = IGB_TX_DESC(tx_ring, i); 6275 6276 dma_unmap_len_set(tx_buffer, len, len); 6277 dma_unmap_addr_set(tx_buffer, dma, dma); 6278 tx_buffer->type = IGB_TYPE_XDP; 6279 tx_buffer->xdpf = xdpf; 6280 6281 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6282 6283 /* put descriptor type bits */ 6284 cmd_type = E1000_ADVTXD_DTYP_DATA | 6285 E1000_ADVTXD_DCMD_DEXT | 6286 E1000_ADVTXD_DCMD_IFCS; 6287 cmd_type |= len | IGB_TXD_DCMD; 6288 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6289 6290 olinfo_status = len << E1000_ADVTXD_PAYLEN_SHIFT; 6291 /* 82575 requires a unique index per ring */ 6292 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6293 olinfo_status |= tx_ring->reg_idx << 4; 6294 6295 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6296 6297 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount); 6298 6299 /* set the timestamp */ 6300 tx_buffer->time_stamp = jiffies; 6301 6302 /* Avoid any potential race with xdp_xmit and cleanup */ 6303 smp_wmb(); 6304 6305 /* set next_to_watch value indicating a packet is present */ 6306 i++; 6307 if (i == tx_ring->count) 6308 i = 0; 6309 6310 tx_buffer->next_to_watch = tx_desc; 6311 tx_ring->next_to_use = i; 6312 6313 /* Make sure there is space in the ring for the next send. */ 6314 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6315 6316 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6317 writel(i, tx_ring->tail); 6318 6319 return IGB_XDP_TX; 6320 } 6321 6322 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6323 struct igb_ring *tx_ring) 6324 { 6325 struct igb_tx_buffer *first; 6326 int tso; 6327 u32 tx_flags = 0; 6328 unsigned short f; 6329 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6330 __be16 protocol = vlan_get_protocol(skb); 6331 u8 hdr_len = 0; 6332 6333 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6334 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6335 * + 2 desc gap to keep tail from touching head, 6336 * + 1 desc for context descriptor, 6337 * otherwise try next time 6338 */ 6339 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6340 count += TXD_USE_COUNT(skb_frag_size( 6341 &skb_shinfo(skb)->frags[f])); 6342 6343 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6344 /* this is a hard error */ 6345 return NETDEV_TX_BUSY; 6346 } 6347 6348 /* record the location of the first descriptor for this packet */ 6349 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6350 first->type = IGB_TYPE_SKB; 6351 first->skb = skb; 6352 first->bytecount = skb->len; 6353 first->gso_segs = 1; 6354 6355 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6356 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6357 6358 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6359 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6360 &adapter->state)) { 6361 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6362 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6363 6364 adapter->ptp_tx_skb = skb_get(skb); 6365 adapter->ptp_tx_start = jiffies; 6366 if (adapter->hw.mac.type == e1000_82576) 6367 schedule_work(&adapter->ptp_tx_work); 6368 } else { 6369 adapter->tx_hwtstamp_skipped++; 6370 } 6371 } 6372 6373 if (skb_vlan_tag_present(skb)) { 6374 tx_flags |= IGB_TX_FLAGS_VLAN; 6375 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6376 } 6377 6378 /* record initial flags and protocol */ 6379 first->tx_flags = tx_flags; 6380 first->protocol = protocol; 6381 6382 tso = igb_tso(tx_ring, first, &hdr_len); 6383 if (tso < 0) 6384 goto out_drop; 6385 else if (!tso) 6386 igb_tx_csum(tx_ring, first); 6387 6388 if (igb_tx_map(tx_ring, first, hdr_len)) 6389 goto cleanup_tx_tstamp; 6390 6391 return NETDEV_TX_OK; 6392 6393 out_drop: 6394 dev_kfree_skb_any(first->skb); 6395 first->skb = NULL; 6396 cleanup_tx_tstamp: 6397 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6398 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6399 6400 dev_kfree_skb_any(adapter->ptp_tx_skb); 6401 adapter->ptp_tx_skb = NULL; 6402 if (adapter->hw.mac.type == e1000_82576) 6403 cancel_work_sync(&adapter->ptp_tx_work); 6404 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6405 } 6406 6407 return NETDEV_TX_OK; 6408 } 6409 6410 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6411 struct sk_buff *skb) 6412 { 6413 unsigned int r_idx = skb->queue_mapping; 6414 6415 if (r_idx >= adapter->num_tx_queues) 6416 r_idx = r_idx % adapter->num_tx_queues; 6417 6418 return adapter->tx_ring[r_idx]; 6419 } 6420 6421 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6422 struct net_device *netdev) 6423 { 6424 struct igb_adapter *adapter = netdev_priv(netdev); 6425 6426 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6427 * in order to meet this minimum size requirement. 6428 */ 6429 if (skb_put_padto(skb, 17)) 6430 return NETDEV_TX_OK; 6431 6432 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6433 } 6434 6435 /** 6436 * igb_tx_timeout - Respond to a Tx Hang 6437 * @netdev: network interface device structure 6438 * @txqueue: number of the Tx queue that hung (unused) 6439 **/ 6440 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6441 { 6442 struct igb_adapter *adapter = netdev_priv(netdev); 6443 struct e1000_hw *hw = &adapter->hw; 6444 6445 /* Do the reset outside of interrupt context */ 6446 adapter->tx_timeout_count++; 6447 6448 if (hw->mac.type >= e1000_82580) 6449 hw->dev_spec._82575.global_device_reset = true; 6450 6451 schedule_work(&adapter->reset_task); 6452 wr32(E1000_EICS, 6453 (adapter->eims_enable_mask & ~adapter->eims_other)); 6454 } 6455 6456 static void igb_reset_task(struct work_struct *work) 6457 { 6458 struct igb_adapter *adapter; 6459 adapter = container_of(work, struct igb_adapter, reset_task); 6460 6461 rtnl_lock(); 6462 /* If we're already down or resetting, just bail */ 6463 if (test_bit(__IGB_DOWN, &adapter->state) || 6464 test_bit(__IGB_RESETTING, &adapter->state)) { 6465 rtnl_unlock(); 6466 return; 6467 } 6468 6469 igb_dump(adapter); 6470 netdev_err(adapter->netdev, "Reset adapter\n"); 6471 igb_reinit_locked(adapter); 6472 rtnl_unlock(); 6473 } 6474 6475 /** 6476 * igb_get_stats64 - Get System Network Statistics 6477 * @netdev: network interface device structure 6478 * @stats: rtnl_link_stats64 pointer 6479 **/ 6480 static void igb_get_stats64(struct net_device *netdev, 6481 struct rtnl_link_stats64 *stats) 6482 { 6483 struct igb_adapter *adapter = netdev_priv(netdev); 6484 6485 spin_lock(&adapter->stats64_lock); 6486 igb_update_stats(adapter); 6487 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6488 spin_unlock(&adapter->stats64_lock); 6489 } 6490 6491 /** 6492 * igb_change_mtu - Change the Maximum Transfer Unit 6493 * @netdev: network interface device structure 6494 * @new_mtu: new value for maximum frame size 6495 * 6496 * Returns 0 on success, negative on failure 6497 **/ 6498 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6499 { 6500 struct igb_adapter *adapter = netdev_priv(netdev); 6501 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6502 6503 if (adapter->xdp_prog) { 6504 int i; 6505 6506 for (i = 0; i < adapter->num_rx_queues; i++) { 6507 struct igb_ring *ring = adapter->rx_ring[i]; 6508 6509 if (max_frame > igb_rx_bufsz(ring)) { 6510 netdev_warn(adapter->netdev, 6511 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6512 max_frame); 6513 return -EINVAL; 6514 } 6515 } 6516 } 6517 6518 /* adjust max frame to be at least the size of a standard frame */ 6519 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6520 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6521 6522 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6523 usleep_range(1000, 2000); 6524 6525 /* igb_down has a dependency on max_frame_size */ 6526 adapter->max_frame_size = max_frame; 6527 6528 if (netif_running(netdev)) 6529 igb_down(adapter); 6530 6531 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6532 netdev->mtu, new_mtu); 6533 netdev->mtu = new_mtu; 6534 6535 if (netif_running(netdev)) 6536 igb_up(adapter); 6537 else 6538 igb_reset(adapter); 6539 6540 clear_bit(__IGB_RESETTING, &adapter->state); 6541 6542 return 0; 6543 } 6544 6545 /** 6546 * igb_update_stats - Update the board statistics counters 6547 * @adapter: board private structure 6548 **/ 6549 void igb_update_stats(struct igb_adapter *adapter) 6550 { 6551 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6552 struct e1000_hw *hw = &adapter->hw; 6553 struct pci_dev *pdev = adapter->pdev; 6554 u32 reg, mpc; 6555 int i; 6556 u64 bytes, packets; 6557 unsigned int start; 6558 u64 _bytes, _packets; 6559 6560 /* Prevent stats update while adapter is being reset, or if the pci 6561 * connection is down. 6562 */ 6563 if (adapter->link_speed == 0) 6564 return; 6565 if (pci_channel_offline(pdev)) 6566 return; 6567 6568 bytes = 0; 6569 packets = 0; 6570 6571 rcu_read_lock(); 6572 for (i = 0; i < adapter->num_rx_queues; i++) { 6573 struct igb_ring *ring = adapter->rx_ring[i]; 6574 u32 rqdpc = rd32(E1000_RQDPC(i)); 6575 if (hw->mac.type >= e1000_i210) 6576 wr32(E1000_RQDPC(i), 0); 6577 6578 if (rqdpc) { 6579 ring->rx_stats.drops += rqdpc; 6580 net_stats->rx_fifo_errors += rqdpc; 6581 } 6582 6583 do { 6584 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6585 _bytes = ring->rx_stats.bytes; 6586 _packets = ring->rx_stats.packets; 6587 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6588 bytes += _bytes; 6589 packets += _packets; 6590 } 6591 6592 net_stats->rx_bytes = bytes; 6593 net_stats->rx_packets = packets; 6594 6595 bytes = 0; 6596 packets = 0; 6597 for (i = 0; i < adapter->num_tx_queues; i++) { 6598 struct igb_ring *ring = adapter->tx_ring[i]; 6599 do { 6600 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6601 _bytes = ring->tx_stats.bytes; 6602 _packets = ring->tx_stats.packets; 6603 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6604 bytes += _bytes; 6605 packets += _packets; 6606 } 6607 net_stats->tx_bytes = bytes; 6608 net_stats->tx_packets = packets; 6609 rcu_read_unlock(); 6610 6611 /* read stats registers */ 6612 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6613 adapter->stats.gprc += rd32(E1000_GPRC); 6614 adapter->stats.gorc += rd32(E1000_GORCL); 6615 rd32(E1000_GORCH); /* clear GORCL */ 6616 adapter->stats.bprc += rd32(E1000_BPRC); 6617 adapter->stats.mprc += rd32(E1000_MPRC); 6618 adapter->stats.roc += rd32(E1000_ROC); 6619 6620 adapter->stats.prc64 += rd32(E1000_PRC64); 6621 adapter->stats.prc127 += rd32(E1000_PRC127); 6622 adapter->stats.prc255 += rd32(E1000_PRC255); 6623 adapter->stats.prc511 += rd32(E1000_PRC511); 6624 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6625 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6626 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6627 adapter->stats.sec += rd32(E1000_SEC); 6628 6629 mpc = rd32(E1000_MPC); 6630 adapter->stats.mpc += mpc; 6631 net_stats->rx_fifo_errors += mpc; 6632 adapter->stats.scc += rd32(E1000_SCC); 6633 adapter->stats.ecol += rd32(E1000_ECOL); 6634 adapter->stats.mcc += rd32(E1000_MCC); 6635 adapter->stats.latecol += rd32(E1000_LATECOL); 6636 adapter->stats.dc += rd32(E1000_DC); 6637 adapter->stats.rlec += rd32(E1000_RLEC); 6638 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6639 adapter->stats.xontxc += rd32(E1000_XONTXC); 6640 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6641 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6642 adapter->stats.fcruc += rd32(E1000_FCRUC); 6643 adapter->stats.gptc += rd32(E1000_GPTC); 6644 adapter->stats.gotc += rd32(E1000_GOTCL); 6645 rd32(E1000_GOTCH); /* clear GOTCL */ 6646 adapter->stats.rnbc += rd32(E1000_RNBC); 6647 adapter->stats.ruc += rd32(E1000_RUC); 6648 adapter->stats.rfc += rd32(E1000_RFC); 6649 adapter->stats.rjc += rd32(E1000_RJC); 6650 adapter->stats.tor += rd32(E1000_TORH); 6651 adapter->stats.tot += rd32(E1000_TOTH); 6652 adapter->stats.tpr += rd32(E1000_TPR); 6653 6654 adapter->stats.ptc64 += rd32(E1000_PTC64); 6655 adapter->stats.ptc127 += rd32(E1000_PTC127); 6656 adapter->stats.ptc255 += rd32(E1000_PTC255); 6657 adapter->stats.ptc511 += rd32(E1000_PTC511); 6658 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6659 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6660 6661 adapter->stats.mptc += rd32(E1000_MPTC); 6662 adapter->stats.bptc += rd32(E1000_BPTC); 6663 6664 adapter->stats.tpt += rd32(E1000_TPT); 6665 adapter->stats.colc += rd32(E1000_COLC); 6666 6667 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6668 /* read internal phy specific stats */ 6669 reg = rd32(E1000_CTRL_EXT); 6670 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6671 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6672 6673 /* this stat has invalid values on i210/i211 */ 6674 if ((hw->mac.type != e1000_i210) && 6675 (hw->mac.type != e1000_i211)) 6676 adapter->stats.tncrs += rd32(E1000_TNCRS); 6677 } 6678 6679 adapter->stats.tsctc += rd32(E1000_TSCTC); 6680 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6681 6682 adapter->stats.iac += rd32(E1000_IAC); 6683 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6684 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6685 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6686 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6687 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6688 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6689 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6690 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6691 6692 /* Fill out the OS statistics structure */ 6693 net_stats->multicast = adapter->stats.mprc; 6694 net_stats->collisions = adapter->stats.colc; 6695 6696 /* Rx Errors */ 6697 6698 /* RLEC on some newer hardware can be incorrect so build 6699 * our own version based on RUC and ROC 6700 */ 6701 net_stats->rx_errors = adapter->stats.rxerrc + 6702 adapter->stats.crcerrs + adapter->stats.algnerrc + 6703 adapter->stats.ruc + adapter->stats.roc + 6704 adapter->stats.cexterr; 6705 net_stats->rx_length_errors = adapter->stats.ruc + 6706 adapter->stats.roc; 6707 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6708 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6709 net_stats->rx_missed_errors = adapter->stats.mpc; 6710 6711 /* Tx Errors */ 6712 net_stats->tx_errors = adapter->stats.ecol + 6713 adapter->stats.latecol; 6714 net_stats->tx_aborted_errors = adapter->stats.ecol; 6715 net_stats->tx_window_errors = adapter->stats.latecol; 6716 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6717 6718 /* Tx Dropped needs to be maintained elsewhere */ 6719 6720 /* Management Stats */ 6721 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6722 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6723 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6724 6725 /* OS2BMC Stats */ 6726 reg = rd32(E1000_MANC); 6727 if (reg & E1000_MANC_EN_BMC2OS) { 6728 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6729 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6730 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6731 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6732 } 6733 } 6734 6735 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6736 { 6737 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6738 struct e1000_hw *hw = &adapter->hw; 6739 struct timespec64 ts; 6740 u32 tsauxc; 6741 6742 if (pin < 0 || pin >= IGB_N_PEROUT) 6743 return; 6744 6745 spin_lock(&adapter->tmreg_lock); 6746 6747 if (hw->mac.type == e1000_82580 || 6748 hw->mac.type == e1000_i354 || 6749 hw->mac.type == e1000_i350) { 6750 s64 ns = timespec64_to_ns(&adapter->perout[pin].period); 6751 u32 systiml, systimh, level_mask, level, rem; 6752 u64 systim, now; 6753 6754 /* read systim registers in sequence */ 6755 rd32(E1000_SYSTIMR); 6756 systiml = rd32(E1000_SYSTIML); 6757 systimh = rd32(E1000_SYSTIMH); 6758 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6759 now = timecounter_cyc2time(&adapter->tc, systim); 6760 6761 if (pin < 2) { 6762 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6763 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6764 } else { 6765 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6766 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6767 } 6768 6769 div_u64_rem(now, ns, &rem); 6770 systim = systim + (ns - rem); 6771 6772 /* synchronize pin level with rising/falling edges */ 6773 div_u64_rem(now, ns << 1, &rem); 6774 if (rem < ns) { 6775 /* first half of period */ 6776 if (level == 0) { 6777 /* output is already low, skip this period */ 6778 systim += ns; 6779 pr_notice("igb: periodic output on %s missed falling edge\n", 6780 adapter->sdp_config[pin].name); 6781 } 6782 } else { 6783 /* second half of period */ 6784 if (level == 1) { 6785 /* output is already high, skip this period */ 6786 systim += ns; 6787 pr_notice("igb: periodic output on %s missed rising edge\n", 6788 adapter->sdp_config[pin].name); 6789 } 6790 } 6791 6792 /* for this chip family tv_sec is the upper part of the binary value, 6793 * so not seconds 6794 */ 6795 ts.tv_nsec = (u32)systim; 6796 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6797 } else { 6798 ts = timespec64_add(adapter->perout[pin].start, 6799 adapter->perout[pin].period); 6800 } 6801 6802 /* u32 conversion of tv_sec is safe until y2106 */ 6803 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6804 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6805 tsauxc = rd32(E1000_TSAUXC); 6806 tsauxc |= TSAUXC_EN_TT0; 6807 wr32(E1000_TSAUXC, tsauxc); 6808 adapter->perout[pin].start = ts; 6809 6810 spin_unlock(&adapter->tmreg_lock); 6811 } 6812 6813 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6814 { 6815 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6816 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6817 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6818 struct e1000_hw *hw = &adapter->hw; 6819 struct ptp_clock_event event; 6820 struct timespec64 ts; 6821 6822 if (pin < 0 || pin >= IGB_N_EXTTS) 6823 return; 6824 6825 if (hw->mac.type == e1000_82580 || 6826 hw->mac.type == e1000_i354 || 6827 hw->mac.type == e1000_i350) { 6828 s64 ns = rd32(auxstmpl); 6829 6830 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6831 ts = ns_to_timespec64(ns); 6832 } else { 6833 ts.tv_nsec = rd32(auxstmpl); 6834 ts.tv_sec = rd32(auxstmph); 6835 } 6836 6837 event.type = PTP_CLOCK_EXTTS; 6838 event.index = tsintr_tt; 6839 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6840 ptp_clock_event(adapter->ptp_clock, &event); 6841 } 6842 6843 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6844 { 6845 struct e1000_hw *hw = &adapter->hw; 6846 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6847 struct ptp_clock_event event; 6848 6849 if (tsicr & TSINTR_SYS_WRAP) { 6850 event.type = PTP_CLOCK_PPS; 6851 if (adapter->ptp_caps.pps) 6852 ptp_clock_event(adapter->ptp_clock, &event); 6853 ack |= TSINTR_SYS_WRAP; 6854 } 6855 6856 if (tsicr & E1000_TSICR_TXTS) { 6857 /* retrieve hardware timestamp */ 6858 schedule_work(&adapter->ptp_tx_work); 6859 ack |= E1000_TSICR_TXTS; 6860 } 6861 6862 if (tsicr & TSINTR_TT0) { 6863 igb_perout(adapter, 0); 6864 ack |= TSINTR_TT0; 6865 } 6866 6867 if (tsicr & TSINTR_TT1) { 6868 igb_perout(adapter, 1); 6869 ack |= TSINTR_TT1; 6870 } 6871 6872 if (tsicr & TSINTR_AUTT0) { 6873 igb_extts(adapter, 0); 6874 ack |= TSINTR_AUTT0; 6875 } 6876 6877 if (tsicr & TSINTR_AUTT1) { 6878 igb_extts(adapter, 1); 6879 ack |= TSINTR_AUTT1; 6880 } 6881 6882 /* acknowledge the interrupts */ 6883 wr32(E1000_TSICR, ack); 6884 } 6885 6886 static irqreturn_t igb_msix_other(int irq, void *data) 6887 { 6888 struct igb_adapter *adapter = data; 6889 struct e1000_hw *hw = &adapter->hw; 6890 u32 icr = rd32(E1000_ICR); 6891 /* reading ICR causes bit 31 of EICR to be cleared */ 6892 6893 if (icr & E1000_ICR_DRSTA) 6894 schedule_work(&adapter->reset_task); 6895 6896 if (icr & E1000_ICR_DOUTSYNC) { 6897 /* HW is reporting DMA is out of sync */ 6898 adapter->stats.doosync++; 6899 /* The DMA Out of Sync is also indication of a spoof event 6900 * in IOV mode. Check the Wrong VM Behavior register to 6901 * see if it is really a spoof event. 6902 */ 6903 igb_check_wvbr(adapter); 6904 } 6905 6906 /* Check for a mailbox event */ 6907 if (icr & E1000_ICR_VMMB) 6908 igb_msg_task(adapter); 6909 6910 if (icr & E1000_ICR_LSC) { 6911 hw->mac.get_link_status = 1; 6912 /* guard against interrupt when we're going down */ 6913 if (!test_bit(__IGB_DOWN, &adapter->state)) 6914 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6915 } 6916 6917 if (icr & E1000_ICR_TS) 6918 igb_tsync_interrupt(adapter); 6919 6920 wr32(E1000_EIMS, adapter->eims_other); 6921 6922 return IRQ_HANDLED; 6923 } 6924 6925 static void igb_write_itr(struct igb_q_vector *q_vector) 6926 { 6927 struct igb_adapter *adapter = q_vector->adapter; 6928 u32 itr_val = q_vector->itr_val & 0x7FFC; 6929 6930 if (!q_vector->set_itr) 6931 return; 6932 6933 if (!itr_val) 6934 itr_val = 0x4; 6935 6936 if (adapter->hw.mac.type == e1000_82575) 6937 itr_val |= itr_val << 16; 6938 else 6939 itr_val |= E1000_EITR_CNT_IGNR; 6940 6941 writel(itr_val, q_vector->itr_register); 6942 q_vector->set_itr = 0; 6943 } 6944 6945 static irqreturn_t igb_msix_ring(int irq, void *data) 6946 { 6947 struct igb_q_vector *q_vector = data; 6948 6949 /* Write the ITR value calculated from the previous interrupt. */ 6950 igb_write_itr(q_vector); 6951 6952 napi_schedule(&q_vector->napi); 6953 6954 return IRQ_HANDLED; 6955 } 6956 6957 #ifdef CONFIG_IGB_DCA 6958 static void igb_update_tx_dca(struct igb_adapter *adapter, 6959 struct igb_ring *tx_ring, 6960 int cpu) 6961 { 6962 struct e1000_hw *hw = &adapter->hw; 6963 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6964 6965 if (hw->mac.type != e1000_82575) 6966 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6967 6968 /* We can enable relaxed ordering for reads, but not writes when 6969 * DCA is enabled. This is due to a known issue in some chipsets 6970 * which will cause the DCA tag to be cleared. 6971 */ 6972 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6973 E1000_DCA_TXCTRL_DATA_RRO_EN | 6974 E1000_DCA_TXCTRL_DESC_DCA_EN; 6975 6976 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6977 } 6978 6979 static void igb_update_rx_dca(struct igb_adapter *adapter, 6980 struct igb_ring *rx_ring, 6981 int cpu) 6982 { 6983 struct e1000_hw *hw = &adapter->hw; 6984 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6985 6986 if (hw->mac.type != e1000_82575) 6987 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6988 6989 /* We can enable relaxed ordering for reads, but not writes when 6990 * DCA is enabled. This is due to a known issue in some chipsets 6991 * which will cause the DCA tag to be cleared. 6992 */ 6993 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6994 E1000_DCA_RXCTRL_DESC_DCA_EN; 6995 6996 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6997 } 6998 6999 static void igb_update_dca(struct igb_q_vector *q_vector) 7000 { 7001 struct igb_adapter *adapter = q_vector->adapter; 7002 int cpu = get_cpu(); 7003 7004 if (q_vector->cpu == cpu) 7005 goto out_no_update; 7006 7007 if (q_vector->tx.ring) 7008 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7009 7010 if (q_vector->rx.ring) 7011 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7012 7013 q_vector->cpu = cpu; 7014 out_no_update: 7015 put_cpu(); 7016 } 7017 7018 static void igb_setup_dca(struct igb_adapter *adapter) 7019 { 7020 struct e1000_hw *hw = &adapter->hw; 7021 int i; 7022 7023 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7024 return; 7025 7026 /* Always use CB2 mode, difference is masked in the CB driver. */ 7027 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7028 7029 for (i = 0; i < adapter->num_q_vectors; i++) { 7030 adapter->q_vector[i]->cpu = -1; 7031 igb_update_dca(adapter->q_vector[i]); 7032 } 7033 } 7034 7035 static int __igb_notify_dca(struct device *dev, void *data) 7036 { 7037 struct net_device *netdev = dev_get_drvdata(dev); 7038 struct igb_adapter *adapter = netdev_priv(netdev); 7039 struct pci_dev *pdev = adapter->pdev; 7040 struct e1000_hw *hw = &adapter->hw; 7041 unsigned long event = *(unsigned long *)data; 7042 7043 switch (event) { 7044 case DCA_PROVIDER_ADD: 7045 /* if already enabled, don't do it again */ 7046 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7047 break; 7048 if (dca_add_requester(dev) == 0) { 7049 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7050 dev_info(&pdev->dev, "DCA enabled\n"); 7051 igb_setup_dca(adapter); 7052 break; 7053 } 7054 fallthrough; /* since DCA is disabled. */ 7055 case DCA_PROVIDER_REMOVE: 7056 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7057 /* without this a class_device is left 7058 * hanging around in the sysfs model 7059 */ 7060 dca_remove_requester(dev); 7061 dev_info(&pdev->dev, "DCA disabled\n"); 7062 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7063 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7064 } 7065 break; 7066 } 7067 7068 return 0; 7069 } 7070 7071 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7072 void *p) 7073 { 7074 int ret_val; 7075 7076 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7077 __igb_notify_dca); 7078 7079 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7080 } 7081 #endif /* CONFIG_IGB_DCA */ 7082 7083 #ifdef CONFIG_PCI_IOV 7084 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7085 { 7086 unsigned char mac_addr[ETH_ALEN]; 7087 7088 eth_zero_addr(mac_addr); 7089 igb_set_vf_mac(adapter, vf, mac_addr); 7090 7091 /* By default spoof check is enabled for all VFs */ 7092 adapter->vf_data[vf].spoofchk_enabled = true; 7093 7094 /* By default VFs are not trusted */ 7095 adapter->vf_data[vf].trusted = false; 7096 7097 return 0; 7098 } 7099 7100 #endif 7101 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7102 { 7103 struct e1000_hw *hw = &adapter->hw; 7104 u32 ping; 7105 int i; 7106 7107 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7108 ping = E1000_PF_CONTROL_MSG; 7109 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7110 ping |= E1000_VT_MSGTYPE_CTS; 7111 igb_write_mbx(hw, &ping, 1, i); 7112 } 7113 } 7114 7115 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7116 { 7117 struct e1000_hw *hw = &adapter->hw; 7118 u32 vmolr = rd32(E1000_VMOLR(vf)); 7119 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7120 7121 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7122 IGB_VF_FLAG_MULTI_PROMISC); 7123 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7124 7125 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7126 vmolr |= E1000_VMOLR_MPME; 7127 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7128 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7129 } else { 7130 /* if we have hashes and we are clearing a multicast promisc 7131 * flag we need to write the hashes to the MTA as this step 7132 * was previously skipped 7133 */ 7134 if (vf_data->num_vf_mc_hashes > 30) { 7135 vmolr |= E1000_VMOLR_MPME; 7136 } else if (vf_data->num_vf_mc_hashes) { 7137 int j; 7138 7139 vmolr |= E1000_VMOLR_ROMPE; 7140 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7141 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7142 } 7143 } 7144 7145 wr32(E1000_VMOLR(vf), vmolr); 7146 7147 /* there are flags left unprocessed, likely not supported */ 7148 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7149 return -EINVAL; 7150 7151 return 0; 7152 } 7153 7154 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7155 u32 *msgbuf, u32 vf) 7156 { 7157 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7158 u16 *hash_list = (u16 *)&msgbuf[1]; 7159 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7160 int i; 7161 7162 /* salt away the number of multicast addresses assigned 7163 * to this VF for later use to restore when the PF multi cast 7164 * list changes 7165 */ 7166 vf_data->num_vf_mc_hashes = n; 7167 7168 /* only up to 30 hash values supported */ 7169 if (n > 30) 7170 n = 30; 7171 7172 /* store the hashes for later use */ 7173 for (i = 0; i < n; i++) 7174 vf_data->vf_mc_hashes[i] = hash_list[i]; 7175 7176 /* Flush and reset the mta with the new values */ 7177 igb_set_rx_mode(adapter->netdev); 7178 7179 return 0; 7180 } 7181 7182 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7183 { 7184 struct e1000_hw *hw = &adapter->hw; 7185 struct vf_data_storage *vf_data; 7186 int i, j; 7187 7188 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7189 u32 vmolr = rd32(E1000_VMOLR(i)); 7190 7191 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7192 7193 vf_data = &adapter->vf_data[i]; 7194 7195 if ((vf_data->num_vf_mc_hashes > 30) || 7196 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7197 vmolr |= E1000_VMOLR_MPME; 7198 } else if (vf_data->num_vf_mc_hashes) { 7199 vmolr |= E1000_VMOLR_ROMPE; 7200 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7201 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7202 } 7203 wr32(E1000_VMOLR(i), vmolr); 7204 } 7205 } 7206 7207 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7208 { 7209 struct e1000_hw *hw = &adapter->hw; 7210 u32 pool_mask, vlvf_mask, i; 7211 7212 /* create mask for VF and other pools */ 7213 pool_mask = E1000_VLVF_POOLSEL_MASK; 7214 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7215 7216 /* drop PF from pool bits */ 7217 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7218 adapter->vfs_allocated_count); 7219 7220 /* Find the vlan filter for this id */ 7221 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7222 u32 vlvf = rd32(E1000_VLVF(i)); 7223 u32 vfta_mask, vid, vfta; 7224 7225 /* remove the vf from the pool */ 7226 if (!(vlvf & vlvf_mask)) 7227 continue; 7228 7229 /* clear out bit from VLVF */ 7230 vlvf ^= vlvf_mask; 7231 7232 /* if other pools are present, just remove ourselves */ 7233 if (vlvf & pool_mask) 7234 goto update_vlvfb; 7235 7236 /* if PF is present, leave VFTA */ 7237 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7238 goto update_vlvf; 7239 7240 vid = vlvf & E1000_VLVF_VLANID_MASK; 7241 vfta_mask = BIT(vid % 32); 7242 7243 /* clear bit from VFTA */ 7244 vfta = adapter->shadow_vfta[vid / 32]; 7245 if (vfta & vfta_mask) 7246 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7247 update_vlvf: 7248 /* clear pool selection enable */ 7249 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7250 vlvf &= E1000_VLVF_POOLSEL_MASK; 7251 else 7252 vlvf = 0; 7253 update_vlvfb: 7254 /* clear pool bits */ 7255 wr32(E1000_VLVF(i), vlvf); 7256 } 7257 } 7258 7259 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7260 { 7261 u32 vlvf; 7262 int idx; 7263 7264 /* short cut the special case */ 7265 if (vlan == 0) 7266 return 0; 7267 7268 /* Search for the VLAN id in the VLVF entries */ 7269 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7270 vlvf = rd32(E1000_VLVF(idx)); 7271 if ((vlvf & VLAN_VID_MASK) == vlan) 7272 break; 7273 } 7274 7275 return idx; 7276 } 7277 7278 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7279 { 7280 struct e1000_hw *hw = &adapter->hw; 7281 u32 bits, pf_id; 7282 int idx; 7283 7284 idx = igb_find_vlvf_entry(hw, vid); 7285 if (!idx) 7286 return; 7287 7288 /* See if any other pools are set for this VLAN filter 7289 * entry other than the PF. 7290 */ 7291 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7292 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7293 bits &= rd32(E1000_VLVF(idx)); 7294 7295 /* Disable the filter so this falls into the default pool. */ 7296 if (!bits) { 7297 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7298 wr32(E1000_VLVF(idx), BIT(pf_id)); 7299 else 7300 wr32(E1000_VLVF(idx), 0); 7301 } 7302 } 7303 7304 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7305 bool add, u32 vf) 7306 { 7307 int pf_id = adapter->vfs_allocated_count; 7308 struct e1000_hw *hw = &adapter->hw; 7309 int err; 7310 7311 /* If VLAN overlaps with one the PF is currently monitoring make 7312 * sure that we are able to allocate a VLVF entry. This may be 7313 * redundant but it guarantees PF will maintain visibility to 7314 * the VLAN. 7315 */ 7316 if (add && test_bit(vid, adapter->active_vlans)) { 7317 err = igb_vfta_set(hw, vid, pf_id, true, false); 7318 if (err) 7319 return err; 7320 } 7321 7322 err = igb_vfta_set(hw, vid, vf, add, false); 7323 7324 if (add && !err) 7325 return err; 7326 7327 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7328 * we may need to drop the PF pool bit in order to allow us to free 7329 * up the VLVF resources. 7330 */ 7331 if (test_bit(vid, adapter->active_vlans) || 7332 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7333 igb_update_pf_vlvf(adapter, vid); 7334 7335 return err; 7336 } 7337 7338 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7339 { 7340 struct e1000_hw *hw = &adapter->hw; 7341 7342 if (vid) 7343 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7344 else 7345 wr32(E1000_VMVIR(vf), 0); 7346 } 7347 7348 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7349 u16 vlan, u8 qos) 7350 { 7351 int err; 7352 7353 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7354 if (err) 7355 return err; 7356 7357 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7358 igb_set_vmolr(adapter, vf, !vlan); 7359 7360 /* revoke access to previous VLAN */ 7361 if (vlan != adapter->vf_data[vf].pf_vlan) 7362 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7363 false, vf); 7364 7365 adapter->vf_data[vf].pf_vlan = vlan; 7366 adapter->vf_data[vf].pf_qos = qos; 7367 igb_set_vf_vlan_strip(adapter, vf, true); 7368 dev_info(&adapter->pdev->dev, 7369 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7370 if (test_bit(__IGB_DOWN, &adapter->state)) { 7371 dev_warn(&adapter->pdev->dev, 7372 "The VF VLAN has been set, but the PF device is not up.\n"); 7373 dev_warn(&adapter->pdev->dev, 7374 "Bring the PF device up before attempting to use the VF device.\n"); 7375 } 7376 7377 return err; 7378 } 7379 7380 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7381 { 7382 /* Restore tagless access via VLAN 0 */ 7383 igb_set_vf_vlan(adapter, 0, true, vf); 7384 7385 igb_set_vmvir(adapter, 0, vf); 7386 igb_set_vmolr(adapter, vf, true); 7387 7388 /* Remove any PF assigned VLAN */ 7389 if (adapter->vf_data[vf].pf_vlan) 7390 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7391 false, vf); 7392 7393 adapter->vf_data[vf].pf_vlan = 0; 7394 adapter->vf_data[vf].pf_qos = 0; 7395 igb_set_vf_vlan_strip(adapter, vf, false); 7396 7397 return 0; 7398 } 7399 7400 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7401 u16 vlan, u8 qos, __be16 vlan_proto) 7402 { 7403 struct igb_adapter *adapter = netdev_priv(netdev); 7404 7405 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7406 return -EINVAL; 7407 7408 if (vlan_proto != htons(ETH_P_8021Q)) 7409 return -EPROTONOSUPPORT; 7410 7411 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7412 igb_disable_port_vlan(adapter, vf); 7413 } 7414 7415 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7416 { 7417 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7418 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7419 int ret; 7420 7421 if (adapter->vf_data[vf].pf_vlan) 7422 return -1; 7423 7424 /* VLAN 0 is a special case, don't allow it to be removed */ 7425 if (!vid && !add) 7426 return 0; 7427 7428 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7429 if (!ret) 7430 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7431 return ret; 7432 } 7433 7434 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7435 { 7436 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7437 7438 /* clear flags - except flag that indicates PF has set the MAC */ 7439 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7440 vf_data->last_nack = jiffies; 7441 7442 /* reset vlans for device */ 7443 igb_clear_vf_vfta(adapter, vf); 7444 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7445 igb_set_vmvir(adapter, vf_data->pf_vlan | 7446 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7447 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7448 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7449 7450 /* reset multicast table array for vf */ 7451 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7452 7453 /* Flush and reset the mta with the new values */ 7454 igb_set_rx_mode(adapter->netdev); 7455 } 7456 7457 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7458 { 7459 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7460 7461 /* clear mac address as we were hotplug removed/added */ 7462 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7463 eth_zero_addr(vf_mac); 7464 7465 /* process remaining reset events */ 7466 igb_vf_reset(adapter, vf); 7467 } 7468 7469 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7470 { 7471 struct e1000_hw *hw = &adapter->hw; 7472 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7473 u32 reg, msgbuf[3]; 7474 u8 *addr = (u8 *)(&msgbuf[1]); 7475 7476 /* process all the same items cleared in a function level reset */ 7477 igb_vf_reset(adapter, vf); 7478 7479 /* set vf mac address */ 7480 igb_set_vf_mac(adapter, vf, vf_mac); 7481 7482 /* enable transmit and receive for vf */ 7483 reg = rd32(E1000_VFTE); 7484 wr32(E1000_VFTE, reg | BIT(vf)); 7485 reg = rd32(E1000_VFRE); 7486 wr32(E1000_VFRE, reg | BIT(vf)); 7487 7488 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7489 7490 /* reply to reset with ack and vf mac address */ 7491 if (!is_zero_ether_addr(vf_mac)) { 7492 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7493 memcpy(addr, vf_mac, ETH_ALEN); 7494 } else { 7495 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7496 } 7497 igb_write_mbx(hw, msgbuf, 3, vf); 7498 } 7499 7500 static void igb_flush_mac_table(struct igb_adapter *adapter) 7501 { 7502 struct e1000_hw *hw = &adapter->hw; 7503 int i; 7504 7505 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7506 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7507 eth_zero_addr(adapter->mac_table[i].addr); 7508 adapter->mac_table[i].queue = 0; 7509 igb_rar_set_index(adapter, i); 7510 } 7511 } 7512 7513 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7514 { 7515 struct e1000_hw *hw = &adapter->hw; 7516 /* do not count rar entries reserved for VFs MAC addresses */ 7517 int rar_entries = hw->mac.rar_entry_count - 7518 adapter->vfs_allocated_count; 7519 int i, count = 0; 7520 7521 for (i = 0; i < rar_entries; i++) { 7522 /* do not count default entries */ 7523 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7524 continue; 7525 7526 /* do not count "in use" entries for different queues */ 7527 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7528 (adapter->mac_table[i].queue != queue)) 7529 continue; 7530 7531 count++; 7532 } 7533 7534 return count; 7535 } 7536 7537 /* Set default MAC address for the PF in the first RAR entry */ 7538 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7539 { 7540 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7541 7542 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7543 mac_table->queue = adapter->vfs_allocated_count; 7544 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7545 7546 igb_rar_set_index(adapter, 0); 7547 } 7548 7549 /* If the filter to be added and an already existing filter express 7550 * the same address and address type, it should be possible to only 7551 * override the other configurations, for example the queue to steer 7552 * traffic. 7553 */ 7554 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7555 const u8 *addr, const u8 flags) 7556 { 7557 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7558 return true; 7559 7560 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7561 (flags & IGB_MAC_STATE_SRC_ADDR)) 7562 return false; 7563 7564 if (!ether_addr_equal(addr, entry->addr)) 7565 return false; 7566 7567 return true; 7568 } 7569 7570 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7571 * 'flags' is used to indicate what kind of match is made, match is by 7572 * default for the destination address, if matching by source address 7573 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7574 */ 7575 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7576 const u8 *addr, const u8 queue, 7577 const u8 flags) 7578 { 7579 struct e1000_hw *hw = &adapter->hw; 7580 int rar_entries = hw->mac.rar_entry_count - 7581 adapter->vfs_allocated_count; 7582 int i; 7583 7584 if (is_zero_ether_addr(addr)) 7585 return -EINVAL; 7586 7587 /* Search for the first empty entry in the MAC table. 7588 * Do not touch entries at the end of the table reserved for the VF MAC 7589 * addresses. 7590 */ 7591 for (i = 0; i < rar_entries; i++) { 7592 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7593 addr, flags)) 7594 continue; 7595 7596 ether_addr_copy(adapter->mac_table[i].addr, addr); 7597 adapter->mac_table[i].queue = queue; 7598 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7599 7600 igb_rar_set_index(adapter, i); 7601 return i; 7602 } 7603 7604 return -ENOSPC; 7605 } 7606 7607 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7608 const u8 queue) 7609 { 7610 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7611 } 7612 7613 /* Remove a MAC filter for 'addr' directing matching traffic to 7614 * 'queue', 'flags' is used to indicate what kind of match need to be 7615 * removed, match is by default for the destination address, if 7616 * matching by source address is to be removed the flag 7617 * IGB_MAC_STATE_SRC_ADDR can be used. 7618 */ 7619 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7620 const u8 *addr, const u8 queue, 7621 const u8 flags) 7622 { 7623 struct e1000_hw *hw = &adapter->hw; 7624 int rar_entries = hw->mac.rar_entry_count - 7625 adapter->vfs_allocated_count; 7626 int i; 7627 7628 if (is_zero_ether_addr(addr)) 7629 return -EINVAL; 7630 7631 /* Search for matching entry in the MAC table based on given address 7632 * and queue. Do not touch entries at the end of the table reserved 7633 * for the VF MAC addresses. 7634 */ 7635 for (i = 0; i < rar_entries; i++) { 7636 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7637 continue; 7638 if ((adapter->mac_table[i].state & flags) != flags) 7639 continue; 7640 if (adapter->mac_table[i].queue != queue) 7641 continue; 7642 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7643 continue; 7644 7645 /* When a filter for the default address is "deleted", 7646 * we return it to its initial configuration 7647 */ 7648 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7649 adapter->mac_table[i].state = 7650 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7651 adapter->mac_table[i].queue = 7652 adapter->vfs_allocated_count; 7653 } else { 7654 adapter->mac_table[i].state = 0; 7655 adapter->mac_table[i].queue = 0; 7656 eth_zero_addr(adapter->mac_table[i].addr); 7657 } 7658 7659 igb_rar_set_index(adapter, i); 7660 return 0; 7661 } 7662 7663 return -ENOENT; 7664 } 7665 7666 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7667 const u8 queue) 7668 { 7669 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7670 } 7671 7672 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7673 const u8 *addr, u8 queue, u8 flags) 7674 { 7675 struct e1000_hw *hw = &adapter->hw; 7676 7677 /* In theory, this should be supported on 82575 as well, but 7678 * that part wasn't easily accessible during development. 7679 */ 7680 if (hw->mac.type != e1000_i210) 7681 return -EOPNOTSUPP; 7682 7683 return igb_add_mac_filter_flags(adapter, addr, queue, 7684 IGB_MAC_STATE_QUEUE_STEERING | flags); 7685 } 7686 7687 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7688 const u8 *addr, u8 queue, u8 flags) 7689 { 7690 return igb_del_mac_filter_flags(adapter, addr, queue, 7691 IGB_MAC_STATE_QUEUE_STEERING | flags); 7692 } 7693 7694 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7695 { 7696 struct igb_adapter *adapter = netdev_priv(netdev); 7697 int ret; 7698 7699 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7700 7701 return min_t(int, ret, 0); 7702 } 7703 7704 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7705 { 7706 struct igb_adapter *adapter = netdev_priv(netdev); 7707 7708 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7709 7710 return 0; 7711 } 7712 7713 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7714 const u32 info, const u8 *addr) 7715 { 7716 struct pci_dev *pdev = adapter->pdev; 7717 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7718 struct list_head *pos; 7719 struct vf_mac_filter *entry = NULL; 7720 int ret = 0; 7721 7722 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7723 !vf_data->trusted) { 7724 dev_warn(&pdev->dev, 7725 "VF %d requested MAC filter but is administratively denied\n", 7726 vf); 7727 return -EINVAL; 7728 } 7729 if (!is_valid_ether_addr(addr)) { 7730 dev_warn(&pdev->dev, 7731 "VF %d attempted to set invalid MAC filter\n", 7732 vf); 7733 return -EINVAL; 7734 } 7735 7736 switch (info) { 7737 case E1000_VF_MAC_FILTER_CLR: 7738 /* remove all unicast MAC filters related to the current VF */ 7739 list_for_each(pos, &adapter->vf_macs.l) { 7740 entry = list_entry(pos, struct vf_mac_filter, l); 7741 if (entry->vf == vf) { 7742 entry->vf = -1; 7743 entry->free = true; 7744 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7745 } 7746 } 7747 break; 7748 case E1000_VF_MAC_FILTER_ADD: 7749 /* try to find empty slot in the list */ 7750 list_for_each(pos, &adapter->vf_macs.l) { 7751 entry = list_entry(pos, struct vf_mac_filter, l); 7752 if (entry->free) 7753 break; 7754 } 7755 7756 if (entry && entry->free) { 7757 entry->free = false; 7758 entry->vf = vf; 7759 ether_addr_copy(entry->vf_mac, addr); 7760 7761 ret = igb_add_mac_filter(adapter, addr, vf); 7762 ret = min_t(int, ret, 0); 7763 } else { 7764 ret = -ENOSPC; 7765 } 7766 7767 if (ret == -ENOSPC) 7768 dev_warn(&pdev->dev, 7769 "VF %d has requested MAC filter but there is no space for it\n", 7770 vf); 7771 break; 7772 default: 7773 ret = -EINVAL; 7774 break; 7775 } 7776 7777 return ret; 7778 } 7779 7780 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7781 { 7782 struct pci_dev *pdev = adapter->pdev; 7783 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7784 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7785 7786 /* The VF MAC Address is stored in a packed array of bytes 7787 * starting at the second 32 bit word of the msg array 7788 */ 7789 unsigned char *addr = (unsigned char *)&msg[1]; 7790 int ret = 0; 7791 7792 if (!info) { 7793 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7794 !vf_data->trusted) { 7795 dev_warn(&pdev->dev, 7796 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7797 vf); 7798 return -EINVAL; 7799 } 7800 7801 if (!is_valid_ether_addr(addr)) { 7802 dev_warn(&pdev->dev, 7803 "VF %d attempted to set invalid MAC\n", 7804 vf); 7805 return -EINVAL; 7806 } 7807 7808 ret = igb_set_vf_mac(adapter, vf, addr); 7809 } else { 7810 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7811 } 7812 7813 return ret; 7814 } 7815 7816 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7817 { 7818 struct e1000_hw *hw = &adapter->hw; 7819 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7820 u32 msg = E1000_VT_MSGTYPE_NACK; 7821 7822 /* if device isn't clear to send it shouldn't be reading either */ 7823 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7824 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7825 igb_write_mbx(hw, &msg, 1, vf); 7826 vf_data->last_nack = jiffies; 7827 } 7828 } 7829 7830 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7831 { 7832 struct pci_dev *pdev = adapter->pdev; 7833 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7834 struct e1000_hw *hw = &adapter->hw; 7835 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7836 s32 retval; 7837 7838 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7839 7840 if (retval) { 7841 /* if receive failed revoke VF CTS stats and restart init */ 7842 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7843 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7844 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7845 goto unlock; 7846 goto out; 7847 } 7848 7849 /* this is a message we already processed, do nothing */ 7850 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7851 goto unlock; 7852 7853 /* until the vf completes a reset it should not be 7854 * allowed to start any configuration. 7855 */ 7856 if (msgbuf[0] == E1000_VF_RESET) { 7857 /* unlocks mailbox */ 7858 igb_vf_reset_msg(adapter, vf); 7859 return; 7860 } 7861 7862 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7863 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7864 goto unlock; 7865 retval = -1; 7866 goto out; 7867 } 7868 7869 switch ((msgbuf[0] & 0xFFFF)) { 7870 case E1000_VF_SET_MAC_ADDR: 7871 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7872 break; 7873 case E1000_VF_SET_PROMISC: 7874 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7875 break; 7876 case E1000_VF_SET_MULTICAST: 7877 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7878 break; 7879 case E1000_VF_SET_LPE: 7880 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7881 break; 7882 case E1000_VF_SET_VLAN: 7883 retval = -1; 7884 if (vf_data->pf_vlan) 7885 dev_warn(&pdev->dev, 7886 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7887 vf); 7888 else 7889 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7890 break; 7891 default: 7892 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7893 retval = -1; 7894 break; 7895 } 7896 7897 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7898 out: 7899 /* notify the VF of the results of what it sent us */ 7900 if (retval) 7901 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7902 else 7903 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7904 7905 /* unlocks mailbox */ 7906 igb_write_mbx(hw, msgbuf, 1, vf); 7907 return; 7908 7909 unlock: 7910 igb_unlock_mbx(hw, vf); 7911 } 7912 7913 static void igb_msg_task(struct igb_adapter *adapter) 7914 { 7915 struct e1000_hw *hw = &adapter->hw; 7916 u32 vf; 7917 7918 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7919 /* process any reset requests */ 7920 if (!igb_check_for_rst(hw, vf)) 7921 igb_vf_reset_event(adapter, vf); 7922 7923 /* process any messages pending */ 7924 if (!igb_check_for_msg(hw, vf)) 7925 igb_rcv_msg_from_vf(adapter, vf); 7926 7927 /* process any acks */ 7928 if (!igb_check_for_ack(hw, vf)) 7929 igb_rcv_ack_from_vf(adapter, vf); 7930 } 7931 } 7932 7933 /** 7934 * igb_set_uta - Set unicast filter table address 7935 * @adapter: board private structure 7936 * @set: boolean indicating if we are setting or clearing bits 7937 * 7938 * The unicast table address is a register array of 32-bit registers. 7939 * The table is meant to be used in a way similar to how the MTA is used 7940 * however due to certain limitations in the hardware it is necessary to 7941 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7942 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7943 **/ 7944 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7945 { 7946 struct e1000_hw *hw = &adapter->hw; 7947 u32 uta = set ? ~0 : 0; 7948 int i; 7949 7950 /* we only need to do this if VMDq is enabled */ 7951 if (!adapter->vfs_allocated_count) 7952 return; 7953 7954 for (i = hw->mac.uta_reg_count; i--;) 7955 array_wr32(E1000_UTA, i, uta); 7956 } 7957 7958 /** 7959 * igb_intr_msi - Interrupt Handler 7960 * @irq: interrupt number 7961 * @data: pointer to a network interface device structure 7962 **/ 7963 static irqreturn_t igb_intr_msi(int irq, void *data) 7964 { 7965 struct igb_adapter *adapter = data; 7966 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7967 struct e1000_hw *hw = &adapter->hw; 7968 /* read ICR disables interrupts using IAM */ 7969 u32 icr = rd32(E1000_ICR); 7970 7971 igb_write_itr(q_vector); 7972 7973 if (icr & E1000_ICR_DRSTA) 7974 schedule_work(&adapter->reset_task); 7975 7976 if (icr & E1000_ICR_DOUTSYNC) { 7977 /* HW is reporting DMA is out of sync */ 7978 adapter->stats.doosync++; 7979 } 7980 7981 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7982 hw->mac.get_link_status = 1; 7983 if (!test_bit(__IGB_DOWN, &adapter->state)) 7984 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7985 } 7986 7987 if (icr & E1000_ICR_TS) 7988 igb_tsync_interrupt(adapter); 7989 7990 napi_schedule(&q_vector->napi); 7991 7992 return IRQ_HANDLED; 7993 } 7994 7995 /** 7996 * igb_intr - Legacy Interrupt Handler 7997 * @irq: interrupt number 7998 * @data: pointer to a network interface device structure 7999 **/ 8000 static irqreturn_t igb_intr(int irq, void *data) 8001 { 8002 struct igb_adapter *adapter = data; 8003 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8004 struct e1000_hw *hw = &adapter->hw; 8005 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8006 * need for the IMC write 8007 */ 8008 u32 icr = rd32(E1000_ICR); 8009 8010 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8011 * not set, then the adapter didn't send an interrupt 8012 */ 8013 if (!(icr & E1000_ICR_INT_ASSERTED)) 8014 return IRQ_NONE; 8015 8016 igb_write_itr(q_vector); 8017 8018 if (icr & E1000_ICR_DRSTA) 8019 schedule_work(&adapter->reset_task); 8020 8021 if (icr & E1000_ICR_DOUTSYNC) { 8022 /* HW is reporting DMA is out of sync */ 8023 adapter->stats.doosync++; 8024 } 8025 8026 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8027 hw->mac.get_link_status = 1; 8028 /* guard against interrupt when we're going down */ 8029 if (!test_bit(__IGB_DOWN, &adapter->state)) 8030 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8031 } 8032 8033 if (icr & E1000_ICR_TS) 8034 igb_tsync_interrupt(adapter); 8035 8036 napi_schedule(&q_vector->napi); 8037 8038 return IRQ_HANDLED; 8039 } 8040 8041 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8042 { 8043 struct igb_adapter *adapter = q_vector->adapter; 8044 struct e1000_hw *hw = &adapter->hw; 8045 8046 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8047 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8048 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8049 igb_set_itr(q_vector); 8050 else 8051 igb_update_ring_itr(q_vector); 8052 } 8053 8054 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8055 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8056 wr32(E1000_EIMS, q_vector->eims_value); 8057 else 8058 igb_irq_enable(adapter); 8059 } 8060 } 8061 8062 /** 8063 * igb_poll - NAPI Rx polling callback 8064 * @napi: napi polling structure 8065 * @budget: count of how many packets we should handle 8066 **/ 8067 static int igb_poll(struct napi_struct *napi, int budget) 8068 { 8069 struct igb_q_vector *q_vector = container_of(napi, 8070 struct igb_q_vector, 8071 napi); 8072 bool clean_complete = true; 8073 int work_done = 0; 8074 8075 #ifdef CONFIG_IGB_DCA 8076 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8077 igb_update_dca(q_vector); 8078 #endif 8079 if (q_vector->tx.ring) 8080 clean_complete = igb_clean_tx_irq(q_vector, budget); 8081 8082 if (q_vector->rx.ring) { 8083 int cleaned = igb_clean_rx_irq(q_vector, budget); 8084 8085 work_done += cleaned; 8086 if (cleaned >= budget) 8087 clean_complete = false; 8088 } 8089 8090 /* If all work not completed, return budget and keep polling */ 8091 if (!clean_complete) 8092 return budget; 8093 8094 /* Exit the polling mode, but don't re-enable interrupts if stack might 8095 * poll us due to busy-polling 8096 */ 8097 if (likely(napi_complete_done(napi, work_done))) 8098 igb_ring_irq_enable(q_vector); 8099 8100 return work_done; 8101 } 8102 8103 /** 8104 * igb_clean_tx_irq - Reclaim resources after transmit completes 8105 * @q_vector: pointer to q_vector containing needed info 8106 * @napi_budget: Used to determine if we are in netpoll 8107 * 8108 * returns true if ring is completely cleaned 8109 **/ 8110 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8111 { 8112 struct igb_adapter *adapter = q_vector->adapter; 8113 struct igb_ring *tx_ring = q_vector->tx.ring; 8114 struct igb_tx_buffer *tx_buffer; 8115 union e1000_adv_tx_desc *tx_desc; 8116 unsigned int total_bytes = 0, total_packets = 0; 8117 unsigned int budget = q_vector->tx.work_limit; 8118 unsigned int i = tx_ring->next_to_clean; 8119 8120 if (test_bit(__IGB_DOWN, &adapter->state)) 8121 return true; 8122 8123 tx_buffer = &tx_ring->tx_buffer_info[i]; 8124 tx_desc = IGB_TX_DESC(tx_ring, i); 8125 i -= tx_ring->count; 8126 8127 do { 8128 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8129 8130 /* if next_to_watch is not set then there is no work pending */ 8131 if (!eop_desc) 8132 break; 8133 8134 /* prevent any other reads prior to eop_desc */ 8135 smp_rmb(); 8136 8137 /* if DD is not set pending work has not been completed */ 8138 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8139 break; 8140 8141 /* clear next_to_watch to prevent false hangs */ 8142 tx_buffer->next_to_watch = NULL; 8143 8144 /* update the statistics for this packet */ 8145 total_bytes += tx_buffer->bytecount; 8146 total_packets += tx_buffer->gso_segs; 8147 8148 /* free the skb */ 8149 if (tx_buffer->type == IGB_TYPE_SKB) 8150 napi_consume_skb(tx_buffer->skb, napi_budget); 8151 else 8152 xdp_return_frame(tx_buffer->xdpf); 8153 8154 /* unmap skb header data */ 8155 dma_unmap_single(tx_ring->dev, 8156 dma_unmap_addr(tx_buffer, dma), 8157 dma_unmap_len(tx_buffer, len), 8158 DMA_TO_DEVICE); 8159 8160 /* clear tx_buffer data */ 8161 dma_unmap_len_set(tx_buffer, len, 0); 8162 8163 /* clear last DMA location and unmap remaining buffers */ 8164 while (tx_desc != eop_desc) { 8165 tx_buffer++; 8166 tx_desc++; 8167 i++; 8168 if (unlikely(!i)) { 8169 i -= tx_ring->count; 8170 tx_buffer = tx_ring->tx_buffer_info; 8171 tx_desc = IGB_TX_DESC(tx_ring, 0); 8172 } 8173 8174 /* unmap any remaining paged data */ 8175 if (dma_unmap_len(tx_buffer, len)) { 8176 dma_unmap_page(tx_ring->dev, 8177 dma_unmap_addr(tx_buffer, dma), 8178 dma_unmap_len(tx_buffer, len), 8179 DMA_TO_DEVICE); 8180 dma_unmap_len_set(tx_buffer, len, 0); 8181 } 8182 } 8183 8184 /* move us one more past the eop_desc for start of next pkt */ 8185 tx_buffer++; 8186 tx_desc++; 8187 i++; 8188 if (unlikely(!i)) { 8189 i -= tx_ring->count; 8190 tx_buffer = tx_ring->tx_buffer_info; 8191 tx_desc = IGB_TX_DESC(tx_ring, 0); 8192 } 8193 8194 /* issue prefetch for next Tx descriptor */ 8195 prefetch(tx_desc); 8196 8197 /* update budget accounting */ 8198 budget--; 8199 } while (likely(budget)); 8200 8201 netdev_tx_completed_queue(txring_txq(tx_ring), 8202 total_packets, total_bytes); 8203 i += tx_ring->count; 8204 tx_ring->next_to_clean = i; 8205 u64_stats_update_begin(&tx_ring->tx_syncp); 8206 tx_ring->tx_stats.bytes += total_bytes; 8207 tx_ring->tx_stats.packets += total_packets; 8208 u64_stats_update_end(&tx_ring->tx_syncp); 8209 q_vector->tx.total_bytes += total_bytes; 8210 q_vector->tx.total_packets += total_packets; 8211 8212 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8213 struct e1000_hw *hw = &adapter->hw; 8214 8215 /* Detect a transmit hang in hardware, this serializes the 8216 * check with the clearing of time_stamp and movement of i 8217 */ 8218 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8219 if (tx_buffer->next_to_watch && 8220 time_after(jiffies, tx_buffer->time_stamp + 8221 (adapter->tx_timeout_factor * HZ)) && 8222 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8223 8224 /* detected Tx unit hang */ 8225 dev_err(tx_ring->dev, 8226 "Detected Tx Unit Hang\n" 8227 " Tx Queue <%d>\n" 8228 " TDH <%x>\n" 8229 " TDT <%x>\n" 8230 " next_to_use <%x>\n" 8231 " next_to_clean <%x>\n" 8232 "buffer_info[next_to_clean]\n" 8233 " time_stamp <%lx>\n" 8234 " next_to_watch <%p>\n" 8235 " jiffies <%lx>\n" 8236 " desc.status <%x>\n", 8237 tx_ring->queue_index, 8238 rd32(E1000_TDH(tx_ring->reg_idx)), 8239 readl(tx_ring->tail), 8240 tx_ring->next_to_use, 8241 tx_ring->next_to_clean, 8242 tx_buffer->time_stamp, 8243 tx_buffer->next_to_watch, 8244 jiffies, 8245 tx_buffer->next_to_watch->wb.status); 8246 netif_stop_subqueue(tx_ring->netdev, 8247 tx_ring->queue_index); 8248 8249 /* we are about to reset, no point in enabling stuff */ 8250 return true; 8251 } 8252 } 8253 8254 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8255 if (unlikely(total_packets && 8256 netif_carrier_ok(tx_ring->netdev) && 8257 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8258 /* Make sure that anybody stopping the queue after this 8259 * sees the new next_to_clean. 8260 */ 8261 smp_mb(); 8262 if (__netif_subqueue_stopped(tx_ring->netdev, 8263 tx_ring->queue_index) && 8264 !(test_bit(__IGB_DOWN, &adapter->state))) { 8265 netif_wake_subqueue(tx_ring->netdev, 8266 tx_ring->queue_index); 8267 8268 u64_stats_update_begin(&tx_ring->tx_syncp); 8269 tx_ring->tx_stats.restart_queue++; 8270 u64_stats_update_end(&tx_ring->tx_syncp); 8271 } 8272 } 8273 8274 return !!budget; 8275 } 8276 8277 /** 8278 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8279 * @rx_ring: rx descriptor ring to store buffers on 8280 * @old_buff: donor buffer to have page reused 8281 * 8282 * Synchronizes page for reuse by the adapter 8283 **/ 8284 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8285 struct igb_rx_buffer *old_buff) 8286 { 8287 struct igb_rx_buffer *new_buff; 8288 u16 nta = rx_ring->next_to_alloc; 8289 8290 new_buff = &rx_ring->rx_buffer_info[nta]; 8291 8292 /* update, and store next to alloc */ 8293 nta++; 8294 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8295 8296 /* Transfer page from old buffer to new buffer. 8297 * Move each member individually to avoid possible store 8298 * forwarding stalls. 8299 */ 8300 new_buff->dma = old_buff->dma; 8301 new_buff->page = old_buff->page; 8302 new_buff->page_offset = old_buff->page_offset; 8303 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8304 } 8305 8306 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8307 int rx_buf_pgcnt) 8308 { 8309 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8310 struct page *page = rx_buffer->page; 8311 8312 /* avoid re-using remote and pfmemalloc pages */ 8313 if (!dev_page_is_reusable(page)) 8314 return false; 8315 8316 #if (PAGE_SIZE < 8192) 8317 /* if we are only owner of page we can reuse it */ 8318 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8319 return false; 8320 #else 8321 #define IGB_LAST_OFFSET \ 8322 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8323 8324 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8325 return false; 8326 #endif 8327 8328 /* If we have drained the page fragment pool we need to update 8329 * the pagecnt_bias and page count so that we fully restock the 8330 * number of references the driver holds. 8331 */ 8332 if (unlikely(pagecnt_bias == 1)) { 8333 page_ref_add(page, USHRT_MAX - 1); 8334 rx_buffer->pagecnt_bias = USHRT_MAX; 8335 } 8336 8337 return true; 8338 } 8339 8340 /** 8341 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8342 * @rx_ring: rx descriptor ring to transact packets on 8343 * @rx_buffer: buffer containing page to add 8344 * @skb: sk_buff to place the data into 8345 * @size: size of buffer to be added 8346 * 8347 * This function will add the data contained in rx_buffer->page to the skb. 8348 **/ 8349 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8350 struct igb_rx_buffer *rx_buffer, 8351 struct sk_buff *skb, 8352 unsigned int size) 8353 { 8354 #if (PAGE_SIZE < 8192) 8355 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8356 #else 8357 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8358 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8359 SKB_DATA_ALIGN(size); 8360 #endif 8361 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8362 rx_buffer->page_offset, size, truesize); 8363 #if (PAGE_SIZE < 8192) 8364 rx_buffer->page_offset ^= truesize; 8365 #else 8366 rx_buffer->page_offset += truesize; 8367 #endif 8368 } 8369 8370 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8371 struct igb_rx_buffer *rx_buffer, 8372 struct xdp_buff *xdp, 8373 ktime_t timestamp) 8374 { 8375 #if (PAGE_SIZE < 8192) 8376 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8377 #else 8378 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8379 xdp->data_hard_start); 8380 #endif 8381 unsigned int size = xdp->data_end - xdp->data; 8382 unsigned int headlen; 8383 struct sk_buff *skb; 8384 8385 /* prefetch first cache line of first page */ 8386 net_prefetch(xdp->data); 8387 8388 /* allocate a skb to store the frags */ 8389 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8390 if (unlikely(!skb)) 8391 return NULL; 8392 8393 if (timestamp) 8394 skb_hwtstamps(skb)->hwtstamp = timestamp; 8395 8396 /* Determine available headroom for copy */ 8397 headlen = size; 8398 if (headlen > IGB_RX_HDR_LEN) 8399 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8400 8401 /* align pull length to size of long to optimize memcpy performance */ 8402 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8403 8404 /* update all of the pointers */ 8405 size -= headlen; 8406 if (size) { 8407 skb_add_rx_frag(skb, 0, rx_buffer->page, 8408 (xdp->data + headlen) - page_address(rx_buffer->page), 8409 size, truesize); 8410 #if (PAGE_SIZE < 8192) 8411 rx_buffer->page_offset ^= truesize; 8412 #else 8413 rx_buffer->page_offset += truesize; 8414 #endif 8415 } else { 8416 rx_buffer->pagecnt_bias++; 8417 } 8418 8419 return skb; 8420 } 8421 8422 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8423 struct igb_rx_buffer *rx_buffer, 8424 struct xdp_buff *xdp, 8425 ktime_t timestamp) 8426 { 8427 #if (PAGE_SIZE < 8192) 8428 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8429 #else 8430 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8431 SKB_DATA_ALIGN(xdp->data_end - 8432 xdp->data_hard_start); 8433 #endif 8434 unsigned int metasize = xdp->data - xdp->data_meta; 8435 struct sk_buff *skb; 8436 8437 /* prefetch first cache line of first page */ 8438 net_prefetch(xdp->data_meta); 8439 8440 /* build an skb around the page buffer */ 8441 skb = napi_build_skb(xdp->data_hard_start, truesize); 8442 if (unlikely(!skb)) 8443 return NULL; 8444 8445 /* update pointers within the skb to store the data */ 8446 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8447 __skb_put(skb, xdp->data_end - xdp->data); 8448 8449 if (metasize) 8450 skb_metadata_set(skb, metasize); 8451 8452 if (timestamp) 8453 skb_hwtstamps(skb)->hwtstamp = timestamp; 8454 8455 /* update buffer offset */ 8456 #if (PAGE_SIZE < 8192) 8457 rx_buffer->page_offset ^= truesize; 8458 #else 8459 rx_buffer->page_offset += truesize; 8460 #endif 8461 8462 return skb; 8463 } 8464 8465 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8466 struct igb_ring *rx_ring, 8467 struct xdp_buff *xdp) 8468 { 8469 int err, result = IGB_XDP_PASS; 8470 struct bpf_prog *xdp_prog; 8471 u32 act; 8472 8473 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8474 8475 if (!xdp_prog) 8476 goto xdp_out; 8477 8478 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8479 8480 act = bpf_prog_run_xdp(xdp_prog, xdp); 8481 switch (act) { 8482 case XDP_PASS: 8483 break; 8484 case XDP_TX: 8485 result = igb_xdp_xmit_back(adapter, xdp); 8486 if (result == IGB_XDP_CONSUMED) 8487 goto out_failure; 8488 break; 8489 case XDP_REDIRECT: 8490 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8491 if (err) 8492 goto out_failure; 8493 result = IGB_XDP_REDIR; 8494 break; 8495 default: 8496 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8497 fallthrough; 8498 case XDP_ABORTED: 8499 out_failure: 8500 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8501 fallthrough; 8502 case XDP_DROP: 8503 result = IGB_XDP_CONSUMED; 8504 break; 8505 } 8506 xdp_out: 8507 return ERR_PTR(-result); 8508 } 8509 8510 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8511 unsigned int size) 8512 { 8513 unsigned int truesize; 8514 8515 #if (PAGE_SIZE < 8192) 8516 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8517 #else 8518 truesize = ring_uses_build_skb(rx_ring) ? 8519 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8520 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8521 SKB_DATA_ALIGN(size); 8522 #endif 8523 return truesize; 8524 } 8525 8526 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8527 struct igb_rx_buffer *rx_buffer, 8528 unsigned int size) 8529 { 8530 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8531 #if (PAGE_SIZE < 8192) 8532 rx_buffer->page_offset ^= truesize; 8533 #else 8534 rx_buffer->page_offset += truesize; 8535 #endif 8536 } 8537 8538 static inline void igb_rx_checksum(struct igb_ring *ring, 8539 union e1000_adv_rx_desc *rx_desc, 8540 struct sk_buff *skb) 8541 { 8542 skb_checksum_none_assert(skb); 8543 8544 /* Ignore Checksum bit is set */ 8545 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8546 return; 8547 8548 /* Rx checksum disabled via ethtool */ 8549 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8550 return; 8551 8552 /* TCP/UDP checksum error bit is set */ 8553 if (igb_test_staterr(rx_desc, 8554 E1000_RXDEXT_STATERR_TCPE | 8555 E1000_RXDEXT_STATERR_IPE)) { 8556 /* work around errata with sctp packets where the TCPE aka 8557 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8558 * packets, (aka let the stack check the crc32c) 8559 */ 8560 if (!((skb->len == 60) && 8561 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8562 u64_stats_update_begin(&ring->rx_syncp); 8563 ring->rx_stats.csum_err++; 8564 u64_stats_update_end(&ring->rx_syncp); 8565 } 8566 /* let the stack verify checksum errors */ 8567 return; 8568 } 8569 /* It must be a TCP or UDP packet with a valid checksum */ 8570 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8571 E1000_RXD_STAT_UDPCS)) 8572 skb->ip_summed = CHECKSUM_UNNECESSARY; 8573 8574 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8575 le32_to_cpu(rx_desc->wb.upper.status_error)); 8576 } 8577 8578 static inline void igb_rx_hash(struct igb_ring *ring, 8579 union e1000_adv_rx_desc *rx_desc, 8580 struct sk_buff *skb) 8581 { 8582 if (ring->netdev->features & NETIF_F_RXHASH) 8583 skb_set_hash(skb, 8584 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8585 PKT_HASH_TYPE_L3); 8586 } 8587 8588 /** 8589 * igb_is_non_eop - process handling of non-EOP buffers 8590 * @rx_ring: Rx ring being processed 8591 * @rx_desc: Rx descriptor for current buffer 8592 * 8593 * This function updates next to clean. If the buffer is an EOP buffer 8594 * this function exits returning false, otherwise it will place the 8595 * sk_buff in the next buffer to be chained and return true indicating 8596 * that this is in fact a non-EOP buffer. 8597 **/ 8598 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8599 union e1000_adv_rx_desc *rx_desc) 8600 { 8601 u32 ntc = rx_ring->next_to_clean + 1; 8602 8603 /* fetch, update, and store next to clean */ 8604 ntc = (ntc < rx_ring->count) ? ntc : 0; 8605 rx_ring->next_to_clean = ntc; 8606 8607 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8608 8609 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8610 return false; 8611 8612 return true; 8613 } 8614 8615 /** 8616 * igb_cleanup_headers - Correct corrupted or empty headers 8617 * @rx_ring: rx descriptor ring packet is being transacted on 8618 * @rx_desc: pointer to the EOP Rx descriptor 8619 * @skb: pointer to current skb being fixed 8620 * 8621 * Address the case where we are pulling data in on pages only 8622 * and as such no data is present in the skb header. 8623 * 8624 * In addition if skb is not at least 60 bytes we need to pad it so that 8625 * it is large enough to qualify as a valid Ethernet frame. 8626 * 8627 * Returns true if an error was encountered and skb was freed. 8628 **/ 8629 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8630 union e1000_adv_rx_desc *rx_desc, 8631 struct sk_buff *skb) 8632 { 8633 /* XDP packets use error pointer so abort at this point */ 8634 if (IS_ERR(skb)) 8635 return true; 8636 8637 if (unlikely((igb_test_staterr(rx_desc, 8638 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8639 struct net_device *netdev = rx_ring->netdev; 8640 if (!(netdev->features & NETIF_F_RXALL)) { 8641 dev_kfree_skb_any(skb); 8642 return true; 8643 } 8644 } 8645 8646 /* if eth_skb_pad returns an error the skb was freed */ 8647 if (eth_skb_pad(skb)) 8648 return true; 8649 8650 return false; 8651 } 8652 8653 /** 8654 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8655 * @rx_ring: rx descriptor ring packet is being transacted on 8656 * @rx_desc: pointer to the EOP Rx descriptor 8657 * @skb: pointer to current skb being populated 8658 * 8659 * This function checks the ring, descriptor, and packet information in 8660 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8661 * other fields within the skb. 8662 **/ 8663 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8664 union e1000_adv_rx_desc *rx_desc, 8665 struct sk_buff *skb) 8666 { 8667 struct net_device *dev = rx_ring->netdev; 8668 8669 igb_rx_hash(rx_ring, rx_desc, skb); 8670 8671 igb_rx_checksum(rx_ring, rx_desc, skb); 8672 8673 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8674 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8675 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8676 8677 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8678 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8679 u16 vid; 8680 8681 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8682 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8683 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8684 else 8685 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8686 8687 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8688 } 8689 8690 skb_record_rx_queue(skb, rx_ring->queue_index); 8691 8692 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8693 } 8694 8695 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8696 { 8697 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8698 } 8699 8700 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8701 const unsigned int size, int *rx_buf_pgcnt) 8702 { 8703 struct igb_rx_buffer *rx_buffer; 8704 8705 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8706 *rx_buf_pgcnt = 8707 #if (PAGE_SIZE < 8192) 8708 page_count(rx_buffer->page); 8709 #else 8710 0; 8711 #endif 8712 prefetchw(rx_buffer->page); 8713 8714 /* we are reusing so sync this buffer for CPU use */ 8715 dma_sync_single_range_for_cpu(rx_ring->dev, 8716 rx_buffer->dma, 8717 rx_buffer->page_offset, 8718 size, 8719 DMA_FROM_DEVICE); 8720 8721 rx_buffer->pagecnt_bias--; 8722 8723 return rx_buffer; 8724 } 8725 8726 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8727 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8728 { 8729 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8730 /* hand second half of page back to the ring */ 8731 igb_reuse_rx_page(rx_ring, rx_buffer); 8732 } else { 8733 /* We are not reusing the buffer so unmap it and free 8734 * any references we are holding to it 8735 */ 8736 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8737 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8738 IGB_RX_DMA_ATTR); 8739 __page_frag_cache_drain(rx_buffer->page, 8740 rx_buffer->pagecnt_bias); 8741 } 8742 8743 /* clear contents of rx_buffer */ 8744 rx_buffer->page = NULL; 8745 } 8746 8747 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8748 { 8749 struct igb_adapter *adapter = q_vector->adapter; 8750 struct igb_ring *rx_ring = q_vector->rx.ring; 8751 struct sk_buff *skb = rx_ring->skb; 8752 unsigned int total_bytes = 0, total_packets = 0; 8753 u16 cleaned_count = igb_desc_unused(rx_ring); 8754 unsigned int xdp_xmit = 0; 8755 struct xdp_buff xdp; 8756 u32 frame_sz = 0; 8757 int rx_buf_pgcnt; 8758 8759 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8760 #if (PAGE_SIZE < 8192) 8761 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8762 #endif 8763 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8764 8765 while (likely(total_packets < budget)) { 8766 union e1000_adv_rx_desc *rx_desc; 8767 struct igb_rx_buffer *rx_buffer; 8768 ktime_t timestamp = 0; 8769 int pkt_offset = 0; 8770 unsigned int size; 8771 void *pktbuf; 8772 8773 /* return some buffers to hardware, one at a time is too slow */ 8774 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8775 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8776 cleaned_count = 0; 8777 } 8778 8779 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8780 size = le16_to_cpu(rx_desc->wb.upper.length); 8781 if (!size) 8782 break; 8783 8784 /* This memory barrier is needed to keep us from reading 8785 * any other fields out of the rx_desc until we know the 8786 * descriptor has been written back 8787 */ 8788 dma_rmb(); 8789 8790 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8791 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8792 8793 /* pull rx packet timestamp if available and valid */ 8794 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8795 int ts_hdr_len; 8796 8797 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8798 pktbuf, ×tamp); 8799 8800 pkt_offset += ts_hdr_len; 8801 size -= ts_hdr_len; 8802 } 8803 8804 /* retrieve a buffer from the ring */ 8805 if (!skb) { 8806 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8807 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8808 8809 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8810 #if (PAGE_SIZE > 4096) 8811 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8812 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8813 #endif 8814 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8815 } 8816 8817 if (IS_ERR(skb)) { 8818 unsigned int xdp_res = -PTR_ERR(skb); 8819 8820 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8821 xdp_xmit |= xdp_res; 8822 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8823 } else { 8824 rx_buffer->pagecnt_bias++; 8825 } 8826 total_packets++; 8827 total_bytes += size; 8828 } else if (skb) 8829 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8830 else if (ring_uses_build_skb(rx_ring)) 8831 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8832 timestamp); 8833 else 8834 skb = igb_construct_skb(rx_ring, rx_buffer, 8835 &xdp, timestamp); 8836 8837 /* exit if we failed to retrieve a buffer */ 8838 if (!skb) { 8839 rx_ring->rx_stats.alloc_failed++; 8840 rx_buffer->pagecnt_bias++; 8841 break; 8842 } 8843 8844 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8845 cleaned_count++; 8846 8847 /* fetch next buffer in frame if non-eop */ 8848 if (igb_is_non_eop(rx_ring, rx_desc)) 8849 continue; 8850 8851 /* verify the packet layout is correct */ 8852 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8853 skb = NULL; 8854 continue; 8855 } 8856 8857 /* probably a little skewed due to removing CRC */ 8858 total_bytes += skb->len; 8859 8860 /* populate checksum, timestamp, VLAN, and protocol */ 8861 igb_process_skb_fields(rx_ring, rx_desc, skb); 8862 8863 napi_gro_receive(&q_vector->napi, skb); 8864 8865 /* reset skb pointer */ 8866 skb = NULL; 8867 8868 /* update budget accounting */ 8869 total_packets++; 8870 } 8871 8872 /* place incomplete frames back on ring for completion */ 8873 rx_ring->skb = skb; 8874 8875 if (xdp_xmit & IGB_XDP_REDIR) 8876 xdp_do_flush(); 8877 8878 if (xdp_xmit & IGB_XDP_TX) { 8879 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8880 8881 igb_xdp_ring_update_tail(tx_ring); 8882 } 8883 8884 u64_stats_update_begin(&rx_ring->rx_syncp); 8885 rx_ring->rx_stats.packets += total_packets; 8886 rx_ring->rx_stats.bytes += total_bytes; 8887 u64_stats_update_end(&rx_ring->rx_syncp); 8888 q_vector->rx.total_packets += total_packets; 8889 q_vector->rx.total_bytes += total_bytes; 8890 8891 if (cleaned_count) 8892 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8893 8894 return total_packets; 8895 } 8896 8897 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8898 struct igb_rx_buffer *bi) 8899 { 8900 struct page *page = bi->page; 8901 dma_addr_t dma; 8902 8903 /* since we are recycling buffers we should seldom need to alloc */ 8904 if (likely(page)) 8905 return true; 8906 8907 /* alloc new page for storage */ 8908 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8909 if (unlikely(!page)) { 8910 rx_ring->rx_stats.alloc_failed++; 8911 return false; 8912 } 8913 8914 /* map page for use */ 8915 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8916 igb_rx_pg_size(rx_ring), 8917 DMA_FROM_DEVICE, 8918 IGB_RX_DMA_ATTR); 8919 8920 /* if mapping failed free memory back to system since 8921 * there isn't much point in holding memory we can't use 8922 */ 8923 if (dma_mapping_error(rx_ring->dev, dma)) { 8924 __free_pages(page, igb_rx_pg_order(rx_ring)); 8925 8926 rx_ring->rx_stats.alloc_failed++; 8927 return false; 8928 } 8929 8930 bi->dma = dma; 8931 bi->page = page; 8932 bi->page_offset = igb_rx_offset(rx_ring); 8933 page_ref_add(page, USHRT_MAX - 1); 8934 bi->pagecnt_bias = USHRT_MAX; 8935 8936 return true; 8937 } 8938 8939 /** 8940 * igb_alloc_rx_buffers - Replace used receive buffers 8941 * @rx_ring: rx descriptor ring to allocate new receive buffers 8942 * @cleaned_count: count of buffers to allocate 8943 **/ 8944 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8945 { 8946 union e1000_adv_rx_desc *rx_desc; 8947 struct igb_rx_buffer *bi; 8948 u16 i = rx_ring->next_to_use; 8949 u16 bufsz; 8950 8951 /* nothing to do */ 8952 if (!cleaned_count) 8953 return; 8954 8955 rx_desc = IGB_RX_DESC(rx_ring, i); 8956 bi = &rx_ring->rx_buffer_info[i]; 8957 i -= rx_ring->count; 8958 8959 bufsz = igb_rx_bufsz(rx_ring); 8960 8961 do { 8962 if (!igb_alloc_mapped_page(rx_ring, bi)) 8963 break; 8964 8965 /* sync the buffer for use by the device */ 8966 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8967 bi->page_offset, bufsz, 8968 DMA_FROM_DEVICE); 8969 8970 /* Refresh the desc even if buffer_addrs didn't change 8971 * because each write-back erases this info. 8972 */ 8973 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8974 8975 rx_desc++; 8976 bi++; 8977 i++; 8978 if (unlikely(!i)) { 8979 rx_desc = IGB_RX_DESC(rx_ring, 0); 8980 bi = rx_ring->rx_buffer_info; 8981 i -= rx_ring->count; 8982 } 8983 8984 /* clear the length for the next_to_use descriptor */ 8985 rx_desc->wb.upper.length = 0; 8986 8987 cleaned_count--; 8988 } while (cleaned_count); 8989 8990 i += rx_ring->count; 8991 8992 if (rx_ring->next_to_use != i) { 8993 /* record the next descriptor to use */ 8994 rx_ring->next_to_use = i; 8995 8996 /* update next to alloc since we have filled the ring */ 8997 rx_ring->next_to_alloc = i; 8998 8999 /* Force memory writes to complete before letting h/w 9000 * know there are new descriptors to fetch. (Only 9001 * applicable for weak-ordered memory model archs, 9002 * such as IA-64). 9003 */ 9004 dma_wmb(); 9005 writel(i, rx_ring->tail); 9006 } 9007 } 9008 9009 /** 9010 * igb_mii_ioctl - 9011 * @netdev: pointer to netdev struct 9012 * @ifr: interface structure 9013 * @cmd: ioctl command to execute 9014 **/ 9015 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9016 { 9017 struct igb_adapter *adapter = netdev_priv(netdev); 9018 struct mii_ioctl_data *data = if_mii(ifr); 9019 9020 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9021 return -EOPNOTSUPP; 9022 9023 switch (cmd) { 9024 case SIOCGMIIPHY: 9025 data->phy_id = adapter->hw.phy.addr; 9026 break; 9027 case SIOCGMIIREG: 9028 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9029 &data->val_out)) 9030 return -EIO; 9031 break; 9032 case SIOCSMIIREG: 9033 default: 9034 return -EOPNOTSUPP; 9035 } 9036 return 0; 9037 } 9038 9039 /** 9040 * igb_ioctl - 9041 * @netdev: pointer to netdev struct 9042 * @ifr: interface structure 9043 * @cmd: ioctl command to execute 9044 **/ 9045 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9046 { 9047 switch (cmd) { 9048 case SIOCGMIIPHY: 9049 case SIOCGMIIREG: 9050 case SIOCSMIIREG: 9051 return igb_mii_ioctl(netdev, ifr, cmd); 9052 case SIOCGHWTSTAMP: 9053 return igb_ptp_get_ts_config(netdev, ifr); 9054 case SIOCSHWTSTAMP: 9055 return igb_ptp_set_ts_config(netdev, ifr); 9056 default: 9057 return -EOPNOTSUPP; 9058 } 9059 } 9060 9061 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9062 { 9063 struct igb_adapter *adapter = hw->back; 9064 9065 pci_read_config_word(adapter->pdev, reg, value); 9066 } 9067 9068 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9069 { 9070 struct igb_adapter *adapter = hw->back; 9071 9072 pci_write_config_word(adapter->pdev, reg, *value); 9073 } 9074 9075 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9076 { 9077 struct igb_adapter *adapter = hw->back; 9078 9079 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9080 return -E1000_ERR_CONFIG; 9081 9082 return 0; 9083 } 9084 9085 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9086 { 9087 struct igb_adapter *adapter = hw->back; 9088 9089 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9090 return -E1000_ERR_CONFIG; 9091 9092 return 0; 9093 } 9094 9095 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9096 { 9097 struct igb_adapter *adapter = netdev_priv(netdev); 9098 struct e1000_hw *hw = &adapter->hw; 9099 u32 ctrl, rctl; 9100 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9101 9102 if (enable) { 9103 /* enable VLAN tag insert/strip */ 9104 ctrl = rd32(E1000_CTRL); 9105 ctrl |= E1000_CTRL_VME; 9106 wr32(E1000_CTRL, ctrl); 9107 9108 /* Disable CFI check */ 9109 rctl = rd32(E1000_RCTL); 9110 rctl &= ~E1000_RCTL_CFIEN; 9111 wr32(E1000_RCTL, rctl); 9112 } else { 9113 /* disable VLAN tag insert/strip */ 9114 ctrl = rd32(E1000_CTRL); 9115 ctrl &= ~E1000_CTRL_VME; 9116 wr32(E1000_CTRL, ctrl); 9117 } 9118 9119 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9120 } 9121 9122 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9123 __be16 proto, u16 vid) 9124 { 9125 struct igb_adapter *adapter = netdev_priv(netdev); 9126 struct e1000_hw *hw = &adapter->hw; 9127 int pf_id = adapter->vfs_allocated_count; 9128 9129 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9130 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9131 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9132 9133 set_bit(vid, adapter->active_vlans); 9134 9135 return 0; 9136 } 9137 9138 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9139 __be16 proto, u16 vid) 9140 { 9141 struct igb_adapter *adapter = netdev_priv(netdev); 9142 int pf_id = adapter->vfs_allocated_count; 9143 struct e1000_hw *hw = &adapter->hw; 9144 9145 /* remove VID from filter table */ 9146 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9147 igb_vfta_set(hw, vid, pf_id, false, true); 9148 9149 clear_bit(vid, adapter->active_vlans); 9150 9151 return 0; 9152 } 9153 9154 static void igb_restore_vlan(struct igb_adapter *adapter) 9155 { 9156 u16 vid = 1; 9157 9158 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9159 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9160 9161 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9162 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9163 } 9164 9165 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9166 { 9167 struct pci_dev *pdev = adapter->pdev; 9168 struct e1000_mac_info *mac = &adapter->hw.mac; 9169 9170 mac->autoneg = 0; 9171 9172 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9173 * for the switch() below to work 9174 */ 9175 if ((spd & 1) || (dplx & ~1)) 9176 goto err_inval; 9177 9178 /* Fiber NIC's only allow 1000 gbps Full duplex 9179 * and 100Mbps Full duplex for 100baseFx sfp 9180 */ 9181 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9182 switch (spd + dplx) { 9183 case SPEED_10 + DUPLEX_HALF: 9184 case SPEED_10 + DUPLEX_FULL: 9185 case SPEED_100 + DUPLEX_HALF: 9186 goto err_inval; 9187 default: 9188 break; 9189 } 9190 } 9191 9192 switch (spd + dplx) { 9193 case SPEED_10 + DUPLEX_HALF: 9194 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9195 break; 9196 case SPEED_10 + DUPLEX_FULL: 9197 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9198 break; 9199 case SPEED_100 + DUPLEX_HALF: 9200 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9201 break; 9202 case SPEED_100 + DUPLEX_FULL: 9203 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9204 break; 9205 case SPEED_1000 + DUPLEX_FULL: 9206 mac->autoneg = 1; 9207 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9208 break; 9209 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9210 default: 9211 goto err_inval; 9212 } 9213 9214 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9215 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9216 9217 return 0; 9218 9219 err_inval: 9220 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9221 return -EINVAL; 9222 } 9223 9224 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9225 bool runtime) 9226 { 9227 struct net_device *netdev = pci_get_drvdata(pdev); 9228 struct igb_adapter *adapter = netdev_priv(netdev); 9229 struct e1000_hw *hw = &adapter->hw; 9230 u32 ctrl, rctl, status; 9231 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9232 bool wake; 9233 9234 rtnl_lock(); 9235 netif_device_detach(netdev); 9236 9237 if (netif_running(netdev)) 9238 __igb_close(netdev, true); 9239 9240 igb_ptp_suspend(adapter); 9241 9242 igb_clear_interrupt_scheme(adapter); 9243 rtnl_unlock(); 9244 9245 status = rd32(E1000_STATUS); 9246 if (status & E1000_STATUS_LU) 9247 wufc &= ~E1000_WUFC_LNKC; 9248 9249 if (wufc) { 9250 igb_setup_rctl(adapter); 9251 igb_set_rx_mode(netdev); 9252 9253 /* turn on all-multi mode if wake on multicast is enabled */ 9254 if (wufc & E1000_WUFC_MC) { 9255 rctl = rd32(E1000_RCTL); 9256 rctl |= E1000_RCTL_MPE; 9257 wr32(E1000_RCTL, rctl); 9258 } 9259 9260 ctrl = rd32(E1000_CTRL); 9261 ctrl |= E1000_CTRL_ADVD3WUC; 9262 wr32(E1000_CTRL, ctrl); 9263 9264 /* Allow time for pending master requests to run */ 9265 igb_disable_pcie_master(hw); 9266 9267 wr32(E1000_WUC, E1000_WUC_PME_EN); 9268 wr32(E1000_WUFC, wufc); 9269 } else { 9270 wr32(E1000_WUC, 0); 9271 wr32(E1000_WUFC, 0); 9272 } 9273 9274 wake = wufc || adapter->en_mng_pt; 9275 if (!wake) 9276 igb_power_down_link(adapter); 9277 else 9278 igb_power_up_link(adapter); 9279 9280 if (enable_wake) 9281 *enable_wake = wake; 9282 9283 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9284 * would have already happened in close and is redundant. 9285 */ 9286 igb_release_hw_control(adapter); 9287 9288 pci_disable_device(pdev); 9289 9290 return 0; 9291 } 9292 9293 static void igb_deliver_wake_packet(struct net_device *netdev) 9294 { 9295 struct igb_adapter *adapter = netdev_priv(netdev); 9296 struct e1000_hw *hw = &adapter->hw; 9297 struct sk_buff *skb; 9298 u32 wupl; 9299 9300 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9301 9302 /* WUPM stores only the first 128 bytes of the wake packet. 9303 * Read the packet only if we have the whole thing. 9304 */ 9305 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9306 return; 9307 9308 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9309 if (!skb) 9310 return; 9311 9312 skb_put(skb, wupl); 9313 9314 /* Ensure reads are 32-bit aligned */ 9315 wupl = roundup(wupl, 4); 9316 9317 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9318 9319 skb->protocol = eth_type_trans(skb, netdev); 9320 netif_rx(skb); 9321 } 9322 9323 static int __maybe_unused igb_suspend(struct device *dev) 9324 { 9325 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9326 } 9327 9328 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9329 { 9330 struct pci_dev *pdev = to_pci_dev(dev); 9331 struct net_device *netdev = pci_get_drvdata(pdev); 9332 struct igb_adapter *adapter = netdev_priv(netdev); 9333 struct e1000_hw *hw = &adapter->hw; 9334 u32 err, val; 9335 9336 pci_set_power_state(pdev, PCI_D0); 9337 pci_restore_state(pdev); 9338 pci_save_state(pdev); 9339 9340 if (!pci_device_is_present(pdev)) 9341 return -ENODEV; 9342 err = pci_enable_device_mem(pdev); 9343 if (err) { 9344 dev_err(&pdev->dev, 9345 "igb: Cannot enable PCI device from suspend\n"); 9346 return err; 9347 } 9348 pci_set_master(pdev); 9349 9350 pci_enable_wake(pdev, PCI_D3hot, 0); 9351 pci_enable_wake(pdev, PCI_D3cold, 0); 9352 9353 if (igb_init_interrupt_scheme(adapter, true)) { 9354 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9355 return -ENOMEM; 9356 } 9357 9358 igb_reset(adapter); 9359 9360 /* let the f/w know that the h/w is now under the control of the 9361 * driver. 9362 */ 9363 igb_get_hw_control(adapter); 9364 9365 val = rd32(E1000_WUS); 9366 if (val & WAKE_PKT_WUS) 9367 igb_deliver_wake_packet(netdev); 9368 9369 wr32(E1000_WUS, ~0); 9370 9371 if (!rpm) 9372 rtnl_lock(); 9373 if (!err && netif_running(netdev)) 9374 err = __igb_open(netdev, true); 9375 9376 if (!err) 9377 netif_device_attach(netdev); 9378 if (!rpm) 9379 rtnl_unlock(); 9380 9381 return err; 9382 } 9383 9384 static int __maybe_unused igb_resume(struct device *dev) 9385 { 9386 return __igb_resume(dev, false); 9387 } 9388 9389 static int __maybe_unused igb_runtime_idle(struct device *dev) 9390 { 9391 struct net_device *netdev = dev_get_drvdata(dev); 9392 struct igb_adapter *adapter = netdev_priv(netdev); 9393 9394 if (!igb_has_link(adapter)) 9395 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9396 9397 return -EBUSY; 9398 } 9399 9400 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9401 { 9402 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9403 } 9404 9405 static int __maybe_unused igb_runtime_resume(struct device *dev) 9406 { 9407 return __igb_resume(dev, true); 9408 } 9409 9410 static void igb_shutdown(struct pci_dev *pdev) 9411 { 9412 bool wake; 9413 9414 __igb_shutdown(pdev, &wake, 0); 9415 9416 if (system_state == SYSTEM_POWER_OFF) { 9417 pci_wake_from_d3(pdev, wake); 9418 pci_set_power_state(pdev, PCI_D3hot); 9419 } 9420 } 9421 9422 #ifdef CONFIG_PCI_IOV 9423 static int igb_sriov_reinit(struct pci_dev *dev) 9424 { 9425 struct net_device *netdev = pci_get_drvdata(dev); 9426 struct igb_adapter *adapter = netdev_priv(netdev); 9427 struct pci_dev *pdev = adapter->pdev; 9428 9429 rtnl_lock(); 9430 9431 if (netif_running(netdev)) 9432 igb_close(netdev); 9433 else 9434 igb_reset(adapter); 9435 9436 igb_clear_interrupt_scheme(adapter); 9437 9438 igb_init_queue_configuration(adapter); 9439 9440 if (igb_init_interrupt_scheme(adapter, true)) { 9441 rtnl_unlock(); 9442 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9443 return -ENOMEM; 9444 } 9445 9446 if (netif_running(netdev)) 9447 igb_open(netdev); 9448 9449 rtnl_unlock(); 9450 9451 return 0; 9452 } 9453 9454 static int igb_pci_disable_sriov(struct pci_dev *dev) 9455 { 9456 int err = igb_disable_sriov(dev); 9457 9458 if (!err) 9459 err = igb_sriov_reinit(dev); 9460 9461 return err; 9462 } 9463 9464 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9465 { 9466 int err = igb_enable_sriov(dev, num_vfs); 9467 9468 if (err) 9469 goto out; 9470 9471 err = igb_sriov_reinit(dev); 9472 if (!err) 9473 return num_vfs; 9474 9475 out: 9476 return err; 9477 } 9478 9479 #endif 9480 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9481 { 9482 #ifdef CONFIG_PCI_IOV 9483 if (num_vfs == 0) 9484 return igb_pci_disable_sriov(dev); 9485 else 9486 return igb_pci_enable_sriov(dev, num_vfs); 9487 #endif 9488 return 0; 9489 } 9490 9491 /** 9492 * igb_io_error_detected - called when PCI error is detected 9493 * @pdev: Pointer to PCI device 9494 * @state: The current pci connection state 9495 * 9496 * This function is called after a PCI bus error affecting 9497 * this device has been detected. 9498 **/ 9499 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9500 pci_channel_state_t state) 9501 { 9502 struct net_device *netdev = pci_get_drvdata(pdev); 9503 struct igb_adapter *adapter = netdev_priv(netdev); 9504 9505 netif_device_detach(netdev); 9506 9507 if (state == pci_channel_io_perm_failure) 9508 return PCI_ERS_RESULT_DISCONNECT; 9509 9510 if (netif_running(netdev)) 9511 igb_down(adapter); 9512 pci_disable_device(pdev); 9513 9514 /* Request a slot slot reset. */ 9515 return PCI_ERS_RESULT_NEED_RESET; 9516 } 9517 9518 /** 9519 * igb_io_slot_reset - called after the pci bus has been reset. 9520 * @pdev: Pointer to PCI device 9521 * 9522 * Restart the card from scratch, as if from a cold-boot. Implementation 9523 * resembles the first-half of the __igb_resume routine. 9524 **/ 9525 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9526 { 9527 struct net_device *netdev = pci_get_drvdata(pdev); 9528 struct igb_adapter *adapter = netdev_priv(netdev); 9529 struct e1000_hw *hw = &adapter->hw; 9530 pci_ers_result_t result; 9531 9532 if (pci_enable_device_mem(pdev)) { 9533 dev_err(&pdev->dev, 9534 "Cannot re-enable PCI device after reset.\n"); 9535 result = PCI_ERS_RESULT_DISCONNECT; 9536 } else { 9537 pci_set_master(pdev); 9538 pci_restore_state(pdev); 9539 pci_save_state(pdev); 9540 9541 pci_enable_wake(pdev, PCI_D3hot, 0); 9542 pci_enable_wake(pdev, PCI_D3cold, 0); 9543 9544 /* In case of PCI error, adapter lose its HW address 9545 * so we should re-assign it here. 9546 */ 9547 hw->hw_addr = adapter->io_addr; 9548 9549 igb_reset(adapter); 9550 wr32(E1000_WUS, ~0); 9551 result = PCI_ERS_RESULT_RECOVERED; 9552 } 9553 9554 return result; 9555 } 9556 9557 /** 9558 * igb_io_resume - called when traffic can start flowing again. 9559 * @pdev: Pointer to PCI device 9560 * 9561 * This callback is called when the error recovery driver tells us that 9562 * its OK to resume normal operation. Implementation resembles the 9563 * second-half of the __igb_resume routine. 9564 */ 9565 static void igb_io_resume(struct pci_dev *pdev) 9566 { 9567 struct net_device *netdev = pci_get_drvdata(pdev); 9568 struct igb_adapter *adapter = netdev_priv(netdev); 9569 9570 if (netif_running(netdev)) { 9571 if (igb_up(adapter)) { 9572 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9573 return; 9574 } 9575 } 9576 9577 netif_device_attach(netdev); 9578 9579 /* let the f/w know that the h/w is now under the control of the 9580 * driver. 9581 */ 9582 igb_get_hw_control(adapter); 9583 } 9584 9585 /** 9586 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9587 * @adapter: Pointer to adapter structure 9588 * @index: Index of the RAR entry which need to be synced with MAC table 9589 **/ 9590 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9591 { 9592 struct e1000_hw *hw = &adapter->hw; 9593 u32 rar_low, rar_high; 9594 u8 *addr = adapter->mac_table[index].addr; 9595 9596 /* HW expects these to be in network order when they are plugged 9597 * into the registers which are little endian. In order to guarantee 9598 * that ordering we need to do an leXX_to_cpup here in order to be 9599 * ready for the byteswap that occurs with writel 9600 */ 9601 rar_low = le32_to_cpup((__le32 *)(addr)); 9602 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9603 9604 /* Indicate to hardware the Address is Valid. */ 9605 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9606 if (is_valid_ether_addr(addr)) 9607 rar_high |= E1000_RAH_AV; 9608 9609 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9610 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9611 9612 switch (hw->mac.type) { 9613 case e1000_82575: 9614 case e1000_i210: 9615 if (adapter->mac_table[index].state & 9616 IGB_MAC_STATE_QUEUE_STEERING) 9617 rar_high |= E1000_RAH_QSEL_ENABLE; 9618 9619 rar_high |= E1000_RAH_POOL_1 * 9620 adapter->mac_table[index].queue; 9621 break; 9622 default: 9623 rar_high |= E1000_RAH_POOL_1 << 9624 adapter->mac_table[index].queue; 9625 break; 9626 } 9627 } 9628 9629 wr32(E1000_RAL(index), rar_low); 9630 wrfl(); 9631 wr32(E1000_RAH(index), rar_high); 9632 wrfl(); 9633 } 9634 9635 static int igb_set_vf_mac(struct igb_adapter *adapter, 9636 int vf, unsigned char *mac_addr) 9637 { 9638 struct e1000_hw *hw = &adapter->hw; 9639 /* VF MAC addresses start at end of receive addresses and moves 9640 * towards the first, as a result a collision should not be possible 9641 */ 9642 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9643 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9644 9645 ether_addr_copy(vf_mac_addr, mac_addr); 9646 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9647 adapter->mac_table[rar_entry].queue = vf; 9648 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9649 igb_rar_set_index(adapter, rar_entry); 9650 9651 return 0; 9652 } 9653 9654 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9655 { 9656 struct igb_adapter *adapter = netdev_priv(netdev); 9657 9658 if (vf >= adapter->vfs_allocated_count) 9659 return -EINVAL; 9660 9661 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9662 * flag and allows to overwrite the MAC via VF netdev. This 9663 * is necessary to allow libvirt a way to restore the original 9664 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9665 * down a VM. 9666 */ 9667 if (is_zero_ether_addr(mac)) { 9668 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9669 dev_info(&adapter->pdev->dev, 9670 "remove administratively set MAC on VF %d\n", 9671 vf); 9672 } else if (is_valid_ether_addr(mac)) { 9673 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9674 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9675 mac, vf); 9676 dev_info(&adapter->pdev->dev, 9677 "Reload the VF driver to make this change effective."); 9678 /* Generate additional warning if PF is down */ 9679 if (test_bit(__IGB_DOWN, &adapter->state)) { 9680 dev_warn(&adapter->pdev->dev, 9681 "The VF MAC address has been set, but the PF device is not up.\n"); 9682 dev_warn(&adapter->pdev->dev, 9683 "Bring the PF device up before attempting to use the VF device.\n"); 9684 } 9685 } else { 9686 return -EINVAL; 9687 } 9688 return igb_set_vf_mac(adapter, vf, mac); 9689 } 9690 9691 static int igb_link_mbps(int internal_link_speed) 9692 { 9693 switch (internal_link_speed) { 9694 case SPEED_100: 9695 return 100; 9696 case SPEED_1000: 9697 return 1000; 9698 default: 9699 return 0; 9700 } 9701 } 9702 9703 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9704 int link_speed) 9705 { 9706 int rf_dec, rf_int; 9707 u32 bcnrc_val; 9708 9709 if (tx_rate != 0) { 9710 /* Calculate the rate factor values to set */ 9711 rf_int = link_speed / tx_rate; 9712 rf_dec = (link_speed - (rf_int * tx_rate)); 9713 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9714 tx_rate; 9715 9716 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9717 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9718 E1000_RTTBCNRC_RF_INT_MASK); 9719 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9720 } else { 9721 bcnrc_val = 0; 9722 } 9723 9724 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9725 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9726 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9727 */ 9728 wr32(E1000_RTTBCNRM, 0x14); 9729 wr32(E1000_RTTBCNRC, bcnrc_val); 9730 } 9731 9732 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9733 { 9734 int actual_link_speed, i; 9735 bool reset_rate = false; 9736 9737 /* VF TX rate limit was not set or not supported */ 9738 if ((adapter->vf_rate_link_speed == 0) || 9739 (adapter->hw.mac.type != e1000_82576)) 9740 return; 9741 9742 actual_link_speed = igb_link_mbps(adapter->link_speed); 9743 if (actual_link_speed != adapter->vf_rate_link_speed) { 9744 reset_rate = true; 9745 adapter->vf_rate_link_speed = 0; 9746 dev_info(&adapter->pdev->dev, 9747 "Link speed has been changed. VF Transmit rate is disabled\n"); 9748 } 9749 9750 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9751 if (reset_rate) 9752 adapter->vf_data[i].tx_rate = 0; 9753 9754 igb_set_vf_rate_limit(&adapter->hw, i, 9755 adapter->vf_data[i].tx_rate, 9756 actual_link_speed); 9757 } 9758 } 9759 9760 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9761 int min_tx_rate, int max_tx_rate) 9762 { 9763 struct igb_adapter *adapter = netdev_priv(netdev); 9764 struct e1000_hw *hw = &adapter->hw; 9765 int actual_link_speed; 9766 9767 if (hw->mac.type != e1000_82576) 9768 return -EOPNOTSUPP; 9769 9770 if (min_tx_rate) 9771 return -EINVAL; 9772 9773 actual_link_speed = igb_link_mbps(adapter->link_speed); 9774 if ((vf >= adapter->vfs_allocated_count) || 9775 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9776 (max_tx_rate < 0) || 9777 (max_tx_rate > actual_link_speed)) 9778 return -EINVAL; 9779 9780 adapter->vf_rate_link_speed = actual_link_speed; 9781 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9782 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9783 9784 return 0; 9785 } 9786 9787 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9788 bool setting) 9789 { 9790 struct igb_adapter *adapter = netdev_priv(netdev); 9791 struct e1000_hw *hw = &adapter->hw; 9792 u32 reg_val, reg_offset; 9793 9794 if (!adapter->vfs_allocated_count) 9795 return -EOPNOTSUPP; 9796 9797 if (vf >= adapter->vfs_allocated_count) 9798 return -EINVAL; 9799 9800 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9801 reg_val = rd32(reg_offset); 9802 if (setting) 9803 reg_val |= (BIT(vf) | 9804 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9805 else 9806 reg_val &= ~(BIT(vf) | 9807 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9808 wr32(reg_offset, reg_val); 9809 9810 adapter->vf_data[vf].spoofchk_enabled = setting; 9811 return 0; 9812 } 9813 9814 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9815 { 9816 struct igb_adapter *adapter = netdev_priv(netdev); 9817 9818 if (vf >= adapter->vfs_allocated_count) 9819 return -EINVAL; 9820 if (adapter->vf_data[vf].trusted == setting) 9821 return 0; 9822 9823 adapter->vf_data[vf].trusted = setting; 9824 9825 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9826 vf, setting ? "" : "not "); 9827 return 0; 9828 } 9829 9830 static int igb_ndo_get_vf_config(struct net_device *netdev, 9831 int vf, struct ifla_vf_info *ivi) 9832 { 9833 struct igb_adapter *adapter = netdev_priv(netdev); 9834 if (vf >= adapter->vfs_allocated_count) 9835 return -EINVAL; 9836 ivi->vf = vf; 9837 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9838 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9839 ivi->min_tx_rate = 0; 9840 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9841 ivi->qos = adapter->vf_data[vf].pf_qos; 9842 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9843 ivi->trusted = adapter->vf_data[vf].trusted; 9844 return 0; 9845 } 9846 9847 static void igb_vmm_control(struct igb_adapter *adapter) 9848 { 9849 struct e1000_hw *hw = &adapter->hw; 9850 u32 reg; 9851 9852 switch (hw->mac.type) { 9853 case e1000_82575: 9854 case e1000_i210: 9855 case e1000_i211: 9856 case e1000_i354: 9857 default: 9858 /* replication is not supported for 82575 */ 9859 return; 9860 case e1000_82576: 9861 /* notify HW that the MAC is adding vlan tags */ 9862 reg = rd32(E1000_DTXCTL); 9863 reg |= E1000_DTXCTL_VLAN_ADDED; 9864 wr32(E1000_DTXCTL, reg); 9865 fallthrough; 9866 case e1000_82580: 9867 /* enable replication vlan tag stripping */ 9868 reg = rd32(E1000_RPLOLR); 9869 reg |= E1000_RPLOLR_STRVLAN; 9870 wr32(E1000_RPLOLR, reg); 9871 fallthrough; 9872 case e1000_i350: 9873 /* none of the above registers are supported by i350 */ 9874 break; 9875 } 9876 9877 if (adapter->vfs_allocated_count) { 9878 igb_vmdq_set_loopback_pf(hw, true); 9879 igb_vmdq_set_replication_pf(hw, true); 9880 igb_vmdq_set_anti_spoofing_pf(hw, true, 9881 adapter->vfs_allocated_count); 9882 } else { 9883 igb_vmdq_set_loopback_pf(hw, false); 9884 igb_vmdq_set_replication_pf(hw, false); 9885 } 9886 } 9887 9888 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9889 { 9890 struct e1000_hw *hw = &adapter->hw; 9891 u32 dmac_thr; 9892 u16 hwm; 9893 9894 if (hw->mac.type > e1000_82580) { 9895 if (adapter->flags & IGB_FLAG_DMAC) { 9896 u32 reg; 9897 9898 /* force threshold to 0. */ 9899 wr32(E1000_DMCTXTH, 0); 9900 9901 /* DMA Coalescing high water mark needs to be greater 9902 * than the Rx threshold. Set hwm to PBA - max frame 9903 * size in 16B units, capping it at PBA - 6KB. 9904 */ 9905 hwm = 64 * (pba - 6); 9906 reg = rd32(E1000_FCRTC); 9907 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9908 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9909 & E1000_FCRTC_RTH_COAL_MASK); 9910 wr32(E1000_FCRTC, reg); 9911 9912 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9913 * frame size, capping it at PBA - 10KB. 9914 */ 9915 dmac_thr = pba - 10; 9916 reg = rd32(E1000_DMACR); 9917 reg &= ~E1000_DMACR_DMACTHR_MASK; 9918 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9919 & E1000_DMACR_DMACTHR_MASK); 9920 9921 /* transition to L0x or L1 if available..*/ 9922 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9923 9924 /* watchdog timer= +-1000 usec in 32usec intervals */ 9925 reg |= (1000 >> 5); 9926 9927 /* Disable BMC-to-OS Watchdog Enable */ 9928 if (hw->mac.type != e1000_i354) 9929 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9930 9931 wr32(E1000_DMACR, reg); 9932 9933 /* no lower threshold to disable 9934 * coalescing(smart fifb)-UTRESH=0 9935 */ 9936 wr32(E1000_DMCRTRH, 0); 9937 9938 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9939 9940 wr32(E1000_DMCTLX, reg); 9941 9942 /* free space in tx packet buffer to wake from 9943 * DMA coal 9944 */ 9945 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9946 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9947 9948 /* make low power state decision controlled 9949 * by DMA coal 9950 */ 9951 reg = rd32(E1000_PCIEMISC); 9952 reg &= ~E1000_PCIEMISC_LX_DECISION; 9953 wr32(E1000_PCIEMISC, reg); 9954 } /* endif adapter->dmac is not disabled */ 9955 } else if (hw->mac.type == e1000_82580) { 9956 u32 reg = rd32(E1000_PCIEMISC); 9957 9958 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9959 wr32(E1000_DMACR, 0); 9960 } 9961 } 9962 9963 /** 9964 * igb_read_i2c_byte - Reads 8 bit word over I2C 9965 * @hw: pointer to hardware structure 9966 * @byte_offset: byte offset to read 9967 * @dev_addr: device address 9968 * @data: value read 9969 * 9970 * Performs byte read operation over I2C interface at 9971 * a specified device address. 9972 **/ 9973 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9974 u8 dev_addr, u8 *data) 9975 { 9976 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9977 struct i2c_client *this_client = adapter->i2c_client; 9978 s32 status; 9979 u16 swfw_mask = 0; 9980 9981 if (!this_client) 9982 return E1000_ERR_I2C; 9983 9984 swfw_mask = E1000_SWFW_PHY0_SM; 9985 9986 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9987 return E1000_ERR_SWFW_SYNC; 9988 9989 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9990 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9991 9992 if (status < 0) 9993 return E1000_ERR_I2C; 9994 else { 9995 *data = status; 9996 return 0; 9997 } 9998 } 9999 10000 /** 10001 * igb_write_i2c_byte - Writes 8 bit word over I2C 10002 * @hw: pointer to hardware structure 10003 * @byte_offset: byte offset to write 10004 * @dev_addr: device address 10005 * @data: value to write 10006 * 10007 * Performs byte write operation over I2C interface at 10008 * a specified device address. 10009 **/ 10010 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10011 u8 dev_addr, u8 data) 10012 { 10013 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10014 struct i2c_client *this_client = adapter->i2c_client; 10015 s32 status; 10016 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10017 10018 if (!this_client) 10019 return E1000_ERR_I2C; 10020 10021 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10022 return E1000_ERR_SWFW_SYNC; 10023 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10024 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10025 10026 if (status) 10027 return E1000_ERR_I2C; 10028 else 10029 return 0; 10030 10031 } 10032 10033 int igb_reinit_queues(struct igb_adapter *adapter) 10034 { 10035 struct net_device *netdev = adapter->netdev; 10036 struct pci_dev *pdev = adapter->pdev; 10037 int err = 0; 10038 10039 if (netif_running(netdev)) 10040 igb_close(netdev); 10041 10042 igb_reset_interrupt_capability(adapter); 10043 10044 if (igb_init_interrupt_scheme(adapter, true)) { 10045 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10046 return -ENOMEM; 10047 } 10048 10049 if (netif_running(netdev)) 10050 err = igb_open(netdev); 10051 10052 return err; 10053 } 10054 10055 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10056 { 10057 struct igb_nfc_filter *rule; 10058 10059 spin_lock(&adapter->nfc_lock); 10060 10061 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10062 igb_erase_filter(adapter, rule); 10063 10064 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10065 igb_erase_filter(adapter, rule); 10066 10067 spin_unlock(&adapter->nfc_lock); 10068 } 10069 10070 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10071 { 10072 struct igb_nfc_filter *rule; 10073 10074 spin_lock(&adapter->nfc_lock); 10075 10076 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10077 igb_add_filter(adapter, rule); 10078 10079 spin_unlock(&adapter->nfc_lock); 10080 } 10081 /* igb_main.c */ 10082