1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_clean_tx_ring(struct igb_ring *); 119 static void igb_clean_rx_ring(struct igb_ring *); 120 static void igb_set_rx_mode(struct net_device *); 121 static void igb_update_phy_info(struct timer_list *); 122 static void igb_watchdog(struct timer_list *); 123 static void igb_watchdog_task(struct work_struct *); 124 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 125 static void igb_get_stats64(struct net_device *dev, 126 struct rtnl_link_stats64 *stats); 127 static int igb_change_mtu(struct net_device *, int); 128 static int igb_set_mac(struct net_device *, void *); 129 static void igb_set_uta(struct igb_adapter *adapter, bool set); 130 static irqreturn_t igb_intr(int irq, void *); 131 static irqreturn_t igb_intr_msi(int irq, void *); 132 static irqreturn_t igb_msix_other(int irq, void *); 133 static irqreturn_t igb_msix_ring(int irq, void *); 134 #ifdef CONFIG_IGB_DCA 135 static void igb_update_dca(struct igb_q_vector *); 136 static void igb_setup_dca(struct igb_adapter *); 137 #endif /* CONFIG_IGB_DCA */ 138 static int igb_poll(struct napi_struct *, int); 139 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 140 static int igb_clean_rx_irq(struct igb_q_vector *, int); 141 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 142 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 143 static void igb_reset_task(struct work_struct *); 144 static void igb_vlan_mode(struct net_device *netdev, 145 netdev_features_t features); 146 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 147 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 148 static void igb_restore_vlan(struct igb_adapter *); 149 static void igb_rar_set_index(struct igb_adapter *, u32); 150 static void igb_ping_all_vfs(struct igb_adapter *); 151 static void igb_msg_task(struct igb_adapter *); 152 static void igb_vmm_control(struct igb_adapter *); 153 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 154 static void igb_flush_mac_table(struct igb_adapter *); 155 static int igb_available_rars(struct igb_adapter *, u8); 156 static void igb_set_default_mac_filter(struct igb_adapter *); 157 static int igb_uc_sync(struct net_device *, const unsigned char *); 158 static int igb_uc_unsync(struct net_device *, const unsigned char *); 159 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 160 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 161 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 162 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 163 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 164 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 169 struct ifla_vf_info *ivi); 170 static void igb_check_vf_rate_limit(struct igb_adapter *); 171 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 172 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 173 174 #ifdef CONFIG_PCI_IOV 175 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 176 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 177 #endif 178 179 #ifdef CONFIG_IGB_DCA 180 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 181 static struct notifier_block dca_notifier = { 182 .notifier_call = igb_notify_dca, 183 .next = NULL, 184 .priority = 0 185 }; 186 #endif 187 #ifdef CONFIG_PCI_IOV 188 static unsigned int max_vfs; 189 module_param(max_vfs, uint, 0444); 190 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 191 #endif /* CONFIG_PCI_IOV */ 192 193 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 194 pci_channel_state_t); 195 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 196 static void igb_io_resume(struct pci_dev *); 197 198 static const struct pci_error_handlers igb_err_handler = { 199 .error_detected = igb_io_error_detected, 200 .slot_reset = igb_io_slot_reset, 201 .resume = igb_io_resume, 202 }; 203 204 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 205 206 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 207 MODULE_LICENSE("GPL v2"); 208 209 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 210 static int debug = -1; 211 module_param(debug, int, 0); 212 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 213 214 struct igb_reg_info { 215 u32 ofs; 216 char *name; 217 }; 218 219 static const struct igb_reg_info igb_reg_info_tbl[] = { 220 221 /* General Registers */ 222 {E1000_CTRL, "CTRL"}, 223 {E1000_STATUS, "STATUS"}, 224 {E1000_CTRL_EXT, "CTRL_EXT"}, 225 226 /* Interrupt Registers */ 227 {E1000_ICR, "ICR"}, 228 229 /* RX Registers */ 230 {E1000_RCTL, "RCTL"}, 231 {E1000_RDLEN(0), "RDLEN"}, 232 {E1000_RDH(0), "RDH"}, 233 {E1000_RDT(0), "RDT"}, 234 {E1000_RXDCTL(0), "RXDCTL"}, 235 {E1000_RDBAL(0), "RDBAL"}, 236 {E1000_RDBAH(0), "RDBAH"}, 237 238 /* TX Registers */ 239 {E1000_TCTL, "TCTL"}, 240 {E1000_TDBAL(0), "TDBAL"}, 241 {E1000_TDBAH(0), "TDBAH"}, 242 {E1000_TDLEN(0), "TDLEN"}, 243 {E1000_TDH(0), "TDH"}, 244 {E1000_TDT(0), "TDT"}, 245 {E1000_TXDCTL(0), "TXDCTL"}, 246 {E1000_TDFH, "TDFH"}, 247 {E1000_TDFT, "TDFT"}, 248 {E1000_TDFHS, "TDFHS"}, 249 {E1000_TDFPC, "TDFPC"}, 250 251 /* List Terminator */ 252 {} 253 }; 254 255 /* igb_regdump - register printout routine */ 256 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 257 { 258 int n = 0; 259 char rname[16]; 260 u32 regs[8]; 261 262 switch (reginfo->ofs) { 263 case E1000_RDLEN(0): 264 for (n = 0; n < 4; n++) 265 regs[n] = rd32(E1000_RDLEN(n)); 266 break; 267 case E1000_RDH(0): 268 for (n = 0; n < 4; n++) 269 regs[n] = rd32(E1000_RDH(n)); 270 break; 271 case E1000_RDT(0): 272 for (n = 0; n < 4; n++) 273 regs[n] = rd32(E1000_RDT(n)); 274 break; 275 case E1000_RXDCTL(0): 276 for (n = 0; n < 4; n++) 277 regs[n] = rd32(E1000_RXDCTL(n)); 278 break; 279 case E1000_RDBAL(0): 280 for (n = 0; n < 4; n++) 281 regs[n] = rd32(E1000_RDBAL(n)); 282 break; 283 case E1000_RDBAH(0): 284 for (n = 0; n < 4; n++) 285 regs[n] = rd32(E1000_RDBAH(n)); 286 break; 287 case E1000_TDBAL(0): 288 for (n = 0; n < 4; n++) 289 regs[n] = rd32(E1000_TDBAL(n)); 290 break; 291 case E1000_TDBAH(0): 292 for (n = 0; n < 4; n++) 293 regs[n] = rd32(E1000_TDBAH(n)); 294 break; 295 case E1000_TDLEN(0): 296 for (n = 0; n < 4; n++) 297 regs[n] = rd32(E1000_TDLEN(n)); 298 break; 299 case E1000_TDH(0): 300 for (n = 0; n < 4; n++) 301 regs[n] = rd32(E1000_TDH(n)); 302 break; 303 case E1000_TDT(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_TDT(n)); 306 break; 307 case E1000_TXDCTL(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_TXDCTL(n)); 310 break; 311 default: 312 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 313 return; 314 } 315 316 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 317 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 318 regs[2], regs[3]); 319 } 320 321 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 322 static void igb_dump(struct igb_adapter *adapter) 323 { 324 struct net_device *netdev = adapter->netdev; 325 struct e1000_hw *hw = &adapter->hw; 326 struct igb_reg_info *reginfo; 327 struct igb_ring *tx_ring; 328 union e1000_adv_tx_desc *tx_desc; 329 struct my_u0 { __le64 a; __le64 b; } *u0; 330 struct igb_ring *rx_ring; 331 union e1000_adv_rx_desc *rx_desc; 332 u32 staterr; 333 u16 i, n; 334 335 if (!netif_msg_hw(adapter)) 336 return; 337 338 /* Print netdevice Info */ 339 if (netdev) { 340 dev_info(&adapter->pdev->dev, "Net device Info\n"); 341 pr_info("Device Name state trans_start\n"); 342 pr_info("%-15s %016lX %016lX\n", netdev->name, 343 netdev->state, dev_trans_start(netdev)); 344 } 345 346 /* Print Registers */ 347 dev_info(&adapter->pdev->dev, "Register Dump\n"); 348 pr_info(" Register Name Value\n"); 349 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 350 reginfo->name; reginfo++) { 351 igb_regdump(hw, reginfo); 352 } 353 354 /* Print TX Ring Summary */ 355 if (!netdev || !netif_running(netdev)) 356 goto exit; 357 358 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 359 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 360 for (n = 0; n < adapter->num_tx_queues; n++) { 361 struct igb_tx_buffer *buffer_info; 362 tx_ring = adapter->tx_ring[n]; 363 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 364 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 365 n, tx_ring->next_to_use, tx_ring->next_to_clean, 366 (u64)dma_unmap_addr(buffer_info, dma), 367 dma_unmap_len(buffer_info, len), 368 buffer_info->next_to_watch, 369 (u64)buffer_info->time_stamp); 370 } 371 372 /* Print TX Rings */ 373 if (!netif_msg_tx_done(adapter)) 374 goto rx_ring_summary; 375 376 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 377 378 /* Transmit Descriptor Formats 379 * 380 * Advanced Transmit Descriptor 381 * +--------------------------------------------------------------+ 382 * 0 | Buffer Address [63:0] | 383 * +--------------------------------------------------------------+ 384 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 385 * +--------------------------------------------------------------+ 386 * 63 46 45 40 39 38 36 35 32 31 24 15 0 387 */ 388 389 for (n = 0; n < adapter->num_tx_queues; n++) { 390 tx_ring = adapter->tx_ring[n]; 391 pr_info("------------------------------------\n"); 392 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 393 pr_info("------------------------------------\n"); 394 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 395 396 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 397 const char *next_desc; 398 struct igb_tx_buffer *buffer_info; 399 tx_desc = IGB_TX_DESC(tx_ring, i); 400 buffer_info = &tx_ring->tx_buffer_info[i]; 401 u0 = (struct my_u0 *)tx_desc; 402 if (i == tx_ring->next_to_use && 403 i == tx_ring->next_to_clean) 404 next_desc = " NTC/U"; 405 else if (i == tx_ring->next_to_use) 406 next_desc = " NTU"; 407 else if (i == tx_ring->next_to_clean) 408 next_desc = " NTC"; 409 else 410 next_desc = ""; 411 412 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 413 i, le64_to_cpu(u0->a), 414 le64_to_cpu(u0->b), 415 (u64)dma_unmap_addr(buffer_info, dma), 416 dma_unmap_len(buffer_info, len), 417 buffer_info->next_to_watch, 418 (u64)buffer_info->time_stamp, 419 buffer_info->skb, next_desc); 420 421 if (netif_msg_pktdata(adapter) && buffer_info->skb) 422 print_hex_dump(KERN_INFO, "", 423 DUMP_PREFIX_ADDRESS, 424 16, 1, buffer_info->skb->data, 425 dma_unmap_len(buffer_info, len), 426 true); 427 } 428 } 429 430 /* Print RX Rings Summary */ 431 rx_ring_summary: 432 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 433 pr_info("Queue [NTU] [NTC]\n"); 434 for (n = 0; n < adapter->num_rx_queues; n++) { 435 rx_ring = adapter->rx_ring[n]; 436 pr_info(" %5d %5X %5X\n", 437 n, rx_ring->next_to_use, rx_ring->next_to_clean); 438 } 439 440 /* Print RX Rings */ 441 if (!netif_msg_rx_status(adapter)) 442 goto exit; 443 444 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 445 446 /* Advanced Receive Descriptor (Read) Format 447 * 63 1 0 448 * +-----------------------------------------------------+ 449 * 0 | Packet Buffer Address [63:1] |A0/NSE| 450 * +----------------------------------------------+------+ 451 * 8 | Header Buffer Address [63:1] | DD | 452 * +-----------------------------------------------------+ 453 * 454 * 455 * Advanced Receive Descriptor (Write-Back) Format 456 * 457 * 63 48 47 32 31 30 21 20 17 16 4 3 0 458 * +------------------------------------------------------+ 459 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 460 * | Checksum Ident | | | | Type | Type | 461 * +------------------------------------------------------+ 462 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 463 * +------------------------------------------------------+ 464 * 63 48 47 32 31 20 19 0 465 */ 466 467 for (n = 0; n < adapter->num_rx_queues; n++) { 468 rx_ring = adapter->rx_ring[n]; 469 pr_info("------------------------------------\n"); 470 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 471 pr_info("------------------------------------\n"); 472 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 473 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 474 475 for (i = 0; i < rx_ring->count; i++) { 476 const char *next_desc; 477 struct igb_rx_buffer *buffer_info; 478 buffer_info = &rx_ring->rx_buffer_info[i]; 479 rx_desc = IGB_RX_DESC(rx_ring, i); 480 u0 = (struct my_u0 *)rx_desc; 481 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 482 483 if (i == rx_ring->next_to_use) 484 next_desc = " NTU"; 485 else if (i == rx_ring->next_to_clean) 486 next_desc = " NTC"; 487 else 488 next_desc = ""; 489 490 if (staterr & E1000_RXD_STAT_DD) { 491 /* Descriptor Done */ 492 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 493 "RWB", i, 494 le64_to_cpu(u0->a), 495 le64_to_cpu(u0->b), 496 next_desc); 497 } else { 498 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 499 "R ", i, 500 le64_to_cpu(u0->a), 501 le64_to_cpu(u0->b), 502 (u64)buffer_info->dma, 503 next_desc); 504 505 if (netif_msg_pktdata(adapter) && 506 buffer_info->dma && buffer_info->page) { 507 print_hex_dump(KERN_INFO, "", 508 DUMP_PREFIX_ADDRESS, 509 16, 1, 510 page_address(buffer_info->page) + 511 buffer_info->page_offset, 512 igb_rx_bufsz(rx_ring), true); 513 } 514 } 515 } 516 } 517 518 exit: 519 return; 520 } 521 522 /** 523 * igb_get_i2c_data - Reads the I2C SDA data bit 524 * @data: opaque pointer to adapter struct 525 * 526 * Returns the I2C data bit value 527 **/ 528 static int igb_get_i2c_data(void *data) 529 { 530 struct igb_adapter *adapter = (struct igb_adapter *)data; 531 struct e1000_hw *hw = &adapter->hw; 532 s32 i2cctl = rd32(E1000_I2CPARAMS); 533 534 return !!(i2cctl & E1000_I2C_DATA_IN); 535 } 536 537 /** 538 * igb_set_i2c_data - Sets the I2C data bit 539 * @data: pointer to hardware structure 540 * @state: I2C data value (0 or 1) to set 541 * 542 * Sets the I2C data bit 543 **/ 544 static void igb_set_i2c_data(void *data, int state) 545 { 546 struct igb_adapter *adapter = (struct igb_adapter *)data; 547 struct e1000_hw *hw = &adapter->hw; 548 s32 i2cctl = rd32(E1000_I2CPARAMS); 549 550 if (state) { 551 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 552 } else { 553 i2cctl &= ~E1000_I2C_DATA_OE_N; 554 i2cctl &= ~E1000_I2C_DATA_OUT; 555 } 556 557 wr32(E1000_I2CPARAMS, i2cctl); 558 wrfl(); 559 } 560 561 /** 562 * igb_set_i2c_clk - Sets the I2C SCL clock 563 * @data: pointer to hardware structure 564 * @state: state to set clock 565 * 566 * Sets the I2C clock line to state 567 **/ 568 static void igb_set_i2c_clk(void *data, int state) 569 { 570 struct igb_adapter *adapter = (struct igb_adapter *)data; 571 struct e1000_hw *hw = &adapter->hw; 572 s32 i2cctl = rd32(E1000_I2CPARAMS); 573 574 if (state) { 575 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 576 } else { 577 i2cctl &= ~E1000_I2C_CLK_OUT; 578 i2cctl &= ~E1000_I2C_CLK_OE_N; 579 } 580 wr32(E1000_I2CPARAMS, i2cctl); 581 wrfl(); 582 } 583 584 /** 585 * igb_get_i2c_clk - Gets the I2C SCL clock state 586 * @data: pointer to hardware structure 587 * 588 * Gets the I2C clock state 589 **/ 590 static int igb_get_i2c_clk(void *data) 591 { 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 return !!(i2cctl & E1000_I2C_CLK_IN); 597 } 598 599 static const struct i2c_algo_bit_data igb_i2c_algo = { 600 .setsda = igb_set_i2c_data, 601 .setscl = igb_set_i2c_clk, 602 .getsda = igb_get_i2c_data, 603 .getscl = igb_get_i2c_clk, 604 .udelay = 5, 605 .timeout = 20, 606 }; 607 608 /** 609 * igb_get_hw_dev - return device 610 * @hw: pointer to hardware structure 611 * 612 * used by hardware layer to print debugging information 613 **/ 614 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 615 { 616 struct igb_adapter *adapter = hw->back; 617 return adapter->netdev; 618 } 619 620 static struct pci_driver igb_driver; 621 622 /** 623 * igb_init_module - Driver Registration Routine 624 * 625 * igb_init_module is the first routine called when the driver is 626 * loaded. All it does is register with the PCI subsystem. 627 **/ 628 static int __init igb_init_module(void) 629 { 630 int ret; 631 632 pr_info("%s\n", igb_driver_string); 633 pr_info("%s\n", igb_copyright); 634 635 #ifdef CONFIG_IGB_DCA 636 dca_register_notify(&dca_notifier); 637 #endif 638 ret = pci_register_driver(&igb_driver); 639 return ret; 640 } 641 642 module_init(igb_init_module); 643 644 /** 645 * igb_exit_module - Driver Exit Cleanup Routine 646 * 647 * igb_exit_module is called just before the driver is removed 648 * from memory. 649 **/ 650 static void __exit igb_exit_module(void) 651 { 652 #ifdef CONFIG_IGB_DCA 653 dca_unregister_notify(&dca_notifier); 654 #endif 655 pci_unregister_driver(&igb_driver); 656 } 657 658 module_exit(igb_exit_module); 659 660 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 661 /** 662 * igb_cache_ring_register - Descriptor ring to register mapping 663 * @adapter: board private structure to initialize 664 * 665 * Once we know the feature-set enabled for the device, we'll cache 666 * the register offset the descriptor ring is assigned to. 667 **/ 668 static void igb_cache_ring_register(struct igb_adapter *adapter) 669 { 670 int i = 0, j = 0; 671 u32 rbase_offset = adapter->vfs_allocated_count; 672 673 switch (adapter->hw.mac.type) { 674 case e1000_82576: 675 /* The queues are allocated for virtualization such that VF 0 676 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 677 * In order to avoid collision we start at the first free queue 678 * and continue consuming queues in the same sequence 679 */ 680 if (adapter->vfs_allocated_count) { 681 for (; i < adapter->rss_queues; i++) 682 adapter->rx_ring[i]->reg_idx = rbase_offset + 683 Q_IDX_82576(i); 684 } 685 fallthrough; 686 case e1000_82575: 687 case e1000_82580: 688 case e1000_i350: 689 case e1000_i354: 690 case e1000_i210: 691 case e1000_i211: 692 default: 693 for (; i < adapter->num_rx_queues; i++) 694 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 695 for (; j < adapter->num_tx_queues; j++) 696 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 697 break; 698 } 699 } 700 701 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 702 { 703 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 704 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 705 u32 value = 0; 706 707 if (E1000_REMOVED(hw_addr)) 708 return ~value; 709 710 value = readl(&hw_addr[reg]); 711 712 /* reads should not return all F's */ 713 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 714 struct net_device *netdev = igb->netdev; 715 hw->hw_addr = NULL; 716 netdev_err(netdev, "PCIe link lost\n"); 717 WARN(pci_device_is_present(igb->pdev), 718 "igb: Failed to read reg 0x%x!\n", reg); 719 } 720 721 return value; 722 } 723 724 /** 725 * igb_write_ivar - configure ivar for given MSI-X vector 726 * @hw: pointer to the HW structure 727 * @msix_vector: vector number we are allocating to a given ring 728 * @index: row index of IVAR register to write within IVAR table 729 * @offset: column offset of in IVAR, should be multiple of 8 730 * 731 * This function is intended to handle the writing of the IVAR register 732 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 733 * each containing an cause allocation for an Rx and Tx ring, and a 734 * variable number of rows depending on the number of queues supported. 735 **/ 736 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 737 int index, int offset) 738 { 739 u32 ivar = array_rd32(E1000_IVAR0, index); 740 741 /* clear any bits that are currently set */ 742 ivar &= ~((u32)0xFF << offset); 743 744 /* write vector and valid bit */ 745 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 746 747 array_wr32(E1000_IVAR0, index, ivar); 748 } 749 750 #define IGB_N0_QUEUE -1 751 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 752 { 753 struct igb_adapter *adapter = q_vector->adapter; 754 struct e1000_hw *hw = &adapter->hw; 755 int rx_queue = IGB_N0_QUEUE; 756 int tx_queue = IGB_N0_QUEUE; 757 u32 msixbm = 0; 758 759 if (q_vector->rx.ring) 760 rx_queue = q_vector->rx.ring->reg_idx; 761 if (q_vector->tx.ring) 762 tx_queue = q_vector->tx.ring->reg_idx; 763 764 switch (hw->mac.type) { 765 case e1000_82575: 766 /* The 82575 assigns vectors using a bitmask, which matches the 767 * bitmask for the EICR/EIMS/EIMC registers. To assign one 768 * or more queues to a vector, we write the appropriate bits 769 * into the MSIXBM register for that vector. 770 */ 771 if (rx_queue > IGB_N0_QUEUE) 772 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 773 if (tx_queue > IGB_N0_QUEUE) 774 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 775 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 776 msixbm |= E1000_EIMS_OTHER; 777 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 778 q_vector->eims_value = msixbm; 779 break; 780 case e1000_82576: 781 /* 82576 uses a table that essentially consists of 2 columns 782 * with 8 rows. The ordering is column-major so we use the 783 * lower 3 bits as the row index, and the 4th bit as the 784 * column offset. 785 */ 786 if (rx_queue > IGB_N0_QUEUE) 787 igb_write_ivar(hw, msix_vector, 788 rx_queue & 0x7, 789 (rx_queue & 0x8) << 1); 790 if (tx_queue > IGB_N0_QUEUE) 791 igb_write_ivar(hw, msix_vector, 792 tx_queue & 0x7, 793 ((tx_queue & 0x8) << 1) + 8); 794 q_vector->eims_value = BIT(msix_vector); 795 break; 796 case e1000_82580: 797 case e1000_i350: 798 case e1000_i354: 799 case e1000_i210: 800 case e1000_i211: 801 /* On 82580 and newer adapters the scheme is similar to 82576 802 * however instead of ordering column-major we have things 803 * ordered row-major. So we traverse the table by using 804 * bit 0 as the column offset, and the remaining bits as the 805 * row index. 806 */ 807 if (rx_queue > IGB_N0_QUEUE) 808 igb_write_ivar(hw, msix_vector, 809 rx_queue >> 1, 810 (rx_queue & 0x1) << 4); 811 if (tx_queue > IGB_N0_QUEUE) 812 igb_write_ivar(hw, msix_vector, 813 tx_queue >> 1, 814 ((tx_queue & 0x1) << 4) + 8); 815 q_vector->eims_value = BIT(msix_vector); 816 break; 817 default: 818 BUG(); 819 break; 820 } 821 822 /* add q_vector eims value to global eims_enable_mask */ 823 adapter->eims_enable_mask |= q_vector->eims_value; 824 825 /* configure q_vector to set itr on first interrupt */ 826 q_vector->set_itr = 1; 827 } 828 829 /** 830 * igb_configure_msix - Configure MSI-X hardware 831 * @adapter: board private structure to initialize 832 * 833 * igb_configure_msix sets up the hardware to properly 834 * generate MSI-X interrupts. 835 **/ 836 static void igb_configure_msix(struct igb_adapter *adapter) 837 { 838 u32 tmp; 839 int i, vector = 0; 840 struct e1000_hw *hw = &adapter->hw; 841 842 adapter->eims_enable_mask = 0; 843 844 /* set vector for other causes, i.e. link changes */ 845 switch (hw->mac.type) { 846 case e1000_82575: 847 tmp = rd32(E1000_CTRL_EXT); 848 /* enable MSI-X PBA support*/ 849 tmp |= E1000_CTRL_EXT_PBA_CLR; 850 851 /* Auto-Mask interrupts upon ICR read. */ 852 tmp |= E1000_CTRL_EXT_EIAME; 853 tmp |= E1000_CTRL_EXT_IRCA; 854 855 wr32(E1000_CTRL_EXT, tmp); 856 857 /* enable msix_other interrupt */ 858 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 859 adapter->eims_other = E1000_EIMS_OTHER; 860 861 break; 862 863 case e1000_82576: 864 case e1000_82580: 865 case e1000_i350: 866 case e1000_i354: 867 case e1000_i210: 868 case e1000_i211: 869 /* Turn on MSI-X capability first, or our settings 870 * won't stick. And it will take days to debug. 871 */ 872 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 873 E1000_GPIE_PBA | E1000_GPIE_EIAME | 874 E1000_GPIE_NSICR); 875 876 /* enable msix_other interrupt */ 877 adapter->eims_other = BIT(vector); 878 tmp = (vector++ | E1000_IVAR_VALID) << 8; 879 880 wr32(E1000_IVAR_MISC, tmp); 881 break; 882 default: 883 /* do nothing, since nothing else supports MSI-X */ 884 break; 885 } /* switch (hw->mac.type) */ 886 887 adapter->eims_enable_mask |= adapter->eims_other; 888 889 for (i = 0; i < adapter->num_q_vectors; i++) 890 igb_assign_vector(adapter->q_vector[i], vector++); 891 892 wrfl(); 893 } 894 895 /** 896 * igb_request_msix - Initialize MSI-X interrupts 897 * @adapter: board private structure to initialize 898 * 899 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 900 * kernel. 901 **/ 902 static int igb_request_msix(struct igb_adapter *adapter) 903 { 904 unsigned int num_q_vectors = adapter->num_q_vectors; 905 struct net_device *netdev = adapter->netdev; 906 int i, err = 0, vector = 0, free_vector = 0; 907 908 err = request_irq(adapter->msix_entries[vector].vector, 909 igb_msix_other, 0, netdev->name, adapter); 910 if (err) 911 goto err_out; 912 913 if (num_q_vectors > MAX_Q_VECTORS) { 914 num_q_vectors = MAX_Q_VECTORS; 915 dev_warn(&adapter->pdev->dev, 916 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 917 adapter->num_q_vectors, MAX_Q_VECTORS); 918 } 919 for (i = 0; i < num_q_vectors; i++) { 920 struct igb_q_vector *q_vector = adapter->q_vector[i]; 921 922 vector++; 923 924 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 925 926 if (q_vector->rx.ring && q_vector->tx.ring) 927 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 928 q_vector->rx.ring->queue_index); 929 else if (q_vector->tx.ring) 930 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 931 q_vector->tx.ring->queue_index); 932 else if (q_vector->rx.ring) 933 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 934 q_vector->rx.ring->queue_index); 935 else 936 sprintf(q_vector->name, "%s-unused", netdev->name); 937 938 err = request_irq(adapter->msix_entries[vector].vector, 939 igb_msix_ring, 0, q_vector->name, 940 q_vector); 941 if (err) 942 goto err_free; 943 } 944 945 igb_configure_msix(adapter); 946 return 0; 947 948 err_free: 949 /* free already assigned IRQs */ 950 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 951 952 vector--; 953 for (i = 0; i < vector; i++) { 954 free_irq(adapter->msix_entries[free_vector++].vector, 955 adapter->q_vector[i]); 956 } 957 err_out: 958 return err; 959 } 960 961 /** 962 * igb_free_q_vector - Free memory allocated for specific interrupt vector 963 * @adapter: board private structure to initialize 964 * @v_idx: Index of vector to be freed 965 * 966 * This function frees the memory allocated to the q_vector. 967 **/ 968 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 969 { 970 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 971 972 adapter->q_vector[v_idx] = NULL; 973 974 /* igb_get_stats64() might access the rings on this vector, 975 * we must wait a grace period before freeing it. 976 */ 977 if (q_vector) 978 kfree_rcu(q_vector, rcu); 979 } 980 981 /** 982 * igb_reset_q_vector - Reset config for interrupt vector 983 * @adapter: board private structure to initialize 984 * @v_idx: Index of vector to be reset 985 * 986 * If NAPI is enabled it will delete any references to the 987 * NAPI struct. This is preparation for igb_free_q_vector. 988 **/ 989 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 990 { 991 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 992 993 /* Coming from igb_set_interrupt_capability, the vectors are not yet 994 * allocated. So, q_vector is NULL so we should stop here. 995 */ 996 if (!q_vector) 997 return; 998 999 if (q_vector->tx.ring) 1000 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1001 1002 if (q_vector->rx.ring) 1003 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1004 1005 netif_napi_del(&q_vector->napi); 1006 1007 } 1008 1009 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1010 { 1011 int v_idx = adapter->num_q_vectors; 1012 1013 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1014 pci_disable_msix(adapter->pdev); 1015 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1016 pci_disable_msi(adapter->pdev); 1017 1018 while (v_idx--) 1019 igb_reset_q_vector(adapter, v_idx); 1020 } 1021 1022 /** 1023 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1024 * @adapter: board private structure to initialize 1025 * 1026 * This function frees the memory allocated to the q_vectors. In addition if 1027 * NAPI is enabled it will delete any references to the NAPI struct prior 1028 * to freeing the q_vector. 1029 **/ 1030 static void igb_free_q_vectors(struct igb_adapter *adapter) 1031 { 1032 int v_idx = adapter->num_q_vectors; 1033 1034 adapter->num_tx_queues = 0; 1035 adapter->num_rx_queues = 0; 1036 adapter->num_q_vectors = 0; 1037 1038 while (v_idx--) { 1039 igb_reset_q_vector(adapter, v_idx); 1040 igb_free_q_vector(adapter, v_idx); 1041 } 1042 } 1043 1044 /** 1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1046 * @adapter: board private structure to initialize 1047 * 1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1049 * MSI-X interrupts allocated. 1050 */ 1051 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1052 { 1053 igb_free_q_vectors(adapter); 1054 igb_reset_interrupt_capability(adapter); 1055 } 1056 1057 /** 1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1059 * @adapter: board private structure to initialize 1060 * @msix: boolean value of MSIX capability 1061 * 1062 * Attempt to configure interrupts using the best available 1063 * capabilities of the hardware and kernel. 1064 **/ 1065 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1066 { 1067 int err; 1068 int numvecs, i; 1069 1070 if (!msix) 1071 goto msi_only; 1072 adapter->flags |= IGB_FLAG_HAS_MSIX; 1073 1074 /* Number of supported queues. */ 1075 adapter->num_rx_queues = adapter->rss_queues; 1076 if (adapter->vfs_allocated_count) 1077 adapter->num_tx_queues = 1; 1078 else 1079 adapter->num_tx_queues = adapter->rss_queues; 1080 1081 /* start with one vector for every Rx queue */ 1082 numvecs = adapter->num_rx_queues; 1083 1084 /* if Tx handler is separate add 1 for every Tx queue */ 1085 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1086 numvecs += adapter->num_tx_queues; 1087 1088 /* store the number of vectors reserved for queues */ 1089 adapter->num_q_vectors = numvecs; 1090 1091 /* add 1 vector for link status interrupts */ 1092 numvecs++; 1093 for (i = 0; i < numvecs; i++) 1094 adapter->msix_entries[i].entry = i; 1095 1096 err = pci_enable_msix_range(adapter->pdev, 1097 adapter->msix_entries, 1098 numvecs, 1099 numvecs); 1100 if (err > 0) 1101 return; 1102 1103 igb_reset_interrupt_capability(adapter); 1104 1105 /* If we can't do MSI-X, try MSI */ 1106 msi_only: 1107 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1108 #ifdef CONFIG_PCI_IOV 1109 /* disable SR-IOV for non MSI-X configurations */ 1110 if (adapter->vf_data) { 1111 struct e1000_hw *hw = &adapter->hw; 1112 /* disable iov and allow time for transactions to clear */ 1113 pci_disable_sriov(adapter->pdev); 1114 msleep(500); 1115 1116 kfree(adapter->vf_mac_list); 1117 adapter->vf_mac_list = NULL; 1118 kfree(adapter->vf_data); 1119 adapter->vf_data = NULL; 1120 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1121 wrfl(); 1122 msleep(100); 1123 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1124 } 1125 #endif 1126 adapter->vfs_allocated_count = 0; 1127 adapter->rss_queues = 1; 1128 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1129 adapter->num_rx_queues = 1; 1130 adapter->num_tx_queues = 1; 1131 adapter->num_q_vectors = 1; 1132 if (!pci_enable_msi(adapter->pdev)) 1133 adapter->flags |= IGB_FLAG_HAS_MSI; 1134 } 1135 1136 static void igb_add_ring(struct igb_ring *ring, 1137 struct igb_ring_container *head) 1138 { 1139 head->ring = ring; 1140 head->count++; 1141 } 1142 1143 /** 1144 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1145 * @adapter: board private structure to initialize 1146 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1147 * @v_idx: index of vector in adapter struct 1148 * @txr_count: total number of Tx rings to allocate 1149 * @txr_idx: index of first Tx ring to allocate 1150 * @rxr_count: total number of Rx rings to allocate 1151 * @rxr_idx: index of first Rx ring to allocate 1152 * 1153 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1154 **/ 1155 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1156 int v_count, int v_idx, 1157 int txr_count, int txr_idx, 1158 int rxr_count, int rxr_idx) 1159 { 1160 struct igb_q_vector *q_vector; 1161 struct igb_ring *ring; 1162 int ring_count; 1163 size_t size; 1164 1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1166 if (txr_count > 1 || rxr_count > 1) 1167 return -ENOMEM; 1168 1169 ring_count = txr_count + rxr_count; 1170 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1171 1172 /* allocate q_vector and rings */ 1173 q_vector = adapter->q_vector[v_idx]; 1174 if (!q_vector) { 1175 q_vector = kzalloc(size, GFP_KERNEL); 1176 } else if (size > ksize(q_vector)) { 1177 struct igb_q_vector *new_q_vector; 1178 1179 new_q_vector = kzalloc(size, GFP_KERNEL); 1180 if (new_q_vector) 1181 kfree_rcu(q_vector, rcu); 1182 q_vector = new_q_vector; 1183 } else { 1184 memset(q_vector, 0, size); 1185 } 1186 if (!q_vector) 1187 return -ENOMEM; 1188 1189 /* initialize NAPI */ 1190 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1191 1192 /* tie q_vector and adapter together */ 1193 adapter->q_vector[v_idx] = q_vector; 1194 q_vector->adapter = adapter; 1195 1196 /* initialize work limits */ 1197 q_vector->tx.work_limit = adapter->tx_work_limit; 1198 1199 /* initialize ITR configuration */ 1200 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1201 q_vector->itr_val = IGB_START_ITR; 1202 1203 /* initialize pointer to rings */ 1204 ring = q_vector->ring; 1205 1206 /* intialize ITR */ 1207 if (rxr_count) { 1208 /* rx or rx/tx vector */ 1209 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1210 q_vector->itr_val = adapter->rx_itr_setting; 1211 } else { 1212 /* tx only vector */ 1213 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1214 q_vector->itr_val = adapter->tx_itr_setting; 1215 } 1216 1217 if (txr_count) { 1218 /* assign generic ring traits */ 1219 ring->dev = &adapter->pdev->dev; 1220 ring->netdev = adapter->netdev; 1221 1222 /* configure backlink on ring */ 1223 ring->q_vector = q_vector; 1224 1225 /* update q_vector Tx values */ 1226 igb_add_ring(ring, &q_vector->tx); 1227 1228 /* For 82575, context index must be unique per ring. */ 1229 if (adapter->hw.mac.type == e1000_82575) 1230 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1231 1232 /* apply Tx specific ring traits */ 1233 ring->count = adapter->tx_ring_count; 1234 ring->queue_index = txr_idx; 1235 1236 ring->cbs_enable = false; 1237 ring->idleslope = 0; 1238 ring->sendslope = 0; 1239 ring->hicredit = 0; 1240 ring->locredit = 0; 1241 1242 u64_stats_init(&ring->tx_syncp); 1243 u64_stats_init(&ring->tx_syncp2); 1244 1245 /* assign ring to adapter */ 1246 adapter->tx_ring[txr_idx] = ring; 1247 1248 /* push pointer to next ring */ 1249 ring++; 1250 } 1251 1252 if (rxr_count) { 1253 /* assign generic ring traits */ 1254 ring->dev = &adapter->pdev->dev; 1255 ring->netdev = adapter->netdev; 1256 1257 /* configure backlink on ring */ 1258 ring->q_vector = q_vector; 1259 1260 /* update q_vector Rx values */ 1261 igb_add_ring(ring, &q_vector->rx); 1262 1263 /* set flag indicating ring supports SCTP checksum offload */ 1264 if (adapter->hw.mac.type >= e1000_82576) 1265 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1266 1267 /* On i350, i354, i210, and i211, loopback VLAN packets 1268 * have the tag byte-swapped. 1269 */ 1270 if (adapter->hw.mac.type >= e1000_i350) 1271 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1272 1273 /* apply Rx specific ring traits */ 1274 ring->count = adapter->rx_ring_count; 1275 ring->queue_index = rxr_idx; 1276 1277 u64_stats_init(&ring->rx_syncp); 1278 1279 /* assign ring to adapter */ 1280 adapter->rx_ring[rxr_idx] = ring; 1281 } 1282 1283 return 0; 1284 } 1285 1286 1287 /** 1288 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1289 * @adapter: board private structure to initialize 1290 * 1291 * We allocate one q_vector per queue interrupt. If allocation fails we 1292 * return -ENOMEM. 1293 **/ 1294 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1295 { 1296 int q_vectors = adapter->num_q_vectors; 1297 int rxr_remaining = adapter->num_rx_queues; 1298 int txr_remaining = adapter->num_tx_queues; 1299 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1300 int err; 1301 1302 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1303 for (; rxr_remaining; v_idx++) { 1304 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1305 0, 0, 1, rxr_idx); 1306 1307 if (err) 1308 goto err_out; 1309 1310 /* update counts and index */ 1311 rxr_remaining--; 1312 rxr_idx++; 1313 } 1314 } 1315 1316 for (; v_idx < q_vectors; v_idx++) { 1317 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1318 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1319 1320 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1321 tqpv, txr_idx, rqpv, rxr_idx); 1322 1323 if (err) 1324 goto err_out; 1325 1326 /* update counts and index */ 1327 rxr_remaining -= rqpv; 1328 txr_remaining -= tqpv; 1329 rxr_idx++; 1330 txr_idx++; 1331 } 1332 1333 return 0; 1334 1335 err_out: 1336 adapter->num_tx_queues = 0; 1337 adapter->num_rx_queues = 0; 1338 adapter->num_q_vectors = 0; 1339 1340 while (v_idx--) 1341 igb_free_q_vector(adapter, v_idx); 1342 1343 return -ENOMEM; 1344 } 1345 1346 /** 1347 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1348 * @adapter: board private structure to initialize 1349 * @msix: boolean value of MSIX capability 1350 * 1351 * This function initializes the interrupts and allocates all of the queues. 1352 **/ 1353 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1354 { 1355 struct pci_dev *pdev = adapter->pdev; 1356 int err; 1357 1358 igb_set_interrupt_capability(adapter, msix); 1359 1360 err = igb_alloc_q_vectors(adapter); 1361 if (err) { 1362 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1363 goto err_alloc_q_vectors; 1364 } 1365 1366 igb_cache_ring_register(adapter); 1367 1368 return 0; 1369 1370 err_alloc_q_vectors: 1371 igb_reset_interrupt_capability(adapter); 1372 return err; 1373 } 1374 1375 /** 1376 * igb_request_irq - initialize interrupts 1377 * @adapter: board private structure to initialize 1378 * 1379 * Attempts to configure interrupts using the best available 1380 * capabilities of the hardware and kernel. 1381 **/ 1382 static int igb_request_irq(struct igb_adapter *adapter) 1383 { 1384 struct net_device *netdev = adapter->netdev; 1385 struct pci_dev *pdev = adapter->pdev; 1386 int err = 0; 1387 1388 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1389 err = igb_request_msix(adapter); 1390 if (!err) 1391 goto request_done; 1392 /* fall back to MSI */ 1393 igb_free_all_tx_resources(adapter); 1394 igb_free_all_rx_resources(adapter); 1395 1396 igb_clear_interrupt_scheme(adapter); 1397 err = igb_init_interrupt_scheme(adapter, false); 1398 if (err) 1399 goto request_done; 1400 1401 igb_setup_all_tx_resources(adapter); 1402 igb_setup_all_rx_resources(adapter); 1403 igb_configure(adapter); 1404 } 1405 1406 igb_assign_vector(adapter->q_vector[0], 0); 1407 1408 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1409 err = request_irq(pdev->irq, igb_intr_msi, 0, 1410 netdev->name, adapter); 1411 if (!err) 1412 goto request_done; 1413 1414 /* fall back to legacy interrupts */ 1415 igb_reset_interrupt_capability(adapter); 1416 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1417 } 1418 1419 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1420 netdev->name, adapter); 1421 1422 if (err) 1423 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1424 err); 1425 1426 request_done: 1427 return err; 1428 } 1429 1430 static void igb_free_irq(struct igb_adapter *adapter) 1431 { 1432 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1433 int vector = 0, i; 1434 1435 free_irq(adapter->msix_entries[vector++].vector, adapter); 1436 1437 for (i = 0; i < adapter->num_q_vectors; i++) 1438 free_irq(adapter->msix_entries[vector++].vector, 1439 adapter->q_vector[i]); 1440 } else { 1441 free_irq(adapter->pdev->irq, adapter); 1442 } 1443 } 1444 1445 /** 1446 * igb_irq_disable - Mask off interrupt generation on the NIC 1447 * @adapter: board private structure 1448 **/ 1449 static void igb_irq_disable(struct igb_adapter *adapter) 1450 { 1451 struct e1000_hw *hw = &adapter->hw; 1452 1453 /* we need to be careful when disabling interrupts. The VFs are also 1454 * mapped into these registers and so clearing the bits can cause 1455 * issues on the VF drivers so we only need to clear what we set 1456 */ 1457 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1458 u32 regval = rd32(E1000_EIAM); 1459 1460 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1461 wr32(E1000_EIMC, adapter->eims_enable_mask); 1462 regval = rd32(E1000_EIAC); 1463 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1464 } 1465 1466 wr32(E1000_IAM, 0); 1467 wr32(E1000_IMC, ~0); 1468 wrfl(); 1469 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1470 int i; 1471 1472 for (i = 0; i < adapter->num_q_vectors; i++) 1473 synchronize_irq(adapter->msix_entries[i].vector); 1474 } else { 1475 synchronize_irq(adapter->pdev->irq); 1476 } 1477 } 1478 1479 /** 1480 * igb_irq_enable - Enable default interrupt generation settings 1481 * @adapter: board private structure 1482 **/ 1483 static void igb_irq_enable(struct igb_adapter *adapter) 1484 { 1485 struct e1000_hw *hw = &adapter->hw; 1486 1487 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1488 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1489 u32 regval = rd32(E1000_EIAC); 1490 1491 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1492 regval = rd32(E1000_EIAM); 1493 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1494 wr32(E1000_EIMS, adapter->eims_enable_mask); 1495 if (adapter->vfs_allocated_count) { 1496 wr32(E1000_MBVFIMR, 0xFF); 1497 ims |= E1000_IMS_VMMB; 1498 } 1499 wr32(E1000_IMS, ims); 1500 } else { 1501 wr32(E1000_IMS, IMS_ENABLE_MASK | 1502 E1000_IMS_DRSTA); 1503 wr32(E1000_IAM, IMS_ENABLE_MASK | 1504 E1000_IMS_DRSTA); 1505 } 1506 } 1507 1508 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1509 { 1510 struct e1000_hw *hw = &adapter->hw; 1511 u16 pf_id = adapter->vfs_allocated_count; 1512 u16 vid = adapter->hw.mng_cookie.vlan_id; 1513 u16 old_vid = adapter->mng_vlan_id; 1514 1515 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1516 /* add VID to filter table */ 1517 igb_vfta_set(hw, vid, pf_id, true, true); 1518 adapter->mng_vlan_id = vid; 1519 } else { 1520 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1521 } 1522 1523 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1524 (vid != old_vid) && 1525 !test_bit(old_vid, adapter->active_vlans)) { 1526 /* remove VID from filter table */ 1527 igb_vfta_set(hw, vid, pf_id, false, true); 1528 } 1529 } 1530 1531 /** 1532 * igb_release_hw_control - release control of the h/w to f/w 1533 * @adapter: address of board private structure 1534 * 1535 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1536 * For ASF and Pass Through versions of f/w this means that the 1537 * driver is no longer loaded. 1538 **/ 1539 static void igb_release_hw_control(struct igb_adapter *adapter) 1540 { 1541 struct e1000_hw *hw = &adapter->hw; 1542 u32 ctrl_ext; 1543 1544 /* Let firmware take over control of h/w */ 1545 ctrl_ext = rd32(E1000_CTRL_EXT); 1546 wr32(E1000_CTRL_EXT, 1547 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1548 } 1549 1550 /** 1551 * igb_get_hw_control - get control of the h/w from f/w 1552 * @adapter: address of board private structure 1553 * 1554 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1555 * For ASF and Pass Through versions of f/w this means that 1556 * the driver is loaded. 1557 **/ 1558 static void igb_get_hw_control(struct igb_adapter *adapter) 1559 { 1560 struct e1000_hw *hw = &adapter->hw; 1561 u32 ctrl_ext; 1562 1563 /* Let firmware know the driver has taken over */ 1564 ctrl_ext = rd32(E1000_CTRL_EXT); 1565 wr32(E1000_CTRL_EXT, 1566 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1567 } 1568 1569 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1570 { 1571 struct net_device *netdev = adapter->netdev; 1572 struct e1000_hw *hw = &adapter->hw; 1573 1574 WARN_ON(hw->mac.type != e1000_i210); 1575 1576 if (enable) 1577 adapter->flags |= IGB_FLAG_FQTSS; 1578 else 1579 adapter->flags &= ~IGB_FLAG_FQTSS; 1580 1581 if (netif_running(netdev)) 1582 schedule_work(&adapter->reset_task); 1583 } 1584 1585 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1586 { 1587 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1588 } 1589 1590 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1591 enum tx_queue_prio prio) 1592 { 1593 u32 val; 1594 1595 WARN_ON(hw->mac.type != e1000_i210); 1596 WARN_ON(queue < 0 || queue > 4); 1597 1598 val = rd32(E1000_I210_TXDCTL(queue)); 1599 1600 if (prio == TX_QUEUE_PRIO_HIGH) 1601 val |= E1000_TXDCTL_PRIORITY; 1602 else 1603 val &= ~E1000_TXDCTL_PRIORITY; 1604 1605 wr32(E1000_I210_TXDCTL(queue), val); 1606 } 1607 1608 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1609 { 1610 u32 val; 1611 1612 WARN_ON(hw->mac.type != e1000_i210); 1613 WARN_ON(queue < 0 || queue > 1); 1614 1615 val = rd32(E1000_I210_TQAVCC(queue)); 1616 1617 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1618 val |= E1000_TQAVCC_QUEUEMODE; 1619 else 1620 val &= ~E1000_TQAVCC_QUEUEMODE; 1621 1622 wr32(E1000_I210_TQAVCC(queue), val); 1623 } 1624 1625 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1626 { 1627 int i; 1628 1629 for (i = 0; i < adapter->num_tx_queues; i++) { 1630 if (adapter->tx_ring[i]->cbs_enable) 1631 return true; 1632 } 1633 1634 return false; 1635 } 1636 1637 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1638 { 1639 int i; 1640 1641 for (i = 0; i < adapter->num_tx_queues; i++) { 1642 if (adapter->tx_ring[i]->launchtime_enable) 1643 return true; 1644 } 1645 1646 return false; 1647 } 1648 1649 /** 1650 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1651 * @adapter: pointer to adapter struct 1652 * @queue: queue number 1653 * 1654 * Configure CBS and Launchtime for a given hardware queue. 1655 * Parameters are retrieved from the correct Tx ring, so 1656 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1657 * for setting those correctly prior to this function being called. 1658 **/ 1659 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1660 { 1661 struct net_device *netdev = adapter->netdev; 1662 struct e1000_hw *hw = &adapter->hw; 1663 struct igb_ring *ring; 1664 u32 tqavcc, tqavctrl; 1665 u16 value; 1666 1667 WARN_ON(hw->mac.type != e1000_i210); 1668 WARN_ON(queue < 0 || queue > 1); 1669 ring = adapter->tx_ring[queue]; 1670 1671 /* If any of the Qav features is enabled, configure queues as SR and 1672 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1673 * as SP. 1674 */ 1675 if (ring->cbs_enable || ring->launchtime_enable) { 1676 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1677 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1678 } else { 1679 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1680 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1681 } 1682 1683 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1684 if (ring->cbs_enable || queue == 0) { 1685 /* i210 does not allow the queue 0 to be in the Strict 1686 * Priority mode while the Qav mode is enabled, so, 1687 * instead of disabling strict priority mode, we give 1688 * queue 0 the maximum of credits possible. 1689 * 1690 * See section 8.12.19 of the i210 datasheet, "Note: 1691 * Queue0 QueueMode must be set to 1b when 1692 * TransmitMode is set to Qav." 1693 */ 1694 if (queue == 0 && !ring->cbs_enable) { 1695 /* max "linkspeed" idleslope in kbps */ 1696 ring->idleslope = 1000000; 1697 ring->hicredit = ETH_FRAME_LEN; 1698 } 1699 1700 /* Always set data transfer arbitration to credit-based 1701 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1702 * the queues. 1703 */ 1704 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1705 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1706 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1707 1708 /* According to i210 datasheet section 7.2.7.7, we should set 1709 * the 'idleSlope' field from TQAVCC register following the 1710 * equation: 1711 * 1712 * For 100 Mbps link speed: 1713 * 1714 * value = BW * 0x7735 * 0.2 (E1) 1715 * 1716 * For 1000Mbps link speed: 1717 * 1718 * value = BW * 0x7735 * 2 (E2) 1719 * 1720 * E1 and E2 can be merged into one equation as shown below. 1721 * Note that 'link-speed' is in Mbps. 1722 * 1723 * value = BW * 0x7735 * 2 * link-speed 1724 * -------------- (E3) 1725 * 1000 1726 * 1727 * 'BW' is the percentage bandwidth out of full link speed 1728 * which can be found with the following equation. Note that 1729 * idleSlope here is the parameter from this function which 1730 * is in kbps. 1731 * 1732 * BW = idleSlope 1733 * ----------------- (E4) 1734 * link-speed * 1000 1735 * 1736 * That said, we can come up with a generic equation to 1737 * calculate the value we should set it TQAVCC register by 1738 * replacing 'BW' in E3 by E4. The resulting equation is: 1739 * 1740 * value = idleSlope * 0x7735 * 2 * link-speed 1741 * ----------------- -------------- (E5) 1742 * link-speed * 1000 1000 1743 * 1744 * 'link-speed' is present in both sides of the fraction so 1745 * it is canceled out. The final equation is the following: 1746 * 1747 * value = idleSlope * 61034 1748 * ----------------- (E6) 1749 * 1000000 1750 * 1751 * NOTE: For i210, given the above, we can see that idleslope 1752 * is represented in 16.38431 kbps units by the value at 1753 * the TQAVCC register (1Gbps / 61034), which reduces 1754 * the granularity for idleslope increments. 1755 * For instance, if you want to configure a 2576kbps 1756 * idleslope, the value to be written on the register 1757 * would have to be 157.23. If rounded down, you end 1758 * up with less bandwidth available than originally 1759 * required (~2572 kbps). If rounded up, you end up 1760 * with a higher bandwidth (~2589 kbps). Below the 1761 * approach we take is to always round up the 1762 * calculated value, so the resulting bandwidth might 1763 * be slightly higher for some configurations. 1764 */ 1765 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1766 1767 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1768 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1769 tqavcc |= value; 1770 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1771 1772 wr32(E1000_I210_TQAVHC(queue), 1773 0x80000000 + ring->hicredit * 0x7735); 1774 } else { 1775 1776 /* Set idleSlope to zero. */ 1777 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1778 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1779 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1780 1781 /* Set hiCredit to zero. */ 1782 wr32(E1000_I210_TQAVHC(queue), 0); 1783 1784 /* If CBS is not enabled for any queues anymore, then return to 1785 * the default state of Data Transmission Arbitration on 1786 * TQAVCTRL. 1787 */ 1788 if (!is_any_cbs_enabled(adapter)) { 1789 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1790 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1791 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1792 } 1793 } 1794 1795 /* If LaunchTime is enabled, set DataTranTIM. */ 1796 if (ring->launchtime_enable) { 1797 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1798 * for any of the SR queues, and configure fetchtime delta. 1799 * XXX NOTE: 1800 * - LaunchTime will be enabled for all SR queues. 1801 * - A fixed offset can be added relative to the launch 1802 * time of all packets if configured at reg LAUNCH_OS0. 1803 * We are keeping it as 0 for now (default value). 1804 */ 1805 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1806 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1807 E1000_TQAVCTRL_FETCHTIME_DELTA; 1808 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1809 } else { 1810 /* If Launchtime is not enabled for any SR queues anymore, 1811 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1812 * effectively disabling Launchtime. 1813 */ 1814 if (!is_any_txtime_enabled(adapter)) { 1815 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1816 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1817 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } 1820 } 1821 1822 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1823 * CBS are not configurable by software so we don't do any 'controller 1824 * configuration' in respect to these parameters. 1825 */ 1826 1827 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1828 ring->cbs_enable ? "enabled" : "disabled", 1829 ring->launchtime_enable ? "enabled" : "disabled", 1830 queue, 1831 ring->idleslope, ring->sendslope, 1832 ring->hicredit, ring->locredit); 1833 } 1834 1835 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1836 bool enable) 1837 { 1838 struct igb_ring *ring; 1839 1840 if (queue < 0 || queue > adapter->num_tx_queues) 1841 return -EINVAL; 1842 1843 ring = adapter->tx_ring[queue]; 1844 ring->launchtime_enable = enable; 1845 1846 return 0; 1847 } 1848 1849 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1850 bool enable, int idleslope, int sendslope, 1851 int hicredit, int locredit) 1852 { 1853 struct igb_ring *ring; 1854 1855 if (queue < 0 || queue > adapter->num_tx_queues) 1856 return -EINVAL; 1857 1858 ring = adapter->tx_ring[queue]; 1859 1860 ring->cbs_enable = enable; 1861 ring->idleslope = idleslope; 1862 ring->sendslope = sendslope; 1863 ring->hicredit = hicredit; 1864 ring->locredit = locredit; 1865 1866 return 0; 1867 } 1868 1869 /** 1870 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1871 * @adapter: pointer to adapter struct 1872 * 1873 * Configure TQAVCTRL register switching the controller's Tx mode 1874 * if FQTSS mode is enabled or disabled. Additionally, will issue 1875 * a call to igb_config_tx_modes() per queue so any previously saved 1876 * Tx parameters are applied. 1877 **/ 1878 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1879 { 1880 struct net_device *netdev = adapter->netdev; 1881 struct e1000_hw *hw = &adapter->hw; 1882 u32 val; 1883 1884 /* Only i210 controller supports changing the transmission mode. */ 1885 if (hw->mac.type != e1000_i210) 1886 return; 1887 1888 if (is_fqtss_enabled(adapter)) { 1889 int i, max_queue; 1890 1891 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1892 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1893 * so SP queues wait for SR ones. 1894 */ 1895 val = rd32(E1000_I210_TQAVCTRL); 1896 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1897 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1898 wr32(E1000_I210_TQAVCTRL, val); 1899 1900 /* Configure Tx and Rx packet buffers sizes as described in 1901 * i210 datasheet section 7.2.7.7. 1902 */ 1903 val = rd32(E1000_TXPBS); 1904 val &= ~I210_TXPBSIZE_MASK; 1905 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1906 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1907 wr32(E1000_TXPBS, val); 1908 1909 val = rd32(E1000_RXPBS); 1910 val &= ~I210_RXPBSIZE_MASK; 1911 val |= I210_RXPBSIZE_PB_30KB; 1912 wr32(E1000_RXPBS, val); 1913 1914 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1915 * register should not exceed the buffer size programmed in 1916 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1917 * so according to the datasheet we should set MAX_TPKT_SIZE to 1918 * 4kB / 64. 1919 * 1920 * However, when we do so, no frame from queue 2 and 3 are 1921 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1922 * or _equal_ to the buffer size programmed in TXPBS. For this 1923 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1924 */ 1925 val = (4096 - 1) / 64; 1926 wr32(E1000_I210_DTXMXPKTSZ, val); 1927 1928 /* Since FQTSS mode is enabled, apply any CBS configuration 1929 * previously set. If no previous CBS configuration has been 1930 * done, then the initial configuration is applied, which means 1931 * CBS is disabled. 1932 */ 1933 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1934 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1935 1936 for (i = 0; i < max_queue; i++) { 1937 igb_config_tx_modes(adapter, i); 1938 } 1939 } else { 1940 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1941 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1942 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1943 1944 val = rd32(E1000_I210_TQAVCTRL); 1945 /* According to Section 8.12.21, the other flags we've set when 1946 * enabling FQTSS are not relevant when disabling FQTSS so we 1947 * don't set they here. 1948 */ 1949 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1950 wr32(E1000_I210_TQAVCTRL, val); 1951 } 1952 1953 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1954 "enabled" : "disabled"); 1955 } 1956 1957 /** 1958 * igb_configure - configure the hardware for RX and TX 1959 * @adapter: private board structure 1960 **/ 1961 static void igb_configure(struct igb_adapter *adapter) 1962 { 1963 struct net_device *netdev = adapter->netdev; 1964 int i; 1965 1966 igb_get_hw_control(adapter); 1967 igb_set_rx_mode(netdev); 1968 igb_setup_tx_mode(adapter); 1969 1970 igb_restore_vlan(adapter); 1971 1972 igb_setup_tctl(adapter); 1973 igb_setup_mrqc(adapter); 1974 igb_setup_rctl(adapter); 1975 1976 igb_nfc_filter_restore(adapter); 1977 igb_configure_tx(adapter); 1978 igb_configure_rx(adapter); 1979 1980 igb_rx_fifo_flush_82575(&adapter->hw); 1981 1982 /* call igb_desc_unused which always leaves 1983 * at least 1 descriptor unused to make sure 1984 * next_to_use != next_to_clean 1985 */ 1986 for (i = 0; i < adapter->num_rx_queues; i++) { 1987 struct igb_ring *ring = adapter->rx_ring[i]; 1988 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1989 } 1990 } 1991 1992 /** 1993 * igb_power_up_link - Power up the phy/serdes link 1994 * @adapter: address of board private structure 1995 **/ 1996 void igb_power_up_link(struct igb_adapter *adapter) 1997 { 1998 igb_reset_phy(&adapter->hw); 1999 2000 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2001 igb_power_up_phy_copper(&adapter->hw); 2002 else 2003 igb_power_up_serdes_link_82575(&adapter->hw); 2004 2005 igb_setup_link(&adapter->hw); 2006 } 2007 2008 /** 2009 * igb_power_down_link - Power down the phy/serdes link 2010 * @adapter: address of board private structure 2011 */ 2012 static void igb_power_down_link(struct igb_adapter *adapter) 2013 { 2014 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2015 igb_power_down_phy_copper_82575(&adapter->hw); 2016 else 2017 igb_shutdown_serdes_link_82575(&adapter->hw); 2018 } 2019 2020 /** 2021 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2022 * @adapter: address of the board private structure 2023 **/ 2024 static void igb_check_swap_media(struct igb_adapter *adapter) 2025 { 2026 struct e1000_hw *hw = &adapter->hw; 2027 u32 ctrl_ext, connsw; 2028 bool swap_now = false; 2029 2030 ctrl_ext = rd32(E1000_CTRL_EXT); 2031 connsw = rd32(E1000_CONNSW); 2032 2033 /* need to live swap if current media is copper and we have fiber/serdes 2034 * to go to. 2035 */ 2036 2037 if ((hw->phy.media_type == e1000_media_type_copper) && 2038 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2039 swap_now = true; 2040 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2041 !(connsw & E1000_CONNSW_SERDESD)) { 2042 /* copper signal takes time to appear */ 2043 if (adapter->copper_tries < 4) { 2044 adapter->copper_tries++; 2045 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2046 wr32(E1000_CONNSW, connsw); 2047 return; 2048 } else { 2049 adapter->copper_tries = 0; 2050 if ((connsw & E1000_CONNSW_PHYSD) && 2051 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2052 swap_now = true; 2053 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2054 wr32(E1000_CONNSW, connsw); 2055 } 2056 } 2057 } 2058 2059 if (!swap_now) 2060 return; 2061 2062 switch (hw->phy.media_type) { 2063 case e1000_media_type_copper: 2064 netdev_info(adapter->netdev, 2065 "MAS: changing media to fiber/serdes\n"); 2066 ctrl_ext |= 2067 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2068 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2069 adapter->copper_tries = 0; 2070 break; 2071 case e1000_media_type_internal_serdes: 2072 case e1000_media_type_fiber: 2073 netdev_info(adapter->netdev, 2074 "MAS: changing media to copper\n"); 2075 ctrl_ext &= 2076 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2077 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2078 break; 2079 default: 2080 /* shouldn't get here during regular operation */ 2081 netdev_err(adapter->netdev, 2082 "AMS: Invalid media type found, returning\n"); 2083 break; 2084 } 2085 wr32(E1000_CTRL_EXT, ctrl_ext); 2086 } 2087 2088 /** 2089 * igb_up - Open the interface and prepare it to handle traffic 2090 * @adapter: board private structure 2091 **/ 2092 int igb_up(struct igb_adapter *adapter) 2093 { 2094 struct e1000_hw *hw = &adapter->hw; 2095 int i; 2096 2097 /* hardware has been reset, we need to reload some things */ 2098 igb_configure(adapter); 2099 2100 clear_bit(__IGB_DOWN, &adapter->state); 2101 2102 for (i = 0; i < adapter->num_q_vectors; i++) 2103 napi_enable(&(adapter->q_vector[i]->napi)); 2104 2105 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2106 igb_configure_msix(adapter); 2107 else 2108 igb_assign_vector(adapter->q_vector[0], 0); 2109 2110 /* Clear any pending interrupts. */ 2111 rd32(E1000_TSICR); 2112 rd32(E1000_ICR); 2113 igb_irq_enable(adapter); 2114 2115 /* notify VFs that reset has been completed */ 2116 if (adapter->vfs_allocated_count) { 2117 u32 reg_data = rd32(E1000_CTRL_EXT); 2118 2119 reg_data |= E1000_CTRL_EXT_PFRSTD; 2120 wr32(E1000_CTRL_EXT, reg_data); 2121 } 2122 2123 netif_tx_start_all_queues(adapter->netdev); 2124 2125 /* start the watchdog. */ 2126 hw->mac.get_link_status = 1; 2127 schedule_work(&adapter->watchdog_task); 2128 2129 if ((adapter->flags & IGB_FLAG_EEE) && 2130 (!hw->dev_spec._82575.eee_disable)) 2131 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2132 2133 return 0; 2134 } 2135 2136 void igb_down(struct igb_adapter *adapter) 2137 { 2138 struct net_device *netdev = adapter->netdev; 2139 struct e1000_hw *hw = &adapter->hw; 2140 u32 tctl, rctl; 2141 int i; 2142 2143 /* signal that we're down so the interrupt handler does not 2144 * reschedule our watchdog timer 2145 */ 2146 set_bit(__IGB_DOWN, &adapter->state); 2147 2148 /* disable receives in the hardware */ 2149 rctl = rd32(E1000_RCTL); 2150 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2151 /* flush and sleep below */ 2152 2153 igb_nfc_filter_exit(adapter); 2154 2155 netif_carrier_off(netdev); 2156 netif_tx_stop_all_queues(netdev); 2157 2158 /* disable transmits in the hardware */ 2159 tctl = rd32(E1000_TCTL); 2160 tctl &= ~E1000_TCTL_EN; 2161 wr32(E1000_TCTL, tctl); 2162 /* flush both disables and wait for them to finish */ 2163 wrfl(); 2164 usleep_range(10000, 11000); 2165 2166 igb_irq_disable(adapter); 2167 2168 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2169 2170 for (i = 0; i < adapter->num_q_vectors; i++) { 2171 if (adapter->q_vector[i]) { 2172 napi_synchronize(&adapter->q_vector[i]->napi); 2173 napi_disable(&adapter->q_vector[i]->napi); 2174 } 2175 } 2176 2177 del_timer_sync(&adapter->watchdog_timer); 2178 del_timer_sync(&adapter->phy_info_timer); 2179 2180 /* record the stats before reset*/ 2181 spin_lock(&adapter->stats64_lock); 2182 igb_update_stats(adapter); 2183 spin_unlock(&adapter->stats64_lock); 2184 2185 adapter->link_speed = 0; 2186 adapter->link_duplex = 0; 2187 2188 if (!pci_channel_offline(adapter->pdev)) 2189 igb_reset(adapter); 2190 2191 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2192 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2193 2194 igb_clean_all_tx_rings(adapter); 2195 igb_clean_all_rx_rings(adapter); 2196 #ifdef CONFIG_IGB_DCA 2197 2198 /* since we reset the hardware DCA settings were cleared */ 2199 igb_setup_dca(adapter); 2200 #endif 2201 } 2202 2203 void igb_reinit_locked(struct igb_adapter *adapter) 2204 { 2205 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2206 usleep_range(1000, 2000); 2207 igb_down(adapter); 2208 igb_up(adapter); 2209 clear_bit(__IGB_RESETTING, &adapter->state); 2210 } 2211 2212 /** igb_enable_mas - Media Autosense re-enable after swap 2213 * 2214 * @adapter: adapter struct 2215 **/ 2216 static void igb_enable_mas(struct igb_adapter *adapter) 2217 { 2218 struct e1000_hw *hw = &adapter->hw; 2219 u32 connsw = rd32(E1000_CONNSW); 2220 2221 /* configure for SerDes media detect */ 2222 if ((hw->phy.media_type == e1000_media_type_copper) && 2223 (!(connsw & E1000_CONNSW_SERDESD))) { 2224 connsw |= E1000_CONNSW_ENRGSRC; 2225 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2226 wr32(E1000_CONNSW, connsw); 2227 wrfl(); 2228 } 2229 } 2230 2231 #ifdef CONFIG_IGB_HWMON 2232 /** 2233 * igb_set_i2c_bb - Init I2C interface 2234 * @hw: pointer to hardware structure 2235 **/ 2236 static void igb_set_i2c_bb(struct e1000_hw *hw) 2237 { 2238 u32 ctrl_ext; 2239 s32 i2cctl; 2240 2241 ctrl_ext = rd32(E1000_CTRL_EXT); 2242 ctrl_ext |= E1000_CTRL_I2C_ENA; 2243 wr32(E1000_CTRL_EXT, ctrl_ext); 2244 wrfl(); 2245 2246 i2cctl = rd32(E1000_I2CPARAMS); 2247 i2cctl |= E1000_I2CBB_EN 2248 | E1000_I2C_CLK_OE_N 2249 | E1000_I2C_DATA_OE_N; 2250 wr32(E1000_I2CPARAMS, i2cctl); 2251 wrfl(); 2252 } 2253 #endif 2254 2255 void igb_reset(struct igb_adapter *adapter) 2256 { 2257 struct pci_dev *pdev = adapter->pdev; 2258 struct e1000_hw *hw = &adapter->hw; 2259 struct e1000_mac_info *mac = &hw->mac; 2260 struct e1000_fc_info *fc = &hw->fc; 2261 u32 pba, hwm; 2262 2263 /* Repartition Pba for greater than 9k mtu 2264 * To take effect CTRL.RST is required. 2265 */ 2266 switch (mac->type) { 2267 case e1000_i350: 2268 case e1000_i354: 2269 case e1000_82580: 2270 pba = rd32(E1000_RXPBS); 2271 pba = igb_rxpbs_adjust_82580(pba); 2272 break; 2273 case e1000_82576: 2274 pba = rd32(E1000_RXPBS); 2275 pba &= E1000_RXPBS_SIZE_MASK_82576; 2276 break; 2277 case e1000_82575: 2278 case e1000_i210: 2279 case e1000_i211: 2280 default: 2281 pba = E1000_PBA_34K; 2282 break; 2283 } 2284 2285 if (mac->type == e1000_82575) { 2286 u32 min_rx_space, min_tx_space, needed_tx_space; 2287 2288 /* write Rx PBA so that hardware can report correct Tx PBA */ 2289 wr32(E1000_PBA, pba); 2290 2291 /* To maintain wire speed transmits, the Tx FIFO should be 2292 * large enough to accommodate two full transmit packets, 2293 * rounded up to the next 1KB and expressed in KB. Likewise, 2294 * the Rx FIFO should be large enough to accommodate at least 2295 * one full receive packet and is similarly rounded up and 2296 * expressed in KB. 2297 */ 2298 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2299 2300 /* The Tx FIFO also stores 16 bytes of information about the Tx 2301 * but don't include Ethernet FCS because hardware appends it. 2302 * We only need to round down to the nearest 512 byte block 2303 * count since the value we care about is 2 frames, not 1. 2304 */ 2305 min_tx_space = adapter->max_frame_size; 2306 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2307 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2308 2309 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2310 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2311 2312 /* If current Tx allocation is less than the min Tx FIFO size, 2313 * and the min Tx FIFO size is less than the current Rx FIFO 2314 * allocation, take space away from current Rx allocation. 2315 */ 2316 if (needed_tx_space < pba) { 2317 pba -= needed_tx_space; 2318 2319 /* if short on Rx space, Rx wins and must trump Tx 2320 * adjustment 2321 */ 2322 if (pba < min_rx_space) 2323 pba = min_rx_space; 2324 } 2325 2326 /* adjust PBA for jumbo frames */ 2327 wr32(E1000_PBA, pba); 2328 } 2329 2330 /* flow control settings 2331 * The high water mark must be low enough to fit one full frame 2332 * after transmitting the pause frame. As such we must have enough 2333 * space to allow for us to complete our current transmit and then 2334 * receive the frame that is in progress from the link partner. 2335 * Set it to: 2336 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2337 */ 2338 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2339 2340 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2341 fc->low_water = fc->high_water - 16; 2342 fc->pause_time = 0xFFFF; 2343 fc->send_xon = 1; 2344 fc->current_mode = fc->requested_mode; 2345 2346 /* disable receive for all VFs and wait one second */ 2347 if (adapter->vfs_allocated_count) { 2348 int i; 2349 2350 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2351 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2352 2353 /* ping all the active vfs to let them know we are going down */ 2354 igb_ping_all_vfs(adapter); 2355 2356 /* disable transmits and receives */ 2357 wr32(E1000_VFRE, 0); 2358 wr32(E1000_VFTE, 0); 2359 } 2360 2361 /* Allow time for pending master requests to run */ 2362 hw->mac.ops.reset_hw(hw); 2363 wr32(E1000_WUC, 0); 2364 2365 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2366 /* need to resetup here after media swap */ 2367 adapter->ei.get_invariants(hw); 2368 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2369 } 2370 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2371 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2372 igb_enable_mas(adapter); 2373 } 2374 if (hw->mac.ops.init_hw(hw)) 2375 dev_err(&pdev->dev, "Hardware Error\n"); 2376 2377 /* RAR registers were cleared during init_hw, clear mac table */ 2378 igb_flush_mac_table(adapter); 2379 __dev_uc_unsync(adapter->netdev, NULL); 2380 2381 /* Recover default RAR entry */ 2382 igb_set_default_mac_filter(adapter); 2383 2384 /* Flow control settings reset on hardware reset, so guarantee flow 2385 * control is off when forcing speed. 2386 */ 2387 if (!hw->mac.autoneg) 2388 igb_force_mac_fc(hw); 2389 2390 igb_init_dmac(adapter, pba); 2391 #ifdef CONFIG_IGB_HWMON 2392 /* Re-initialize the thermal sensor on i350 devices. */ 2393 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2394 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2395 /* If present, re-initialize the external thermal sensor 2396 * interface. 2397 */ 2398 if (adapter->ets) 2399 igb_set_i2c_bb(hw); 2400 mac->ops.init_thermal_sensor_thresh(hw); 2401 } 2402 } 2403 #endif 2404 /* Re-establish EEE setting */ 2405 if (hw->phy.media_type == e1000_media_type_copper) { 2406 switch (mac->type) { 2407 case e1000_i350: 2408 case e1000_i210: 2409 case e1000_i211: 2410 igb_set_eee_i350(hw, true, true); 2411 break; 2412 case e1000_i354: 2413 igb_set_eee_i354(hw, true, true); 2414 break; 2415 default: 2416 break; 2417 } 2418 } 2419 if (!netif_running(adapter->netdev)) 2420 igb_power_down_link(adapter); 2421 2422 igb_update_mng_vlan(adapter); 2423 2424 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2425 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2426 2427 /* Re-enable PTP, where applicable. */ 2428 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2429 igb_ptp_reset(adapter); 2430 2431 igb_get_phy_info(hw); 2432 } 2433 2434 static netdev_features_t igb_fix_features(struct net_device *netdev, 2435 netdev_features_t features) 2436 { 2437 /* Since there is no support for separate Rx/Tx vlan accel 2438 * enable/disable make sure Tx flag is always in same state as Rx. 2439 */ 2440 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2441 features |= NETIF_F_HW_VLAN_CTAG_TX; 2442 else 2443 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2444 2445 return features; 2446 } 2447 2448 static int igb_set_features(struct net_device *netdev, 2449 netdev_features_t features) 2450 { 2451 netdev_features_t changed = netdev->features ^ features; 2452 struct igb_adapter *adapter = netdev_priv(netdev); 2453 2454 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2455 igb_vlan_mode(netdev, features); 2456 2457 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2458 return 0; 2459 2460 if (!(features & NETIF_F_NTUPLE)) { 2461 struct hlist_node *node2; 2462 struct igb_nfc_filter *rule; 2463 2464 spin_lock(&adapter->nfc_lock); 2465 hlist_for_each_entry_safe(rule, node2, 2466 &adapter->nfc_filter_list, nfc_node) { 2467 igb_erase_filter(adapter, rule); 2468 hlist_del(&rule->nfc_node); 2469 kfree(rule); 2470 } 2471 spin_unlock(&adapter->nfc_lock); 2472 adapter->nfc_filter_count = 0; 2473 } 2474 2475 netdev->features = features; 2476 2477 if (netif_running(netdev)) 2478 igb_reinit_locked(adapter); 2479 else 2480 igb_reset(adapter); 2481 2482 return 1; 2483 } 2484 2485 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2486 struct net_device *dev, 2487 const unsigned char *addr, u16 vid, 2488 u16 flags, 2489 struct netlink_ext_ack *extack) 2490 { 2491 /* guarantee we can provide a unique filter for the unicast address */ 2492 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2493 struct igb_adapter *adapter = netdev_priv(dev); 2494 int vfn = adapter->vfs_allocated_count; 2495 2496 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2497 return -ENOMEM; 2498 } 2499 2500 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2501 } 2502 2503 #define IGB_MAX_MAC_HDR_LEN 127 2504 #define IGB_MAX_NETWORK_HDR_LEN 511 2505 2506 static netdev_features_t 2507 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2508 netdev_features_t features) 2509 { 2510 unsigned int network_hdr_len, mac_hdr_len; 2511 2512 /* Make certain the headers can be described by a context descriptor */ 2513 mac_hdr_len = skb_network_offset(skb); 2514 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2515 return features & ~(NETIF_F_HW_CSUM | 2516 NETIF_F_SCTP_CRC | 2517 NETIF_F_GSO_UDP_L4 | 2518 NETIF_F_HW_VLAN_CTAG_TX | 2519 NETIF_F_TSO | 2520 NETIF_F_TSO6); 2521 2522 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2523 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2524 return features & ~(NETIF_F_HW_CSUM | 2525 NETIF_F_SCTP_CRC | 2526 NETIF_F_GSO_UDP_L4 | 2527 NETIF_F_TSO | 2528 NETIF_F_TSO6); 2529 2530 /* We can only support IPV4 TSO in tunnels if we can mangle the 2531 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2532 */ 2533 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2534 features &= ~NETIF_F_TSO; 2535 2536 return features; 2537 } 2538 2539 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2540 { 2541 if (!is_fqtss_enabled(adapter)) { 2542 enable_fqtss(adapter, true); 2543 return; 2544 } 2545 2546 igb_config_tx_modes(adapter, queue); 2547 2548 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2549 enable_fqtss(adapter, false); 2550 } 2551 2552 static int igb_offload_cbs(struct igb_adapter *adapter, 2553 struct tc_cbs_qopt_offload *qopt) 2554 { 2555 struct e1000_hw *hw = &adapter->hw; 2556 int err; 2557 2558 /* CBS offloading is only supported by i210 controller. */ 2559 if (hw->mac.type != e1000_i210) 2560 return -EOPNOTSUPP; 2561 2562 /* CBS offloading is only supported by queue 0 and queue 1. */ 2563 if (qopt->queue < 0 || qopt->queue > 1) 2564 return -EINVAL; 2565 2566 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2567 qopt->idleslope, qopt->sendslope, 2568 qopt->hicredit, qopt->locredit); 2569 if (err) 2570 return err; 2571 2572 igb_offload_apply(adapter, qopt->queue); 2573 2574 return 0; 2575 } 2576 2577 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2578 #define VLAN_PRIO_FULL_MASK (0x07) 2579 2580 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2581 struct flow_cls_offload *f, 2582 int traffic_class, 2583 struct igb_nfc_filter *input) 2584 { 2585 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2586 struct flow_dissector *dissector = rule->match.dissector; 2587 struct netlink_ext_ack *extack = f->common.extack; 2588 2589 if (dissector->used_keys & 2590 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2591 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2592 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2593 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2594 NL_SET_ERR_MSG_MOD(extack, 2595 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (flow_rule_match_has_control_flags(rule, extack)) 2600 return -EOPNOTSUPP; 2601 2602 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2603 struct flow_match_eth_addrs match; 2604 2605 flow_rule_match_eth_addrs(rule, &match); 2606 if (!is_zero_ether_addr(match.mask->dst)) { 2607 if (!is_broadcast_ether_addr(match.mask->dst)) { 2608 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2609 return -EINVAL; 2610 } 2611 2612 input->filter.match_flags |= 2613 IGB_FILTER_FLAG_DST_MAC_ADDR; 2614 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2615 } 2616 2617 if (!is_zero_ether_addr(match.mask->src)) { 2618 if (!is_broadcast_ether_addr(match.mask->src)) { 2619 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2620 return -EINVAL; 2621 } 2622 2623 input->filter.match_flags |= 2624 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2625 ether_addr_copy(input->filter.src_addr, match.key->src); 2626 } 2627 } 2628 2629 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2630 struct flow_match_basic match; 2631 2632 flow_rule_match_basic(rule, &match); 2633 if (match.mask->n_proto) { 2634 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2635 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2636 return -EINVAL; 2637 } 2638 2639 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2640 input->filter.etype = match.key->n_proto; 2641 } 2642 } 2643 2644 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2645 struct flow_match_vlan match; 2646 2647 flow_rule_match_vlan(rule, &match); 2648 if (match.mask->vlan_priority) { 2649 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2650 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2651 return -EINVAL; 2652 } 2653 2654 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2655 input->filter.vlan_tci = 2656 (__force __be16)match.key->vlan_priority; 2657 } 2658 } 2659 2660 input->action = traffic_class; 2661 input->cookie = f->cookie; 2662 2663 return 0; 2664 } 2665 2666 static int igb_configure_clsflower(struct igb_adapter *adapter, 2667 struct flow_cls_offload *cls_flower) 2668 { 2669 struct netlink_ext_ack *extack = cls_flower->common.extack; 2670 struct igb_nfc_filter *filter, *f; 2671 int err, tc; 2672 2673 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2674 if (tc < 0) { 2675 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2676 return -EINVAL; 2677 } 2678 2679 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2680 if (!filter) 2681 return -ENOMEM; 2682 2683 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2684 if (err < 0) 2685 goto err_parse; 2686 2687 spin_lock(&adapter->nfc_lock); 2688 2689 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2690 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2691 err = -EEXIST; 2692 NL_SET_ERR_MSG_MOD(extack, 2693 "This filter is already set in ethtool"); 2694 goto err_locked; 2695 } 2696 } 2697 2698 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2699 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2700 err = -EEXIST; 2701 NL_SET_ERR_MSG_MOD(extack, 2702 "This filter is already set in cls_flower"); 2703 goto err_locked; 2704 } 2705 } 2706 2707 err = igb_add_filter(adapter, filter); 2708 if (err < 0) { 2709 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2710 goto err_locked; 2711 } 2712 2713 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2714 2715 spin_unlock(&adapter->nfc_lock); 2716 2717 return 0; 2718 2719 err_locked: 2720 spin_unlock(&adapter->nfc_lock); 2721 2722 err_parse: 2723 kfree(filter); 2724 2725 return err; 2726 } 2727 2728 static int igb_delete_clsflower(struct igb_adapter *adapter, 2729 struct flow_cls_offload *cls_flower) 2730 { 2731 struct igb_nfc_filter *filter; 2732 int err; 2733 2734 spin_lock(&adapter->nfc_lock); 2735 2736 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2737 if (filter->cookie == cls_flower->cookie) 2738 break; 2739 2740 if (!filter) { 2741 err = -ENOENT; 2742 goto out; 2743 } 2744 2745 err = igb_erase_filter(adapter, filter); 2746 if (err < 0) 2747 goto out; 2748 2749 hlist_del(&filter->nfc_node); 2750 kfree(filter); 2751 2752 out: 2753 spin_unlock(&adapter->nfc_lock); 2754 2755 return err; 2756 } 2757 2758 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2759 struct flow_cls_offload *cls_flower) 2760 { 2761 switch (cls_flower->command) { 2762 case FLOW_CLS_REPLACE: 2763 return igb_configure_clsflower(adapter, cls_flower); 2764 case FLOW_CLS_DESTROY: 2765 return igb_delete_clsflower(adapter, cls_flower); 2766 case FLOW_CLS_STATS: 2767 return -EOPNOTSUPP; 2768 default: 2769 return -EOPNOTSUPP; 2770 } 2771 } 2772 2773 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2774 void *cb_priv) 2775 { 2776 struct igb_adapter *adapter = cb_priv; 2777 2778 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2779 return -EOPNOTSUPP; 2780 2781 switch (type) { 2782 case TC_SETUP_CLSFLOWER: 2783 return igb_setup_tc_cls_flower(adapter, type_data); 2784 2785 default: 2786 return -EOPNOTSUPP; 2787 } 2788 } 2789 2790 static int igb_offload_txtime(struct igb_adapter *adapter, 2791 struct tc_etf_qopt_offload *qopt) 2792 { 2793 struct e1000_hw *hw = &adapter->hw; 2794 int err; 2795 2796 /* Launchtime offloading is only supported by i210 controller. */ 2797 if (hw->mac.type != e1000_i210) 2798 return -EOPNOTSUPP; 2799 2800 /* Launchtime offloading is only supported by queues 0 and 1. */ 2801 if (qopt->queue < 0 || qopt->queue > 1) 2802 return -EINVAL; 2803 2804 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2805 if (err) 2806 return err; 2807 2808 igb_offload_apply(adapter, qopt->queue); 2809 2810 return 0; 2811 } 2812 2813 static int igb_tc_query_caps(struct igb_adapter *adapter, 2814 struct tc_query_caps_base *base) 2815 { 2816 switch (base->type) { 2817 case TC_SETUP_QDISC_TAPRIO: { 2818 struct tc_taprio_caps *caps = base->caps; 2819 2820 caps->broken_mqprio = true; 2821 2822 return 0; 2823 } 2824 default: 2825 return -EOPNOTSUPP; 2826 } 2827 } 2828 2829 static LIST_HEAD(igb_block_cb_list); 2830 2831 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2832 void *type_data) 2833 { 2834 struct igb_adapter *adapter = netdev_priv(dev); 2835 2836 switch (type) { 2837 case TC_QUERY_CAPS: 2838 return igb_tc_query_caps(adapter, type_data); 2839 case TC_SETUP_QDISC_CBS: 2840 return igb_offload_cbs(adapter, type_data); 2841 case TC_SETUP_BLOCK: 2842 return flow_block_cb_setup_simple(type_data, 2843 &igb_block_cb_list, 2844 igb_setup_tc_block_cb, 2845 adapter, adapter, true); 2846 2847 case TC_SETUP_QDISC_ETF: 2848 return igb_offload_txtime(adapter, type_data); 2849 2850 default: 2851 return -EOPNOTSUPP; 2852 } 2853 } 2854 2855 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2856 { 2857 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2858 struct igb_adapter *adapter = netdev_priv(dev); 2859 struct bpf_prog *prog = bpf->prog, *old_prog; 2860 bool running = netif_running(dev); 2861 bool need_reset; 2862 2863 /* verify igb ring attributes are sufficient for XDP */ 2864 for (i = 0; i < adapter->num_rx_queues; i++) { 2865 struct igb_ring *ring = adapter->rx_ring[i]; 2866 2867 if (frame_size > igb_rx_bufsz(ring)) { 2868 NL_SET_ERR_MSG_MOD(bpf->extack, 2869 "The RX buffer size is too small for the frame size"); 2870 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2871 igb_rx_bufsz(ring), frame_size); 2872 return -EINVAL; 2873 } 2874 } 2875 2876 old_prog = xchg(&adapter->xdp_prog, prog); 2877 need_reset = (!!prog != !!old_prog); 2878 2879 /* device is up and bpf is added/removed, must setup the RX queues */ 2880 if (need_reset && running) { 2881 igb_close(dev); 2882 } else { 2883 for (i = 0; i < adapter->num_rx_queues; i++) 2884 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2885 adapter->xdp_prog); 2886 } 2887 2888 if (old_prog) 2889 bpf_prog_put(old_prog); 2890 2891 /* bpf is just replaced, RXQ and MTU are already setup */ 2892 if (!need_reset) { 2893 return 0; 2894 } else { 2895 if (prog) 2896 xdp_features_set_redirect_target(dev, true); 2897 else 2898 xdp_features_clear_redirect_target(dev); 2899 } 2900 2901 if (running) 2902 igb_open(dev); 2903 2904 return 0; 2905 } 2906 2907 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2908 { 2909 switch (xdp->command) { 2910 case XDP_SETUP_PROG: 2911 return igb_xdp_setup(dev, xdp); 2912 default: 2913 return -EINVAL; 2914 } 2915 } 2916 2917 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2918 { 2919 /* Force memory writes to complete before letting h/w know there 2920 * are new descriptors to fetch. 2921 */ 2922 wmb(); 2923 writel(ring->next_to_use, ring->tail); 2924 } 2925 2926 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2927 { 2928 unsigned int r_idx = smp_processor_id(); 2929 2930 if (r_idx >= adapter->num_tx_queues) 2931 r_idx = r_idx % adapter->num_tx_queues; 2932 2933 return adapter->tx_ring[r_idx]; 2934 } 2935 2936 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2937 { 2938 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2939 int cpu = smp_processor_id(); 2940 struct igb_ring *tx_ring; 2941 struct netdev_queue *nq; 2942 u32 ret; 2943 2944 if (unlikely(!xdpf)) 2945 return IGB_XDP_CONSUMED; 2946 2947 /* During program transitions its possible adapter->xdp_prog is assigned 2948 * but ring has not been configured yet. In this case simply abort xmit. 2949 */ 2950 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2951 if (unlikely(!tx_ring)) 2952 return IGB_XDP_CONSUMED; 2953 2954 nq = txring_txq(tx_ring); 2955 __netif_tx_lock(nq, cpu); 2956 /* Avoid transmit queue timeout since we share it with the slow path */ 2957 txq_trans_cond_update(nq); 2958 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2959 __netif_tx_unlock(nq); 2960 2961 return ret; 2962 } 2963 2964 static int igb_xdp_xmit(struct net_device *dev, int n, 2965 struct xdp_frame **frames, u32 flags) 2966 { 2967 struct igb_adapter *adapter = netdev_priv(dev); 2968 int cpu = smp_processor_id(); 2969 struct igb_ring *tx_ring; 2970 struct netdev_queue *nq; 2971 int nxmit = 0; 2972 int i; 2973 2974 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2975 return -ENETDOWN; 2976 2977 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2978 return -EINVAL; 2979 2980 /* During program transitions its possible adapter->xdp_prog is assigned 2981 * but ring has not been configured yet. In this case simply abort xmit. 2982 */ 2983 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2984 if (unlikely(!tx_ring)) 2985 return -ENXIO; 2986 2987 nq = txring_txq(tx_ring); 2988 __netif_tx_lock(nq, cpu); 2989 2990 /* Avoid transmit queue timeout since we share it with the slow path */ 2991 txq_trans_cond_update(nq); 2992 2993 for (i = 0; i < n; i++) { 2994 struct xdp_frame *xdpf = frames[i]; 2995 int err; 2996 2997 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2998 if (err != IGB_XDP_TX) 2999 break; 3000 nxmit++; 3001 } 3002 3003 __netif_tx_unlock(nq); 3004 3005 if (unlikely(flags & XDP_XMIT_FLUSH)) 3006 igb_xdp_ring_update_tail(tx_ring); 3007 3008 return nxmit; 3009 } 3010 3011 static const struct net_device_ops igb_netdev_ops = { 3012 .ndo_open = igb_open, 3013 .ndo_stop = igb_close, 3014 .ndo_start_xmit = igb_xmit_frame, 3015 .ndo_get_stats64 = igb_get_stats64, 3016 .ndo_set_rx_mode = igb_set_rx_mode, 3017 .ndo_set_mac_address = igb_set_mac, 3018 .ndo_change_mtu = igb_change_mtu, 3019 .ndo_eth_ioctl = igb_ioctl, 3020 .ndo_tx_timeout = igb_tx_timeout, 3021 .ndo_validate_addr = eth_validate_addr, 3022 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3023 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3024 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3025 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3026 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3027 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3028 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3029 .ndo_get_vf_config = igb_ndo_get_vf_config, 3030 .ndo_fix_features = igb_fix_features, 3031 .ndo_set_features = igb_set_features, 3032 .ndo_fdb_add = igb_ndo_fdb_add, 3033 .ndo_features_check = igb_features_check, 3034 .ndo_setup_tc = igb_setup_tc, 3035 .ndo_bpf = igb_xdp, 3036 .ndo_xdp_xmit = igb_xdp_xmit, 3037 }; 3038 3039 /** 3040 * igb_set_fw_version - Configure version string for ethtool 3041 * @adapter: adapter struct 3042 **/ 3043 void igb_set_fw_version(struct igb_adapter *adapter) 3044 { 3045 struct e1000_hw *hw = &adapter->hw; 3046 struct e1000_fw_version fw; 3047 3048 igb_get_fw_version(hw, &fw); 3049 3050 switch (hw->mac.type) { 3051 case e1000_i210: 3052 case e1000_i211: 3053 if (!(igb_get_flash_presence_i210(hw))) { 3054 snprintf(adapter->fw_version, 3055 sizeof(adapter->fw_version), 3056 "%2d.%2d-%d", 3057 fw.invm_major, fw.invm_minor, 3058 fw.invm_img_type); 3059 break; 3060 } 3061 fallthrough; 3062 default: 3063 /* if option rom is valid, display its version too */ 3064 if (fw.or_valid) { 3065 snprintf(adapter->fw_version, 3066 sizeof(adapter->fw_version), 3067 "%d.%d, 0x%08x, %d.%d.%d", 3068 fw.eep_major, fw.eep_minor, fw.etrack_id, 3069 fw.or_major, fw.or_build, fw.or_patch); 3070 /* no option rom */ 3071 } else if (fw.etrack_id != 0X0000) { 3072 snprintf(adapter->fw_version, 3073 sizeof(adapter->fw_version), 3074 "%d.%d, 0x%08x", 3075 fw.eep_major, fw.eep_minor, fw.etrack_id); 3076 } else { 3077 snprintf(adapter->fw_version, 3078 sizeof(adapter->fw_version), 3079 "%d.%d.%d", 3080 fw.eep_major, fw.eep_minor, fw.eep_build); 3081 } 3082 break; 3083 } 3084 } 3085 3086 /** 3087 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3088 * 3089 * @adapter: adapter struct 3090 **/ 3091 static void igb_init_mas(struct igb_adapter *adapter) 3092 { 3093 struct e1000_hw *hw = &adapter->hw; 3094 u16 eeprom_data; 3095 3096 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3097 switch (hw->bus.func) { 3098 case E1000_FUNC_0: 3099 if (eeprom_data & IGB_MAS_ENABLE_0) { 3100 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3101 netdev_info(adapter->netdev, 3102 "MAS: Enabling Media Autosense for port %d\n", 3103 hw->bus.func); 3104 } 3105 break; 3106 case E1000_FUNC_1: 3107 if (eeprom_data & IGB_MAS_ENABLE_1) { 3108 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3109 netdev_info(adapter->netdev, 3110 "MAS: Enabling Media Autosense for port %d\n", 3111 hw->bus.func); 3112 } 3113 break; 3114 case E1000_FUNC_2: 3115 if (eeprom_data & IGB_MAS_ENABLE_2) { 3116 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3117 netdev_info(adapter->netdev, 3118 "MAS: Enabling Media Autosense for port %d\n", 3119 hw->bus.func); 3120 } 3121 break; 3122 case E1000_FUNC_3: 3123 if (eeprom_data & IGB_MAS_ENABLE_3) { 3124 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3125 netdev_info(adapter->netdev, 3126 "MAS: Enabling Media Autosense for port %d\n", 3127 hw->bus.func); 3128 } 3129 break; 3130 default: 3131 /* Shouldn't get here */ 3132 netdev_err(adapter->netdev, 3133 "MAS: Invalid port configuration, returning\n"); 3134 break; 3135 } 3136 } 3137 3138 /** 3139 * igb_init_i2c - Init I2C interface 3140 * @adapter: pointer to adapter structure 3141 **/ 3142 static s32 igb_init_i2c(struct igb_adapter *adapter) 3143 { 3144 s32 status = 0; 3145 3146 /* I2C interface supported on i350 devices */ 3147 if (adapter->hw.mac.type != e1000_i350) 3148 return 0; 3149 3150 /* Initialize the i2c bus which is controlled by the registers. 3151 * This bus will use the i2c_algo_bit structure that implements 3152 * the protocol through toggling of the 4 bits in the register. 3153 */ 3154 adapter->i2c_adap.owner = THIS_MODULE; 3155 adapter->i2c_algo = igb_i2c_algo; 3156 adapter->i2c_algo.data = adapter; 3157 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3158 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3159 strscpy(adapter->i2c_adap.name, "igb BB", 3160 sizeof(adapter->i2c_adap.name)); 3161 status = i2c_bit_add_bus(&adapter->i2c_adap); 3162 return status; 3163 } 3164 3165 /** 3166 * igb_probe - Device Initialization Routine 3167 * @pdev: PCI device information struct 3168 * @ent: entry in igb_pci_tbl 3169 * 3170 * Returns 0 on success, negative on failure 3171 * 3172 * igb_probe initializes an adapter identified by a pci_dev structure. 3173 * The OS initialization, configuring of the adapter private structure, 3174 * and a hardware reset occur. 3175 **/ 3176 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3177 { 3178 struct net_device *netdev; 3179 struct igb_adapter *adapter; 3180 struct e1000_hw *hw; 3181 u16 eeprom_data = 0; 3182 s32 ret_val; 3183 static int global_quad_port_a; /* global quad port a indication */ 3184 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3185 u8 part_str[E1000_PBANUM_LENGTH]; 3186 int err; 3187 3188 /* Catch broken hardware that put the wrong VF device ID in 3189 * the PCIe SR-IOV capability. 3190 */ 3191 if (pdev->is_virtfn) { 3192 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3193 pci_name(pdev), pdev->vendor, pdev->device); 3194 return -EINVAL; 3195 } 3196 3197 err = pci_enable_device_mem(pdev); 3198 if (err) 3199 return err; 3200 3201 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3202 if (err) { 3203 dev_err(&pdev->dev, 3204 "No usable DMA configuration, aborting\n"); 3205 goto err_dma; 3206 } 3207 3208 err = pci_request_mem_regions(pdev, igb_driver_name); 3209 if (err) 3210 goto err_pci_reg; 3211 3212 pci_set_master(pdev); 3213 pci_save_state(pdev); 3214 3215 err = -ENOMEM; 3216 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3217 IGB_MAX_TX_QUEUES); 3218 if (!netdev) 3219 goto err_alloc_etherdev; 3220 3221 SET_NETDEV_DEV(netdev, &pdev->dev); 3222 3223 pci_set_drvdata(pdev, netdev); 3224 adapter = netdev_priv(netdev); 3225 adapter->netdev = netdev; 3226 adapter->pdev = pdev; 3227 hw = &adapter->hw; 3228 hw->back = adapter; 3229 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3230 3231 err = -EIO; 3232 adapter->io_addr = pci_iomap(pdev, 0, 0); 3233 if (!adapter->io_addr) 3234 goto err_ioremap; 3235 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3236 hw->hw_addr = adapter->io_addr; 3237 3238 netdev->netdev_ops = &igb_netdev_ops; 3239 igb_set_ethtool_ops(netdev); 3240 netdev->watchdog_timeo = 5 * HZ; 3241 3242 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3243 3244 netdev->mem_start = pci_resource_start(pdev, 0); 3245 netdev->mem_end = pci_resource_end(pdev, 0); 3246 3247 /* PCI config space info */ 3248 hw->vendor_id = pdev->vendor; 3249 hw->device_id = pdev->device; 3250 hw->revision_id = pdev->revision; 3251 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3252 hw->subsystem_device_id = pdev->subsystem_device; 3253 3254 /* Copy the default MAC, PHY and NVM function pointers */ 3255 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3256 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3257 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3258 /* Initialize skew-specific constants */ 3259 err = ei->get_invariants(hw); 3260 if (err) 3261 goto err_sw_init; 3262 3263 /* setup the private structure */ 3264 err = igb_sw_init(adapter); 3265 if (err) 3266 goto err_sw_init; 3267 3268 igb_get_bus_info_pcie(hw); 3269 3270 hw->phy.autoneg_wait_to_complete = false; 3271 3272 /* Copper options */ 3273 if (hw->phy.media_type == e1000_media_type_copper) { 3274 hw->phy.mdix = AUTO_ALL_MODES; 3275 hw->phy.disable_polarity_correction = false; 3276 hw->phy.ms_type = e1000_ms_hw_default; 3277 } 3278 3279 if (igb_check_reset_block(hw)) 3280 dev_info(&pdev->dev, 3281 "PHY reset is blocked due to SOL/IDER session.\n"); 3282 3283 /* features is initialized to 0 in allocation, it might have bits 3284 * set by igb_sw_init so we should use an or instead of an 3285 * assignment. 3286 */ 3287 netdev->features |= NETIF_F_SG | 3288 NETIF_F_TSO | 3289 NETIF_F_TSO6 | 3290 NETIF_F_RXHASH | 3291 NETIF_F_RXCSUM | 3292 NETIF_F_HW_CSUM; 3293 3294 if (hw->mac.type >= e1000_82576) 3295 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3296 3297 if (hw->mac.type >= e1000_i350) 3298 netdev->features |= NETIF_F_HW_TC; 3299 3300 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3301 NETIF_F_GSO_GRE_CSUM | \ 3302 NETIF_F_GSO_IPXIP4 | \ 3303 NETIF_F_GSO_IPXIP6 | \ 3304 NETIF_F_GSO_UDP_TUNNEL | \ 3305 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3306 3307 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3308 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3309 3310 /* copy netdev features into list of user selectable features */ 3311 netdev->hw_features |= netdev->features | 3312 NETIF_F_HW_VLAN_CTAG_RX | 3313 NETIF_F_HW_VLAN_CTAG_TX | 3314 NETIF_F_RXALL; 3315 3316 if (hw->mac.type >= e1000_i350) 3317 netdev->hw_features |= NETIF_F_NTUPLE; 3318 3319 netdev->features |= NETIF_F_HIGHDMA; 3320 3321 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3322 netdev->mpls_features |= NETIF_F_HW_CSUM; 3323 netdev->hw_enc_features |= netdev->vlan_features; 3324 3325 /* set this bit last since it cannot be part of vlan_features */ 3326 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3327 NETIF_F_HW_VLAN_CTAG_RX | 3328 NETIF_F_HW_VLAN_CTAG_TX; 3329 3330 netdev->priv_flags |= IFF_SUPP_NOFCS; 3331 3332 netdev->priv_flags |= IFF_UNICAST_FLT; 3333 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3334 3335 /* MTU range: 68 - 9216 */ 3336 netdev->min_mtu = ETH_MIN_MTU; 3337 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3338 3339 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3340 3341 /* before reading the NVM, reset the controller to put the device in a 3342 * known good starting state 3343 */ 3344 hw->mac.ops.reset_hw(hw); 3345 3346 /* make sure the NVM is good , i211/i210 parts can have special NVM 3347 * that doesn't contain a checksum 3348 */ 3349 switch (hw->mac.type) { 3350 case e1000_i210: 3351 case e1000_i211: 3352 if (igb_get_flash_presence_i210(hw)) { 3353 if (hw->nvm.ops.validate(hw) < 0) { 3354 dev_err(&pdev->dev, 3355 "The NVM Checksum Is Not Valid\n"); 3356 err = -EIO; 3357 goto err_eeprom; 3358 } 3359 } 3360 break; 3361 default: 3362 if (hw->nvm.ops.validate(hw) < 0) { 3363 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3364 err = -EIO; 3365 goto err_eeprom; 3366 } 3367 break; 3368 } 3369 3370 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3371 /* copy the MAC address out of the NVM */ 3372 if (hw->mac.ops.read_mac_addr(hw)) 3373 dev_err(&pdev->dev, "NVM Read Error\n"); 3374 } 3375 3376 eth_hw_addr_set(netdev, hw->mac.addr); 3377 3378 if (!is_valid_ether_addr(netdev->dev_addr)) { 3379 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3380 err = -EIO; 3381 goto err_eeprom; 3382 } 3383 3384 igb_set_default_mac_filter(adapter); 3385 3386 /* get firmware version for ethtool -i */ 3387 igb_set_fw_version(adapter); 3388 3389 /* configure RXPBSIZE and TXPBSIZE */ 3390 if (hw->mac.type == e1000_i210) { 3391 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3392 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3393 } 3394 3395 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3396 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3397 3398 INIT_WORK(&adapter->reset_task, igb_reset_task); 3399 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3400 3401 /* Initialize link properties that are user-changeable */ 3402 adapter->fc_autoneg = true; 3403 hw->mac.autoneg = true; 3404 hw->phy.autoneg_advertised = 0x2f; 3405 3406 hw->fc.requested_mode = e1000_fc_default; 3407 hw->fc.current_mode = e1000_fc_default; 3408 3409 igb_validate_mdi_setting(hw); 3410 3411 /* By default, support wake on port A */ 3412 if (hw->bus.func == 0) 3413 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3414 3415 /* Check the NVM for wake support on non-port A ports */ 3416 if (hw->mac.type >= e1000_82580) 3417 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3418 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3419 &eeprom_data); 3420 else if (hw->bus.func == 1) 3421 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3422 3423 if (eeprom_data & IGB_EEPROM_APME) 3424 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3425 3426 /* now that we have the eeprom settings, apply the special cases where 3427 * the eeprom may be wrong or the board simply won't support wake on 3428 * lan on a particular port 3429 */ 3430 switch (pdev->device) { 3431 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3432 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3433 break; 3434 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3435 case E1000_DEV_ID_82576_FIBER: 3436 case E1000_DEV_ID_82576_SERDES: 3437 /* Wake events only supported on port A for dual fiber 3438 * regardless of eeprom setting 3439 */ 3440 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3441 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3442 break; 3443 case E1000_DEV_ID_82576_QUAD_COPPER: 3444 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3445 /* if quad port adapter, disable WoL on all but port A */ 3446 if (global_quad_port_a != 0) 3447 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3448 else 3449 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3450 /* Reset for multiple quad port adapters */ 3451 if (++global_quad_port_a == 4) 3452 global_quad_port_a = 0; 3453 break; 3454 default: 3455 /* If the device can't wake, don't set software support */ 3456 if (!device_can_wakeup(&adapter->pdev->dev)) 3457 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3458 } 3459 3460 /* initialize the wol settings based on the eeprom settings */ 3461 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3462 adapter->wol |= E1000_WUFC_MAG; 3463 3464 /* Some vendors want WoL disabled by default, but still supported */ 3465 if ((hw->mac.type == e1000_i350) && 3466 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3468 adapter->wol = 0; 3469 } 3470 3471 /* Some vendors want the ability to Use the EEPROM setting as 3472 * enable/disable only, and not for capability 3473 */ 3474 if (((hw->mac.type == e1000_i350) || 3475 (hw->mac.type == e1000_i354)) && 3476 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3477 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3478 adapter->wol = 0; 3479 } 3480 if (hw->mac.type == e1000_i350) { 3481 if (((pdev->subsystem_device == 0x5001) || 3482 (pdev->subsystem_device == 0x5002)) && 3483 (hw->bus.func == 0)) { 3484 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3485 adapter->wol = 0; 3486 } 3487 if (pdev->subsystem_device == 0x1F52) 3488 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3489 } 3490 3491 device_set_wakeup_enable(&adapter->pdev->dev, 3492 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3493 3494 /* reset the hardware with the new settings */ 3495 igb_reset(adapter); 3496 3497 /* Init the I2C interface */ 3498 err = igb_init_i2c(adapter); 3499 if (err) { 3500 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3501 goto err_eeprom; 3502 } 3503 3504 /* let the f/w know that the h/w is now under the control of the 3505 * driver. 3506 */ 3507 igb_get_hw_control(adapter); 3508 3509 strcpy(netdev->name, "eth%d"); 3510 err = register_netdev(netdev); 3511 if (err) 3512 goto err_register; 3513 3514 /* carrier off reporting is important to ethtool even BEFORE open */ 3515 netif_carrier_off(netdev); 3516 3517 #ifdef CONFIG_IGB_DCA 3518 if (dca_add_requester(&pdev->dev) == 0) { 3519 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3520 dev_info(&pdev->dev, "DCA enabled\n"); 3521 igb_setup_dca(adapter); 3522 } 3523 3524 #endif 3525 #ifdef CONFIG_IGB_HWMON 3526 /* Initialize the thermal sensor on i350 devices. */ 3527 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3528 u16 ets_word; 3529 3530 /* Read the NVM to determine if this i350 device supports an 3531 * external thermal sensor. 3532 */ 3533 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3534 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3535 adapter->ets = true; 3536 else 3537 adapter->ets = false; 3538 /* Only enable I2C bit banging if an external thermal 3539 * sensor is supported. 3540 */ 3541 if (adapter->ets) 3542 igb_set_i2c_bb(hw); 3543 hw->mac.ops.init_thermal_sensor_thresh(hw); 3544 if (igb_sysfs_init(adapter)) 3545 dev_err(&pdev->dev, 3546 "failed to allocate sysfs resources\n"); 3547 } else { 3548 adapter->ets = false; 3549 } 3550 #endif 3551 /* Check if Media Autosense is enabled */ 3552 adapter->ei = *ei; 3553 if (hw->dev_spec._82575.mas_capable) 3554 igb_init_mas(adapter); 3555 3556 /* do hw tstamp init after resetting */ 3557 igb_ptp_init(adapter); 3558 3559 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3560 /* print bus type/speed/width info, not applicable to i354 */ 3561 if (hw->mac.type != e1000_i354) { 3562 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3563 netdev->name, 3564 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3565 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3566 "unknown"), 3567 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3568 "Width x4" : 3569 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3570 "Width x2" : 3571 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3572 "Width x1" : "unknown"), netdev->dev_addr); 3573 } 3574 3575 if ((hw->mac.type == e1000_82576 && 3576 rd32(E1000_EECD) & E1000_EECD_PRES) || 3577 (hw->mac.type >= e1000_i210 || 3578 igb_get_flash_presence_i210(hw))) { 3579 ret_val = igb_read_part_string(hw, part_str, 3580 E1000_PBANUM_LENGTH); 3581 } else { 3582 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3583 } 3584 3585 if (ret_val) 3586 strcpy(part_str, "Unknown"); 3587 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3588 dev_info(&pdev->dev, 3589 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3590 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3591 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3592 adapter->num_rx_queues, adapter->num_tx_queues); 3593 if (hw->phy.media_type == e1000_media_type_copper) { 3594 switch (hw->mac.type) { 3595 case e1000_i350: 3596 case e1000_i210: 3597 case e1000_i211: 3598 /* Enable EEE for internal copper PHY devices */ 3599 err = igb_set_eee_i350(hw, true, true); 3600 if ((!err) && 3601 (!hw->dev_spec._82575.eee_disable)) { 3602 adapter->eee_advert = 3603 MDIO_EEE_100TX | MDIO_EEE_1000T; 3604 adapter->flags |= IGB_FLAG_EEE; 3605 } 3606 break; 3607 case e1000_i354: 3608 if ((rd32(E1000_CTRL_EXT) & 3609 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3610 err = igb_set_eee_i354(hw, true, true); 3611 if ((!err) && 3612 (!hw->dev_spec._82575.eee_disable)) { 3613 adapter->eee_advert = 3614 MDIO_EEE_100TX | MDIO_EEE_1000T; 3615 adapter->flags |= IGB_FLAG_EEE; 3616 } 3617 } 3618 break; 3619 default: 3620 break; 3621 } 3622 } 3623 3624 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3625 3626 pm_runtime_put_noidle(&pdev->dev); 3627 return 0; 3628 3629 err_register: 3630 igb_release_hw_control(adapter); 3631 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3632 err_eeprom: 3633 if (!igb_check_reset_block(hw)) 3634 igb_reset_phy(hw); 3635 3636 if (hw->flash_address) 3637 iounmap(hw->flash_address); 3638 err_sw_init: 3639 kfree(adapter->mac_table); 3640 kfree(adapter->shadow_vfta); 3641 igb_clear_interrupt_scheme(adapter); 3642 #ifdef CONFIG_PCI_IOV 3643 igb_disable_sriov(pdev, false); 3644 #endif 3645 pci_iounmap(pdev, adapter->io_addr); 3646 err_ioremap: 3647 free_netdev(netdev); 3648 err_alloc_etherdev: 3649 pci_release_mem_regions(pdev); 3650 err_pci_reg: 3651 err_dma: 3652 pci_disable_device(pdev); 3653 return err; 3654 } 3655 3656 #ifdef CONFIG_PCI_IOV 3657 static int igb_sriov_reinit(struct pci_dev *dev) 3658 { 3659 struct net_device *netdev = pci_get_drvdata(dev); 3660 struct igb_adapter *adapter = netdev_priv(netdev); 3661 struct pci_dev *pdev = adapter->pdev; 3662 3663 rtnl_lock(); 3664 3665 if (netif_running(netdev)) 3666 igb_close(netdev); 3667 else 3668 igb_reset(adapter); 3669 3670 igb_clear_interrupt_scheme(adapter); 3671 3672 igb_init_queue_configuration(adapter); 3673 3674 if (igb_init_interrupt_scheme(adapter, true)) { 3675 rtnl_unlock(); 3676 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3677 return -ENOMEM; 3678 } 3679 3680 if (netif_running(netdev)) 3681 igb_open(netdev); 3682 3683 rtnl_unlock(); 3684 3685 return 0; 3686 } 3687 3688 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3689 { 3690 struct net_device *netdev = pci_get_drvdata(pdev); 3691 struct igb_adapter *adapter = netdev_priv(netdev); 3692 struct e1000_hw *hw = &adapter->hw; 3693 unsigned long flags; 3694 3695 /* reclaim resources allocated to VFs */ 3696 if (adapter->vf_data) { 3697 /* disable iov and allow time for transactions to clear */ 3698 if (pci_vfs_assigned(pdev)) { 3699 dev_warn(&pdev->dev, 3700 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3701 return -EPERM; 3702 } else { 3703 pci_disable_sriov(pdev); 3704 msleep(500); 3705 } 3706 spin_lock_irqsave(&adapter->vfs_lock, flags); 3707 kfree(adapter->vf_mac_list); 3708 adapter->vf_mac_list = NULL; 3709 kfree(adapter->vf_data); 3710 adapter->vf_data = NULL; 3711 adapter->vfs_allocated_count = 0; 3712 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3713 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3714 wrfl(); 3715 msleep(100); 3716 dev_info(&pdev->dev, "IOV Disabled\n"); 3717 3718 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3719 adapter->flags |= IGB_FLAG_DMAC; 3720 } 3721 3722 return reinit ? igb_sriov_reinit(pdev) : 0; 3723 } 3724 3725 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3726 { 3727 struct net_device *netdev = pci_get_drvdata(pdev); 3728 struct igb_adapter *adapter = netdev_priv(netdev); 3729 int old_vfs = pci_num_vf(pdev); 3730 struct vf_mac_filter *mac_list; 3731 int err = 0; 3732 int num_vf_mac_filters, i; 3733 3734 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3735 err = -EPERM; 3736 goto out; 3737 } 3738 if (!num_vfs) 3739 goto out; 3740 3741 if (old_vfs) { 3742 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3743 old_vfs, max_vfs); 3744 adapter->vfs_allocated_count = old_vfs; 3745 } else 3746 adapter->vfs_allocated_count = num_vfs; 3747 3748 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3749 sizeof(struct vf_data_storage), GFP_KERNEL); 3750 3751 /* if allocation failed then we do not support SR-IOV */ 3752 if (!adapter->vf_data) { 3753 adapter->vfs_allocated_count = 0; 3754 err = -ENOMEM; 3755 goto out; 3756 } 3757 3758 /* Due to the limited number of RAR entries calculate potential 3759 * number of MAC filters available for the VFs. Reserve entries 3760 * for PF default MAC, PF MAC filters and at least one RAR entry 3761 * for each VF for VF MAC. 3762 */ 3763 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3764 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3765 adapter->vfs_allocated_count); 3766 3767 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3768 sizeof(struct vf_mac_filter), 3769 GFP_KERNEL); 3770 3771 mac_list = adapter->vf_mac_list; 3772 INIT_LIST_HEAD(&adapter->vf_macs.l); 3773 3774 if (adapter->vf_mac_list) { 3775 /* Initialize list of VF MAC filters */ 3776 for (i = 0; i < num_vf_mac_filters; i++) { 3777 mac_list->vf = -1; 3778 mac_list->free = true; 3779 list_add(&mac_list->l, &adapter->vf_macs.l); 3780 mac_list++; 3781 } 3782 } else { 3783 /* If we could not allocate memory for the VF MAC filters 3784 * we can continue without this feature but warn user. 3785 */ 3786 dev_err(&pdev->dev, 3787 "Unable to allocate memory for VF MAC filter list\n"); 3788 } 3789 3790 dev_info(&pdev->dev, "%d VFs allocated\n", 3791 adapter->vfs_allocated_count); 3792 for (i = 0; i < adapter->vfs_allocated_count; i++) 3793 igb_vf_configure(adapter, i); 3794 3795 /* DMA Coalescing is not supported in IOV mode. */ 3796 adapter->flags &= ~IGB_FLAG_DMAC; 3797 3798 if (reinit) { 3799 err = igb_sriov_reinit(pdev); 3800 if (err) 3801 goto err_out; 3802 } 3803 3804 /* only call pci_enable_sriov() if no VFs are allocated already */ 3805 if (!old_vfs) { 3806 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3807 if (err) 3808 goto err_out; 3809 } 3810 3811 goto out; 3812 3813 err_out: 3814 kfree(adapter->vf_mac_list); 3815 adapter->vf_mac_list = NULL; 3816 kfree(adapter->vf_data); 3817 adapter->vf_data = NULL; 3818 adapter->vfs_allocated_count = 0; 3819 out: 3820 return err; 3821 } 3822 3823 #endif 3824 /** 3825 * igb_remove_i2c - Cleanup I2C interface 3826 * @adapter: pointer to adapter structure 3827 **/ 3828 static void igb_remove_i2c(struct igb_adapter *adapter) 3829 { 3830 /* free the adapter bus structure */ 3831 i2c_del_adapter(&adapter->i2c_adap); 3832 } 3833 3834 /** 3835 * igb_remove - Device Removal Routine 3836 * @pdev: PCI device information struct 3837 * 3838 * igb_remove is called by the PCI subsystem to alert the driver 3839 * that it should release a PCI device. The could be caused by a 3840 * Hot-Plug event, or because the driver is going to be removed from 3841 * memory. 3842 **/ 3843 static void igb_remove(struct pci_dev *pdev) 3844 { 3845 struct net_device *netdev = pci_get_drvdata(pdev); 3846 struct igb_adapter *adapter = netdev_priv(netdev); 3847 struct e1000_hw *hw = &adapter->hw; 3848 3849 pm_runtime_get_noresume(&pdev->dev); 3850 #ifdef CONFIG_IGB_HWMON 3851 igb_sysfs_exit(adapter); 3852 #endif 3853 igb_remove_i2c(adapter); 3854 igb_ptp_stop(adapter); 3855 /* The watchdog timer may be rescheduled, so explicitly 3856 * disable watchdog from being rescheduled. 3857 */ 3858 set_bit(__IGB_DOWN, &adapter->state); 3859 del_timer_sync(&adapter->watchdog_timer); 3860 del_timer_sync(&adapter->phy_info_timer); 3861 3862 cancel_work_sync(&adapter->reset_task); 3863 cancel_work_sync(&adapter->watchdog_task); 3864 3865 #ifdef CONFIG_IGB_DCA 3866 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3867 dev_info(&pdev->dev, "DCA disabled\n"); 3868 dca_remove_requester(&pdev->dev); 3869 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3870 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3871 } 3872 #endif 3873 3874 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3875 * would have already happened in close and is redundant. 3876 */ 3877 igb_release_hw_control(adapter); 3878 3879 #ifdef CONFIG_PCI_IOV 3880 igb_disable_sriov(pdev, false); 3881 #endif 3882 3883 unregister_netdev(netdev); 3884 3885 igb_clear_interrupt_scheme(adapter); 3886 3887 pci_iounmap(pdev, adapter->io_addr); 3888 if (hw->flash_address) 3889 iounmap(hw->flash_address); 3890 pci_release_mem_regions(pdev); 3891 3892 kfree(adapter->mac_table); 3893 kfree(adapter->shadow_vfta); 3894 free_netdev(netdev); 3895 3896 pci_disable_device(pdev); 3897 } 3898 3899 /** 3900 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3901 * @adapter: board private structure to initialize 3902 * 3903 * This function initializes the vf specific data storage and then attempts to 3904 * allocate the VFs. The reason for ordering it this way is because it is much 3905 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3906 * the memory for the VFs. 3907 **/ 3908 static void igb_probe_vfs(struct igb_adapter *adapter) 3909 { 3910 #ifdef CONFIG_PCI_IOV 3911 struct pci_dev *pdev = adapter->pdev; 3912 struct e1000_hw *hw = &adapter->hw; 3913 3914 /* Virtualization features not supported on i210 and 82580 family. */ 3915 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3916 (hw->mac.type == e1000_82580)) 3917 return; 3918 3919 /* Of the below we really only want the effect of getting 3920 * IGB_FLAG_HAS_MSIX set (if available), without which 3921 * igb_enable_sriov() has no effect. 3922 */ 3923 igb_set_interrupt_capability(adapter, true); 3924 igb_reset_interrupt_capability(adapter); 3925 3926 pci_sriov_set_totalvfs(pdev, 7); 3927 igb_enable_sriov(pdev, max_vfs, false); 3928 3929 #endif /* CONFIG_PCI_IOV */ 3930 } 3931 3932 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3933 { 3934 struct e1000_hw *hw = &adapter->hw; 3935 unsigned int max_rss_queues; 3936 3937 /* Determine the maximum number of RSS queues supported. */ 3938 switch (hw->mac.type) { 3939 case e1000_i211: 3940 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3941 break; 3942 case e1000_82575: 3943 case e1000_i210: 3944 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3945 break; 3946 case e1000_i350: 3947 /* I350 cannot do RSS and SR-IOV at the same time */ 3948 if (!!adapter->vfs_allocated_count) { 3949 max_rss_queues = 1; 3950 break; 3951 } 3952 fallthrough; 3953 case e1000_82576: 3954 if (!!adapter->vfs_allocated_count) { 3955 max_rss_queues = 2; 3956 break; 3957 } 3958 fallthrough; 3959 case e1000_82580: 3960 case e1000_i354: 3961 default: 3962 max_rss_queues = IGB_MAX_RX_QUEUES; 3963 break; 3964 } 3965 3966 return max_rss_queues; 3967 } 3968 3969 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3970 { 3971 u32 max_rss_queues; 3972 3973 max_rss_queues = igb_get_max_rss_queues(adapter); 3974 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3975 3976 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3977 } 3978 3979 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3980 const u32 max_rss_queues) 3981 { 3982 struct e1000_hw *hw = &adapter->hw; 3983 3984 /* Determine if we need to pair queues. */ 3985 switch (hw->mac.type) { 3986 case e1000_82575: 3987 case e1000_i211: 3988 /* Device supports enough interrupts without queue pairing. */ 3989 break; 3990 case e1000_82576: 3991 case e1000_82580: 3992 case e1000_i350: 3993 case e1000_i354: 3994 case e1000_i210: 3995 default: 3996 /* If rss_queues > half of max_rss_queues, pair the queues in 3997 * order to conserve interrupts due to limited supply. 3998 */ 3999 if (adapter->rss_queues > (max_rss_queues / 2)) 4000 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4001 else 4002 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4003 break; 4004 } 4005 } 4006 4007 /** 4008 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4009 * @adapter: board private structure to initialize 4010 * 4011 * igb_sw_init initializes the Adapter private data structure. 4012 * Fields are initialized based on PCI device information and 4013 * OS network device settings (MTU size). 4014 **/ 4015 static int igb_sw_init(struct igb_adapter *adapter) 4016 { 4017 struct e1000_hw *hw = &adapter->hw; 4018 struct net_device *netdev = adapter->netdev; 4019 struct pci_dev *pdev = adapter->pdev; 4020 4021 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4022 4023 /* set default ring sizes */ 4024 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4025 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4026 4027 /* set default ITR values */ 4028 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4029 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4030 4031 /* set default work limits */ 4032 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4033 4034 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4035 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4036 4037 spin_lock_init(&adapter->nfc_lock); 4038 spin_lock_init(&adapter->stats64_lock); 4039 4040 /* init spinlock to avoid concurrency of VF resources */ 4041 spin_lock_init(&adapter->vfs_lock); 4042 #ifdef CONFIG_PCI_IOV 4043 switch (hw->mac.type) { 4044 case e1000_82576: 4045 case e1000_i350: 4046 if (max_vfs > 7) { 4047 dev_warn(&pdev->dev, 4048 "Maximum of 7 VFs per PF, using max\n"); 4049 max_vfs = adapter->vfs_allocated_count = 7; 4050 } else 4051 adapter->vfs_allocated_count = max_vfs; 4052 if (adapter->vfs_allocated_count) 4053 dev_warn(&pdev->dev, 4054 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4055 break; 4056 default: 4057 break; 4058 } 4059 #endif /* CONFIG_PCI_IOV */ 4060 4061 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4062 adapter->flags |= IGB_FLAG_HAS_MSIX; 4063 4064 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4065 sizeof(struct igb_mac_addr), 4066 GFP_KERNEL); 4067 if (!adapter->mac_table) 4068 return -ENOMEM; 4069 4070 igb_probe_vfs(adapter); 4071 4072 igb_init_queue_configuration(adapter); 4073 4074 /* Setup and initialize a copy of the hw vlan table array */ 4075 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4076 GFP_KERNEL); 4077 if (!adapter->shadow_vfta) 4078 return -ENOMEM; 4079 4080 /* This call may decrease the number of queues */ 4081 if (igb_init_interrupt_scheme(adapter, true)) { 4082 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4083 return -ENOMEM; 4084 } 4085 4086 /* Explicitly disable IRQ since the NIC can be in any state. */ 4087 igb_irq_disable(adapter); 4088 4089 if (hw->mac.type >= e1000_i350) 4090 adapter->flags &= ~IGB_FLAG_DMAC; 4091 4092 set_bit(__IGB_DOWN, &adapter->state); 4093 return 0; 4094 } 4095 4096 /** 4097 * __igb_open - Called when a network interface is made active 4098 * @netdev: network interface device structure 4099 * @resuming: indicates whether we are in a resume call 4100 * 4101 * Returns 0 on success, negative value on failure 4102 * 4103 * The open entry point is called when a network interface is made 4104 * active by the system (IFF_UP). At this point all resources needed 4105 * for transmit and receive operations are allocated, the interrupt 4106 * handler is registered with the OS, the watchdog timer is started, 4107 * and the stack is notified that the interface is ready. 4108 **/ 4109 static int __igb_open(struct net_device *netdev, bool resuming) 4110 { 4111 struct igb_adapter *adapter = netdev_priv(netdev); 4112 struct e1000_hw *hw = &adapter->hw; 4113 struct pci_dev *pdev = adapter->pdev; 4114 int err; 4115 int i; 4116 4117 /* disallow open during test */ 4118 if (test_bit(__IGB_TESTING, &adapter->state)) { 4119 WARN_ON(resuming); 4120 return -EBUSY; 4121 } 4122 4123 if (!resuming) 4124 pm_runtime_get_sync(&pdev->dev); 4125 4126 netif_carrier_off(netdev); 4127 4128 /* allocate transmit descriptors */ 4129 err = igb_setup_all_tx_resources(adapter); 4130 if (err) 4131 goto err_setup_tx; 4132 4133 /* allocate receive descriptors */ 4134 err = igb_setup_all_rx_resources(adapter); 4135 if (err) 4136 goto err_setup_rx; 4137 4138 igb_power_up_link(adapter); 4139 4140 /* before we allocate an interrupt, we must be ready to handle it. 4141 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4142 * as soon as we call pci_request_irq, so we have to setup our 4143 * clean_rx handler before we do so. 4144 */ 4145 igb_configure(adapter); 4146 4147 err = igb_request_irq(adapter); 4148 if (err) 4149 goto err_req_irq; 4150 4151 /* Notify the stack of the actual queue counts. */ 4152 err = netif_set_real_num_tx_queues(adapter->netdev, 4153 adapter->num_tx_queues); 4154 if (err) 4155 goto err_set_queues; 4156 4157 err = netif_set_real_num_rx_queues(adapter->netdev, 4158 adapter->num_rx_queues); 4159 if (err) 4160 goto err_set_queues; 4161 4162 /* From here on the code is the same as igb_up() */ 4163 clear_bit(__IGB_DOWN, &adapter->state); 4164 4165 for (i = 0; i < adapter->num_q_vectors; i++) 4166 napi_enable(&(adapter->q_vector[i]->napi)); 4167 4168 /* Clear any pending interrupts. */ 4169 rd32(E1000_TSICR); 4170 rd32(E1000_ICR); 4171 4172 igb_irq_enable(adapter); 4173 4174 /* notify VFs that reset has been completed */ 4175 if (adapter->vfs_allocated_count) { 4176 u32 reg_data = rd32(E1000_CTRL_EXT); 4177 4178 reg_data |= E1000_CTRL_EXT_PFRSTD; 4179 wr32(E1000_CTRL_EXT, reg_data); 4180 } 4181 4182 netif_tx_start_all_queues(netdev); 4183 4184 if (!resuming) 4185 pm_runtime_put(&pdev->dev); 4186 4187 /* start the watchdog. */ 4188 hw->mac.get_link_status = 1; 4189 schedule_work(&adapter->watchdog_task); 4190 4191 return 0; 4192 4193 err_set_queues: 4194 igb_free_irq(adapter); 4195 err_req_irq: 4196 igb_release_hw_control(adapter); 4197 igb_power_down_link(adapter); 4198 igb_free_all_rx_resources(adapter); 4199 err_setup_rx: 4200 igb_free_all_tx_resources(adapter); 4201 err_setup_tx: 4202 igb_reset(adapter); 4203 if (!resuming) 4204 pm_runtime_put(&pdev->dev); 4205 4206 return err; 4207 } 4208 4209 int igb_open(struct net_device *netdev) 4210 { 4211 return __igb_open(netdev, false); 4212 } 4213 4214 /** 4215 * __igb_close - Disables a network interface 4216 * @netdev: network interface device structure 4217 * @suspending: indicates we are in a suspend call 4218 * 4219 * Returns 0, this is not allowed to fail 4220 * 4221 * The close entry point is called when an interface is de-activated 4222 * by the OS. The hardware is still under the driver's control, but 4223 * needs to be disabled. A global MAC reset is issued to stop the 4224 * hardware, and all transmit and receive resources are freed. 4225 **/ 4226 static int __igb_close(struct net_device *netdev, bool suspending) 4227 { 4228 struct igb_adapter *adapter = netdev_priv(netdev); 4229 struct pci_dev *pdev = adapter->pdev; 4230 4231 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4232 4233 if (!suspending) 4234 pm_runtime_get_sync(&pdev->dev); 4235 4236 igb_down(adapter); 4237 igb_free_irq(adapter); 4238 4239 igb_free_all_tx_resources(adapter); 4240 igb_free_all_rx_resources(adapter); 4241 4242 if (!suspending) 4243 pm_runtime_put_sync(&pdev->dev); 4244 return 0; 4245 } 4246 4247 int igb_close(struct net_device *netdev) 4248 { 4249 if (netif_device_present(netdev) || netdev->dismantle) 4250 return __igb_close(netdev, false); 4251 return 0; 4252 } 4253 4254 /** 4255 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4256 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4257 * 4258 * Return 0 on success, negative on failure 4259 **/ 4260 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4261 { 4262 struct device *dev = tx_ring->dev; 4263 int size; 4264 4265 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4266 4267 tx_ring->tx_buffer_info = vmalloc(size); 4268 if (!tx_ring->tx_buffer_info) 4269 goto err; 4270 4271 /* round up to nearest 4K */ 4272 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4273 tx_ring->size = ALIGN(tx_ring->size, 4096); 4274 4275 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4276 &tx_ring->dma, GFP_KERNEL); 4277 if (!tx_ring->desc) 4278 goto err; 4279 4280 tx_ring->next_to_use = 0; 4281 tx_ring->next_to_clean = 0; 4282 4283 return 0; 4284 4285 err: 4286 vfree(tx_ring->tx_buffer_info); 4287 tx_ring->tx_buffer_info = NULL; 4288 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4289 return -ENOMEM; 4290 } 4291 4292 /** 4293 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4294 * (Descriptors) for all queues 4295 * @adapter: board private structure 4296 * 4297 * Return 0 on success, negative on failure 4298 **/ 4299 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4300 { 4301 struct pci_dev *pdev = adapter->pdev; 4302 int i, err = 0; 4303 4304 for (i = 0; i < adapter->num_tx_queues; i++) { 4305 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4306 if (err) { 4307 dev_err(&pdev->dev, 4308 "Allocation for Tx Queue %u failed\n", i); 4309 for (i--; i >= 0; i--) 4310 igb_free_tx_resources(adapter->tx_ring[i]); 4311 break; 4312 } 4313 } 4314 4315 return err; 4316 } 4317 4318 /** 4319 * igb_setup_tctl - configure the transmit control registers 4320 * @adapter: Board private structure 4321 **/ 4322 void igb_setup_tctl(struct igb_adapter *adapter) 4323 { 4324 struct e1000_hw *hw = &adapter->hw; 4325 u32 tctl; 4326 4327 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4328 wr32(E1000_TXDCTL(0), 0); 4329 4330 /* Program the Transmit Control Register */ 4331 tctl = rd32(E1000_TCTL); 4332 tctl &= ~E1000_TCTL_CT; 4333 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4334 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4335 4336 igb_config_collision_dist(hw); 4337 4338 /* Enable transmits */ 4339 tctl |= E1000_TCTL_EN; 4340 4341 wr32(E1000_TCTL, tctl); 4342 } 4343 4344 /** 4345 * igb_configure_tx_ring - Configure transmit ring after Reset 4346 * @adapter: board private structure 4347 * @ring: tx ring to configure 4348 * 4349 * Configure a transmit ring after a reset. 4350 **/ 4351 void igb_configure_tx_ring(struct igb_adapter *adapter, 4352 struct igb_ring *ring) 4353 { 4354 struct e1000_hw *hw = &adapter->hw; 4355 u32 txdctl = 0; 4356 u64 tdba = ring->dma; 4357 int reg_idx = ring->reg_idx; 4358 4359 wr32(E1000_TDLEN(reg_idx), 4360 ring->count * sizeof(union e1000_adv_tx_desc)); 4361 wr32(E1000_TDBAL(reg_idx), 4362 tdba & 0x00000000ffffffffULL); 4363 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4364 4365 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4366 wr32(E1000_TDH(reg_idx), 0); 4367 writel(0, ring->tail); 4368 4369 txdctl |= IGB_TX_PTHRESH; 4370 txdctl |= IGB_TX_HTHRESH << 8; 4371 txdctl |= IGB_TX_WTHRESH << 16; 4372 4373 /* reinitialize tx_buffer_info */ 4374 memset(ring->tx_buffer_info, 0, 4375 sizeof(struct igb_tx_buffer) * ring->count); 4376 4377 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4378 wr32(E1000_TXDCTL(reg_idx), txdctl); 4379 } 4380 4381 /** 4382 * igb_configure_tx - Configure transmit Unit after Reset 4383 * @adapter: board private structure 4384 * 4385 * Configure the Tx unit of the MAC after a reset. 4386 **/ 4387 static void igb_configure_tx(struct igb_adapter *adapter) 4388 { 4389 struct e1000_hw *hw = &adapter->hw; 4390 int i; 4391 4392 /* disable the queues */ 4393 for (i = 0; i < adapter->num_tx_queues; i++) 4394 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4395 4396 wrfl(); 4397 usleep_range(10000, 20000); 4398 4399 for (i = 0; i < adapter->num_tx_queues; i++) 4400 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4401 } 4402 4403 /** 4404 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4405 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4406 * 4407 * Returns 0 on success, negative on failure 4408 **/ 4409 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4410 { 4411 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4412 struct device *dev = rx_ring->dev; 4413 int size, res; 4414 4415 /* XDP RX-queue info */ 4416 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4417 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4418 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4419 rx_ring->queue_index, 0); 4420 if (res < 0) { 4421 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4422 rx_ring->queue_index); 4423 return res; 4424 } 4425 4426 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4427 4428 rx_ring->rx_buffer_info = vmalloc(size); 4429 if (!rx_ring->rx_buffer_info) 4430 goto err; 4431 4432 /* Round up to nearest 4K */ 4433 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4434 rx_ring->size = ALIGN(rx_ring->size, 4096); 4435 4436 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4437 &rx_ring->dma, GFP_KERNEL); 4438 if (!rx_ring->desc) 4439 goto err; 4440 4441 rx_ring->next_to_alloc = 0; 4442 rx_ring->next_to_clean = 0; 4443 rx_ring->next_to_use = 0; 4444 4445 rx_ring->xdp_prog = adapter->xdp_prog; 4446 4447 return 0; 4448 4449 err: 4450 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4451 vfree(rx_ring->rx_buffer_info); 4452 rx_ring->rx_buffer_info = NULL; 4453 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4454 return -ENOMEM; 4455 } 4456 4457 /** 4458 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4459 * (Descriptors) for all queues 4460 * @adapter: board private structure 4461 * 4462 * Return 0 on success, negative on failure 4463 **/ 4464 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4465 { 4466 struct pci_dev *pdev = adapter->pdev; 4467 int i, err = 0; 4468 4469 for (i = 0; i < adapter->num_rx_queues; i++) { 4470 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4471 if (err) { 4472 dev_err(&pdev->dev, 4473 "Allocation for Rx Queue %u failed\n", i); 4474 for (i--; i >= 0; i--) 4475 igb_free_rx_resources(adapter->rx_ring[i]); 4476 break; 4477 } 4478 } 4479 4480 return err; 4481 } 4482 4483 /** 4484 * igb_setup_mrqc - configure the multiple receive queue control registers 4485 * @adapter: Board private structure 4486 **/ 4487 static void igb_setup_mrqc(struct igb_adapter *adapter) 4488 { 4489 struct e1000_hw *hw = &adapter->hw; 4490 u32 mrqc, rxcsum; 4491 u32 j, num_rx_queues; 4492 u32 rss_key[10]; 4493 4494 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4495 for (j = 0; j < 10; j++) 4496 wr32(E1000_RSSRK(j), rss_key[j]); 4497 4498 num_rx_queues = adapter->rss_queues; 4499 4500 switch (hw->mac.type) { 4501 case e1000_82576: 4502 /* 82576 supports 2 RSS queues for SR-IOV */ 4503 if (adapter->vfs_allocated_count) 4504 num_rx_queues = 2; 4505 break; 4506 default: 4507 break; 4508 } 4509 4510 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4511 for (j = 0; j < IGB_RETA_SIZE; j++) 4512 adapter->rss_indir_tbl[j] = 4513 (j * num_rx_queues) / IGB_RETA_SIZE; 4514 adapter->rss_indir_tbl_init = num_rx_queues; 4515 } 4516 igb_write_rss_indir_tbl(adapter); 4517 4518 /* Disable raw packet checksumming so that RSS hash is placed in 4519 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4520 * offloads as they are enabled by default 4521 */ 4522 rxcsum = rd32(E1000_RXCSUM); 4523 rxcsum |= E1000_RXCSUM_PCSD; 4524 4525 if (adapter->hw.mac.type >= e1000_82576) 4526 /* Enable Receive Checksum Offload for SCTP */ 4527 rxcsum |= E1000_RXCSUM_CRCOFL; 4528 4529 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4530 wr32(E1000_RXCSUM, rxcsum); 4531 4532 /* Generate RSS hash based on packet types, TCP/UDP 4533 * port numbers and/or IPv4/v6 src and dst addresses 4534 */ 4535 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4536 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4537 E1000_MRQC_RSS_FIELD_IPV6 | 4538 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4539 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4540 4541 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4542 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4543 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4544 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4545 4546 /* If VMDq is enabled then we set the appropriate mode for that, else 4547 * we default to RSS so that an RSS hash is calculated per packet even 4548 * if we are only using one queue 4549 */ 4550 if (adapter->vfs_allocated_count) { 4551 if (hw->mac.type > e1000_82575) { 4552 /* Set the default pool for the PF's first queue */ 4553 u32 vtctl = rd32(E1000_VT_CTL); 4554 4555 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4556 E1000_VT_CTL_DISABLE_DEF_POOL); 4557 vtctl |= adapter->vfs_allocated_count << 4558 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4559 wr32(E1000_VT_CTL, vtctl); 4560 } 4561 if (adapter->rss_queues > 1) 4562 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4563 else 4564 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4565 } else { 4566 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4567 } 4568 igb_vmm_control(adapter); 4569 4570 wr32(E1000_MRQC, mrqc); 4571 } 4572 4573 /** 4574 * igb_setup_rctl - configure the receive control registers 4575 * @adapter: Board private structure 4576 **/ 4577 void igb_setup_rctl(struct igb_adapter *adapter) 4578 { 4579 struct e1000_hw *hw = &adapter->hw; 4580 u32 rctl; 4581 4582 rctl = rd32(E1000_RCTL); 4583 4584 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4585 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4586 4587 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4588 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4589 4590 /* enable stripping of CRC. It's unlikely this will break BMC 4591 * redirection as it did with e1000. Newer features require 4592 * that the HW strips the CRC. 4593 */ 4594 rctl |= E1000_RCTL_SECRC; 4595 4596 /* disable store bad packets and clear size bits. */ 4597 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4598 4599 /* enable LPE to allow for reception of jumbo frames */ 4600 rctl |= E1000_RCTL_LPE; 4601 4602 /* disable queue 0 to prevent tail write w/o re-config */ 4603 wr32(E1000_RXDCTL(0), 0); 4604 4605 /* Attention!!! For SR-IOV PF driver operations you must enable 4606 * queue drop for all VF and PF queues to prevent head of line blocking 4607 * if an un-trusted VF does not provide descriptors to hardware. 4608 */ 4609 if (adapter->vfs_allocated_count) { 4610 /* set all queue drop enable bits */ 4611 wr32(E1000_QDE, ALL_QUEUES); 4612 } 4613 4614 /* This is useful for sniffing bad packets. */ 4615 if (adapter->netdev->features & NETIF_F_RXALL) { 4616 /* UPE and MPE will be handled by normal PROMISC logic 4617 * in e1000e_set_rx_mode 4618 */ 4619 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4620 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4621 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4622 4623 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4624 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4625 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4626 * and that breaks VLANs. 4627 */ 4628 } 4629 4630 wr32(E1000_RCTL, rctl); 4631 } 4632 4633 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4634 int vfn) 4635 { 4636 struct e1000_hw *hw = &adapter->hw; 4637 u32 vmolr; 4638 4639 if (size > MAX_JUMBO_FRAME_SIZE) 4640 size = MAX_JUMBO_FRAME_SIZE; 4641 4642 vmolr = rd32(E1000_VMOLR(vfn)); 4643 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4644 vmolr |= size | E1000_VMOLR_LPE; 4645 wr32(E1000_VMOLR(vfn), vmolr); 4646 4647 return 0; 4648 } 4649 4650 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4651 int vfn, bool enable) 4652 { 4653 struct e1000_hw *hw = &adapter->hw; 4654 u32 val, reg; 4655 4656 if (hw->mac.type < e1000_82576) 4657 return; 4658 4659 if (hw->mac.type == e1000_i350) 4660 reg = E1000_DVMOLR(vfn); 4661 else 4662 reg = E1000_VMOLR(vfn); 4663 4664 val = rd32(reg); 4665 if (enable) 4666 val |= E1000_VMOLR_STRVLAN; 4667 else 4668 val &= ~(E1000_VMOLR_STRVLAN); 4669 wr32(reg, val); 4670 } 4671 4672 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4673 int vfn, bool aupe) 4674 { 4675 struct e1000_hw *hw = &adapter->hw; 4676 u32 vmolr; 4677 4678 /* This register exists only on 82576 and newer so if we are older then 4679 * we should exit and do nothing 4680 */ 4681 if (hw->mac.type < e1000_82576) 4682 return; 4683 4684 vmolr = rd32(E1000_VMOLR(vfn)); 4685 if (aupe) 4686 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4687 else 4688 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4689 4690 /* clear all bits that might not be set */ 4691 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4692 4693 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4694 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4695 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4696 * multicast packets 4697 */ 4698 if (vfn <= adapter->vfs_allocated_count) 4699 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4700 4701 wr32(E1000_VMOLR(vfn), vmolr); 4702 } 4703 4704 /** 4705 * igb_setup_srrctl - configure the split and replication receive control 4706 * registers 4707 * @adapter: Board private structure 4708 * @ring: receive ring to be configured 4709 **/ 4710 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4711 { 4712 struct e1000_hw *hw = &adapter->hw; 4713 int reg_idx = ring->reg_idx; 4714 u32 srrctl = 0; 4715 4716 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4717 if (ring_uses_large_buffer(ring)) 4718 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4719 else 4720 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4721 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4722 if (hw->mac.type >= e1000_82580) 4723 srrctl |= E1000_SRRCTL_TIMESTAMP; 4724 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4725 * queues and rx flow control is disabled 4726 */ 4727 if (adapter->vfs_allocated_count || 4728 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4729 adapter->num_rx_queues > 1)) 4730 srrctl |= E1000_SRRCTL_DROP_EN; 4731 4732 wr32(E1000_SRRCTL(reg_idx), srrctl); 4733 } 4734 4735 /** 4736 * igb_configure_rx_ring - Configure a receive ring after Reset 4737 * @adapter: board private structure 4738 * @ring: receive ring to be configured 4739 * 4740 * Configure the Rx unit of the MAC after a reset. 4741 **/ 4742 void igb_configure_rx_ring(struct igb_adapter *adapter, 4743 struct igb_ring *ring) 4744 { 4745 struct e1000_hw *hw = &adapter->hw; 4746 union e1000_adv_rx_desc *rx_desc; 4747 u64 rdba = ring->dma; 4748 int reg_idx = ring->reg_idx; 4749 u32 rxdctl = 0; 4750 4751 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4752 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4753 MEM_TYPE_PAGE_SHARED, NULL)); 4754 4755 /* disable the queue */ 4756 wr32(E1000_RXDCTL(reg_idx), 0); 4757 4758 /* Set DMA base address registers */ 4759 wr32(E1000_RDBAL(reg_idx), 4760 rdba & 0x00000000ffffffffULL); 4761 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4762 wr32(E1000_RDLEN(reg_idx), 4763 ring->count * sizeof(union e1000_adv_rx_desc)); 4764 4765 /* initialize head and tail */ 4766 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4767 wr32(E1000_RDH(reg_idx), 0); 4768 writel(0, ring->tail); 4769 4770 /* set descriptor configuration */ 4771 igb_setup_srrctl(adapter, ring); 4772 4773 /* set filtering for VMDQ pools */ 4774 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4775 4776 rxdctl |= IGB_RX_PTHRESH; 4777 rxdctl |= IGB_RX_HTHRESH << 8; 4778 rxdctl |= IGB_RX_WTHRESH << 16; 4779 4780 /* initialize rx_buffer_info */ 4781 memset(ring->rx_buffer_info, 0, 4782 sizeof(struct igb_rx_buffer) * ring->count); 4783 4784 /* initialize Rx descriptor 0 */ 4785 rx_desc = IGB_RX_DESC(ring, 0); 4786 rx_desc->wb.upper.length = 0; 4787 4788 /* enable receive descriptor fetching */ 4789 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4790 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4791 } 4792 4793 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4794 struct igb_ring *rx_ring) 4795 { 4796 #if (PAGE_SIZE < 8192) 4797 struct e1000_hw *hw = &adapter->hw; 4798 #endif 4799 4800 /* set build_skb and buffer size flags */ 4801 clear_ring_build_skb_enabled(rx_ring); 4802 clear_ring_uses_large_buffer(rx_ring); 4803 4804 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4805 return; 4806 4807 set_ring_build_skb_enabled(rx_ring); 4808 4809 #if (PAGE_SIZE < 8192) 4810 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4811 IGB_2K_TOO_SMALL_WITH_PADDING || 4812 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4813 set_ring_uses_large_buffer(rx_ring); 4814 #endif 4815 } 4816 4817 /** 4818 * igb_configure_rx - Configure receive Unit after Reset 4819 * @adapter: board private structure 4820 * 4821 * Configure the Rx unit of the MAC after a reset. 4822 **/ 4823 static void igb_configure_rx(struct igb_adapter *adapter) 4824 { 4825 int i; 4826 4827 /* set the correct pool for the PF default MAC address in entry 0 */ 4828 igb_set_default_mac_filter(adapter); 4829 4830 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4831 * the Base and Length of the Rx Descriptor Ring 4832 */ 4833 for (i = 0; i < adapter->num_rx_queues; i++) { 4834 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4835 4836 igb_set_rx_buffer_len(adapter, rx_ring); 4837 igb_configure_rx_ring(adapter, rx_ring); 4838 } 4839 } 4840 4841 /** 4842 * igb_free_tx_resources - Free Tx Resources per Queue 4843 * @tx_ring: Tx descriptor ring for a specific queue 4844 * 4845 * Free all transmit software resources 4846 **/ 4847 void igb_free_tx_resources(struct igb_ring *tx_ring) 4848 { 4849 igb_clean_tx_ring(tx_ring); 4850 4851 vfree(tx_ring->tx_buffer_info); 4852 tx_ring->tx_buffer_info = NULL; 4853 4854 /* if not set, then don't free */ 4855 if (!tx_ring->desc) 4856 return; 4857 4858 dma_free_coherent(tx_ring->dev, tx_ring->size, 4859 tx_ring->desc, tx_ring->dma); 4860 4861 tx_ring->desc = NULL; 4862 } 4863 4864 /** 4865 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4866 * @adapter: board private structure 4867 * 4868 * Free all transmit software resources 4869 **/ 4870 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4871 { 4872 int i; 4873 4874 for (i = 0; i < adapter->num_tx_queues; i++) 4875 if (adapter->tx_ring[i]) 4876 igb_free_tx_resources(adapter->tx_ring[i]); 4877 } 4878 4879 /** 4880 * igb_clean_tx_ring - Free Tx Buffers 4881 * @tx_ring: ring to be cleaned 4882 **/ 4883 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4884 { 4885 u16 i = tx_ring->next_to_clean; 4886 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4887 4888 while (i != tx_ring->next_to_use) { 4889 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4890 4891 /* Free all the Tx ring sk_buffs or xdp frames */ 4892 if (tx_buffer->type == IGB_TYPE_SKB) 4893 dev_kfree_skb_any(tx_buffer->skb); 4894 else 4895 xdp_return_frame(tx_buffer->xdpf); 4896 4897 /* unmap skb header data */ 4898 dma_unmap_single(tx_ring->dev, 4899 dma_unmap_addr(tx_buffer, dma), 4900 dma_unmap_len(tx_buffer, len), 4901 DMA_TO_DEVICE); 4902 4903 /* check for eop_desc to determine the end of the packet */ 4904 eop_desc = tx_buffer->next_to_watch; 4905 tx_desc = IGB_TX_DESC(tx_ring, i); 4906 4907 /* unmap remaining buffers */ 4908 while (tx_desc != eop_desc) { 4909 tx_buffer++; 4910 tx_desc++; 4911 i++; 4912 if (unlikely(i == tx_ring->count)) { 4913 i = 0; 4914 tx_buffer = tx_ring->tx_buffer_info; 4915 tx_desc = IGB_TX_DESC(tx_ring, 0); 4916 } 4917 4918 /* unmap any remaining paged data */ 4919 if (dma_unmap_len(tx_buffer, len)) 4920 dma_unmap_page(tx_ring->dev, 4921 dma_unmap_addr(tx_buffer, dma), 4922 dma_unmap_len(tx_buffer, len), 4923 DMA_TO_DEVICE); 4924 } 4925 4926 tx_buffer->next_to_watch = NULL; 4927 4928 /* move us one more past the eop_desc for start of next pkt */ 4929 tx_buffer++; 4930 i++; 4931 if (unlikely(i == tx_ring->count)) { 4932 i = 0; 4933 tx_buffer = tx_ring->tx_buffer_info; 4934 } 4935 } 4936 4937 /* reset BQL for queue */ 4938 netdev_tx_reset_queue(txring_txq(tx_ring)); 4939 4940 /* reset next_to_use and next_to_clean */ 4941 tx_ring->next_to_use = 0; 4942 tx_ring->next_to_clean = 0; 4943 } 4944 4945 /** 4946 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4947 * @adapter: board private structure 4948 **/ 4949 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4950 { 4951 int i; 4952 4953 for (i = 0; i < adapter->num_tx_queues; i++) 4954 if (adapter->tx_ring[i]) 4955 igb_clean_tx_ring(adapter->tx_ring[i]); 4956 } 4957 4958 /** 4959 * igb_free_rx_resources - Free Rx Resources 4960 * @rx_ring: ring to clean the resources from 4961 * 4962 * Free all receive software resources 4963 **/ 4964 void igb_free_rx_resources(struct igb_ring *rx_ring) 4965 { 4966 igb_clean_rx_ring(rx_ring); 4967 4968 rx_ring->xdp_prog = NULL; 4969 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4970 vfree(rx_ring->rx_buffer_info); 4971 rx_ring->rx_buffer_info = NULL; 4972 4973 /* if not set, then don't free */ 4974 if (!rx_ring->desc) 4975 return; 4976 4977 dma_free_coherent(rx_ring->dev, rx_ring->size, 4978 rx_ring->desc, rx_ring->dma); 4979 4980 rx_ring->desc = NULL; 4981 } 4982 4983 /** 4984 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4985 * @adapter: board private structure 4986 * 4987 * Free all receive software resources 4988 **/ 4989 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4990 { 4991 int i; 4992 4993 for (i = 0; i < adapter->num_rx_queues; i++) 4994 if (adapter->rx_ring[i]) 4995 igb_free_rx_resources(adapter->rx_ring[i]); 4996 } 4997 4998 /** 4999 * igb_clean_rx_ring - Free Rx Buffers per Queue 5000 * @rx_ring: ring to free buffers from 5001 **/ 5002 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5003 { 5004 u16 i = rx_ring->next_to_clean; 5005 5006 dev_kfree_skb(rx_ring->skb); 5007 rx_ring->skb = NULL; 5008 5009 /* Free all the Rx ring sk_buffs */ 5010 while (i != rx_ring->next_to_alloc) { 5011 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5012 5013 /* Invalidate cache lines that may have been written to by 5014 * device so that we avoid corrupting memory. 5015 */ 5016 dma_sync_single_range_for_cpu(rx_ring->dev, 5017 buffer_info->dma, 5018 buffer_info->page_offset, 5019 igb_rx_bufsz(rx_ring), 5020 DMA_FROM_DEVICE); 5021 5022 /* free resources associated with mapping */ 5023 dma_unmap_page_attrs(rx_ring->dev, 5024 buffer_info->dma, 5025 igb_rx_pg_size(rx_ring), 5026 DMA_FROM_DEVICE, 5027 IGB_RX_DMA_ATTR); 5028 __page_frag_cache_drain(buffer_info->page, 5029 buffer_info->pagecnt_bias); 5030 5031 i++; 5032 if (i == rx_ring->count) 5033 i = 0; 5034 } 5035 5036 rx_ring->next_to_alloc = 0; 5037 rx_ring->next_to_clean = 0; 5038 rx_ring->next_to_use = 0; 5039 } 5040 5041 /** 5042 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5043 * @adapter: board private structure 5044 **/ 5045 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5046 { 5047 int i; 5048 5049 for (i = 0; i < adapter->num_rx_queues; i++) 5050 if (adapter->rx_ring[i]) 5051 igb_clean_rx_ring(adapter->rx_ring[i]); 5052 } 5053 5054 /** 5055 * igb_set_mac - Change the Ethernet Address of the NIC 5056 * @netdev: network interface device structure 5057 * @p: pointer to an address structure 5058 * 5059 * Returns 0 on success, negative on failure 5060 **/ 5061 static int igb_set_mac(struct net_device *netdev, void *p) 5062 { 5063 struct igb_adapter *adapter = netdev_priv(netdev); 5064 struct e1000_hw *hw = &adapter->hw; 5065 struct sockaddr *addr = p; 5066 5067 if (!is_valid_ether_addr(addr->sa_data)) 5068 return -EADDRNOTAVAIL; 5069 5070 eth_hw_addr_set(netdev, addr->sa_data); 5071 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5072 5073 /* set the correct pool for the new PF MAC address in entry 0 */ 5074 igb_set_default_mac_filter(adapter); 5075 5076 return 0; 5077 } 5078 5079 /** 5080 * igb_write_mc_addr_list - write multicast addresses to MTA 5081 * @netdev: network interface device structure 5082 * 5083 * Writes multicast address list to the MTA hash table. 5084 * Returns: -ENOMEM on failure 5085 * 0 on no addresses written 5086 * X on writing X addresses to MTA 5087 **/ 5088 static int igb_write_mc_addr_list(struct net_device *netdev) 5089 { 5090 struct igb_adapter *adapter = netdev_priv(netdev); 5091 struct e1000_hw *hw = &adapter->hw; 5092 struct netdev_hw_addr *ha; 5093 u8 *mta_list; 5094 int i; 5095 5096 if (netdev_mc_empty(netdev)) { 5097 /* nothing to program, so clear mc list */ 5098 igb_update_mc_addr_list(hw, NULL, 0); 5099 igb_restore_vf_multicasts(adapter); 5100 return 0; 5101 } 5102 5103 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5104 if (!mta_list) 5105 return -ENOMEM; 5106 5107 /* The shared function expects a packed array of only addresses. */ 5108 i = 0; 5109 netdev_for_each_mc_addr(ha, netdev) 5110 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5111 5112 igb_update_mc_addr_list(hw, mta_list, i); 5113 kfree(mta_list); 5114 5115 return netdev_mc_count(netdev); 5116 } 5117 5118 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5119 { 5120 struct e1000_hw *hw = &adapter->hw; 5121 u32 i, pf_id; 5122 5123 switch (hw->mac.type) { 5124 case e1000_i210: 5125 case e1000_i211: 5126 case e1000_i350: 5127 /* VLAN filtering needed for VLAN prio filter */ 5128 if (adapter->netdev->features & NETIF_F_NTUPLE) 5129 break; 5130 fallthrough; 5131 case e1000_82576: 5132 case e1000_82580: 5133 case e1000_i354: 5134 /* VLAN filtering needed for pool filtering */ 5135 if (adapter->vfs_allocated_count) 5136 break; 5137 fallthrough; 5138 default: 5139 return 1; 5140 } 5141 5142 /* We are already in VLAN promisc, nothing to do */ 5143 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5144 return 0; 5145 5146 if (!adapter->vfs_allocated_count) 5147 goto set_vfta; 5148 5149 /* Add PF to all active pools */ 5150 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5151 5152 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5153 u32 vlvf = rd32(E1000_VLVF(i)); 5154 5155 vlvf |= BIT(pf_id); 5156 wr32(E1000_VLVF(i), vlvf); 5157 } 5158 5159 set_vfta: 5160 /* Set all bits in the VLAN filter table array */ 5161 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5162 hw->mac.ops.write_vfta(hw, i, ~0U); 5163 5164 /* Set flag so we don't redo unnecessary work */ 5165 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5166 5167 return 0; 5168 } 5169 5170 #define VFTA_BLOCK_SIZE 8 5171 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5172 { 5173 struct e1000_hw *hw = &adapter->hw; 5174 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5175 u32 vid_start = vfta_offset * 32; 5176 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5177 u32 i, vid, word, bits, pf_id; 5178 5179 /* guarantee that we don't scrub out management VLAN */ 5180 vid = adapter->mng_vlan_id; 5181 if (vid >= vid_start && vid < vid_end) 5182 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5183 5184 if (!adapter->vfs_allocated_count) 5185 goto set_vfta; 5186 5187 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5188 5189 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5190 u32 vlvf = rd32(E1000_VLVF(i)); 5191 5192 /* pull VLAN ID from VLVF */ 5193 vid = vlvf & VLAN_VID_MASK; 5194 5195 /* only concern ourselves with a certain range */ 5196 if (vid < vid_start || vid >= vid_end) 5197 continue; 5198 5199 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5200 /* record VLAN ID in VFTA */ 5201 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5202 5203 /* if PF is part of this then continue */ 5204 if (test_bit(vid, adapter->active_vlans)) 5205 continue; 5206 } 5207 5208 /* remove PF from the pool */ 5209 bits = ~BIT(pf_id); 5210 bits &= rd32(E1000_VLVF(i)); 5211 wr32(E1000_VLVF(i), bits); 5212 } 5213 5214 set_vfta: 5215 /* extract values from active_vlans and write back to VFTA */ 5216 for (i = VFTA_BLOCK_SIZE; i--;) { 5217 vid = (vfta_offset + i) * 32; 5218 word = vid / BITS_PER_LONG; 5219 bits = vid % BITS_PER_LONG; 5220 5221 vfta[i] |= adapter->active_vlans[word] >> bits; 5222 5223 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5224 } 5225 } 5226 5227 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5228 { 5229 u32 i; 5230 5231 /* We are not in VLAN promisc, nothing to do */ 5232 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5233 return; 5234 5235 /* Set flag so we don't redo unnecessary work */ 5236 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5237 5238 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5239 igb_scrub_vfta(adapter, i); 5240 } 5241 5242 /** 5243 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5244 * @netdev: network interface device structure 5245 * 5246 * The set_rx_mode entry point is called whenever the unicast or multicast 5247 * address lists or the network interface flags are updated. This routine is 5248 * responsible for configuring the hardware for proper unicast, multicast, 5249 * promiscuous mode, and all-multi behavior. 5250 **/ 5251 static void igb_set_rx_mode(struct net_device *netdev) 5252 { 5253 struct igb_adapter *adapter = netdev_priv(netdev); 5254 struct e1000_hw *hw = &adapter->hw; 5255 unsigned int vfn = adapter->vfs_allocated_count; 5256 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5257 int count; 5258 5259 /* Check for Promiscuous and All Multicast modes */ 5260 if (netdev->flags & IFF_PROMISC) { 5261 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5262 vmolr |= E1000_VMOLR_MPME; 5263 5264 /* enable use of UTA filter to force packets to default pool */ 5265 if (hw->mac.type == e1000_82576) 5266 vmolr |= E1000_VMOLR_ROPE; 5267 } else { 5268 if (netdev->flags & IFF_ALLMULTI) { 5269 rctl |= E1000_RCTL_MPE; 5270 vmolr |= E1000_VMOLR_MPME; 5271 } else { 5272 /* Write addresses to the MTA, if the attempt fails 5273 * then we should just turn on promiscuous mode so 5274 * that we can at least receive multicast traffic 5275 */ 5276 count = igb_write_mc_addr_list(netdev); 5277 if (count < 0) { 5278 rctl |= E1000_RCTL_MPE; 5279 vmolr |= E1000_VMOLR_MPME; 5280 } else if (count) { 5281 vmolr |= E1000_VMOLR_ROMPE; 5282 } 5283 } 5284 } 5285 5286 /* Write addresses to available RAR registers, if there is not 5287 * sufficient space to store all the addresses then enable 5288 * unicast promiscuous mode 5289 */ 5290 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5291 rctl |= E1000_RCTL_UPE; 5292 vmolr |= E1000_VMOLR_ROPE; 5293 } 5294 5295 /* enable VLAN filtering by default */ 5296 rctl |= E1000_RCTL_VFE; 5297 5298 /* disable VLAN filtering for modes that require it */ 5299 if ((netdev->flags & IFF_PROMISC) || 5300 (netdev->features & NETIF_F_RXALL)) { 5301 /* if we fail to set all rules then just clear VFE */ 5302 if (igb_vlan_promisc_enable(adapter)) 5303 rctl &= ~E1000_RCTL_VFE; 5304 } else { 5305 igb_vlan_promisc_disable(adapter); 5306 } 5307 5308 /* update state of unicast, multicast, and VLAN filtering modes */ 5309 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5310 E1000_RCTL_VFE); 5311 wr32(E1000_RCTL, rctl); 5312 5313 #if (PAGE_SIZE < 8192) 5314 if (!adapter->vfs_allocated_count) { 5315 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5316 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5317 } 5318 #endif 5319 wr32(E1000_RLPML, rlpml); 5320 5321 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5322 * the VMOLR to enable the appropriate modes. Without this workaround 5323 * we will have issues with VLAN tag stripping not being done for frames 5324 * that are only arriving because we are the default pool 5325 */ 5326 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5327 return; 5328 5329 /* set UTA to appropriate mode */ 5330 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5331 5332 vmolr |= rd32(E1000_VMOLR(vfn)) & 5333 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5334 5335 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5336 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5337 #if (PAGE_SIZE < 8192) 5338 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5339 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5340 else 5341 #endif 5342 vmolr |= MAX_JUMBO_FRAME_SIZE; 5343 vmolr |= E1000_VMOLR_LPE; 5344 5345 wr32(E1000_VMOLR(vfn), vmolr); 5346 5347 igb_restore_vf_multicasts(adapter); 5348 } 5349 5350 static void igb_check_wvbr(struct igb_adapter *adapter) 5351 { 5352 struct e1000_hw *hw = &adapter->hw; 5353 u32 wvbr = 0; 5354 5355 switch (hw->mac.type) { 5356 case e1000_82576: 5357 case e1000_i350: 5358 wvbr = rd32(E1000_WVBR); 5359 if (!wvbr) 5360 return; 5361 break; 5362 default: 5363 break; 5364 } 5365 5366 adapter->wvbr |= wvbr; 5367 } 5368 5369 #define IGB_STAGGERED_QUEUE_OFFSET 8 5370 5371 static void igb_spoof_check(struct igb_adapter *adapter) 5372 { 5373 int j; 5374 5375 if (!adapter->wvbr) 5376 return; 5377 5378 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5379 if (adapter->wvbr & BIT(j) || 5380 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5381 dev_warn(&adapter->pdev->dev, 5382 "Spoof event(s) detected on VF %d\n", j); 5383 adapter->wvbr &= 5384 ~(BIT(j) | 5385 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5386 } 5387 } 5388 } 5389 5390 /* Need to wait a few seconds after link up to get diagnostic information from 5391 * the phy 5392 */ 5393 static void igb_update_phy_info(struct timer_list *t) 5394 { 5395 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5396 igb_get_phy_info(&adapter->hw); 5397 } 5398 5399 /** 5400 * igb_has_link - check shared code for link and determine up/down 5401 * @adapter: pointer to driver private info 5402 **/ 5403 bool igb_has_link(struct igb_adapter *adapter) 5404 { 5405 struct e1000_hw *hw = &adapter->hw; 5406 bool link_active = false; 5407 5408 /* get_link_status is set on LSC (link status) interrupt or 5409 * rx sequence error interrupt. get_link_status will stay 5410 * false until the e1000_check_for_link establishes link 5411 * for copper adapters ONLY 5412 */ 5413 switch (hw->phy.media_type) { 5414 case e1000_media_type_copper: 5415 if (!hw->mac.get_link_status) 5416 return true; 5417 fallthrough; 5418 case e1000_media_type_internal_serdes: 5419 hw->mac.ops.check_for_link(hw); 5420 link_active = !hw->mac.get_link_status; 5421 break; 5422 default: 5423 case e1000_media_type_unknown: 5424 break; 5425 } 5426 5427 if (((hw->mac.type == e1000_i210) || 5428 (hw->mac.type == e1000_i211)) && 5429 (hw->phy.id == I210_I_PHY_ID)) { 5430 if (!netif_carrier_ok(adapter->netdev)) { 5431 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5432 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5433 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5434 adapter->link_check_timeout = jiffies; 5435 } 5436 } 5437 5438 return link_active; 5439 } 5440 5441 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5442 { 5443 bool ret = false; 5444 u32 ctrl_ext, thstat; 5445 5446 /* check for thermal sensor event on i350 copper only */ 5447 if (hw->mac.type == e1000_i350) { 5448 thstat = rd32(E1000_THSTAT); 5449 ctrl_ext = rd32(E1000_CTRL_EXT); 5450 5451 if ((hw->phy.media_type == e1000_media_type_copper) && 5452 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5453 ret = !!(thstat & event); 5454 } 5455 5456 return ret; 5457 } 5458 5459 /** 5460 * igb_check_lvmmc - check for malformed packets received 5461 * and indicated in LVMMC register 5462 * @adapter: pointer to adapter 5463 **/ 5464 static void igb_check_lvmmc(struct igb_adapter *adapter) 5465 { 5466 struct e1000_hw *hw = &adapter->hw; 5467 u32 lvmmc; 5468 5469 lvmmc = rd32(E1000_LVMMC); 5470 if (lvmmc) { 5471 if (unlikely(net_ratelimit())) { 5472 netdev_warn(adapter->netdev, 5473 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5474 lvmmc); 5475 } 5476 } 5477 } 5478 5479 /** 5480 * igb_watchdog - Timer Call-back 5481 * @t: pointer to timer_list containing our private info pointer 5482 **/ 5483 static void igb_watchdog(struct timer_list *t) 5484 { 5485 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5486 /* Do the rest outside of interrupt context */ 5487 schedule_work(&adapter->watchdog_task); 5488 } 5489 5490 static void igb_watchdog_task(struct work_struct *work) 5491 { 5492 struct igb_adapter *adapter = container_of(work, 5493 struct igb_adapter, 5494 watchdog_task); 5495 struct e1000_hw *hw = &adapter->hw; 5496 struct e1000_phy_info *phy = &hw->phy; 5497 struct net_device *netdev = adapter->netdev; 5498 u32 link; 5499 int i; 5500 u32 connsw; 5501 u16 phy_data, retry_count = 20; 5502 5503 link = igb_has_link(adapter); 5504 5505 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5506 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5507 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5508 else 5509 link = false; 5510 } 5511 5512 /* Force link down if we have fiber to swap to */ 5513 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5514 if (hw->phy.media_type == e1000_media_type_copper) { 5515 connsw = rd32(E1000_CONNSW); 5516 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5517 link = 0; 5518 } 5519 } 5520 if (link) { 5521 /* Perform a reset if the media type changed. */ 5522 if (hw->dev_spec._82575.media_changed) { 5523 hw->dev_spec._82575.media_changed = false; 5524 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5525 igb_reset(adapter); 5526 } 5527 /* Cancel scheduled suspend requests. */ 5528 pm_runtime_resume(netdev->dev.parent); 5529 5530 if (!netif_carrier_ok(netdev)) { 5531 u32 ctrl; 5532 5533 hw->mac.ops.get_speed_and_duplex(hw, 5534 &adapter->link_speed, 5535 &adapter->link_duplex); 5536 5537 ctrl = rd32(E1000_CTRL); 5538 /* Links status message must follow this format */ 5539 netdev_info(netdev, 5540 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5541 netdev->name, 5542 adapter->link_speed, 5543 adapter->link_duplex == FULL_DUPLEX ? 5544 "Full" : "Half", 5545 (ctrl & E1000_CTRL_TFCE) && 5546 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5547 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5548 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5549 5550 /* disable EEE if enabled */ 5551 if ((adapter->flags & IGB_FLAG_EEE) && 5552 (adapter->link_duplex == HALF_DUPLEX)) { 5553 dev_info(&adapter->pdev->dev, 5554 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5555 adapter->hw.dev_spec._82575.eee_disable = true; 5556 adapter->flags &= ~IGB_FLAG_EEE; 5557 } 5558 5559 /* check if SmartSpeed worked */ 5560 igb_check_downshift(hw); 5561 if (phy->speed_downgraded) 5562 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5563 5564 /* check for thermal sensor event */ 5565 if (igb_thermal_sensor_event(hw, 5566 E1000_THSTAT_LINK_THROTTLE)) 5567 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5568 5569 /* adjust timeout factor according to speed/duplex */ 5570 adapter->tx_timeout_factor = 1; 5571 switch (adapter->link_speed) { 5572 case SPEED_10: 5573 adapter->tx_timeout_factor = 14; 5574 break; 5575 case SPEED_100: 5576 /* maybe add some timeout factor ? */ 5577 break; 5578 } 5579 5580 if (adapter->link_speed != SPEED_1000 || 5581 !hw->phy.ops.read_reg) 5582 goto no_wait; 5583 5584 /* wait for Remote receiver status OK */ 5585 retry_read_status: 5586 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5587 &phy_data)) { 5588 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5589 retry_count) { 5590 msleep(100); 5591 retry_count--; 5592 goto retry_read_status; 5593 } else if (!retry_count) { 5594 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5595 } 5596 } else { 5597 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5598 } 5599 no_wait: 5600 netif_carrier_on(netdev); 5601 5602 igb_ping_all_vfs(adapter); 5603 igb_check_vf_rate_limit(adapter); 5604 5605 /* link state has changed, schedule phy info update */ 5606 if (!test_bit(__IGB_DOWN, &adapter->state)) 5607 mod_timer(&adapter->phy_info_timer, 5608 round_jiffies(jiffies + 2 * HZ)); 5609 } 5610 } else { 5611 if (netif_carrier_ok(netdev)) { 5612 adapter->link_speed = 0; 5613 adapter->link_duplex = 0; 5614 5615 /* check for thermal sensor event */ 5616 if (igb_thermal_sensor_event(hw, 5617 E1000_THSTAT_PWR_DOWN)) { 5618 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5619 } 5620 5621 /* Links status message must follow this format */ 5622 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5623 netdev->name); 5624 netif_carrier_off(netdev); 5625 5626 igb_ping_all_vfs(adapter); 5627 5628 /* link state has changed, schedule phy info update */ 5629 if (!test_bit(__IGB_DOWN, &adapter->state)) 5630 mod_timer(&adapter->phy_info_timer, 5631 round_jiffies(jiffies + 2 * HZ)); 5632 5633 /* link is down, time to check for alternate media */ 5634 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5635 igb_check_swap_media(adapter); 5636 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5637 schedule_work(&adapter->reset_task); 5638 /* return immediately */ 5639 return; 5640 } 5641 } 5642 pm_schedule_suspend(netdev->dev.parent, 5643 MSEC_PER_SEC * 5); 5644 5645 /* also check for alternate media here */ 5646 } else if (!netif_carrier_ok(netdev) && 5647 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5648 igb_check_swap_media(adapter); 5649 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5650 schedule_work(&adapter->reset_task); 5651 /* return immediately */ 5652 return; 5653 } 5654 } 5655 } 5656 5657 spin_lock(&adapter->stats64_lock); 5658 igb_update_stats(adapter); 5659 spin_unlock(&adapter->stats64_lock); 5660 5661 for (i = 0; i < adapter->num_tx_queues; i++) { 5662 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5663 if (!netif_carrier_ok(netdev)) { 5664 /* We've lost link, so the controller stops DMA, 5665 * but we've got queued Tx work that's never going 5666 * to get done, so reset controller to flush Tx. 5667 * (Do the reset outside of interrupt context). 5668 */ 5669 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5670 adapter->tx_timeout_count++; 5671 schedule_work(&adapter->reset_task); 5672 /* return immediately since reset is imminent */ 5673 return; 5674 } 5675 } 5676 5677 /* Force detection of hung controller every watchdog period */ 5678 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5679 } 5680 5681 /* Cause software interrupt to ensure Rx ring is cleaned */ 5682 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5683 u32 eics = 0; 5684 5685 for (i = 0; i < adapter->num_q_vectors; i++) 5686 eics |= adapter->q_vector[i]->eims_value; 5687 wr32(E1000_EICS, eics); 5688 } else { 5689 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5690 } 5691 5692 igb_spoof_check(adapter); 5693 igb_ptp_rx_hang(adapter); 5694 igb_ptp_tx_hang(adapter); 5695 5696 /* Check LVMMC register on i350/i354 only */ 5697 if ((adapter->hw.mac.type == e1000_i350) || 5698 (adapter->hw.mac.type == e1000_i354)) 5699 igb_check_lvmmc(adapter); 5700 5701 /* Reset the timer */ 5702 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5703 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5704 mod_timer(&adapter->watchdog_timer, 5705 round_jiffies(jiffies + HZ)); 5706 else 5707 mod_timer(&adapter->watchdog_timer, 5708 round_jiffies(jiffies + 2 * HZ)); 5709 } 5710 } 5711 5712 enum latency_range { 5713 lowest_latency = 0, 5714 low_latency = 1, 5715 bulk_latency = 2, 5716 latency_invalid = 255 5717 }; 5718 5719 /** 5720 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5721 * @q_vector: pointer to q_vector 5722 * 5723 * Stores a new ITR value based on strictly on packet size. This 5724 * algorithm is less sophisticated than that used in igb_update_itr, 5725 * due to the difficulty of synchronizing statistics across multiple 5726 * receive rings. The divisors and thresholds used by this function 5727 * were determined based on theoretical maximum wire speed and testing 5728 * data, in order to minimize response time while increasing bulk 5729 * throughput. 5730 * This functionality is controlled by ethtool's coalescing settings. 5731 * NOTE: This function is called only when operating in a multiqueue 5732 * receive environment. 5733 **/ 5734 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5735 { 5736 int new_val = q_vector->itr_val; 5737 int avg_wire_size = 0; 5738 struct igb_adapter *adapter = q_vector->adapter; 5739 unsigned int packets; 5740 5741 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5742 * ints/sec - ITR timer value of 120 ticks. 5743 */ 5744 if (adapter->link_speed != SPEED_1000) { 5745 new_val = IGB_4K_ITR; 5746 goto set_itr_val; 5747 } 5748 5749 packets = q_vector->rx.total_packets; 5750 if (packets) 5751 avg_wire_size = q_vector->rx.total_bytes / packets; 5752 5753 packets = q_vector->tx.total_packets; 5754 if (packets) 5755 avg_wire_size = max_t(u32, avg_wire_size, 5756 q_vector->tx.total_bytes / packets); 5757 5758 /* if avg_wire_size isn't set no work was done */ 5759 if (!avg_wire_size) 5760 goto clear_counts; 5761 5762 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5763 avg_wire_size += 24; 5764 5765 /* Don't starve jumbo frames */ 5766 avg_wire_size = min(avg_wire_size, 3000); 5767 5768 /* Give a little boost to mid-size frames */ 5769 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5770 new_val = avg_wire_size / 3; 5771 else 5772 new_val = avg_wire_size / 2; 5773 5774 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5775 if (new_val < IGB_20K_ITR && 5776 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5777 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5778 new_val = IGB_20K_ITR; 5779 5780 set_itr_val: 5781 if (new_val != q_vector->itr_val) { 5782 q_vector->itr_val = new_val; 5783 q_vector->set_itr = 1; 5784 } 5785 clear_counts: 5786 q_vector->rx.total_bytes = 0; 5787 q_vector->rx.total_packets = 0; 5788 q_vector->tx.total_bytes = 0; 5789 q_vector->tx.total_packets = 0; 5790 } 5791 5792 /** 5793 * igb_update_itr - update the dynamic ITR value based on statistics 5794 * @q_vector: pointer to q_vector 5795 * @ring_container: ring info to update the itr for 5796 * 5797 * Stores a new ITR value based on packets and byte 5798 * counts during the last interrupt. The advantage of per interrupt 5799 * computation is faster updates and more accurate ITR for the current 5800 * traffic pattern. Constants in this function were computed 5801 * based on theoretical maximum wire speed and thresholds were set based 5802 * on testing data as well as attempting to minimize response time 5803 * while increasing bulk throughput. 5804 * This functionality is controlled by ethtool's coalescing settings. 5805 * NOTE: These calculations are only valid when operating in a single- 5806 * queue environment. 5807 **/ 5808 static void igb_update_itr(struct igb_q_vector *q_vector, 5809 struct igb_ring_container *ring_container) 5810 { 5811 unsigned int packets = ring_container->total_packets; 5812 unsigned int bytes = ring_container->total_bytes; 5813 u8 itrval = ring_container->itr; 5814 5815 /* no packets, exit with status unchanged */ 5816 if (packets == 0) 5817 return; 5818 5819 switch (itrval) { 5820 case lowest_latency: 5821 /* handle TSO and jumbo frames */ 5822 if (bytes/packets > 8000) 5823 itrval = bulk_latency; 5824 else if ((packets < 5) && (bytes > 512)) 5825 itrval = low_latency; 5826 break; 5827 case low_latency: /* 50 usec aka 20000 ints/s */ 5828 if (bytes > 10000) { 5829 /* this if handles the TSO accounting */ 5830 if (bytes/packets > 8000) 5831 itrval = bulk_latency; 5832 else if ((packets < 10) || ((bytes/packets) > 1200)) 5833 itrval = bulk_latency; 5834 else if ((packets > 35)) 5835 itrval = lowest_latency; 5836 } else if (bytes/packets > 2000) { 5837 itrval = bulk_latency; 5838 } else if (packets <= 2 && bytes < 512) { 5839 itrval = lowest_latency; 5840 } 5841 break; 5842 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5843 if (bytes > 25000) { 5844 if (packets > 35) 5845 itrval = low_latency; 5846 } else if (bytes < 1500) { 5847 itrval = low_latency; 5848 } 5849 break; 5850 } 5851 5852 /* clear work counters since we have the values we need */ 5853 ring_container->total_bytes = 0; 5854 ring_container->total_packets = 0; 5855 5856 /* write updated itr to ring container */ 5857 ring_container->itr = itrval; 5858 } 5859 5860 static void igb_set_itr(struct igb_q_vector *q_vector) 5861 { 5862 struct igb_adapter *adapter = q_vector->adapter; 5863 u32 new_itr = q_vector->itr_val; 5864 u8 current_itr = 0; 5865 5866 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5867 if (adapter->link_speed != SPEED_1000) { 5868 current_itr = 0; 5869 new_itr = IGB_4K_ITR; 5870 goto set_itr_now; 5871 } 5872 5873 igb_update_itr(q_vector, &q_vector->tx); 5874 igb_update_itr(q_vector, &q_vector->rx); 5875 5876 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5877 5878 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5879 if (current_itr == lowest_latency && 5880 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5881 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5882 current_itr = low_latency; 5883 5884 switch (current_itr) { 5885 /* counts and packets in update_itr are dependent on these numbers */ 5886 case lowest_latency: 5887 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5888 break; 5889 case low_latency: 5890 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5891 break; 5892 case bulk_latency: 5893 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5894 break; 5895 default: 5896 break; 5897 } 5898 5899 set_itr_now: 5900 if (new_itr != q_vector->itr_val) { 5901 /* this attempts to bias the interrupt rate towards Bulk 5902 * by adding intermediate steps when interrupt rate is 5903 * increasing 5904 */ 5905 new_itr = new_itr > q_vector->itr_val ? 5906 max((new_itr * q_vector->itr_val) / 5907 (new_itr + (q_vector->itr_val >> 2)), 5908 new_itr) : new_itr; 5909 /* Don't write the value here; it resets the adapter's 5910 * internal timer, and causes us to delay far longer than 5911 * we should between interrupts. Instead, we write the ITR 5912 * value at the beginning of the next interrupt so the timing 5913 * ends up being correct. 5914 */ 5915 q_vector->itr_val = new_itr; 5916 q_vector->set_itr = 1; 5917 } 5918 } 5919 5920 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5921 struct igb_tx_buffer *first, 5922 u32 vlan_macip_lens, u32 type_tucmd, 5923 u32 mss_l4len_idx) 5924 { 5925 struct e1000_adv_tx_context_desc *context_desc; 5926 u16 i = tx_ring->next_to_use; 5927 struct timespec64 ts; 5928 5929 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5930 5931 i++; 5932 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5933 5934 /* set bits to identify this as an advanced context descriptor */ 5935 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5936 5937 /* For 82575, context index must be unique per ring. */ 5938 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5939 mss_l4len_idx |= tx_ring->reg_idx << 4; 5940 5941 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5942 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5943 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5944 5945 /* We assume there is always a valid tx time available. Invalid times 5946 * should have been handled by the upper layers. 5947 */ 5948 if (tx_ring->launchtime_enable) { 5949 ts = ktime_to_timespec64(first->skb->tstamp); 5950 skb_txtime_consumed(first->skb); 5951 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5952 } else { 5953 context_desc->seqnum_seed = 0; 5954 } 5955 } 5956 5957 static int igb_tso(struct igb_ring *tx_ring, 5958 struct igb_tx_buffer *first, 5959 u8 *hdr_len) 5960 { 5961 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5962 struct sk_buff *skb = first->skb; 5963 union { 5964 struct iphdr *v4; 5965 struct ipv6hdr *v6; 5966 unsigned char *hdr; 5967 } ip; 5968 union { 5969 struct tcphdr *tcp; 5970 struct udphdr *udp; 5971 unsigned char *hdr; 5972 } l4; 5973 u32 paylen, l4_offset; 5974 int err; 5975 5976 if (skb->ip_summed != CHECKSUM_PARTIAL) 5977 return 0; 5978 5979 if (!skb_is_gso(skb)) 5980 return 0; 5981 5982 err = skb_cow_head(skb, 0); 5983 if (err < 0) 5984 return err; 5985 5986 ip.hdr = skb_network_header(skb); 5987 l4.hdr = skb_checksum_start(skb); 5988 5989 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5990 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5991 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5992 5993 /* initialize outer IP header fields */ 5994 if (ip.v4->version == 4) { 5995 unsigned char *csum_start = skb_checksum_start(skb); 5996 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5997 5998 /* IP header will have to cancel out any data that 5999 * is not a part of the outer IP header 6000 */ 6001 ip.v4->check = csum_fold(csum_partial(trans_start, 6002 csum_start - trans_start, 6003 0)); 6004 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6005 6006 ip.v4->tot_len = 0; 6007 first->tx_flags |= IGB_TX_FLAGS_TSO | 6008 IGB_TX_FLAGS_CSUM | 6009 IGB_TX_FLAGS_IPV4; 6010 } else { 6011 ip.v6->payload_len = 0; 6012 first->tx_flags |= IGB_TX_FLAGS_TSO | 6013 IGB_TX_FLAGS_CSUM; 6014 } 6015 6016 /* determine offset of inner transport header */ 6017 l4_offset = l4.hdr - skb->data; 6018 6019 /* remove payload length from inner checksum */ 6020 paylen = skb->len - l4_offset; 6021 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6022 /* compute length of segmentation header */ 6023 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6024 csum_replace_by_diff(&l4.tcp->check, 6025 (__force __wsum)htonl(paylen)); 6026 } else { 6027 /* compute length of segmentation header */ 6028 *hdr_len = sizeof(*l4.udp) + l4_offset; 6029 csum_replace_by_diff(&l4.udp->check, 6030 (__force __wsum)htonl(paylen)); 6031 } 6032 6033 /* update gso size and bytecount with header size */ 6034 first->gso_segs = skb_shinfo(skb)->gso_segs; 6035 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6036 6037 /* MSS L4LEN IDX */ 6038 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6039 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6040 6041 /* VLAN MACLEN IPLEN */ 6042 vlan_macip_lens = l4.hdr - ip.hdr; 6043 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6044 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6045 6046 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6047 type_tucmd, mss_l4len_idx); 6048 6049 return 1; 6050 } 6051 6052 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6053 { 6054 struct sk_buff *skb = first->skb; 6055 u32 vlan_macip_lens = 0; 6056 u32 type_tucmd = 0; 6057 6058 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6059 csum_failed: 6060 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6061 !tx_ring->launchtime_enable) 6062 return; 6063 goto no_csum; 6064 } 6065 6066 switch (skb->csum_offset) { 6067 case offsetof(struct tcphdr, check): 6068 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6069 fallthrough; 6070 case offsetof(struct udphdr, check): 6071 break; 6072 case offsetof(struct sctphdr, checksum): 6073 /* validate that this is actually an SCTP request */ 6074 if (skb_csum_is_sctp(skb)) { 6075 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6076 break; 6077 } 6078 fallthrough; 6079 default: 6080 skb_checksum_help(skb); 6081 goto csum_failed; 6082 } 6083 6084 /* update TX checksum flag */ 6085 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6086 vlan_macip_lens = skb_checksum_start_offset(skb) - 6087 skb_network_offset(skb); 6088 no_csum: 6089 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6090 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6091 6092 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6093 } 6094 6095 #define IGB_SET_FLAG(_input, _flag, _result) \ 6096 ((_flag <= _result) ? \ 6097 ((u32)(_input & _flag) * (_result / _flag)) : \ 6098 ((u32)(_input & _flag) / (_flag / _result))) 6099 6100 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6101 { 6102 /* set type for advanced descriptor with frame checksum insertion */ 6103 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6104 E1000_ADVTXD_DCMD_DEXT | 6105 E1000_ADVTXD_DCMD_IFCS; 6106 6107 /* set HW vlan bit if vlan is present */ 6108 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6109 (E1000_ADVTXD_DCMD_VLE)); 6110 6111 /* set segmentation bits for TSO */ 6112 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6113 (E1000_ADVTXD_DCMD_TSE)); 6114 6115 /* set timestamp bit if present */ 6116 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6117 (E1000_ADVTXD_MAC_TSTAMP)); 6118 6119 /* insert frame checksum */ 6120 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6121 6122 return cmd_type; 6123 } 6124 6125 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6126 union e1000_adv_tx_desc *tx_desc, 6127 u32 tx_flags, unsigned int paylen) 6128 { 6129 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6130 6131 /* 82575 requires a unique index per ring */ 6132 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6133 olinfo_status |= tx_ring->reg_idx << 4; 6134 6135 /* insert L4 checksum */ 6136 olinfo_status |= IGB_SET_FLAG(tx_flags, 6137 IGB_TX_FLAGS_CSUM, 6138 (E1000_TXD_POPTS_TXSM << 8)); 6139 6140 /* insert IPv4 checksum */ 6141 olinfo_status |= IGB_SET_FLAG(tx_flags, 6142 IGB_TX_FLAGS_IPV4, 6143 (E1000_TXD_POPTS_IXSM << 8)); 6144 6145 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6146 } 6147 6148 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6149 { 6150 struct net_device *netdev = tx_ring->netdev; 6151 6152 netif_stop_subqueue(netdev, tx_ring->queue_index); 6153 6154 /* Herbert's original patch had: 6155 * smp_mb__after_netif_stop_queue(); 6156 * but since that doesn't exist yet, just open code it. 6157 */ 6158 smp_mb(); 6159 6160 /* We need to check again in a case another CPU has just 6161 * made room available. 6162 */ 6163 if (igb_desc_unused(tx_ring) < size) 6164 return -EBUSY; 6165 6166 /* A reprieve! */ 6167 netif_wake_subqueue(netdev, tx_ring->queue_index); 6168 6169 u64_stats_update_begin(&tx_ring->tx_syncp2); 6170 tx_ring->tx_stats.restart_queue2++; 6171 u64_stats_update_end(&tx_ring->tx_syncp2); 6172 6173 return 0; 6174 } 6175 6176 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6177 { 6178 if (igb_desc_unused(tx_ring) >= size) 6179 return 0; 6180 return __igb_maybe_stop_tx(tx_ring, size); 6181 } 6182 6183 static int igb_tx_map(struct igb_ring *tx_ring, 6184 struct igb_tx_buffer *first, 6185 const u8 hdr_len) 6186 { 6187 struct sk_buff *skb = first->skb; 6188 struct igb_tx_buffer *tx_buffer; 6189 union e1000_adv_tx_desc *tx_desc; 6190 skb_frag_t *frag; 6191 dma_addr_t dma; 6192 unsigned int data_len, size; 6193 u32 tx_flags = first->tx_flags; 6194 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6195 u16 i = tx_ring->next_to_use; 6196 6197 tx_desc = IGB_TX_DESC(tx_ring, i); 6198 6199 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6200 6201 size = skb_headlen(skb); 6202 data_len = skb->data_len; 6203 6204 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6205 6206 tx_buffer = first; 6207 6208 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6209 if (dma_mapping_error(tx_ring->dev, dma)) 6210 goto dma_error; 6211 6212 /* record length, and DMA address */ 6213 dma_unmap_len_set(tx_buffer, len, size); 6214 dma_unmap_addr_set(tx_buffer, dma, dma); 6215 6216 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6217 6218 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6219 tx_desc->read.cmd_type_len = 6220 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6221 6222 i++; 6223 tx_desc++; 6224 if (i == tx_ring->count) { 6225 tx_desc = IGB_TX_DESC(tx_ring, 0); 6226 i = 0; 6227 } 6228 tx_desc->read.olinfo_status = 0; 6229 6230 dma += IGB_MAX_DATA_PER_TXD; 6231 size -= IGB_MAX_DATA_PER_TXD; 6232 6233 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6234 } 6235 6236 if (likely(!data_len)) 6237 break; 6238 6239 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6240 6241 i++; 6242 tx_desc++; 6243 if (i == tx_ring->count) { 6244 tx_desc = IGB_TX_DESC(tx_ring, 0); 6245 i = 0; 6246 } 6247 tx_desc->read.olinfo_status = 0; 6248 6249 size = skb_frag_size(frag); 6250 data_len -= size; 6251 6252 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6253 size, DMA_TO_DEVICE); 6254 6255 tx_buffer = &tx_ring->tx_buffer_info[i]; 6256 } 6257 6258 /* write last descriptor with RS and EOP bits */ 6259 cmd_type |= size | IGB_TXD_DCMD; 6260 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6261 6262 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6263 6264 /* set the timestamp */ 6265 first->time_stamp = jiffies; 6266 6267 skb_tx_timestamp(skb); 6268 6269 /* Force memory writes to complete before letting h/w know there 6270 * are new descriptors to fetch. (Only applicable for weak-ordered 6271 * memory model archs, such as IA-64). 6272 * 6273 * We also need this memory barrier to make certain all of the 6274 * status bits have been updated before next_to_watch is written. 6275 */ 6276 dma_wmb(); 6277 6278 /* set next_to_watch value indicating a packet is present */ 6279 first->next_to_watch = tx_desc; 6280 6281 i++; 6282 if (i == tx_ring->count) 6283 i = 0; 6284 6285 tx_ring->next_to_use = i; 6286 6287 /* Make sure there is space in the ring for the next send. */ 6288 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6289 6290 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6291 writel(i, tx_ring->tail); 6292 } 6293 return 0; 6294 6295 dma_error: 6296 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6297 tx_buffer = &tx_ring->tx_buffer_info[i]; 6298 6299 /* clear dma mappings for failed tx_buffer_info map */ 6300 while (tx_buffer != first) { 6301 if (dma_unmap_len(tx_buffer, len)) 6302 dma_unmap_page(tx_ring->dev, 6303 dma_unmap_addr(tx_buffer, dma), 6304 dma_unmap_len(tx_buffer, len), 6305 DMA_TO_DEVICE); 6306 dma_unmap_len_set(tx_buffer, len, 0); 6307 6308 if (i-- == 0) 6309 i += tx_ring->count; 6310 tx_buffer = &tx_ring->tx_buffer_info[i]; 6311 } 6312 6313 if (dma_unmap_len(tx_buffer, len)) 6314 dma_unmap_single(tx_ring->dev, 6315 dma_unmap_addr(tx_buffer, dma), 6316 dma_unmap_len(tx_buffer, len), 6317 DMA_TO_DEVICE); 6318 dma_unmap_len_set(tx_buffer, len, 0); 6319 6320 dev_kfree_skb_any(tx_buffer->skb); 6321 tx_buffer->skb = NULL; 6322 6323 tx_ring->next_to_use = i; 6324 6325 return -1; 6326 } 6327 6328 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6329 struct igb_ring *tx_ring, 6330 struct xdp_frame *xdpf) 6331 { 6332 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6333 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6334 u16 count, i, index = tx_ring->next_to_use; 6335 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6336 struct igb_tx_buffer *tx_buffer = tx_head; 6337 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6338 u32 len = xdpf->len, cmd_type, olinfo_status; 6339 void *data = xdpf->data; 6340 6341 count = TXD_USE_COUNT(len); 6342 for (i = 0; i < nr_frags; i++) 6343 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6344 6345 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6346 return IGB_XDP_CONSUMED; 6347 6348 i = 0; 6349 /* record the location of the first descriptor for this packet */ 6350 tx_head->bytecount = xdp_get_frame_len(xdpf); 6351 tx_head->type = IGB_TYPE_XDP; 6352 tx_head->gso_segs = 1; 6353 tx_head->xdpf = xdpf; 6354 6355 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6356 /* 82575 requires a unique index per ring */ 6357 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6358 olinfo_status |= tx_ring->reg_idx << 4; 6359 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6360 6361 for (;;) { 6362 dma_addr_t dma; 6363 6364 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6365 if (dma_mapping_error(tx_ring->dev, dma)) 6366 goto unmap; 6367 6368 /* record length, and DMA address */ 6369 dma_unmap_len_set(tx_buffer, len, len); 6370 dma_unmap_addr_set(tx_buffer, dma, dma); 6371 6372 /* put descriptor type bits */ 6373 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6374 E1000_ADVTXD_DCMD_IFCS | len; 6375 6376 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6377 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6378 6379 tx_buffer->protocol = 0; 6380 6381 if (++index == tx_ring->count) 6382 index = 0; 6383 6384 if (i == nr_frags) 6385 break; 6386 6387 tx_buffer = &tx_ring->tx_buffer_info[index]; 6388 tx_desc = IGB_TX_DESC(tx_ring, index); 6389 tx_desc->read.olinfo_status = 0; 6390 6391 data = skb_frag_address(&sinfo->frags[i]); 6392 len = skb_frag_size(&sinfo->frags[i]); 6393 i++; 6394 } 6395 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6396 6397 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6398 /* set the timestamp */ 6399 tx_head->time_stamp = jiffies; 6400 6401 /* Avoid any potential race with xdp_xmit and cleanup */ 6402 smp_wmb(); 6403 6404 /* set next_to_watch value indicating a packet is present */ 6405 tx_head->next_to_watch = tx_desc; 6406 tx_ring->next_to_use = index; 6407 6408 /* Make sure there is space in the ring for the next send. */ 6409 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6410 6411 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6412 writel(index, tx_ring->tail); 6413 6414 return IGB_XDP_TX; 6415 6416 unmap: 6417 for (;;) { 6418 tx_buffer = &tx_ring->tx_buffer_info[index]; 6419 if (dma_unmap_len(tx_buffer, len)) 6420 dma_unmap_page(tx_ring->dev, 6421 dma_unmap_addr(tx_buffer, dma), 6422 dma_unmap_len(tx_buffer, len), 6423 DMA_TO_DEVICE); 6424 dma_unmap_len_set(tx_buffer, len, 0); 6425 if (tx_buffer == tx_head) 6426 break; 6427 6428 if (!index) 6429 index += tx_ring->count; 6430 index--; 6431 } 6432 6433 return IGB_XDP_CONSUMED; 6434 } 6435 6436 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6437 struct igb_ring *tx_ring) 6438 { 6439 struct igb_tx_buffer *first; 6440 int tso; 6441 u32 tx_flags = 0; 6442 unsigned short f; 6443 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6444 __be16 protocol = vlan_get_protocol(skb); 6445 u8 hdr_len = 0; 6446 6447 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6448 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6449 * + 2 desc gap to keep tail from touching head, 6450 * + 1 desc for context descriptor, 6451 * otherwise try next time 6452 */ 6453 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6454 count += TXD_USE_COUNT(skb_frag_size( 6455 &skb_shinfo(skb)->frags[f])); 6456 6457 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6458 /* this is a hard error */ 6459 return NETDEV_TX_BUSY; 6460 } 6461 6462 /* record the location of the first descriptor for this packet */ 6463 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6464 first->type = IGB_TYPE_SKB; 6465 first->skb = skb; 6466 first->bytecount = skb->len; 6467 first->gso_segs = 1; 6468 6469 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6470 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6471 6472 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6473 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6474 &adapter->state)) { 6475 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6476 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6477 6478 adapter->ptp_tx_skb = skb_get(skb); 6479 adapter->ptp_tx_start = jiffies; 6480 if (adapter->hw.mac.type == e1000_82576) 6481 schedule_work(&adapter->ptp_tx_work); 6482 } else { 6483 adapter->tx_hwtstamp_skipped++; 6484 } 6485 } 6486 6487 if (skb_vlan_tag_present(skb)) { 6488 tx_flags |= IGB_TX_FLAGS_VLAN; 6489 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6490 } 6491 6492 /* record initial flags and protocol */ 6493 first->tx_flags = tx_flags; 6494 first->protocol = protocol; 6495 6496 tso = igb_tso(tx_ring, first, &hdr_len); 6497 if (tso < 0) 6498 goto out_drop; 6499 else if (!tso) 6500 igb_tx_csum(tx_ring, first); 6501 6502 if (igb_tx_map(tx_ring, first, hdr_len)) 6503 goto cleanup_tx_tstamp; 6504 6505 return NETDEV_TX_OK; 6506 6507 out_drop: 6508 dev_kfree_skb_any(first->skb); 6509 first->skb = NULL; 6510 cleanup_tx_tstamp: 6511 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6512 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6513 6514 dev_kfree_skb_any(adapter->ptp_tx_skb); 6515 adapter->ptp_tx_skb = NULL; 6516 if (adapter->hw.mac.type == e1000_82576) 6517 cancel_work_sync(&adapter->ptp_tx_work); 6518 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6519 } 6520 6521 return NETDEV_TX_OK; 6522 } 6523 6524 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6525 struct sk_buff *skb) 6526 { 6527 unsigned int r_idx = skb->queue_mapping; 6528 6529 if (r_idx >= adapter->num_tx_queues) 6530 r_idx = r_idx % adapter->num_tx_queues; 6531 6532 return adapter->tx_ring[r_idx]; 6533 } 6534 6535 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6536 struct net_device *netdev) 6537 { 6538 struct igb_adapter *adapter = netdev_priv(netdev); 6539 6540 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6541 * in order to meet this minimum size requirement. 6542 */ 6543 if (skb_put_padto(skb, 17)) 6544 return NETDEV_TX_OK; 6545 6546 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6547 } 6548 6549 /** 6550 * igb_tx_timeout - Respond to a Tx Hang 6551 * @netdev: network interface device structure 6552 * @txqueue: number of the Tx queue that hung (unused) 6553 **/ 6554 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6555 { 6556 struct igb_adapter *adapter = netdev_priv(netdev); 6557 struct e1000_hw *hw = &adapter->hw; 6558 6559 /* Do the reset outside of interrupt context */ 6560 adapter->tx_timeout_count++; 6561 6562 if (hw->mac.type >= e1000_82580) 6563 hw->dev_spec._82575.global_device_reset = true; 6564 6565 schedule_work(&adapter->reset_task); 6566 wr32(E1000_EICS, 6567 (adapter->eims_enable_mask & ~adapter->eims_other)); 6568 } 6569 6570 static void igb_reset_task(struct work_struct *work) 6571 { 6572 struct igb_adapter *adapter; 6573 adapter = container_of(work, struct igb_adapter, reset_task); 6574 6575 rtnl_lock(); 6576 /* If we're already down or resetting, just bail */ 6577 if (test_bit(__IGB_DOWN, &adapter->state) || 6578 test_bit(__IGB_RESETTING, &adapter->state)) { 6579 rtnl_unlock(); 6580 return; 6581 } 6582 6583 igb_dump(adapter); 6584 netdev_err(adapter->netdev, "Reset adapter\n"); 6585 igb_reinit_locked(adapter); 6586 rtnl_unlock(); 6587 } 6588 6589 /** 6590 * igb_get_stats64 - Get System Network Statistics 6591 * @netdev: network interface device structure 6592 * @stats: rtnl_link_stats64 pointer 6593 **/ 6594 static void igb_get_stats64(struct net_device *netdev, 6595 struct rtnl_link_stats64 *stats) 6596 { 6597 struct igb_adapter *adapter = netdev_priv(netdev); 6598 6599 spin_lock(&adapter->stats64_lock); 6600 igb_update_stats(adapter); 6601 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6602 spin_unlock(&adapter->stats64_lock); 6603 } 6604 6605 /** 6606 * igb_change_mtu - Change the Maximum Transfer Unit 6607 * @netdev: network interface device structure 6608 * @new_mtu: new value for maximum frame size 6609 * 6610 * Returns 0 on success, negative on failure 6611 **/ 6612 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6613 { 6614 struct igb_adapter *adapter = netdev_priv(netdev); 6615 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6616 6617 if (adapter->xdp_prog) { 6618 int i; 6619 6620 for (i = 0; i < adapter->num_rx_queues; i++) { 6621 struct igb_ring *ring = adapter->rx_ring[i]; 6622 6623 if (max_frame > igb_rx_bufsz(ring)) { 6624 netdev_warn(adapter->netdev, 6625 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6626 max_frame); 6627 return -EINVAL; 6628 } 6629 } 6630 } 6631 6632 /* adjust max frame to be at least the size of a standard frame */ 6633 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6634 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6635 6636 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6637 usleep_range(1000, 2000); 6638 6639 /* igb_down has a dependency on max_frame_size */ 6640 adapter->max_frame_size = max_frame; 6641 6642 if (netif_running(netdev)) 6643 igb_down(adapter); 6644 6645 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6646 netdev->mtu, new_mtu); 6647 WRITE_ONCE(netdev->mtu, new_mtu); 6648 6649 if (netif_running(netdev)) 6650 igb_up(adapter); 6651 else 6652 igb_reset(adapter); 6653 6654 clear_bit(__IGB_RESETTING, &adapter->state); 6655 6656 return 0; 6657 } 6658 6659 /** 6660 * igb_update_stats - Update the board statistics counters 6661 * @adapter: board private structure 6662 **/ 6663 void igb_update_stats(struct igb_adapter *adapter) 6664 { 6665 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6666 struct e1000_hw *hw = &adapter->hw; 6667 struct pci_dev *pdev = adapter->pdev; 6668 u32 reg, mpc; 6669 int i; 6670 u64 bytes, packets; 6671 unsigned int start; 6672 u64 _bytes, _packets; 6673 6674 /* Prevent stats update while adapter is being reset, or if the pci 6675 * connection is down. 6676 */ 6677 if (adapter->link_speed == 0) 6678 return; 6679 if (pci_channel_offline(pdev)) 6680 return; 6681 6682 bytes = 0; 6683 packets = 0; 6684 6685 rcu_read_lock(); 6686 for (i = 0; i < adapter->num_rx_queues; i++) { 6687 struct igb_ring *ring = adapter->rx_ring[i]; 6688 u32 rqdpc = rd32(E1000_RQDPC(i)); 6689 if (hw->mac.type >= e1000_i210) 6690 wr32(E1000_RQDPC(i), 0); 6691 6692 if (rqdpc) { 6693 ring->rx_stats.drops += rqdpc; 6694 net_stats->rx_fifo_errors += rqdpc; 6695 } 6696 6697 do { 6698 start = u64_stats_fetch_begin(&ring->rx_syncp); 6699 _bytes = ring->rx_stats.bytes; 6700 _packets = ring->rx_stats.packets; 6701 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6702 bytes += _bytes; 6703 packets += _packets; 6704 } 6705 6706 net_stats->rx_bytes = bytes; 6707 net_stats->rx_packets = packets; 6708 6709 bytes = 0; 6710 packets = 0; 6711 for (i = 0; i < adapter->num_tx_queues; i++) { 6712 struct igb_ring *ring = adapter->tx_ring[i]; 6713 do { 6714 start = u64_stats_fetch_begin(&ring->tx_syncp); 6715 _bytes = ring->tx_stats.bytes; 6716 _packets = ring->tx_stats.packets; 6717 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6718 bytes += _bytes; 6719 packets += _packets; 6720 } 6721 net_stats->tx_bytes = bytes; 6722 net_stats->tx_packets = packets; 6723 rcu_read_unlock(); 6724 6725 /* read stats registers */ 6726 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6727 adapter->stats.gprc += rd32(E1000_GPRC); 6728 adapter->stats.gorc += rd32(E1000_GORCL); 6729 rd32(E1000_GORCH); /* clear GORCL */ 6730 adapter->stats.bprc += rd32(E1000_BPRC); 6731 adapter->stats.mprc += rd32(E1000_MPRC); 6732 adapter->stats.roc += rd32(E1000_ROC); 6733 6734 adapter->stats.prc64 += rd32(E1000_PRC64); 6735 adapter->stats.prc127 += rd32(E1000_PRC127); 6736 adapter->stats.prc255 += rd32(E1000_PRC255); 6737 adapter->stats.prc511 += rd32(E1000_PRC511); 6738 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6739 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6740 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6741 adapter->stats.sec += rd32(E1000_SEC); 6742 6743 mpc = rd32(E1000_MPC); 6744 adapter->stats.mpc += mpc; 6745 net_stats->rx_fifo_errors += mpc; 6746 adapter->stats.scc += rd32(E1000_SCC); 6747 adapter->stats.ecol += rd32(E1000_ECOL); 6748 adapter->stats.mcc += rd32(E1000_MCC); 6749 adapter->stats.latecol += rd32(E1000_LATECOL); 6750 adapter->stats.dc += rd32(E1000_DC); 6751 adapter->stats.rlec += rd32(E1000_RLEC); 6752 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6753 adapter->stats.xontxc += rd32(E1000_XONTXC); 6754 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6755 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6756 adapter->stats.fcruc += rd32(E1000_FCRUC); 6757 adapter->stats.gptc += rd32(E1000_GPTC); 6758 adapter->stats.gotc += rd32(E1000_GOTCL); 6759 rd32(E1000_GOTCH); /* clear GOTCL */ 6760 adapter->stats.rnbc += rd32(E1000_RNBC); 6761 adapter->stats.ruc += rd32(E1000_RUC); 6762 adapter->stats.rfc += rd32(E1000_RFC); 6763 adapter->stats.rjc += rd32(E1000_RJC); 6764 adapter->stats.tor += rd32(E1000_TORH); 6765 adapter->stats.tot += rd32(E1000_TOTH); 6766 adapter->stats.tpr += rd32(E1000_TPR); 6767 6768 adapter->stats.ptc64 += rd32(E1000_PTC64); 6769 adapter->stats.ptc127 += rd32(E1000_PTC127); 6770 adapter->stats.ptc255 += rd32(E1000_PTC255); 6771 adapter->stats.ptc511 += rd32(E1000_PTC511); 6772 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6773 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6774 6775 adapter->stats.mptc += rd32(E1000_MPTC); 6776 adapter->stats.bptc += rd32(E1000_BPTC); 6777 6778 adapter->stats.tpt += rd32(E1000_TPT); 6779 adapter->stats.colc += rd32(E1000_COLC); 6780 6781 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6782 /* read internal phy specific stats */ 6783 reg = rd32(E1000_CTRL_EXT); 6784 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6785 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6786 6787 /* this stat has invalid values on i210/i211 */ 6788 if ((hw->mac.type != e1000_i210) && 6789 (hw->mac.type != e1000_i211)) 6790 adapter->stats.tncrs += rd32(E1000_TNCRS); 6791 } 6792 6793 adapter->stats.tsctc += rd32(E1000_TSCTC); 6794 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6795 6796 adapter->stats.iac += rd32(E1000_IAC); 6797 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6798 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6799 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6800 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6801 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6802 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6803 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6804 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6805 6806 /* Fill out the OS statistics structure */ 6807 net_stats->multicast = adapter->stats.mprc; 6808 net_stats->collisions = adapter->stats.colc; 6809 6810 /* Rx Errors */ 6811 6812 /* RLEC on some newer hardware can be incorrect so build 6813 * our own version based on RUC and ROC 6814 */ 6815 net_stats->rx_errors = adapter->stats.rxerrc + 6816 adapter->stats.crcerrs + adapter->stats.algnerrc + 6817 adapter->stats.ruc + adapter->stats.roc + 6818 adapter->stats.cexterr; 6819 net_stats->rx_length_errors = adapter->stats.ruc + 6820 adapter->stats.roc; 6821 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6822 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6823 net_stats->rx_missed_errors = adapter->stats.mpc; 6824 6825 /* Tx Errors */ 6826 net_stats->tx_errors = adapter->stats.ecol + 6827 adapter->stats.latecol; 6828 net_stats->tx_aborted_errors = adapter->stats.ecol; 6829 net_stats->tx_window_errors = adapter->stats.latecol; 6830 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6831 6832 /* Tx Dropped needs to be maintained elsewhere */ 6833 6834 /* Management Stats */ 6835 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6836 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6837 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6838 6839 /* OS2BMC Stats */ 6840 reg = rd32(E1000_MANC); 6841 if (reg & E1000_MANC_EN_BMC2OS) { 6842 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6843 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6844 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6845 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6846 } 6847 } 6848 6849 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6850 { 6851 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6852 struct e1000_hw *hw = &adapter->hw; 6853 struct timespec64 ts; 6854 u32 tsauxc; 6855 6856 if (pin < 0 || pin >= IGB_N_SDP) 6857 return; 6858 6859 spin_lock(&adapter->tmreg_lock); 6860 6861 if (hw->mac.type == e1000_82580 || 6862 hw->mac.type == e1000_i354 || 6863 hw->mac.type == e1000_i350) { 6864 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6865 u32 systiml, systimh, level_mask, level, rem; 6866 u64 systim, now; 6867 6868 /* read systim registers in sequence */ 6869 rd32(E1000_SYSTIMR); 6870 systiml = rd32(E1000_SYSTIML); 6871 systimh = rd32(E1000_SYSTIMH); 6872 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6873 now = timecounter_cyc2time(&adapter->tc, systim); 6874 6875 if (pin < 2) { 6876 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6877 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6878 } else { 6879 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6880 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6881 } 6882 6883 div_u64_rem(now, ns, &rem); 6884 systim = systim + (ns - rem); 6885 6886 /* synchronize pin level with rising/falling edges */ 6887 div_u64_rem(now, ns << 1, &rem); 6888 if (rem < ns) { 6889 /* first half of period */ 6890 if (level == 0) { 6891 /* output is already low, skip this period */ 6892 systim += ns; 6893 pr_notice("igb: periodic output on %s missed falling edge\n", 6894 adapter->sdp_config[pin].name); 6895 } 6896 } else { 6897 /* second half of period */ 6898 if (level == 1) { 6899 /* output is already high, skip this period */ 6900 systim += ns; 6901 pr_notice("igb: periodic output on %s missed rising edge\n", 6902 adapter->sdp_config[pin].name); 6903 } 6904 } 6905 6906 /* for this chip family tv_sec is the upper part of the binary value, 6907 * so not seconds 6908 */ 6909 ts.tv_nsec = (u32)systim; 6910 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6911 } else { 6912 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6913 adapter->perout[tsintr_tt].period); 6914 } 6915 6916 /* u32 conversion of tv_sec is safe until y2106 */ 6917 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6918 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6919 tsauxc = rd32(E1000_TSAUXC); 6920 tsauxc |= TSAUXC_EN_TT0; 6921 wr32(E1000_TSAUXC, tsauxc); 6922 adapter->perout[tsintr_tt].start = ts; 6923 6924 spin_unlock(&adapter->tmreg_lock); 6925 } 6926 6927 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6928 { 6929 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6930 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6931 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6932 struct e1000_hw *hw = &adapter->hw; 6933 struct ptp_clock_event event; 6934 struct timespec64 ts; 6935 unsigned long flags; 6936 6937 if (pin < 0 || pin >= IGB_N_SDP) 6938 return; 6939 6940 if (hw->mac.type == e1000_82580 || 6941 hw->mac.type == e1000_i354 || 6942 hw->mac.type == e1000_i350) { 6943 u64 ns = rd32(auxstmpl); 6944 6945 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 6946 spin_lock_irqsave(&adapter->tmreg_lock, flags); 6947 ns = timecounter_cyc2time(&adapter->tc, ns); 6948 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 6949 ts = ns_to_timespec64(ns); 6950 } else { 6951 ts.tv_nsec = rd32(auxstmpl); 6952 ts.tv_sec = rd32(auxstmph); 6953 } 6954 6955 event.type = PTP_CLOCK_EXTTS; 6956 event.index = tsintr_tt; 6957 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6958 ptp_clock_event(adapter->ptp_clock, &event); 6959 } 6960 6961 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6962 { 6963 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 6964 TSINTR_TT0 | TSINTR_TT1 | 6965 TSINTR_AUTT0 | TSINTR_AUTT1); 6966 struct e1000_hw *hw = &adapter->hw; 6967 u32 tsicr = rd32(E1000_TSICR); 6968 struct ptp_clock_event event; 6969 6970 if (hw->mac.type == e1000_82580) { 6971 /* 82580 has a hardware bug that requires an explicit 6972 * write to clear the TimeSync interrupt cause. 6973 */ 6974 wr32(E1000_TSICR, tsicr & mask); 6975 } 6976 6977 if (tsicr & TSINTR_SYS_WRAP) { 6978 event.type = PTP_CLOCK_PPS; 6979 if (adapter->ptp_caps.pps) 6980 ptp_clock_event(adapter->ptp_clock, &event); 6981 } 6982 6983 if (tsicr & E1000_TSICR_TXTS) { 6984 /* retrieve hardware timestamp */ 6985 schedule_work(&adapter->ptp_tx_work); 6986 } 6987 6988 if (tsicr & TSINTR_TT0) 6989 igb_perout(adapter, 0); 6990 6991 if (tsicr & TSINTR_TT1) 6992 igb_perout(adapter, 1); 6993 6994 if (tsicr & TSINTR_AUTT0) 6995 igb_extts(adapter, 0); 6996 6997 if (tsicr & TSINTR_AUTT1) 6998 igb_extts(adapter, 1); 6999 } 7000 7001 static irqreturn_t igb_msix_other(int irq, void *data) 7002 { 7003 struct igb_adapter *adapter = data; 7004 struct e1000_hw *hw = &adapter->hw; 7005 u32 icr = rd32(E1000_ICR); 7006 /* reading ICR causes bit 31 of EICR to be cleared */ 7007 7008 if (icr & E1000_ICR_DRSTA) 7009 schedule_work(&adapter->reset_task); 7010 7011 if (icr & E1000_ICR_DOUTSYNC) { 7012 /* HW is reporting DMA is out of sync */ 7013 adapter->stats.doosync++; 7014 /* The DMA Out of Sync is also indication of a spoof event 7015 * in IOV mode. Check the Wrong VM Behavior register to 7016 * see if it is really a spoof event. 7017 */ 7018 igb_check_wvbr(adapter); 7019 } 7020 7021 /* Check for a mailbox event */ 7022 if (icr & E1000_ICR_VMMB) 7023 igb_msg_task(adapter); 7024 7025 if (icr & E1000_ICR_LSC) { 7026 hw->mac.get_link_status = 1; 7027 /* guard against interrupt when we're going down */ 7028 if (!test_bit(__IGB_DOWN, &adapter->state)) 7029 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7030 } 7031 7032 if (icr & E1000_ICR_TS) 7033 igb_tsync_interrupt(adapter); 7034 7035 wr32(E1000_EIMS, adapter->eims_other); 7036 7037 return IRQ_HANDLED; 7038 } 7039 7040 static void igb_write_itr(struct igb_q_vector *q_vector) 7041 { 7042 struct igb_adapter *adapter = q_vector->adapter; 7043 u32 itr_val = q_vector->itr_val & 0x7FFC; 7044 7045 if (!q_vector->set_itr) 7046 return; 7047 7048 if (!itr_val) 7049 itr_val = 0x4; 7050 7051 if (adapter->hw.mac.type == e1000_82575) 7052 itr_val |= itr_val << 16; 7053 else 7054 itr_val |= E1000_EITR_CNT_IGNR; 7055 7056 writel(itr_val, q_vector->itr_register); 7057 q_vector->set_itr = 0; 7058 } 7059 7060 static irqreturn_t igb_msix_ring(int irq, void *data) 7061 { 7062 struct igb_q_vector *q_vector = data; 7063 7064 /* Write the ITR value calculated from the previous interrupt. */ 7065 igb_write_itr(q_vector); 7066 7067 napi_schedule(&q_vector->napi); 7068 7069 return IRQ_HANDLED; 7070 } 7071 7072 #ifdef CONFIG_IGB_DCA 7073 static void igb_update_tx_dca(struct igb_adapter *adapter, 7074 struct igb_ring *tx_ring, 7075 int cpu) 7076 { 7077 struct e1000_hw *hw = &adapter->hw; 7078 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7079 7080 if (hw->mac.type != e1000_82575) 7081 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7082 7083 /* We can enable relaxed ordering for reads, but not writes when 7084 * DCA is enabled. This is due to a known issue in some chipsets 7085 * which will cause the DCA tag to be cleared. 7086 */ 7087 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7088 E1000_DCA_TXCTRL_DATA_RRO_EN | 7089 E1000_DCA_TXCTRL_DESC_DCA_EN; 7090 7091 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7092 } 7093 7094 static void igb_update_rx_dca(struct igb_adapter *adapter, 7095 struct igb_ring *rx_ring, 7096 int cpu) 7097 { 7098 struct e1000_hw *hw = &adapter->hw; 7099 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7100 7101 if (hw->mac.type != e1000_82575) 7102 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7103 7104 /* We can enable relaxed ordering for reads, but not writes when 7105 * DCA is enabled. This is due to a known issue in some chipsets 7106 * which will cause the DCA tag to be cleared. 7107 */ 7108 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7109 E1000_DCA_RXCTRL_DESC_DCA_EN; 7110 7111 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7112 } 7113 7114 static void igb_update_dca(struct igb_q_vector *q_vector) 7115 { 7116 struct igb_adapter *adapter = q_vector->adapter; 7117 int cpu = get_cpu(); 7118 7119 if (q_vector->cpu == cpu) 7120 goto out_no_update; 7121 7122 if (q_vector->tx.ring) 7123 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7124 7125 if (q_vector->rx.ring) 7126 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7127 7128 q_vector->cpu = cpu; 7129 out_no_update: 7130 put_cpu(); 7131 } 7132 7133 static void igb_setup_dca(struct igb_adapter *adapter) 7134 { 7135 struct e1000_hw *hw = &adapter->hw; 7136 int i; 7137 7138 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7139 return; 7140 7141 /* Always use CB2 mode, difference is masked in the CB driver. */ 7142 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7143 7144 for (i = 0; i < adapter->num_q_vectors; i++) { 7145 adapter->q_vector[i]->cpu = -1; 7146 igb_update_dca(adapter->q_vector[i]); 7147 } 7148 } 7149 7150 static int __igb_notify_dca(struct device *dev, void *data) 7151 { 7152 struct net_device *netdev = dev_get_drvdata(dev); 7153 struct igb_adapter *adapter = netdev_priv(netdev); 7154 struct pci_dev *pdev = adapter->pdev; 7155 struct e1000_hw *hw = &adapter->hw; 7156 unsigned long event = *(unsigned long *)data; 7157 7158 switch (event) { 7159 case DCA_PROVIDER_ADD: 7160 /* if already enabled, don't do it again */ 7161 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7162 break; 7163 if (dca_add_requester(dev) == 0) { 7164 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7165 dev_info(&pdev->dev, "DCA enabled\n"); 7166 igb_setup_dca(adapter); 7167 break; 7168 } 7169 fallthrough; /* since DCA is disabled. */ 7170 case DCA_PROVIDER_REMOVE: 7171 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7172 /* without this a class_device is left 7173 * hanging around in the sysfs model 7174 */ 7175 dca_remove_requester(dev); 7176 dev_info(&pdev->dev, "DCA disabled\n"); 7177 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7178 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7179 } 7180 break; 7181 } 7182 7183 return 0; 7184 } 7185 7186 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7187 void *p) 7188 { 7189 int ret_val; 7190 7191 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7192 __igb_notify_dca); 7193 7194 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7195 } 7196 #endif /* CONFIG_IGB_DCA */ 7197 7198 #ifdef CONFIG_PCI_IOV 7199 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7200 { 7201 unsigned char mac_addr[ETH_ALEN]; 7202 7203 eth_zero_addr(mac_addr); 7204 igb_set_vf_mac(adapter, vf, mac_addr); 7205 7206 /* By default spoof check is enabled for all VFs */ 7207 adapter->vf_data[vf].spoofchk_enabled = true; 7208 7209 /* By default VFs are not trusted */ 7210 adapter->vf_data[vf].trusted = false; 7211 7212 return 0; 7213 } 7214 7215 #endif 7216 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7217 { 7218 struct e1000_hw *hw = &adapter->hw; 7219 u32 ping; 7220 int i; 7221 7222 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7223 ping = E1000_PF_CONTROL_MSG; 7224 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7225 ping |= E1000_VT_MSGTYPE_CTS; 7226 igb_write_mbx(hw, &ping, 1, i); 7227 } 7228 } 7229 7230 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7231 { 7232 struct e1000_hw *hw = &adapter->hw; 7233 u32 vmolr = rd32(E1000_VMOLR(vf)); 7234 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7235 7236 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7237 IGB_VF_FLAG_MULTI_PROMISC); 7238 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7239 7240 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7241 vmolr |= E1000_VMOLR_MPME; 7242 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7243 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7244 } else { 7245 /* if we have hashes and we are clearing a multicast promisc 7246 * flag we need to write the hashes to the MTA as this step 7247 * was previously skipped 7248 */ 7249 if (vf_data->num_vf_mc_hashes > 30) { 7250 vmolr |= E1000_VMOLR_MPME; 7251 } else if (vf_data->num_vf_mc_hashes) { 7252 int j; 7253 7254 vmolr |= E1000_VMOLR_ROMPE; 7255 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7256 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7257 } 7258 } 7259 7260 wr32(E1000_VMOLR(vf), vmolr); 7261 7262 /* there are flags left unprocessed, likely not supported */ 7263 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7264 return -EINVAL; 7265 7266 return 0; 7267 } 7268 7269 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7270 u32 *msgbuf, u32 vf) 7271 { 7272 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7273 u16 *hash_list = (u16 *)&msgbuf[1]; 7274 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7275 int i; 7276 7277 /* salt away the number of multicast addresses assigned 7278 * to this VF for later use to restore when the PF multi cast 7279 * list changes 7280 */ 7281 vf_data->num_vf_mc_hashes = n; 7282 7283 /* only up to 30 hash values supported */ 7284 if (n > 30) 7285 n = 30; 7286 7287 /* store the hashes for later use */ 7288 for (i = 0; i < n; i++) 7289 vf_data->vf_mc_hashes[i] = hash_list[i]; 7290 7291 /* Flush and reset the mta with the new values */ 7292 igb_set_rx_mode(adapter->netdev); 7293 7294 return 0; 7295 } 7296 7297 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7298 { 7299 struct e1000_hw *hw = &adapter->hw; 7300 struct vf_data_storage *vf_data; 7301 int i, j; 7302 7303 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7304 u32 vmolr = rd32(E1000_VMOLR(i)); 7305 7306 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7307 7308 vf_data = &adapter->vf_data[i]; 7309 7310 if ((vf_data->num_vf_mc_hashes > 30) || 7311 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7312 vmolr |= E1000_VMOLR_MPME; 7313 } else if (vf_data->num_vf_mc_hashes) { 7314 vmolr |= E1000_VMOLR_ROMPE; 7315 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7316 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7317 } 7318 wr32(E1000_VMOLR(i), vmolr); 7319 } 7320 } 7321 7322 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7323 { 7324 struct e1000_hw *hw = &adapter->hw; 7325 u32 pool_mask, vlvf_mask, i; 7326 7327 /* create mask for VF and other pools */ 7328 pool_mask = E1000_VLVF_POOLSEL_MASK; 7329 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7330 7331 /* drop PF from pool bits */ 7332 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7333 adapter->vfs_allocated_count); 7334 7335 /* Find the vlan filter for this id */ 7336 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7337 u32 vlvf = rd32(E1000_VLVF(i)); 7338 u32 vfta_mask, vid, vfta; 7339 7340 /* remove the vf from the pool */ 7341 if (!(vlvf & vlvf_mask)) 7342 continue; 7343 7344 /* clear out bit from VLVF */ 7345 vlvf ^= vlvf_mask; 7346 7347 /* if other pools are present, just remove ourselves */ 7348 if (vlvf & pool_mask) 7349 goto update_vlvfb; 7350 7351 /* if PF is present, leave VFTA */ 7352 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7353 goto update_vlvf; 7354 7355 vid = vlvf & E1000_VLVF_VLANID_MASK; 7356 vfta_mask = BIT(vid % 32); 7357 7358 /* clear bit from VFTA */ 7359 vfta = adapter->shadow_vfta[vid / 32]; 7360 if (vfta & vfta_mask) 7361 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7362 update_vlvf: 7363 /* clear pool selection enable */ 7364 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7365 vlvf &= E1000_VLVF_POOLSEL_MASK; 7366 else 7367 vlvf = 0; 7368 update_vlvfb: 7369 /* clear pool bits */ 7370 wr32(E1000_VLVF(i), vlvf); 7371 } 7372 } 7373 7374 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7375 { 7376 u32 vlvf; 7377 int idx; 7378 7379 /* short cut the special case */ 7380 if (vlan == 0) 7381 return 0; 7382 7383 /* Search for the VLAN id in the VLVF entries */ 7384 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7385 vlvf = rd32(E1000_VLVF(idx)); 7386 if ((vlvf & VLAN_VID_MASK) == vlan) 7387 break; 7388 } 7389 7390 return idx; 7391 } 7392 7393 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7394 { 7395 struct e1000_hw *hw = &adapter->hw; 7396 u32 bits, pf_id; 7397 int idx; 7398 7399 idx = igb_find_vlvf_entry(hw, vid); 7400 if (!idx) 7401 return; 7402 7403 /* See if any other pools are set for this VLAN filter 7404 * entry other than the PF. 7405 */ 7406 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7407 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7408 bits &= rd32(E1000_VLVF(idx)); 7409 7410 /* Disable the filter so this falls into the default pool. */ 7411 if (!bits) { 7412 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7413 wr32(E1000_VLVF(idx), BIT(pf_id)); 7414 else 7415 wr32(E1000_VLVF(idx), 0); 7416 } 7417 } 7418 7419 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7420 bool add, u32 vf) 7421 { 7422 int pf_id = adapter->vfs_allocated_count; 7423 struct e1000_hw *hw = &adapter->hw; 7424 int err; 7425 7426 /* If VLAN overlaps with one the PF is currently monitoring make 7427 * sure that we are able to allocate a VLVF entry. This may be 7428 * redundant but it guarantees PF will maintain visibility to 7429 * the VLAN. 7430 */ 7431 if (add && test_bit(vid, adapter->active_vlans)) { 7432 err = igb_vfta_set(hw, vid, pf_id, true, false); 7433 if (err) 7434 return err; 7435 } 7436 7437 err = igb_vfta_set(hw, vid, vf, add, false); 7438 7439 if (add && !err) 7440 return err; 7441 7442 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7443 * we may need to drop the PF pool bit in order to allow us to free 7444 * up the VLVF resources. 7445 */ 7446 if (test_bit(vid, adapter->active_vlans) || 7447 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7448 igb_update_pf_vlvf(adapter, vid); 7449 7450 return err; 7451 } 7452 7453 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7454 { 7455 struct e1000_hw *hw = &adapter->hw; 7456 7457 if (vid) 7458 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7459 else 7460 wr32(E1000_VMVIR(vf), 0); 7461 } 7462 7463 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7464 u16 vlan, u8 qos) 7465 { 7466 int err; 7467 7468 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7469 if (err) 7470 return err; 7471 7472 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7473 igb_set_vmolr(adapter, vf, !vlan); 7474 7475 /* revoke access to previous VLAN */ 7476 if (vlan != adapter->vf_data[vf].pf_vlan) 7477 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7478 false, vf); 7479 7480 adapter->vf_data[vf].pf_vlan = vlan; 7481 adapter->vf_data[vf].pf_qos = qos; 7482 igb_set_vf_vlan_strip(adapter, vf, true); 7483 dev_info(&adapter->pdev->dev, 7484 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7485 if (test_bit(__IGB_DOWN, &adapter->state)) { 7486 dev_warn(&adapter->pdev->dev, 7487 "The VF VLAN has been set, but the PF device is not up.\n"); 7488 dev_warn(&adapter->pdev->dev, 7489 "Bring the PF device up before attempting to use the VF device.\n"); 7490 } 7491 7492 return err; 7493 } 7494 7495 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7496 { 7497 /* Restore tagless access via VLAN 0 */ 7498 igb_set_vf_vlan(adapter, 0, true, vf); 7499 7500 igb_set_vmvir(adapter, 0, vf); 7501 igb_set_vmolr(adapter, vf, true); 7502 7503 /* Remove any PF assigned VLAN */ 7504 if (adapter->vf_data[vf].pf_vlan) 7505 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7506 false, vf); 7507 7508 adapter->vf_data[vf].pf_vlan = 0; 7509 adapter->vf_data[vf].pf_qos = 0; 7510 igb_set_vf_vlan_strip(adapter, vf, false); 7511 7512 return 0; 7513 } 7514 7515 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7516 u16 vlan, u8 qos, __be16 vlan_proto) 7517 { 7518 struct igb_adapter *adapter = netdev_priv(netdev); 7519 7520 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7521 return -EINVAL; 7522 7523 if (vlan_proto != htons(ETH_P_8021Q)) 7524 return -EPROTONOSUPPORT; 7525 7526 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7527 igb_disable_port_vlan(adapter, vf); 7528 } 7529 7530 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7531 { 7532 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7533 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7534 int ret; 7535 7536 if (adapter->vf_data[vf].pf_vlan) 7537 return -1; 7538 7539 /* VLAN 0 is a special case, don't allow it to be removed */ 7540 if (!vid && !add) 7541 return 0; 7542 7543 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7544 if (!ret) 7545 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7546 return ret; 7547 } 7548 7549 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7550 { 7551 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7552 7553 /* clear flags - except flag that indicates PF has set the MAC */ 7554 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7555 vf_data->last_nack = jiffies; 7556 7557 /* reset vlans for device */ 7558 igb_clear_vf_vfta(adapter, vf); 7559 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7560 igb_set_vmvir(adapter, vf_data->pf_vlan | 7561 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7562 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7563 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7564 7565 /* reset multicast table array for vf */ 7566 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7567 7568 /* Flush and reset the mta with the new values */ 7569 igb_set_rx_mode(adapter->netdev); 7570 } 7571 7572 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7573 { 7574 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7575 7576 /* clear mac address as we were hotplug removed/added */ 7577 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7578 eth_zero_addr(vf_mac); 7579 7580 /* process remaining reset events */ 7581 igb_vf_reset(adapter, vf); 7582 } 7583 7584 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7585 { 7586 struct e1000_hw *hw = &adapter->hw; 7587 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7588 u32 reg, msgbuf[3] = {}; 7589 u8 *addr = (u8 *)(&msgbuf[1]); 7590 7591 /* process all the same items cleared in a function level reset */ 7592 igb_vf_reset(adapter, vf); 7593 7594 /* set vf mac address */ 7595 igb_set_vf_mac(adapter, vf, vf_mac); 7596 7597 /* enable transmit and receive for vf */ 7598 reg = rd32(E1000_VFTE); 7599 wr32(E1000_VFTE, reg | BIT(vf)); 7600 reg = rd32(E1000_VFRE); 7601 wr32(E1000_VFRE, reg | BIT(vf)); 7602 7603 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7604 7605 /* reply to reset with ack and vf mac address */ 7606 if (!is_zero_ether_addr(vf_mac)) { 7607 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7608 memcpy(addr, vf_mac, ETH_ALEN); 7609 } else { 7610 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7611 } 7612 igb_write_mbx(hw, msgbuf, 3, vf); 7613 } 7614 7615 static void igb_flush_mac_table(struct igb_adapter *adapter) 7616 { 7617 struct e1000_hw *hw = &adapter->hw; 7618 int i; 7619 7620 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7621 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7622 eth_zero_addr(adapter->mac_table[i].addr); 7623 adapter->mac_table[i].queue = 0; 7624 igb_rar_set_index(adapter, i); 7625 } 7626 } 7627 7628 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7629 { 7630 struct e1000_hw *hw = &adapter->hw; 7631 /* do not count rar entries reserved for VFs MAC addresses */ 7632 int rar_entries = hw->mac.rar_entry_count - 7633 adapter->vfs_allocated_count; 7634 int i, count = 0; 7635 7636 for (i = 0; i < rar_entries; i++) { 7637 /* do not count default entries */ 7638 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7639 continue; 7640 7641 /* do not count "in use" entries for different queues */ 7642 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7643 (adapter->mac_table[i].queue != queue)) 7644 continue; 7645 7646 count++; 7647 } 7648 7649 return count; 7650 } 7651 7652 /* Set default MAC address for the PF in the first RAR entry */ 7653 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7654 { 7655 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7656 7657 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7658 mac_table->queue = adapter->vfs_allocated_count; 7659 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7660 7661 igb_rar_set_index(adapter, 0); 7662 } 7663 7664 /* If the filter to be added and an already existing filter express 7665 * the same address and address type, it should be possible to only 7666 * override the other configurations, for example the queue to steer 7667 * traffic. 7668 */ 7669 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7670 const u8 *addr, const u8 flags) 7671 { 7672 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7673 return true; 7674 7675 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7676 (flags & IGB_MAC_STATE_SRC_ADDR)) 7677 return false; 7678 7679 if (!ether_addr_equal(addr, entry->addr)) 7680 return false; 7681 7682 return true; 7683 } 7684 7685 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7686 * 'flags' is used to indicate what kind of match is made, match is by 7687 * default for the destination address, if matching by source address 7688 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7689 */ 7690 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7691 const u8 *addr, const u8 queue, 7692 const u8 flags) 7693 { 7694 struct e1000_hw *hw = &adapter->hw; 7695 int rar_entries = hw->mac.rar_entry_count - 7696 adapter->vfs_allocated_count; 7697 int i; 7698 7699 if (is_zero_ether_addr(addr)) 7700 return -EINVAL; 7701 7702 /* Search for the first empty entry in the MAC table. 7703 * Do not touch entries at the end of the table reserved for the VF MAC 7704 * addresses. 7705 */ 7706 for (i = 0; i < rar_entries; i++) { 7707 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7708 addr, flags)) 7709 continue; 7710 7711 ether_addr_copy(adapter->mac_table[i].addr, addr); 7712 adapter->mac_table[i].queue = queue; 7713 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7714 7715 igb_rar_set_index(adapter, i); 7716 return i; 7717 } 7718 7719 return -ENOSPC; 7720 } 7721 7722 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7723 const u8 queue) 7724 { 7725 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7726 } 7727 7728 /* Remove a MAC filter for 'addr' directing matching traffic to 7729 * 'queue', 'flags' is used to indicate what kind of match need to be 7730 * removed, match is by default for the destination address, if 7731 * matching by source address is to be removed the flag 7732 * IGB_MAC_STATE_SRC_ADDR can be used. 7733 */ 7734 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7735 const u8 *addr, const u8 queue, 7736 const u8 flags) 7737 { 7738 struct e1000_hw *hw = &adapter->hw; 7739 int rar_entries = hw->mac.rar_entry_count - 7740 adapter->vfs_allocated_count; 7741 int i; 7742 7743 if (is_zero_ether_addr(addr)) 7744 return -EINVAL; 7745 7746 /* Search for matching entry in the MAC table based on given address 7747 * and queue. Do not touch entries at the end of the table reserved 7748 * for the VF MAC addresses. 7749 */ 7750 for (i = 0; i < rar_entries; i++) { 7751 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7752 continue; 7753 if ((adapter->mac_table[i].state & flags) != flags) 7754 continue; 7755 if (adapter->mac_table[i].queue != queue) 7756 continue; 7757 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7758 continue; 7759 7760 /* When a filter for the default address is "deleted", 7761 * we return it to its initial configuration 7762 */ 7763 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7764 adapter->mac_table[i].state = 7765 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7766 adapter->mac_table[i].queue = 7767 adapter->vfs_allocated_count; 7768 } else { 7769 adapter->mac_table[i].state = 0; 7770 adapter->mac_table[i].queue = 0; 7771 eth_zero_addr(adapter->mac_table[i].addr); 7772 } 7773 7774 igb_rar_set_index(adapter, i); 7775 return 0; 7776 } 7777 7778 return -ENOENT; 7779 } 7780 7781 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7782 const u8 queue) 7783 { 7784 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7785 } 7786 7787 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7788 const u8 *addr, u8 queue, u8 flags) 7789 { 7790 struct e1000_hw *hw = &adapter->hw; 7791 7792 /* In theory, this should be supported on 82575 as well, but 7793 * that part wasn't easily accessible during development. 7794 */ 7795 if (hw->mac.type != e1000_i210) 7796 return -EOPNOTSUPP; 7797 7798 return igb_add_mac_filter_flags(adapter, addr, queue, 7799 IGB_MAC_STATE_QUEUE_STEERING | flags); 7800 } 7801 7802 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7803 const u8 *addr, u8 queue, u8 flags) 7804 { 7805 return igb_del_mac_filter_flags(adapter, addr, queue, 7806 IGB_MAC_STATE_QUEUE_STEERING | flags); 7807 } 7808 7809 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7810 { 7811 struct igb_adapter *adapter = netdev_priv(netdev); 7812 int ret; 7813 7814 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7815 7816 return min_t(int, ret, 0); 7817 } 7818 7819 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7820 { 7821 struct igb_adapter *adapter = netdev_priv(netdev); 7822 7823 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7824 7825 return 0; 7826 } 7827 7828 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7829 const u32 info, const u8 *addr) 7830 { 7831 struct pci_dev *pdev = adapter->pdev; 7832 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7833 struct vf_mac_filter *entry; 7834 bool found = false; 7835 int ret = 0; 7836 7837 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7838 !vf_data->trusted) { 7839 dev_warn(&pdev->dev, 7840 "VF %d requested MAC filter but is administratively denied\n", 7841 vf); 7842 return -EINVAL; 7843 } 7844 if (!is_valid_ether_addr(addr)) { 7845 dev_warn(&pdev->dev, 7846 "VF %d attempted to set invalid MAC filter\n", 7847 vf); 7848 return -EINVAL; 7849 } 7850 7851 switch (info) { 7852 case E1000_VF_MAC_FILTER_CLR: 7853 /* remove all unicast MAC filters related to the current VF */ 7854 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7855 if (entry->vf == vf) { 7856 entry->vf = -1; 7857 entry->free = true; 7858 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7859 } 7860 } 7861 break; 7862 case E1000_VF_MAC_FILTER_ADD: 7863 /* try to find empty slot in the list */ 7864 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7865 if (entry->free) { 7866 found = true; 7867 break; 7868 } 7869 } 7870 7871 if (found) { 7872 entry->free = false; 7873 entry->vf = vf; 7874 ether_addr_copy(entry->vf_mac, addr); 7875 7876 ret = igb_add_mac_filter(adapter, addr, vf); 7877 ret = min_t(int, ret, 0); 7878 } else { 7879 ret = -ENOSPC; 7880 } 7881 7882 if (ret == -ENOSPC) 7883 dev_warn(&pdev->dev, 7884 "VF %d has requested MAC filter but there is no space for it\n", 7885 vf); 7886 break; 7887 default: 7888 ret = -EINVAL; 7889 break; 7890 } 7891 7892 return ret; 7893 } 7894 7895 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7896 { 7897 struct pci_dev *pdev = adapter->pdev; 7898 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7899 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7900 7901 /* The VF MAC Address is stored in a packed array of bytes 7902 * starting at the second 32 bit word of the msg array 7903 */ 7904 unsigned char *addr = (unsigned char *)&msg[1]; 7905 int ret = 0; 7906 7907 if (!info) { 7908 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7909 !vf_data->trusted) { 7910 dev_warn(&pdev->dev, 7911 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7912 vf); 7913 return -EINVAL; 7914 } 7915 7916 if (!is_valid_ether_addr(addr)) { 7917 dev_warn(&pdev->dev, 7918 "VF %d attempted to set invalid MAC\n", 7919 vf); 7920 return -EINVAL; 7921 } 7922 7923 ret = igb_set_vf_mac(adapter, vf, addr); 7924 } else { 7925 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7926 } 7927 7928 return ret; 7929 } 7930 7931 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7932 { 7933 struct e1000_hw *hw = &adapter->hw; 7934 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7935 u32 msg = E1000_VT_MSGTYPE_NACK; 7936 7937 /* if device isn't clear to send it shouldn't be reading either */ 7938 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7939 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7940 igb_write_mbx(hw, &msg, 1, vf); 7941 vf_data->last_nack = jiffies; 7942 } 7943 } 7944 7945 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7946 { 7947 struct pci_dev *pdev = adapter->pdev; 7948 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7949 struct e1000_hw *hw = &adapter->hw; 7950 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7951 s32 retval; 7952 7953 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7954 7955 if (retval) { 7956 /* if receive failed revoke VF CTS stats and restart init */ 7957 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7958 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7959 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7960 goto unlock; 7961 goto out; 7962 } 7963 7964 /* this is a message we already processed, do nothing */ 7965 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7966 goto unlock; 7967 7968 /* until the vf completes a reset it should not be 7969 * allowed to start any configuration. 7970 */ 7971 if (msgbuf[0] == E1000_VF_RESET) { 7972 /* unlocks mailbox */ 7973 igb_vf_reset_msg(adapter, vf); 7974 return; 7975 } 7976 7977 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7978 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7979 goto unlock; 7980 retval = -1; 7981 goto out; 7982 } 7983 7984 switch ((msgbuf[0] & 0xFFFF)) { 7985 case E1000_VF_SET_MAC_ADDR: 7986 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7987 break; 7988 case E1000_VF_SET_PROMISC: 7989 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7990 break; 7991 case E1000_VF_SET_MULTICAST: 7992 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7993 break; 7994 case E1000_VF_SET_LPE: 7995 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7996 break; 7997 case E1000_VF_SET_VLAN: 7998 retval = -1; 7999 if (vf_data->pf_vlan) 8000 dev_warn(&pdev->dev, 8001 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8002 vf); 8003 else 8004 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8005 break; 8006 default: 8007 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8008 retval = -1; 8009 break; 8010 } 8011 8012 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8013 out: 8014 /* notify the VF of the results of what it sent us */ 8015 if (retval) 8016 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8017 else 8018 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8019 8020 /* unlocks mailbox */ 8021 igb_write_mbx(hw, msgbuf, 1, vf); 8022 return; 8023 8024 unlock: 8025 igb_unlock_mbx(hw, vf); 8026 } 8027 8028 static void igb_msg_task(struct igb_adapter *adapter) 8029 { 8030 struct e1000_hw *hw = &adapter->hw; 8031 unsigned long flags; 8032 u32 vf; 8033 8034 spin_lock_irqsave(&adapter->vfs_lock, flags); 8035 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8036 /* process any reset requests */ 8037 if (!igb_check_for_rst(hw, vf)) 8038 igb_vf_reset_event(adapter, vf); 8039 8040 /* process any messages pending */ 8041 if (!igb_check_for_msg(hw, vf)) 8042 igb_rcv_msg_from_vf(adapter, vf); 8043 8044 /* process any acks */ 8045 if (!igb_check_for_ack(hw, vf)) 8046 igb_rcv_ack_from_vf(adapter, vf); 8047 } 8048 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8049 } 8050 8051 /** 8052 * igb_set_uta - Set unicast filter table address 8053 * @adapter: board private structure 8054 * @set: boolean indicating if we are setting or clearing bits 8055 * 8056 * The unicast table address is a register array of 32-bit registers. 8057 * The table is meant to be used in a way similar to how the MTA is used 8058 * however due to certain limitations in the hardware it is necessary to 8059 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8060 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8061 **/ 8062 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8063 { 8064 struct e1000_hw *hw = &adapter->hw; 8065 u32 uta = set ? ~0 : 0; 8066 int i; 8067 8068 /* we only need to do this if VMDq is enabled */ 8069 if (!adapter->vfs_allocated_count) 8070 return; 8071 8072 for (i = hw->mac.uta_reg_count; i--;) 8073 array_wr32(E1000_UTA, i, uta); 8074 } 8075 8076 /** 8077 * igb_intr_msi - Interrupt Handler 8078 * @irq: interrupt number 8079 * @data: pointer to a network interface device structure 8080 **/ 8081 static irqreturn_t igb_intr_msi(int irq, void *data) 8082 { 8083 struct igb_adapter *adapter = data; 8084 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8085 struct e1000_hw *hw = &adapter->hw; 8086 /* read ICR disables interrupts using IAM */ 8087 u32 icr = rd32(E1000_ICR); 8088 8089 igb_write_itr(q_vector); 8090 8091 if (icr & E1000_ICR_DRSTA) 8092 schedule_work(&adapter->reset_task); 8093 8094 if (icr & E1000_ICR_DOUTSYNC) { 8095 /* HW is reporting DMA is out of sync */ 8096 adapter->stats.doosync++; 8097 } 8098 8099 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8100 hw->mac.get_link_status = 1; 8101 if (!test_bit(__IGB_DOWN, &adapter->state)) 8102 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8103 } 8104 8105 if (icr & E1000_ICR_TS) 8106 igb_tsync_interrupt(adapter); 8107 8108 napi_schedule(&q_vector->napi); 8109 8110 return IRQ_HANDLED; 8111 } 8112 8113 /** 8114 * igb_intr - Legacy Interrupt Handler 8115 * @irq: interrupt number 8116 * @data: pointer to a network interface device structure 8117 **/ 8118 static irqreturn_t igb_intr(int irq, void *data) 8119 { 8120 struct igb_adapter *adapter = data; 8121 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8122 struct e1000_hw *hw = &adapter->hw; 8123 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8124 * need for the IMC write 8125 */ 8126 u32 icr = rd32(E1000_ICR); 8127 8128 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8129 * not set, then the adapter didn't send an interrupt 8130 */ 8131 if (!(icr & E1000_ICR_INT_ASSERTED)) 8132 return IRQ_NONE; 8133 8134 igb_write_itr(q_vector); 8135 8136 if (icr & E1000_ICR_DRSTA) 8137 schedule_work(&adapter->reset_task); 8138 8139 if (icr & E1000_ICR_DOUTSYNC) { 8140 /* HW is reporting DMA is out of sync */ 8141 adapter->stats.doosync++; 8142 } 8143 8144 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8145 hw->mac.get_link_status = 1; 8146 /* guard against interrupt when we're going down */ 8147 if (!test_bit(__IGB_DOWN, &adapter->state)) 8148 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8149 } 8150 8151 if (icr & E1000_ICR_TS) 8152 igb_tsync_interrupt(adapter); 8153 8154 napi_schedule(&q_vector->napi); 8155 8156 return IRQ_HANDLED; 8157 } 8158 8159 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8160 { 8161 struct igb_adapter *adapter = q_vector->adapter; 8162 struct e1000_hw *hw = &adapter->hw; 8163 8164 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8165 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8166 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8167 igb_set_itr(q_vector); 8168 else 8169 igb_update_ring_itr(q_vector); 8170 } 8171 8172 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8173 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8174 wr32(E1000_EIMS, q_vector->eims_value); 8175 else 8176 igb_irq_enable(adapter); 8177 } 8178 } 8179 8180 /** 8181 * igb_poll - NAPI Rx polling callback 8182 * @napi: napi polling structure 8183 * @budget: count of how many packets we should handle 8184 **/ 8185 static int igb_poll(struct napi_struct *napi, int budget) 8186 { 8187 struct igb_q_vector *q_vector = container_of(napi, 8188 struct igb_q_vector, 8189 napi); 8190 bool clean_complete = true; 8191 int work_done = 0; 8192 8193 #ifdef CONFIG_IGB_DCA 8194 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8195 igb_update_dca(q_vector); 8196 #endif 8197 if (q_vector->tx.ring) 8198 clean_complete = igb_clean_tx_irq(q_vector, budget); 8199 8200 if (q_vector->rx.ring) { 8201 int cleaned = igb_clean_rx_irq(q_vector, budget); 8202 8203 work_done += cleaned; 8204 if (cleaned >= budget) 8205 clean_complete = false; 8206 } 8207 8208 /* If all work not completed, return budget and keep polling */ 8209 if (!clean_complete) 8210 return budget; 8211 8212 /* Exit the polling mode, but don't re-enable interrupts if stack might 8213 * poll us due to busy-polling 8214 */ 8215 if (likely(napi_complete_done(napi, work_done))) 8216 igb_ring_irq_enable(q_vector); 8217 8218 return work_done; 8219 } 8220 8221 /** 8222 * igb_clean_tx_irq - Reclaim resources after transmit completes 8223 * @q_vector: pointer to q_vector containing needed info 8224 * @napi_budget: Used to determine if we are in netpoll 8225 * 8226 * returns true if ring is completely cleaned 8227 **/ 8228 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8229 { 8230 struct igb_adapter *adapter = q_vector->adapter; 8231 struct igb_ring *tx_ring = q_vector->tx.ring; 8232 struct igb_tx_buffer *tx_buffer; 8233 union e1000_adv_tx_desc *tx_desc; 8234 unsigned int total_bytes = 0, total_packets = 0; 8235 unsigned int budget = q_vector->tx.work_limit; 8236 unsigned int i = tx_ring->next_to_clean; 8237 8238 if (test_bit(__IGB_DOWN, &adapter->state)) 8239 return true; 8240 8241 tx_buffer = &tx_ring->tx_buffer_info[i]; 8242 tx_desc = IGB_TX_DESC(tx_ring, i); 8243 i -= tx_ring->count; 8244 8245 do { 8246 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8247 8248 /* if next_to_watch is not set then there is no work pending */ 8249 if (!eop_desc) 8250 break; 8251 8252 /* prevent any other reads prior to eop_desc */ 8253 smp_rmb(); 8254 8255 /* if DD is not set pending work has not been completed */ 8256 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8257 break; 8258 8259 /* clear next_to_watch to prevent false hangs */ 8260 tx_buffer->next_to_watch = NULL; 8261 8262 /* update the statistics for this packet */ 8263 total_bytes += tx_buffer->bytecount; 8264 total_packets += tx_buffer->gso_segs; 8265 8266 /* free the skb */ 8267 if (tx_buffer->type == IGB_TYPE_SKB) 8268 napi_consume_skb(tx_buffer->skb, napi_budget); 8269 else 8270 xdp_return_frame(tx_buffer->xdpf); 8271 8272 /* unmap skb header data */ 8273 dma_unmap_single(tx_ring->dev, 8274 dma_unmap_addr(tx_buffer, dma), 8275 dma_unmap_len(tx_buffer, len), 8276 DMA_TO_DEVICE); 8277 8278 /* clear tx_buffer data */ 8279 dma_unmap_len_set(tx_buffer, len, 0); 8280 8281 /* clear last DMA location and unmap remaining buffers */ 8282 while (tx_desc != eop_desc) { 8283 tx_buffer++; 8284 tx_desc++; 8285 i++; 8286 if (unlikely(!i)) { 8287 i -= tx_ring->count; 8288 tx_buffer = tx_ring->tx_buffer_info; 8289 tx_desc = IGB_TX_DESC(tx_ring, 0); 8290 } 8291 8292 /* unmap any remaining paged data */ 8293 if (dma_unmap_len(tx_buffer, len)) { 8294 dma_unmap_page(tx_ring->dev, 8295 dma_unmap_addr(tx_buffer, dma), 8296 dma_unmap_len(tx_buffer, len), 8297 DMA_TO_DEVICE); 8298 dma_unmap_len_set(tx_buffer, len, 0); 8299 } 8300 } 8301 8302 /* move us one more past the eop_desc for start of next pkt */ 8303 tx_buffer++; 8304 tx_desc++; 8305 i++; 8306 if (unlikely(!i)) { 8307 i -= tx_ring->count; 8308 tx_buffer = tx_ring->tx_buffer_info; 8309 tx_desc = IGB_TX_DESC(tx_ring, 0); 8310 } 8311 8312 /* issue prefetch for next Tx descriptor */ 8313 prefetch(tx_desc); 8314 8315 /* update budget accounting */ 8316 budget--; 8317 } while (likely(budget)); 8318 8319 netdev_tx_completed_queue(txring_txq(tx_ring), 8320 total_packets, total_bytes); 8321 i += tx_ring->count; 8322 tx_ring->next_to_clean = i; 8323 u64_stats_update_begin(&tx_ring->tx_syncp); 8324 tx_ring->tx_stats.bytes += total_bytes; 8325 tx_ring->tx_stats.packets += total_packets; 8326 u64_stats_update_end(&tx_ring->tx_syncp); 8327 q_vector->tx.total_bytes += total_bytes; 8328 q_vector->tx.total_packets += total_packets; 8329 8330 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8331 struct e1000_hw *hw = &adapter->hw; 8332 8333 /* Detect a transmit hang in hardware, this serializes the 8334 * check with the clearing of time_stamp and movement of i 8335 */ 8336 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8337 if (tx_buffer->next_to_watch && 8338 time_after(jiffies, tx_buffer->time_stamp + 8339 (adapter->tx_timeout_factor * HZ)) && 8340 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8341 8342 /* detected Tx unit hang */ 8343 dev_err(tx_ring->dev, 8344 "Detected Tx Unit Hang\n" 8345 " Tx Queue <%d>\n" 8346 " TDH <%x>\n" 8347 " TDT <%x>\n" 8348 " next_to_use <%x>\n" 8349 " next_to_clean <%x>\n" 8350 "buffer_info[next_to_clean]\n" 8351 " time_stamp <%lx>\n" 8352 " next_to_watch <%p>\n" 8353 " jiffies <%lx>\n" 8354 " desc.status <%x>\n", 8355 tx_ring->queue_index, 8356 rd32(E1000_TDH(tx_ring->reg_idx)), 8357 readl(tx_ring->tail), 8358 tx_ring->next_to_use, 8359 tx_ring->next_to_clean, 8360 tx_buffer->time_stamp, 8361 tx_buffer->next_to_watch, 8362 jiffies, 8363 tx_buffer->next_to_watch->wb.status); 8364 netif_stop_subqueue(tx_ring->netdev, 8365 tx_ring->queue_index); 8366 8367 /* we are about to reset, no point in enabling stuff */ 8368 return true; 8369 } 8370 } 8371 8372 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8373 if (unlikely(total_packets && 8374 netif_carrier_ok(tx_ring->netdev) && 8375 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8376 /* Make sure that anybody stopping the queue after this 8377 * sees the new next_to_clean. 8378 */ 8379 smp_mb(); 8380 if (__netif_subqueue_stopped(tx_ring->netdev, 8381 tx_ring->queue_index) && 8382 !(test_bit(__IGB_DOWN, &adapter->state))) { 8383 netif_wake_subqueue(tx_ring->netdev, 8384 tx_ring->queue_index); 8385 8386 u64_stats_update_begin(&tx_ring->tx_syncp); 8387 tx_ring->tx_stats.restart_queue++; 8388 u64_stats_update_end(&tx_ring->tx_syncp); 8389 } 8390 } 8391 8392 return !!budget; 8393 } 8394 8395 /** 8396 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8397 * @rx_ring: rx descriptor ring to store buffers on 8398 * @old_buff: donor buffer to have page reused 8399 * 8400 * Synchronizes page for reuse by the adapter 8401 **/ 8402 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8403 struct igb_rx_buffer *old_buff) 8404 { 8405 struct igb_rx_buffer *new_buff; 8406 u16 nta = rx_ring->next_to_alloc; 8407 8408 new_buff = &rx_ring->rx_buffer_info[nta]; 8409 8410 /* update, and store next to alloc */ 8411 nta++; 8412 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8413 8414 /* Transfer page from old buffer to new buffer. 8415 * Move each member individually to avoid possible store 8416 * forwarding stalls. 8417 */ 8418 new_buff->dma = old_buff->dma; 8419 new_buff->page = old_buff->page; 8420 new_buff->page_offset = old_buff->page_offset; 8421 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8422 } 8423 8424 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8425 int rx_buf_pgcnt) 8426 { 8427 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8428 struct page *page = rx_buffer->page; 8429 8430 /* avoid re-using remote and pfmemalloc pages */ 8431 if (!dev_page_is_reusable(page)) 8432 return false; 8433 8434 #if (PAGE_SIZE < 8192) 8435 /* if we are only owner of page we can reuse it */ 8436 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8437 return false; 8438 #else 8439 #define IGB_LAST_OFFSET \ 8440 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8441 8442 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8443 return false; 8444 #endif 8445 8446 /* If we have drained the page fragment pool we need to update 8447 * the pagecnt_bias and page count so that we fully restock the 8448 * number of references the driver holds. 8449 */ 8450 if (unlikely(pagecnt_bias == 1)) { 8451 page_ref_add(page, USHRT_MAX - 1); 8452 rx_buffer->pagecnt_bias = USHRT_MAX; 8453 } 8454 8455 return true; 8456 } 8457 8458 /** 8459 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8460 * @rx_ring: rx descriptor ring to transact packets on 8461 * @rx_buffer: buffer containing page to add 8462 * @skb: sk_buff to place the data into 8463 * @size: size of buffer to be added 8464 * 8465 * This function will add the data contained in rx_buffer->page to the skb. 8466 **/ 8467 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8468 struct igb_rx_buffer *rx_buffer, 8469 struct sk_buff *skb, 8470 unsigned int size) 8471 { 8472 #if (PAGE_SIZE < 8192) 8473 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8474 #else 8475 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8476 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8477 SKB_DATA_ALIGN(size); 8478 #endif 8479 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8480 rx_buffer->page_offset, size, truesize); 8481 #if (PAGE_SIZE < 8192) 8482 rx_buffer->page_offset ^= truesize; 8483 #else 8484 rx_buffer->page_offset += truesize; 8485 #endif 8486 } 8487 8488 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8489 struct igb_rx_buffer *rx_buffer, 8490 struct xdp_buff *xdp, 8491 ktime_t timestamp) 8492 { 8493 #if (PAGE_SIZE < 8192) 8494 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8495 #else 8496 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8497 xdp->data_hard_start); 8498 #endif 8499 unsigned int size = xdp->data_end - xdp->data; 8500 unsigned int headlen; 8501 struct sk_buff *skb; 8502 8503 /* prefetch first cache line of first page */ 8504 net_prefetch(xdp->data); 8505 8506 /* allocate a skb to store the frags */ 8507 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8508 if (unlikely(!skb)) 8509 return NULL; 8510 8511 if (timestamp) 8512 skb_hwtstamps(skb)->hwtstamp = timestamp; 8513 8514 /* Determine available headroom for copy */ 8515 headlen = size; 8516 if (headlen > IGB_RX_HDR_LEN) 8517 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8518 8519 /* align pull length to size of long to optimize memcpy performance */ 8520 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8521 8522 /* update all of the pointers */ 8523 size -= headlen; 8524 if (size) { 8525 skb_add_rx_frag(skb, 0, rx_buffer->page, 8526 (xdp->data + headlen) - page_address(rx_buffer->page), 8527 size, truesize); 8528 #if (PAGE_SIZE < 8192) 8529 rx_buffer->page_offset ^= truesize; 8530 #else 8531 rx_buffer->page_offset += truesize; 8532 #endif 8533 } else { 8534 rx_buffer->pagecnt_bias++; 8535 } 8536 8537 return skb; 8538 } 8539 8540 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8541 struct igb_rx_buffer *rx_buffer, 8542 struct xdp_buff *xdp, 8543 ktime_t timestamp) 8544 { 8545 #if (PAGE_SIZE < 8192) 8546 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8547 #else 8548 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8549 SKB_DATA_ALIGN(xdp->data_end - 8550 xdp->data_hard_start); 8551 #endif 8552 unsigned int metasize = xdp->data - xdp->data_meta; 8553 struct sk_buff *skb; 8554 8555 /* prefetch first cache line of first page */ 8556 net_prefetch(xdp->data_meta); 8557 8558 /* build an skb around the page buffer */ 8559 skb = napi_build_skb(xdp->data_hard_start, truesize); 8560 if (unlikely(!skb)) 8561 return NULL; 8562 8563 /* update pointers within the skb to store the data */ 8564 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8565 __skb_put(skb, xdp->data_end - xdp->data); 8566 8567 if (metasize) 8568 skb_metadata_set(skb, metasize); 8569 8570 if (timestamp) 8571 skb_hwtstamps(skb)->hwtstamp = timestamp; 8572 8573 /* update buffer offset */ 8574 #if (PAGE_SIZE < 8192) 8575 rx_buffer->page_offset ^= truesize; 8576 #else 8577 rx_buffer->page_offset += truesize; 8578 #endif 8579 8580 return skb; 8581 } 8582 8583 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8584 struct igb_ring *rx_ring, 8585 struct xdp_buff *xdp) 8586 { 8587 int err, result = IGB_XDP_PASS; 8588 struct bpf_prog *xdp_prog; 8589 u32 act; 8590 8591 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8592 8593 if (!xdp_prog) 8594 goto xdp_out; 8595 8596 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8597 8598 act = bpf_prog_run_xdp(xdp_prog, xdp); 8599 switch (act) { 8600 case XDP_PASS: 8601 break; 8602 case XDP_TX: 8603 result = igb_xdp_xmit_back(adapter, xdp); 8604 if (result == IGB_XDP_CONSUMED) 8605 goto out_failure; 8606 break; 8607 case XDP_REDIRECT: 8608 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8609 if (err) 8610 goto out_failure; 8611 result = IGB_XDP_REDIR; 8612 break; 8613 default: 8614 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8615 fallthrough; 8616 case XDP_ABORTED: 8617 out_failure: 8618 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8619 fallthrough; 8620 case XDP_DROP: 8621 result = IGB_XDP_CONSUMED; 8622 break; 8623 } 8624 xdp_out: 8625 return ERR_PTR(-result); 8626 } 8627 8628 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8629 unsigned int size) 8630 { 8631 unsigned int truesize; 8632 8633 #if (PAGE_SIZE < 8192) 8634 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8635 #else 8636 truesize = ring_uses_build_skb(rx_ring) ? 8637 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8638 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8639 SKB_DATA_ALIGN(size); 8640 #endif 8641 return truesize; 8642 } 8643 8644 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8645 struct igb_rx_buffer *rx_buffer, 8646 unsigned int size) 8647 { 8648 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8649 #if (PAGE_SIZE < 8192) 8650 rx_buffer->page_offset ^= truesize; 8651 #else 8652 rx_buffer->page_offset += truesize; 8653 #endif 8654 } 8655 8656 static inline void igb_rx_checksum(struct igb_ring *ring, 8657 union e1000_adv_rx_desc *rx_desc, 8658 struct sk_buff *skb) 8659 { 8660 skb_checksum_none_assert(skb); 8661 8662 /* Ignore Checksum bit is set */ 8663 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8664 return; 8665 8666 /* Rx checksum disabled via ethtool */ 8667 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8668 return; 8669 8670 /* TCP/UDP checksum error bit is set */ 8671 if (igb_test_staterr(rx_desc, 8672 E1000_RXDEXT_STATERR_TCPE | 8673 E1000_RXDEXT_STATERR_IPE)) { 8674 /* work around errata with sctp packets where the TCPE aka 8675 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8676 * packets, (aka let the stack check the crc32c) 8677 */ 8678 if (!((skb->len == 60) && 8679 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8680 u64_stats_update_begin(&ring->rx_syncp); 8681 ring->rx_stats.csum_err++; 8682 u64_stats_update_end(&ring->rx_syncp); 8683 } 8684 /* let the stack verify checksum errors */ 8685 return; 8686 } 8687 /* It must be a TCP or UDP packet with a valid checksum */ 8688 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8689 E1000_RXD_STAT_UDPCS)) 8690 skb->ip_summed = CHECKSUM_UNNECESSARY; 8691 8692 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8693 le32_to_cpu(rx_desc->wb.upper.status_error)); 8694 } 8695 8696 static inline void igb_rx_hash(struct igb_ring *ring, 8697 union e1000_adv_rx_desc *rx_desc, 8698 struct sk_buff *skb) 8699 { 8700 if (ring->netdev->features & NETIF_F_RXHASH) 8701 skb_set_hash(skb, 8702 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8703 PKT_HASH_TYPE_L3); 8704 } 8705 8706 /** 8707 * igb_is_non_eop - process handling of non-EOP buffers 8708 * @rx_ring: Rx ring being processed 8709 * @rx_desc: Rx descriptor for current buffer 8710 * 8711 * This function updates next to clean. If the buffer is an EOP buffer 8712 * this function exits returning false, otherwise it will place the 8713 * sk_buff in the next buffer to be chained and return true indicating 8714 * that this is in fact a non-EOP buffer. 8715 **/ 8716 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8717 union e1000_adv_rx_desc *rx_desc) 8718 { 8719 u32 ntc = rx_ring->next_to_clean + 1; 8720 8721 /* fetch, update, and store next to clean */ 8722 ntc = (ntc < rx_ring->count) ? ntc : 0; 8723 rx_ring->next_to_clean = ntc; 8724 8725 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8726 8727 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8728 return false; 8729 8730 return true; 8731 } 8732 8733 /** 8734 * igb_cleanup_headers - Correct corrupted or empty headers 8735 * @rx_ring: rx descriptor ring packet is being transacted on 8736 * @rx_desc: pointer to the EOP Rx descriptor 8737 * @skb: pointer to current skb being fixed 8738 * 8739 * Address the case where we are pulling data in on pages only 8740 * and as such no data is present in the skb header. 8741 * 8742 * In addition if skb is not at least 60 bytes we need to pad it so that 8743 * it is large enough to qualify as a valid Ethernet frame. 8744 * 8745 * Returns true if an error was encountered and skb was freed. 8746 **/ 8747 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8748 union e1000_adv_rx_desc *rx_desc, 8749 struct sk_buff *skb) 8750 { 8751 /* XDP packets use error pointer so abort at this point */ 8752 if (IS_ERR(skb)) 8753 return true; 8754 8755 if (unlikely((igb_test_staterr(rx_desc, 8756 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8757 struct net_device *netdev = rx_ring->netdev; 8758 if (!(netdev->features & NETIF_F_RXALL)) { 8759 dev_kfree_skb_any(skb); 8760 return true; 8761 } 8762 } 8763 8764 /* if eth_skb_pad returns an error the skb was freed */ 8765 if (eth_skb_pad(skb)) 8766 return true; 8767 8768 return false; 8769 } 8770 8771 /** 8772 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8773 * @rx_ring: rx descriptor ring packet is being transacted on 8774 * @rx_desc: pointer to the EOP Rx descriptor 8775 * @skb: pointer to current skb being populated 8776 * 8777 * This function checks the ring, descriptor, and packet information in 8778 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8779 * other fields within the skb. 8780 **/ 8781 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8782 union e1000_adv_rx_desc *rx_desc, 8783 struct sk_buff *skb) 8784 { 8785 struct net_device *dev = rx_ring->netdev; 8786 8787 igb_rx_hash(rx_ring, rx_desc, skb); 8788 8789 igb_rx_checksum(rx_ring, rx_desc, skb); 8790 8791 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8792 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8793 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8794 8795 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8796 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8797 u16 vid; 8798 8799 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8800 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8801 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8802 else 8803 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8804 8805 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8806 } 8807 8808 skb_record_rx_queue(skb, rx_ring->queue_index); 8809 8810 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8811 } 8812 8813 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8814 { 8815 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8816 } 8817 8818 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8819 const unsigned int size, int *rx_buf_pgcnt) 8820 { 8821 struct igb_rx_buffer *rx_buffer; 8822 8823 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8824 *rx_buf_pgcnt = 8825 #if (PAGE_SIZE < 8192) 8826 page_count(rx_buffer->page); 8827 #else 8828 0; 8829 #endif 8830 prefetchw(rx_buffer->page); 8831 8832 /* we are reusing so sync this buffer for CPU use */ 8833 dma_sync_single_range_for_cpu(rx_ring->dev, 8834 rx_buffer->dma, 8835 rx_buffer->page_offset, 8836 size, 8837 DMA_FROM_DEVICE); 8838 8839 rx_buffer->pagecnt_bias--; 8840 8841 return rx_buffer; 8842 } 8843 8844 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8845 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8846 { 8847 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8848 /* hand second half of page back to the ring */ 8849 igb_reuse_rx_page(rx_ring, rx_buffer); 8850 } else { 8851 /* We are not reusing the buffer so unmap it and free 8852 * any references we are holding to it 8853 */ 8854 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8855 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8856 IGB_RX_DMA_ATTR); 8857 __page_frag_cache_drain(rx_buffer->page, 8858 rx_buffer->pagecnt_bias); 8859 } 8860 8861 /* clear contents of rx_buffer */ 8862 rx_buffer->page = NULL; 8863 } 8864 8865 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8866 { 8867 struct igb_adapter *adapter = q_vector->adapter; 8868 struct igb_ring *rx_ring = q_vector->rx.ring; 8869 struct sk_buff *skb = rx_ring->skb; 8870 unsigned int total_bytes = 0, total_packets = 0; 8871 u16 cleaned_count = igb_desc_unused(rx_ring); 8872 unsigned int xdp_xmit = 0; 8873 struct xdp_buff xdp; 8874 u32 frame_sz = 0; 8875 int rx_buf_pgcnt; 8876 8877 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8878 #if (PAGE_SIZE < 8192) 8879 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8880 #endif 8881 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8882 8883 while (likely(total_packets < budget)) { 8884 union e1000_adv_rx_desc *rx_desc; 8885 struct igb_rx_buffer *rx_buffer; 8886 ktime_t timestamp = 0; 8887 int pkt_offset = 0; 8888 unsigned int size; 8889 void *pktbuf; 8890 8891 /* return some buffers to hardware, one at a time is too slow */ 8892 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8893 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8894 cleaned_count = 0; 8895 } 8896 8897 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8898 size = le16_to_cpu(rx_desc->wb.upper.length); 8899 if (!size) 8900 break; 8901 8902 /* This memory barrier is needed to keep us from reading 8903 * any other fields out of the rx_desc until we know the 8904 * descriptor has been written back 8905 */ 8906 dma_rmb(); 8907 8908 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8909 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8910 8911 /* pull rx packet timestamp if available and valid */ 8912 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8913 int ts_hdr_len; 8914 8915 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8916 pktbuf, ×tamp); 8917 8918 pkt_offset += ts_hdr_len; 8919 size -= ts_hdr_len; 8920 } 8921 8922 /* retrieve a buffer from the ring */ 8923 if (!skb) { 8924 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8925 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8926 8927 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8928 xdp_buff_clear_frags_flag(&xdp); 8929 #if (PAGE_SIZE > 4096) 8930 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8931 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8932 #endif 8933 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8934 } 8935 8936 if (IS_ERR(skb)) { 8937 unsigned int xdp_res = -PTR_ERR(skb); 8938 8939 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8940 xdp_xmit |= xdp_res; 8941 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8942 } else { 8943 rx_buffer->pagecnt_bias++; 8944 } 8945 total_packets++; 8946 total_bytes += size; 8947 } else if (skb) 8948 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8949 else if (ring_uses_build_skb(rx_ring)) 8950 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8951 timestamp); 8952 else 8953 skb = igb_construct_skb(rx_ring, rx_buffer, 8954 &xdp, timestamp); 8955 8956 /* exit if we failed to retrieve a buffer */ 8957 if (!skb) { 8958 rx_ring->rx_stats.alloc_failed++; 8959 rx_buffer->pagecnt_bias++; 8960 break; 8961 } 8962 8963 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8964 cleaned_count++; 8965 8966 /* fetch next buffer in frame if non-eop */ 8967 if (igb_is_non_eop(rx_ring, rx_desc)) 8968 continue; 8969 8970 /* verify the packet layout is correct */ 8971 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8972 skb = NULL; 8973 continue; 8974 } 8975 8976 /* probably a little skewed due to removing CRC */ 8977 total_bytes += skb->len; 8978 8979 /* populate checksum, timestamp, VLAN, and protocol */ 8980 igb_process_skb_fields(rx_ring, rx_desc, skb); 8981 8982 napi_gro_receive(&q_vector->napi, skb); 8983 8984 /* reset skb pointer */ 8985 skb = NULL; 8986 8987 /* update budget accounting */ 8988 total_packets++; 8989 } 8990 8991 /* place incomplete frames back on ring for completion */ 8992 rx_ring->skb = skb; 8993 8994 if (xdp_xmit & IGB_XDP_REDIR) 8995 xdp_do_flush(); 8996 8997 if (xdp_xmit & IGB_XDP_TX) { 8998 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8999 9000 igb_xdp_ring_update_tail(tx_ring); 9001 } 9002 9003 u64_stats_update_begin(&rx_ring->rx_syncp); 9004 rx_ring->rx_stats.packets += total_packets; 9005 rx_ring->rx_stats.bytes += total_bytes; 9006 u64_stats_update_end(&rx_ring->rx_syncp); 9007 q_vector->rx.total_packets += total_packets; 9008 q_vector->rx.total_bytes += total_bytes; 9009 9010 if (cleaned_count) 9011 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9012 9013 return total_packets; 9014 } 9015 9016 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9017 struct igb_rx_buffer *bi) 9018 { 9019 struct page *page = bi->page; 9020 dma_addr_t dma; 9021 9022 /* since we are recycling buffers we should seldom need to alloc */ 9023 if (likely(page)) 9024 return true; 9025 9026 /* alloc new page for storage */ 9027 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9028 if (unlikely(!page)) { 9029 rx_ring->rx_stats.alloc_failed++; 9030 return false; 9031 } 9032 9033 /* map page for use */ 9034 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9035 igb_rx_pg_size(rx_ring), 9036 DMA_FROM_DEVICE, 9037 IGB_RX_DMA_ATTR); 9038 9039 /* if mapping failed free memory back to system since 9040 * there isn't much point in holding memory we can't use 9041 */ 9042 if (dma_mapping_error(rx_ring->dev, dma)) { 9043 __free_pages(page, igb_rx_pg_order(rx_ring)); 9044 9045 rx_ring->rx_stats.alloc_failed++; 9046 return false; 9047 } 9048 9049 bi->dma = dma; 9050 bi->page = page; 9051 bi->page_offset = igb_rx_offset(rx_ring); 9052 page_ref_add(page, USHRT_MAX - 1); 9053 bi->pagecnt_bias = USHRT_MAX; 9054 9055 return true; 9056 } 9057 9058 /** 9059 * igb_alloc_rx_buffers - Replace used receive buffers 9060 * @rx_ring: rx descriptor ring to allocate new receive buffers 9061 * @cleaned_count: count of buffers to allocate 9062 **/ 9063 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9064 { 9065 union e1000_adv_rx_desc *rx_desc; 9066 struct igb_rx_buffer *bi; 9067 u16 i = rx_ring->next_to_use; 9068 u16 bufsz; 9069 9070 /* nothing to do */ 9071 if (!cleaned_count) 9072 return; 9073 9074 rx_desc = IGB_RX_DESC(rx_ring, i); 9075 bi = &rx_ring->rx_buffer_info[i]; 9076 i -= rx_ring->count; 9077 9078 bufsz = igb_rx_bufsz(rx_ring); 9079 9080 do { 9081 if (!igb_alloc_mapped_page(rx_ring, bi)) 9082 break; 9083 9084 /* sync the buffer for use by the device */ 9085 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9086 bi->page_offset, bufsz, 9087 DMA_FROM_DEVICE); 9088 9089 /* Refresh the desc even if buffer_addrs didn't change 9090 * because each write-back erases this info. 9091 */ 9092 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9093 9094 rx_desc++; 9095 bi++; 9096 i++; 9097 if (unlikely(!i)) { 9098 rx_desc = IGB_RX_DESC(rx_ring, 0); 9099 bi = rx_ring->rx_buffer_info; 9100 i -= rx_ring->count; 9101 } 9102 9103 /* clear the length for the next_to_use descriptor */ 9104 rx_desc->wb.upper.length = 0; 9105 9106 cleaned_count--; 9107 } while (cleaned_count); 9108 9109 i += rx_ring->count; 9110 9111 if (rx_ring->next_to_use != i) { 9112 /* record the next descriptor to use */ 9113 rx_ring->next_to_use = i; 9114 9115 /* update next to alloc since we have filled the ring */ 9116 rx_ring->next_to_alloc = i; 9117 9118 /* Force memory writes to complete before letting h/w 9119 * know there are new descriptors to fetch. (Only 9120 * applicable for weak-ordered memory model archs, 9121 * such as IA-64). 9122 */ 9123 dma_wmb(); 9124 writel(i, rx_ring->tail); 9125 } 9126 } 9127 9128 /** 9129 * igb_mii_ioctl - 9130 * @netdev: pointer to netdev struct 9131 * @ifr: interface structure 9132 * @cmd: ioctl command to execute 9133 **/ 9134 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9135 { 9136 struct igb_adapter *adapter = netdev_priv(netdev); 9137 struct mii_ioctl_data *data = if_mii(ifr); 9138 9139 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9140 return -EOPNOTSUPP; 9141 9142 switch (cmd) { 9143 case SIOCGMIIPHY: 9144 data->phy_id = adapter->hw.phy.addr; 9145 break; 9146 case SIOCGMIIREG: 9147 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9148 &data->val_out)) 9149 return -EIO; 9150 break; 9151 case SIOCSMIIREG: 9152 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9153 data->val_in)) 9154 return -EIO; 9155 break; 9156 default: 9157 return -EOPNOTSUPP; 9158 } 9159 return 0; 9160 } 9161 9162 /** 9163 * igb_ioctl - 9164 * @netdev: pointer to netdev struct 9165 * @ifr: interface structure 9166 * @cmd: ioctl command to execute 9167 **/ 9168 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9169 { 9170 switch (cmd) { 9171 case SIOCGMIIPHY: 9172 case SIOCGMIIREG: 9173 case SIOCSMIIREG: 9174 return igb_mii_ioctl(netdev, ifr, cmd); 9175 case SIOCGHWTSTAMP: 9176 return igb_ptp_get_ts_config(netdev, ifr); 9177 case SIOCSHWTSTAMP: 9178 return igb_ptp_set_ts_config(netdev, ifr); 9179 default: 9180 return -EOPNOTSUPP; 9181 } 9182 } 9183 9184 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9185 { 9186 struct igb_adapter *adapter = hw->back; 9187 9188 pci_read_config_word(adapter->pdev, reg, value); 9189 } 9190 9191 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9192 { 9193 struct igb_adapter *adapter = hw->back; 9194 9195 pci_write_config_word(adapter->pdev, reg, *value); 9196 } 9197 9198 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9199 { 9200 struct igb_adapter *adapter = hw->back; 9201 9202 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9203 return -E1000_ERR_CONFIG; 9204 9205 return 0; 9206 } 9207 9208 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9209 { 9210 struct igb_adapter *adapter = hw->back; 9211 9212 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9213 return -E1000_ERR_CONFIG; 9214 9215 return 0; 9216 } 9217 9218 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9219 { 9220 struct igb_adapter *adapter = netdev_priv(netdev); 9221 struct e1000_hw *hw = &adapter->hw; 9222 u32 ctrl, rctl; 9223 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9224 9225 if (enable) { 9226 /* enable VLAN tag insert/strip */ 9227 ctrl = rd32(E1000_CTRL); 9228 ctrl |= E1000_CTRL_VME; 9229 wr32(E1000_CTRL, ctrl); 9230 9231 /* Disable CFI check */ 9232 rctl = rd32(E1000_RCTL); 9233 rctl &= ~E1000_RCTL_CFIEN; 9234 wr32(E1000_RCTL, rctl); 9235 } else { 9236 /* disable VLAN tag insert/strip */ 9237 ctrl = rd32(E1000_CTRL); 9238 ctrl &= ~E1000_CTRL_VME; 9239 wr32(E1000_CTRL, ctrl); 9240 } 9241 9242 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9243 } 9244 9245 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9246 __be16 proto, u16 vid) 9247 { 9248 struct igb_adapter *adapter = netdev_priv(netdev); 9249 struct e1000_hw *hw = &adapter->hw; 9250 int pf_id = adapter->vfs_allocated_count; 9251 9252 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9253 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9254 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9255 9256 set_bit(vid, adapter->active_vlans); 9257 9258 return 0; 9259 } 9260 9261 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9262 __be16 proto, u16 vid) 9263 { 9264 struct igb_adapter *adapter = netdev_priv(netdev); 9265 int pf_id = adapter->vfs_allocated_count; 9266 struct e1000_hw *hw = &adapter->hw; 9267 9268 /* remove VID from filter table */ 9269 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9270 igb_vfta_set(hw, vid, pf_id, false, true); 9271 9272 clear_bit(vid, adapter->active_vlans); 9273 9274 return 0; 9275 } 9276 9277 static void igb_restore_vlan(struct igb_adapter *adapter) 9278 { 9279 u16 vid = 1; 9280 9281 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9282 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9283 9284 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9285 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9286 } 9287 9288 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9289 { 9290 struct pci_dev *pdev = adapter->pdev; 9291 struct e1000_mac_info *mac = &adapter->hw.mac; 9292 9293 mac->autoneg = 0; 9294 9295 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9296 * for the switch() below to work 9297 */ 9298 if ((spd & 1) || (dplx & ~1)) 9299 goto err_inval; 9300 9301 /* Fiber NIC's only allow 1000 gbps Full duplex 9302 * and 100Mbps Full duplex for 100baseFx sfp 9303 */ 9304 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9305 switch (spd + dplx) { 9306 case SPEED_10 + DUPLEX_HALF: 9307 case SPEED_10 + DUPLEX_FULL: 9308 case SPEED_100 + DUPLEX_HALF: 9309 goto err_inval; 9310 default: 9311 break; 9312 } 9313 } 9314 9315 switch (spd + dplx) { 9316 case SPEED_10 + DUPLEX_HALF: 9317 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9318 break; 9319 case SPEED_10 + DUPLEX_FULL: 9320 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9321 break; 9322 case SPEED_100 + DUPLEX_HALF: 9323 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9324 break; 9325 case SPEED_100 + DUPLEX_FULL: 9326 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9327 break; 9328 case SPEED_1000 + DUPLEX_FULL: 9329 mac->autoneg = 1; 9330 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9331 break; 9332 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9333 default: 9334 goto err_inval; 9335 } 9336 9337 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9338 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9339 9340 return 0; 9341 9342 err_inval: 9343 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9344 return -EINVAL; 9345 } 9346 9347 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9348 bool runtime) 9349 { 9350 struct net_device *netdev = pci_get_drvdata(pdev); 9351 struct igb_adapter *adapter = netdev_priv(netdev); 9352 struct e1000_hw *hw = &adapter->hw; 9353 u32 ctrl, rctl, status; 9354 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9355 bool wake; 9356 9357 rtnl_lock(); 9358 netif_device_detach(netdev); 9359 9360 if (netif_running(netdev)) 9361 __igb_close(netdev, true); 9362 9363 igb_ptp_suspend(adapter); 9364 9365 igb_clear_interrupt_scheme(adapter); 9366 rtnl_unlock(); 9367 9368 status = rd32(E1000_STATUS); 9369 if (status & E1000_STATUS_LU) 9370 wufc &= ~E1000_WUFC_LNKC; 9371 9372 if (wufc) { 9373 igb_setup_rctl(adapter); 9374 igb_set_rx_mode(netdev); 9375 9376 /* turn on all-multi mode if wake on multicast is enabled */ 9377 if (wufc & E1000_WUFC_MC) { 9378 rctl = rd32(E1000_RCTL); 9379 rctl |= E1000_RCTL_MPE; 9380 wr32(E1000_RCTL, rctl); 9381 } 9382 9383 ctrl = rd32(E1000_CTRL); 9384 ctrl |= E1000_CTRL_ADVD3WUC; 9385 wr32(E1000_CTRL, ctrl); 9386 9387 /* Allow time for pending master requests to run */ 9388 igb_disable_pcie_master(hw); 9389 9390 wr32(E1000_WUC, E1000_WUC_PME_EN); 9391 wr32(E1000_WUFC, wufc); 9392 } else { 9393 wr32(E1000_WUC, 0); 9394 wr32(E1000_WUFC, 0); 9395 } 9396 9397 wake = wufc || adapter->en_mng_pt; 9398 if (!wake) 9399 igb_power_down_link(adapter); 9400 else 9401 igb_power_up_link(adapter); 9402 9403 if (enable_wake) 9404 *enable_wake = wake; 9405 9406 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9407 * would have already happened in close and is redundant. 9408 */ 9409 igb_release_hw_control(adapter); 9410 9411 pci_disable_device(pdev); 9412 9413 return 0; 9414 } 9415 9416 static void igb_deliver_wake_packet(struct net_device *netdev) 9417 { 9418 struct igb_adapter *adapter = netdev_priv(netdev); 9419 struct e1000_hw *hw = &adapter->hw; 9420 struct sk_buff *skb; 9421 u32 wupl; 9422 9423 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9424 9425 /* WUPM stores only the first 128 bytes of the wake packet. 9426 * Read the packet only if we have the whole thing. 9427 */ 9428 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9429 return; 9430 9431 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9432 if (!skb) 9433 return; 9434 9435 skb_put(skb, wupl); 9436 9437 /* Ensure reads are 32-bit aligned */ 9438 wupl = roundup(wupl, 4); 9439 9440 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9441 9442 skb->protocol = eth_type_trans(skb, netdev); 9443 netif_rx(skb); 9444 } 9445 9446 static int igb_suspend(struct device *dev) 9447 { 9448 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9449 } 9450 9451 static int __igb_resume(struct device *dev, bool rpm) 9452 { 9453 struct pci_dev *pdev = to_pci_dev(dev); 9454 struct net_device *netdev = pci_get_drvdata(pdev); 9455 struct igb_adapter *adapter = netdev_priv(netdev); 9456 struct e1000_hw *hw = &adapter->hw; 9457 u32 err, val; 9458 9459 pci_set_power_state(pdev, PCI_D0); 9460 pci_restore_state(pdev); 9461 pci_save_state(pdev); 9462 9463 if (!pci_device_is_present(pdev)) 9464 return -ENODEV; 9465 err = pci_enable_device_mem(pdev); 9466 if (err) { 9467 dev_err(&pdev->dev, 9468 "igb: Cannot enable PCI device from suspend\n"); 9469 return err; 9470 } 9471 pci_set_master(pdev); 9472 9473 pci_enable_wake(pdev, PCI_D3hot, 0); 9474 pci_enable_wake(pdev, PCI_D3cold, 0); 9475 9476 if (igb_init_interrupt_scheme(adapter, true)) { 9477 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9478 return -ENOMEM; 9479 } 9480 9481 igb_reset(adapter); 9482 9483 /* let the f/w know that the h/w is now under the control of the 9484 * driver. 9485 */ 9486 igb_get_hw_control(adapter); 9487 9488 val = rd32(E1000_WUS); 9489 if (val & WAKE_PKT_WUS) 9490 igb_deliver_wake_packet(netdev); 9491 9492 wr32(E1000_WUS, ~0); 9493 9494 if (!rpm) 9495 rtnl_lock(); 9496 if (!err && netif_running(netdev)) 9497 err = __igb_open(netdev, true); 9498 9499 if (!err) 9500 netif_device_attach(netdev); 9501 if (!rpm) 9502 rtnl_unlock(); 9503 9504 return err; 9505 } 9506 9507 static int igb_resume(struct device *dev) 9508 { 9509 return __igb_resume(dev, false); 9510 } 9511 9512 static int igb_runtime_idle(struct device *dev) 9513 { 9514 struct net_device *netdev = dev_get_drvdata(dev); 9515 struct igb_adapter *adapter = netdev_priv(netdev); 9516 9517 if (!igb_has_link(adapter)) 9518 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9519 9520 return -EBUSY; 9521 } 9522 9523 static int igb_runtime_suspend(struct device *dev) 9524 { 9525 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9526 } 9527 9528 static int igb_runtime_resume(struct device *dev) 9529 { 9530 return __igb_resume(dev, true); 9531 } 9532 9533 static void igb_shutdown(struct pci_dev *pdev) 9534 { 9535 bool wake; 9536 9537 __igb_shutdown(pdev, &wake, 0); 9538 9539 if (system_state == SYSTEM_POWER_OFF) { 9540 pci_wake_from_d3(pdev, wake); 9541 pci_set_power_state(pdev, PCI_D3hot); 9542 } 9543 } 9544 9545 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9546 { 9547 #ifdef CONFIG_PCI_IOV 9548 int err; 9549 9550 if (num_vfs == 0) { 9551 return igb_disable_sriov(dev, true); 9552 } else { 9553 err = igb_enable_sriov(dev, num_vfs, true); 9554 return err ? err : num_vfs; 9555 } 9556 #endif 9557 return 0; 9558 } 9559 9560 /** 9561 * igb_io_error_detected - called when PCI error is detected 9562 * @pdev: Pointer to PCI device 9563 * @state: The current pci connection state 9564 * 9565 * This function is called after a PCI bus error affecting 9566 * this device has been detected. 9567 **/ 9568 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9569 pci_channel_state_t state) 9570 { 9571 struct net_device *netdev = pci_get_drvdata(pdev); 9572 struct igb_adapter *adapter = netdev_priv(netdev); 9573 9574 if (state == pci_channel_io_normal) { 9575 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9576 return PCI_ERS_RESULT_CAN_RECOVER; 9577 } 9578 9579 netif_device_detach(netdev); 9580 9581 if (state == pci_channel_io_perm_failure) 9582 return PCI_ERS_RESULT_DISCONNECT; 9583 9584 if (netif_running(netdev)) 9585 igb_down(adapter); 9586 pci_disable_device(pdev); 9587 9588 /* Request a slot reset. */ 9589 return PCI_ERS_RESULT_NEED_RESET; 9590 } 9591 9592 /** 9593 * igb_io_slot_reset - called after the pci bus has been reset. 9594 * @pdev: Pointer to PCI device 9595 * 9596 * Restart the card from scratch, as if from a cold-boot. Implementation 9597 * resembles the first-half of the __igb_resume routine. 9598 **/ 9599 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9600 { 9601 struct net_device *netdev = pci_get_drvdata(pdev); 9602 struct igb_adapter *adapter = netdev_priv(netdev); 9603 struct e1000_hw *hw = &adapter->hw; 9604 pci_ers_result_t result; 9605 9606 if (pci_enable_device_mem(pdev)) { 9607 dev_err(&pdev->dev, 9608 "Cannot re-enable PCI device after reset.\n"); 9609 result = PCI_ERS_RESULT_DISCONNECT; 9610 } else { 9611 pci_set_master(pdev); 9612 pci_restore_state(pdev); 9613 pci_save_state(pdev); 9614 9615 pci_enable_wake(pdev, PCI_D3hot, 0); 9616 pci_enable_wake(pdev, PCI_D3cold, 0); 9617 9618 /* In case of PCI error, adapter lose its HW address 9619 * so we should re-assign it here. 9620 */ 9621 hw->hw_addr = adapter->io_addr; 9622 9623 igb_reset(adapter); 9624 wr32(E1000_WUS, ~0); 9625 result = PCI_ERS_RESULT_RECOVERED; 9626 } 9627 9628 return result; 9629 } 9630 9631 /** 9632 * igb_io_resume - called when traffic can start flowing again. 9633 * @pdev: Pointer to PCI device 9634 * 9635 * This callback is called when the error recovery driver tells us that 9636 * its OK to resume normal operation. Implementation resembles the 9637 * second-half of the __igb_resume routine. 9638 */ 9639 static void igb_io_resume(struct pci_dev *pdev) 9640 { 9641 struct net_device *netdev = pci_get_drvdata(pdev); 9642 struct igb_adapter *adapter = netdev_priv(netdev); 9643 9644 if (netif_running(netdev)) { 9645 if (igb_up(adapter)) { 9646 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9647 return; 9648 } 9649 } 9650 9651 netif_device_attach(netdev); 9652 9653 /* let the f/w know that the h/w is now under the control of the 9654 * driver. 9655 */ 9656 igb_get_hw_control(adapter); 9657 } 9658 9659 /** 9660 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9661 * @adapter: Pointer to adapter structure 9662 * @index: Index of the RAR entry which need to be synced with MAC table 9663 **/ 9664 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9665 { 9666 struct e1000_hw *hw = &adapter->hw; 9667 u32 rar_low, rar_high; 9668 u8 *addr = adapter->mac_table[index].addr; 9669 9670 /* HW expects these to be in network order when they are plugged 9671 * into the registers which are little endian. In order to guarantee 9672 * that ordering we need to do an leXX_to_cpup here in order to be 9673 * ready for the byteswap that occurs with writel 9674 */ 9675 rar_low = le32_to_cpup((__le32 *)(addr)); 9676 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9677 9678 /* Indicate to hardware the Address is Valid. */ 9679 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9680 if (is_valid_ether_addr(addr)) 9681 rar_high |= E1000_RAH_AV; 9682 9683 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9684 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9685 9686 switch (hw->mac.type) { 9687 case e1000_82575: 9688 case e1000_i210: 9689 if (adapter->mac_table[index].state & 9690 IGB_MAC_STATE_QUEUE_STEERING) 9691 rar_high |= E1000_RAH_QSEL_ENABLE; 9692 9693 rar_high |= E1000_RAH_POOL_1 * 9694 adapter->mac_table[index].queue; 9695 break; 9696 default: 9697 rar_high |= E1000_RAH_POOL_1 << 9698 adapter->mac_table[index].queue; 9699 break; 9700 } 9701 } 9702 9703 wr32(E1000_RAL(index), rar_low); 9704 wrfl(); 9705 wr32(E1000_RAH(index), rar_high); 9706 wrfl(); 9707 } 9708 9709 static int igb_set_vf_mac(struct igb_adapter *adapter, 9710 int vf, unsigned char *mac_addr) 9711 { 9712 struct e1000_hw *hw = &adapter->hw; 9713 /* VF MAC addresses start at end of receive addresses and moves 9714 * towards the first, as a result a collision should not be possible 9715 */ 9716 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9717 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9718 9719 ether_addr_copy(vf_mac_addr, mac_addr); 9720 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9721 adapter->mac_table[rar_entry].queue = vf; 9722 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9723 igb_rar_set_index(adapter, rar_entry); 9724 9725 return 0; 9726 } 9727 9728 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9729 { 9730 struct igb_adapter *adapter = netdev_priv(netdev); 9731 9732 if (vf >= adapter->vfs_allocated_count) 9733 return -EINVAL; 9734 9735 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9736 * flag and allows to overwrite the MAC via VF netdev. This 9737 * is necessary to allow libvirt a way to restore the original 9738 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9739 * down a VM. 9740 */ 9741 if (is_zero_ether_addr(mac)) { 9742 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9743 dev_info(&adapter->pdev->dev, 9744 "remove administratively set MAC on VF %d\n", 9745 vf); 9746 } else if (is_valid_ether_addr(mac)) { 9747 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9748 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9749 mac, vf); 9750 dev_info(&adapter->pdev->dev, 9751 "Reload the VF driver to make this change effective."); 9752 /* Generate additional warning if PF is down */ 9753 if (test_bit(__IGB_DOWN, &adapter->state)) { 9754 dev_warn(&adapter->pdev->dev, 9755 "The VF MAC address has been set, but the PF device is not up.\n"); 9756 dev_warn(&adapter->pdev->dev, 9757 "Bring the PF device up before attempting to use the VF device.\n"); 9758 } 9759 } else { 9760 return -EINVAL; 9761 } 9762 return igb_set_vf_mac(adapter, vf, mac); 9763 } 9764 9765 static int igb_link_mbps(int internal_link_speed) 9766 { 9767 switch (internal_link_speed) { 9768 case SPEED_100: 9769 return 100; 9770 case SPEED_1000: 9771 return 1000; 9772 default: 9773 return 0; 9774 } 9775 } 9776 9777 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9778 int link_speed) 9779 { 9780 int rf_dec, rf_int; 9781 u32 bcnrc_val; 9782 9783 if (tx_rate != 0) { 9784 /* Calculate the rate factor values to set */ 9785 rf_int = link_speed / tx_rate; 9786 rf_dec = (link_speed - (rf_int * tx_rate)); 9787 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9788 tx_rate; 9789 9790 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9791 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9792 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9793 } else { 9794 bcnrc_val = 0; 9795 } 9796 9797 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9798 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9799 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9800 */ 9801 wr32(E1000_RTTBCNRM, 0x14); 9802 wr32(E1000_RTTBCNRC, bcnrc_val); 9803 } 9804 9805 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9806 { 9807 int actual_link_speed, i; 9808 bool reset_rate = false; 9809 9810 /* VF TX rate limit was not set or not supported */ 9811 if ((adapter->vf_rate_link_speed == 0) || 9812 (adapter->hw.mac.type != e1000_82576)) 9813 return; 9814 9815 actual_link_speed = igb_link_mbps(adapter->link_speed); 9816 if (actual_link_speed != adapter->vf_rate_link_speed) { 9817 reset_rate = true; 9818 adapter->vf_rate_link_speed = 0; 9819 dev_info(&adapter->pdev->dev, 9820 "Link speed has been changed. VF Transmit rate is disabled\n"); 9821 } 9822 9823 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9824 if (reset_rate) 9825 adapter->vf_data[i].tx_rate = 0; 9826 9827 igb_set_vf_rate_limit(&adapter->hw, i, 9828 adapter->vf_data[i].tx_rate, 9829 actual_link_speed); 9830 } 9831 } 9832 9833 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9834 int min_tx_rate, int max_tx_rate) 9835 { 9836 struct igb_adapter *adapter = netdev_priv(netdev); 9837 struct e1000_hw *hw = &adapter->hw; 9838 int actual_link_speed; 9839 9840 if (hw->mac.type != e1000_82576) 9841 return -EOPNOTSUPP; 9842 9843 if (min_tx_rate) 9844 return -EINVAL; 9845 9846 actual_link_speed = igb_link_mbps(adapter->link_speed); 9847 if ((vf >= adapter->vfs_allocated_count) || 9848 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9849 (max_tx_rate < 0) || 9850 (max_tx_rate > actual_link_speed)) 9851 return -EINVAL; 9852 9853 adapter->vf_rate_link_speed = actual_link_speed; 9854 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9855 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9856 9857 return 0; 9858 } 9859 9860 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9861 bool setting) 9862 { 9863 struct igb_adapter *adapter = netdev_priv(netdev); 9864 struct e1000_hw *hw = &adapter->hw; 9865 u32 reg_val, reg_offset; 9866 9867 if (!adapter->vfs_allocated_count) 9868 return -EOPNOTSUPP; 9869 9870 if (vf >= adapter->vfs_allocated_count) 9871 return -EINVAL; 9872 9873 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9874 reg_val = rd32(reg_offset); 9875 if (setting) 9876 reg_val |= (BIT(vf) | 9877 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9878 else 9879 reg_val &= ~(BIT(vf) | 9880 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9881 wr32(reg_offset, reg_val); 9882 9883 adapter->vf_data[vf].spoofchk_enabled = setting; 9884 return 0; 9885 } 9886 9887 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9888 { 9889 struct igb_adapter *adapter = netdev_priv(netdev); 9890 9891 if (vf >= adapter->vfs_allocated_count) 9892 return -EINVAL; 9893 if (adapter->vf_data[vf].trusted == setting) 9894 return 0; 9895 9896 adapter->vf_data[vf].trusted = setting; 9897 9898 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9899 vf, setting ? "" : "not "); 9900 return 0; 9901 } 9902 9903 static int igb_ndo_get_vf_config(struct net_device *netdev, 9904 int vf, struct ifla_vf_info *ivi) 9905 { 9906 struct igb_adapter *adapter = netdev_priv(netdev); 9907 if (vf >= adapter->vfs_allocated_count) 9908 return -EINVAL; 9909 ivi->vf = vf; 9910 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9911 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9912 ivi->min_tx_rate = 0; 9913 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9914 ivi->qos = adapter->vf_data[vf].pf_qos; 9915 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9916 ivi->trusted = adapter->vf_data[vf].trusted; 9917 return 0; 9918 } 9919 9920 static void igb_vmm_control(struct igb_adapter *adapter) 9921 { 9922 struct e1000_hw *hw = &adapter->hw; 9923 u32 reg; 9924 9925 switch (hw->mac.type) { 9926 case e1000_82575: 9927 case e1000_i210: 9928 case e1000_i211: 9929 case e1000_i354: 9930 default: 9931 /* replication is not supported for 82575 */ 9932 return; 9933 case e1000_82576: 9934 /* notify HW that the MAC is adding vlan tags */ 9935 reg = rd32(E1000_DTXCTL); 9936 reg |= E1000_DTXCTL_VLAN_ADDED; 9937 wr32(E1000_DTXCTL, reg); 9938 fallthrough; 9939 case e1000_82580: 9940 /* enable replication vlan tag stripping */ 9941 reg = rd32(E1000_RPLOLR); 9942 reg |= E1000_RPLOLR_STRVLAN; 9943 wr32(E1000_RPLOLR, reg); 9944 fallthrough; 9945 case e1000_i350: 9946 /* none of the above registers are supported by i350 */ 9947 break; 9948 } 9949 9950 if (adapter->vfs_allocated_count) { 9951 igb_vmdq_set_loopback_pf(hw, true); 9952 igb_vmdq_set_replication_pf(hw, true); 9953 igb_vmdq_set_anti_spoofing_pf(hw, true, 9954 adapter->vfs_allocated_count); 9955 } else { 9956 igb_vmdq_set_loopback_pf(hw, false); 9957 igb_vmdq_set_replication_pf(hw, false); 9958 } 9959 } 9960 9961 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9962 { 9963 struct e1000_hw *hw = &adapter->hw; 9964 u32 dmac_thr; 9965 u16 hwm; 9966 u32 reg; 9967 9968 if (hw->mac.type > e1000_82580) { 9969 if (adapter->flags & IGB_FLAG_DMAC) { 9970 /* force threshold to 0. */ 9971 wr32(E1000_DMCTXTH, 0); 9972 9973 /* DMA Coalescing high water mark needs to be greater 9974 * than the Rx threshold. Set hwm to PBA - max frame 9975 * size in 16B units, capping it at PBA - 6KB. 9976 */ 9977 hwm = 64 * (pba - 6); 9978 reg = rd32(E1000_FCRTC); 9979 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9980 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 9981 wr32(E1000_FCRTC, reg); 9982 9983 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9984 * frame size, capping it at PBA - 10KB. 9985 */ 9986 dmac_thr = pba - 10; 9987 reg = rd32(E1000_DMACR); 9988 reg &= ~E1000_DMACR_DMACTHR_MASK; 9989 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 9990 9991 /* transition to L0x or L1 if available..*/ 9992 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9993 9994 /* watchdog timer= +-1000 usec in 32usec intervals */ 9995 reg |= (1000 >> 5); 9996 9997 /* Disable BMC-to-OS Watchdog Enable */ 9998 if (hw->mac.type != e1000_i354) 9999 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10000 wr32(E1000_DMACR, reg); 10001 10002 /* no lower threshold to disable 10003 * coalescing(smart fifb)-UTRESH=0 10004 */ 10005 wr32(E1000_DMCRTRH, 0); 10006 10007 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10008 10009 wr32(E1000_DMCTLX, reg); 10010 10011 /* free space in tx packet buffer to wake from 10012 * DMA coal 10013 */ 10014 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10015 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10016 } 10017 10018 if (hw->mac.type >= e1000_i210 || 10019 (adapter->flags & IGB_FLAG_DMAC)) { 10020 reg = rd32(E1000_PCIEMISC); 10021 reg |= E1000_PCIEMISC_LX_DECISION; 10022 wr32(E1000_PCIEMISC, reg); 10023 } /* endif adapter->dmac is not disabled */ 10024 } else if (hw->mac.type == e1000_82580) { 10025 u32 reg = rd32(E1000_PCIEMISC); 10026 10027 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10028 wr32(E1000_DMACR, 0); 10029 } 10030 } 10031 10032 /** 10033 * igb_read_i2c_byte - Reads 8 bit word over I2C 10034 * @hw: pointer to hardware structure 10035 * @byte_offset: byte offset to read 10036 * @dev_addr: device address 10037 * @data: value read 10038 * 10039 * Performs byte read operation over I2C interface at 10040 * a specified device address. 10041 **/ 10042 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10043 u8 dev_addr, u8 *data) 10044 { 10045 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10046 struct i2c_client *this_client = adapter->i2c_client; 10047 s32 status; 10048 u16 swfw_mask = 0; 10049 10050 if (!this_client) 10051 return E1000_ERR_I2C; 10052 10053 swfw_mask = E1000_SWFW_PHY0_SM; 10054 10055 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10056 return E1000_ERR_SWFW_SYNC; 10057 10058 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10059 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10060 10061 if (status < 0) 10062 return E1000_ERR_I2C; 10063 else { 10064 *data = status; 10065 return 0; 10066 } 10067 } 10068 10069 /** 10070 * igb_write_i2c_byte - Writes 8 bit word over I2C 10071 * @hw: pointer to hardware structure 10072 * @byte_offset: byte offset to write 10073 * @dev_addr: device address 10074 * @data: value to write 10075 * 10076 * Performs byte write operation over I2C interface at 10077 * a specified device address. 10078 **/ 10079 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10080 u8 dev_addr, u8 data) 10081 { 10082 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10083 struct i2c_client *this_client = adapter->i2c_client; 10084 s32 status; 10085 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10086 10087 if (!this_client) 10088 return E1000_ERR_I2C; 10089 10090 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10091 return E1000_ERR_SWFW_SYNC; 10092 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10093 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10094 10095 if (status) 10096 return E1000_ERR_I2C; 10097 else 10098 return 0; 10099 10100 } 10101 10102 int igb_reinit_queues(struct igb_adapter *adapter) 10103 { 10104 struct net_device *netdev = adapter->netdev; 10105 struct pci_dev *pdev = adapter->pdev; 10106 int err = 0; 10107 10108 if (netif_running(netdev)) 10109 igb_close(netdev); 10110 10111 igb_reset_interrupt_capability(adapter); 10112 10113 if (igb_init_interrupt_scheme(adapter, true)) { 10114 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10115 return -ENOMEM; 10116 } 10117 10118 if (netif_running(netdev)) 10119 err = igb_open(netdev); 10120 10121 return err; 10122 } 10123 10124 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10125 { 10126 struct igb_nfc_filter *rule; 10127 10128 spin_lock(&adapter->nfc_lock); 10129 10130 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10131 igb_erase_filter(adapter, rule); 10132 10133 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10134 igb_erase_filter(adapter, rule); 10135 10136 spin_unlock(&adapter->nfc_lock); 10137 } 10138 10139 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10140 { 10141 struct igb_nfc_filter *rule; 10142 10143 spin_lock(&adapter->nfc_lock); 10144 10145 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10146 igb_add_filter(adapter, rule); 10147 10148 spin_unlock(&adapter->nfc_lock); 10149 } 10150 10151 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10152 igb_runtime_suspend, igb_runtime_resume, 10153 igb_runtime_idle); 10154 10155 static struct pci_driver igb_driver = { 10156 .name = igb_driver_name, 10157 .id_table = igb_pci_tbl, 10158 .probe = igb_probe, 10159 .remove = igb_remove, 10160 .driver.pm = pm_ptr(&igb_pm_ops), 10161 .shutdown = igb_shutdown, 10162 .sriov_configure = igb_pci_sriov_configure, 10163 .err_handler = &igb_err_handler 10164 }; 10165 10166 /* igb_main.c */ 10167