1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 3 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 170 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 171 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 172 int vf, u16 vlan, u8 qos); 173 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 174 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 180 #ifdef CONFIG_PCI_IOV 181 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 182 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 183 static int igb_disable_sriov(struct pci_dev *dev); 184 static int igb_pci_disable_sriov(struct pci_dev *dev); 185 #endif 186 187 #ifdef CONFIG_PM 188 #ifdef CONFIG_PM_SLEEP 189 static int igb_suspend(struct device *); 190 #endif 191 static int igb_resume(struct device *); 192 static int igb_runtime_suspend(struct device *dev); 193 static int igb_runtime_resume(struct device *dev); 194 static int igb_runtime_idle(struct device *dev); 195 static const struct dev_pm_ops igb_pm_ops = { 196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 198 igb_runtime_idle) 199 }; 200 #endif 201 static void igb_shutdown(struct pci_dev *); 202 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 203 #ifdef CONFIG_IGB_DCA 204 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 205 static struct notifier_block dca_notifier = { 206 .notifier_call = igb_notify_dca, 207 .next = NULL, 208 .priority = 0 209 }; 210 #endif 211 #ifdef CONFIG_NET_POLL_CONTROLLER 212 /* for netdump / net console */ 213 static void igb_netpoll(struct net_device *); 214 #endif 215 #ifdef CONFIG_PCI_IOV 216 static unsigned int max_vfs; 217 module_param(max_vfs, uint, 0); 218 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 219 #endif /* CONFIG_PCI_IOV */ 220 221 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 222 pci_channel_state_t); 223 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 224 static void igb_io_resume(struct pci_dev *); 225 226 static const struct pci_error_handlers igb_err_handler = { 227 .error_detected = igb_io_error_detected, 228 .slot_reset = igb_io_slot_reset, 229 .resume = igb_io_resume, 230 }; 231 232 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 233 234 static struct pci_driver igb_driver = { 235 .name = igb_driver_name, 236 .id_table = igb_pci_tbl, 237 .probe = igb_probe, 238 .remove = igb_remove, 239 #ifdef CONFIG_PM 240 .driver.pm = &igb_pm_ops, 241 #endif 242 .shutdown = igb_shutdown, 243 .sriov_configure = igb_pci_sriov_configure, 244 .err_handler = &igb_err_handler 245 }; 246 247 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 248 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 249 MODULE_LICENSE("GPL"); 250 MODULE_VERSION(DRV_VERSION); 251 252 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 253 static int debug = -1; 254 module_param(debug, int, 0); 255 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 256 257 struct igb_reg_info { 258 u32 ofs; 259 char *name; 260 }; 261 262 static const struct igb_reg_info igb_reg_info_tbl[] = { 263 264 /* General Registers */ 265 {E1000_CTRL, "CTRL"}, 266 {E1000_STATUS, "STATUS"}, 267 {E1000_CTRL_EXT, "CTRL_EXT"}, 268 269 /* Interrupt Registers */ 270 {E1000_ICR, "ICR"}, 271 272 /* RX Registers */ 273 {E1000_RCTL, "RCTL"}, 274 {E1000_RDLEN(0), "RDLEN"}, 275 {E1000_RDH(0), "RDH"}, 276 {E1000_RDT(0), "RDT"}, 277 {E1000_RXDCTL(0), "RXDCTL"}, 278 {E1000_RDBAL(0), "RDBAL"}, 279 {E1000_RDBAH(0), "RDBAH"}, 280 281 /* TX Registers */ 282 {E1000_TCTL, "TCTL"}, 283 {E1000_TDBAL(0), "TDBAL"}, 284 {E1000_TDBAH(0), "TDBAH"}, 285 {E1000_TDLEN(0), "TDLEN"}, 286 {E1000_TDH(0), "TDH"}, 287 {E1000_TDT(0), "TDT"}, 288 {E1000_TXDCTL(0), "TXDCTL"}, 289 {E1000_TDFH, "TDFH"}, 290 {E1000_TDFT, "TDFT"}, 291 {E1000_TDFHS, "TDFHS"}, 292 {E1000_TDFPC, "TDFPC"}, 293 294 /* List Terminator */ 295 {} 296 }; 297 298 /* igb_regdump - register printout routine */ 299 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 300 { 301 int n = 0; 302 char rname[16]; 303 u32 regs[8]; 304 305 switch (reginfo->ofs) { 306 case E1000_RDLEN(0): 307 for (n = 0; n < 4; n++) 308 regs[n] = rd32(E1000_RDLEN(n)); 309 break; 310 case E1000_RDH(0): 311 for (n = 0; n < 4; n++) 312 regs[n] = rd32(E1000_RDH(n)); 313 break; 314 case E1000_RDT(0): 315 for (n = 0; n < 4; n++) 316 regs[n] = rd32(E1000_RDT(n)); 317 break; 318 case E1000_RXDCTL(0): 319 for (n = 0; n < 4; n++) 320 regs[n] = rd32(E1000_RXDCTL(n)); 321 break; 322 case E1000_RDBAL(0): 323 for (n = 0; n < 4; n++) 324 regs[n] = rd32(E1000_RDBAL(n)); 325 break; 326 case E1000_RDBAH(0): 327 for (n = 0; n < 4; n++) 328 regs[n] = rd32(E1000_RDBAH(n)); 329 break; 330 case E1000_TDBAL(0): 331 for (n = 0; n < 4; n++) 332 regs[n] = rd32(E1000_RDBAL(n)); 333 break; 334 case E1000_TDBAH(0): 335 for (n = 0; n < 4; n++) 336 regs[n] = rd32(E1000_TDBAH(n)); 337 break; 338 case E1000_TDLEN(0): 339 for (n = 0; n < 4; n++) 340 regs[n] = rd32(E1000_TDLEN(n)); 341 break; 342 case E1000_TDH(0): 343 for (n = 0; n < 4; n++) 344 regs[n] = rd32(E1000_TDH(n)); 345 break; 346 case E1000_TDT(0): 347 for (n = 0; n < 4; n++) 348 regs[n] = rd32(E1000_TDT(n)); 349 break; 350 case E1000_TXDCTL(0): 351 for (n = 0; n < 4; n++) 352 regs[n] = rd32(E1000_TXDCTL(n)); 353 break; 354 default: 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 356 return; 357 } 358 359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 361 regs[2], regs[3]); 362 } 363 364 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 365 static void igb_dump(struct igb_adapter *adapter) 366 { 367 struct net_device *netdev = adapter->netdev; 368 struct e1000_hw *hw = &adapter->hw; 369 struct igb_reg_info *reginfo; 370 struct igb_ring *tx_ring; 371 union e1000_adv_tx_desc *tx_desc; 372 struct my_u0 { u64 a; u64 b; } *u0; 373 struct igb_ring *rx_ring; 374 union e1000_adv_rx_desc *rx_desc; 375 u32 staterr; 376 u16 i, n; 377 378 if (!netif_msg_hw(adapter)) 379 return; 380 381 /* Print netdevice Info */ 382 if (netdev) { 383 dev_info(&adapter->pdev->dev, "Net device Info\n"); 384 pr_info("Device Name state trans_start last_rx\n"); 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 386 netdev->state, dev_trans_start(netdev), netdev->last_rx); 387 } 388 389 /* Print Registers */ 390 dev_info(&adapter->pdev->dev, "Register Dump\n"); 391 pr_info(" Register Name Value\n"); 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 393 reginfo->name; reginfo++) { 394 igb_regdump(hw, reginfo); 395 } 396 397 /* Print TX Ring Summary */ 398 if (!netdev || !netif_running(netdev)) 399 goto exit; 400 401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 403 for (n = 0; n < adapter->num_tx_queues; n++) { 404 struct igb_tx_buffer *buffer_info; 405 tx_ring = adapter->tx_ring[n]; 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 408 n, tx_ring->next_to_use, tx_ring->next_to_clean, 409 (u64)dma_unmap_addr(buffer_info, dma), 410 dma_unmap_len(buffer_info, len), 411 buffer_info->next_to_watch, 412 (u64)buffer_info->time_stamp); 413 } 414 415 /* Print TX Rings */ 416 if (!netif_msg_tx_done(adapter)) 417 goto rx_ring_summary; 418 419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 420 421 /* Transmit Descriptor Formats 422 * 423 * Advanced Transmit Descriptor 424 * +--------------------------------------------------------------+ 425 * 0 | Buffer Address [63:0] | 426 * +--------------------------------------------------------------+ 427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 428 * +--------------------------------------------------------------+ 429 * 63 46 45 40 39 38 36 35 32 31 24 15 0 430 */ 431 432 for (n = 0; n < adapter->num_tx_queues; n++) { 433 tx_ring = adapter->tx_ring[n]; 434 pr_info("------------------------------------\n"); 435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 436 pr_info("------------------------------------\n"); 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 438 439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 440 const char *next_desc; 441 struct igb_tx_buffer *buffer_info; 442 tx_desc = IGB_TX_DESC(tx_ring, i); 443 buffer_info = &tx_ring->tx_buffer_info[i]; 444 u0 = (struct my_u0 *)tx_desc; 445 if (i == tx_ring->next_to_use && 446 i == tx_ring->next_to_clean) 447 next_desc = " NTC/U"; 448 else if (i == tx_ring->next_to_use) 449 next_desc = " NTU"; 450 else if (i == tx_ring->next_to_clean) 451 next_desc = " NTC"; 452 else 453 next_desc = ""; 454 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 456 i, le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)dma_unmap_addr(buffer_info, dma), 459 dma_unmap_len(buffer_info, len), 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 dma_unmap_len(buffer_info, len), 469 true); 470 } 471 } 472 473 /* Print RX Rings Summary */ 474 rx_ring_summary: 475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 476 pr_info("Queue [NTU] [NTC]\n"); 477 for (n = 0; n < adapter->num_rx_queues; n++) { 478 rx_ring = adapter->rx_ring[n]; 479 pr_info(" %5d %5X %5X\n", 480 n, rx_ring->next_to_use, rx_ring->next_to_clean); 481 } 482 483 /* Print RX Rings */ 484 if (!netif_msg_rx_status(adapter)) 485 goto exit; 486 487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 488 489 /* Advanced Receive Descriptor (Read) Format 490 * 63 1 0 491 * +-----------------------------------------------------+ 492 * 0 | Packet Buffer Address [63:1] |A0/NSE| 493 * +----------------------------------------------+------+ 494 * 8 | Header Buffer Address [63:1] | DD | 495 * +-----------------------------------------------------+ 496 * 497 * 498 * Advanced Receive Descriptor (Write-Back) Format 499 * 500 * 63 48 47 32 31 30 21 20 17 16 4 3 0 501 * +------------------------------------------------------+ 502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 503 * | Checksum Ident | | | | Type | Type | 504 * +------------------------------------------------------+ 505 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 506 * +------------------------------------------------------+ 507 * 63 48 47 32 31 20 19 0 508 */ 509 510 for (n = 0; n < adapter->num_rx_queues; n++) { 511 rx_ring = adapter->rx_ring[n]; 512 pr_info("------------------------------------\n"); 513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 514 pr_info("------------------------------------\n"); 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 517 518 for (i = 0; i < rx_ring->count; i++) { 519 const char *next_desc; 520 struct igb_rx_buffer *buffer_info; 521 buffer_info = &rx_ring->rx_buffer_info[i]; 522 rx_desc = IGB_RX_DESC(rx_ring, i); 523 u0 = (struct my_u0 *)rx_desc; 524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 525 526 if (i == rx_ring->next_to_use) 527 next_desc = " NTU"; 528 else if (i == rx_ring->next_to_clean) 529 next_desc = " NTC"; 530 else 531 next_desc = ""; 532 533 if (staterr & E1000_RXD_STAT_DD) { 534 /* Descriptor Done */ 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 536 "RWB", i, 537 le64_to_cpu(u0->a), 538 le64_to_cpu(u0->b), 539 next_desc); 540 } else { 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 542 "R ", i, 543 le64_to_cpu(u0->a), 544 le64_to_cpu(u0->b), 545 (u64)buffer_info->dma, 546 next_desc); 547 548 if (netif_msg_pktdata(adapter) && 549 buffer_info->dma && buffer_info->page) { 550 print_hex_dump(KERN_INFO, "", 551 DUMP_PREFIX_ADDRESS, 552 16, 1, 553 page_address(buffer_info->page) + 554 buffer_info->page_offset, 555 IGB_RX_BUFSZ, true); 556 } 557 } 558 } 559 } 560 561 exit: 562 return; 563 } 564 565 /** 566 * igb_get_i2c_data - Reads the I2C SDA data bit 567 * @hw: pointer to hardware structure 568 * @i2cctl: Current value of I2CCTL register 569 * 570 * Returns the I2C data bit value 571 **/ 572 static int igb_get_i2c_data(void *data) 573 { 574 struct igb_adapter *adapter = (struct igb_adapter *)data; 575 struct e1000_hw *hw = &adapter->hw; 576 s32 i2cctl = rd32(E1000_I2CPARAMS); 577 578 return !!(i2cctl & E1000_I2C_DATA_IN); 579 } 580 581 /** 582 * igb_set_i2c_data - Sets the I2C data bit 583 * @data: pointer to hardware structure 584 * @state: I2C data value (0 or 1) to set 585 * 586 * Sets the I2C data bit 587 **/ 588 static void igb_set_i2c_data(void *data, int state) 589 { 590 struct igb_adapter *adapter = (struct igb_adapter *)data; 591 struct e1000_hw *hw = &adapter->hw; 592 s32 i2cctl = rd32(E1000_I2CPARAMS); 593 594 if (state) 595 i2cctl |= E1000_I2C_DATA_OUT; 596 else 597 i2cctl &= ~E1000_I2C_DATA_OUT; 598 599 i2cctl &= ~E1000_I2C_DATA_OE_N; 600 i2cctl |= E1000_I2C_CLK_OE_N; 601 wr32(E1000_I2CPARAMS, i2cctl); 602 wrfl(); 603 604 } 605 606 /** 607 * igb_set_i2c_clk - Sets the I2C SCL clock 608 * @data: pointer to hardware structure 609 * @state: state to set clock 610 * 611 * Sets the I2C clock line to state 612 **/ 613 static void igb_set_i2c_clk(void *data, int state) 614 { 615 struct igb_adapter *adapter = (struct igb_adapter *)data; 616 struct e1000_hw *hw = &adapter->hw; 617 s32 i2cctl = rd32(E1000_I2CPARAMS); 618 619 if (state) { 620 i2cctl |= E1000_I2C_CLK_OUT; 621 i2cctl &= ~E1000_I2C_CLK_OE_N; 622 } else { 623 i2cctl &= ~E1000_I2C_CLK_OUT; 624 i2cctl &= ~E1000_I2C_CLK_OE_N; 625 } 626 wr32(E1000_I2CPARAMS, i2cctl); 627 wrfl(); 628 } 629 630 /** 631 * igb_get_i2c_clk - Gets the I2C SCL clock state 632 * @data: pointer to hardware structure 633 * 634 * Gets the I2C clock state 635 **/ 636 static int igb_get_i2c_clk(void *data) 637 { 638 struct igb_adapter *adapter = (struct igb_adapter *)data; 639 struct e1000_hw *hw = &adapter->hw; 640 s32 i2cctl = rd32(E1000_I2CPARAMS); 641 642 return !!(i2cctl & E1000_I2C_CLK_IN); 643 } 644 645 static const struct i2c_algo_bit_data igb_i2c_algo = { 646 .setsda = igb_set_i2c_data, 647 .setscl = igb_set_i2c_clk, 648 .getsda = igb_get_i2c_data, 649 .getscl = igb_get_i2c_clk, 650 .udelay = 5, 651 .timeout = 20, 652 }; 653 654 /** 655 * igb_get_hw_dev - return device 656 * @hw: pointer to hardware structure 657 * 658 * used by hardware layer to print debugging information 659 **/ 660 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 661 { 662 struct igb_adapter *adapter = hw->back; 663 return adapter->netdev; 664 } 665 666 /** 667 * igb_init_module - Driver Registration Routine 668 * 669 * igb_init_module is the first routine called when the driver is 670 * loaded. All it does is register with the PCI subsystem. 671 **/ 672 static int __init igb_init_module(void) 673 { 674 int ret; 675 676 pr_info("%s - version %s\n", 677 igb_driver_string, igb_driver_version); 678 pr_info("%s\n", igb_copyright); 679 680 #ifdef CONFIG_IGB_DCA 681 dca_register_notify(&dca_notifier); 682 #endif 683 ret = pci_register_driver(&igb_driver); 684 return ret; 685 } 686 687 module_init(igb_init_module); 688 689 /** 690 * igb_exit_module - Driver Exit Cleanup Routine 691 * 692 * igb_exit_module is called just before the driver is removed 693 * from memory. 694 **/ 695 static void __exit igb_exit_module(void) 696 { 697 #ifdef CONFIG_IGB_DCA 698 dca_unregister_notify(&dca_notifier); 699 #endif 700 pci_unregister_driver(&igb_driver); 701 } 702 703 module_exit(igb_exit_module); 704 705 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 706 /** 707 * igb_cache_ring_register - Descriptor ring to register mapping 708 * @adapter: board private structure to initialize 709 * 710 * Once we know the feature-set enabled for the device, we'll cache 711 * the register offset the descriptor ring is assigned to. 712 **/ 713 static void igb_cache_ring_register(struct igb_adapter *adapter) 714 { 715 int i = 0, j = 0; 716 u32 rbase_offset = adapter->vfs_allocated_count; 717 718 switch (adapter->hw.mac.type) { 719 case e1000_82576: 720 /* The queues are allocated for virtualization such that VF 0 721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 722 * In order to avoid collision we start at the first free queue 723 * and continue consuming queues in the same sequence 724 */ 725 if (adapter->vfs_allocated_count) { 726 for (; i < adapter->rss_queues; i++) 727 adapter->rx_ring[i]->reg_idx = rbase_offset + 728 Q_IDX_82576(i); 729 } 730 /* Fall through */ 731 case e1000_82575: 732 case e1000_82580: 733 case e1000_i350: 734 case e1000_i354: 735 case e1000_i210: 736 case e1000_i211: 737 /* Fall through */ 738 default: 739 for (; i < adapter->num_rx_queues; i++) 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 741 for (; j < adapter->num_tx_queues; j++) 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 743 break; 744 } 745 } 746 747 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 748 { 749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 751 u32 value = 0; 752 753 if (E1000_REMOVED(hw_addr)) 754 return ~value; 755 756 value = readl(&hw_addr[reg]); 757 758 /* reads should not return all F's */ 759 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 760 struct net_device *netdev = igb->netdev; 761 hw->hw_addr = NULL; 762 netif_device_detach(netdev); 763 netdev_err(netdev, "PCIe link lost, device now detached\n"); 764 } 765 766 return value; 767 } 768 769 /** 770 * igb_write_ivar - configure ivar for given MSI-X vector 771 * @hw: pointer to the HW structure 772 * @msix_vector: vector number we are allocating to a given ring 773 * @index: row index of IVAR register to write within IVAR table 774 * @offset: column offset of in IVAR, should be multiple of 8 775 * 776 * This function is intended to handle the writing of the IVAR register 777 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 778 * each containing an cause allocation for an Rx and Tx ring, and a 779 * variable number of rows depending on the number of queues supported. 780 **/ 781 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 782 int index, int offset) 783 { 784 u32 ivar = array_rd32(E1000_IVAR0, index); 785 786 /* clear any bits that are currently set */ 787 ivar &= ~((u32)0xFF << offset); 788 789 /* write vector and valid bit */ 790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 791 792 array_wr32(E1000_IVAR0, index, ivar); 793 } 794 795 #define IGB_N0_QUEUE -1 796 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 797 { 798 struct igb_adapter *adapter = q_vector->adapter; 799 struct e1000_hw *hw = &adapter->hw; 800 int rx_queue = IGB_N0_QUEUE; 801 int tx_queue = IGB_N0_QUEUE; 802 u32 msixbm = 0; 803 804 if (q_vector->rx.ring) 805 rx_queue = q_vector->rx.ring->reg_idx; 806 if (q_vector->tx.ring) 807 tx_queue = q_vector->tx.ring->reg_idx; 808 809 switch (hw->mac.type) { 810 case e1000_82575: 811 /* The 82575 assigns vectors using a bitmask, which matches the 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one 813 * or more queues to a vector, we write the appropriate bits 814 * into the MSIXBM register for that vector. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 818 if (tx_queue > IGB_N0_QUEUE) 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 821 msixbm |= E1000_EIMS_OTHER; 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 823 q_vector->eims_value = msixbm; 824 break; 825 case e1000_82576: 826 /* 82576 uses a table that essentially consists of 2 columns 827 * with 8 rows. The ordering is column-major so we use the 828 * lower 3 bits as the row index, and the 4th bit as the 829 * column offset. 830 */ 831 if (rx_queue > IGB_N0_QUEUE) 832 igb_write_ivar(hw, msix_vector, 833 rx_queue & 0x7, 834 (rx_queue & 0x8) << 1); 835 if (tx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 tx_queue & 0x7, 838 ((tx_queue & 0x8) << 1) + 8); 839 q_vector->eims_value = BIT(msix_vector); 840 break; 841 case e1000_82580: 842 case e1000_i350: 843 case e1000_i354: 844 case e1000_i210: 845 case e1000_i211: 846 /* On 82580 and newer adapters the scheme is similar to 82576 847 * however instead of ordering column-major we have things 848 * ordered row-major. So we traverse the table by using 849 * bit 0 as the column offset, and the remaining bits as the 850 * row index. 851 */ 852 if (rx_queue > IGB_N0_QUEUE) 853 igb_write_ivar(hw, msix_vector, 854 rx_queue >> 1, 855 (rx_queue & 0x1) << 4); 856 if (tx_queue > IGB_N0_QUEUE) 857 igb_write_ivar(hw, msix_vector, 858 tx_queue >> 1, 859 ((tx_queue & 0x1) << 4) + 8); 860 q_vector->eims_value = BIT(msix_vector); 861 break; 862 default: 863 BUG(); 864 break; 865 } 866 867 /* add q_vector eims value to global eims_enable_mask */ 868 adapter->eims_enable_mask |= q_vector->eims_value; 869 870 /* configure q_vector to set itr on first interrupt */ 871 q_vector->set_itr = 1; 872 } 873 874 /** 875 * igb_configure_msix - Configure MSI-X hardware 876 * @adapter: board private structure to initialize 877 * 878 * igb_configure_msix sets up the hardware to properly 879 * generate MSI-X interrupts. 880 **/ 881 static void igb_configure_msix(struct igb_adapter *adapter) 882 { 883 u32 tmp; 884 int i, vector = 0; 885 struct e1000_hw *hw = &adapter->hw; 886 887 adapter->eims_enable_mask = 0; 888 889 /* set vector for other causes, i.e. link changes */ 890 switch (hw->mac.type) { 891 case e1000_82575: 892 tmp = rd32(E1000_CTRL_EXT); 893 /* enable MSI-X PBA support*/ 894 tmp |= E1000_CTRL_EXT_PBA_CLR; 895 896 /* Auto-Mask interrupts upon ICR read. */ 897 tmp |= E1000_CTRL_EXT_EIAME; 898 tmp |= E1000_CTRL_EXT_IRCA; 899 900 wr32(E1000_CTRL_EXT, tmp); 901 902 /* enable msix_other interrupt */ 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 904 adapter->eims_other = E1000_EIMS_OTHER; 905 906 break; 907 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 case e1000_i210: 913 case e1000_i211: 914 /* Turn on MSI-X capability first, or our settings 915 * won't stick. And it will take days to debug. 916 */ 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 918 E1000_GPIE_PBA | E1000_GPIE_EIAME | 919 E1000_GPIE_NSICR); 920 921 /* enable msix_other interrupt */ 922 adapter->eims_other = BIT(vector); 923 tmp = (vector++ | E1000_IVAR_VALID) << 8; 924 925 wr32(E1000_IVAR_MISC, tmp); 926 break; 927 default: 928 /* do nothing, since nothing else supports MSI-X */ 929 break; 930 } /* switch (hw->mac.type) */ 931 932 adapter->eims_enable_mask |= adapter->eims_other; 933 934 for (i = 0; i < adapter->num_q_vectors; i++) 935 igb_assign_vector(adapter->q_vector[i], vector++); 936 937 wrfl(); 938 } 939 940 /** 941 * igb_request_msix - Initialize MSI-X interrupts 942 * @adapter: board private structure to initialize 943 * 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 945 * kernel. 946 **/ 947 static int igb_request_msix(struct igb_adapter *adapter) 948 { 949 struct net_device *netdev = adapter->netdev; 950 int i, err = 0, vector = 0, free_vector = 0; 951 952 err = request_irq(adapter->msix_entries[vector].vector, 953 igb_msix_other, 0, netdev->name, adapter); 954 if (err) 955 goto err_out; 956 957 for (i = 0; i < adapter->num_q_vectors; i++) { 958 struct igb_q_vector *q_vector = adapter->q_vector[i]; 959 960 vector++; 961 962 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 963 964 if (q_vector->rx.ring && q_vector->tx.ring) 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 966 q_vector->rx.ring->queue_index); 967 else if (q_vector->tx.ring) 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 969 q_vector->tx.ring->queue_index); 970 else if (q_vector->rx.ring) 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 972 q_vector->rx.ring->queue_index); 973 else 974 sprintf(q_vector->name, "%s-unused", netdev->name); 975 976 err = request_irq(adapter->msix_entries[vector].vector, 977 igb_msix_ring, 0, q_vector->name, 978 q_vector); 979 if (err) 980 goto err_free; 981 } 982 983 igb_configure_msix(adapter); 984 return 0; 985 986 err_free: 987 /* free already assigned IRQs */ 988 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 989 990 vector--; 991 for (i = 0; i < vector; i++) { 992 free_irq(adapter->msix_entries[free_vector++].vector, 993 adapter->q_vector[i]); 994 } 995 err_out: 996 return err; 997 } 998 999 /** 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1001 * @adapter: board private structure to initialize 1002 * @v_idx: Index of vector to be freed 1003 * 1004 * This function frees the memory allocated to the q_vector. 1005 **/ 1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1007 { 1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1009 1010 adapter->q_vector[v_idx] = NULL; 1011 1012 /* igb_get_stats64() might access the rings on this vector, 1013 * we must wait a grace period before freeing it. 1014 */ 1015 if (q_vector) 1016 kfree_rcu(q_vector, rcu); 1017 } 1018 1019 /** 1020 * igb_reset_q_vector - Reset config for interrupt vector 1021 * @adapter: board private structure to initialize 1022 * @v_idx: Index of vector to be reset 1023 * 1024 * If NAPI is enabled it will delete any references to the 1025 * NAPI struct. This is preparation for igb_free_q_vector. 1026 **/ 1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1028 { 1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1030 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1032 * allocated. So, q_vector is NULL so we should stop here. 1033 */ 1034 if (!q_vector) 1035 return; 1036 1037 if (q_vector->tx.ring) 1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1039 1040 if (q_vector->rx.ring) 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1042 1043 netif_napi_del(&q_vector->napi); 1044 1045 } 1046 1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1048 { 1049 int v_idx = adapter->num_q_vectors; 1050 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1052 pci_disable_msix(adapter->pdev); 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1054 pci_disable_msi(adapter->pdev); 1055 1056 while (v_idx--) 1057 igb_reset_q_vector(adapter, v_idx); 1058 } 1059 1060 /** 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1062 * @adapter: board private structure to initialize 1063 * 1064 * This function frees the memory allocated to the q_vectors. In addition if 1065 * NAPI is enabled it will delete any references to the NAPI struct prior 1066 * to freeing the q_vector. 1067 **/ 1068 static void igb_free_q_vectors(struct igb_adapter *adapter) 1069 { 1070 int v_idx = adapter->num_q_vectors; 1071 1072 adapter->num_tx_queues = 0; 1073 adapter->num_rx_queues = 0; 1074 adapter->num_q_vectors = 0; 1075 1076 while (v_idx--) { 1077 igb_reset_q_vector(adapter, v_idx); 1078 igb_free_q_vector(adapter, v_idx); 1079 } 1080 } 1081 1082 /** 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1084 * @adapter: board private structure to initialize 1085 * 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1087 * MSI-X interrupts allocated. 1088 */ 1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1090 { 1091 igb_free_q_vectors(adapter); 1092 igb_reset_interrupt_capability(adapter); 1093 } 1094 1095 /** 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1097 * @adapter: board private structure to initialize 1098 * @msix: boolean value of MSIX capability 1099 * 1100 * Attempt to configure interrupts using the best available 1101 * capabilities of the hardware and kernel. 1102 **/ 1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1104 { 1105 int err; 1106 int numvecs, i; 1107 1108 if (!msix) 1109 goto msi_only; 1110 adapter->flags |= IGB_FLAG_HAS_MSIX; 1111 1112 /* Number of supported queues. */ 1113 adapter->num_rx_queues = adapter->rss_queues; 1114 if (adapter->vfs_allocated_count) 1115 adapter->num_tx_queues = 1; 1116 else 1117 adapter->num_tx_queues = adapter->rss_queues; 1118 1119 /* start with one vector for every Rx queue */ 1120 numvecs = adapter->num_rx_queues; 1121 1122 /* if Tx handler is separate add 1 for every Tx queue */ 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1124 numvecs += adapter->num_tx_queues; 1125 1126 /* store the number of vectors reserved for queues */ 1127 adapter->num_q_vectors = numvecs; 1128 1129 /* add 1 vector for link status interrupts */ 1130 numvecs++; 1131 for (i = 0; i < numvecs; i++) 1132 adapter->msix_entries[i].entry = i; 1133 1134 err = pci_enable_msix_range(adapter->pdev, 1135 adapter->msix_entries, 1136 numvecs, 1137 numvecs); 1138 if (err > 0) 1139 return; 1140 1141 igb_reset_interrupt_capability(adapter); 1142 1143 /* If we can't do MSI-X, try MSI */ 1144 msi_only: 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1146 #ifdef CONFIG_PCI_IOV 1147 /* disable SR-IOV for non MSI-X configurations */ 1148 if (adapter->vf_data) { 1149 struct e1000_hw *hw = &adapter->hw; 1150 /* disable iov and allow time for transactions to clear */ 1151 pci_disable_sriov(adapter->pdev); 1152 msleep(500); 1153 1154 kfree(adapter->vf_data); 1155 adapter->vf_data = NULL; 1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1157 wrfl(); 1158 msleep(100); 1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1160 } 1161 #endif 1162 adapter->vfs_allocated_count = 0; 1163 adapter->rss_queues = 1; 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1165 adapter->num_rx_queues = 1; 1166 adapter->num_tx_queues = 1; 1167 adapter->num_q_vectors = 1; 1168 if (!pci_enable_msi(adapter->pdev)) 1169 adapter->flags |= IGB_FLAG_HAS_MSI; 1170 } 1171 1172 static void igb_add_ring(struct igb_ring *ring, 1173 struct igb_ring_container *head) 1174 { 1175 head->ring = ring; 1176 head->count++; 1177 } 1178 1179 /** 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1181 * @adapter: board private structure to initialize 1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1183 * @v_idx: index of vector in adapter struct 1184 * @txr_count: total number of Tx rings to allocate 1185 * @txr_idx: index of first Tx ring to allocate 1186 * @rxr_count: total number of Rx rings to allocate 1187 * @rxr_idx: index of first Rx ring to allocate 1188 * 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1190 **/ 1191 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1192 int v_count, int v_idx, 1193 int txr_count, int txr_idx, 1194 int rxr_count, int rxr_idx) 1195 { 1196 struct igb_q_vector *q_vector; 1197 struct igb_ring *ring; 1198 int ring_count, size; 1199 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1201 if (txr_count > 1 || rxr_count > 1) 1202 return -ENOMEM; 1203 1204 ring_count = txr_count + rxr_count; 1205 size = sizeof(struct igb_q_vector) + 1206 (sizeof(struct igb_ring) * ring_count); 1207 1208 /* allocate q_vector and rings */ 1209 q_vector = adapter->q_vector[v_idx]; 1210 if (!q_vector) { 1211 q_vector = kzalloc(size, GFP_KERNEL); 1212 } else if (size > ksize(q_vector)) { 1213 kfree_rcu(q_vector, rcu); 1214 q_vector = kzalloc(size, GFP_KERNEL); 1215 } else { 1216 memset(q_vector, 0, size); 1217 } 1218 if (!q_vector) 1219 return -ENOMEM; 1220 1221 /* initialize NAPI */ 1222 netif_napi_add(adapter->netdev, &q_vector->napi, 1223 igb_poll, 64); 1224 1225 /* tie q_vector and adapter together */ 1226 adapter->q_vector[v_idx] = q_vector; 1227 q_vector->adapter = adapter; 1228 1229 /* initialize work limits */ 1230 q_vector->tx.work_limit = adapter->tx_work_limit; 1231 1232 /* initialize ITR configuration */ 1233 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1234 q_vector->itr_val = IGB_START_ITR; 1235 1236 /* initialize pointer to rings */ 1237 ring = q_vector->ring; 1238 1239 /* intialize ITR */ 1240 if (rxr_count) { 1241 /* rx or rx/tx vector */ 1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1243 q_vector->itr_val = adapter->rx_itr_setting; 1244 } else { 1245 /* tx only vector */ 1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1247 q_vector->itr_val = adapter->tx_itr_setting; 1248 } 1249 1250 if (txr_count) { 1251 /* assign generic ring traits */ 1252 ring->dev = &adapter->pdev->dev; 1253 ring->netdev = adapter->netdev; 1254 1255 /* configure backlink on ring */ 1256 ring->q_vector = q_vector; 1257 1258 /* update q_vector Tx values */ 1259 igb_add_ring(ring, &q_vector->tx); 1260 1261 /* For 82575, context index must be unique per ring. */ 1262 if (adapter->hw.mac.type == e1000_82575) 1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1264 1265 /* apply Tx specific ring traits */ 1266 ring->count = adapter->tx_ring_count; 1267 ring->queue_index = txr_idx; 1268 1269 u64_stats_init(&ring->tx_syncp); 1270 u64_stats_init(&ring->tx_syncp2); 1271 1272 /* assign ring to adapter */ 1273 adapter->tx_ring[txr_idx] = ring; 1274 1275 /* push pointer to next ring */ 1276 ring++; 1277 } 1278 1279 if (rxr_count) { 1280 /* assign generic ring traits */ 1281 ring->dev = &adapter->pdev->dev; 1282 ring->netdev = adapter->netdev; 1283 1284 /* configure backlink on ring */ 1285 ring->q_vector = q_vector; 1286 1287 /* update q_vector Rx values */ 1288 igb_add_ring(ring, &q_vector->rx); 1289 1290 /* set flag indicating ring supports SCTP checksum offload */ 1291 if (adapter->hw.mac.type >= e1000_82576) 1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1293 1294 /* On i350, i354, i210, and i211, loopback VLAN packets 1295 * have the tag byte-swapped. 1296 */ 1297 if (adapter->hw.mac.type >= e1000_i350) 1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1299 1300 /* apply Rx specific ring traits */ 1301 ring->count = adapter->rx_ring_count; 1302 ring->queue_index = rxr_idx; 1303 1304 u64_stats_init(&ring->rx_syncp); 1305 1306 /* assign ring to adapter */ 1307 adapter->rx_ring[rxr_idx] = ring; 1308 } 1309 1310 return 0; 1311 } 1312 1313 1314 /** 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1316 * @adapter: board private structure to initialize 1317 * 1318 * We allocate one q_vector per queue interrupt. If allocation fails we 1319 * return -ENOMEM. 1320 **/ 1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1322 { 1323 int q_vectors = adapter->num_q_vectors; 1324 int rxr_remaining = adapter->num_rx_queues; 1325 int txr_remaining = adapter->num_tx_queues; 1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1327 int err; 1328 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1330 for (; rxr_remaining; v_idx++) { 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 0, 0, 1, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining--; 1339 rxr_idx++; 1340 } 1341 } 1342 1343 for (; v_idx < q_vectors; v_idx++) { 1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1346 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1348 tqpv, txr_idx, rqpv, rxr_idx); 1349 1350 if (err) 1351 goto err_out; 1352 1353 /* update counts and index */ 1354 rxr_remaining -= rqpv; 1355 txr_remaining -= tqpv; 1356 rxr_idx++; 1357 txr_idx++; 1358 } 1359 1360 return 0; 1361 1362 err_out: 1363 adapter->num_tx_queues = 0; 1364 adapter->num_rx_queues = 0; 1365 adapter->num_q_vectors = 0; 1366 1367 while (v_idx--) 1368 igb_free_q_vector(adapter, v_idx); 1369 1370 return -ENOMEM; 1371 } 1372 1373 /** 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1375 * @adapter: board private structure to initialize 1376 * @msix: boolean value of MSIX capability 1377 * 1378 * This function initializes the interrupts and allocates all of the queues. 1379 **/ 1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1381 { 1382 struct pci_dev *pdev = adapter->pdev; 1383 int err; 1384 1385 igb_set_interrupt_capability(adapter, msix); 1386 1387 err = igb_alloc_q_vectors(adapter); 1388 if (err) { 1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1390 goto err_alloc_q_vectors; 1391 } 1392 1393 igb_cache_ring_register(adapter); 1394 1395 return 0; 1396 1397 err_alloc_q_vectors: 1398 igb_reset_interrupt_capability(adapter); 1399 return err; 1400 } 1401 1402 /** 1403 * igb_request_irq - initialize interrupts 1404 * @adapter: board private structure to initialize 1405 * 1406 * Attempts to configure interrupts using the best available 1407 * capabilities of the hardware and kernel. 1408 **/ 1409 static int igb_request_irq(struct igb_adapter *adapter) 1410 { 1411 struct net_device *netdev = adapter->netdev; 1412 struct pci_dev *pdev = adapter->pdev; 1413 int err = 0; 1414 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1416 err = igb_request_msix(adapter); 1417 if (!err) 1418 goto request_done; 1419 /* fall back to MSI */ 1420 igb_free_all_tx_resources(adapter); 1421 igb_free_all_rx_resources(adapter); 1422 1423 igb_clear_interrupt_scheme(adapter); 1424 err = igb_init_interrupt_scheme(adapter, false); 1425 if (err) 1426 goto request_done; 1427 1428 igb_setup_all_tx_resources(adapter); 1429 igb_setup_all_rx_resources(adapter); 1430 igb_configure(adapter); 1431 } 1432 1433 igb_assign_vector(adapter->q_vector[0], 0); 1434 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1436 err = request_irq(pdev->irq, igb_intr_msi, 0, 1437 netdev->name, adapter); 1438 if (!err) 1439 goto request_done; 1440 1441 /* fall back to legacy interrupts */ 1442 igb_reset_interrupt_capability(adapter); 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1444 } 1445 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1447 netdev->name, adapter); 1448 1449 if (err) 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1451 err); 1452 1453 request_done: 1454 return err; 1455 } 1456 1457 static void igb_free_irq(struct igb_adapter *adapter) 1458 { 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1460 int vector = 0, i; 1461 1462 free_irq(adapter->msix_entries[vector++].vector, adapter); 1463 1464 for (i = 0; i < adapter->num_q_vectors; i++) 1465 free_irq(adapter->msix_entries[vector++].vector, 1466 adapter->q_vector[i]); 1467 } else { 1468 free_irq(adapter->pdev->irq, adapter); 1469 } 1470 } 1471 1472 /** 1473 * igb_irq_disable - Mask off interrupt generation on the NIC 1474 * @adapter: board private structure 1475 **/ 1476 static void igb_irq_disable(struct igb_adapter *adapter) 1477 { 1478 struct e1000_hw *hw = &adapter->hw; 1479 1480 /* we need to be careful when disabling interrupts. The VFs are also 1481 * mapped into these registers and so clearing the bits can cause 1482 * issues on the VF drivers so we only need to clear what we set 1483 */ 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 regval = rd32(E1000_EIAM); 1486 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1488 wr32(E1000_EIMC, adapter->eims_enable_mask); 1489 regval = rd32(E1000_EIAC); 1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1491 } 1492 1493 wr32(E1000_IAM, 0); 1494 wr32(E1000_IMC, ~0); 1495 wrfl(); 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1497 int i; 1498 1499 for (i = 0; i < adapter->num_q_vectors; i++) 1500 synchronize_irq(adapter->msix_entries[i].vector); 1501 } else { 1502 synchronize_irq(adapter->pdev->irq); 1503 } 1504 } 1505 1506 /** 1507 * igb_irq_enable - Enable default interrupt generation settings 1508 * @adapter: board private structure 1509 **/ 1510 static void igb_irq_enable(struct igb_adapter *adapter) 1511 { 1512 struct e1000_hw *hw = &adapter->hw; 1513 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1516 u32 regval = rd32(E1000_EIAC); 1517 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1519 regval = rd32(E1000_EIAM); 1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1521 wr32(E1000_EIMS, adapter->eims_enable_mask); 1522 if (adapter->vfs_allocated_count) { 1523 wr32(E1000_MBVFIMR, 0xFF); 1524 ims |= E1000_IMS_VMMB; 1525 } 1526 wr32(E1000_IMS, ims); 1527 } else { 1528 wr32(E1000_IMS, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 wr32(E1000_IAM, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 } 1533 } 1534 1535 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1536 { 1537 struct e1000_hw *hw = &adapter->hw; 1538 u16 pf_id = adapter->vfs_allocated_count; 1539 u16 vid = adapter->hw.mng_cookie.vlan_id; 1540 u16 old_vid = adapter->mng_vlan_id; 1541 1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1543 /* add VID to filter table */ 1544 igb_vfta_set(hw, vid, pf_id, true, true); 1545 adapter->mng_vlan_id = vid; 1546 } else { 1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1548 } 1549 1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1551 (vid != old_vid) && 1552 !test_bit(old_vid, adapter->active_vlans)) { 1553 /* remove VID from filter table */ 1554 igb_vfta_set(hw, vid, pf_id, false, true); 1555 } 1556 } 1557 1558 /** 1559 * igb_release_hw_control - release control of the h/w to f/w 1560 * @adapter: address of board private structure 1561 * 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1563 * For ASF and Pass Through versions of f/w this means that the 1564 * driver is no longer loaded. 1565 **/ 1566 static void igb_release_hw_control(struct igb_adapter *adapter) 1567 { 1568 struct e1000_hw *hw = &adapter->hw; 1569 u32 ctrl_ext; 1570 1571 /* Let firmware take over control of h/w */ 1572 ctrl_ext = rd32(E1000_CTRL_EXT); 1573 wr32(E1000_CTRL_EXT, 1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1575 } 1576 1577 /** 1578 * igb_get_hw_control - get control of the h/w from f/w 1579 * @adapter: address of board private structure 1580 * 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1582 * For ASF and Pass Through versions of f/w this means that 1583 * the driver is loaded. 1584 **/ 1585 static void igb_get_hw_control(struct igb_adapter *adapter) 1586 { 1587 struct e1000_hw *hw = &adapter->hw; 1588 u32 ctrl_ext; 1589 1590 /* Let firmware know the driver has taken over */ 1591 ctrl_ext = rd32(E1000_CTRL_EXT); 1592 wr32(E1000_CTRL_EXT, 1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1594 } 1595 1596 /** 1597 * igb_configure - configure the hardware for RX and TX 1598 * @adapter: private board structure 1599 **/ 1600 static void igb_configure(struct igb_adapter *adapter) 1601 { 1602 struct net_device *netdev = adapter->netdev; 1603 int i; 1604 1605 igb_get_hw_control(adapter); 1606 igb_set_rx_mode(netdev); 1607 1608 igb_restore_vlan(adapter); 1609 1610 igb_setup_tctl(adapter); 1611 igb_setup_mrqc(adapter); 1612 igb_setup_rctl(adapter); 1613 1614 igb_configure_tx(adapter); 1615 igb_configure_rx(adapter); 1616 1617 igb_rx_fifo_flush_82575(&adapter->hw); 1618 1619 /* call igb_desc_unused which always leaves 1620 * at least 1 descriptor unused to make sure 1621 * next_to_use != next_to_clean 1622 */ 1623 for (i = 0; i < adapter->num_rx_queues; i++) { 1624 struct igb_ring *ring = adapter->rx_ring[i]; 1625 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1626 } 1627 } 1628 1629 /** 1630 * igb_power_up_link - Power up the phy/serdes link 1631 * @adapter: address of board private structure 1632 **/ 1633 void igb_power_up_link(struct igb_adapter *adapter) 1634 { 1635 igb_reset_phy(&adapter->hw); 1636 1637 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1638 igb_power_up_phy_copper(&adapter->hw); 1639 else 1640 igb_power_up_serdes_link_82575(&adapter->hw); 1641 1642 igb_setup_link(&adapter->hw); 1643 } 1644 1645 /** 1646 * igb_power_down_link - Power down the phy/serdes link 1647 * @adapter: address of board private structure 1648 */ 1649 static void igb_power_down_link(struct igb_adapter *adapter) 1650 { 1651 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1652 igb_power_down_phy_copper_82575(&adapter->hw); 1653 else 1654 igb_shutdown_serdes_link_82575(&adapter->hw); 1655 } 1656 1657 /** 1658 * Detect and switch function for Media Auto Sense 1659 * @adapter: address of the board private structure 1660 **/ 1661 static void igb_check_swap_media(struct igb_adapter *adapter) 1662 { 1663 struct e1000_hw *hw = &adapter->hw; 1664 u32 ctrl_ext, connsw; 1665 bool swap_now = false; 1666 1667 ctrl_ext = rd32(E1000_CTRL_EXT); 1668 connsw = rd32(E1000_CONNSW); 1669 1670 /* need to live swap if current media is copper and we have fiber/serdes 1671 * to go to. 1672 */ 1673 1674 if ((hw->phy.media_type == e1000_media_type_copper) && 1675 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1676 swap_now = true; 1677 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1678 /* copper signal takes time to appear */ 1679 if (adapter->copper_tries < 4) { 1680 adapter->copper_tries++; 1681 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1682 wr32(E1000_CONNSW, connsw); 1683 return; 1684 } else { 1685 adapter->copper_tries = 0; 1686 if ((connsw & E1000_CONNSW_PHYSD) && 1687 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1688 swap_now = true; 1689 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1690 wr32(E1000_CONNSW, connsw); 1691 } 1692 } 1693 } 1694 1695 if (!swap_now) 1696 return; 1697 1698 switch (hw->phy.media_type) { 1699 case e1000_media_type_copper: 1700 netdev_info(adapter->netdev, 1701 "MAS: changing media to fiber/serdes\n"); 1702 ctrl_ext |= 1703 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1704 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1705 adapter->copper_tries = 0; 1706 break; 1707 case e1000_media_type_internal_serdes: 1708 case e1000_media_type_fiber: 1709 netdev_info(adapter->netdev, 1710 "MAS: changing media to copper\n"); 1711 ctrl_ext &= 1712 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1713 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1714 break; 1715 default: 1716 /* shouldn't get here during regular operation */ 1717 netdev_err(adapter->netdev, 1718 "AMS: Invalid media type found, returning\n"); 1719 break; 1720 } 1721 wr32(E1000_CTRL_EXT, ctrl_ext); 1722 } 1723 1724 /** 1725 * igb_up - Open the interface and prepare it to handle traffic 1726 * @adapter: board private structure 1727 **/ 1728 int igb_up(struct igb_adapter *adapter) 1729 { 1730 struct e1000_hw *hw = &adapter->hw; 1731 int i; 1732 1733 /* hardware has been reset, we need to reload some things */ 1734 igb_configure(adapter); 1735 1736 clear_bit(__IGB_DOWN, &adapter->state); 1737 1738 for (i = 0; i < adapter->num_q_vectors; i++) 1739 napi_enable(&(adapter->q_vector[i]->napi)); 1740 1741 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1742 igb_configure_msix(adapter); 1743 else 1744 igb_assign_vector(adapter->q_vector[0], 0); 1745 1746 /* Clear any pending interrupts. */ 1747 rd32(E1000_ICR); 1748 igb_irq_enable(adapter); 1749 1750 /* notify VFs that reset has been completed */ 1751 if (adapter->vfs_allocated_count) { 1752 u32 reg_data = rd32(E1000_CTRL_EXT); 1753 1754 reg_data |= E1000_CTRL_EXT_PFRSTD; 1755 wr32(E1000_CTRL_EXT, reg_data); 1756 } 1757 1758 netif_tx_start_all_queues(adapter->netdev); 1759 1760 /* start the watchdog. */ 1761 hw->mac.get_link_status = 1; 1762 schedule_work(&adapter->watchdog_task); 1763 1764 if ((adapter->flags & IGB_FLAG_EEE) && 1765 (!hw->dev_spec._82575.eee_disable)) 1766 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1767 1768 return 0; 1769 } 1770 1771 void igb_down(struct igb_adapter *adapter) 1772 { 1773 struct net_device *netdev = adapter->netdev; 1774 struct e1000_hw *hw = &adapter->hw; 1775 u32 tctl, rctl; 1776 int i; 1777 1778 /* signal that we're down so the interrupt handler does not 1779 * reschedule our watchdog timer 1780 */ 1781 set_bit(__IGB_DOWN, &adapter->state); 1782 1783 /* disable receives in the hardware */ 1784 rctl = rd32(E1000_RCTL); 1785 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1786 /* flush and sleep below */ 1787 1788 netif_carrier_off(netdev); 1789 netif_tx_stop_all_queues(netdev); 1790 1791 /* disable transmits in the hardware */ 1792 tctl = rd32(E1000_TCTL); 1793 tctl &= ~E1000_TCTL_EN; 1794 wr32(E1000_TCTL, tctl); 1795 /* flush both disables and wait for them to finish */ 1796 wrfl(); 1797 usleep_range(10000, 11000); 1798 1799 igb_irq_disable(adapter); 1800 1801 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1802 1803 for (i = 0; i < adapter->num_q_vectors; i++) { 1804 if (adapter->q_vector[i]) { 1805 napi_synchronize(&adapter->q_vector[i]->napi); 1806 napi_disable(&adapter->q_vector[i]->napi); 1807 } 1808 } 1809 1810 del_timer_sync(&adapter->watchdog_timer); 1811 del_timer_sync(&adapter->phy_info_timer); 1812 1813 /* record the stats before reset*/ 1814 spin_lock(&adapter->stats64_lock); 1815 igb_update_stats(adapter, &adapter->stats64); 1816 spin_unlock(&adapter->stats64_lock); 1817 1818 adapter->link_speed = 0; 1819 adapter->link_duplex = 0; 1820 1821 if (!pci_channel_offline(adapter->pdev)) 1822 igb_reset(adapter); 1823 1824 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1825 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1826 1827 igb_clean_all_tx_rings(adapter); 1828 igb_clean_all_rx_rings(adapter); 1829 #ifdef CONFIG_IGB_DCA 1830 1831 /* since we reset the hardware DCA settings were cleared */ 1832 igb_setup_dca(adapter); 1833 #endif 1834 } 1835 1836 void igb_reinit_locked(struct igb_adapter *adapter) 1837 { 1838 WARN_ON(in_interrupt()); 1839 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1840 usleep_range(1000, 2000); 1841 igb_down(adapter); 1842 igb_up(adapter); 1843 clear_bit(__IGB_RESETTING, &adapter->state); 1844 } 1845 1846 /** igb_enable_mas - Media Autosense re-enable after swap 1847 * 1848 * @adapter: adapter struct 1849 **/ 1850 static void igb_enable_mas(struct igb_adapter *adapter) 1851 { 1852 struct e1000_hw *hw = &adapter->hw; 1853 u32 connsw = rd32(E1000_CONNSW); 1854 1855 /* configure for SerDes media detect */ 1856 if ((hw->phy.media_type == e1000_media_type_copper) && 1857 (!(connsw & E1000_CONNSW_SERDESD))) { 1858 connsw |= E1000_CONNSW_ENRGSRC; 1859 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1860 wr32(E1000_CONNSW, connsw); 1861 wrfl(); 1862 } 1863 } 1864 1865 void igb_reset(struct igb_adapter *adapter) 1866 { 1867 struct pci_dev *pdev = adapter->pdev; 1868 struct e1000_hw *hw = &adapter->hw; 1869 struct e1000_mac_info *mac = &hw->mac; 1870 struct e1000_fc_info *fc = &hw->fc; 1871 u32 pba, hwm; 1872 1873 /* Repartition Pba for greater than 9k mtu 1874 * To take effect CTRL.RST is required. 1875 */ 1876 switch (mac->type) { 1877 case e1000_i350: 1878 case e1000_i354: 1879 case e1000_82580: 1880 pba = rd32(E1000_RXPBS); 1881 pba = igb_rxpbs_adjust_82580(pba); 1882 break; 1883 case e1000_82576: 1884 pba = rd32(E1000_RXPBS); 1885 pba &= E1000_RXPBS_SIZE_MASK_82576; 1886 break; 1887 case e1000_82575: 1888 case e1000_i210: 1889 case e1000_i211: 1890 default: 1891 pba = E1000_PBA_34K; 1892 break; 1893 } 1894 1895 if (mac->type == e1000_82575) { 1896 u32 min_rx_space, min_tx_space, needed_tx_space; 1897 1898 /* write Rx PBA so that hardware can report correct Tx PBA */ 1899 wr32(E1000_PBA, pba); 1900 1901 /* To maintain wire speed transmits, the Tx FIFO should be 1902 * large enough to accommodate two full transmit packets, 1903 * rounded up to the next 1KB and expressed in KB. Likewise, 1904 * the Rx FIFO should be large enough to accommodate at least 1905 * one full receive packet and is similarly rounded up and 1906 * expressed in KB. 1907 */ 1908 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1909 1910 /* The Tx FIFO also stores 16 bytes of information about the Tx 1911 * but don't include Ethernet FCS because hardware appends it. 1912 * We only need to round down to the nearest 512 byte block 1913 * count since the value we care about is 2 frames, not 1. 1914 */ 1915 min_tx_space = adapter->max_frame_size; 1916 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1917 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1918 1919 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1920 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1921 1922 /* If current Tx allocation is less than the min Tx FIFO size, 1923 * and the min Tx FIFO size is less than the current Rx FIFO 1924 * allocation, take space away from current Rx allocation. 1925 */ 1926 if (needed_tx_space < pba) { 1927 pba -= needed_tx_space; 1928 1929 /* if short on Rx space, Rx wins and must trump Tx 1930 * adjustment 1931 */ 1932 if (pba < min_rx_space) 1933 pba = min_rx_space; 1934 } 1935 1936 /* adjust PBA for jumbo frames */ 1937 wr32(E1000_PBA, pba); 1938 } 1939 1940 /* flow control settings 1941 * The high water mark must be low enough to fit one full frame 1942 * after transmitting the pause frame. As such we must have enough 1943 * space to allow for us to complete our current transmit and then 1944 * receive the frame that is in progress from the link partner. 1945 * Set it to: 1946 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1947 */ 1948 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1949 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1951 fc->low_water = fc->high_water - 16; 1952 fc->pause_time = 0xFFFF; 1953 fc->send_xon = 1; 1954 fc->current_mode = fc->requested_mode; 1955 1956 /* disable receive for all VFs and wait one second */ 1957 if (adapter->vfs_allocated_count) { 1958 int i; 1959 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1962 1963 /* ping all the active vfs to let them know we are going down */ 1964 igb_ping_all_vfs(adapter); 1965 1966 /* disable transmits and receives */ 1967 wr32(E1000_VFRE, 0); 1968 wr32(E1000_VFTE, 0); 1969 } 1970 1971 /* Allow time for pending master requests to run */ 1972 hw->mac.ops.reset_hw(hw); 1973 wr32(E1000_WUC, 0); 1974 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1976 /* need to resetup here after media swap */ 1977 adapter->ei.get_invariants(hw); 1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1979 } 1980 if ((mac->type == e1000_82575) && 1981 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1982 igb_enable_mas(adapter); 1983 } 1984 if (hw->mac.ops.init_hw(hw)) 1985 dev_err(&pdev->dev, "Hardware Error\n"); 1986 1987 /* Flow control settings reset on hardware reset, so guarantee flow 1988 * control is off when forcing speed. 1989 */ 1990 if (!hw->mac.autoneg) 1991 igb_force_mac_fc(hw); 1992 1993 igb_init_dmac(adapter, pba); 1994 #ifdef CONFIG_IGB_HWMON 1995 /* Re-initialize the thermal sensor on i350 devices. */ 1996 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1997 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1998 /* If present, re-initialize the external thermal sensor 1999 * interface. 2000 */ 2001 if (adapter->ets) 2002 mac->ops.init_thermal_sensor_thresh(hw); 2003 } 2004 } 2005 #endif 2006 /* Re-establish EEE setting */ 2007 if (hw->phy.media_type == e1000_media_type_copper) { 2008 switch (mac->type) { 2009 case e1000_i350: 2010 case e1000_i210: 2011 case e1000_i211: 2012 igb_set_eee_i350(hw, true, true); 2013 break; 2014 case e1000_i354: 2015 igb_set_eee_i354(hw, true, true); 2016 break; 2017 default: 2018 break; 2019 } 2020 } 2021 if (!netif_running(adapter->netdev)) 2022 igb_power_down_link(adapter); 2023 2024 igb_update_mng_vlan(adapter); 2025 2026 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2027 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2028 2029 /* Re-enable PTP, where applicable. */ 2030 igb_ptp_reset(adapter); 2031 2032 igb_get_phy_info(hw); 2033 } 2034 2035 static netdev_features_t igb_fix_features(struct net_device *netdev, 2036 netdev_features_t features) 2037 { 2038 /* Since there is no support for separate Rx/Tx vlan accel 2039 * enable/disable make sure Tx flag is always in same state as Rx. 2040 */ 2041 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2042 features |= NETIF_F_HW_VLAN_CTAG_TX; 2043 else 2044 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2045 2046 return features; 2047 } 2048 2049 static int igb_set_features(struct net_device *netdev, 2050 netdev_features_t features) 2051 { 2052 netdev_features_t changed = netdev->features ^ features; 2053 struct igb_adapter *adapter = netdev_priv(netdev); 2054 2055 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2056 igb_vlan_mode(netdev, features); 2057 2058 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2059 return 0; 2060 2061 netdev->features = features; 2062 2063 if (netif_running(netdev)) 2064 igb_reinit_locked(adapter); 2065 else 2066 igb_reset(adapter); 2067 2068 return 0; 2069 } 2070 2071 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2072 struct net_device *dev, 2073 const unsigned char *addr, u16 vid, 2074 u16 flags) 2075 { 2076 /* guarantee we can provide a unique filter for the unicast address */ 2077 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2078 struct igb_adapter *adapter = netdev_priv(dev); 2079 struct e1000_hw *hw = &adapter->hw; 2080 int vfn = adapter->vfs_allocated_count; 2081 int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 2082 2083 if (netdev_uc_count(dev) >= rar_entries) 2084 return -ENOMEM; 2085 } 2086 2087 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2088 } 2089 2090 #define IGB_MAX_MAC_HDR_LEN 127 2091 #define IGB_MAX_NETWORK_HDR_LEN 511 2092 2093 static netdev_features_t 2094 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2095 netdev_features_t features) 2096 { 2097 unsigned int network_hdr_len, mac_hdr_len; 2098 2099 /* Make certain the headers can be described by a context descriptor */ 2100 mac_hdr_len = skb_network_header(skb) - skb->data; 2101 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2102 return features & ~(NETIF_F_HW_CSUM | 2103 NETIF_F_SCTP_CRC | 2104 NETIF_F_HW_VLAN_CTAG_TX | 2105 NETIF_F_TSO | 2106 NETIF_F_TSO6); 2107 2108 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2109 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2110 return features & ~(NETIF_F_HW_CSUM | 2111 NETIF_F_SCTP_CRC | 2112 NETIF_F_TSO | 2113 NETIF_F_TSO6); 2114 2115 /* We can only support IPV4 TSO in tunnels if we can mangle the 2116 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2117 */ 2118 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2119 features &= ~NETIF_F_TSO; 2120 2121 return features; 2122 } 2123 2124 static const struct net_device_ops igb_netdev_ops = { 2125 .ndo_open = igb_open, 2126 .ndo_stop = igb_close, 2127 .ndo_start_xmit = igb_xmit_frame, 2128 .ndo_get_stats64 = igb_get_stats64, 2129 .ndo_set_rx_mode = igb_set_rx_mode, 2130 .ndo_set_mac_address = igb_set_mac, 2131 .ndo_change_mtu = igb_change_mtu, 2132 .ndo_do_ioctl = igb_ioctl, 2133 .ndo_tx_timeout = igb_tx_timeout, 2134 .ndo_validate_addr = eth_validate_addr, 2135 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2136 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2137 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2138 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2139 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2140 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2141 .ndo_get_vf_config = igb_ndo_get_vf_config, 2142 #ifdef CONFIG_NET_POLL_CONTROLLER 2143 .ndo_poll_controller = igb_netpoll, 2144 #endif 2145 .ndo_fix_features = igb_fix_features, 2146 .ndo_set_features = igb_set_features, 2147 .ndo_fdb_add = igb_ndo_fdb_add, 2148 .ndo_features_check = igb_features_check, 2149 }; 2150 2151 /** 2152 * igb_set_fw_version - Configure version string for ethtool 2153 * @adapter: adapter struct 2154 **/ 2155 void igb_set_fw_version(struct igb_adapter *adapter) 2156 { 2157 struct e1000_hw *hw = &adapter->hw; 2158 struct e1000_fw_version fw; 2159 2160 igb_get_fw_version(hw, &fw); 2161 2162 switch (hw->mac.type) { 2163 case e1000_i210: 2164 case e1000_i211: 2165 if (!(igb_get_flash_presence_i210(hw))) { 2166 snprintf(adapter->fw_version, 2167 sizeof(adapter->fw_version), 2168 "%2d.%2d-%d", 2169 fw.invm_major, fw.invm_minor, 2170 fw.invm_img_type); 2171 break; 2172 } 2173 /* fall through */ 2174 default: 2175 /* if option is rom valid, display its version too */ 2176 if (fw.or_valid) { 2177 snprintf(adapter->fw_version, 2178 sizeof(adapter->fw_version), 2179 "%d.%d, 0x%08x, %d.%d.%d", 2180 fw.eep_major, fw.eep_minor, fw.etrack_id, 2181 fw.or_major, fw.or_build, fw.or_patch); 2182 /* no option rom */ 2183 } else if (fw.etrack_id != 0X0000) { 2184 snprintf(adapter->fw_version, 2185 sizeof(adapter->fw_version), 2186 "%d.%d, 0x%08x", 2187 fw.eep_major, fw.eep_minor, fw.etrack_id); 2188 } else { 2189 snprintf(adapter->fw_version, 2190 sizeof(adapter->fw_version), 2191 "%d.%d.%d", 2192 fw.eep_major, fw.eep_minor, fw.eep_build); 2193 } 2194 break; 2195 } 2196 } 2197 2198 /** 2199 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2200 * 2201 * @adapter: adapter struct 2202 **/ 2203 static void igb_init_mas(struct igb_adapter *adapter) 2204 { 2205 struct e1000_hw *hw = &adapter->hw; 2206 u16 eeprom_data; 2207 2208 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2209 switch (hw->bus.func) { 2210 case E1000_FUNC_0: 2211 if (eeprom_data & IGB_MAS_ENABLE_0) { 2212 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2213 netdev_info(adapter->netdev, 2214 "MAS: Enabling Media Autosense for port %d\n", 2215 hw->bus.func); 2216 } 2217 break; 2218 case E1000_FUNC_1: 2219 if (eeprom_data & IGB_MAS_ENABLE_1) { 2220 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2221 netdev_info(adapter->netdev, 2222 "MAS: Enabling Media Autosense for port %d\n", 2223 hw->bus.func); 2224 } 2225 break; 2226 case E1000_FUNC_2: 2227 if (eeprom_data & IGB_MAS_ENABLE_2) { 2228 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2229 netdev_info(adapter->netdev, 2230 "MAS: Enabling Media Autosense for port %d\n", 2231 hw->bus.func); 2232 } 2233 break; 2234 case E1000_FUNC_3: 2235 if (eeprom_data & IGB_MAS_ENABLE_3) { 2236 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2237 netdev_info(adapter->netdev, 2238 "MAS: Enabling Media Autosense for port %d\n", 2239 hw->bus.func); 2240 } 2241 break; 2242 default: 2243 /* Shouldn't get here */ 2244 netdev_err(adapter->netdev, 2245 "MAS: Invalid port configuration, returning\n"); 2246 break; 2247 } 2248 } 2249 2250 /** 2251 * igb_init_i2c - Init I2C interface 2252 * @adapter: pointer to adapter structure 2253 **/ 2254 static s32 igb_init_i2c(struct igb_adapter *adapter) 2255 { 2256 s32 status = 0; 2257 2258 /* I2C interface supported on i350 devices */ 2259 if (adapter->hw.mac.type != e1000_i350) 2260 return 0; 2261 2262 /* Initialize the i2c bus which is controlled by the registers. 2263 * This bus will use the i2c_algo_bit structue that implements 2264 * the protocol through toggling of the 4 bits in the register. 2265 */ 2266 adapter->i2c_adap.owner = THIS_MODULE; 2267 adapter->i2c_algo = igb_i2c_algo; 2268 adapter->i2c_algo.data = adapter; 2269 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2270 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2271 strlcpy(adapter->i2c_adap.name, "igb BB", 2272 sizeof(adapter->i2c_adap.name)); 2273 status = i2c_bit_add_bus(&adapter->i2c_adap); 2274 return status; 2275 } 2276 2277 /** 2278 * igb_probe - Device Initialization Routine 2279 * @pdev: PCI device information struct 2280 * @ent: entry in igb_pci_tbl 2281 * 2282 * Returns 0 on success, negative on failure 2283 * 2284 * igb_probe initializes an adapter identified by a pci_dev structure. 2285 * The OS initialization, configuring of the adapter private structure, 2286 * and a hardware reset occur. 2287 **/ 2288 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2289 { 2290 struct net_device *netdev; 2291 struct igb_adapter *adapter; 2292 struct e1000_hw *hw; 2293 u16 eeprom_data = 0; 2294 s32 ret_val; 2295 static int global_quad_port_a; /* global quad port a indication */ 2296 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2297 int err, pci_using_dac; 2298 u8 part_str[E1000_PBANUM_LENGTH]; 2299 2300 /* Catch broken hardware that put the wrong VF device ID in 2301 * the PCIe SR-IOV capability. 2302 */ 2303 if (pdev->is_virtfn) { 2304 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2305 pci_name(pdev), pdev->vendor, pdev->device); 2306 return -EINVAL; 2307 } 2308 2309 err = pci_enable_device_mem(pdev); 2310 if (err) 2311 return err; 2312 2313 pci_using_dac = 0; 2314 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2315 if (!err) { 2316 pci_using_dac = 1; 2317 } else { 2318 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2319 if (err) { 2320 dev_err(&pdev->dev, 2321 "No usable DMA configuration, aborting\n"); 2322 goto err_dma; 2323 } 2324 } 2325 2326 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2327 IORESOURCE_MEM), 2328 igb_driver_name); 2329 if (err) 2330 goto err_pci_reg; 2331 2332 pci_enable_pcie_error_reporting(pdev); 2333 2334 pci_set_master(pdev); 2335 pci_save_state(pdev); 2336 2337 err = -ENOMEM; 2338 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2339 IGB_MAX_TX_QUEUES); 2340 if (!netdev) 2341 goto err_alloc_etherdev; 2342 2343 SET_NETDEV_DEV(netdev, &pdev->dev); 2344 2345 pci_set_drvdata(pdev, netdev); 2346 adapter = netdev_priv(netdev); 2347 adapter->netdev = netdev; 2348 adapter->pdev = pdev; 2349 hw = &adapter->hw; 2350 hw->back = adapter; 2351 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2352 2353 err = -EIO; 2354 adapter->io_addr = pci_iomap(pdev, 0, 0); 2355 if (!adapter->io_addr) 2356 goto err_ioremap; 2357 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2358 hw->hw_addr = adapter->io_addr; 2359 2360 netdev->netdev_ops = &igb_netdev_ops; 2361 igb_set_ethtool_ops(netdev); 2362 netdev->watchdog_timeo = 5 * HZ; 2363 2364 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2365 2366 netdev->mem_start = pci_resource_start(pdev, 0); 2367 netdev->mem_end = pci_resource_end(pdev, 0); 2368 2369 /* PCI config space info */ 2370 hw->vendor_id = pdev->vendor; 2371 hw->device_id = pdev->device; 2372 hw->revision_id = pdev->revision; 2373 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2374 hw->subsystem_device_id = pdev->subsystem_device; 2375 2376 /* Copy the default MAC, PHY and NVM function pointers */ 2377 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2378 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2379 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2380 /* Initialize skew-specific constants */ 2381 err = ei->get_invariants(hw); 2382 if (err) 2383 goto err_sw_init; 2384 2385 /* setup the private structure */ 2386 err = igb_sw_init(adapter); 2387 if (err) 2388 goto err_sw_init; 2389 2390 igb_get_bus_info_pcie(hw); 2391 2392 hw->phy.autoneg_wait_to_complete = false; 2393 2394 /* Copper options */ 2395 if (hw->phy.media_type == e1000_media_type_copper) { 2396 hw->phy.mdix = AUTO_ALL_MODES; 2397 hw->phy.disable_polarity_correction = false; 2398 hw->phy.ms_type = e1000_ms_hw_default; 2399 } 2400 2401 if (igb_check_reset_block(hw)) 2402 dev_info(&pdev->dev, 2403 "PHY reset is blocked due to SOL/IDER session.\n"); 2404 2405 /* features is initialized to 0 in allocation, it might have bits 2406 * set by igb_sw_init so we should use an or instead of an 2407 * assignment. 2408 */ 2409 netdev->features |= NETIF_F_SG | 2410 NETIF_F_TSO | 2411 NETIF_F_TSO6 | 2412 NETIF_F_RXHASH | 2413 NETIF_F_RXCSUM | 2414 NETIF_F_HW_CSUM; 2415 2416 if (hw->mac.type >= e1000_82576) 2417 netdev->features |= NETIF_F_SCTP_CRC; 2418 2419 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2420 NETIF_F_GSO_GRE_CSUM | \ 2421 NETIF_F_GSO_IPXIP4 | \ 2422 NETIF_F_GSO_IPXIP6 | \ 2423 NETIF_F_GSO_UDP_TUNNEL | \ 2424 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2425 2426 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2427 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2428 2429 /* copy netdev features into list of user selectable features */ 2430 netdev->hw_features |= netdev->features | 2431 NETIF_F_HW_VLAN_CTAG_RX | 2432 NETIF_F_HW_VLAN_CTAG_TX | 2433 NETIF_F_RXALL; 2434 2435 if (hw->mac.type >= e1000_i350) 2436 netdev->hw_features |= NETIF_F_NTUPLE; 2437 2438 if (pci_using_dac) 2439 netdev->features |= NETIF_F_HIGHDMA; 2440 2441 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2442 netdev->mpls_features |= NETIF_F_HW_CSUM; 2443 netdev->hw_enc_features |= netdev->vlan_features; 2444 2445 /* set this bit last since it cannot be part of vlan_features */ 2446 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2447 NETIF_F_HW_VLAN_CTAG_RX | 2448 NETIF_F_HW_VLAN_CTAG_TX; 2449 2450 netdev->priv_flags |= IFF_SUPP_NOFCS; 2451 2452 netdev->priv_flags |= IFF_UNICAST_FLT; 2453 2454 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2455 2456 /* before reading the NVM, reset the controller to put the device in a 2457 * known good starting state 2458 */ 2459 hw->mac.ops.reset_hw(hw); 2460 2461 /* make sure the NVM is good , i211/i210 parts can have special NVM 2462 * that doesn't contain a checksum 2463 */ 2464 switch (hw->mac.type) { 2465 case e1000_i210: 2466 case e1000_i211: 2467 if (igb_get_flash_presence_i210(hw)) { 2468 if (hw->nvm.ops.validate(hw) < 0) { 2469 dev_err(&pdev->dev, 2470 "The NVM Checksum Is Not Valid\n"); 2471 err = -EIO; 2472 goto err_eeprom; 2473 } 2474 } 2475 break; 2476 default: 2477 if (hw->nvm.ops.validate(hw) < 0) { 2478 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2479 err = -EIO; 2480 goto err_eeprom; 2481 } 2482 break; 2483 } 2484 2485 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2486 /* copy the MAC address out of the NVM */ 2487 if (hw->mac.ops.read_mac_addr(hw)) 2488 dev_err(&pdev->dev, "NVM Read Error\n"); 2489 } 2490 2491 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2492 2493 if (!is_valid_ether_addr(netdev->dev_addr)) { 2494 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2495 err = -EIO; 2496 goto err_eeprom; 2497 } 2498 2499 /* get firmware version for ethtool -i */ 2500 igb_set_fw_version(adapter); 2501 2502 /* configure RXPBSIZE and TXPBSIZE */ 2503 if (hw->mac.type == e1000_i210) { 2504 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2505 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2506 } 2507 2508 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2509 (unsigned long) adapter); 2510 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2511 (unsigned long) adapter); 2512 2513 INIT_WORK(&adapter->reset_task, igb_reset_task); 2514 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2515 2516 /* Initialize link properties that are user-changeable */ 2517 adapter->fc_autoneg = true; 2518 hw->mac.autoneg = true; 2519 hw->phy.autoneg_advertised = 0x2f; 2520 2521 hw->fc.requested_mode = e1000_fc_default; 2522 hw->fc.current_mode = e1000_fc_default; 2523 2524 igb_validate_mdi_setting(hw); 2525 2526 /* By default, support wake on port A */ 2527 if (hw->bus.func == 0) 2528 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2529 2530 /* Check the NVM for wake support on non-port A ports */ 2531 if (hw->mac.type >= e1000_82580) 2532 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2533 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2534 &eeprom_data); 2535 else if (hw->bus.func == 1) 2536 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2537 2538 if (eeprom_data & IGB_EEPROM_APME) 2539 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2540 2541 /* now that we have the eeprom settings, apply the special cases where 2542 * the eeprom may be wrong or the board simply won't support wake on 2543 * lan on a particular port 2544 */ 2545 switch (pdev->device) { 2546 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2547 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2548 break; 2549 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2550 case E1000_DEV_ID_82576_FIBER: 2551 case E1000_DEV_ID_82576_SERDES: 2552 /* Wake events only supported on port A for dual fiber 2553 * regardless of eeprom setting 2554 */ 2555 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2556 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2557 break; 2558 case E1000_DEV_ID_82576_QUAD_COPPER: 2559 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2560 /* if quad port adapter, disable WoL on all but port A */ 2561 if (global_quad_port_a != 0) 2562 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2563 else 2564 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2565 /* Reset for multiple quad port adapters */ 2566 if (++global_quad_port_a == 4) 2567 global_quad_port_a = 0; 2568 break; 2569 default: 2570 /* If the device can't wake, don't set software support */ 2571 if (!device_can_wakeup(&adapter->pdev->dev)) 2572 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2573 } 2574 2575 /* initialize the wol settings based on the eeprom settings */ 2576 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2577 adapter->wol |= E1000_WUFC_MAG; 2578 2579 /* Some vendors want WoL disabled by default, but still supported */ 2580 if ((hw->mac.type == e1000_i350) && 2581 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2582 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2583 adapter->wol = 0; 2584 } 2585 2586 /* Some vendors want the ability to Use the EEPROM setting as 2587 * enable/disable only, and not for capability 2588 */ 2589 if (((hw->mac.type == e1000_i350) || 2590 (hw->mac.type == e1000_i354)) && 2591 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2592 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2593 adapter->wol = 0; 2594 } 2595 if (hw->mac.type == e1000_i350) { 2596 if (((pdev->subsystem_device == 0x5001) || 2597 (pdev->subsystem_device == 0x5002)) && 2598 (hw->bus.func == 0)) { 2599 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2600 adapter->wol = 0; 2601 } 2602 if (pdev->subsystem_device == 0x1F52) 2603 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2604 } 2605 2606 device_set_wakeup_enable(&adapter->pdev->dev, 2607 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2608 2609 /* reset the hardware with the new settings */ 2610 igb_reset(adapter); 2611 2612 /* Init the I2C interface */ 2613 err = igb_init_i2c(adapter); 2614 if (err) { 2615 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2616 goto err_eeprom; 2617 } 2618 2619 /* let the f/w know that the h/w is now under the control of the 2620 * driver. 2621 */ 2622 igb_get_hw_control(adapter); 2623 2624 strcpy(netdev->name, "eth%d"); 2625 err = register_netdev(netdev); 2626 if (err) 2627 goto err_register; 2628 2629 /* carrier off reporting is important to ethtool even BEFORE open */ 2630 netif_carrier_off(netdev); 2631 2632 #ifdef CONFIG_IGB_DCA 2633 if (dca_add_requester(&pdev->dev) == 0) { 2634 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2635 dev_info(&pdev->dev, "DCA enabled\n"); 2636 igb_setup_dca(adapter); 2637 } 2638 2639 #endif 2640 #ifdef CONFIG_IGB_HWMON 2641 /* Initialize the thermal sensor on i350 devices. */ 2642 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2643 u16 ets_word; 2644 2645 /* Read the NVM to determine if this i350 device supports an 2646 * external thermal sensor. 2647 */ 2648 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2649 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2650 adapter->ets = true; 2651 else 2652 adapter->ets = false; 2653 if (igb_sysfs_init(adapter)) 2654 dev_err(&pdev->dev, 2655 "failed to allocate sysfs resources\n"); 2656 } else { 2657 adapter->ets = false; 2658 } 2659 #endif 2660 /* Check if Media Autosense is enabled */ 2661 adapter->ei = *ei; 2662 if (hw->dev_spec._82575.mas_capable) 2663 igb_init_mas(adapter); 2664 2665 /* do hw tstamp init after resetting */ 2666 igb_ptp_init(adapter); 2667 2668 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2669 /* print bus type/speed/width info, not applicable to i354 */ 2670 if (hw->mac.type != e1000_i354) { 2671 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2672 netdev->name, 2673 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2674 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2675 "unknown"), 2676 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2677 "Width x4" : 2678 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2679 "Width x2" : 2680 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2681 "Width x1" : "unknown"), netdev->dev_addr); 2682 } 2683 2684 if ((hw->mac.type >= e1000_i210 || 2685 igb_get_flash_presence_i210(hw))) { 2686 ret_val = igb_read_part_string(hw, part_str, 2687 E1000_PBANUM_LENGTH); 2688 } else { 2689 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2690 } 2691 2692 if (ret_val) 2693 strcpy(part_str, "Unknown"); 2694 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2695 dev_info(&pdev->dev, 2696 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2697 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2698 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2699 adapter->num_rx_queues, adapter->num_tx_queues); 2700 if (hw->phy.media_type == e1000_media_type_copper) { 2701 switch (hw->mac.type) { 2702 case e1000_i350: 2703 case e1000_i210: 2704 case e1000_i211: 2705 /* Enable EEE for internal copper PHY devices */ 2706 err = igb_set_eee_i350(hw, true, true); 2707 if ((!err) && 2708 (!hw->dev_spec._82575.eee_disable)) { 2709 adapter->eee_advert = 2710 MDIO_EEE_100TX | MDIO_EEE_1000T; 2711 adapter->flags |= IGB_FLAG_EEE; 2712 } 2713 break; 2714 case e1000_i354: 2715 if ((rd32(E1000_CTRL_EXT) & 2716 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2717 err = igb_set_eee_i354(hw, true, true); 2718 if ((!err) && 2719 (!hw->dev_spec._82575.eee_disable)) { 2720 adapter->eee_advert = 2721 MDIO_EEE_100TX | MDIO_EEE_1000T; 2722 adapter->flags |= IGB_FLAG_EEE; 2723 } 2724 } 2725 break; 2726 default: 2727 break; 2728 } 2729 } 2730 pm_runtime_put_noidle(&pdev->dev); 2731 return 0; 2732 2733 err_register: 2734 igb_release_hw_control(adapter); 2735 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2736 err_eeprom: 2737 if (!igb_check_reset_block(hw)) 2738 igb_reset_phy(hw); 2739 2740 if (hw->flash_address) 2741 iounmap(hw->flash_address); 2742 err_sw_init: 2743 kfree(adapter->shadow_vfta); 2744 igb_clear_interrupt_scheme(adapter); 2745 #ifdef CONFIG_PCI_IOV 2746 igb_disable_sriov(pdev); 2747 #endif 2748 pci_iounmap(pdev, adapter->io_addr); 2749 err_ioremap: 2750 free_netdev(netdev); 2751 err_alloc_etherdev: 2752 pci_release_selected_regions(pdev, 2753 pci_select_bars(pdev, IORESOURCE_MEM)); 2754 err_pci_reg: 2755 err_dma: 2756 pci_disable_device(pdev); 2757 return err; 2758 } 2759 2760 #ifdef CONFIG_PCI_IOV 2761 static int igb_disable_sriov(struct pci_dev *pdev) 2762 { 2763 struct net_device *netdev = pci_get_drvdata(pdev); 2764 struct igb_adapter *adapter = netdev_priv(netdev); 2765 struct e1000_hw *hw = &adapter->hw; 2766 2767 /* reclaim resources allocated to VFs */ 2768 if (adapter->vf_data) { 2769 /* disable iov and allow time for transactions to clear */ 2770 if (pci_vfs_assigned(pdev)) { 2771 dev_warn(&pdev->dev, 2772 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2773 return -EPERM; 2774 } else { 2775 pci_disable_sriov(pdev); 2776 msleep(500); 2777 } 2778 2779 kfree(adapter->vf_data); 2780 adapter->vf_data = NULL; 2781 adapter->vfs_allocated_count = 0; 2782 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2783 wrfl(); 2784 msleep(100); 2785 dev_info(&pdev->dev, "IOV Disabled\n"); 2786 2787 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2788 adapter->flags |= IGB_FLAG_DMAC; 2789 } 2790 2791 return 0; 2792 } 2793 2794 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2795 { 2796 struct net_device *netdev = pci_get_drvdata(pdev); 2797 struct igb_adapter *adapter = netdev_priv(netdev); 2798 int old_vfs = pci_num_vf(pdev); 2799 int err = 0; 2800 int i; 2801 2802 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2803 err = -EPERM; 2804 goto out; 2805 } 2806 if (!num_vfs) 2807 goto out; 2808 2809 if (old_vfs) { 2810 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2811 old_vfs, max_vfs); 2812 adapter->vfs_allocated_count = old_vfs; 2813 } else 2814 adapter->vfs_allocated_count = num_vfs; 2815 2816 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2817 sizeof(struct vf_data_storage), GFP_KERNEL); 2818 2819 /* if allocation failed then we do not support SR-IOV */ 2820 if (!adapter->vf_data) { 2821 adapter->vfs_allocated_count = 0; 2822 dev_err(&pdev->dev, 2823 "Unable to allocate memory for VF Data Storage\n"); 2824 err = -ENOMEM; 2825 goto out; 2826 } 2827 2828 /* only call pci_enable_sriov() if no VFs are allocated already */ 2829 if (!old_vfs) { 2830 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2831 if (err) 2832 goto err_out; 2833 } 2834 dev_info(&pdev->dev, "%d VFs allocated\n", 2835 adapter->vfs_allocated_count); 2836 for (i = 0; i < adapter->vfs_allocated_count; i++) 2837 igb_vf_configure(adapter, i); 2838 2839 /* DMA Coalescing is not supported in IOV mode. */ 2840 adapter->flags &= ~IGB_FLAG_DMAC; 2841 goto out; 2842 2843 err_out: 2844 kfree(adapter->vf_data); 2845 adapter->vf_data = NULL; 2846 adapter->vfs_allocated_count = 0; 2847 out: 2848 return err; 2849 } 2850 2851 #endif 2852 /** 2853 * igb_remove_i2c - Cleanup I2C interface 2854 * @adapter: pointer to adapter structure 2855 **/ 2856 static void igb_remove_i2c(struct igb_adapter *adapter) 2857 { 2858 /* free the adapter bus structure */ 2859 i2c_del_adapter(&adapter->i2c_adap); 2860 } 2861 2862 /** 2863 * igb_remove - Device Removal Routine 2864 * @pdev: PCI device information struct 2865 * 2866 * igb_remove is called by the PCI subsystem to alert the driver 2867 * that it should release a PCI device. The could be caused by a 2868 * Hot-Plug event, or because the driver is going to be removed from 2869 * memory. 2870 **/ 2871 static void igb_remove(struct pci_dev *pdev) 2872 { 2873 struct net_device *netdev = pci_get_drvdata(pdev); 2874 struct igb_adapter *adapter = netdev_priv(netdev); 2875 struct e1000_hw *hw = &adapter->hw; 2876 2877 pm_runtime_get_noresume(&pdev->dev); 2878 #ifdef CONFIG_IGB_HWMON 2879 igb_sysfs_exit(adapter); 2880 #endif 2881 igb_remove_i2c(adapter); 2882 igb_ptp_stop(adapter); 2883 /* The watchdog timer may be rescheduled, so explicitly 2884 * disable watchdog from being rescheduled. 2885 */ 2886 set_bit(__IGB_DOWN, &adapter->state); 2887 del_timer_sync(&adapter->watchdog_timer); 2888 del_timer_sync(&adapter->phy_info_timer); 2889 2890 cancel_work_sync(&adapter->reset_task); 2891 cancel_work_sync(&adapter->watchdog_task); 2892 2893 #ifdef CONFIG_IGB_DCA 2894 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2895 dev_info(&pdev->dev, "DCA disabled\n"); 2896 dca_remove_requester(&pdev->dev); 2897 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2898 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2899 } 2900 #endif 2901 2902 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2903 * would have already happened in close and is redundant. 2904 */ 2905 igb_release_hw_control(adapter); 2906 2907 #ifdef CONFIG_PCI_IOV 2908 igb_disable_sriov(pdev); 2909 #endif 2910 2911 unregister_netdev(netdev); 2912 2913 igb_clear_interrupt_scheme(adapter); 2914 2915 pci_iounmap(pdev, adapter->io_addr); 2916 if (hw->flash_address) 2917 iounmap(hw->flash_address); 2918 pci_release_selected_regions(pdev, 2919 pci_select_bars(pdev, IORESOURCE_MEM)); 2920 2921 kfree(adapter->shadow_vfta); 2922 free_netdev(netdev); 2923 2924 pci_disable_pcie_error_reporting(pdev); 2925 2926 pci_disable_device(pdev); 2927 } 2928 2929 /** 2930 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2931 * @adapter: board private structure to initialize 2932 * 2933 * This function initializes the vf specific data storage and then attempts to 2934 * allocate the VFs. The reason for ordering it this way is because it is much 2935 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2936 * the memory for the VFs. 2937 **/ 2938 static void igb_probe_vfs(struct igb_adapter *adapter) 2939 { 2940 #ifdef CONFIG_PCI_IOV 2941 struct pci_dev *pdev = adapter->pdev; 2942 struct e1000_hw *hw = &adapter->hw; 2943 2944 /* Virtualization features not supported on i210 family. */ 2945 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2946 return; 2947 2948 /* Of the below we really only want the effect of getting 2949 * IGB_FLAG_HAS_MSIX set (if available), without which 2950 * igb_enable_sriov() has no effect. 2951 */ 2952 igb_set_interrupt_capability(adapter, true); 2953 igb_reset_interrupt_capability(adapter); 2954 2955 pci_sriov_set_totalvfs(pdev, 7); 2956 igb_enable_sriov(pdev, max_vfs); 2957 2958 #endif /* CONFIG_PCI_IOV */ 2959 } 2960 2961 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2962 { 2963 struct e1000_hw *hw = &adapter->hw; 2964 u32 max_rss_queues; 2965 2966 /* Determine the maximum number of RSS queues supported. */ 2967 switch (hw->mac.type) { 2968 case e1000_i211: 2969 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2970 break; 2971 case e1000_82575: 2972 case e1000_i210: 2973 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2974 break; 2975 case e1000_i350: 2976 /* I350 cannot do RSS and SR-IOV at the same time */ 2977 if (!!adapter->vfs_allocated_count) { 2978 max_rss_queues = 1; 2979 break; 2980 } 2981 /* fall through */ 2982 case e1000_82576: 2983 if (!!adapter->vfs_allocated_count) { 2984 max_rss_queues = 2; 2985 break; 2986 } 2987 /* fall through */ 2988 case e1000_82580: 2989 case e1000_i354: 2990 default: 2991 max_rss_queues = IGB_MAX_RX_QUEUES; 2992 break; 2993 } 2994 2995 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2996 2997 igb_set_flag_queue_pairs(adapter, max_rss_queues); 2998 } 2999 3000 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3001 const u32 max_rss_queues) 3002 { 3003 struct e1000_hw *hw = &adapter->hw; 3004 3005 /* Determine if we need to pair queues. */ 3006 switch (hw->mac.type) { 3007 case e1000_82575: 3008 case e1000_i211: 3009 /* Device supports enough interrupts without queue pairing. */ 3010 break; 3011 case e1000_82576: 3012 case e1000_82580: 3013 case e1000_i350: 3014 case e1000_i354: 3015 case e1000_i210: 3016 default: 3017 /* If rss_queues > half of max_rss_queues, pair the queues in 3018 * order to conserve interrupts due to limited supply. 3019 */ 3020 if (adapter->rss_queues > (max_rss_queues / 2)) 3021 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3022 else 3023 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3024 break; 3025 } 3026 } 3027 3028 /** 3029 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3030 * @adapter: board private structure to initialize 3031 * 3032 * igb_sw_init initializes the Adapter private data structure. 3033 * Fields are initialized based on PCI device information and 3034 * OS network device settings (MTU size). 3035 **/ 3036 static int igb_sw_init(struct igb_adapter *adapter) 3037 { 3038 struct e1000_hw *hw = &adapter->hw; 3039 struct net_device *netdev = adapter->netdev; 3040 struct pci_dev *pdev = adapter->pdev; 3041 3042 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3043 3044 /* set default ring sizes */ 3045 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3046 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3047 3048 /* set default ITR values */ 3049 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3050 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3051 3052 /* set default work limits */ 3053 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3054 3055 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3056 VLAN_HLEN; 3057 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3058 3059 spin_lock_init(&adapter->stats64_lock); 3060 #ifdef CONFIG_PCI_IOV 3061 switch (hw->mac.type) { 3062 case e1000_82576: 3063 case e1000_i350: 3064 if (max_vfs > 7) { 3065 dev_warn(&pdev->dev, 3066 "Maximum of 7 VFs per PF, using max\n"); 3067 max_vfs = adapter->vfs_allocated_count = 7; 3068 } else 3069 adapter->vfs_allocated_count = max_vfs; 3070 if (adapter->vfs_allocated_count) 3071 dev_warn(&pdev->dev, 3072 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3073 break; 3074 default: 3075 break; 3076 } 3077 #endif /* CONFIG_PCI_IOV */ 3078 3079 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3080 adapter->flags |= IGB_FLAG_HAS_MSIX; 3081 3082 igb_probe_vfs(adapter); 3083 3084 igb_init_queue_configuration(adapter); 3085 3086 /* Setup and initialize a copy of the hw vlan table array */ 3087 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3088 GFP_ATOMIC); 3089 3090 /* This call may decrease the number of queues */ 3091 if (igb_init_interrupt_scheme(adapter, true)) { 3092 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3093 return -ENOMEM; 3094 } 3095 3096 /* Explicitly disable IRQ since the NIC can be in any state. */ 3097 igb_irq_disable(adapter); 3098 3099 if (hw->mac.type >= e1000_i350) 3100 adapter->flags &= ~IGB_FLAG_DMAC; 3101 3102 set_bit(__IGB_DOWN, &adapter->state); 3103 return 0; 3104 } 3105 3106 /** 3107 * igb_open - Called when a network interface is made active 3108 * @netdev: network interface device structure 3109 * 3110 * Returns 0 on success, negative value on failure 3111 * 3112 * The open entry point is called when a network interface is made 3113 * active by the system (IFF_UP). At this point all resources needed 3114 * for transmit and receive operations are allocated, the interrupt 3115 * handler is registered with the OS, the watchdog timer is started, 3116 * and the stack is notified that the interface is ready. 3117 **/ 3118 static int __igb_open(struct net_device *netdev, bool resuming) 3119 { 3120 struct igb_adapter *adapter = netdev_priv(netdev); 3121 struct e1000_hw *hw = &adapter->hw; 3122 struct pci_dev *pdev = adapter->pdev; 3123 int err; 3124 int i; 3125 3126 /* disallow open during test */ 3127 if (test_bit(__IGB_TESTING, &adapter->state)) { 3128 WARN_ON(resuming); 3129 return -EBUSY; 3130 } 3131 3132 if (!resuming) 3133 pm_runtime_get_sync(&pdev->dev); 3134 3135 netif_carrier_off(netdev); 3136 3137 /* allocate transmit descriptors */ 3138 err = igb_setup_all_tx_resources(adapter); 3139 if (err) 3140 goto err_setup_tx; 3141 3142 /* allocate receive descriptors */ 3143 err = igb_setup_all_rx_resources(adapter); 3144 if (err) 3145 goto err_setup_rx; 3146 3147 igb_power_up_link(adapter); 3148 3149 /* before we allocate an interrupt, we must be ready to handle it. 3150 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3151 * as soon as we call pci_request_irq, so we have to setup our 3152 * clean_rx handler before we do so. 3153 */ 3154 igb_configure(adapter); 3155 3156 err = igb_request_irq(adapter); 3157 if (err) 3158 goto err_req_irq; 3159 3160 /* Notify the stack of the actual queue counts. */ 3161 err = netif_set_real_num_tx_queues(adapter->netdev, 3162 adapter->num_tx_queues); 3163 if (err) 3164 goto err_set_queues; 3165 3166 err = netif_set_real_num_rx_queues(adapter->netdev, 3167 adapter->num_rx_queues); 3168 if (err) 3169 goto err_set_queues; 3170 3171 /* From here on the code is the same as igb_up() */ 3172 clear_bit(__IGB_DOWN, &adapter->state); 3173 3174 for (i = 0; i < adapter->num_q_vectors; i++) 3175 napi_enable(&(adapter->q_vector[i]->napi)); 3176 3177 /* Clear any pending interrupts. */ 3178 rd32(E1000_ICR); 3179 3180 igb_irq_enable(adapter); 3181 3182 /* notify VFs that reset has been completed */ 3183 if (adapter->vfs_allocated_count) { 3184 u32 reg_data = rd32(E1000_CTRL_EXT); 3185 3186 reg_data |= E1000_CTRL_EXT_PFRSTD; 3187 wr32(E1000_CTRL_EXT, reg_data); 3188 } 3189 3190 netif_tx_start_all_queues(netdev); 3191 3192 if (!resuming) 3193 pm_runtime_put(&pdev->dev); 3194 3195 /* start the watchdog. */ 3196 hw->mac.get_link_status = 1; 3197 schedule_work(&adapter->watchdog_task); 3198 3199 return 0; 3200 3201 err_set_queues: 3202 igb_free_irq(adapter); 3203 err_req_irq: 3204 igb_release_hw_control(adapter); 3205 igb_power_down_link(adapter); 3206 igb_free_all_rx_resources(adapter); 3207 err_setup_rx: 3208 igb_free_all_tx_resources(adapter); 3209 err_setup_tx: 3210 igb_reset(adapter); 3211 if (!resuming) 3212 pm_runtime_put(&pdev->dev); 3213 3214 return err; 3215 } 3216 3217 int igb_open(struct net_device *netdev) 3218 { 3219 return __igb_open(netdev, false); 3220 } 3221 3222 /** 3223 * igb_close - Disables a network interface 3224 * @netdev: network interface device structure 3225 * 3226 * Returns 0, this is not allowed to fail 3227 * 3228 * The close entry point is called when an interface is de-activated 3229 * by the OS. The hardware is still under the driver's control, but 3230 * needs to be disabled. A global MAC reset is issued to stop the 3231 * hardware, and all transmit and receive resources are freed. 3232 **/ 3233 static int __igb_close(struct net_device *netdev, bool suspending) 3234 { 3235 struct igb_adapter *adapter = netdev_priv(netdev); 3236 struct pci_dev *pdev = adapter->pdev; 3237 3238 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3239 3240 if (!suspending) 3241 pm_runtime_get_sync(&pdev->dev); 3242 3243 igb_down(adapter); 3244 igb_free_irq(adapter); 3245 3246 igb_free_all_tx_resources(adapter); 3247 igb_free_all_rx_resources(adapter); 3248 3249 if (!suspending) 3250 pm_runtime_put_sync(&pdev->dev); 3251 return 0; 3252 } 3253 3254 int igb_close(struct net_device *netdev) 3255 { 3256 return __igb_close(netdev, false); 3257 } 3258 3259 /** 3260 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3261 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3262 * 3263 * Return 0 on success, negative on failure 3264 **/ 3265 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3266 { 3267 struct device *dev = tx_ring->dev; 3268 int size; 3269 3270 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3271 3272 tx_ring->tx_buffer_info = vzalloc(size); 3273 if (!tx_ring->tx_buffer_info) 3274 goto err; 3275 3276 /* round up to nearest 4K */ 3277 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3278 tx_ring->size = ALIGN(tx_ring->size, 4096); 3279 3280 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3281 &tx_ring->dma, GFP_KERNEL); 3282 if (!tx_ring->desc) 3283 goto err; 3284 3285 tx_ring->next_to_use = 0; 3286 tx_ring->next_to_clean = 0; 3287 3288 return 0; 3289 3290 err: 3291 vfree(tx_ring->tx_buffer_info); 3292 tx_ring->tx_buffer_info = NULL; 3293 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3294 return -ENOMEM; 3295 } 3296 3297 /** 3298 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3299 * (Descriptors) for all queues 3300 * @adapter: board private structure 3301 * 3302 * Return 0 on success, negative on failure 3303 **/ 3304 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3305 { 3306 struct pci_dev *pdev = adapter->pdev; 3307 int i, err = 0; 3308 3309 for (i = 0; i < adapter->num_tx_queues; i++) { 3310 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3311 if (err) { 3312 dev_err(&pdev->dev, 3313 "Allocation for Tx Queue %u failed\n", i); 3314 for (i--; i >= 0; i--) 3315 igb_free_tx_resources(adapter->tx_ring[i]); 3316 break; 3317 } 3318 } 3319 3320 return err; 3321 } 3322 3323 /** 3324 * igb_setup_tctl - configure the transmit control registers 3325 * @adapter: Board private structure 3326 **/ 3327 void igb_setup_tctl(struct igb_adapter *adapter) 3328 { 3329 struct e1000_hw *hw = &adapter->hw; 3330 u32 tctl; 3331 3332 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3333 wr32(E1000_TXDCTL(0), 0); 3334 3335 /* Program the Transmit Control Register */ 3336 tctl = rd32(E1000_TCTL); 3337 tctl &= ~E1000_TCTL_CT; 3338 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3339 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3340 3341 igb_config_collision_dist(hw); 3342 3343 /* Enable transmits */ 3344 tctl |= E1000_TCTL_EN; 3345 3346 wr32(E1000_TCTL, tctl); 3347 } 3348 3349 /** 3350 * igb_configure_tx_ring - Configure transmit ring after Reset 3351 * @adapter: board private structure 3352 * @ring: tx ring to configure 3353 * 3354 * Configure a transmit ring after a reset. 3355 **/ 3356 void igb_configure_tx_ring(struct igb_adapter *adapter, 3357 struct igb_ring *ring) 3358 { 3359 struct e1000_hw *hw = &adapter->hw; 3360 u32 txdctl = 0; 3361 u64 tdba = ring->dma; 3362 int reg_idx = ring->reg_idx; 3363 3364 /* disable the queue */ 3365 wr32(E1000_TXDCTL(reg_idx), 0); 3366 wrfl(); 3367 mdelay(10); 3368 3369 wr32(E1000_TDLEN(reg_idx), 3370 ring->count * sizeof(union e1000_adv_tx_desc)); 3371 wr32(E1000_TDBAL(reg_idx), 3372 tdba & 0x00000000ffffffffULL); 3373 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3374 3375 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3376 wr32(E1000_TDH(reg_idx), 0); 3377 writel(0, ring->tail); 3378 3379 txdctl |= IGB_TX_PTHRESH; 3380 txdctl |= IGB_TX_HTHRESH << 8; 3381 txdctl |= IGB_TX_WTHRESH << 16; 3382 3383 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3384 wr32(E1000_TXDCTL(reg_idx), txdctl); 3385 } 3386 3387 /** 3388 * igb_configure_tx - Configure transmit Unit after Reset 3389 * @adapter: board private structure 3390 * 3391 * Configure the Tx unit of the MAC after a reset. 3392 **/ 3393 static void igb_configure_tx(struct igb_adapter *adapter) 3394 { 3395 int i; 3396 3397 for (i = 0; i < adapter->num_tx_queues; i++) 3398 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3399 } 3400 3401 /** 3402 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3403 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3404 * 3405 * Returns 0 on success, negative on failure 3406 **/ 3407 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3408 { 3409 struct device *dev = rx_ring->dev; 3410 int size; 3411 3412 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3413 3414 rx_ring->rx_buffer_info = vzalloc(size); 3415 if (!rx_ring->rx_buffer_info) 3416 goto err; 3417 3418 /* Round up to nearest 4K */ 3419 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3420 rx_ring->size = ALIGN(rx_ring->size, 4096); 3421 3422 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3423 &rx_ring->dma, GFP_KERNEL); 3424 if (!rx_ring->desc) 3425 goto err; 3426 3427 rx_ring->next_to_alloc = 0; 3428 rx_ring->next_to_clean = 0; 3429 rx_ring->next_to_use = 0; 3430 3431 return 0; 3432 3433 err: 3434 vfree(rx_ring->rx_buffer_info); 3435 rx_ring->rx_buffer_info = NULL; 3436 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3437 return -ENOMEM; 3438 } 3439 3440 /** 3441 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3442 * (Descriptors) for all queues 3443 * @adapter: board private structure 3444 * 3445 * Return 0 on success, negative on failure 3446 **/ 3447 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3448 { 3449 struct pci_dev *pdev = adapter->pdev; 3450 int i, err = 0; 3451 3452 for (i = 0; i < adapter->num_rx_queues; i++) { 3453 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3454 if (err) { 3455 dev_err(&pdev->dev, 3456 "Allocation for Rx Queue %u failed\n", i); 3457 for (i--; i >= 0; i--) 3458 igb_free_rx_resources(adapter->rx_ring[i]); 3459 break; 3460 } 3461 } 3462 3463 return err; 3464 } 3465 3466 /** 3467 * igb_setup_mrqc - configure the multiple receive queue control registers 3468 * @adapter: Board private structure 3469 **/ 3470 static void igb_setup_mrqc(struct igb_adapter *adapter) 3471 { 3472 struct e1000_hw *hw = &adapter->hw; 3473 u32 mrqc, rxcsum; 3474 u32 j, num_rx_queues; 3475 u32 rss_key[10]; 3476 3477 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3478 for (j = 0; j < 10; j++) 3479 wr32(E1000_RSSRK(j), rss_key[j]); 3480 3481 num_rx_queues = adapter->rss_queues; 3482 3483 switch (hw->mac.type) { 3484 case e1000_82576: 3485 /* 82576 supports 2 RSS queues for SR-IOV */ 3486 if (adapter->vfs_allocated_count) 3487 num_rx_queues = 2; 3488 break; 3489 default: 3490 break; 3491 } 3492 3493 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3494 for (j = 0; j < IGB_RETA_SIZE; j++) 3495 adapter->rss_indir_tbl[j] = 3496 (j * num_rx_queues) / IGB_RETA_SIZE; 3497 adapter->rss_indir_tbl_init = num_rx_queues; 3498 } 3499 igb_write_rss_indir_tbl(adapter); 3500 3501 /* Disable raw packet checksumming so that RSS hash is placed in 3502 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3503 * offloads as they are enabled by default 3504 */ 3505 rxcsum = rd32(E1000_RXCSUM); 3506 rxcsum |= E1000_RXCSUM_PCSD; 3507 3508 if (adapter->hw.mac.type >= e1000_82576) 3509 /* Enable Receive Checksum Offload for SCTP */ 3510 rxcsum |= E1000_RXCSUM_CRCOFL; 3511 3512 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3513 wr32(E1000_RXCSUM, rxcsum); 3514 3515 /* Generate RSS hash based on packet types, TCP/UDP 3516 * port numbers and/or IPv4/v6 src and dst addresses 3517 */ 3518 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3519 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3520 E1000_MRQC_RSS_FIELD_IPV6 | 3521 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3522 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3523 3524 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3525 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3526 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3527 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3528 3529 /* If VMDq is enabled then we set the appropriate mode for that, else 3530 * we default to RSS so that an RSS hash is calculated per packet even 3531 * if we are only using one queue 3532 */ 3533 if (adapter->vfs_allocated_count) { 3534 if (hw->mac.type > e1000_82575) { 3535 /* Set the default pool for the PF's first queue */ 3536 u32 vtctl = rd32(E1000_VT_CTL); 3537 3538 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3539 E1000_VT_CTL_DISABLE_DEF_POOL); 3540 vtctl |= adapter->vfs_allocated_count << 3541 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3542 wr32(E1000_VT_CTL, vtctl); 3543 } 3544 if (adapter->rss_queues > 1) 3545 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3546 else 3547 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3548 } else { 3549 if (hw->mac.type != e1000_i211) 3550 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3551 } 3552 igb_vmm_control(adapter); 3553 3554 wr32(E1000_MRQC, mrqc); 3555 } 3556 3557 /** 3558 * igb_setup_rctl - configure the receive control registers 3559 * @adapter: Board private structure 3560 **/ 3561 void igb_setup_rctl(struct igb_adapter *adapter) 3562 { 3563 struct e1000_hw *hw = &adapter->hw; 3564 u32 rctl; 3565 3566 rctl = rd32(E1000_RCTL); 3567 3568 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3569 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3570 3571 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3572 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3573 3574 /* enable stripping of CRC. It's unlikely this will break BMC 3575 * redirection as it did with e1000. Newer features require 3576 * that the HW strips the CRC. 3577 */ 3578 rctl |= E1000_RCTL_SECRC; 3579 3580 /* disable store bad packets and clear size bits. */ 3581 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3582 3583 /* enable LPE to allow for reception of jumbo frames */ 3584 rctl |= E1000_RCTL_LPE; 3585 3586 /* disable queue 0 to prevent tail write w/o re-config */ 3587 wr32(E1000_RXDCTL(0), 0); 3588 3589 /* Attention!!! For SR-IOV PF driver operations you must enable 3590 * queue drop for all VF and PF queues to prevent head of line blocking 3591 * if an un-trusted VF does not provide descriptors to hardware. 3592 */ 3593 if (adapter->vfs_allocated_count) { 3594 /* set all queue drop enable bits */ 3595 wr32(E1000_QDE, ALL_QUEUES); 3596 } 3597 3598 /* This is useful for sniffing bad packets. */ 3599 if (adapter->netdev->features & NETIF_F_RXALL) { 3600 /* UPE and MPE will be handled by normal PROMISC logic 3601 * in e1000e_set_rx_mode 3602 */ 3603 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3604 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3605 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3606 3607 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3608 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3609 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3610 * and that breaks VLANs. 3611 */ 3612 } 3613 3614 wr32(E1000_RCTL, rctl); 3615 } 3616 3617 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3618 int vfn) 3619 { 3620 struct e1000_hw *hw = &adapter->hw; 3621 u32 vmolr; 3622 3623 if (size > MAX_JUMBO_FRAME_SIZE) 3624 size = MAX_JUMBO_FRAME_SIZE; 3625 3626 vmolr = rd32(E1000_VMOLR(vfn)); 3627 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3628 vmolr |= size | E1000_VMOLR_LPE; 3629 wr32(E1000_VMOLR(vfn), vmolr); 3630 3631 return 0; 3632 } 3633 3634 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3635 int vfn, bool enable) 3636 { 3637 struct e1000_hw *hw = &adapter->hw; 3638 u32 val, reg; 3639 3640 if (hw->mac.type < e1000_82576) 3641 return; 3642 3643 if (hw->mac.type == e1000_i350) 3644 reg = E1000_DVMOLR(vfn); 3645 else 3646 reg = E1000_VMOLR(vfn); 3647 3648 val = rd32(reg); 3649 if (enable) 3650 val |= E1000_VMOLR_STRVLAN; 3651 else 3652 val &= ~(E1000_VMOLR_STRVLAN); 3653 wr32(reg, val); 3654 } 3655 3656 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3657 int vfn, bool aupe) 3658 { 3659 struct e1000_hw *hw = &adapter->hw; 3660 u32 vmolr; 3661 3662 /* This register exists only on 82576 and newer so if we are older then 3663 * we should exit and do nothing 3664 */ 3665 if (hw->mac.type < e1000_82576) 3666 return; 3667 3668 vmolr = rd32(E1000_VMOLR(vfn)); 3669 if (aupe) 3670 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3671 else 3672 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3673 3674 /* clear all bits that might not be set */ 3675 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3676 3677 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3678 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3679 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3680 * multicast packets 3681 */ 3682 if (vfn <= adapter->vfs_allocated_count) 3683 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3684 3685 wr32(E1000_VMOLR(vfn), vmolr); 3686 } 3687 3688 /** 3689 * igb_configure_rx_ring - Configure a receive ring after Reset 3690 * @adapter: board private structure 3691 * @ring: receive ring to be configured 3692 * 3693 * Configure the Rx unit of the MAC after a reset. 3694 **/ 3695 void igb_configure_rx_ring(struct igb_adapter *adapter, 3696 struct igb_ring *ring) 3697 { 3698 struct e1000_hw *hw = &adapter->hw; 3699 u64 rdba = ring->dma; 3700 int reg_idx = ring->reg_idx; 3701 u32 srrctl = 0, rxdctl = 0; 3702 3703 /* disable the queue */ 3704 wr32(E1000_RXDCTL(reg_idx), 0); 3705 3706 /* Set DMA base address registers */ 3707 wr32(E1000_RDBAL(reg_idx), 3708 rdba & 0x00000000ffffffffULL); 3709 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3710 wr32(E1000_RDLEN(reg_idx), 3711 ring->count * sizeof(union e1000_adv_rx_desc)); 3712 3713 /* initialize head and tail */ 3714 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3715 wr32(E1000_RDH(reg_idx), 0); 3716 writel(0, ring->tail); 3717 3718 /* set descriptor configuration */ 3719 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3720 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3721 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3722 if (hw->mac.type >= e1000_82580) 3723 srrctl |= E1000_SRRCTL_TIMESTAMP; 3724 /* Only set Drop Enable if we are supporting multiple queues */ 3725 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3726 srrctl |= E1000_SRRCTL_DROP_EN; 3727 3728 wr32(E1000_SRRCTL(reg_idx), srrctl); 3729 3730 /* set filtering for VMDQ pools */ 3731 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3732 3733 rxdctl |= IGB_RX_PTHRESH; 3734 rxdctl |= IGB_RX_HTHRESH << 8; 3735 rxdctl |= IGB_RX_WTHRESH << 16; 3736 3737 /* enable receive descriptor fetching */ 3738 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3739 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3740 } 3741 3742 /** 3743 * igb_configure_rx - Configure receive Unit after Reset 3744 * @adapter: board private structure 3745 * 3746 * Configure the Rx unit of the MAC after a reset. 3747 **/ 3748 static void igb_configure_rx(struct igb_adapter *adapter) 3749 { 3750 int i; 3751 3752 /* set the correct pool for the PF default MAC address in entry 0 */ 3753 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3754 adapter->vfs_allocated_count); 3755 3756 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3757 * the Base and Length of the Rx Descriptor Ring 3758 */ 3759 for (i = 0; i < adapter->num_rx_queues; i++) 3760 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3761 } 3762 3763 /** 3764 * igb_free_tx_resources - Free Tx Resources per Queue 3765 * @tx_ring: Tx descriptor ring for a specific queue 3766 * 3767 * Free all transmit software resources 3768 **/ 3769 void igb_free_tx_resources(struct igb_ring *tx_ring) 3770 { 3771 igb_clean_tx_ring(tx_ring); 3772 3773 vfree(tx_ring->tx_buffer_info); 3774 tx_ring->tx_buffer_info = NULL; 3775 3776 /* if not set, then don't free */ 3777 if (!tx_ring->desc) 3778 return; 3779 3780 dma_free_coherent(tx_ring->dev, tx_ring->size, 3781 tx_ring->desc, tx_ring->dma); 3782 3783 tx_ring->desc = NULL; 3784 } 3785 3786 /** 3787 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3788 * @adapter: board private structure 3789 * 3790 * Free all transmit software resources 3791 **/ 3792 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3793 { 3794 int i; 3795 3796 for (i = 0; i < adapter->num_tx_queues; i++) 3797 if (adapter->tx_ring[i]) 3798 igb_free_tx_resources(adapter->tx_ring[i]); 3799 } 3800 3801 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3802 struct igb_tx_buffer *tx_buffer) 3803 { 3804 if (tx_buffer->skb) { 3805 dev_kfree_skb_any(tx_buffer->skb); 3806 if (dma_unmap_len(tx_buffer, len)) 3807 dma_unmap_single(ring->dev, 3808 dma_unmap_addr(tx_buffer, dma), 3809 dma_unmap_len(tx_buffer, len), 3810 DMA_TO_DEVICE); 3811 } else if (dma_unmap_len(tx_buffer, len)) { 3812 dma_unmap_page(ring->dev, 3813 dma_unmap_addr(tx_buffer, dma), 3814 dma_unmap_len(tx_buffer, len), 3815 DMA_TO_DEVICE); 3816 } 3817 tx_buffer->next_to_watch = NULL; 3818 tx_buffer->skb = NULL; 3819 dma_unmap_len_set(tx_buffer, len, 0); 3820 /* buffer_info must be completely set up in the transmit path */ 3821 } 3822 3823 /** 3824 * igb_clean_tx_ring - Free Tx Buffers 3825 * @tx_ring: ring to be cleaned 3826 **/ 3827 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3828 { 3829 struct igb_tx_buffer *buffer_info; 3830 unsigned long size; 3831 u16 i; 3832 3833 if (!tx_ring->tx_buffer_info) 3834 return; 3835 /* Free all the Tx ring sk_buffs */ 3836 3837 for (i = 0; i < tx_ring->count; i++) { 3838 buffer_info = &tx_ring->tx_buffer_info[i]; 3839 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3840 } 3841 3842 netdev_tx_reset_queue(txring_txq(tx_ring)); 3843 3844 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3845 memset(tx_ring->tx_buffer_info, 0, size); 3846 3847 /* Zero out the descriptor ring */ 3848 memset(tx_ring->desc, 0, tx_ring->size); 3849 3850 tx_ring->next_to_use = 0; 3851 tx_ring->next_to_clean = 0; 3852 } 3853 3854 /** 3855 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3856 * @adapter: board private structure 3857 **/ 3858 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3859 { 3860 int i; 3861 3862 for (i = 0; i < adapter->num_tx_queues; i++) 3863 if (adapter->tx_ring[i]) 3864 igb_clean_tx_ring(adapter->tx_ring[i]); 3865 } 3866 3867 /** 3868 * igb_free_rx_resources - Free Rx Resources 3869 * @rx_ring: ring to clean the resources from 3870 * 3871 * Free all receive software resources 3872 **/ 3873 void igb_free_rx_resources(struct igb_ring *rx_ring) 3874 { 3875 igb_clean_rx_ring(rx_ring); 3876 3877 vfree(rx_ring->rx_buffer_info); 3878 rx_ring->rx_buffer_info = NULL; 3879 3880 /* if not set, then don't free */ 3881 if (!rx_ring->desc) 3882 return; 3883 3884 dma_free_coherent(rx_ring->dev, rx_ring->size, 3885 rx_ring->desc, rx_ring->dma); 3886 3887 rx_ring->desc = NULL; 3888 } 3889 3890 /** 3891 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3892 * @adapter: board private structure 3893 * 3894 * Free all receive software resources 3895 **/ 3896 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3897 { 3898 int i; 3899 3900 for (i = 0; i < adapter->num_rx_queues; i++) 3901 if (adapter->rx_ring[i]) 3902 igb_free_rx_resources(adapter->rx_ring[i]); 3903 } 3904 3905 /** 3906 * igb_clean_rx_ring - Free Rx Buffers per Queue 3907 * @rx_ring: ring to free buffers from 3908 **/ 3909 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3910 { 3911 unsigned long size; 3912 u16 i; 3913 3914 if (rx_ring->skb) 3915 dev_kfree_skb(rx_ring->skb); 3916 rx_ring->skb = NULL; 3917 3918 if (!rx_ring->rx_buffer_info) 3919 return; 3920 3921 /* Free all the Rx ring sk_buffs */ 3922 for (i = 0; i < rx_ring->count; i++) { 3923 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3924 3925 if (!buffer_info->page) 3926 continue; 3927 3928 dma_unmap_page(rx_ring->dev, 3929 buffer_info->dma, 3930 PAGE_SIZE, 3931 DMA_FROM_DEVICE); 3932 __free_page(buffer_info->page); 3933 3934 buffer_info->page = NULL; 3935 } 3936 3937 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3938 memset(rx_ring->rx_buffer_info, 0, size); 3939 3940 /* Zero out the descriptor ring */ 3941 memset(rx_ring->desc, 0, rx_ring->size); 3942 3943 rx_ring->next_to_alloc = 0; 3944 rx_ring->next_to_clean = 0; 3945 rx_ring->next_to_use = 0; 3946 } 3947 3948 /** 3949 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3950 * @adapter: board private structure 3951 **/ 3952 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3953 { 3954 int i; 3955 3956 for (i = 0; i < adapter->num_rx_queues; i++) 3957 if (adapter->rx_ring[i]) 3958 igb_clean_rx_ring(adapter->rx_ring[i]); 3959 } 3960 3961 /** 3962 * igb_set_mac - Change the Ethernet Address of the NIC 3963 * @netdev: network interface device structure 3964 * @p: pointer to an address structure 3965 * 3966 * Returns 0 on success, negative on failure 3967 **/ 3968 static int igb_set_mac(struct net_device *netdev, void *p) 3969 { 3970 struct igb_adapter *adapter = netdev_priv(netdev); 3971 struct e1000_hw *hw = &adapter->hw; 3972 struct sockaddr *addr = p; 3973 3974 if (!is_valid_ether_addr(addr->sa_data)) 3975 return -EADDRNOTAVAIL; 3976 3977 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3978 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3979 3980 /* set the correct pool for the new PF MAC address in entry 0 */ 3981 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3982 adapter->vfs_allocated_count); 3983 3984 return 0; 3985 } 3986 3987 /** 3988 * igb_write_mc_addr_list - write multicast addresses to MTA 3989 * @netdev: network interface device structure 3990 * 3991 * Writes multicast address list to the MTA hash table. 3992 * Returns: -ENOMEM on failure 3993 * 0 on no addresses written 3994 * X on writing X addresses to MTA 3995 **/ 3996 static int igb_write_mc_addr_list(struct net_device *netdev) 3997 { 3998 struct igb_adapter *adapter = netdev_priv(netdev); 3999 struct e1000_hw *hw = &adapter->hw; 4000 struct netdev_hw_addr *ha; 4001 u8 *mta_list; 4002 int i; 4003 4004 if (netdev_mc_empty(netdev)) { 4005 /* nothing to program, so clear mc list */ 4006 igb_update_mc_addr_list(hw, NULL, 0); 4007 igb_restore_vf_multicasts(adapter); 4008 return 0; 4009 } 4010 4011 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4012 if (!mta_list) 4013 return -ENOMEM; 4014 4015 /* The shared function expects a packed array of only addresses. */ 4016 i = 0; 4017 netdev_for_each_mc_addr(ha, netdev) 4018 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4019 4020 igb_update_mc_addr_list(hw, mta_list, i); 4021 kfree(mta_list); 4022 4023 return netdev_mc_count(netdev); 4024 } 4025 4026 /** 4027 * igb_write_uc_addr_list - write unicast addresses to RAR table 4028 * @netdev: network interface device structure 4029 * 4030 * Writes unicast address list to the RAR table. 4031 * Returns: -ENOMEM on failure/insufficient address space 4032 * 0 on no addresses written 4033 * X on writing X addresses to the RAR table 4034 **/ 4035 static int igb_write_uc_addr_list(struct net_device *netdev) 4036 { 4037 struct igb_adapter *adapter = netdev_priv(netdev); 4038 struct e1000_hw *hw = &adapter->hw; 4039 unsigned int vfn = adapter->vfs_allocated_count; 4040 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 4041 int count = 0; 4042 4043 /* return ENOMEM indicating insufficient memory for addresses */ 4044 if (netdev_uc_count(netdev) > rar_entries) 4045 return -ENOMEM; 4046 4047 if (!netdev_uc_empty(netdev) && rar_entries) { 4048 struct netdev_hw_addr *ha; 4049 4050 netdev_for_each_uc_addr(ha, netdev) { 4051 if (!rar_entries) 4052 break; 4053 igb_rar_set_qsel(adapter, ha->addr, 4054 rar_entries--, 4055 vfn); 4056 count++; 4057 } 4058 } 4059 /* write the addresses in reverse order to avoid write combining */ 4060 for (; rar_entries > 0 ; rar_entries--) { 4061 wr32(E1000_RAH(rar_entries), 0); 4062 wr32(E1000_RAL(rar_entries), 0); 4063 } 4064 wrfl(); 4065 4066 return count; 4067 } 4068 4069 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4070 { 4071 struct e1000_hw *hw = &adapter->hw; 4072 u32 i, pf_id; 4073 4074 switch (hw->mac.type) { 4075 case e1000_i210: 4076 case e1000_i211: 4077 case e1000_i350: 4078 /* VLAN filtering needed for VLAN prio filter */ 4079 if (adapter->netdev->features & NETIF_F_NTUPLE) 4080 break; 4081 /* fall through */ 4082 case e1000_82576: 4083 case e1000_82580: 4084 case e1000_i354: 4085 /* VLAN filtering needed for pool filtering */ 4086 if (adapter->vfs_allocated_count) 4087 break; 4088 /* fall through */ 4089 default: 4090 return 1; 4091 } 4092 4093 /* We are already in VLAN promisc, nothing to do */ 4094 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4095 return 0; 4096 4097 if (!adapter->vfs_allocated_count) 4098 goto set_vfta; 4099 4100 /* Add PF to all active pools */ 4101 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4102 4103 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4104 u32 vlvf = rd32(E1000_VLVF(i)); 4105 4106 vlvf |= BIT(pf_id); 4107 wr32(E1000_VLVF(i), vlvf); 4108 } 4109 4110 set_vfta: 4111 /* Set all bits in the VLAN filter table array */ 4112 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4113 hw->mac.ops.write_vfta(hw, i, ~0U); 4114 4115 /* Set flag so we don't redo unnecessary work */ 4116 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4117 4118 return 0; 4119 } 4120 4121 #define VFTA_BLOCK_SIZE 8 4122 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4123 { 4124 struct e1000_hw *hw = &adapter->hw; 4125 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4126 u32 vid_start = vfta_offset * 32; 4127 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4128 u32 i, vid, word, bits, pf_id; 4129 4130 /* guarantee that we don't scrub out management VLAN */ 4131 vid = adapter->mng_vlan_id; 4132 if (vid >= vid_start && vid < vid_end) 4133 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4134 4135 if (!adapter->vfs_allocated_count) 4136 goto set_vfta; 4137 4138 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4139 4140 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4141 u32 vlvf = rd32(E1000_VLVF(i)); 4142 4143 /* pull VLAN ID from VLVF */ 4144 vid = vlvf & VLAN_VID_MASK; 4145 4146 /* only concern ourselves with a certain range */ 4147 if (vid < vid_start || vid >= vid_end) 4148 continue; 4149 4150 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4151 /* record VLAN ID in VFTA */ 4152 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4153 4154 /* if PF is part of this then continue */ 4155 if (test_bit(vid, adapter->active_vlans)) 4156 continue; 4157 } 4158 4159 /* remove PF from the pool */ 4160 bits = ~BIT(pf_id); 4161 bits &= rd32(E1000_VLVF(i)); 4162 wr32(E1000_VLVF(i), bits); 4163 } 4164 4165 set_vfta: 4166 /* extract values from active_vlans and write back to VFTA */ 4167 for (i = VFTA_BLOCK_SIZE; i--;) { 4168 vid = (vfta_offset + i) * 32; 4169 word = vid / BITS_PER_LONG; 4170 bits = vid % BITS_PER_LONG; 4171 4172 vfta[i] |= adapter->active_vlans[word] >> bits; 4173 4174 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4175 } 4176 } 4177 4178 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4179 { 4180 u32 i; 4181 4182 /* We are not in VLAN promisc, nothing to do */ 4183 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4184 return; 4185 4186 /* Set flag so we don't redo unnecessary work */ 4187 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4188 4189 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4190 igb_scrub_vfta(adapter, i); 4191 } 4192 4193 /** 4194 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4195 * @netdev: network interface device structure 4196 * 4197 * The set_rx_mode entry point is called whenever the unicast or multicast 4198 * address lists or the network interface flags are updated. This routine is 4199 * responsible for configuring the hardware for proper unicast, multicast, 4200 * promiscuous mode, and all-multi behavior. 4201 **/ 4202 static void igb_set_rx_mode(struct net_device *netdev) 4203 { 4204 struct igb_adapter *adapter = netdev_priv(netdev); 4205 struct e1000_hw *hw = &adapter->hw; 4206 unsigned int vfn = adapter->vfs_allocated_count; 4207 u32 rctl = 0, vmolr = 0; 4208 int count; 4209 4210 /* Check for Promiscuous and All Multicast modes */ 4211 if (netdev->flags & IFF_PROMISC) { 4212 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4213 vmolr |= E1000_VMOLR_MPME; 4214 4215 /* enable use of UTA filter to force packets to default pool */ 4216 if (hw->mac.type == e1000_82576) 4217 vmolr |= E1000_VMOLR_ROPE; 4218 } else { 4219 if (netdev->flags & IFF_ALLMULTI) { 4220 rctl |= E1000_RCTL_MPE; 4221 vmolr |= E1000_VMOLR_MPME; 4222 } else { 4223 /* Write addresses to the MTA, if the attempt fails 4224 * then we should just turn on promiscuous mode so 4225 * that we can at least receive multicast traffic 4226 */ 4227 count = igb_write_mc_addr_list(netdev); 4228 if (count < 0) { 4229 rctl |= E1000_RCTL_MPE; 4230 vmolr |= E1000_VMOLR_MPME; 4231 } else if (count) { 4232 vmolr |= E1000_VMOLR_ROMPE; 4233 } 4234 } 4235 } 4236 4237 /* Write addresses to available RAR registers, if there is not 4238 * sufficient space to store all the addresses then enable 4239 * unicast promiscuous mode 4240 */ 4241 count = igb_write_uc_addr_list(netdev); 4242 if (count < 0) { 4243 rctl |= E1000_RCTL_UPE; 4244 vmolr |= E1000_VMOLR_ROPE; 4245 } 4246 4247 /* enable VLAN filtering by default */ 4248 rctl |= E1000_RCTL_VFE; 4249 4250 /* disable VLAN filtering for modes that require it */ 4251 if ((netdev->flags & IFF_PROMISC) || 4252 (netdev->features & NETIF_F_RXALL)) { 4253 /* if we fail to set all rules then just clear VFE */ 4254 if (igb_vlan_promisc_enable(adapter)) 4255 rctl &= ~E1000_RCTL_VFE; 4256 } else { 4257 igb_vlan_promisc_disable(adapter); 4258 } 4259 4260 /* update state of unicast, multicast, and VLAN filtering modes */ 4261 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4262 E1000_RCTL_VFE); 4263 wr32(E1000_RCTL, rctl); 4264 4265 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4266 * the VMOLR to enable the appropriate modes. Without this workaround 4267 * we will have issues with VLAN tag stripping not being done for frames 4268 * that are only arriving because we are the default pool 4269 */ 4270 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4271 return; 4272 4273 /* set UTA to appropriate mode */ 4274 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4275 4276 vmolr |= rd32(E1000_VMOLR(vfn)) & 4277 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4278 4279 /* enable Rx jumbo frames, no need for restriction */ 4280 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4281 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE; 4282 4283 wr32(E1000_VMOLR(vfn), vmolr); 4284 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE); 4285 4286 igb_restore_vf_multicasts(adapter); 4287 } 4288 4289 static void igb_check_wvbr(struct igb_adapter *adapter) 4290 { 4291 struct e1000_hw *hw = &adapter->hw; 4292 u32 wvbr = 0; 4293 4294 switch (hw->mac.type) { 4295 case e1000_82576: 4296 case e1000_i350: 4297 wvbr = rd32(E1000_WVBR); 4298 if (!wvbr) 4299 return; 4300 break; 4301 default: 4302 break; 4303 } 4304 4305 adapter->wvbr |= wvbr; 4306 } 4307 4308 #define IGB_STAGGERED_QUEUE_OFFSET 8 4309 4310 static void igb_spoof_check(struct igb_adapter *adapter) 4311 { 4312 int j; 4313 4314 if (!adapter->wvbr) 4315 return; 4316 4317 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4318 if (adapter->wvbr & BIT(j) || 4319 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4320 dev_warn(&adapter->pdev->dev, 4321 "Spoof event(s) detected on VF %d\n", j); 4322 adapter->wvbr &= 4323 ~(BIT(j) | 4324 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4325 } 4326 } 4327 } 4328 4329 /* Need to wait a few seconds after link up to get diagnostic information from 4330 * the phy 4331 */ 4332 static void igb_update_phy_info(unsigned long data) 4333 { 4334 struct igb_adapter *adapter = (struct igb_adapter *) data; 4335 igb_get_phy_info(&adapter->hw); 4336 } 4337 4338 /** 4339 * igb_has_link - check shared code for link and determine up/down 4340 * @adapter: pointer to driver private info 4341 **/ 4342 bool igb_has_link(struct igb_adapter *adapter) 4343 { 4344 struct e1000_hw *hw = &adapter->hw; 4345 bool link_active = false; 4346 4347 /* get_link_status is set on LSC (link status) interrupt or 4348 * rx sequence error interrupt. get_link_status will stay 4349 * false until the e1000_check_for_link establishes link 4350 * for copper adapters ONLY 4351 */ 4352 switch (hw->phy.media_type) { 4353 case e1000_media_type_copper: 4354 if (!hw->mac.get_link_status) 4355 return true; 4356 case e1000_media_type_internal_serdes: 4357 hw->mac.ops.check_for_link(hw); 4358 link_active = !hw->mac.get_link_status; 4359 break; 4360 default: 4361 case e1000_media_type_unknown: 4362 break; 4363 } 4364 4365 if (((hw->mac.type == e1000_i210) || 4366 (hw->mac.type == e1000_i211)) && 4367 (hw->phy.id == I210_I_PHY_ID)) { 4368 if (!netif_carrier_ok(adapter->netdev)) { 4369 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4370 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4371 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4372 adapter->link_check_timeout = jiffies; 4373 } 4374 } 4375 4376 return link_active; 4377 } 4378 4379 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4380 { 4381 bool ret = false; 4382 u32 ctrl_ext, thstat; 4383 4384 /* check for thermal sensor event on i350 copper only */ 4385 if (hw->mac.type == e1000_i350) { 4386 thstat = rd32(E1000_THSTAT); 4387 ctrl_ext = rd32(E1000_CTRL_EXT); 4388 4389 if ((hw->phy.media_type == e1000_media_type_copper) && 4390 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4391 ret = !!(thstat & event); 4392 } 4393 4394 return ret; 4395 } 4396 4397 /** 4398 * igb_check_lvmmc - check for malformed packets received 4399 * and indicated in LVMMC register 4400 * @adapter: pointer to adapter 4401 **/ 4402 static void igb_check_lvmmc(struct igb_adapter *adapter) 4403 { 4404 struct e1000_hw *hw = &adapter->hw; 4405 u32 lvmmc; 4406 4407 lvmmc = rd32(E1000_LVMMC); 4408 if (lvmmc) { 4409 if (unlikely(net_ratelimit())) { 4410 netdev_warn(adapter->netdev, 4411 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4412 lvmmc); 4413 } 4414 } 4415 } 4416 4417 /** 4418 * igb_watchdog - Timer Call-back 4419 * @data: pointer to adapter cast into an unsigned long 4420 **/ 4421 static void igb_watchdog(unsigned long data) 4422 { 4423 struct igb_adapter *adapter = (struct igb_adapter *)data; 4424 /* Do the rest outside of interrupt context */ 4425 schedule_work(&adapter->watchdog_task); 4426 } 4427 4428 static void igb_watchdog_task(struct work_struct *work) 4429 { 4430 struct igb_adapter *adapter = container_of(work, 4431 struct igb_adapter, 4432 watchdog_task); 4433 struct e1000_hw *hw = &adapter->hw; 4434 struct e1000_phy_info *phy = &hw->phy; 4435 struct net_device *netdev = adapter->netdev; 4436 u32 link; 4437 int i; 4438 u32 connsw; 4439 u16 phy_data, retry_count = 20; 4440 4441 link = igb_has_link(adapter); 4442 4443 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4444 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4445 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4446 else 4447 link = false; 4448 } 4449 4450 /* Force link down if we have fiber to swap to */ 4451 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4452 if (hw->phy.media_type == e1000_media_type_copper) { 4453 connsw = rd32(E1000_CONNSW); 4454 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4455 link = 0; 4456 } 4457 } 4458 if (link) { 4459 /* Perform a reset if the media type changed. */ 4460 if (hw->dev_spec._82575.media_changed) { 4461 hw->dev_spec._82575.media_changed = false; 4462 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4463 igb_reset(adapter); 4464 } 4465 /* Cancel scheduled suspend requests. */ 4466 pm_runtime_resume(netdev->dev.parent); 4467 4468 if (!netif_carrier_ok(netdev)) { 4469 u32 ctrl; 4470 4471 hw->mac.ops.get_speed_and_duplex(hw, 4472 &adapter->link_speed, 4473 &adapter->link_duplex); 4474 4475 ctrl = rd32(E1000_CTRL); 4476 /* Links status message must follow this format */ 4477 netdev_info(netdev, 4478 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4479 netdev->name, 4480 adapter->link_speed, 4481 adapter->link_duplex == FULL_DUPLEX ? 4482 "Full" : "Half", 4483 (ctrl & E1000_CTRL_TFCE) && 4484 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4485 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4486 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4487 4488 /* disable EEE if enabled */ 4489 if ((adapter->flags & IGB_FLAG_EEE) && 4490 (adapter->link_duplex == HALF_DUPLEX)) { 4491 dev_info(&adapter->pdev->dev, 4492 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4493 adapter->hw.dev_spec._82575.eee_disable = true; 4494 adapter->flags &= ~IGB_FLAG_EEE; 4495 } 4496 4497 /* check if SmartSpeed worked */ 4498 igb_check_downshift(hw); 4499 if (phy->speed_downgraded) 4500 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4501 4502 /* check for thermal sensor event */ 4503 if (igb_thermal_sensor_event(hw, 4504 E1000_THSTAT_LINK_THROTTLE)) 4505 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4506 4507 /* adjust timeout factor according to speed/duplex */ 4508 adapter->tx_timeout_factor = 1; 4509 switch (adapter->link_speed) { 4510 case SPEED_10: 4511 adapter->tx_timeout_factor = 14; 4512 break; 4513 case SPEED_100: 4514 /* maybe add some timeout factor ? */ 4515 break; 4516 } 4517 4518 if (adapter->link_speed != SPEED_1000) 4519 goto no_wait; 4520 4521 /* wait for Remote receiver status OK */ 4522 retry_read_status: 4523 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4524 &phy_data)) { 4525 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4526 retry_count) { 4527 msleep(100); 4528 retry_count--; 4529 goto retry_read_status; 4530 } else if (!retry_count) { 4531 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4532 } 4533 } else { 4534 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4535 } 4536 no_wait: 4537 netif_carrier_on(netdev); 4538 4539 igb_ping_all_vfs(adapter); 4540 igb_check_vf_rate_limit(adapter); 4541 4542 /* link state has changed, schedule phy info update */ 4543 if (!test_bit(__IGB_DOWN, &adapter->state)) 4544 mod_timer(&adapter->phy_info_timer, 4545 round_jiffies(jiffies + 2 * HZ)); 4546 } 4547 } else { 4548 if (netif_carrier_ok(netdev)) { 4549 adapter->link_speed = 0; 4550 adapter->link_duplex = 0; 4551 4552 /* check for thermal sensor event */ 4553 if (igb_thermal_sensor_event(hw, 4554 E1000_THSTAT_PWR_DOWN)) { 4555 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4556 } 4557 4558 /* Links status message must follow this format */ 4559 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4560 netdev->name); 4561 netif_carrier_off(netdev); 4562 4563 igb_ping_all_vfs(adapter); 4564 4565 /* link state has changed, schedule phy info update */ 4566 if (!test_bit(__IGB_DOWN, &adapter->state)) 4567 mod_timer(&adapter->phy_info_timer, 4568 round_jiffies(jiffies + 2 * HZ)); 4569 4570 /* link is down, time to check for alternate media */ 4571 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4572 igb_check_swap_media(adapter); 4573 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4574 schedule_work(&adapter->reset_task); 4575 /* return immediately */ 4576 return; 4577 } 4578 } 4579 pm_schedule_suspend(netdev->dev.parent, 4580 MSEC_PER_SEC * 5); 4581 4582 /* also check for alternate media here */ 4583 } else if (!netif_carrier_ok(netdev) && 4584 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4585 igb_check_swap_media(adapter); 4586 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4587 schedule_work(&adapter->reset_task); 4588 /* return immediately */ 4589 return; 4590 } 4591 } 4592 } 4593 4594 spin_lock(&adapter->stats64_lock); 4595 igb_update_stats(adapter, &adapter->stats64); 4596 spin_unlock(&adapter->stats64_lock); 4597 4598 for (i = 0; i < adapter->num_tx_queues; i++) { 4599 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4600 if (!netif_carrier_ok(netdev)) { 4601 /* We've lost link, so the controller stops DMA, 4602 * but we've got queued Tx work that's never going 4603 * to get done, so reset controller to flush Tx. 4604 * (Do the reset outside of interrupt context). 4605 */ 4606 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4607 adapter->tx_timeout_count++; 4608 schedule_work(&adapter->reset_task); 4609 /* return immediately since reset is imminent */ 4610 return; 4611 } 4612 } 4613 4614 /* Force detection of hung controller every watchdog period */ 4615 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4616 } 4617 4618 /* Cause software interrupt to ensure Rx ring is cleaned */ 4619 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4620 u32 eics = 0; 4621 4622 for (i = 0; i < adapter->num_q_vectors; i++) 4623 eics |= adapter->q_vector[i]->eims_value; 4624 wr32(E1000_EICS, eics); 4625 } else { 4626 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4627 } 4628 4629 igb_spoof_check(adapter); 4630 igb_ptp_rx_hang(adapter); 4631 4632 /* Check LVMMC register on i350/i354 only */ 4633 if ((adapter->hw.mac.type == e1000_i350) || 4634 (adapter->hw.mac.type == e1000_i354)) 4635 igb_check_lvmmc(adapter); 4636 4637 /* Reset the timer */ 4638 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4639 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4640 mod_timer(&adapter->watchdog_timer, 4641 round_jiffies(jiffies + HZ)); 4642 else 4643 mod_timer(&adapter->watchdog_timer, 4644 round_jiffies(jiffies + 2 * HZ)); 4645 } 4646 } 4647 4648 enum latency_range { 4649 lowest_latency = 0, 4650 low_latency = 1, 4651 bulk_latency = 2, 4652 latency_invalid = 255 4653 }; 4654 4655 /** 4656 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4657 * @q_vector: pointer to q_vector 4658 * 4659 * Stores a new ITR value based on strictly on packet size. This 4660 * algorithm is less sophisticated than that used in igb_update_itr, 4661 * due to the difficulty of synchronizing statistics across multiple 4662 * receive rings. The divisors and thresholds used by this function 4663 * were determined based on theoretical maximum wire speed and testing 4664 * data, in order to minimize response time while increasing bulk 4665 * throughput. 4666 * This functionality is controlled by ethtool's coalescing settings. 4667 * NOTE: This function is called only when operating in a multiqueue 4668 * receive environment. 4669 **/ 4670 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4671 { 4672 int new_val = q_vector->itr_val; 4673 int avg_wire_size = 0; 4674 struct igb_adapter *adapter = q_vector->adapter; 4675 unsigned int packets; 4676 4677 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4678 * ints/sec - ITR timer value of 120 ticks. 4679 */ 4680 if (adapter->link_speed != SPEED_1000) { 4681 new_val = IGB_4K_ITR; 4682 goto set_itr_val; 4683 } 4684 4685 packets = q_vector->rx.total_packets; 4686 if (packets) 4687 avg_wire_size = q_vector->rx.total_bytes / packets; 4688 4689 packets = q_vector->tx.total_packets; 4690 if (packets) 4691 avg_wire_size = max_t(u32, avg_wire_size, 4692 q_vector->tx.total_bytes / packets); 4693 4694 /* if avg_wire_size isn't set no work was done */ 4695 if (!avg_wire_size) 4696 goto clear_counts; 4697 4698 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4699 avg_wire_size += 24; 4700 4701 /* Don't starve jumbo frames */ 4702 avg_wire_size = min(avg_wire_size, 3000); 4703 4704 /* Give a little boost to mid-size frames */ 4705 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4706 new_val = avg_wire_size / 3; 4707 else 4708 new_val = avg_wire_size / 2; 4709 4710 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4711 if (new_val < IGB_20K_ITR && 4712 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4713 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4714 new_val = IGB_20K_ITR; 4715 4716 set_itr_val: 4717 if (new_val != q_vector->itr_val) { 4718 q_vector->itr_val = new_val; 4719 q_vector->set_itr = 1; 4720 } 4721 clear_counts: 4722 q_vector->rx.total_bytes = 0; 4723 q_vector->rx.total_packets = 0; 4724 q_vector->tx.total_bytes = 0; 4725 q_vector->tx.total_packets = 0; 4726 } 4727 4728 /** 4729 * igb_update_itr - update the dynamic ITR value based on statistics 4730 * @q_vector: pointer to q_vector 4731 * @ring_container: ring info to update the itr for 4732 * 4733 * Stores a new ITR value based on packets and byte 4734 * counts during the last interrupt. The advantage of per interrupt 4735 * computation is faster updates and more accurate ITR for the current 4736 * traffic pattern. Constants in this function were computed 4737 * based on theoretical maximum wire speed and thresholds were set based 4738 * on testing data as well as attempting to minimize response time 4739 * while increasing bulk throughput. 4740 * This functionality is controlled by ethtool's coalescing settings. 4741 * NOTE: These calculations are only valid when operating in a single- 4742 * queue environment. 4743 **/ 4744 static void igb_update_itr(struct igb_q_vector *q_vector, 4745 struct igb_ring_container *ring_container) 4746 { 4747 unsigned int packets = ring_container->total_packets; 4748 unsigned int bytes = ring_container->total_bytes; 4749 u8 itrval = ring_container->itr; 4750 4751 /* no packets, exit with status unchanged */ 4752 if (packets == 0) 4753 return; 4754 4755 switch (itrval) { 4756 case lowest_latency: 4757 /* handle TSO and jumbo frames */ 4758 if (bytes/packets > 8000) 4759 itrval = bulk_latency; 4760 else if ((packets < 5) && (bytes > 512)) 4761 itrval = low_latency; 4762 break; 4763 case low_latency: /* 50 usec aka 20000 ints/s */ 4764 if (bytes > 10000) { 4765 /* this if handles the TSO accounting */ 4766 if (bytes/packets > 8000) 4767 itrval = bulk_latency; 4768 else if ((packets < 10) || ((bytes/packets) > 1200)) 4769 itrval = bulk_latency; 4770 else if ((packets > 35)) 4771 itrval = lowest_latency; 4772 } else if (bytes/packets > 2000) { 4773 itrval = bulk_latency; 4774 } else if (packets <= 2 && bytes < 512) { 4775 itrval = lowest_latency; 4776 } 4777 break; 4778 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4779 if (bytes > 25000) { 4780 if (packets > 35) 4781 itrval = low_latency; 4782 } else if (bytes < 1500) { 4783 itrval = low_latency; 4784 } 4785 break; 4786 } 4787 4788 /* clear work counters since we have the values we need */ 4789 ring_container->total_bytes = 0; 4790 ring_container->total_packets = 0; 4791 4792 /* write updated itr to ring container */ 4793 ring_container->itr = itrval; 4794 } 4795 4796 static void igb_set_itr(struct igb_q_vector *q_vector) 4797 { 4798 struct igb_adapter *adapter = q_vector->adapter; 4799 u32 new_itr = q_vector->itr_val; 4800 u8 current_itr = 0; 4801 4802 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4803 if (adapter->link_speed != SPEED_1000) { 4804 current_itr = 0; 4805 new_itr = IGB_4K_ITR; 4806 goto set_itr_now; 4807 } 4808 4809 igb_update_itr(q_vector, &q_vector->tx); 4810 igb_update_itr(q_vector, &q_vector->rx); 4811 4812 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4813 4814 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4815 if (current_itr == lowest_latency && 4816 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4817 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4818 current_itr = low_latency; 4819 4820 switch (current_itr) { 4821 /* counts and packets in update_itr are dependent on these numbers */ 4822 case lowest_latency: 4823 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4824 break; 4825 case low_latency: 4826 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4827 break; 4828 case bulk_latency: 4829 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4830 break; 4831 default: 4832 break; 4833 } 4834 4835 set_itr_now: 4836 if (new_itr != q_vector->itr_val) { 4837 /* this attempts to bias the interrupt rate towards Bulk 4838 * by adding intermediate steps when interrupt rate is 4839 * increasing 4840 */ 4841 new_itr = new_itr > q_vector->itr_val ? 4842 max((new_itr * q_vector->itr_val) / 4843 (new_itr + (q_vector->itr_val >> 2)), 4844 new_itr) : new_itr; 4845 /* Don't write the value here; it resets the adapter's 4846 * internal timer, and causes us to delay far longer than 4847 * we should between interrupts. Instead, we write the ITR 4848 * value at the beginning of the next interrupt so the timing 4849 * ends up being correct. 4850 */ 4851 q_vector->itr_val = new_itr; 4852 q_vector->set_itr = 1; 4853 } 4854 } 4855 4856 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4857 u32 type_tucmd, u32 mss_l4len_idx) 4858 { 4859 struct e1000_adv_tx_context_desc *context_desc; 4860 u16 i = tx_ring->next_to_use; 4861 4862 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4863 4864 i++; 4865 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4866 4867 /* set bits to identify this as an advanced context descriptor */ 4868 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4869 4870 /* For 82575, context index must be unique per ring. */ 4871 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4872 mss_l4len_idx |= tx_ring->reg_idx << 4; 4873 4874 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4875 context_desc->seqnum_seed = 0; 4876 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4877 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4878 } 4879 4880 static int igb_tso(struct igb_ring *tx_ring, 4881 struct igb_tx_buffer *first, 4882 u8 *hdr_len) 4883 { 4884 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4885 struct sk_buff *skb = first->skb; 4886 union { 4887 struct iphdr *v4; 4888 struct ipv6hdr *v6; 4889 unsigned char *hdr; 4890 } ip; 4891 union { 4892 struct tcphdr *tcp; 4893 unsigned char *hdr; 4894 } l4; 4895 u32 paylen, l4_offset; 4896 int err; 4897 4898 if (skb->ip_summed != CHECKSUM_PARTIAL) 4899 return 0; 4900 4901 if (!skb_is_gso(skb)) 4902 return 0; 4903 4904 err = skb_cow_head(skb, 0); 4905 if (err < 0) 4906 return err; 4907 4908 ip.hdr = skb_network_header(skb); 4909 l4.hdr = skb_checksum_start(skb); 4910 4911 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4912 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4913 4914 /* initialize outer IP header fields */ 4915 if (ip.v4->version == 4) { 4916 /* IP header will have to cancel out any data that 4917 * is not a part of the outer IP header 4918 */ 4919 ip.v4->check = csum_fold(csum_add(lco_csum(skb), 4920 csum_unfold(l4.tcp->check))); 4921 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4922 4923 ip.v4->tot_len = 0; 4924 first->tx_flags |= IGB_TX_FLAGS_TSO | 4925 IGB_TX_FLAGS_CSUM | 4926 IGB_TX_FLAGS_IPV4; 4927 } else { 4928 ip.v6->payload_len = 0; 4929 first->tx_flags |= IGB_TX_FLAGS_TSO | 4930 IGB_TX_FLAGS_CSUM; 4931 } 4932 4933 /* determine offset of inner transport header */ 4934 l4_offset = l4.hdr - skb->data; 4935 4936 /* compute length of segmentation header */ 4937 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 4938 4939 /* remove payload length from inner checksum */ 4940 paylen = skb->len - l4_offset; 4941 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 4942 4943 /* update gso size and bytecount with header size */ 4944 first->gso_segs = skb_shinfo(skb)->gso_segs; 4945 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4946 4947 /* MSS L4LEN IDX */ 4948 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 4949 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4950 4951 /* VLAN MACLEN IPLEN */ 4952 vlan_macip_lens = l4.hdr - ip.hdr; 4953 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 4954 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4955 4956 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4957 4958 return 1; 4959 } 4960 4961 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 4962 { 4963 unsigned int offset = 0; 4964 4965 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 4966 4967 return offset == skb_checksum_start_offset(skb); 4968 } 4969 4970 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4971 { 4972 struct sk_buff *skb = first->skb; 4973 u32 vlan_macip_lens = 0; 4974 u32 type_tucmd = 0; 4975 4976 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4977 csum_failed: 4978 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4979 return; 4980 goto no_csum; 4981 } 4982 4983 switch (skb->csum_offset) { 4984 case offsetof(struct tcphdr, check): 4985 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4986 /* fall through */ 4987 case offsetof(struct udphdr, check): 4988 break; 4989 case offsetof(struct sctphdr, checksum): 4990 /* validate that this is actually an SCTP request */ 4991 if (((first->protocol == htons(ETH_P_IP)) && 4992 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 4993 ((first->protocol == htons(ETH_P_IPV6)) && 4994 igb_ipv6_csum_is_sctp(skb))) { 4995 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 4996 break; 4997 } 4998 default: 4999 skb_checksum_help(skb); 5000 goto csum_failed; 5001 } 5002 5003 /* update TX checksum flag */ 5004 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5005 vlan_macip_lens = skb_checksum_start_offset(skb) - 5006 skb_network_offset(skb); 5007 no_csum: 5008 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5009 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5010 5011 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5012 } 5013 5014 #define IGB_SET_FLAG(_input, _flag, _result) \ 5015 ((_flag <= _result) ? \ 5016 ((u32)(_input & _flag) * (_result / _flag)) : \ 5017 ((u32)(_input & _flag) / (_flag / _result))) 5018 5019 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5020 { 5021 /* set type for advanced descriptor with frame checksum insertion */ 5022 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5023 E1000_ADVTXD_DCMD_DEXT | 5024 E1000_ADVTXD_DCMD_IFCS; 5025 5026 /* set HW vlan bit if vlan is present */ 5027 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5028 (E1000_ADVTXD_DCMD_VLE)); 5029 5030 /* set segmentation bits for TSO */ 5031 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5032 (E1000_ADVTXD_DCMD_TSE)); 5033 5034 /* set timestamp bit if present */ 5035 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5036 (E1000_ADVTXD_MAC_TSTAMP)); 5037 5038 /* insert frame checksum */ 5039 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5040 5041 return cmd_type; 5042 } 5043 5044 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5045 union e1000_adv_tx_desc *tx_desc, 5046 u32 tx_flags, unsigned int paylen) 5047 { 5048 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5049 5050 /* 82575 requires a unique index per ring */ 5051 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5052 olinfo_status |= tx_ring->reg_idx << 4; 5053 5054 /* insert L4 checksum */ 5055 olinfo_status |= IGB_SET_FLAG(tx_flags, 5056 IGB_TX_FLAGS_CSUM, 5057 (E1000_TXD_POPTS_TXSM << 8)); 5058 5059 /* insert IPv4 checksum */ 5060 olinfo_status |= IGB_SET_FLAG(tx_flags, 5061 IGB_TX_FLAGS_IPV4, 5062 (E1000_TXD_POPTS_IXSM << 8)); 5063 5064 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5065 } 5066 5067 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5068 { 5069 struct net_device *netdev = tx_ring->netdev; 5070 5071 netif_stop_subqueue(netdev, tx_ring->queue_index); 5072 5073 /* Herbert's original patch had: 5074 * smp_mb__after_netif_stop_queue(); 5075 * but since that doesn't exist yet, just open code it. 5076 */ 5077 smp_mb(); 5078 5079 /* We need to check again in a case another CPU has just 5080 * made room available. 5081 */ 5082 if (igb_desc_unused(tx_ring) < size) 5083 return -EBUSY; 5084 5085 /* A reprieve! */ 5086 netif_wake_subqueue(netdev, tx_ring->queue_index); 5087 5088 u64_stats_update_begin(&tx_ring->tx_syncp2); 5089 tx_ring->tx_stats.restart_queue2++; 5090 u64_stats_update_end(&tx_ring->tx_syncp2); 5091 5092 return 0; 5093 } 5094 5095 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5096 { 5097 if (igb_desc_unused(tx_ring) >= size) 5098 return 0; 5099 return __igb_maybe_stop_tx(tx_ring, size); 5100 } 5101 5102 static void igb_tx_map(struct igb_ring *tx_ring, 5103 struct igb_tx_buffer *first, 5104 const u8 hdr_len) 5105 { 5106 struct sk_buff *skb = first->skb; 5107 struct igb_tx_buffer *tx_buffer; 5108 union e1000_adv_tx_desc *tx_desc; 5109 struct skb_frag_struct *frag; 5110 dma_addr_t dma; 5111 unsigned int data_len, size; 5112 u32 tx_flags = first->tx_flags; 5113 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5114 u16 i = tx_ring->next_to_use; 5115 5116 tx_desc = IGB_TX_DESC(tx_ring, i); 5117 5118 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5119 5120 size = skb_headlen(skb); 5121 data_len = skb->data_len; 5122 5123 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5124 5125 tx_buffer = first; 5126 5127 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5128 if (dma_mapping_error(tx_ring->dev, dma)) 5129 goto dma_error; 5130 5131 /* record length, and DMA address */ 5132 dma_unmap_len_set(tx_buffer, len, size); 5133 dma_unmap_addr_set(tx_buffer, dma, dma); 5134 5135 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5136 5137 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5138 tx_desc->read.cmd_type_len = 5139 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5140 5141 i++; 5142 tx_desc++; 5143 if (i == tx_ring->count) { 5144 tx_desc = IGB_TX_DESC(tx_ring, 0); 5145 i = 0; 5146 } 5147 tx_desc->read.olinfo_status = 0; 5148 5149 dma += IGB_MAX_DATA_PER_TXD; 5150 size -= IGB_MAX_DATA_PER_TXD; 5151 5152 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5153 } 5154 5155 if (likely(!data_len)) 5156 break; 5157 5158 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5159 5160 i++; 5161 tx_desc++; 5162 if (i == tx_ring->count) { 5163 tx_desc = IGB_TX_DESC(tx_ring, 0); 5164 i = 0; 5165 } 5166 tx_desc->read.olinfo_status = 0; 5167 5168 size = skb_frag_size(frag); 5169 data_len -= size; 5170 5171 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5172 size, DMA_TO_DEVICE); 5173 5174 tx_buffer = &tx_ring->tx_buffer_info[i]; 5175 } 5176 5177 /* write last descriptor with RS and EOP bits */ 5178 cmd_type |= size | IGB_TXD_DCMD; 5179 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5180 5181 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5182 5183 /* set the timestamp */ 5184 first->time_stamp = jiffies; 5185 5186 /* Force memory writes to complete before letting h/w know there 5187 * are new descriptors to fetch. (Only applicable for weak-ordered 5188 * memory model archs, such as IA-64). 5189 * 5190 * We also need this memory barrier to make certain all of the 5191 * status bits have been updated before next_to_watch is written. 5192 */ 5193 wmb(); 5194 5195 /* set next_to_watch value indicating a packet is present */ 5196 first->next_to_watch = tx_desc; 5197 5198 i++; 5199 if (i == tx_ring->count) 5200 i = 0; 5201 5202 tx_ring->next_to_use = i; 5203 5204 /* Make sure there is space in the ring for the next send. */ 5205 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5206 5207 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5208 writel(i, tx_ring->tail); 5209 5210 /* we need this if more than one processor can write to our tail 5211 * at a time, it synchronizes IO on IA64/Altix systems 5212 */ 5213 mmiowb(); 5214 } 5215 return; 5216 5217 dma_error: 5218 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5219 5220 /* clear dma mappings for failed tx_buffer_info map */ 5221 for (;;) { 5222 tx_buffer = &tx_ring->tx_buffer_info[i]; 5223 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 5224 if (tx_buffer == first) 5225 break; 5226 if (i == 0) 5227 i = tx_ring->count; 5228 i--; 5229 } 5230 5231 tx_ring->next_to_use = i; 5232 } 5233 5234 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5235 struct igb_ring *tx_ring) 5236 { 5237 struct igb_tx_buffer *first; 5238 int tso; 5239 u32 tx_flags = 0; 5240 unsigned short f; 5241 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5242 __be16 protocol = vlan_get_protocol(skb); 5243 u8 hdr_len = 0; 5244 5245 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5246 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5247 * + 2 desc gap to keep tail from touching head, 5248 * + 1 desc for context descriptor, 5249 * otherwise try next time 5250 */ 5251 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5252 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5253 5254 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5255 /* this is a hard error */ 5256 return NETDEV_TX_BUSY; 5257 } 5258 5259 /* record the location of the first descriptor for this packet */ 5260 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5261 first->skb = skb; 5262 first->bytecount = skb->len; 5263 first->gso_segs = 1; 5264 5265 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5266 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5267 5268 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5269 &adapter->state)) { 5270 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5271 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5272 5273 adapter->ptp_tx_skb = skb_get(skb); 5274 adapter->ptp_tx_start = jiffies; 5275 if (adapter->hw.mac.type == e1000_82576) 5276 schedule_work(&adapter->ptp_tx_work); 5277 } 5278 } 5279 5280 skb_tx_timestamp(skb); 5281 5282 if (skb_vlan_tag_present(skb)) { 5283 tx_flags |= IGB_TX_FLAGS_VLAN; 5284 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5285 } 5286 5287 /* record initial flags and protocol */ 5288 first->tx_flags = tx_flags; 5289 first->protocol = protocol; 5290 5291 tso = igb_tso(tx_ring, first, &hdr_len); 5292 if (tso < 0) 5293 goto out_drop; 5294 else if (!tso) 5295 igb_tx_csum(tx_ring, first); 5296 5297 igb_tx_map(tx_ring, first, hdr_len); 5298 5299 return NETDEV_TX_OK; 5300 5301 out_drop: 5302 igb_unmap_and_free_tx_resource(tx_ring, first); 5303 5304 return NETDEV_TX_OK; 5305 } 5306 5307 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5308 struct sk_buff *skb) 5309 { 5310 unsigned int r_idx = skb->queue_mapping; 5311 5312 if (r_idx >= adapter->num_tx_queues) 5313 r_idx = r_idx % adapter->num_tx_queues; 5314 5315 return adapter->tx_ring[r_idx]; 5316 } 5317 5318 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5319 struct net_device *netdev) 5320 { 5321 struct igb_adapter *adapter = netdev_priv(netdev); 5322 5323 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5324 * in order to meet this minimum size requirement. 5325 */ 5326 if (skb_put_padto(skb, 17)) 5327 return NETDEV_TX_OK; 5328 5329 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5330 } 5331 5332 /** 5333 * igb_tx_timeout - Respond to a Tx Hang 5334 * @netdev: network interface device structure 5335 **/ 5336 static void igb_tx_timeout(struct net_device *netdev) 5337 { 5338 struct igb_adapter *adapter = netdev_priv(netdev); 5339 struct e1000_hw *hw = &adapter->hw; 5340 5341 /* Do the reset outside of interrupt context */ 5342 adapter->tx_timeout_count++; 5343 5344 if (hw->mac.type >= e1000_82580) 5345 hw->dev_spec._82575.global_device_reset = true; 5346 5347 schedule_work(&adapter->reset_task); 5348 wr32(E1000_EICS, 5349 (adapter->eims_enable_mask & ~adapter->eims_other)); 5350 } 5351 5352 static void igb_reset_task(struct work_struct *work) 5353 { 5354 struct igb_adapter *adapter; 5355 adapter = container_of(work, struct igb_adapter, reset_task); 5356 5357 igb_dump(adapter); 5358 netdev_err(adapter->netdev, "Reset adapter\n"); 5359 igb_reinit_locked(adapter); 5360 } 5361 5362 /** 5363 * igb_get_stats64 - Get System Network Statistics 5364 * @netdev: network interface device structure 5365 * @stats: rtnl_link_stats64 pointer 5366 **/ 5367 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5368 struct rtnl_link_stats64 *stats) 5369 { 5370 struct igb_adapter *adapter = netdev_priv(netdev); 5371 5372 spin_lock(&adapter->stats64_lock); 5373 igb_update_stats(adapter, &adapter->stats64); 5374 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5375 spin_unlock(&adapter->stats64_lock); 5376 5377 return stats; 5378 } 5379 5380 /** 5381 * igb_change_mtu - Change the Maximum Transfer Unit 5382 * @netdev: network interface device structure 5383 * @new_mtu: new value for maximum frame size 5384 * 5385 * Returns 0 on success, negative on failure 5386 **/ 5387 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5388 { 5389 struct igb_adapter *adapter = netdev_priv(netdev); 5390 struct pci_dev *pdev = adapter->pdev; 5391 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5392 5393 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5394 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5395 return -EINVAL; 5396 } 5397 5398 #define MAX_STD_JUMBO_FRAME_SIZE 9238 5399 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5400 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5401 return -EINVAL; 5402 } 5403 5404 /* adjust max frame to be at least the size of a standard frame */ 5405 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5406 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5407 5408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5409 usleep_range(1000, 2000); 5410 5411 /* igb_down has a dependency on max_frame_size */ 5412 adapter->max_frame_size = max_frame; 5413 5414 if (netif_running(netdev)) 5415 igb_down(adapter); 5416 5417 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5418 netdev->mtu, new_mtu); 5419 netdev->mtu = new_mtu; 5420 5421 if (netif_running(netdev)) 5422 igb_up(adapter); 5423 else 5424 igb_reset(adapter); 5425 5426 clear_bit(__IGB_RESETTING, &adapter->state); 5427 5428 return 0; 5429 } 5430 5431 /** 5432 * igb_update_stats - Update the board statistics counters 5433 * @adapter: board private structure 5434 **/ 5435 void igb_update_stats(struct igb_adapter *adapter, 5436 struct rtnl_link_stats64 *net_stats) 5437 { 5438 struct e1000_hw *hw = &adapter->hw; 5439 struct pci_dev *pdev = adapter->pdev; 5440 u32 reg, mpc; 5441 int i; 5442 u64 bytes, packets; 5443 unsigned int start; 5444 u64 _bytes, _packets; 5445 5446 /* Prevent stats update while adapter is being reset, or if the pci 5447 * connection is down. 5448 */ 5449 if (adapter->link_speed == 0) 5450 return; 5451 if (pci_channel_offline(pdev)) 5452 return; 5453 5454 bytes = 0; 5455 packets = 0; 5456 5457 rcu_read_lock(); 5458 for (i = 0; i < adapter->num_rx_queues; i++) { 5459 struct igb_ring *ring = adapter->rx_ring[i]; 5460 u32 rqdpc = rd32(E1000_RQDPC(i)); 5461 if (hw->mac.type >= e1000_i210) 5462 wr32(E1000_RQDPC(i), 0); 5463 5464 if (rqdpc) { 5465 ring->rx_stats.drops += rqdpc; 5466 net_stats->rx_fifo_errors += rqdpc; 5467 } 5468 5469 do { 5470 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5471 _bytes = ring->rx_stats.bytes; 5472 _packets = ring->rx_stats.packets; 5473 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5474 bytes += _bytes; 5475 packets += _packets; 5476 } 5477 5478 net_stats->rx_bytes = bytes; 5479 net_stats->rx_packets = packets; 5480 5481 bytes = 0; 5482 packets = 0; 5483 for (i = 0; i < adapter->num_tx_queues; i++) { 5484 struct igb_ring *ring = adapter->tx_ring[i]; 5485 do { 5486 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5487 _bytes = ring->tx_stats.bytes; 5488 _packets = ring->tx_stats.packets; 5489 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5490 bytes += _bytes; 5491 packets += _packets; 5492 } 5493 net_stats->tx_bytes = bytes; 5494 net_stats->tx_packets = packets; 5495 rcu_read_unlock(); 5496 5497 /* read stats registers */ 5498 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5499 adapter->stats.gprc += rd32(E1000_GPRC); 5500 adapter->stats.gorc += rd32(E1000_GORCL); 5501 rd32(E1000_GORCH); /* clear GORCL */ 5502 adapter->stats.bprc += rd32(E1000_BPRC); 5503 adapter->stats.mprc += rd32(E1000_MPRC); 5504 adapter->stats.roc += rd32(E1000_ROC); 5505 5506 adapter->stats.prc64 += rd32(E1000_PRC64); 5507 adapter->stats.prc127 += rd32(E1000_PRC127); 5508 adapter->stats.prc255 += rd32(E1000_PRC255); 5509 adapter->stats.prc511 += rd32(E1000_PRC511); 5510 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5511 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5512 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5513 adapter->stats.sec += rd32(E1000_SEC); 5514 5515 mpc = rd32(E1000_MPC); 5516 adapter->stats.mpc += mpc; 5517 net_stats->rx_fifo_errors += mpc; 5518 adapter->stats.scc += rd32(E1000_SCC); 5519 adapter->stats.ecol += rd32(E1000_ECOL); 5520 adapter->stats.mcc += rd32(E1000_MCC); 5521 adapter->stats.latecol += rd32(E1000_LATECOL); 5522 adapter->stats.dc += rd32(E1000_DC); 5523 adapter->stats.rlec += rd32(E1000_RLEC); 5524 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5525 adapter->stats.xontxc += rd32(E1000_XONTXC); 5526 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5527 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5528 adapter->stats.fcruc += rd32(E1000_FCRUC); 5529 adapter->stats.gptc += rd32(E1000_GPTC); 5530 adapter->stats.gotc += rd32(E1000_GOTCL); 5531 rd32(E1000_GOTCH); /* clear GOTCL */ 5532 adapter->stats.rnbc += rd32(E1000_RNBC); 5533 adapter->stats.ruc += rd32(E1000_RUC); 5534 adapter->stats.rfc += rd32(E1000_RFC); 5535 adapter->stats.rjc += rd32(E1000_RJC); 5536 adapter->stats.tor += rd32(E1000_TORH); 5537 adapter->stats.tot += rd32(E1000_TOTH); 5538 adapter->stats.tpr += rd32(E1000_TPR); 5539 5540 adapter->stats.ptc64 += rd32(E1000_PTC64); 5541 adapter->stats.ptc127 += rd32(E1000_PTC127); 5542 adapter->stats.ptc255 += rd32(E1000_PTC255); 5543 adapter->stats.ptc511 += rd32(E1000_PTC511); 5544 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5545 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5546 5547 adapter->stats.mptc += rd32(E1000_MPTC); 5548 adapter->stats.bptc += rd32(E1000_BPTC); 5549 5550 adapter->stats.tpt += rd32(E1000_TPT); 5551 adapter->stats.colc += rd32(E1000_COLC); 5552 5553 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5554 /* read internal phy specific stats */ 5555 reg = rd32(E1000_CTRL_EXT); 5556 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5557 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5558 5559 /* this stat has invalid values on i210/i211 */ 5560 if ((hw->mac.type != e1000_i210) && 5561 (hw->mac.type != e1000_i211)) 5562 adapter->stats.tncrs += rd32(E1000_TNCRS); 5563 } 5564 5565 adapter->stats.tsctc += rd32(E1000_TSCTC); 5566 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5567 5568 adapter->stats.iac += rd32(E1000_IAC); 5569 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5570 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5571 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5572 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5573 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5574 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5575 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5576 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5577 5578 /* Fill out the OS statistics structure */ 5579 net_stats->multicast = adapter->stats.mprc; 5580 net_stats->collisions = adapter->stats.colc; 5581 5582 /* Rx Errors */ 5583 5584 /* RLEC on some newer hardware can be incorrect so build 5585 * our own version based on RUC and ROC 5586 */ 5587 net_stats->rx_errors = adapter->stats.rxerrc + 5588 adapter->stats.crcerrs + adapter->stats.algnerrc + 5589 adapter->stats.ruc + adapter->stats.roc + 5590 adapter->stats.cexterr; 5591 net_stats->rx_length_errors = adapter->stats.ruc + 5592 adapter->stats.roc; 5593 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5594 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5595 net_stats->rx_missed_errors = adapter->stats.mpc; 5596 5597 /* Tx Errors */ 5598 net_stats->tx_errors = adapter->stats.ecol + 5599 adapter->stats.latecol; 5600 net_stats->tx_aborted_errors = adapter->stats.ecol; 5601 net_stats->tx_window_errors = adapter->stats.latecol; 5602 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5603 5604 /* Tx Dropped needs to be maintained elsewhere */ 5605 5606 /* Management Stats */ 5607 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5608 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5609 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5610 5611 /* OS2BMC Stats */ 5612 reg = rd32(E1000_MANC); 5613 if (reg & E1000_MANC_EN_BMC2OS) { 5614 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5615 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5616 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5617 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5618 } 5619 } 5620 5621 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5622 { 5623 struct e1000_hw *hw = &adapter->hw; 5624 struct ptp_clock_event event; 5625 struct timespec64 ts; 5626 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5627 5628 if (tsicr & TSINTR_SYS_WRAP) { 5629 event.type = PTP_CLOCK_PPS; 5630 if (adapter->ptp_caps.pps) 5631 ptp_clock_event(adapter->ptp_clock, &event); 5632 else 5633 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5634 ack |= TSINTR_SYS_WRAP; 5635 } 5636 5637 if (tsicr & E1000_TSICR_TXTS) { 5638 /* retrieve hardware timestamp */ 5639 schedule_work(&adapter->ptp_tx_work); 5640 ack |= E1000_TSICR_TXTS; 5641 } 5642 5643 if (tsicr & TSINTR_TT0) { 5644 spin_lock(&adapter->tmreg_lock); 5645 ts = timespec64_add(adapter->perout[0].start, 5646 adapter->perout[0].period); 5647 /* u32 conversion of tv_sec is safe until y2106 */ 5648 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5649 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5650 tsauxc = rd32(E1000_TSAUXC); 5651 tsauxc |= TSAUXC_EN_TT0; 5652 wr32(E1000_TSAUXC, tsauxc); 5653 adapter->perout[0].start = ts; 5654 spin_unlock(&adapter->tmreg_lock); 5655 ack |= TSINTR_TT0; 5656 } 5657 5658 if (tsicr & TSINTR_TT1) { 5659 spin_lock(&adapter->tmreg_lock); 5660 ts = timespec64_add(adapter->perout[1].start, 5661 adapter->perout[1].period); 5662 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5663 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5664 tsauxc = rd32(E1000_TSAUXC); 5665 tsauxc |= TSAUXC_EN_TT1; 5666 wr32(E1000_TSAUXC, tsauxc); 5667 adapter->perout[1].start = ts; 5668 spin_unlock(&adapter->tmreg_lock); 5669 ack |= TSINTR_TT1; 5670 } 5671 5672 if (tsicr & TSINTR_AUTT0) { 5673 nsec = rd32(E1000_AUXSTMPL0); 5674 sec = rd32(E1000_AUXSTMPH0); 5675 event.type = PTP_CLOCK_EXTTS; 5676 event.index = 0; 5677 event.timestamp = sec * 1000000000ULL + nsec; 5678 ptp_clock_event(adapter->ptp_clock, &event); 5679 ack |= TSINTR_AUTT0; 5680 } 5681 5682 if (tsicr & TSINTR_AUTT1) { 5683 nsec = rd32(E1000_AUXSTMPL1); 5684 sec = rd32(E1000_AUXSTMPH1); 5685 event.type = PTP_CLOCK_EXTTS; 5686 event.index = 1; 5687 event.timestamp = sec * 1000000000ULL + nsec; 5688 ptp_clock_event(adapter->ptp_clock, &event); 5689 ack |= TSINTR_AUTT1; 5690 } 5691 5692 /* acknowledge the interrupts */ 5693 wr32(E1000_TSICR, ack); 5694 } 5695 5696 static irqreturn_t igb_msix_other(int irq, void *data) 5697 { 5698 struct igb_adapter *adapter = data; 5699 struct e1000_hw *hw = &adapter->hw; 5700 u32 icr = rd32(E1000_ICR); 5701 /* reading ICR causes bit 31 of EICR to be cleared */ 5702 5703 if (icr & E1000_ICR_DRSTA) 5704 schedule_work(&adapter->reset_task); 5705 5706 if (icr & E1000_ICR_DOUTSYNC) { 5707 /* HW is reporting DMA is out of sync */ 5708 adapter->stats.doosync++; 5709 /* The DMA Out of Sync is also indication of a spoof event 5710 * in IOV mode. Check the Wrong VM Behavior register to 5711 * see if it is really a spoof event. 5712 */ 5713 igb_check_wvbr(adapter); 5714 } 5715 5716 /* Check for a mailbox event */ 5717 if (icr & E1000_ICR_VMMB) 5718 igb_msg_task(adapter); 5719 5720 if (icr & E1000_ICR_LSC) { 5721 hw->mac.get_link_status = 1; 5722 /* guard against interrupt when we're going down */ 5723 if (!test_bit(__IGB_DOWN, &adapter->state)) 5724 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5725 } 5726 5727 if (icr & E1000_ICR_TS) 5728 igb_tsync_interrupt(adapter); 5729 5730 wr32(E1000_EIMS, adapter->eims_other); 5731 5732 return IRQ_HANDLED; 5733 } 5734 5735 static void igb_write_itr(struct igb_q_vector *q_vector) 5736 { 5737 struct igb_adapter *adapter = q_vector->adapter; 5738 u32 itr_val = q_vector->itr_val & 0x7FFC; 5739 5740 if (!q_vector->set_itr) 5741 return; 5742 5743 if (!itr_val) 5744 itr_val = 0x4; 5745 5746 if (adapter->hw.mac.type == e1000_82575) 5747 itr_val |= itr_val << 16; 5748 else 5749 itr_val |= E1000_EITR_CNT_IGNR; 5750 5751 writel(itr_val, q_vector->itr_register); 5752 q_vector->set_itr = 0; 5753 } 5754 5755 static irqreturn_t igb_msix_ring(int irq, void *data) 5756 { 5757 struct igb_q_vector *q_vector = data; 5758 5759 /* Write the ITR value calculated from the previous interrupt. */ 5760 igb_write_itr(q_vector); 5761 5762 napi_schedule(&q_vector->napi); 5763 5764 return IRQ_HANDLED; 5765 } 5766 5767 #ifdef CONFIG_IGB_DCA 5768 static void igb_update_tx_dca(struct igb_adapter *adapter, 5769 struct igb_ring *tx_ring, 5770 int cpu) 5771 { 5772 struct e1000_hw *hw = &adapter->hw; 5773 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5774 5775 if (hw->mac.type != e1000_82575) 5776 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5777 5778 /* We can enable relaxed ordering for reads, but not writes when 5779 * DCA is enabled. This is due to a known issue in some chipsets 5780 * which will cause the DCA tag to be cleared. 5781 */ 5782 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5783 E1000_DCA_TXCTRL_DATA_RRO_EN | 5784 E1000_DCA_TXCTRL_DESC_DCA_EN; 5785 5786 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5787 } 5788 5789 static void igb_update_rx_dca(struct igb_adapter *adapter, 5790 struct igb_ring *rx_ring, 5791 int cpu) 5792 { 5793 struct e1000_hw *hw = &adapter->hw; 5794 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5795 5796 if (hw->mac.type != e1000_82575) 5797 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5798 5799 /* We can enable relaxed ordering for reads, but not writes when 5800 * DCA is enabled. This is due to a known issue in some chipsets 5801 * which will cause the DCA tag to be cleared. 5802 */ 5803 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5804 E1000_DCA_RXCTRL_DESC_DCA_EN; 5805 5806 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5807 } 5808 5809 static void igb_update_dca(struct igb_q_vector *q_vector) 5810 { 5811 struct igb_adapter *adapter = q_vector->adapter; 5812 int cpu = get_cpu(); 5813 5814 if (q_vector->cpu == cpu) 5815 goto out_no_update; 5816 5817 if (q_vector->tx.ring) 5818 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5819 5820 if (q_vector->rx.ring) 5821 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5822 5823 q_vector->cpu = cpu; 5824 out_no_update: 5825 put_cpu(); 5826 } 5827 5828 static void igb_setup_dca(struct igb_adapter *adapter) 5829 { 5830 struct e1000_hw *hw = &adapter->hw; 5831 int i; 5832 5833 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5834 return; 5835 5836 /* Always use CB2 mode, difference is masked in the CB driver. */ 5837 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5838 5839 for (i = 0; i < adapter->num_q_vectors; i++) { 5840 adapter->q_vector[i]->cpu = -1; 5841 igb_update_dca(adapter->q_vector[i]); 5842 } 5843 } 5844 5845 static int __igb_notify_dca(struct device *dev, void *data) 5846 { 5847 struct net_device *netdev = dev_get_drvdata(dev); 5848 struct igb_adapter *adapter = netdev_priv(netdev); 5849 struct pci_dev *pdev = adapter->pdev; 5850 struct e1000_hw *hw = &adapter->hw; 5851 unsigned long event = *(unsigned long *)data; 5852 5853 switch (event) { 5854 case DCA_PROVIDER_ADD: 5855 /* if already enabled, don't do it again */ 5856 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5857 break; 5858 if (dca_add_requester(dev) == 0) { 5859 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5860 dev_info(&pdev->dev, "DCA enabled\n"); 5861 igb_setup_dca(adapter); 5862 break; 5863 } 5864 /* Fall Through since DCA is disabled. */ 5865 case DCA_PROVIDER_REMOVE: 5866 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5867 /* without this a class_device is left 5868 * hanging around in the sysfs model 5869 */ 5870 dca_remove_requester(dev); 5871 dev_info(&pdev->dev, "DCA disabled\n"); 5872 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5873 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5874 } 5875 break; 5876 } 5877 5878 return 0; 5879 } 5880 5881 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5882 void *p) 5883 { 5884 int ret_val; 5885 5886 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5887 __igb_notify_dca); 5888 5889 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5890 } 5891 #endif /* CONFIG_IGB_DCA */ 5892 5893 #ifdef CONFIG_PCI_IOV 5894 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5895 { 5896 unsigned char mac_addr[ETH_ALEN]; 5897 5898 eth_zero_addr(mac_addr); 5899 igb_set_vf_mac(adapter, vf, mac_addr); 5900 5901 /* By default spoof check is enabled for all VFs */ 5902 adapter->vf_data[vf].spoofchk_enabled = true; 5903 5904 return 0; 5905 } 5906 5907 #endif 5908 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5909 { 5910 struct e1000_hw *hw = &adapter->hw; 5911 u32 ping; 5912 int i; 5913 5914 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5915 ping = E1000_PF_CONTROL_MSG; 5916 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5917 ping |= E1000_VT_MSGTYPE_CTS; 5918 igb_write_mbx(hw, &ping, 1, i); 5919 } 5920 } 5921 5922 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5923 { 5924 struct e1000_hw *hw = &adapter->hw; 5925 u32 vmolr = rd32(E1000_VMOLR(vf)); 5926 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5927 5928 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5929 IGB_VF_FLAG_MULTI_PROMISC); 5930 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5931 5932 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5933 vmolr |= E1000_VMOLR_MPME; 5934 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5935 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5936 } else { 5937 /* if we have hashes and we are clearing a multicast promisc 5938 * flag we need to write the hashes to the MTA as this step 5939 * was previously skipped 5940 */ 5941 if (vf_data->num_vf_mc_hashes > 30) { 5942 vmolr |= E1000_VMOLR_MPME; 5943 } else if (vf_data->num_vf_mc_hashes) { 5944 int j; 5945 5946 vmolr |= E1000_VMOLR_ROMPE; 5947 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5948 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5949 } 5950 } 5951 5952 wr32(E1000_VMOLR(vf), vmolr); 5953 5954 /* there are flags left unprocessed, likely not supported */ 5955 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5956 return -EINVAL; 5957 5958 return 0; 5959 } 5960 5961 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5962 u32 *msgbuf, u32 vf) 5963 { 5964 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5965 u16 *hash_list = (u16 *)&msgbuf[1]; 5966 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5967 int i; 5968 5969 /* salt away the number of multicast addresses assigned 5970 * to this VF for later use to restore when the PF multi cast 5971 * list changes 5972 */ 5973 vf_data->num_vf_mc_hashes = n; 5974 5975 /* only up to 30 hash values supported */ 5976 if (n > 30) 5977 n = 30; 5978 5979 /* store the hashes for later use */ 5980 for (i = 0; i < n; i++) 5981 vf_data->vf_mc_hashes[i] = hash_list[i]; 5982 5983 /* Flush and reset the mta with the new values */ 5984 igb_set_rx_mode(adapter->netdev); 5985 5986 return 0; 5987 } 5988 5989 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5990 { 5991 struct e1000_hw *hw = &adapter->hw; 5992 struct vf_data_storage *vf_data; 5993 int i, j; 5994 5995 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5996 u32 vmolr = rd32(E1000_VMOLR(i)); 5997 5998 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5999 6000 vf_data = &adapter->vf_data[i]; 6001 6002 if ((vf_data->num_vf_mc_hashes > 30) || 6003 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6004 vmolr |= E1000_VMOLR_MPME; 6005 } else if (vf_data->num_vf_mc_hashes) { 6006 vmolr |= E1000_VMOLR_ROMPE; 6007 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6008 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6009 } 6010 wr32(E1000_VMOLR(i), vmolr); 6011 } 6012 } 6013 6014 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6015 { 6016 struct e1000_hw *hw = &adapter->hw; 6017 u32 pool_mask, vlvf_mask, i; 6018 6019 /* create mask for VF and other pools */ 6020 pool_mask = E1000_VLVF_POOLSEL_MASK; 6021 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6022 6023 /* drop PF from pool bits */ 6024 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6025 adapter->vfs_allocated_count); 6026 6027 /* Find the vlan filter for this id */ 6028 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6029 u32 vlvf = rd32(E1000_VLVF(i)); 6030 u32 vfta_mask, vid, vfta; 6031 6032 /* remove the vf from the pool */ 6033 if (!(vlvf & vlvf_mask)) 6034 continue; 6035 6036 /* clear out bit from VLVF */ 6037 vlvf ^= vlvf_mask; 6038 6039 /* if other pools are present, just remove ourselves */ 6040 if (vlvf & pool_mask) 6041 goto update_vlvfb; 6042 6043 /* if PF is present, leave VFTA */ 6044 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6045 goto update_vlvf; 6046 6047 vid = vlvf & E1000_VLVF_VLANID_MASK; 6048 vfta_mask = BIT(vid % 32); 6049 6050 /* clear bit from VFTA */ 6051 vfta = adapter->shadow_vfta[vid / 32]; 6052 if (vfta & vfta_mask) 6053 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6054 update_vlvf: 6055 /* clear pool selection enable */ 6056 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6057 vlvf &= E1000_VLVF_POOLSEL_MASK; 6058 else 6059 vlvf = 0; 6060 update_vlvfb: 6061 /* clear pool bits */ 6062 wr32(E1000_VLVF(i), vlvf); 6063 } 6064 } 6065 6066 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6067 { 6068 u32 vlvf; 6069 int idx; 6070 6071 /* short cut the special case */ 6072 if (vlan == 0) 6073 return 0; 6074 6075 /* Search for the VLAN id in the VLVF entries */ 6076 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6077 vlvf = rd32(E1000_VLVF(idx)); 6078 if ((vlvf & VLAN_VID_MASK) == vlan) 6079 break; 6080 } 6081 6082 return idx; 6083 } 6084 6085 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6086 { 6087 struct e1000_hw *hw = &adapter->hw; 6088 u32 bits, pf_id; 6089 int idx; 6090 6091 idx = igb_find_vlvf_entry(hw, vid); 6092 if (!idx) 6093 return; 6094 6095 /* See if any other pools are set for this VLAN filter 6096 * entry other than the PF. 6097 */ 6098 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6099 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6100 bits &= rd32(E1000_VLVF(idx)); 6101 6102 /* Disable the filter so this falls into the default pool. */ 6103 if (!bits) { 6104 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6105 wr32(E1000_VLVF(idx), BIT(pf_id)); 6106 else 6107 wr32(E1000_VLVF(idx), 0); 6108 } 6109 } 6110 6111 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6112 bool add, u32 vf) 6113 { 6114 int pf_id = adapter->vfs_allocated_count; 6115 struct e1000_hw *hw = &adapter->hw; 6116 int err; 6117 6118 /* If VLAN overlaps with one the PF is currently monitoring make 6119 * sure that we are able to allocate a VLVF entry. This may be 6120 * redundant but it guarantees PF will maintain visibility to 6121 * the VLAN. 6122 */ 6123 if (add && test_bit(vid, adapter->active_vlans)) { 6124 err = igb_vfta_set(hw, vid, pf_id, true, false); 6125 if (err) 6126 return err; 6127 } 6128 6129 err = igb_vfta_set(hw, vid, vf, add, false); 6130 6131 if (add && !err) 6132 return err; 6133 6134 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6135 * we may need to drop the PF pool bit in order to allow us to free 6136 * up the VLVF resources. 6137 */ 6138 if (test_bit(vid, adapter->active_vlans) || 6139 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6140 igb_update_pf_vlvf(adapter, vid); 6141 6142 return err; 6143 } 6144 6145 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6146 { 6147 struct e1000_hw *hw = &adapter->hw; 6148 6149 if (vid) 6150 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6151 else 6152 wr32(E1000_VMVIR(vf), 0); 6153 } 6154 6155 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6156 u16 vlan, u8 qos) 6157 { 6158 int err; 6159 6160 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6161 if (err) 6162 return err; 6163 6164 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6165 igb_set_vmolr(adapter, vf, !vlan); 6166 6167 /* revoke access to previous VLAN */ 6168 if (vlan != adapter->vf_data[vf].pf_vlan) 6169 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6170 false, vf); 6171 6172 adapter->vf_data[vf].pf_vlan = vlan; 6173 adapter->vf_data[vf].pf_qos = qos; 6174 igb_set_vf_vlan_strip(adapter, vf, true); 6175 dev_info(&adapter->pdev->dev, 6176 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6177 if (test_bit(__IGB_DOWN, &adapter->state)) { 6178 dev_warn(&adapter->pdev->dev, 6179 "The VF VLAN has been set, but the PF device is not up.\n"); 6180 dev_warn(&adapter->pdev->dev, 6181 "Bring the PF device up before attempting to use the VF device.\n"); 6182 } 6183 6184 return err; 6185 } 6186 6187 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6188 { 6189 /* Restore tagless access via VLAN 0 */ 6190 igb_set_vf_vlan(adapter, 0, true, vf); 6191 6192 igb_set_vmvir(adapter, 0, vf); 6193 igb_set_vmolr(adapter, vf, true); 6194 6195 /* Remove any PF assigned VLAN */ 6196 if (adapter->vf_data[vf].pf_vlan) 6197 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6198 false, vf); 6199 6200 adapter->vf_data[vf].pf_vlan = 0; 6201 adapter->vf_data[vf].pf_qos = 0; 6202 igb_set_vf_vlan_strip(adapter, vf, false); 6203 6204 return 0; 6205 } 6206 6207 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 6208 int vf, u16 vlan, u8 qos) 6209 { 6210 struct igb_adapter *adapter = netdev_priv(netdev); 6211 6212 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6213 return -EINVAL; 6214 6215 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6216 igb_disable_port_vlan(adapter, vf); 6217 } 6218 6219 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6220 { 6221 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6222 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6223 int ret; 6224 6225 if (adapter->vf_data[vf].pf_vlan) 6226 return -1; 6227 6228 /* VLAN 0 is a special case, don't allow it to be removed */ 6229 if (!vid && !add) 6230 return 0; 6231 6232 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6233 if (!ret) 6234 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6235 return ret; 6236 } 6237 6238 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6239 { 6240 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6241 6242 /* clear flags - except flag that indicates PF has set the MAC */ 6243 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6244 vf_data->last_nack = jiffies; 6245 6246 /* reset vlans for device */ 6247 igb_clear_vf_vfta(adapter, vf); 6248 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6249 igb_set_vmvir(adapter, vf_data->pf_vlan | 6250 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6251 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6252 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6253 6254 /* reset multicast table array for vf */ 6255 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6256 6257 /* Flush and reset the mta with the new values */ 6258 igb_set_rx_mode(adapter->netdev); 6259 } 6260 6261 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6262 { 6263 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6264 6265 /* clear mac address as we were hotplug removed/added */ 6266 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6267 eth_zero_addr(vf_mac); 6268 6269 /* process remaining reset events */ 6270 igb_vf_reset(adapter, vf); 6271 } 6272 6273 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6274 { 6275 struct e1000_hw *hw = &adapter->hw; 6276 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6277 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6278 u32 reg, msgbuf[3]; 6279 u8 *addr = (u8 *)(&msgbuf[1]); 6280 6281 /* process all the same items cleared in a function level reset */ 6282 igb_vf_reset(adapter, vf); 6283 6284 /* set vf mac address */ 6285 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6286 6287 /* enable transmit and receive for vf */ 6288 reg = rd32(E1000_VFTE); 6289 wr32(E1000_VFTE, reg | BIT(vf)); 6290 reg = rd32(E1000_VFRE); 6291 wr32(E1000_VFRE, reg | BIT(vf)); 6292 6293 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6294 6295 /* reply to reset with ack and vf mac address */ 6296 if (!is_zero_ether_addr(vf_mac)) { 6297 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6298 memcpy(addr, vf_mac, ETH_ALEN); 6299 } else { 6300 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6301 } 6302 igb_write_mbx(hw, msgbuf, 3, vf); 6303 } 6304 6305 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6306 { 6307 /* The VF MAC Address is stored in a packed array of bytes 6308 * starting at the second 32 bit word of the msg array 6309 */ 6310 unsigned char *addr = (char *)&msg[1]; 6311 int err = -1; 6312 6313 if (is_valid_ether_addr(addr)) 6314 err = igb_set_vf_mac(adapter, vf, addr); 6315 6316 return err; 6317 } 6318 6319 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6320 { 6321 struct e1000_hw *hw = &adapter->hw; 6322 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6323 u32 msg = E1000_VT_MSGTYPE_NACK; 6324 6325 /* if device isn't clear to send it shouldn't be reading either */ 6326 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6327 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6328 igb_write_mbx(hw, &msg, 1, vf); 6329 vf_data->last_nack = jiffies; 6330 } 6331 } 6332 6333 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6334 { 6335 struct pci_dev *pdev = adapter->pdev; 6336 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6337 struct e1000_hw *hw = &adapter->hw; 6338 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6339 s32 retval; 6340 6341 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6342 6343 if (retval) { 6344 /* if receive failed revoke VF CTS stats and restart init */ 6345 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6346 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6347 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6348 return; 6349 goto out; 6350 } 6351 6352 /* this is a message we already processed, do nothing */ 6353 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6354 return; 6355 6356 /* until the vf completes a reset it should not be 6357 * allowed to start any configuration. 6358 */ 6359 if (msgbuf[0] == E1000_VF_RESET) { 6360 igb_vf_reset_msg(adapter, vf); 6361 return; 6362 } 6363 6364 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6365 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6366 return; 6367 retval = -1; 6368 goto out; 6369 } 6370 6371 switch ((msgbuf[0] & 0xFFFF)) { 6372 case E1000_VF_SET_MAC_ADDR: 6373 retval = -EINVAL; 6374 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6375 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6376 else 6377 dev_warn(&pdev->dev, 6378 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6379 vf); 6380 break; 6381 case E1000_VF_SET_PROMISC: 6382 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6383 break; 6384 case E1000_VF_SET_MULTICAST: 6385 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6386 break; 6387 case E1000_VF_SET_LPE: 6388 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6389 break; 6390 case E1000_VF_SET_VLAN: 6391 retval = -1; 6392 if (vf_data->pf_vlan) 6393 dev_warn(&pdev->dev, 6394 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6395 vf); 6396 else 6397 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6398 break; 6399 default: 6400 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6401 retval = -1; 6402 break; 6403 } 6404 6405 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6406 out: 6407 /* notify the VF of the results of what it sent us */ 6408 if (retval) 6409 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6410 else 6411 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6412 6413 igb_write_mbx(hw, msgbuf, 1, vf); 6414 } 6415 6416 static void igb_msg_task(struct igb_adapter *adapter) 6417 { 6418 struct e1000_hw *hw = &adapter->hw; 6419 u32 vf; 6420 6421 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6422 /* process any reset requests */ 6423 if (!igb_check_for_rst(hw, vf)) 6424 igb_vf_reset_event(adapter, vf); 6425 6426 /* process any messages pending */ 6427 if (!igb_check_for_msg(hw, vf)) 6428 igb_rcv_msg_from_vf(adapter, vf); 6429 6430 /* process any acks */ 6431 if (!igb_check_for_ack(hw, vf)) 6432 igb_rcv_ack_from_vf(adapter, vf); 6433 } 6434 } 6435 6436 /** 6437 * igb_set_uta - Set unicast filter table address 6438 * @adapter: board private structure 6439 * @set: boolean indicating if we are setting or clearing bits 6440 * 6441 * The unicast table address is a register array of 32-bit registers. 6442 * The table is meant to be used in a way similar to how the MTA is used 6443 * however due to certain limitations in the hardware it is necessary to 6444 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6445 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6446 **/ 6447 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6448 { 6449 struct e1000_hw *hw = &adapter->hw; 6450 u32 uta = set ? ~0 : 0; 6451 int i; 6452 6453 /* we only need to do this if VMDq is enabled */ 6454 if (!adapter->vfs_allocated_count) 6455 return; 6456 6457 for (i = hw->mac.uta_reg_count; i--;) 6458 array_wr32(E1000_UTA, i, uta); 6459 } 6460 6461 /** 6462 * igb_intr_msi - Interrupt Handler 6463 * @irq: interrupt number 6464 * @data: pointer to a network interface device structure 6465 **/ 6466 static irqreturn_t igb_intr_msi(int irq, void *data) 6467 { 6468 struct igb_adapter *adapter = data; 6469 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6470 struct e1000_hw *hw = &adapter->hw; 6471 /* read ICR disables interrupts using IAM */ 6472 u32 icr = rd32(E1000_ICR); 6473 6474 igb_write_itr(q_vector); 6475 6476 if (icr & E1000_ICR_DRSTA) 6477 schedule_work(&adapter->reset_task); 6478 6479 if (icr & E1000_ICR_DOUTSYNC) { 6480 /* HW is reporting DMA is out of sync */ 6481 adapter->stats.doosync++; 6482 } 6483 6484 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6485 hw->mac.get_link_status = 1; 6486 if (!test_bit(__IGB_DOWN, &adapter->state)) 6487 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6488 } 6489 6490 if (icr & E1000_ICR_TS) 6491 igb_tsync_interrupt(adapter); 6492 6493 napi_schedule(&q_vector->napi); 6494 6495 return IRQ_HANDLED; 6496 } 6497 6498 /** 6499 * igb_intr - Legacy Interrupt Handler 6500 * @irq: interrupt number 6501 * @data: pointer to a network interface device structure 6502 **/ 6503 static irqreturn_t igb_intr(int irq, void *data) 6504 { 6505 struct igb_adapter *adapter = data; 6506 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6507 struct e1000_hw *hw = &adapter->hw; 6508 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6509 * need for the IMC write 6510 */ 6511 u32 icr = rd32(E1000_ICR); 6512 6513 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6514 * not set, then the adapter didn't send an interrupt 6515 */ 6516 if (!(icr & E1000_ICR_INT_ASSERTED)) 6517 return IRQ_NONE; 6518 6519 igb_write_itr(q_vector); 6520 6521 if (icr & E1000_ICR_DRSTA) 6522 schedule_work(&adapter->reset_task); 6523 6524 if (icr & E1000_ICR_DOUTSYNC) { 6525 /* HW is reporting DMA is out of sync */ 6526 adapter->stats.doosync++; 6527 } 6528 6529 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6530 hw->mac.get_link_status = 1; 6531 /* guard against interrupt when we're going down */ 6532 if (!test_bit(__IGB_DOWN, &adapter->state)) 6533 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6534 } 6535 6536 if (icr & E1000_ICR_TS) 6537 igb_tsync_interrupt(adapter); 6538 6539 napi_schedule(&q_vector->napi); 6540 6541 return IRQ_HANDLED; 6542 } 6543 6544 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6545 { 6546 struct igb_adapter *adapter = q_vector->adapter; 6547 struct e1000_hw *hw = &adapter->hw; 6548 6549 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6550 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6551 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6552 igb_set_itr(q_vector); 6553 else 6554 igb_update_ring_itr(q_vector); 6555 } 6556 6557 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6558 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6559 wr32(E1000_EIMS, q_vector->eims_value); 6560 else 6561 igb_irq_enable(adapter); 6562 } 6563 } 6564 6565 /** 6566 * igb_poll - NAPI Rx polling callback 6567 * @napi: napi polling structure 6568 * @budget: count of how many packets we should handle 6569 **/ 6570 static int igb_poll(struct napi_struct *napi, int budget) 6571 { 6572 struct igb_q_vector *q_vector = container_of(napi, 6573 struct igb_q_vector, 6574 napi); 6575 bool clean_complete = true; 6576 int work_done = 0; 6577 6578 #ifdef CONFIG_IGB_DCA 6579 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6580 igb_update_dca(q_vector); 6581 #endif 6582 if (q_vector->tx.ring) 6583 clean_complete = igb_clean_tx_irq(q_vector, budget); 6584 6585 if (q_vector->rx.ring) { 6586 int cleaned = igb_clean_rx_irq(q_vector, budget); 6587 6588 work_done += cleaned; 6589 if (cleaned >= budget) 6590 clean_complete = false; 6591 } 6592 6593 /* If all work not completed, return budget and keep polling */ 6594 if (!clean_complete) 6595 return budget; 6596 6597 /* If not enough Rx work done, exit the polling mode */ 6598 napi_complete_done(napi, work_done); 6599 igb_ring_irq_enable(q_vector); 6600 6601 return 0; 6602 } 6603 6604 /** 6605 * igb_clean_tx_irq - Reclaim resources after transmit completes 6606 * @q_vector: pointer to q_vector containing needed info 6607 * @napi_budget: Used to determine if we are in netpoll 6608 * 6609 * returns true if ring is completely cleaned 6610 **/ 6611 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6612 { 6613 struct igb_adapter *adapter = q_vector->adapter; 6614 struct igb_ring *tx_ring = q_vector->tx.ring; 6615 struct igb_tx_buffer *tx_buffer; 6616 union e1000_adv_tx_desc *tx_desc; 6617 unsigned int total_bytes = 0, total_packets = 0; 6618 unsigned int budget = q_vector->tx.work_limit; 6619 unsigned int i = tx_ring->next_to_clean; 6620 6621 if (test_bit(__IGB_DOWN, &adapter->state)) 6622 return true; 6623 6624 tx_buffer = &tx_ring->tx_buffer_info[i]; 6625 tx_desc = IGB_TX_DESC(tx_ring, i); 6626 i -= tx_ring->count; 6627 6628 do { 6629 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6630 6631 /* if next_to_watch is not set then there is no work pending */ 6632 if (!eop_desc) 6633 break; 6634 6635 /* prevent any other reads prior to eop_desc */ 6636 read_barrier_depends(); 6637 6638 /* if DD is not set pending work has not been completed */ 6639 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6640 break; 6641 6642 /* clear next_to_watch to prevent false hangs */ 6643 tx_buffer->next_to_watch = NULL; 6644 6645 /* update the statistics for this packet */ 6646 total_bytes += tx_buffer->bytecount; 6647 total_packets += tx_buffer->gso_segs; 6648 6649 /* free the skb */ 6650 napi_consume_skb(tx_buffer->skb, napi_budget); 6651 6652 /* unmap skb header data */ 6653 dma_unmap_single(tx_ring->dev, 6654 dma_unmap_addr(tx_buffer, dma), 6655 dma_unmap_len(tx_buffer, len), 6656 DMA_TO_DEVICE); 6657 6658 /* clear tx_buffer data */ 6659 tx_buffer->skb = NULL; 6660 dma_unmap_len_set(tx_buffer, len, 0); 6661 6662 /* clear last DMA location and unmap remaining buffers */ 6663 while (tx_desc != eop_desc) { 6664 tx_buffer++; 6665 tx_desc++; 6666 i++; 6667 if (unlikely(!i)) { 6668 i -= tx_ring->count; 6669 tx_buffer = tx_ring->tx_buffer_info; 6670 tx_desc = IGB_TX_DESC(tx_ring, 0); 6671 } 6672 6673 /* unmap any remaining paged data */ 6674 if (dma_unmap_len(tx_buffer, len)) { 6675 dma_unmap_page(tx_ring->dev, 6676 dma_unmap_addr(tx_buffer, dma), 6677 dma_unmap_len(tx_buffer, len), 6678 DMA_TO_DEVICE); 6679 dma_unmap_len_set(tx_buffer, len, 0); 6680 } 6681 } 6682 6683 /* move us one more past the eop_desc for start of next pkt */ 6684 tx_buffer++; 6685 tx_desc++; 6686 i++; 6687 if (unlikely(!i)) { 6688 i -= tx_ring->count; 6689 tx_buffer = tx_ring->tx_buffer_info; 6690 tx_desc = IGB_TX_DESC(tx_ring, 0); 6691 } 6692 6693 /* issue prefetch for next Tx descriptor */ 6694 prefetch(tx_desc); 6695 6696 /* update budget accounting */ 6697 budget--; 6698 } while (likely(budget)); 6699 6700 netdev_tx_completed_queue(txring_txq(tx_ring), 6701 total_packets, total_bytes); 6702 i += tx_ring->count; 6703 tx_ring->next_to_clean = i; 6704 u64_stats_update_begin(&tx_ring->tx_syncp); 6705 tx_ring->tx_stats.bytes += total_bytes; 6706 tx_ring->tx_stats.packets += total_packets; 6707 u64_stats_update_end(&tx_ring->tx_syncp); 6708 q_vector->tx.total_bytes += total_bytes; 6709 q_vector->tx.total_packets += total_packets; 6710 6711 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6712 struct e1000_hw *hw = &adapter->hw; 6713 6714 /* Detect a transmit hang in hardware, this serializes the 6715 * check with the clearing of time_stamp and movement of i 6716 */ 6717 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6718 if (tx_buffer->next_to_watch && 6719 time_after(jiffies, tx_buffer->time_stamp + 6720 (adapter->tx_timeout_factor * HZ)) && 6721 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6722 6723 /* detected Tx unit hang */ 6724 dev_err(tx_ring->dev, 6725 "Detected Tx Unit Hang\n" 6726 " Tx Queue <%d>\n" 6727 " TDH <%x>\n" 6728 " TDT <%x>\n" 6729 " next_to_use <%x>\n" 6730 " next_to_clean <%x>\n" 6731 "buffer_info[next_to_clean]\n" 6732 " time_stamp <%lx>\n" 6733 " next_to_watch <%p>\n" 6734 " jiffies <%lx>\n" 6735 " desc.status <%x>\n", 6736 tx_ring->queue_index, 6737 rd32(E1000_TDH(tx_ring->reg_idx)), 6738 readl(tx_ring->tail), 6739 tx_ring->next_to_use, 6740 tx_ring->next_to_clean, 6741 tx_buffer->time_stamp, 6742 tx_buffer->next_to_watch, 6743 jiffies, 6744 tx_buffer->next_to_watch->wb.status); 6745 netif_stop_subqueue(tx_ring->netdev, 6746 tx_ring->queue_index); 6747 6748 /* we are about to reset, no point in enabling stuff */ 6749 return true; 6750 } 6751 } 6752 6753 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6754 if (unlikely(total_packets && 6755 netif_carrier_ok(tx_ring->netdev) && 6756 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6757 /* Make sure that anybody stopping the queue after this 6758 * sees the new next_to_clean. 6759 */ 6760 smp_mb(); 6761 if (__netif_subqueue_stopped(tx_ring->netdev, 6762 tx_ring->queue_index) && 6763 !(test_bit(__IGB_DOWN, &adapter->state))) { 6764 netif_wake_subqueue(tx_ring->netdev, 6765 tx_ring->queue_index); 6766 6767 u64_stats_update_begin(&tx_ring->tx_syncp); 6768 tx_ring->tx_stats.restart_queue++; 6769 u64_stats_update_end(&tx_ring->tx_syncp); 6770 } 6771 } 6772 6773 return !!budget; 6774 } 6775 6776 /** 6777 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6778 * @rx_ring: rx descriptor ring to store buffers on 6779 * @old_buff: donor buffer to have page reused 6780 * 6781 * Synchronizes page for reuse by the adapter 6782 **/ 6783 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6784 struct igb_rx_buffer *old_buff) 6785 { 6786 struct igb_rx_buffer *new_buff; 6787 u16 nta = rx_ring->next_to_alloc; 6788 6789 new_buff = &rx_ring->rx_buffer_info[nta]; 6790 6791 /* update, and store next to alloc */ 6792 nta++; 6793 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6794 6795 /* transfer page from old buffer to new buffer */ 6796 *new_buff = *old_buff; 6797 6798 /* sync the buffer for use by the device */ 6799 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6800 old_buff->page_offset, 6801 IGB_RX_BUFSZ, 6802 DMA_FROM_DEVICE); 6803 } 6804 6805 static inline bool igb_page_is_reserved(struct page *page) 6806 { 6807 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 6808 } 6809 6810 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6811 struct page *page, 6812 unsigned int truesize) 6813 { 6814 /* avoid re-using remote pages */ 6815 if (unlikely(igb_page_is_reserved(page))) 6816 return false; 6817 6818 #if (PAGE_SIZE < 8192) 6819 /* if we are only owner of page we can reuse it */ 6820 if (unlikely(page_count(page) != 1)) 6821 return false; 6822 6823 /* flip page offset to other buffer */ 6824 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6825 #else 6826 /* move offset up to the next cache line */ 6827 rx_buffer->page_offset += truesize; 6828 6829 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6830 return false; 6831 #endif 6832 6833 /* Even if we own the page, we are not allowed to use atomic_set() 6834 * This would break get_page_unless_zero() users. 6835 */ 6836 page_ref_inc(page); 6837 6838 return true; 6839 } 6840 6841 /** 6842 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6843 * @rx_ring: rx descriptor ring to transact packets on 6844 * @rx_buffer: buffer containing page to add 6845 * @rx_desc: descriptor containing length of buffer written by hardware 6846 * @skb: sk_buff to place the data into 6847 * 6848 * This function will add the data contained in rx_buffer->page to the skb. 6849 * This is done either through a direct copy if the data in the buffer is 6850 * less than the skb header size, otherwise it will just attach the page as 6851 * a frag to the skb. 6852 * 6853 * The function will then update the page offset if necessary and return 6854 * true if the buffer can be reused by the adapter. 6855 **/ 6856 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6857 struct igb_rx_buffer *rx_buffer, 6858 union e1000_adv_rx_desc *rx_desc, 6859 struct sk_buff *skb) 6860 { 6861 struct page *page = rx_buffer->page; 6862 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6863 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6864 #if (PAGE_SIZE < 8192) 6865 unsigned int truesize = IGB_RX_BUFSZ; 6866 #else 6867 unsigned int truesize = SKB_DATA_ALIGN(size); 6868 #endif 6869 unsigned int pull_len; 6870 6871 if (unlikely(skb_is_nonlinear(skb))) 6872 goto add_tail_frag; 6873 6874 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 6875 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6876 va += IGB_TS_HDR_LEN; 6877 size -= IGB_TS_HDR_LEN; 6878 } 6879 6880 if (likely(size <= IGB_RX_HDR_LEN)) { 6881 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6882 6883 /* page is not reserved, we can reuse buffer as-is */ 6884 if (likely(!igb_page_is_reserved(page))) 6885 return true; 6886 6887 /* this page cannot be reused so discard it */ 6888 __free_page(page); 6889 return false; 6890 } 6891 6892 /* we need the header to contain the greater of either ETH_HLEN or 6893 * 60 bytes if the skb->len is less than 60 for skb_pad. 6894 */ 6895 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6896 6897 /* align pull length to size of long to optimize memcpy performance */ 6898 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 6899 6900 /* update all of the pointers */ 6901 va += pull_len; 6902 size -= pull_len; 6903 6904 add_tail_frag: 6905 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6906 (unsigned long)va & ~PAGE_MASK, size, truesize); 6907 6908 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6909 } 6910 6911 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6912 union e1000_adv_rx_desc *rx_desc, 6913 struct sk_buff *skb) 6914 { 6915 struct igb_rx_buffer *rx_buffer; 6916 struct page *page; 6917 6918 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6919 page = rx_buffer->page; 6920 prefetchw(page); 6921 6922 if (likely(!skb)) { 6923 void *page_addr = page_address(page) + 6924 rx_buffer->page_offset; 6925 6926 /* prefetch first cache line of first page */ 6927 prefetch(page_addr); 6928 #if L1_CACHE_BYTES < 128 6929 prefetch(page_addr + L1_CACHE_BYTES); 6930 #endif 6931 6932 /* allocate a skb to store the frags */ 6933 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6934 if (unlikely(!skb)) { 6935 rx_ring->rx_stats.alloc_failed++; 6936 return NULL; 6937 } 6938 6939 /* we will be copying header into skb->data in 6940 * pskb_may_pull so it is in our interest to prefetch 6941 * it now to avoid a possible cache miss 6942 */ 6943 prefetchw(skb->data); 6944 } 6945 6946 /* we are reusing so sync this buffer for CPU use */ 6947 dma_sync_single_range_for_cpu(rx_ring->dev, 6948 rx_buffer->dma, 6949 rx_buffer->page_offset, 6950 IGB_RX_BUFSZ, 6951 DMA_FROM_DEVICE); 6952 6953 /* pull page into skb */ 6954 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6955 /* hand second half of page back to the ring */ 6956 igb_reuse_rx_page(rx_ring, rx_buffer); 6957 } else { 6958 /* we are not reusing the buffer so unmap it */ 6959 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6960 PAGE_SIZE, DMA_FROM_DEVICE); 6961 } 6962 6963 /* clear contents of rx_buffer */ 6964 rx_buffer->page = NULL; 6965 6966 return skb; 6967 } 6968 6969 static inline void igb_rx_checksum(struct igb_ring *ring, 6970 union e1000_adv_rx_desc *rx_desc, 6971 struct sk_buff *skb) 6972 { 6973 skb_checksum_none_assert(skb); 6974 6975 /* Ignore Checksum bit is set */ 6976 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6977 return; 6978 6979 /* Rx checksum disabled via ethtool */ 6980 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6981 return; 6982 6983 /* TCP/UDP checksum error bit is set */ 6984 if (igb_test_staterr(rx_desc, 6985 E1000_RXDEXT_STATERR_TCPE | 6986 E1000_RXDEXT_STATERR_IPE)) { 6987 /* work around errata with sctp packets where the TCPE aka 6988 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6989 * packets, (aka let the stack check the crc32c) 6990 */ 6991 if (!((skb->len == 60) && 6992 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6993 u64_stats_update_begin(&ring->rx_syncp); 6994 ring->rx_stats.csum_err++; 6995 u64_stats_update_end(&ring->rx_syncp); 6996 } 6997 /* let the stack verify checksum errors */ 6998 return; 6999 } 7000 /* It must be a TCP or UDP packet with a valid checksum */ 7001 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7002 E1000_RXD_STAT_UDPCS)) 7003 skb->ip_summed = CHECKSUM_UNNECESSARY; 7004 7005 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7006 le32_to_cpu(rx_desc->wb.upper.status_error)); 7007 } 7008 7009 static inline void igb_rx_hash(struct igb_ring *ring, 7010 union e1000_adv_rx_desc *rx_desc, 7011 struct sk_buff *skb) 7012 { 7013 if (ring->netdev->features & NETIF_F_RXHASH) 7014 skb_set_hash(skb, 7015 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7016 PKT_HASH_TYPE_L3); 7017 } 7018 7019 /** 7020 * igb_is_non_eop - process handling of non-EOP buffers 7021 * @rx_ring: Rx ring being processed 7022 * @rx_desc: Rx descriptor for current buffer 7023 * @skb: current socket buffer containing buffer in progress 7024 * 7025 * This function updates next to clean. If the buffer is an EOP buffer 7026 * this function exits returning false, otherwise it will place the 7027 * sk_buff in the next buffer to be chained and return true indicating 7028 * that this is in fact a non-EOP buffer. 7029 **/ 7030 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7031 union e1000_adv_rx_desc *rx_desc) 7032 { 7033 u32 ntc = rx_ring->next_to_clean + 1; 7034 7035 /* fetch, update, and store next to clean */ 7036 ntc = (ntc < rx_ring->count) ? ntc : 0; 7037 rx_ring->next_to_clean = ntc; 7038 7039 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7040 7041 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7042 return false; 7043 7044 return true; 7045 } 7046 7047 /** 7048 * igb_cleanup_headers - Correct corrupted or empty headers 7049 * @rx_ring: rx descriptor ring packet is being transacted on 7050 * @rx_desc: pointer to the EOP Rx descriptor 7051 * @skb: pointer to current skb being fixed 7052 * 7053 * Address the case where we are pulling data in on pages only 7054 * and as such no data is present in the skb header. 7055 * 7056 * In addition if skb is not at least 60 bytes we need to pad it so that 7057 * it is large enough to qualify as a valid Ethernet frame. 7058 * 7059 * Returns true if an error was encountered and skb was freed. 7060 **/ 7061 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7062 union e1000_adv_rx_desc *rx_desc, 7063 struct sk_buff *skb) 7064 { 7065 if (unlikely((igb_test_staterr(rx_desc, 7066 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7067 struct net_device *netdev = rx_ring->netdev; 7068 if (!(netdev->features & NETIF_F_RXALL)) { 7069 dev_kfree_skb_any(skb); 7070 return true; 7071 } 7072 } 7073 7074 /* if eth_skb_pad returns an error the skb was freed */ 7075 if (eth_skb_pad(skb)) 7076 return true; 7077 7078 return false; 7079 } 7080 7081 /** 7082 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7083 * @rx_ring: rx descriptor ring packet is being transacted on 7084 * @rx_desc: pointer to the EOP Rx descriptor 7085 * @skb: pointer to current skb being populated 7086 * 7087 * This function checks the ring, descriptor, and packet information in 7088 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7089 * other fields within the skb. 7090 **/ 7091 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7092 union e1000_adv_rx_desc *rx_desc, 7093 struct sk_buff *skb) 7094 { 7095 struct net_device *dev = rx_ring->netdev; 7096 7097 igb_rx_hash(rx_ring, rx_desc, skb); 7098 7099 igb_rx_checksum(rx_ring, rx_desc, skb); 7100 7101 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7102 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7103 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7104 7105 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7106 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7107 u16 vid; 7108 7109 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7110 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7111 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7112 else 7113 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7114 7115 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7116 } 7117 7118 skb_record_rx_queue(skb, rx_ring->queue_index); 7119 7120 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7121 } 7122 7123 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7124 { 7125 struct igb_ring *rx_ring = q_vector->rx.ring; 7126 struct sk_buff *skb = rx_ring->skb; 7127 unsigned int total_bytes = 0, total_packets = 0; 7128 u16 cleaned_count = igb_desc_unused(rx_ring); 7129 7130 while (likely(total_packets < budget)) { 7131 union e1000_adv_rx_desc *rx_desc; 7132 7133 /* return some buffers to hardware, one at a time is too slow */ 7134 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7135 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7136 cleaned_count = 0; 7137 } 7138 7139 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7140 7141 if (!rx_desc->wb.upper.status_error) 7142 break; 7143 7144 /* This memory barrier is needed to keep us from reading 7145 * any other fields out of the rx_desc until we know the 7146 * descriptor has been written back 7147 */ 7148 dma_rmb(); 7149 7150 /* retrieve a buffer from the ring */ 7151 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7152 7153 /* exit if we failed to retrieve a buffer */ 7154 if (!skb) 7155 break; 7156 7157 cleaned_count++; 7158 7159 /* fetch next buffer in frame if non-eop */ 7160 if (igb_is_non_eop(rx_ring, rx_desc)) 7161 continue; 7162 7163 /* verify the packet layout is correct */ 7164 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7165 skb = NULL; 7166 continue; 7167 } 7168 7169 /* probably a little skewed due to removing CRC */ 7170 total_bytes += skb->len; 7171 7172 /* populate checksum, timestamp, VLAN, and protocol */ 7173 igb_process_skb_fields(rx_ring, rx_desc, skb); 7174 7175 napi_gro_receive(&q_vector->napi, skb); 7176 7177 /* reset skb pointer */ 7178 skb = NULL; 7179 7180 /* update budget accounting */ 7181 total_packets++; 7182 } 7183 7184 /* place incomplete frames back on ring for completion */ 7185 rx_ring->skb = skb; 7186 7187 u64_stats_update_begin(&rx_ring->rx_syncp); 7188 rx_ring->rx_stats.packets += total_packets; 7189 rx_ring->rx_stats.bytes += total_bytes; 7190 u64_stats_update_end(&rx_ring->rx_syncp); 7191 q_vector->rx.total_packets += total_packets; 7192 q_vector->rx.total_bytes += total_bytes; 7193 7194 if (cleaned_count) 7195 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7196 7197 return total_packets; 7198 } 7199 7200 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7201 struct igb_rx_buffer *bi) 7202 { 7203 struct page *page = bi->page; 7204 dma_addr_t dma; 7205 7206 /* since we are recycling buffers we should seldom need to alloc */ 7207 if (likely(page)) 7208 return true; 7209 7210 /* alloc new page for storage */ 7211 page = dev_alloc_page(); 7212 if (unlikely(!page)) { 7213 rx_ring->rx_stats.alloc_failed++; 7214 return false; 7215 } 7216 7217 /* map page for use */ 7218 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7219 7220 /* if mapping failed free memory back to system since 7221 * there isn't much point in holding memory we can't use 7222 */ 7223 if (dma_mapping_error(rx_ring->dev, dma)) { 7224 __free_page(page); 7225 7226 rx_ring->rx_stats.alloc_failed++; 7227 return false; 7228 } 7229 7230 bi->dma = dma; 7231 bi->page = page; 7232 bi->page_offset = 0; 7233 7234 return true; 7235 } 7236 7237 /** 7238 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7239 * @adapter: address of board private structure 7240 **/ 7241 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7242 { 7243 union e1000_adv_rx_desc *rx_desc; 7244 struct igb_rx_buffer *bi; 7245 u16 i = rx_ring->next_to_use; 7246 7247 /* nothing to do */ 7248 if (!cleaned_count) 7249 return; 7250 7251 rx_desc = IGB_RX_DESC(rx_ring, i); 7252 bi = &rx_ring->rx_buffer_info[i]; 7253 i -= rx_ring->count; 7254 7255 do { 7256 if (!igb_alloc_mapped_page(rx_ring, bi)) 7257 break; 7258 7259 /* Refresh the desc even if buffer_addrs didn't change 7260 * because each write-back erases this info. 7261 */ 7262 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7263 7264 rx_desc++; 7265 bi++; 7266 i++; 7267 if (unlikely(!i)) { 7268 rx_desc = IGB_RX_DESC(rx_ring, 0); 7269 bi = rx_ring->rx_buffer_info; 7270 i -= rx_ring->count; 7271 } 7272 7273 /* clear the status bits for the next_to_use descriptor */ 7274 rx_desc->wb.upper.status_error = 0; 7275 7276 cleaned_count--; 7277 } while (cleaned_count); 7278 7279 i += rx_ring->count; 7280 7281 if (rx_ring->next_to_use != i) { 7282 /* record the next descriptor to use */ 7283 rx_ring->next_to_use = i; 7284 7285 /* update next to alloc since we have filled the ring */ 7286 rx_ring->next_to_alloc = i; 7287 7288 /* Force memory writes to complete before letting h/w 7289 * know there are new descriptors to fetch. (Only 7290 * applicable for weak-ordered memory model archs, 7291 * such as IA-64). 7292 */ 7293 wmb(); 7294 writel(i, rx_ring->tail); 7295 } 7296 } 7297 7298 /** 7299 * igb_mii_ioctl - 7300 * @netdev: 7301 * @ifreq: 7302 * @cmd: 7303 **/ 7304 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7305 { 7306 struct igb_adapter *adapter = netdev_priv(netdev); 7307 struct mii_ioctl_data *data = if_mii(ifr); 7308 7309 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7310 return -EOPNOTSUPP; 7311 7312 switch (cmd) { 7313 case SIOCGMIIPHY: 7314 data->phy_id = adapter->hw.phy.addr; 7315 break; 7316 case SIOCGMIIREG: 7317 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7318 &data->val_out)) 7319 return -EIO; 7320 break; 7321 case SIOCSMIIREG: 7322 default: 7323 return -EOPNOTSUPP; 7324 } 7325 return 0; 7326 } 7327 7328 /** 7329 * igb_ioctl - 7330 * @netdev: 7331 * @ifreq: 7332 * @cmd: 7333 **/ 7334 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7335 { 7336 switch (cmd) { 7337 case SIOCGMIIPHY: 7338 case SIOCGMIIREG: 7339 case SIOCSMIIREG: 7340 return igb_mii_ioctl(netdev, ifr, cmd); 7341 case SIOCGHWTSTAMP: 7342 return igb_ptp_get_ts_config(netdev, ifr); 7343 case SIOCSHWTSTAMP: 7344 return igb_ptp_set_ts_config(netdev, ifr); 7345 default: 7346 return -EOPNOTSUPP; 7347 } 7348 } 7349 7350 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7351 { 7352 struct igb_adapter *adapter = hw->back; 7353 7354 pci_read_config_word(adapter->pdev, reg, value); 7355 } 7356 7357 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7358 { 7359 struct igb_adapter *adapter = hw->back; 7360 7361 pci_write_config_word(adapter->pdev, reg, *value); 7362 } 7363 7364 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7365 { 7366 struct igb_adapter *adapter = hw->back; 7367 7368 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7369 return -E1000_ERR_CONFIG; 7370 7371 return 0; 7372 } 7373 7374 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7375 { 7376 struct igb_adapter *adapter = hw->back; 7377 7378 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7379 return -E1000_ERR_CONFIG; 7380 7381 return 0; 7382 } 7383 7384 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7385 { 7386 struct igb_adapter *adapter = netdev_priv(netdev); 7387 struct e1000_hw *hw = &adapter->hw; 7388 u32 ctrl, rctl; 7389 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7390 7391 if (enable) { 7392 /* enable VLAN tag insert/strip */ 7393 ctrl = rd32(E1000_CTRL); 7394 ctrl |= E1000_CTRL_VME; 7395 wr32(E1000_CTRL, ctrl); 7396 7397 /* Disable CFI check */ 7398 rctl = rd32(E1000_RCTL); 7399 rctl &= ~E1000_RCTL_CFIEN; 7400 wr32(E1000_RCTL, rctl); 7401 } else { 7402 /* disable VLAN tag insert/strip */ 7403 ctrl = rd32(E1000_CTRL); 7404 ctrl &= ~E1000_CTRL_VME; 7405 wr32(E1000_CTRL, ctrl); 7406 } 7407 7408 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7409 } 7410 7411 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7412 __be16 proto, u16 vid) 7413 { 7414 struct igb_adapter *adapter = netdev_priv(netdev); 7415 struct e1000_hw *hw = &adapter->hw; 7416 int pf_id = adapter->vfs_allocated_count; 7417 7418 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7419 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7420 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7421 7422 set_bit(vid, adapter->active_vlans); 7423 7424 return 0; 7425 } 7426 7427 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7428 __be16 proto, u16 vid) 7429 { 7430 struct igb_adapter *adapter = netdev_priv(netdev); 7431 int pf_id = adapter->vfs_allocated_count; 7432 struct e1000_hw *hw = &adapter->hw; 7433 7434 /* remove VID from filter table */ 7435 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7436 igb_vfta_set(hw, vid, pf_id, false, true); 7437 7438 clear_bit(vid, adapter->active_vlans); 7439 7440 return 0; 7441 } 7442 7443 static void igb_restore_vlan(struct igb_adapter *adapter) 7444 { 7445 u16 vid = 1; 7446 7447 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7448 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7449 7450 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7451 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7452 } 7453 7454 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7455 { 7456 struct pci_dev *pdev = adapter->pdev; 7457 struct e1000_mac_info *mac = &adapter->hw.mac; 7458 7459 mac->autoneg = 0; 7460 7461 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7462 * for the switch() below to work 7463 */ 7464 if ((spd & 1) || (dplx & ~1)) 7465 goto err_inval; 7466 7467 /* Fiber NIC's only allow 1000 gbps Full duplex 7468 * and 100Mbps Full duplex for 100baseFx sfp 7469 */ 7470 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7471 switch (spd + dplx) { 7472 case SPEED_10 + DUPLEX_HALF: 7473 case SPEED_10 + DUPLEX_FULL: 7474 case SPEED_100 + DUPLEX_HALF: 7475 goto err_inval; 7476 default: 7477 break; 7478 } 7479 } 7480 7481 switch (spd + dplx) { 7482 case SPEED_10 + DUPLEX_HALF: 7483 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7484 break; 7485 case SPEED_10 + DUPLEX_FULL: 7486 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7487 break; 7488 case SPEED_100 + DUPLEX_HALF: 7489 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7490 break; 7491 case SPEED_100 + DUPLEX_FULL: 7492 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7493 break; 7494 case SPEED_1000 + DUPLEX_FULL: 7495 mac->autoneg = 1; 7496 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7497 break; 7498 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7499 default: 7500 goto err_inval; 7501 } 7502 7503 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7504 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7505 7506 return 0; 7507 7508 err_inval: 7509 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7510 return -EINVAL; 7511 } 7512 7513 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7514 bool runtime) 7515 { 7516 struct net_device *netdev = pci_get_drvdata(pdev); 7517 struct igb_adapter *adapter = netdev_priv(netdev); 7518 struct e1000_hw *hw = &adapter->hw; 7519 u32 ctrl, rctl, status; 7520 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7521 #ifdef CONFIG_PM 7522 int retval = 0; 7523 #endif 7524 7525 netif_device_detach(netdev); 7526 7527 if (netif_running(netdev)) 7528 __igb_close(netdev, true); 7529 7530 igb_clear_interrupt_scheme(adapter); 7531 7532 #ifdef CONFIG_PM 7533 retval = pci_save_state(pdev); 7534 if (retval) 7535 return retval; 7536 #endif 7537 7538 status = rd32(E1000_STATUS); 7539 if (status & E1000_STATUS_LU) 7540 wufc &= ~E1000_WUFC_LNKC; 7541 7542 if (wufc) { 7543 igb_setup_rctl(adapter); 7544 igb_set_rx_mode(netdev); 7545 7546 /* turn on all-multi mode if wake on multicast is enabled */ 7547 if (wufc & E1000_WUFC_MC) { 7548 rctl = rd32(E1000_RCTL); 7549 rctl |= E1000_RCTL_MPE; 7550 wr32(E1000_RCTL, rctl); 7551 } 7552 7553 ctrl = rd32(E1000_CTRL); 7554 /* advertise wake from D3Cold */ 7555 #define E1000_CTRL_ADVD3WUC 0x00100000 7556 /* phy power management enable */ 7557 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7558 ctrl |= E1000_CTRL_ADVD3WUC; 7559 wr32(E1000_CTRL, ctrl); 7560 7561 /* Allow time for pending master requests to run */ 7562 igb_disable_pcie_master(hw); 7563 7564 wr32(E1000_WUC, E1000_WUC_PME_EN); 7565 wr32(E1000_WUFC, wufc); 7566 } else { 7567 wr32(E1000_WUC, 0); 7568 wr32(E1000_WUFC, 0); 7569 } 7570 7571 *enable_wake = wufc || adapter->en_mng_pt; 7572 if (!*enable_wake) 7573 igb_power_down_link(adapter); 7574 else 7575 igb_power_up_link(adapter); 7576 7577 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7578 * would have already happened in close and is redundant. 7579 */ 7580 igb_release_hw_control(adapter); 7581 7582 pci_disable_device(pdev); 7583 7584 return 0; 7585 } 7586 7587 #ifdef CONFIG_PM 7588 #ifdef CONFIG_PM_SLEEP 7589 static int igb_suspend(struct device *dev) 7590 { 7591 int retval; 7592 bool wake; 7593 struct pci_dev *pdev = to_pci_dev(dev); 7594 7595 retval = __igb_shutdown(pdev, &wake, 0); 7596 if (retval) 7597 return retval; 7598 7599 if (wake) { 7600 pci_prepare_to_sleep(pdev); 7601 } else { 7602 pci_wake_from_d3(pdev, false); 7603 pci_set_power_state(pdev, PCI_D3hot); 7604 } 7605 7606 return 0; 7607 } 7608 #endif /* CONFIG_PM_SLEEP */ 7609 7610 static int igb_resume(struct device *dev) 7611 { 7612 struct pci_dev *pdev = to_pci_dev(dev); 7613 struct net_device *netdev = pci_get_drvdata(pdev); 7614 struct igb_adapter *adapter = netdev_priv(netdev); 7615 struct e1000_hw *hw = &adapter->hw; 7616 u32 err; 7617 7618 pci_set_power_state(pdev, PCI_D0); 7619 pci_restore_state(pdev); 7620 pci_save_state(pdev); 7621 7622 if (!pci_device_is_present(pdev)) 7623 return -ENODEV; 7624 err = pci_enable_device_mem(pdev); 7625 if (err) { 7626 dev_err(&pdev->dev, 7627 "igb: Cannot enable PCI device from suspend\n"); 7628 return err; 7629 } 7630 pci_set_master(pdev); 7631 7632 pci_enable_wake(pdev, PCI_D3hot, 0); 7633 pci_enable_wake(pdev, PCI_D3cold, 0); 7634 7635 if (igb_init_interrupt_scheme(adapter, true)) { 7636 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7637 return -ENOMEM; 7638 } 7639 7640 igb_reset(adapter); 7641 7642 /* let the f/w know that the h/w is now under the control of the 7643 * driver. 7644 */ 7645 igb_get_hw_control(adapter); 7646 7647 wr32(E1000_WUS, ~0); 7648 7649 if (netdev->flags & IFF_UP) { 7650 rtnl_lock(); 7651 err = __igb_open(netdev, true); 7652 rtnl_unlock(); 7653 if (err) 7654 return err; 7655 } 7656 7657 netif_device_attach(netdev); 7658 return 0; 7659 } 7660 7661 static int igb_runtime_idle(struct device *dev) 7662 { 7663 struct pci_dev *pdev = to_pci_dev(dev); 7664 struct net_device *netdev = pci_get_drvdata(pdev); 7665 struct igb_adapter *adapter = netdev_priv(netdev); 7666 7667 if (!igb_has_link(adapter)) 7668 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7669 7670 return -EBUSY; 7671 } 7672 7673 static int igb_runtime_suspend(struct device *dev) 7674 { 7675 struct pci_dev *pdev = to_pci_dev(dev); 7676 int retval; 7677 bool wake; 7678 7679 retval = __igb_shutdown(pdev, &wake, 1); 7680 if (retval) 7681 return retval; 7682 7683 if (wake) { 7684 pci_prepare_to_sleep(pdev); 7685 } else { 7686 pci_wake_from_d3(pdev, false); 7687 pci_set_power_state(pdev, PCI_D3hot); 7688 } 7689 7690 return 0; 7691 } 7692 7693 static int igb_runtime_resume(struct device *dev) 7694 { 7695 return igb_resume(dev); 7696 } 7697 #endif /* CONFIG_PM */ 7698 7699 static void igb_shutdown(struct pci_dev *pdev) 7700 { 7701 bool wake; 7702 7703 __igb_shutdown(pdev, &wake, 0); 7704 7705 if (system_state == SYSTEM_POWER_OFF) { 7706 pci_wake_from_d3(pdev, wake); 7707 pci_set_power_state(pdev, PCI_D3hot); 7708 } 7709 } 7710 7711 #ifdef CONFIG_PCI_IOV 7712 static int igb_sriov_reinit(struct pci_dev *dev) 7713 { 7714 struct net_device *netdev = pci_get_drvdata(dev); 7715 struct igb_adapter *adapter = netdev_priv(netdev); 7716 struct pci_dev *pdev = adapter->pdev; 7717 7718 rtnl_lock(); 7719 7720 if (netif_running(netdev)) 7721 igb_close(netdev); 7722 else 7723 igb_reset(adapter); 7724 7725 igb_clear_interrupt_scheme(adapter); 7726 7727 igb_init_queue_configuration(adapter); 7728 7729 if (igb_init_interrupt_scheme(adapter, true)) { 7730 rtnl_unlock(); 7731 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7732 return -ENOMEM; 7733 } 7734 7735 if (netif_running(netdev)) 7736 igb_open(netdev); 7737 7738 rtnl_unlock(); 7739 7740 return 0; 7741 } 7742 7743 static int igb_pci_disable_sriov(struct pci_dev *dev) 7744 { 7745 int err = igb_disable_sriov(dev); 7746 7747 if (!err) 7748 err = igb_sriov_reinit(dev); 7749 7750 return err; 7751 } 7752 7753 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7754 { 7755 int err = igb_enable_sriov(dev, num_vfs); 7756 7757 if (err) 7758 goto out; 7759 7760 err = igb_sriov_reinit(dev); 7761 if (!err) 7762 return num_vfs; 7763 7764 out: 7765 return err; 7766 } 7767 7768 #endif 7769 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7770 { 7771 #ifdef CONFIG_PCI_IOV 7772 if (num_vfs == 0) 7773 return igb_pci_disable_sriov(dev); 7774 else 7775 return igb_pci_enable_sriov(dev, num_vfs); 7776 #endif 7777 return 0; 7778 } 7779 7780 #ifdef CONFIG_NET_POLL_CONTROLLER 7781 /* Polling 'interrupt' - used by things like netconsole to send skbs 7782 * without having to re-enable interrupts. It's not called while 7783 * the interrupt routine is executing. 7784 */ 7785 static void igb_netpoll(struct net_device *netdev) 7786 { 7787 struct igb_adapter *adapter = netdev_priv(netdev); 7788 struct e1000_hw *hw = &adapter->hw; 7789 struct igb_q_vector *q_vector; 7790 int i; 7791 7792 for (i = 0; i < adapter->num_q_vectors; i++) { 7793 q_vector = adapter->q_vector[i]; 7794 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7795 wr32(E1000_EIMC, q_vector->eims_value); 7796 else 7797 igb_irq_disable(adapter); 7798 napi_schedule(&q_vector->napi); 7799 } 7800 } 7801 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7802 7803 /** 7804 * igb_io_error_detected - called when PCI error is detected 7805 * @pdev: Pointer to PCI device 7806 * @state: The current pci connection state 7807 * 7808 * This function is called after a PCI bus error affecting 7809 * this device has been detected. 7810 **/ 7811 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7812 pci_channel_state_t state) 7813 { 7814 struct net_device *netdev = pci_get_drvdata(pdev); 7815 struct igb_adapter *adapter = netdev_priv(netdev); 7816 7817 netif_device_detach(netdev); 7818 7819 if (state == pci_channel_io_perm_failure) 7820 return PCI_ERS_RESULT_DISCONNECT; 7821 7822 if (netif_running(netdev)) 7823 igb_down(adapter); 7824 pci_disable_device(pdev); 7825 7826 /* Request a slot slot reset. */ 7827 return PCI_ERS_RESULT_NEED_RESET; 7828 } 7829 7830 /** 7831 * igb_io_slot_reset - called after the pci bus has been reset. 7832 * @pdev: Pointer to PCI device 7833 * 7834 * Restart the card from scratch, as if from a cold-boot. Implementation 7835 * resembles the first-half of the igb_resume routine. 7836 **/ 7837 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7838 { 7839 struct net_device *netdev = pci_get_drvdata(pdev); 7840 struct igb_adapter *adapter = netdev_priv(netdev); 7841 struct e1000_hw *hw = &adapter->hw; 7842 pci_ers_result_t result; 7843 int err; 7844 7845 if (pci_enable_device_mem(pdev)) { 7846 dev_err(&pdev->dev, 7847 "Cannot re-enable PCI device after reset.\n"); 7848 result = PCI_ERS_RESULT_DISCONNECT; 7849 } else { 7850 pci_set_master(pdev); 7851 pci_restore_state(pdev); 7852 pci_save_state(pdev); 7853 7854 pci_enable_wake(pdev, PCI_D3hot, 0); 7855 pci_enable_wake(pdev, PCI_D3cold, 0); 7856 7857 igb_reset(adapter); 7858 wr32(E1000_WUS, ~0); 7859 result = PCI_ERS_RESULT_RECOVERED; 7860 } 7861 7862 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7863 if (err) { 7864 dev_err(&pdev->dev, 7865 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7866 err); 7867 /* non-fatal, continue */ 7868 } 7869 7870 return result; 7871 } 7872 7873 /** 7874 * igb_io_resume - called when traffic can start flowing again. 7875 * @pdev: Pointer to PCI device 7876 * 7877 * This callback is called when the error recovery driver tells us that 7878 * its OK to resume normal operation. Implementation resembles the 7879 * second-half of the igb_resume routine. 7880 */ 7881 static void igb_io_resume(struct pci_dev *pdev) 7882 { 7883 struct net_device *netdev = pci_get_drvdata(pdev); 7884 struct igb_adapter *adapter = netdev_priv(netdev); 7885 7886 if (netif_running(netdev)) { 7887 if (igb_up(adapter)) { 7888 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7889 return; 7890 } 7891 } 7892 7893 netif_device_attach(netdev); 7894 7895 /* let the f/w know that the h/w is now under the control of the 7896 * driver. 7897 */ 7898 igb_get_hw_control(adapter); 7899 } 7900 7901 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7902 u8 qsel) 7903 { 7904 struct e1000_hw *hw = &adapter->hw; 7905 u32 rar_low, rar_high; 7906 7907 /* HW expects these to be in network order when they are plugged 7908 * into the registers which are little endian. In order to guarantee 7909 * that ordering we need to do an leXX_to_cpup here in order to be 7910 * ready for the byteswap that occurs with writel 7911 */ 7912 rar_low = le32_to_cpup((__le32 *)(addr)); 7913 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 7914 7915 /* Indicate to hardware the Address is Valid. */ 7916 rar_high |= E1000_RAH_AV; 7917 7918 if (hw->mac.type == e1000_82575) 7919 rar_high |= E1000_RAH_POOL_1 * qsel; 7920 else 7921 rar_high |= E1000_RAH_POOL_1 << qsel; 7922 7923 wr32(E1000_RAL(index), rar_low); 7924 wrfl(); 7925 wr32(E1000_RAH(index), rar_high); 7926 wrfl(); 7927 } 7928 7929 static int igb_set_vf_mac(struct igb_adapter *adapter, 7930 int vf, unsigned char *mac_addr) 7931 { 7932 struct e1000_hw *hw = &adapter->hw; 7933 /* VF MAC addresses start at end of receive addresses and moves 7934 * towards the first, as a result a collision should not be possible 7935 */ 7936 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7937 7938 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7939 7940 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7941 7942 return 0; 7943 } 7944 7945 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7946 { 7947 struct igb_adapter *adapter = netdev_priv(netdev); 7948 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7949 return -EINVAL; 7950 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7951 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7952 dev_info(&adapter->pdev->dev, 7953 "Reload the VF driver to make this change effective."); 7954 if (test_bit(__IGB_DOWN, &adapter->state)) { 7955 dev_warn(&adapter->pdev->dev, 7956 "The VF MAC address has been set, but the PF device is not up.\n"); 7957 dev_warn(&adapter->pdev->dev, 7958 "Bring the PF device up before attempting to use the VF device.\n"); 7959 } 7960 return igb_set_vf_mac(adapter, vf, mac); 7961 } 7962 7963 static int igb_link_mbps(int internal_link_speed) 7964 { 7965 switch (internal_link_speed) { 7966 case SPEED_100: 7967 return 100; 7968 case SPEED_1000: 7969 return 1000; 7970 default: 7971 return 0; 7972 } 7973 } 7974 7975 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7976 int link_speed) 7977 { 7978 int rf_dec, rf_int; 7979 u32 bcnrc_val; 7980 7981 if (tx_rate != 0) { 7982 /* Calculate the rate factor values to set */ 7983 rf_int = link_speed / tx_rate; 7984 rf_dec = (link_speed - (rf_int * tx_rate)); 7985 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 7986 tx_rate; 7987 7988 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7989 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7990 E1000_RTTBCNRC_RF_INT_MASK); 7991 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7992 } else { 7993 bcnrc_val = 0; 7994 } 7995 7996 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7997 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7998 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7999 */ 8000 wr32(E1000_RTTBCNRM, 0x14); 8001 wr32(E1000_RTTBCNRC, bcnrc_val); 8002 } 8003 8004 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8005 { 8006 int actual_link_speed, i; 8007 bool reset_rate = false; 8008 8009 /* VF TX rate limit was not set or not supported */ 8010 if ((adapter->vf_rate_link_speed == 0) || 8011 (adapter->hw.mac.type != e1000_82576)) 8012 return; 8013 8014 actual_link_speed = igb_link_mbps(adapter->link_speed); 8015 if (actual_link_speed != adapter->vf_rate_link_speed) { 8016 reset_rate = true; 8017 adapter->vf_rate_link_speed = 0; 8018 dev_info(&adapter->pdev->dev, 8019 "Link speed has been changed. VF Transmit rate is disabled\n"); 8020 } 8021 8022 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8023 if (reset_rate) 8024 adapter->vf_data[i].tx_rate = 0; 8025 8026 igb_set_vf_rate_limit(&adapter->hw, i, 8027 adapter->vf_data[i].tx_rate, 8028 actual_link_speed); 8029 } 8030 } 8031 8032 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8033 int min_tx_rate, int max_tx_rate) 8034 { 8035 struct igb_adapter *adapter = netdev_priv(netdev); 8036 struct e1000_hw *hw = &adapter->hw; 8037 int actual_link_speed; 8038 8039 if (hw->mac.type != e1000_82576) 8040 return -EOPNOTSUPP; 8041 8042 if (min_tx_rate) 8043 return -EINVAL; 8044 8045 actual_link_speed = igb_link_mbps(adapter->link_speed); 8046 if ((vf >= adapter->vfs_allocated_count) || 8047 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8048 (max_tx_rate < 0) || 8049 (max_tx_rate > actual_link_speed)) 8050 return -EINVAL; 8051 8052 adapter->vf_rate_link_speed = actual_link_speed; 8053 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8054 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8055 8056 return 0; 8057 } 8058 8059 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8060 bool setting) 8061 { 8062 struct igb_adapter *adapter = netdev_priv(netdev); 8063 struct e1000_hw *hw = &adapter->hw; 8064 u32 reg_val, reg_offset; 8065 8066 if (!adapter->vfs_allocated_count) 8067 return -EOPNOTSUPP; 8068 8069 if (vf >= adapter->vfs_allocated_count) 8070 return -EINVAL; 8071 8072 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8073 reg_val = rd32(reg_offset); 8074 if (setting) 8075 reg_val |= (BIT(vf) | 8076 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8077 else 8078 reg_val &= ~(BIT(vf) | 8079 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8080 wr32(reg_offset, reg_val); 8081 8082 adapter->vf_data[vf].spoofchk_enabled = setting; 8083 return 0; 8084 } 8085 8086 static int igb_ndo_get_vf_config(struct net_device *netdev, 8087 int vf, struct ifla_vf_info *ivi) 8088 { 8089 struct igb_adapter *adapter = netdev_priv(netdev); 8090 if (vf >= adapter->vfs_allocated_count) 8091 return -EINVAL; 8092 ivi->vf = vf; 8093 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8094 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8095 ivi->min_tx_rate = 0; 8096 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8097 ivi->qos = adapter->vf_data[vf].pf_qos; 8098 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8099 return 0; 8100 } 8101 8102 static void igb_vmm_control(struct igb_adapter *adapter) 8103 { 8104 struct e1000_hw *hw = &adapter->hw; 8105 u32 reg; 8106 8107 switch (hw->mac.type) { 8108 case e1000_82575: 8109 case e1000_i210: 8110 case e1000_i211: 8111 case e1000_i354: 8112 default: 8113 /* replication is not supported for 82575 */ 8114 return; 8115 case e1000_82576: 8116 /* notify HW that the MAC is adding vlan tags */ 8117 reg = rd32(E1000_DTXCTL); 8118 reg |= E1000_DTXCTL_VLAN_ADDED; 8119 wr32(E1000_DTXCTL, reg); 8120 /* Fall through */ 8121 case e1000_82580: 8122 /* enable replication vlan tag stripping */ 8123 reg = rd32(E1000_RPLOLR); 8124 reg |= E1000_RPLOLR_STRVLAN; 8125 wr32(E1000_RPLOLR, reg); 8126 /* Fall through */ 8127 case e1000_i350: 8128 /* none of the above registers are supported by i350 */ 8129 break; 8130 } 8131 8132 if (adapter->vfs_allocated_count) { 8133 igb_vmdq_set_loopback_pf(hw, true); 8134 igb_vmdq_set_replication_pf(hw, true); 8135 igb_vmdq_set_anti_spoofing_pf(hw, true, 8136 adapter->vfs_allocated_count); 8137 } else { 8138 igb_vmdq_set_loopback_pf(hw, false); 8139 igb_vmdq_set_replication_pf(hw, false); 8140 } 8141 } 8142 8143 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8144 { 8145 struct e1000_hw *hw = &adapter->hw; 8146 u32 dmac_thr; 8147 u16 hwm; 8148 8149 if (hw->mac.type > e1000_82580) { 8150 if (adapter->flags & IGB_FLAG_DMAC) { 8151 u32 reg; 8152 8153 /* force threshold to 0. */ 8154 wr32(E1000_DMCTXTH, 0); 8155 8156 /* DMA Coalescing high water mark needs to be greater 8157 * than the Rx threshold. Set hwm to PBA - max frame 8158 * size in 16B units, capping it at PBA - 6KB. 8159 */ 8160 hwm = 64 * (pba - 6); 8161 reg = rd32(E1000_FCRTC); 8162 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8163 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8164 & E1000_FCRTC_RTH_COAL_MASK); 8165 wr32(E1000_FCRTC, reg); 8166 8167 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8168 * frame size, capping it at PBA - 10KB. 8169 */ 8170 dmac_thr = pba - 10; 8171 reg = rd32(E1000_DMACR); 8172 reg &= ~E1000_DMACR_DMACTHR_MASK; 8173 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8174 & E1000_DMACR_DMACTHR_MASK); 8175 8176 /* transition to L0x or L1 if available..*/ 8177 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8178 8179 /* watchdog timer= +-1000 usec in 32usec intervals */ 8180 reg |= (1000 >> 5); 8181 8182 /* Disable BMC-to-OS Watchdog Enable */ 8183 if (hw->mac.type != e1000_i354) 8184 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8185 8186 wr32(E1000_DMACR, reg); 8187 8188 /* no lower threshold to disable 8189 * coalescing(smart fifb)-UTRESH=0 8190 */ 8191 wr32(E1000_DMCRTRH, 0); 8192 8193 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8194 8195 wr32(E1000_DMCTLX, reg); 8196 8197 /* free space in tx packet buffer to wake from 8198 * DMA coal 8199 */ 8200 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8201 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8202 8203 /* make low power state decision controlled 8204 * by DMA coal 8205 */ 8206 reg = rd32(E1000_PCIEMISC); 8207 reg &= ~E1000_PCIEMISC_LX_DECISION; 8208 wr32(E1000_PCIEMISC, reg); 8209 } /* endif adapter->dmac is not disabled */ 8210 } else if (hw->mac.type == e1000_82580) { 8211 u32 reg = rd32(E1000_PCIEMISC); 8212 8213 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8214 wr32(E1000_DMACR, 0); 8215 } 8216 } 8217 8218 /** 8219 * igb_read_i2c_byte - Reads 8 bit word over I2C 8220 * @hw: pointer to hardware structure 8221 * @byte_offset: byte offset to read 8222 * @dev_addr: device address 8223 * @data: value read 8224 * 8225 * Performs byte read operation over I2C interface at 8226 * a specified device address. 8227 **/ 8228 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8229 u8 dev_addr, u8 *data) 8230 { 8231 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8232 struct i2c_client *this_client = adapter->i2c_client; 8233 s32 status; 8234 u16 swfw_mask = 0; 8235 8236 if (!this_client) 8237 return E1000_ERR_I2C; 8238 8239 swfw_mask = E1000_SWFW_PHY0_SM; 8240 8241 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8242 return E1000_ERR_SWFW_SYNC; 8243 8244 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8245 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8246 8247 if (status < 0) 8248 return E1000_ERR_I2C; 8249 else { 8250 *data = status; 8251 return 0; 8252 } 8253 } 8254 8255 /** 8256 * igb_write_i2c_byte - Writes 8 bit word over I2C 8257 * @hw: pointer to hardware structure 8258 * @byte_offset: byte offset to write 8259 * @dev_addr: device address 8260 * @data: value to write 8261 * 8262 * Performs byte write operation over I2C interface at 8263 * a specified device address. 8264 **/ 8265 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8266 u8 dev_addr, u8 data) 8267 { 8268 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8269 struct i2c_client *this_client = adapter->i2c_client; 8270 s32 status; 8271 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8272 8273 if (!this_client) 8274 return E1000_ERR_I2C; 8275 8276 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8277 return E1000_ERR_SWFW_SYNC; 8278 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8279 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8280 8281 if (status) 8282 return E1000_ERR_I2C; 8283 else 8284 return 0; 8285 8286 } 8287 8288 int igb_reinit_queues(struct igb_adapter *adapter) 8289 { 8290 struct net_device *netdev = adapter->netdev; 8291 struct pci_dev *pdev = adapter->pdev; 8292 int err = 0; 8293 8294 if (netif_running(netdev)) 8295 igb_close(netdev); 8296 8297 igb_reset_interrupt_capability(adapter); 8298 8299 if (igb_init_interrupt_scheme(adapter, true)) { 8300 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8301 return -ENOMEM; 8302 } 8303 8304 if (netif_running(netdev)) 8305 err = igb_open(netdev); 8306 8307 return err; 8308 } 8309 /* igb_main.c */ 8310