1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_set_rx_mode(struct net_device *); 119 static void igb_update_phy_info(struct timer_list *); 120 static void igb_watchdog(struct timer_list *); 121 static void igb_watchdog_task(struct work_struct *); 122 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123 static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125 static int igb_change_mtu(struct net_device *, int); 126 static int igb_set_mac(struct net_device *, void *); 127 static void igb_set_uta(struct igb_adapter *adapter, bool set); 128 static irqreturn_t igb_intr(int irq, void *); 129 static irqreturn_t igb_intr_msi(int irq, void *); 130 static irqreturn_t igb_msix_other(int irq, void *); 131 static irqreturn_t igb_msix_ring(int irq, void *); 132 #ifdef CONFIG_IGB_DCA 133 static void igb_update_dca(struct igb_q_vector *); 134 static void igb_setup_dca(struct igb_adapter *); 135 #endif /* CONFIG_IGB_DCA */ 136 static int igb_poll(struct napi_struct *, int); 137 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138 static int igb_clean_rx_irq(struct igb_q_vector *, int); 139 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141 static void igb_reset_task(struct work_struct *); 142 static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146 static void igb_restore_vlan(struct igb_adapter *); 147 static void igb_rar_set_index(struct igb_adapter *, u32); 148 static void igb_ping_all_vfs(struct igb_adapter *); 149 static void igb_msg_task(struct igb_adapter *); 150 static void igb_vmm_control(struct igb_adapter *); 151 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152 static void igb_flush_mac_table(struct igb_adapter *); 153 static int igb_available_rars(struct igb_adapter *, u8); 154 static void igb_set_default_mac_filter(struct igb_adapter *); 155 static int igb_uc_sync(struct net_device *, const unsigned char *); 156 static int igb_uc_unsync(struct net_device *, const unsigned char *); 157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168 static void igb_check_vf_rate_limit(struct igb_adapter *); 169 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172 #ifdef CONFIG_PCI_IOV 173 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175 #endif 176 177 #ifdef CONFIG_IGB_DCA 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179 static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183 }; 184 #endif 185 #ifdef CONFIG_PCI_IOV 186 static unsigned int max_vfs; 187 module_param(max_vfs, uint, 0444); 188 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189 #endif /* CONFIG_PCI_IOV */ 190 191 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194 static void igb_io_resume(struct pci_dev *); 195 196 static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200 }; 201 202 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205 MODULE_LICENSE("GPL v2"); 206 207 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208 static int debug = -1; 209 module_param(debug, int, 0); 210 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212 struct igb_reg_info { 213 u32 ofs; 214 char *name; 215 }; 216 217 static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251 }; 252 253 /* igb_regdump - register printout routine */ 254 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255 { 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317 } 318 319 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 320 static void igb_dump(struct igb_adapter *adapter) 321 { 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429 rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521 exit: 522 return; 523 } 524 525 /** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531 static int igb_get_i2c_data(void *data) 532 { 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538 } 539 540 /** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547 static void igb_set_i2c_data(void *data, int state) 548 { 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562 } 563 564 /** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571 static void igb_set_i2c_clk(void *data, int state) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585 } 586 587 /** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593 static int igb_get_i2c_clk(void *data) 594 { 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600 } 601 602 static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609 }; 610 611 /** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618 { 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621 } 622 623 static struct pci_driver igb_driver; 624 625 /** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631 static int __init igb_init_module(void) 632 { 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638 #ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640 #endif 641 ret = pci_register_driver(&igb_driver); 642 #ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645 #endif 646 return ret; 647 } 648 649 module_init(igb_init_module); 650 651 /** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657 static void __exit igb_exit_module(void) 658 { 659 #ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661 #endif 662 pci_unregister_driver(&igb_driver); 663 } 664 665 module_exit(igb_exit_module); 666 667 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668 /** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675 static void igb_cache_ring_register(struct igb_adapter *adapter) 676 { 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706 } 707 708 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709 { 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729 } 730 731 /** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745 { 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755 } 756 757 #define IGB_N0_QUEUE -1 758 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759 { 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834 } 835 836 /** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843 static void igb_configure_msix(struct igb_adapter *adapter) 844 { 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900 } 901 902 /** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909 static int igb_request_msix(struct igb_adapter *adapter) 910 { 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 951 netif_napi_set_irq(&q_vector->napi, 952 adapter->msix_entries[vector].vector); 953 } 954 955 igb_configure_msix(adapter); 956 return 0; 957 958 err_free: 959 /* free already assigned IRQs */ 960 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 961 962 vector--; 963 for (i = 0; i < vector; i++) { 964 free_irq(adapter->msix_entries[free_vector++].vector, 965 adapter->q_vector[i]); 966 } 967 err_out: 968 return err; 969 } 970 971 /** 972 * igb_free_q_vector - Free memory allocated for specific interrupt vector 973 * @adapter: board private structure to initialize 974 * @v_idx: Index of vector to be freed 975 * 976 * This function frees the memory allocated to the q_vector. 977 **/ 978 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 979 { 980 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 981 982 adapter->q_vector[v_idx] = NULL; 983 984 /* igb_get_stats64() might access the rings on this vector, 985 * we must wait a grace period before freeing it. 986 */ 987 if (q_vector) 988 kfree_rcu(q_vector, rcu); 989 } 990 991 /** 992 * igb_reset_q_vector - Reset config for interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be reset 995 * 996 * If NAPI is enabled it will delete any references to the 997 * NAPI struct. This is preparation for igb_free_q_vector. 998 **/ 999 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1004 * allocated. So, q_vector is NULL so we should stop here. 1005 */ 1006 if (!q_vector) 1007 return; 1008 1009 if (q_vector->tx.ring) 1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1011 1012 if (q_vector->rx.ring) 1013 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1014 1015 netif_napi_del(&q_vector->napi); 1016 1017 } 1018 1019 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1020 { 1021 int v_idx = adapter->num_q_vectors; 1022 1023 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1024 pci_disable_msix(adapter->pdev); 1025 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1026 pci_disable_msi(adapter->pdev); 1027 1028 while (v_idx--) 1029 igb_reset_q_vector(adapter, v_idx); 1030 } 1031 1032 /** 1033 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1034 * @adapter: board private structure to initialize 1035 * 1036 * This function frees the memory allocated to the q_vectors. In addition if 1037 * NAPI is enabled it will delete any references to the NAPI struct prior 1038 * to freeing the q_vector. 1039 **/ 1040 static void igb_free_q_vectors(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 adapter->num_tx_queues = 0; 1045 adapter->num_rx_queues = 0; 1046 adapter->num_q_vectors = 0; 1047 1048 while (v_idx--) { 1049 igb_reset_q_vector(adapter, v_idx); 1050 igb_free_q_vector(adapter, v_idx); 1051 } 1052 } 1053 1054 /** 1055 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1056 * @adapter: board private structure to initialize 1057 * 1058 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1059 * MSI-X interrupts allocated. 1060 */ 1061 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1062 { 1063 igb_free_q_vectors(adapter); 1064 igb_reset_interrupt_capability(adapter); 1065 } 1066 1067 /** 1068 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1069 * @adapter: board private structure to initialize 1070 * @msix: boolean value of MSIX capability 1071 * 1072 * Attempt to configure interrupts using the best available 1073 * capabilities of the hardware and kernel. 1074 **/ 1075 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1076 { 1077 int err; 1078 int numvecs, i; 1079 1080 if (!msix) 1081 goto msi_only; 1082 adapter->flags |= IGB_FLAG_HAS_MSIX; 1083 1084 /* Number of supported queues. */ 1085 adapter->num_rx_queues = adapter->rss_queues; 1086 if (adapter->vfs_allocated_count) 1087 adapter->num_tx_queues = 1; 1088 else 1089 adapter->num_tx_queues = adapter->rss_queues; 1090 1091 /* start with one vector for every Rx queue */ 1092 numvecs = adapter->num_rx_queues; 1093 1094 /* if Tx handler is separate add 1 for every Tx queue */ 1095 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1096 numvecs += adapter->num_tx_queues; 1097 1098 /* store the number of vectors reserved for queues */ 1099 adapter->num_q_vectors = numvecs; 1100 1101 /* add 1 vector for link status interrupts */ 1102 numvecs++; 1103 for (i = 0; i < numvecs; i++) 1104 adapter->msix_entries[i].entry = i; 1105 1106 err = pci_enable_msix_range(adapter->pdev, 1107 adapter->msix_entries, 1108 numvecs, 1109 numvecs); 1110 if (err > 0) 1111 return; 1112 1113 igb_reset_interrupt_capability(adapter); 1114 1115 /* If we can't do MSI-X, try MSI */ 1116 msi_only: 1117 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1118 #ifdef CONFIG_PCI_IOV 1119 /* disable SR-IOV for non MSI-X configurations */ 1120 if (adapter->vf_data) { 1121 struct e1000_hw *hw = &adapter->hw; 1122 /* disable iov and allow time for transactions to clear */ 1123 pci_disable_sriov(adapter->pdev); 1124 msleep(500); 1125 1126 kfree(adapter->vf_mac_list); 1127 adapter->vf_mac_list = NULL; 1128 kfree(adapter->vf_data); 1129 adapter->vf_data = NULL; 1130 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1131 wrfl(); 1132 msleep(100); 1133 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1134 } 1135 #endif 1136 adapter->vfs_allocated_count = 0; 1137 adapter->rss_queues = 1; 1138 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1139 adapter->num_rx_queues = 1; 1140 adapter->num_tx_queues = 1; 1141 adapter->num_q_vectors = 1; 1142 if (!pci_enable_msi(adapter->pdev)) 1143 adapter->flags |= IGB_FLAG_HAS_MSI; 1144 } 1145 1146 static void igb_add_ring(struct igb_ring *ring, 1147 struct igb_ring_container *head) 1148 { 1149 head->ring = ring; 1150 head->count++; 1151 } 1152 1153 /** 1154 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1155 * @adapter: board private structure to initialize 1156 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1157 * @v_idx: index of vector in adapter struct 1158 * @txr_count: total number of Tx rings to allocate 1159 * @txr_idx: index of first Tx ring to allocate 1160 * @rxr_count: total number of Rx rings to allocate 1161 * @rxr_idx: index of first Rx ring to allocate 1162 * 1163 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1164 **/ 1165 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1166 int v_count, int v_idx, 1167 int txr_count, int txr_idx, 1168 int rxr_count, int rxr_idx) 1169 { 1170 struct igb_q_vector *q_vector; 1171 struct igb_ring *ring; 1172 int ring_count; 1173 size_t size; 1174 1175 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1176 if (txr_count > 1 || rxr_count > 1) 1177 return -ENOMEM; 1178 1179 ring_count = txr_count + rxr_count; 1180 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1181 1182 /* allocate q_vector and rings */ 1183 q_vector = adapter->q_vector[v_idx]; 1184 if (!q_vector) { 1185 q_vector = kzalloc(size, GFP_KERNEL); 1186 } else if (size > ksize(q_vector)) { 1187 struct igb_q_vector *new_q_vector; 1188 1189 new_q_vector = kzalloc(size, GFP_KERNEL); 1190 if (new_q_vector) 1191 kfree_rcu(q_vector, rcu); 1192 q_vector = new_q_vector; 1193 } else { 1194 memset(q_vector, 0, size); 1195 } 1196 if (!q_vector) 1197 return -ENOMEM; 1198 1199 /* initialize NAPI */ 1200 netif_napi_add_config(adapter->netdev, &q_vector->napi, igb_poll, 1201 v_idx); 1202 1203 /* tie q_vector and adapter together */ 1204 adapter->q_vector[v_idx] = q_vector; 1205 q_vector->adapter = adapter; 1206 1207 /* initialize work limits */ 1208 q_vector->tx.work_limit = adapter->tx_work_limit; 1209 1210 /* initialize ITR configuration */ 1211 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1212 q_vector->itr_val = IGB_START_ITR; 1213 1214 /* initialize pointer to rings */ 1215 ring = q_vector->ring; 1216 1217 /* initialize ITR */ 1218 if (rxr_count) { 1219 /* rx or rx/tx vector */ 1220 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1221 q_vector->itr_val = adapter->rx_itr_setting; 1222 } else { 1223 /* tx only vector */ 1224 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1225 q_vector->itr_val = adapter->tx_itr_setting; 1226 } 1227 1228 if (txr_count) { 1229 /* assign generic ring traits */ 1230 ring->dev = &adapter->pdev->dev; 1231 ring->netdev = adapter->netdev; 1232 1233 /* configure backlink on ring */ 1234 ring->q_vector = q_vector; 1235 1236 /* update q_vector Tx values */ 1237 igb_add_ring(ring, &q_vector->tx); 1238 1239 /* For 82575, context index must be unique per ring. */ 1240 if (adapter->hw.mac.type == e1000_82575) 1241 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1242 1243 /* apply Tx specific ring traits */ 1244 ring->count = adapter->tx_ring_count; 1245 ring->queue_index = txr_idx; 1246 1247 ring->cbs_enable = false; 1248 ring->idleslope = 0; 1249 ring->sendslope = 0; 1250 ring->hicredit = 0; 1251 ring->locredit = 0; 1252 1253 u64_stats_init(&ring->tx_syncp); 1254 u64_stats_init(&ring->tx_syncp2); 1255 1256 /* assign ring to adapter */ 1257 adapter->tx_ring[txr_idx] = ring; 1258 1259 /* push pointer to next ring */ 1260 ring++; 1261 } 1262 1263 if (rxr_count) { 1264 /* assign generic ring traits */ 1265 ring->dev = &adapter->pdev->dev; 1266 ring->netdev = adapter->netdev; 1267 1268 /* configure backlink on ring */ 1269 ring->q_vector = q_vector; 1270 1271 /* update q_vector Rx values */ 1272 igb_add_ring(ring, &q_vector->rx); 1273 1274 /* set flag indicating ring supports SCTP checksum offload */ 1275 if (adapter->hw.mac.type >= e1000_82576) 1276 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1277 1278 /* On i350, i354, i210, and i211, loopback VLAN packets 1279 * have the tag byte-swapped. 1280 */ 1281 if (adapter->hw.mac.type >= e1000_i350) 1282 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1283 1284 /* apply Rx specific ring traits */ 1285 ring->count = adapter->rx_ring_count; 1286 ring->queue_index = rxr_idx; 1287 1288 u64_stats_init(&ring->rx_syncp); 1289 1290 /* assign ring to adapter */ 1291 adapter->rx_ring[rxr_idx] = ring; 1292 } 1293 1294 return 0; 1295 } 1296 1297 1298 /** 1299 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1300 * @adapter: board private structure to initialize 1301 * 1302 * We allocate one q_vector per queue interrupt. If allocation fails we 1303 * return -ENOMEM. 1304 **/ 1305 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1306 { 1307 int q_vectors = adapter->num_q_vectors; 1308 int rxr_remaining = adapter->num_rx_queues; 1309 int txr_remaining = adapter->num_tx_queues; 1310 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1311 int err; 1312 1313 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1314 for (; rxr_remaining; v_idx++) { 1315 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1316 0, 0, 1, rxr_idx); 1317 1318 if (err) 1319 goto err_out; 1320 1321 /* update counts and index */ 1322 rxr_remaining--; 1323 rxr_idx++; 1324 } 1325 } 1326 1327 for (; v_idx < q_vectors; v_idx++) { 1328 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1329 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1330 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 tqpv, txr_idx, rqpv, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining -= rqpv; 1339 txr_remaining -= tqpv; 1340 rxr_idx++; 1341 txr_idx++; 1342 } 1343 1344 return 0; 1345 1346 err_out: 1347 adapter->num_tx_queues = 0; 1348 adapter->num_rx_queues = 0; 1349 adapter->num_q_vectors = 0; 1350 1351 while (v_idx--) 1352 igb_free_q_vector(adapter, v_idx); 1353 1354 return -ENOMEM; 1355 } 1356 1357 /** 1358 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1359 * @adapter: board private structure to initialize 1360 * @msix: boolean value of MSIX capability 1361 * 1362 * This function initializes the interrupts and allocates all of the queues. 1363 **/ 1364 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1365 { 1366 struct pci_dev *pdev = adapter->pdev; 1367 int err; 1368 1369 igb_set_interrupt_capability(adapter, msix); 1370 1371 err = igb_alloc_q_vectors(adapter); 1372 if (err) { 1373 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1374 goto err_alloc_q_vectors; 1375 } 1376 1377 igb_cache_ring_register(adapter); 1378 1379 return 0; 1380 1381 err_alloc_q_vectors: 1382 igb_reset_interrupt_capability(adapter); 1383 return err; 1384 } 1385 1386 /** 1387 * igb_request_irq - initialize interrupts 1388 * @adapter: board private structure to initialize 1389 * 1390 * Attempts to configure interrupts using the best available 1391 * capabilities of the hardware and kernel. 1392 **/ 1393 static int igb_request_irq(struct igb_adapter *adapter) 1394 { 1395 struct net_device *netdev = adapter->netdev; 1396 struct pci_dev *pdev = adapter->pdev; 1397 int err = 0; 1398 1399 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1400 err = igb_request_msix(adapter); 1401 if (!err) 1402 goto request_done; 1403 /* fall back to MSI */ 1404 igb_free_all_tx_resources(adapter); 1405 igb_free_all_rx_resources(adapter); 1406 1407 igb_clear_interrupt_scheme(adapter); 1408 err = igb_init_interrupt_scheme(adapter, false); 1409 if (err) 1410 goto request_done; 1411 1412 igb_setup_all_tx_resources(adapter); 1413 igb_setup_all_rx_resources(adapter); 1414 igb_configure(adapter); 1415 } 1416 1417 igb_assign_vector(adapter->q_vector[0], 0); 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1420 err = request_irq(pdev->irq, igb_intr_msi, 0, 1421 netdev->name, adapter); 1422 if (!err) 1423 goto request_done; 1424 1425 /* fall back to legacy interrupts */ 1426 igb_reset_interrupt_capability(adapter); 1427 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1428 } 1429 1430 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1431 netdev->name, adapter); 1432 1433 if (err) 1434 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1435 err); 1436 1437 request_done: 1438 return err; 1439 } 1440 1441 static void igb_free_irq(struct igb_adapter *adapter) 1442 { 1443 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1444 int vector = 0, i; 1445 1446 free_irq(adapter->msix_entries[vector++].vector, adapter); 1447 1448 for (i = 0; i < adapter->num_q_vectors; i++) 1449 free_irq(adapter->msix_entries[vector++].vector, 1450 adapter->q_vector[i]); 1451 } else { 1452 free_irq(adapter->pdev->irq, adapter); 1453 } 1454 } 1455 1456 /** 1457 * igb_irq_disable - Mask off interrupt generation on the NIC 1458 * @adapter: board private structure 1459 **/ 1460 static void igb_irq_disable(struct igb_adapter *adapter) 1461 { 1462 struct e1000_hw *hw = &adapter->hw; 1463 1464 /* we need to be careful when disabling interrupts. The VFs are also 1465 * mapped into these registers and so clearing the bits can cause 1466 * issues on the VF drivers so we only need to clear what we set 1467 */ 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 u32 regval = rd32(E1000_EIAM); 1470 1471 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1472 wr32(E1000_EIMC, adapter->eims_enable_mask); 1473 regval = rd32(E1000_EIAC); 1474 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1475 } 1476 1477 wr32(E1000_IAM, 0); 1478 wr32(E1000_IMC, ~0); 1479 wrfl(); 1480 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1481 int i; 1482 1483 for (i = 0; i < adapter->num_q_vectors; i++) 1484 synchronize_irq(adapter->msix_entries[i].vector); 1485 } else { 1486 synchronize_irq(adapter->pdev->irq); 1487 } 1488 } 1489 1490 /** 1491 * igb_irq_enable - Enable default interrupt generation settings 1492 * @adapter: board private structure 1493 **/ 1494 static void igb_irq_enable(struct igb_adapter *adapter) 1495 { 1496 struct e1000_hw *hw = &adapter->hw; 1497 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1500 u32 regval = rd32(E1000_EIAC); 1501 1502 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1503 regval = rd32(E1000_EIAM); 1504 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1505 wr32(E1000_EIMS, adapter->eims_enable_mask); 1506 if (adapter->vfs_allocated_count) { 1507 wr32(E1000_MBVFIMR, 0xFF); 1508 ims |= E1000_IMS_VMMB; 1509 } 1510 wr32(E1000_IMS, ims); 1511 } else { 1512 wr32(E1000_IMS, IMS_ENABLE_MASK | 1513 E1000_IMS_DRSTA); 1514 wr32(E1000_IAM, IMS_ENABLE_MASK | 1515 E1000_IMS_DRSTA); 1516 } 1517 } 1518 1519 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1520 { 1521 struct e1000_hw *hw = &adapter->hw; 1522 u16 pf_id = adapter->vfs_allocated_count; 1523 u16 vid = adapter->hw.mng_cookie.vlan_id; 1524 u16 old_vid = adapter->mng_vlan_id; 1525 1526 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1527 /* add VID to filter table */ 1528 igb_vfta_set(hw, vid, pf_id, true, true); 1529 adapter->mng_vlan_id = vid; 1530 } else { 1531 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1532 } 1533 1534 if (old_vid != IGB_MNG_VLAN_NONE && vid != old_vid && 1535 !test_bit(old_vid, adapter->active_vlans)) { 1536 /* remove VID from filter table */ 1537 igb_vfta_set(hw, vid, pf_id, false, true); 1538 } 1539 } 1540 1541 /** 1542 * igb_release_hw_control - release control of the h/w to f/w 1543 * @adapter: address of board private structure 1544 * 1545 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1546 * For ASF and Pass Through versions of f/w this means that the 1547 * driver is no longer loaded. 1548 **/ 1549 static void igb_release_hw_control(struct igb_adapter *adapter) 1550 { 1551 struct e1000_hw *hw = &adapter->hw; 1552 u32 ctrl_ext; 1553 1554 /* Let firmware take over control of h/w */ 1555 ctrl_ext = rd32(E1000_CTRL_EXT); 1556 wr32(E1000_CTRL_EXT, 1557 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1558 } 1559 1560 /** 1561 * igb_get_hw_control - get control of the h/w from f/w 1562 * @adapter: address of board private structure 1563 * 1564 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1565 * For ASF and Pass Through versions of f/w this means that 1566 * the driver is loaded. 1567 **/ 1568 static void igb_get_hw_control(struct igb_adapter *adapter) 1569 { 1570 struct e1000_hw *hw = &adapter->hw; 1571 u32 ctrl_ext; 1572 1573 /* Let firmware know the driver has taken over */ 1574 ctrl_ext = rd32(E1000_CTRL_EXT); 1575 wr32(E1000_CTRL_EXT, 1576 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1577 } 1578 1579 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1580 { 1581 struct net_device *netdev = adapter->netdev; 1582 struct e1000_hw *hw = &adapter->hw; 1583 1584 WARN_ON(hw->mac.type != e1000_i210); 1585 1586 if (enable) 1587 adapter->flags |= IGB_FLAG_FQTSS; 1588 else 1589 adapter->flags &= ~IGB_FLAG_FQTSS; 1590 1591 if (netif_running(netdev)) 1592 schedule_work(&adapter->reset_task); 1593 } 1594 1595 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1596 { 1597 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1598 } 1599 1600 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1601 enum tx_queue_prio prio) 1602 { 1603 u32 val; 1604 1605 WARN_ON(hw->mac.type != e1000_i210); 1606 WARN_ON(queue < 0 || queue > 4); 1607 1608 val = rd32(E1000_I210_TXDCTL(queue)); 1609 1610 if (prio == TX_QUEUE_PRIO_HIGH) 1611 val |= E1000_TXDCTL_PRIORITY; 1612 else 1613 val &= ~E1000_TXDCTL_PRIORITY; 1614 1615 wr32(E1000_I210_TXDCTL(queue), val); 1616 } 1617 1618 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1619 { 1620 u32 val; 1621 1622 WARN_ON(hw->mac.type != e1000_i210); 1623 WARN_ON(queue < 0 || queue > 1); 1624 1625 val = rd32(E1000_I210_TQAVCC(queue)); 1626 1627 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1628 val |= E1000_TQAVCC_QUEUEMODE; 1629 else 1630 val &= ~E1000_TQAVCC_QUEUEMODE; 1631 1632 wr32(E1000_I210_TQAVCC(queue), val); 1633 } 1634 1635 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1636 { 1637 int i; 1638 1639 for (i = 0; i < adapter->num_tx_queues; i++) { 1640 if (adapter->tx_ring[i]->cbs_enable) 1641 return true; 1642 } 1643 1644 return false; 1645 } 1646 1647 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1648 { 1649 int i; 1650 1651 for (i = 0; i < adapter->num_tx_queues; i++) { 1652 if (adapter->tx_ring[i]->launchtime_enable) 1653 return true; 1654 } 1655 1656 return false; 1657 } 1658 1659 /** 1660 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1661 * @adapter: pointer to adapter struct 1662 * @queue: queue number 1663 * 1664 * Configure CBS and Launchtime for a given hardware queue. 1665 * Parameters are retrieved from the correct Tx ring, so 1666 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1667 * for setting those correctly prior to this function being called. 1668 **/ 1669 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1670 { 1671 struct net_device *netdev = adapter->netdev; 1672 struct e1000_hw *hw = &adapter->hw; 1673 struct igb_ring *ring; 1674 u32 tqavcc, tqavctrl; 1675 u16 value; 1676 1677 WARN_ON(hw->mac.type != e1000_i210); 1678 WARN_ON(queue < 0 || queue > 1); 1679 ring = adapter->tx_ring[queue]; 1680 1681 /* If any of the Qav features is enabled, configure queues as SR and 1682 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1683 * as SP. 1684 */ 1685 if (ring->cbs_enable || ring->launchtime_enable) { 1686 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1687 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1688 } else { 1689 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1690 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1691 } 1692 1693 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1694 if (ring->cbs_enable || queue == 0) { 1695 /* i210 does not allow the queue 0 to be in the Strict 1696 * Priority mode while the Qav mode is enabled, so, 1697 * instead of disabling strict priority mode, we give 1698 * queue 0 the maximum of credits possible. 1699 * 1700 * See section 8.12.19 of the i210 datasheet, "Note: 1701 * Queue0 QueueMode must be set to 1b when 1702 * TransmitMode is set to Qav." 1703 */ 1704 if (queue == 0 && !ring->cbs_enable) { 1705 /* max "linkspeed" idleslope in kbps */ 1706 ring->idleslope = 1000000; 1707 ring->hicredit = ETH_FRAME_LEN; 1708 } 1709 1710 /* Always set data transfer arbitration to credit-based 1711 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1712 * the queues. 1713 */ 1714 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1715 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1716 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1717 1718 /* According to i210 datasheet section 7.2.7.7, we should set 1719 * the 'idleSlope' field from TQAVCC register following the 1720 * equation: 1721 * 1722 * For 100 Mbps link speed: 1723 * 1724 * value = BW * 0x7735 * 0.2 (E1) 1725 * 1726 * For 1000Mbps link speed: 1727 * 1728 * value = BW * 0x7735 * 2 (E2) 1729 * 1730 * E1 and E2 can be merged into one equation as shown below. 1731 * Note that 'link-speed' is in Mbps. 1732 * 1733 * value = BW * 0x7735 * 2 * link-speed 1734 * -------------- (E3) 1735 * 1000 1736 * 1737 * 'BW' is the percentage bandwidth out of full link speed 1738 * which can be found with the following equation. Note that 1739 * idleSlope here is the parameter from this function which 1740 * is in kbps. 1741 * 1742 * BW = idleSlope 1743 * ----------------- (E4) 1744 * link-speed * 1000 1745 * 1746 * That said, we can come up with a generic equation to 1747 * calculate the value we should set it TQAVCC register by 1748 * replacing 'BW' in E3 by E4. The resulting equation is: 1749 * 1750 * value = idleSlope * 0x7735 * 2 * link-speed 1751 * ----------------- -------------- (E5) 1752 * link-speed * 1000 1000 1753 * 1754 * 'link-speed' is present in both sides of the fraction so 1755 * it is canceled out. The final equation is the following: 1756 * 1757 * value = idleSlope * 61034 1758 * ----------------- (E6) 1759 * 1000000 1760 * 1761 * NOTE: For i210, given the above, we can see that idleslope 1762 * is represented in 16.38431 kbps units by the value at 1763 * the TQAVCC register (1Gbps / 61034), which reduces 1764 * the granularity for idleslope increments. 1765 * For instance, if you want to configure a 2576kbps 1766 * idleslope, the value to be written on the register 1767 * would have to be 157.23. If rounded down, you end 1768 * up with less bandwidth available than originally 1769 * required (~2572 kbps). If rounded up, you end up 1770 * with a higher bandwidth (~2589 kbps). Below the 1771 * approach we take is to always round up the 1772 * calculated value, so the resulting bandwidth might 1773 * be slightly higher for some configurations. 1774 */ 1775 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1776 1777 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1778 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1779 tqavcc |= value; 1780 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1781 1782 wr32(E1000_I210_TQAVHC(queue), 1783 0x80000000 + ring->hicredit * 0x7735); 1784 } else { 1785 1786 /* Set idleSlope to zero. */ 1787 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1788 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 /* Set hiCredit to zero. */ 1792 wr32(E1000_I210_TQAVHC(queue), 0); 1793 1794 /* If CBS is not enabled for any queues anymore, then return to 1795 * the default state of Data Transmission Arbitration on 1796 * TQAVCTRL. 1797 */ 1798 if (!is_any_cbs_enabled(adapter)) { 1799 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1800 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1801 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1802 } 1803 } 1804 1805 /* If LaunchTime is enabled, set DataTranTIM. */ 1806 if (ring->launchtime_enable) { 1807 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1808 * for any of the SR queues, and configure fetchtime delta. 1809 * XXX NOTE: 1810 * - LaunchTime will be enabled for all SR queues. 1811 * - A fixed offset can be added relative to the launch 1812 * time of all packets if configured at reg LAUNCH_OS0. 1813 * We are keeping it as 0 for now (default value). 1814 */ 1815 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1816 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1817 E1000_TQAVCTRL_FETCHTIME_DELTA; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } else { 1820 /* If Launchtime is not enabled for any SR queues anymore, 1821 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1822 * effectively disabling Launchtime. 1823 */ 1824 if (!is_any_txtime_enabled(adapter)) { 1825 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1826 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1827 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1828 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1829 } 1830 } 1831 1832 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1833 * CBS are not configurable by software so we don't do any 'controller 1834 * configuration' in respect to these parameters. 1835 */ 1836 1837 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1838 ring->cbs_enable ? "enabled" : "disabled", 1839 ring->launchtime_enable ? "enabled" : "disabled", 1840 queue, 1841 ring->idleslope, ring->sendslope, 1842 ring->hicredit, ring->locredit); 1843 } 1844 1845 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1846 bool enable) 1847 { 1848 struct igb_ring *ring; 1849 1850 if (queue < 0 || queue > adapter->num_tx_queues) 1851 return -EINVAL; 1852 1853 ring = adapter->tx_ring[queue]; 1854 ring->launchtime_enable = enable; 1855 1856 return 0; 1857 } 1858 1859 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1860 bool enable, int idleslope, int sendslope, 1861 int hicredit, int locredit) 1862 { 1863 struct igb_ring *ring; 1864 1865 if (queue < 0 || queue > adapter->num_tx_queues) 1866 return -EINVAL; 1867 1868 ring = adapter->tx_ring[queue]; 1869 1870 ring->cbs_enable = enable; 1871 ring->idleslope = idleslope; 1872 ring->sendslope = sendslope; 1873 ring->hicredit = hicredit; 1874 ring->locredit = locredit; 1875 1876 return 0; 1877 } 1878 1879 /** 1880 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1881 * @adapter: pointer to adapter struct 1882 * 1883 * Configure TQAVCTRL register switching the controller's Tx mode 1884 * if FQTSS mode is enabled or disabled. Additionally, will issue 1885 * a call to igb_config_tx_modes() per queue so any previously saved 1886 * Tx parameters are applied. 1887 **/ 1888 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1889 { 1890 struct net_device *netdev = adapter->netdev; 1891 struct e1000_hw *hw = &adapter->hw; 1892 u32 val; 1893 1894 /* Only i210 controller supports changing the transmission mode. */ 1895 if (hw->mac.type != e1000_i210) 1896 return; 1897 1898 if (is_fqtss_enabled(adapter)) { 1899 int i, max_queue; 1900 1901 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1902 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1903 * so SP queues wait for SR ones. 1904 */ 1905 val = rd32(E1000_I210_TQAVCTRL); 1906 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1907 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1908 wr32(E1000_I210_TQAVCTRL, val); 1909 1910 /* Configure Tx and Rx packet buffers sizes as described in 1911 * i210 datasheet section 7.2.7.7. 1912 */ 1913 val = rd32(E1000_TXPBS); 1914 val &= ~I210_TXPBSIZE_MASK; 1915 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1916 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1917 wr32(E1000_TXPBS, val); 1918 1919 val = rd32(E1000_RXPBS); 1920 val &= ~I210_RXPBSIZE_MASK; 1921 val |= I210_RXPBSIZE_PB_30KB; 1922 wr32(E1000_RXPBS, val); 1923 1924 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1925 * register should not exceed the buffer size programmed in 1926 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1927 * so according to the datasheet we should set MAX_TPKT_SIZE to 1928 * 4kB / 64. 1929 * 1930 * However, when we do so, no frame from queue 2 and 3 are 1931 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1932 * or _equal_ to the buffer size programmed in TXPBS. For this 1933 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1934 */ 1935 val = (4096 - 1) / 64; 1936 wr32(E1000_I210_DTXMXPKTSZ, val); 1937 1938 /* Since FQTSS mode is enabled, apply any CBS configuration 1939 * previously set. If no previous CBS configuration has been 1940 * done, then the initial configuration is applied, which means 1941 * CBS is disabled. 1942 */ 1943 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1944 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1945 1946 for (i = 0; i < max_queue; i++) { 1947 igb_config_tx_modes(adapter, i); 1948 } 1949 } else { 1950 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1951 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1952 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1953 1954 val = rd32(E1000_I210_TQAVCTRL); 1955 /* According to Section 8.12.21, the other flags we've set when 1956 * enabling FQTSS are not relevant when disabling FQTSS so we 1957 * don't set they here. 1958 */ 1959 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1960 wr32(E1000_I210_TQAVCTRL, val); 1961 } 1962 1963 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1964 "enabled" : "disabled"); 1965 } 1966 1967 /** 1968 * igb_configure - configure the hardware for RX and TX 1969 * @adapter: private board structure 1970 **/ 1971 static void igb_configure(struct igb_adapter *adapter) 1972 { 1973 struct net_device *netdev = adapter->netdev; 1974 int i; 1975 1976 igb_get_hw_control(adapter); 1977 igb_set_rx_mode(netdev); 1978 igb_setup_tx_mode(adapter); 1979 1980 igb_restore_vlan(adapter); 1981 1982 igb_setup_tctl(adapter); 1983 igb_setup_mrqc(adapter); 1984 igb_setup_rctl(adapter); 1985 1986 igb_nfc_filter_restore(adapter); 1987 igb_configure_tx(adapter); 1988 igb_configure_rx(adapter); 1989 1990 igb_rx_fifo_flush_82575(&adapter->hw); 1991 1992 /* call igb_desc_unused which always leaves 1993 * at least 1 descriptor unused to make sure 1994 * next_to_use != next_to_clean 1995 */ 1996 for (i = 0; i < adapter->num_rx_queues; i++) { 1997 struct igb_ring *ring = adapter->rx_ring[i]; 1998 if (ring->xsk_pool) 1999 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 2000 igb_desc_unused(ring)); 2001 else 2002 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2003 } 2004 } 2005 2006 /** 2007 * igb_power_up_link - Power up the phy/serdes link 2008 * @adapter: address of board private structure 2009 **/ 2010 void igb_power_up_link(struct igb_adapter *adapter) 2011 { 2012 igb_reset_phy(&adapter->hw); 2013 2014 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2015 igb_power_up_phy_copper(&adapter->hw); 2016 else 2017 igb_power_up_serdes_link_82575(&adapter->hw); 2018 2019 igb_setup_link(&adapter->hw); 2020 } 2021 2022 /** 2023 * igb_power_down_link - Power down the phy/serdes link 2024 * @adapter: address of board private structure 2025 */ 2026 static void igb_power_down_link(struct igb_adapter *adapter) 2027 { 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_down_phy_copper_82575(&adapter->hw); 2030 else 2031 igb_shutdown_serdes_link_82575(&adapter->hw); 2032 } 2033 2034 /** 2035 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2036 * @adapter: address of the board private structure 2037 **/ 2038 static void igb_check_swap_media(struct igb_adapter *adapter) 2039 { 2040 struct e1000_hw *hw = &adapter->hw; 2041 u32 ctrl_ext, connsw; 2042 bool swap_now = false; 2043 2044 ctrl_ext = rd32(E1000_CTRL_EXT); 2045 connsw = rd32(E1000_CONNSW); 2046 2047 /* need to live swap if current media is copper and we have fiber/serdes 2048 * to go to. 2049 */ 2050 2051 if ((hw->phy.media_type == e1000_media_type_copper) && 2052 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2053 swap_now = true; 2054 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2055 !(connsw & E1000_CONNSW_SERDESD)) { 2056 /* copper signal takes time to appear */ 2057 if (adapter->copper_tries < 4) { 2058 adapter->copper_tries++; 2059 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2060 wr32(E1000_CONNSW, connsw); 2061 return; 2062 } else { 2063 adapter->copper_tries = 0; 2064 if ((connsw & E1000_CONNSW_PHYSD) && 2065 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2066 swap_now = true; 2067 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2068 wr32(E1000_CONNSW, connsw); 2069 } 2070 } 2071 } 2072 2073 if (!swap_now) 2074 return; 2075 2076 switch (hw->phy.media_type) { 2077 case e1000_media_type_copper: 2078 netdev_info(adapter->netdev, 2079 "MAS: changing media to fiber/serdes\n"); 2080 ctrl_ext |= 2081 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2082 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2083 adapter->copper_tries = 0; 2084 break; 2085 case e1000_media_type_internal_serdes: 2086 case e1000_media_type_fiber: 2087 netdev_info(adapter->netdev, 2088 "MAS: changing media to copper\n"); 2089 ctrl_ext &= 2090 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2091 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2092 break; 2093 default: 2094 /* shouldn't get here during regular operation */ 2095 netdev_err(adapter->netdev, 2096 "AMS: Invalid media type found, returning\n"); 2097 break; 2098 } 2099 wr32(E1000_CTRL_EXT, ctrl_ext); 2100 } 2101 2102 void igb_set_queue_napi(struct igb_adapter *adapter, int vector, 2103 struct napi_struct *napi) 2104 { 2105 struct igb_q_vector *q_vector = adapter->q_vector[vector]; 2106 2107 if (q_vector->rx.ring) 2108 netif_queue_set_napi(adapter->netdev, 2109 q_vector->rx.ring->queue_index, 2110 NETDEV_QUEUE_TYPE_RX, napi); 2111 2112 if (q_vector->tx.ring) 2113 netif_queue_set_napi(adapter->netdev, 2114 q_vector->tx.ring->queue_index, 2115 NETDEV_QUEUE_TYPE_TX, napi); 2116 } 2117 2118 /** 2119 * igb_up - Open the interface and prepare it to handle traffic 2120 * @adapter: board private structure 2121 **/ 2122 int igb_up(struct igb_adapter *adapter) 2123 { 2124 struct e1000_hw *hw = &adapter->hw; 2125 struct napi_struct *napi; 2126 int i; 2127 2128 /* hardware has been reset, we need to reload some things */ 2129 igb_configure(adapter); 2130 2131 clear_bit(__IGB_DOWN, &adapter->state); 2132 2133 for (i = 0; i < adapter->num_q_vectors; i++) { 2134 napi = &adapter->q_vector[i]->napi; 2135 napi_enable(napi); 2136 igb_set_queue_napi(adapter, i, napi); 2137 } 2138 2139 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2140 igb_configure_msix(adapter); 2141 else 2142 igb_assign_vector(adapter->q_vector[0], 0); 2143 2144 /* Clear any pending interrupts. */ 2145 rd32(E1000_TSICR); 2146 rd32(E1000_ICR); 2147 igb_irq_enable(adapter); 2148 2149 /* notify VFs that reset has been completed */ 2150 if (adapter->vfs_allocated_count) { 2151 u32 reg_data = rd32(E1000_CTRL_EXT); 2152 2153 reg_data |= E1000_CTRL_EXT_PFRSTD; 2154 wr32(E1000_CTRL_EXT, reg_data); 2155 } 2156 2157 netif_tx_start_all_queues(adapter->netdev); 2158 2159 /* start the watchdog. */ 2160 hw->mac.get_link_status = 1; 2161 schedule_work(&adapter->watchdog_task); 2162 2163 if ((adapter->flags & IGB_FLAG_EEE) && 2164 (!hw->dev_spec._82575.eee_disable)) 2165 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2166 2167 return 0; 2168 } 2169 2170 void igb_down(struct igb_adapter *adapter) 2171 { 2172 struct net_device *netdev = adapter->netdev; 2173 struct e1000_hw *hw = &adapter->hw; 2174 u32 tctl, rctl; 2175 int i; 2176 2177 /* signal that we're down so the interrupt handler does not 2178 * reschedule our watchdog timer 2179 */ 2180 set_bit(__IGB_DOWN, &adapter->state); 2181 2182 /* disable receives in the hardware */ 2183 rctl = rd32(E1000_RCTL); 2184 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2185 /* flush and sleep below */ 2186 2187 igb_nfc_filter_exit(adapter); 2188 2189 netif_carrier_off(netdev); 2190 netif_tx_stop_all_queues(netdev); 2191 2192 /* disable transmits in the hardware */ 2193 tctl = rd32(E1000_TCTL); 2194 tctl &= ~E1000_TCTL_EN; 2195 wr32(E1000_TCTL, tctl); 2196 /* flush both disables and wait for them to finish */ 2197 wrfl(); 2198 usleep_range(10000, 11000); 2199 2200 igb_irq_disable(adapter); 2201 2202 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2203 2204 for (i = 0; i < adapter->num_q_vectors; i++) { 2205 if (adapter->q_vector[i]) { 2206 napi_synchronize(&adapter->q_vector[i]->napi); 2207 igb_set_queue_napi(adapter, i, NULL); 2208 napi_disable(&adapter->q_vector[i]->napi); 2209 } 2210 } 2211 2212 timer_delete_sync(&adapter->watchdog_timer); 2213 timer_delete_sync(&adapter->phy_info_timer); 2214 2215 /* record the stats before reset*/ 2216 spin_lock(&adapter->stats64_lock); 2217 igb_update_stats(adapter); 2218 spin_unlock(&adapter->stats64_lock); 2219 2220 adapter->link_speed = 0; 2221 adapter->link_duplex = 0; 2222 2223 if (!pci_channel_offline(adapter->pdev)) 2224 igb_reset(adapter); 2225 2226 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2227 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2228 2229 igb_clean_all_tx_rings(adapter); 2230 igb_clean_all_rx_rings(adapter); 2231 #ifdef CONFIG_IGB_DCA 2232 2233 /* since we reset the hardware DCA settings were cleared */ 2234 igb_setup_dca(adapter); 2235 #endif 2236 } 2237 2238 void igb_reinit_locked(struct igb_adapter *adapter) 2239 { 2240 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2241 usleep_range(1000, 2000); 2242 igb_down(adapter); 2243 igb_up(adapter); 2244 clear_bit(__IGB_RESETTING, &adapter->state); 2245 } 2246 2247 /** igb_enable_mas - Media Autosense re-enable after swap 2248 * 2249 * @adapter: adapter struct 2250 **/ 2251 static void igb_enable_mas(struct igb_adapter *adapter) 2252 { 2253 struct e1000_hw *hw = &adapter->hw; 2254 u32 connsw = rd32(E1000_CONNSW); 2255 2256 /* configure for SerDes media detect */ 2257 if ((hw->phy.media_type == e1000_media_type_copper) && 2258 (!(connsw & E1000_CONNSW_SERDESD))) { 2259 connsw |= E1000_CONNSW_ENRGSRC; 2260 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2261 wr32(E1000_CONNSW, connsw); 2262 wrfl(); 2263 } 2264 } 2265 2266 #ifdef CONFIG_IGB_HWMON 2267 /** 2268 * igb_set_i2c_bb - Init I2C interface 2269 * @hw: pointer to hardware structure 2270 **/ 2271 static void igb_set_i2c_bb(struct e1000_hw *hw) 2272 { 2273 u32 ctrl_ext; 2274 s32 i2cctl; 2275 2276 ctrl_ext = rd32(E1000_CTRL_EXT); 2277 ctrl_ext |= E1000_CTRL_I2C_ENA; 2278 wr32(E1000_CTRL_EXT, ctrl_ext); 2279 wrfl(); 2280 2281 i2cctl = rd32(E1000_I2CPARAMS); 2282 i2cctl |= E1000_I2CBB_EN 2283 | E1000_I2C_CLK_OE_N 2284 | E1000_I2C_DATA_OE_N; 2285 wr32(E1000_I2CPARAMS, i2cctl); 2286 wrfl(); 2287 } 2288 #endif 2289 2290 void igb_reset(struct igb_adapter *adapter) 2291 { 2292 struct pci_dev *pdev = adapter->pdev; 2293 struct e1000_hw *hw = &adapter->hw; 2294 struct e1000_mac_info *mac = &hw->mac; 2295 struct e1000_fc_info *fc = &hw->fc; 2296 u32 pba, hwm; 2297 2298 /* Repartition Pba for greater than 9k mtu 2299 * To take effect CTRL.RST is required. 2300 */ 2301 switch (mac->type) { 2302 case e1000_i350: 2303 case e1000_i354: 2304 case e1000_82580: 2305 pba = rd32(E1000_RXPBS); 2306 pba = igb_rxpbs_adjust_82580(pba); 2307 break; 2308 case e1000_82576: 2309 pba = rd32(E1000_RXPBS); 2310 pba &= E1000_RXPBS_SIZE_MASK_82576; 2311 break; 2312 case e1000_82575: 2313 case e1000_i210: 2314 case e1000_i211: 2315 default: 2316 pba = E1000_PBA_34K; 2317 break; 2318 } 2319 2320 if (mac->type == e1000_82575) { 2321 u32 min_rx_space, min_tx_space, needed_tx_space; 2322 2323 /* write Rx PBA so that hardware can report correct Tx PBA */ 2324 wr32(E1000_PBA, pba); 2325 2326 /* To maintain wire speed transmits, the Tx FIFO should be 2327 * large enough to accommodate two full transmit packets, 2328 * rounded up to the next 1KB and expressed in KB. Likewise, 2329 * the Rx FIFO should be large enough to accommodate at least 2330 * one full receive packet and is similarly rounded up and 2331 * expressed in KB. 2332 */ 2333 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2334 2335 /* The Tx FIFO also stores 16 bytes of information about the Tx 2336 * but don't include Ethernet FCS because hardware appends it. 2337 * We only need to round down to the nearest 512 byte block 2338 * count since the value we care about is 2 frames, not 1. 2339 */ 2340 min_tx_space = adapter->max_frame_size; 2341 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2342 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2343 2344 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2345 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2346 2347 /* If current Tx allocation is less than the min Tx FIFO size, 2348 * and the min Tx FIFO size is less than the current Rx FIFO 2349 * allocation, take space away from current Rx allocation. 2350 */ 2351 if (needed_tx_space < pba) { 2352 pba -= needed_tx_space; 2353 2354 /* if short on Rx space, Rx wins and must trump Tx 2355 * adjustment 2356 */ 2357 if (pba < min_rx_space) 2358 pba = min_rx_space; 2359 } 2360 2361 /* adjust PBA for jumbo frames */ 2362 wr32(E1000_PBA, pba); 2363 } 2364 2365 /* flow control settings 2366 * The high water mark must be low enough to fit one full frame 2367 * after transmitting the pause frame. As such we must have enough 2368 * space to allow for us to complete our current transmit and then 2369 * receive the frame that is in progress from the link partner. 2370 * Set it to: 2371 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2372 */ 2373 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2374 2375 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2376 fc->low_water = fc->high_water - 16; 2377 fc->pause_time = 0xFFFF; 2378 fc->send_xon = 1; 2379 fc->current_mode = fc->requested_mode; 2380 2381 /* disable receive for all VFs and wait one second */ 2382 if (adapter->vfs_allocated_count) { 2383 int i; 2384 2385 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2386 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2387 2388 /* ping all the active vfs to let them know we are going down */ 2389 igb_ping_all_vfs(adapter); 2390 2391 /* disable transmits and receives */ 2392 wr32(E1000_VFRE, 0); 2393 wr32(E1000_VFTE, 0); 2394 } 2395 2396 /* Allow time for pending master requests to run */ 2397 hw->mac.ops.reset_hw(hw); 2398 wr32(E1000_WUC, 0); 2399 2400 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2401 /* need to resetup here after media swap */ 2402 adapter->ei.get_invariants(hw); 2403 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2404 } 2405 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2406 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2407 igb_enable_mas(adapter); 2408 } 2409 if (hw->mac.ops.init_hw(hw)) 2410 dev_err(&pdev->dev, "Hardware Error\n"); 2411 2412 /* RAR registers were cleared during init_hw, clear mac table */ 2413 igb_flush_mac_table(adapter); 2414 __dev_uc_unsync(adapter->netdev, NULL); 2415 2416 /* Recover default RAR entry */ 2417 igb_set_default_mac_filter(adapter); 2418 2419 /* Flow control settings reset on hardware reset, so guarantee flow 2420 * control is off when forcing speed. 2421 */ 2422 if (!hw->mac.autoneg) 2423 igb_force_mac_fc(hw); 2424 2425 igb_init_dmac(adapter, pba); 2426 #ifdef CONFIG_IGB_HWMON 2427 /* Re-initialize the thermal sensor on i350 devices. */ 2428 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2429 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2430 /* If present, re-initialize the external thermal sensor 2431 * interface. 2432 */ 2433 if (adapter->ets) 2434 igb_set_i2c_bb(hw); 2435 mac->ops.init_thermal_sensor_thresh(hw); 2436 } 2437 } 2438 #endif 2439 /* Re-establish EEE setting */ 2440 if (hw->phy.media_type == e1000_media_type_copper) { 2441 switch (mac->type) { 2442 case e1000_i350: 2443 case e1000_i210: 2444 case e1000_i211: 2445 igb_set_eee_i350(hw, true, true); 2446 break; 2447 case e1000_i354: 2448 igb_set_eee_i354(hw, true, true); 2449 break; 2450 default: 2451 break; 2452 } 2453 } 2454 if (!netif_running(adapter->netdev)) 2455 igb_power_down_link(adapter); 2456 2457 igb_update_mng_vlan(adapter); 2458 2459 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2460 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2461 2462 /* Re-enable PTP, where applicable. */ 2463 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2464 igb_ptp_reset(adapter); 2465 2466 igb_get_phy_info(hw); 2467 } 2468 2469 static netdev_features_t igb_fix_features(struct net_device *netdev, 2470 netdev_features_t features) 2471 { 2472 /* Since there is no support for separate Rx/Tx vlan accel 2473 * enable/disable make sure Tx flag is always in same state as Rx. 2474 */ 2475 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2476 features |= NETIF_F_HW_VLAN_CTAG_TX; 2477 else 2478 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2479 2480 return features; 2481 } 2482 2483 static int igb_set_features(struct net_device *netdev, 2484 netdev_features_t features) 2485 { 2486 netdev_features_t changed = netdev->features ^ features; 2487 struct igb_adapter *adapter = netdev_priv(netdev); 2488 2489 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2490 igb_vlan_mode(netdev, features); 2491 2492 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2493 return 0; 2494 2495 if (!(features & NETIF_F_NTUPLE)) { 2496 struct hlist_node *node2; 2497 struct igb_nfc_filter *rule; 2498 2499 spin_lock(&adapter->nfc_lock); 2500 hlist_for_each_entry_safe(rule, node2, 2501 &adapter->nfc_filter_list, nfc_node) { 2502 igb_erase_filter(adapter, rule); 2503 hlist_del(&rule->nfc_node); 2504 kfree(rule); 2505 } 2506 spin_unlock(&adapter->nfc_lock); 2507 adapter->nfc_filter_count = 0; 2508 } 2509 2510 netdev->features = features; 2511 2512 if (netif_running(netdev)) 2513 igb_reinit_locked(adapter); 2514 else 2515 igb_reset(adapter); 2516 2517 return 1; 2518 } 2519 2520 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2521 struct net_device *dev, 2522 const unsigned char *addr, u16 vid, 2523 u16 flags, bool *notified, 2524 struct netlink_ext_ack *extack) 2525 { 2526 /* guarantee we can provide a unique filter for the unicast address */ 2527 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2528 struct igb_adapter *adapter = netdev_priv(dev); 2529 int vfn = adapter->vfs_allocated_count; 2530 2531 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2532 return -ENOMEM; 2533 } 2534 2535 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2536 } 2537 2538 #define IGB_MAX_MAC_HDR_LEN 127 2539 #define IGB_MAX_NETWORK_HDR_LEN 511 2540 2541 static netdev_features_t 2542 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2543 netdev_features_t features) 2544 { 2545 unsigned int network_hdr_len, mac_hdr_len; 2546 2547 /* Make certain the headers can be described by a context descriptor */ 2548 mac_hdr_len = skb_network_offset(skb); 2549 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2550 return features & ~(NETIF_F_HW_CSUM | 2551 NETIF_F_SCTP_CRC | 2552 NETIF_F_GSO_UDP_L4 | 2553 NETIF_F_HW_VLAN_CTAG_TX | 2554 NETIF_F_TSO | 2555 NETIF_F_TSO6); 2556 2557 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2558 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2559 return features & ~(NETIF_F_HW_CSUM | 2560 NETIF_F_SCTP_CRC | 2561 NETIF_F_GSO_UDP_L4 | 2562 NETIF_F_TSO | 2563 NETIF_F_TSO6); 2564 2565 /* We can only support IPV4 TSO in tunnels if we can mangle the 2566 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2567 */ 2568 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2569 features &= ~NETIF_F_TSO; 2570 2571 return features; 2572 } 2573 2574 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2575 { 2576 if (!is_fqtss_enabled(adapter)) { 2577 enable_fqtss(adapter, true); 2578 return; 2579 } 2580 2581 igb_config_tx_modes(adapter, queue); 2582 2583 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2584 enable_fqtss(adapter, false); 2585 } 2586 2587 static int igb_offload_cbs(struct igb_adapter *adapter, 2588 struct tc_cbs_qopt_offload *qopt) 2589 { 2590 struct e1000_hw *hw = &adapter->hw; 2591 int err; 2592 2593 /* CBS offloading is only supported by i210 controller. */ 2594 if (hw->mac.type != e1000_i210) 2595 return -EOPNOTSUPP; 2596 2597 /* CBS offloading is only supported by queue 0 and queue 1. */ 2598 if (qopt->queue < 0 || qopt->queue > 1) 2599 return -EINVAL; 2600 2601 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2602 qopt->idleslope, qopt->sendslope, 2603 qopt->hicredit, qopt->locredit); 2604 if (err) 2605 return err; 2606 2607 igb_offload_apply(adapter, qopt->queue); 2608 2609 return 0; 2610 } 2611 2612 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2613 #define VLAN_PRIO_FULL_MASK (0x07) 2614 2615 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2616 struct flow_cls_offload *f, 2617 int traffic_class, 2618 struct igb_nfc_filter *input) 2619 { 2620 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2621 struct flow_dissector *dissector = rule->match.dissector; 2622 struct netlink_ext_ack *extack = f->common.extack; 2623 2624 if (dissector->used_keys & 2625 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2626 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2627 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2628 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2629 NL_SET_ERR_MSG_MOD(extack, 2630 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2631 return -EOPNOTSUPP; 2632 } 2633 2634 if (flow_rule_match_has_control_flags(rule, extack)) 2635 return -EOPNOTSUPP; 2636 2637 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2638 struct flow_match_eth_addrs match; 2639 2640 flow_rule_match_eth_addrs(rule, &match); 2641 if (!is_zero_ether_addr(match.mask->dst)) { 2642 if (!is_broadcast_ether_addr(match.mask->dst)) { 2643 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2644 return -EINVAL; 2645 } 2646 2647 input->filter.match_flags |= 2648 IGB_FILTER_FLAG_DST_MAC_ADDR; 2649 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2650 } 2651 2652 if (!is_zero_ether_addr(match.mask->src)) { 2653 if (!is_broadcast_ether_addr(match.mask->src)) { 2654 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2655 return -EINVAL; 2656 } 2657 2658 input->filter.match_flags |= 2659 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2660 ether_addr_copy(input->filter.src_addr, match.key->src); 2661 } 2662 } 2663 2664 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2665 struct flow_match_basic match; 2666 2667 flow_rule_match_basic(rule, &match); 2668 if (match.mask->n_proto) { 2669 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2670 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2671 return -EINVAL; 2672 } 2673 2674 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2675 input->filter.etype = match.key->n_proto; 2676 } 2677 } 2678 2679 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2680 struct flow_match_vlan match; 2681 2682 flow_rule_match_vlan(rule, &match); 2683 if (match.mask->vlan_priority) { 2684 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2685 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2686 return -EINVAL; 2687 } 2688 2689 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2690 input->filter.vlan_tci = 2691 (__force __be16)match.key->vlan_priority; 2692 } 2693 } 2694 2695 input->action = traffic_class; 2696 input->cookie = f->cookie; 2697 2698 return 0; 2699 } 2700 2701 static int igb_configure_clsflower(struct igb_adapter *adapter, 2702 struct flow_cls_offload *cls_flower) 2703 { 2704 struct netlink_ext_ack *extack = cls_flower->common.extack; 2705 struct igb_nfc_filter *filter, *f; 2706 int err, tc; 2707 2708 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2709 if (tc < 0) { 2710 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2711 return -EINVAL; 2712 } 2713 2714 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2715 if (!filter) 2716 return -ENOMEM; 2717 2718 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2719 if (err < 0) 2720 goto err_parse; 2721 2722 spin_lock(&adapter->nfc_lock); 2723 2724 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2725 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2726 err = -EEXIST; 2727 NL_SET_ERR_MSG_MOD(extack, 2728 "This filter is already set in ethtool"); 2729 goto err_locked; 2730 } 2731 } 2732 2733 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2734 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2735 err = -EEXIST; 2736 NL_SET_ERR_MSG_MOD(extack, 2737 "This filter is already set in cls_flower"); 2738 goto err_locked; 2739 } 2740 } 2741 2742 err = igb_add_filter(adapter, filter); 2743 if (err < 0) { 2744 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2745 goto err_locked; 2746 } 2747 2748 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2749 2750 spin_unlock(&adapter->nfc_lock); 2751 2752 return 0; 2753 2754 err_locked: 2755 spin_unlock(&adapter->nfc_lock); 2756 2757 err_parse: 2758 kfree(filter); 2759 2760 return err; 2761 } 2762 2763 static int igb_delete_clsflower(struct igb_adapter *adapter, 2764 struct flow_cls_offload *cls_flower) 2765 { 2766 struct igb_nfc_filter *filter; 2767 int err; 2768 2769 spin_lock(&adapter->nfc_lock); 2770 2771 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2772 if (filter->cookie == cls_flower->cookie) 2773 break; 2774 2775 if (!filter) { 2776 err = -ENOENT; 2777 goto out; 2778 } 2779 2780 err = igb_erase_filter(adapter, filter); 2781 if (err < 0) 2782 goto out; 2783 2784 hlist_del(&filter->nfc_node); 2785 kfree(filter); 2786 2787 out: 2788 spin_unlock(&adapter->nfc_lock); 2789 2790 return err; 2791 } 2792 2793 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2794 struct flow_cls_offload *cls_flower) 2795 { 2796 switch (cls_flower->command) { 2797 case FLOW_CLS_REPLACE: 2798 return igb_configure_clsflower(adapter, cls_flower); 2799 case FLOW_CLS_DESTROY: 2800 return igb_delete_clsflower(adapter, cls_flower); 2801 case FLOW_CLS_STATS: 2802 return -EOPNOTSUPP; 2803 default: 2804 return -EOPNOTSUPP; 2805 } 2806 } 2807 2808 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2809 void *cb_priv) 2810 { 2811 struct igb_adapter *adapter = cb_priv; 2812 2813 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2814 return -EOPNOTSUPP; 2815 2816 switch (type) { 2817 case TC_SETUP_CLSFLOWER: 2818 return igb_setup_tc_cls_flower(adapter, type_data); 2819 2820 default: 2821 return -EOPNOTSUPP; 2822 } 2823 } 2824 2825 static int igb_offload_txtime(struct igb_adapter *adapter, 2826 struct tc_etf_qopt_offload *qopt) 2827 { 2828 struct e1000_hw *hw = &adapter->hw; 2829 int err; 2830 2831 /* Launchtime offloading is only supported by i210 controller. */ 2832 if (hw->mac.type != e1000_i210) 2833 return -EOPNOTSUPP; 2834 2835 /* Launchtime offloading is only supported by queues 0 and 1. */ 2836 if (qopt->queue < 0 || qopt->queue > 1) 2837 return -EINVAL; 2838 2839 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2840 if (err) 2841 return err; 2842 2843 igb_offload_apply(adapter, qopt->queue); 2844 2845 return 0; 2846 } 2847 2848 static int igb_tc_query_caps(struct igb_adapter *adapter, 2849 struct tc_query_caps_base *base) 2850 { 2851 switch (base->type) { 2852 case TC_SETUP_QDISC_TAPRIO: { 2853 struct tc_taprio_caps *caps = base->caps; 2854 2855 caps->broken_mqprio = true; 2856 2857 return 0; 2858 } 2859 default: 2860 return -EOPNOTSUPP; 2861 } 2862 } 2863 2864 static LIST_HEAD(igb_block_cb_list); 2865 2866 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2867 void *type_data) 2868 { 2869 struct igb_adapter *adapter = netdev_priv(dev); 2870 2871 switch (type) { 2872 case TC_QUERY_CAPS: 2873 return igb_tc_query_caps(adapter, type_data); 2874 case TC_SETUP_QDISC_CBS: 2875 return igb_offload_cbs(adapter, type_data); 2876 case TC_SETUP_BLOCK: 2877 return flow_block_cb_setup_simple(type_data, 2878 &igb_block_cb_list, 2879 igb_setup_tc_block_cb, 2880 adapter, adapter, true); 2881 2882 case TC_SETUP_QDISC_ETF: 2883 return igb_offload_txtime(adapter, type_data); 2884 2885 default: 2886 return -EOPNOTSUPP; 2887 } 2888 } 2889 2890 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2891 { 2892 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2893 struct igb_adapter *adapter = netdev_priv(dev); 2894 struct bpf_prog *prog = bpf->prog, *old_prog; 2895 bool running = netif_running(dev); 2896 bool need_reset; 2897 2898 /* verify igb ring attributes are sufficient for XDP */ 2899 for (i = 0; i < adapter->num_rx_queues; i++) { 2900 struct igb_ring *ring = adapter->rx_ring[i]; 2901 2902 if (frame_size > igb_rx_bufsz(ring)) { 2903 NL_SET_ERR_MSG_MOD(bpf->extack, 2904 "The RX buffer size is too small for the frame size"); 2905 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2906 igb_rx_bufsz(ring), frame_size); 2907 return -EINVAL; 2908 } 2909 } 2910 2911 old_prog = xchg(&adapter->xdp_prog, prog); 2912 need_reset = (!!prog != !!old_prog); 2913 2914 /* device is up and bpf is added/removed, must setup the RX queues */ 2915 if (need_reset && running) { 2916 igb_close(dev); 2917 } else { 2918 for (i = 0; i < adapter->num_rx_queues; i++) 2919 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2920 adapter->xdp_prog); 2921 } 2922 2923 if (old_prog) 2924 bpf_prog_put(old_prog); 2925 2926 /* bpf is just replaced, RXQ and MTU are already setup */ 2927 if (!need_reset) { 2928 return 0; 2929 } else { 2930 if (prog) 2931 xdp_features_set_redirect_target(dev, true); 2932 else 2933 xdp_features_clear_redirect_target(dev); 2934 } 2935 2936 if (running) 2937 igb_open(dev); 2938 2939 return 0; 2940 } 2941 2942 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2943 { 2944 struct igb_adapter *adapter = netdev_priv(dev); 2945 2946 switch (xdp->command) { 2947 case XDP_SETUP_PROG: 2948 return igb_xdp_setup(dev, xdp); 2949 case XDP_SETUP_XSK_POOL: 2950 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2951 xdp->xsk.queue_id); 2952 default: 2953 return -EINVAL; 2954 } 2955 } 2956 2957 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2958 { 2959 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2960 int cpu = smp_processor_id(); 2961 struct igb_ring *tx_ring; 2962 struct netdev_queue *nq; 2963 u32 ret; 2964 2965 if (unlikely(!xdpf)) 2966 return IGB_XDP_CONSUMED; 2967 2968 /* During program transitions its possible adapter->xdp_prog is assigned 2969 * but ring has not been configured yet. In this case simply abort xmit. 2970 */ 2971 tx_ring = igb_xdp_is_enabled(adapter) ? 2972 igb_xdp_tx_queue_mapping(adapter) : NULL; 2973 if (unlikely(!tx_ring)) 2974 return IGB_XDP_CONSUMED; 2975 2976 nq = txring_txq(tx_ring); 2977 __netif_tx_lock(nq, cpu); 2978 /* Avoid transmit queue timeout since we share it with the slow path */ 2979 txq_trans_cond_update(nq); 2980 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2981 __netif_tx_unlock(nq); 2982 2983 return ret; 2984 } 2985 2986 static int igb_xdp_xmit(struct net_device *dev, int n, 2987 struct xdp_frame **frames, u32 flags) 2988 { 2989 struct igb_adapter *adapter = netdev_priv(dev); 2990 int cpu = smp_processor_id(); 2991 struct igb_ring *tx_ring; 2992 struct netdev_queue *nq; 2993 int nxmit = 0; 2994 int i; 2995 2996 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2997 return -ENETDOWN; 2998 2999 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3000 return -EINVAL; 3001 3002 /* During program transitions its possible adapter->xdp_prog is assigned 3003 * but ring has not been configured yet. In this case simply abort xmit. 3004 */ 3005 tx_ring = igb_xdp_is_enabled(adapter) ? 3006 igb_xdp_tx_queue_mapping(adapter) : NULL; 3007 if (unlikely(!tx_ring)) 3008 return -ENXIO; 3009 3010 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 3011 return -ENXIO; 3012 3013 nq = txring_txq(tx_ring); 3014 __netif_tx_lock(nq, cpu); 3015 3016 /* Avoid transmit queue timeout since we share it with the slow path */ 3017 txq_trans_cond_update(nq); 3018 3019 for (i = 0; i < n; i++) { 3020 struct xdp_frame *xdpf = frames[i]; 3021 int err; 3022 3023 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3024 if (err != IGB_XDP_TX) 3025 break; 3026 nxmit++; 3027 } 3028 3029 if (unlikely(flags & XDP_XMIT_FLUSH)) 3030 igb_xdp_ring_update_tail(tx_ring); 3031 3032 __netif_tx_unlock(nq); 3033 3034 return nxmit; 3035 } 3036 3037 static const struct net_device_ops igb_netdev_ops = { 3038 .ndo_open = igb_open, 3039 .ndo_stop = igb_close, 3040 .ndo_start_xmit = igb_xmit_frame, 3041 .ndo_get_stats64 = igb_get_stats64, 3042 .ndo_set_rx_mode = igb_set_rx_mode, 3043 .ndo_set_mac_address = igb_set_mac, 3044 .ndo_change_mtu = igb_change_mtu, 3045 .ndo_eth_ioctl = igb_ioctl, 3046 .ndo_tx_timeout = igb_tx_timeout, 3047 .ndo_validate_addr = eth_validate_addr, 3048 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3049 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3050 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3051 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3052 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3053 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3054 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3055 .ndo_get_vf_config = igb_ndo_get_vf_config, 3056 .ndo_fix_features = igb_fix_features, 3057 .ndo_set_features = igb_set_features, 3058 .ndo_fdb_add = igb_ndo_fdb_add, 3059 .ndo_features_check = igb_features_check, 3060 .ndo_setup_tc = igb_setup_tc, 3061 .ndo_bpf = igb_xdp, 3062 .ndo_xdp_xmit = igb_xdp_xmit, 3063 .ndo_xsk_wakeup = igb_xsk_wakeup, 3064 .ndo_hwtstamp_get = igb_ptp_hwtstamp_get, 3065 .ndo_hwtstamp_set = igb_ptp_hwtstamp_set, 3066 }; 3067 3068 /** 3069 * igb_set_fw_version - Configure version string for ethtool 3070 * @adapter: adapter struct 3071 **/ 3072 void igb_set_fw_version(struct igb_adapter *adapter) 3073 { 3074 struct e1000_hw *hw = &adapter->hw; 3075 struct e1000_fw_version fw; 3076 3077 igb_get_fw_version(hw, &fw); 3078 3079 switch (hw->mac.type) { 3080 case e1000_i210: 3081 case e1000_i211: 3082 if (!(igb_get_flash_presence_i210(hw))) { 3083 snprintf(adapter->fw_version, 3084 sizeof(adapter->fw_version), 3085 "%2d.%2d-%d", 3086 fw.invm_major, fw.invm_minor, 3087 fw.invm_img_type); 3088 break; 3089 } 3090 fallthrough; 3091 default: 3092 /* if option rom is valid, display its version too */ 3093 if (fw.or_valid) { 3094 snprintf(adapter->fw_version, 3095 sizeof(adapter->fw_version), 3096 "%d.%d, 0x%08x, %d.%d.%d", 3097 fw.eep_major, fw.eep_minor, fw.etrack_id, 3098 fw.or_major, fw.or_build, fw.or_patch); 3099 /* no option rom */ 3100 } else if (fw.etrack_id != 0X0000) { 3101 snprintf(adapter->fw_version, 3102 sizeof(adapter->fw_version), 3103 "%d.%d, 0x%08x", 3104 fw.eep_major, fw.eep_minor, fw.etrack_id); 3105 } else { 3106 snprintf(adapter->fw_version, 3107 sizeof(adapter->fw_version), 3108 "%d.%d.%d", 3109 fw.eep_major, fw.eep_minor, fw.eep_build); 3110 } 3111 break; 3112 } 3113 } 3114 3115 /** 3116 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3117 * 3118 * @adapter: adapter struct 3119 **/ 3120 static void igb_init_mas(struct igb_adapter *adapter) 3121 { 3122 struct e1000_hw *hw = &adapter->hw; 3123 u16 eeprom_data; 3124 3125 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3126 switch (hw->bus.func) { 3127 case E1000_FUNC_0: 3128 if (eeprom_data & IGB_MAS_ENABLE_0) { 3129 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3130 netdev_info(adapter->netdev, 3131 "MAS: Enabling Media Autosense for port %d\n", 3132 hw->bus.func); 3133 } 3134 break; 3135 case E1000_FUNC_1: 3136 if (eeprom_data & IGB_MAS_ENABLE_1) { 3137 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3138 netdev_info(adapter->netdev, 3139 "MAS: Enabling Media Autosense for port %d\n", 3140 hw->bus.func); 3141 } 3142 break; 3143 case E1000_FUNC_2: 3144 if (eeprom_data & IGB_MAS_ENABLE_2) { 3145 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3146 netdev_info(adapter->netdev, 3147 "MAS: Enabling Media Autosense for port %d\n", 3148 hw->bus.func); 3149 } 3150 break; 3151 case E1000_FUNC_3: 3152 if (eeprom_data & IGB_MAS_ENABLE_3) { 3153 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3154 netdev_info(adapter->netdev, 3155 "MAS: Enabling Media Autosense for port %d\n", 3156 hw->bus.func); 3157 } 3158 break; 3159 default: 3160 /* Shouldn't get here */ 3161 netdev_err(adapter->netdev, 3162 "MAS: Invalid port configuration, returning\n"); 3163 break; 3164 } 3165 } 3166 3167 /** 3168 * igb_init_i2c - Init I2C interface 3169 * @adapter: pointer to adapter structure 3170 **/ 3171 static s32 igb_init_i2c(struct igb_adapter *adapter) 3172 { 3173 s32 status = 0; 3174 3175 /* I2C interface supported on i350 devices */ 3176 if (adapter->hw.mac.type != e1000_i350) 3177 return 0; 3178 3179 /* Initialize the i2c bus which is controlled by the registers. 3180 * This bus will use the i2c_algo_bit structure that implements 3181 * the protocol through toggling of the 4 bits in the register. 3182 */ 3183 adapter->i2c_adap.owner = THIS_MODULE; 3184 adapter->i2c_algo = igb_i2c_algo; 3185 adapter->i2c_algo.data = adapter; 3186 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3187 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3188 strscpy(adapter->i2c_adap.name, "igb BB", 3189 sizeof(adapter->i2c_adap.name)); 3190 status = i2c_bit_add_bus(&adapter->i2c_adap); 3191 return status; 3192 } 3193 3194 /** 3195 * igb_probe - Device Initialization Routine 3196 * @pdev: PCI device information struct 3197 * @ent: entry in igb_pci_tbl 3198 * 3199 * Returns 0 on success, negative on failure 3200 * 3201 * igb_probe initializes an adapter identified by a pci_dev structure. 3202 * The OS initialization, configuring of the adapter private structure, 3203 * and a hardware reset occur. 3204 **/ 3205 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3206 { 3207 struct net_device *netdev; 3208 struct igb_adapter *adapter; 3209 struct e1000_hw *hw; 3210 u16 eeprom_data = 0; 3211 s32 ret_val; 3212 static int global_quad_port_a; /* global quad port a indication */ 3213 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3214 u8 part_str[E1000_PBANUM_LENGTH]; 3215 int err; 3216 3217 /* Catch broken hardware that put the wrong VF device ID in 3218 * the PCIe SR-IOV capability. 3219 */ 3220 if (pdev->is_virtfn) { 3221 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3222 pci_name(pdev), pdev->vendor, pdev->device); 3223 return -EINVAL; 3224 } 3225 3226 err = pci_enable_device_mem(pdev); 3227 if (err) 3228 return err; 3229 3230 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3231 if (err) { 3232 dev_err(&pdev->dev, 3233 "No usable DMA configuration, aborting\n"); 3234 goto err_dma; 3235 } 3236 3237 err = pci_request_mem_regions(pdev, igb_driver_name); 3238 if (err) 3239 goto err_pci_reg; 3240 3241 pci_set_master(pdev); 3242 pci_save_state(pdev); 3243 3244 err = -ENOMEM; 3245 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3246 IGB_MAX_TX_QUEUES); 3247 if (!netdev) 3248 goto err_alloc_etherdev; 3249 3250 SET_NETDEV_DEV(netdev, &pdev->dev); 3251 3252 pci_set_drvdata(pdev, netdev); 3253 adapter = netdev_priv(netdev); 3254 adapter->netdev = netdev; 3255 adapter->pdev = pdev; 3256 hw = &adapter->hw; 3257 hw->back = adapter; 3258 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3259 3260 err = -EIO; 3261 adapter->io_addr = pci_iomap(pdev, 0, 0); 3262 if (!adapter->io_addr) 3263 goto err_ioremap; 3264 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3265 hw->hw_addr = adapter->io_addr; 3266 3267 netdev->netdev_ops = &igb_netdev_ops; 3268 igb_set_ethtool_ops(netdev); 3269 netdev->watchdog_timeo = 5 * HZ; 3270 3271 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3272 3273 netdev->mem_start = pci_resource_start(pdev, 0); 3274 netdev->mem_end = pci_resource_end(pdev, 0); 3275 3276 /* PCI config space info */ 3277 hw->vendor_id = pdev->vendor; 3278 hw->device_id = pdev->device; 3279 hw->revision_id = pdev->revision; 3280 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3281 hw->subsystem_device_id = pdev->subsystem_device; 3282 3283 /* Copy the default MAC, PHY and NVM function pointers */ 3284 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3285 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3286 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3287 /* Initialize skew-specific constants */ 3288 err = ei->get_invariants(hw); 3289 if (err) 3290 goto err_sw_init; 3291 3292 /* setup the private structure */ 3293 err = igb_sw_init(adapter); 3294 if (err) 3295 goto err_sw_init; 3296 3297 igb_get_bus_info_pcie(hw); 3298 3299 hw->phy.autoneg_wait_to_complete = false; 3300 3301 /* Copper options */ 3302 if (hw->phy.media_type == e1000_media_type_copper) { 3303 hw->phy.mdix = AUTO_ALL_MODES; 3304 hw->phy.disable_polarity_correction = false; 3305 hw->phy.ms_type = e1000_ms_hw_default; 3306 } 3307 3308 if (igb_check_reset_block(hw)) 3309 dev_info(&pdev->dev, 3310 "PHY reset is blocked due to SOL/IDER session.\n"); 3311 3312 /* features is initialized to 0 in allocation, it might have bits 3313 * set by igb_sw_init so we should use an or instead of an 3314 * assignment. 3315 */ 3316 netdev->features |= NETIF_F_SG | 3317 NETIF_F_TSO | 3318 NETIF_F_TSO6 | 3319 NETIF_F_RXHASH | 3320 NETIF_F_RXCSUM | 3321 NETIF_F_HW_CSUM; 3322 3323 if (hw->mac.type >= e1000_82576) 3324 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3325 3326 if (hw->mac.type >= e1000_i350) 3327 netdev->features |= NETIF_F_HW_TC; 3328 3329 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3330 NETIF_F_GSO_GRE_CSUM | \ 3331 NETIF_F_GSO_IPXIP4 | \ 3332 NETIF_F_GSO_IPXIP6 | \ 3333 NETIF_F_GSO_UDP_TUNNEL | \ 3334 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3335 3336 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3337 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3338 3339 /* copy netdev features into list of user selectable features */ 3340 netdev->hw_features |= netdev->features | 3341 NETIF_F_HW_VLAN_CTAG_RX | 3342 NETIF_F_HW_VLAN_CTAG_TX | 3343 NETIF_F_RXALL; 3344 3345 if (hw->mac.type >= e1000_i350) 3346 netdev->hw_features |= NETIF_F_NTUPLE; 3347 3348 netdev->features |= NETIF_F_HIGHDMA; 3349 3350 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3351 netdev->mpls_features |= NETIF_F_HW_CSUM; 3352 netdev->hw_enc_features |= netdev->vlan_features; 3353 3354 /* set this bit last since it cannot be part of vlan_features */ 3355 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3356 NETIF_F_HW_VLAN_CTAG_RX | 3357 NETIF_F_HW_VLAN_CTAG_TX; 3358 3359 netdev->priv_flags |= IFF_SUPP_NOFCS; 3360 3361 netdev->priv_flags |= IFF_UNICAST_FLT; 3362 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3363 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3364 3365 /* MTU range: 68 - 9216 */ 3366 netdev->min_mtu = ETH_MIN_MTU; 3367 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3368 3369 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3370 3371 /* before reading the NVM, reset the controller to put the device in a 3372 * known good starting state 3373 */ 3374 hw->mac.ops.reset_hw(hw); 3375 3376 /* make sure the NVM is good , i211/i210 parts can have special NVM 3377 * that doesn't contain a checksum 3378 */ 3379 switch (hw->mac.type) { 3380 case e1000_i210: 3381 case e1000_i211: 3382 if (igb_get_flash_presence_i210(hw)) { 3383 if (hw->nvm.ops.validate(hw) < 0) { 3384 dev_err(&pdev->dev, 3385 "The NVM Checksum Is Not Valid\n"); 3386 err = -EIO; 3387 goto err_eeprom; 3388 } 3389 } 3390 break; 3391 default: 3392 if (hw->nvm.ops.validate(hw) < 0) { 3393 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3394 err = -EIO; 3395 goto err_eeprom; 3396 } 3397 break; 3398 } 3399 3400 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3401 /* copy the MAC address out of the NVM */ 3402 if (hw->mac.ops.read_mac_addr(hw)) 3403 dev_err(&pdev->dev, "NVM Read Error\n"); 3404 } 3405 3406 eth_hw_addr_set(netdev, hw->mac.addr); 3407 3408 if (!is_valid_ether_addr(netdev->dev_addr)) { 3409 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3410 err = -EIO; 3411 goto err_eeprom; 3412 } 3413 3414 igb_set_default_mac_filter(adapter); 3415 3416 /* get firmware version for ethtool -i */ 3417 igb_set_fw_version(adapter); 3418 3419 /* configure RXPBSIZE and TXPBSIZE */ 3420 if (hw->mac.type == e1000_i210) { 3421 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3422 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3423 } 3424 3425 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3426 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3427 3428 INIT_WORK(&adapter->reset_task, igb_reset_task); 3429 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3430 3431 /* Initialize link properties that are user-changeable */ 3432 adapter->fc_autoneg = true; 3433 hw->mac.autoneg = true; 3434 hw->phy.autoneg_advertised = 0x2f; 3435 3436 hw->fc.requested_mode = e1000_fc_default; 3437 hw->fc.current_mode = e1000_fc_default; 3438 3439 igb_validate_mdi_setting(hw); 3440 3441 /* By default, support wake on port A */ 3442 if (hw->bus.func == 0) 3443 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3444 3445 /* Check the NVM for wake support on non-port A ports */ 3446 if (hw->mac.type >= e1000_82580) 3447 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3448 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3449 &eeprom_data); 3450 else if (hw->bus.func == 1) 3451 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3452 3453 if (eeprom_data & IGB_EEPROM_APME) 3454 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3455 3456 /* now that we have the eeprom settings, apply the special cases where 3457 * the eeprom may be wrong or the board simply won't support wake on 3458 * lan on a particular port 3459 */ 3460 switch (pdev->device) { 3461 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3462 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3463 break; 3464 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3465 case E1000_DEV_ID_82576_FIBER: 3466 case E1000_DEV_ID_82576_SERDES: 3467 /* Wake events only supported on port A for dual fiber 3468 * regardless of eeprom setting 3469 */ 3470 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3471 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3472 break; 3473 case E1000_DEV_ID_82576_QUAD_COPPER: 3474 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3475 /* if quad port adapter, disable WoL on all but port A */ 3476 if (global_quad_port_a != 0) 3477 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3478 else 3479 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3480 /* Reset for multiple quad port adapters */ 3481 if (++global_quad_port_a == 4) 3482 global_quad_port_a = 0; 3483 break; 3484 default: 3485 /* If the device can't wake, don't set software support */ 3486 if (!device_can_wakeup(&adapter->pdev->dev)) 3487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3488 } 3489 3490 /* initialize the wol settings based on the eeprom settings */ 3491 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3492 adapter->wol |= E1000_WUFC_MAG; 3493 3494 /* Some vendors want WoL disabled by default, but still supported */ 3495 if ((hw->mac.type == e1000_i350) && 3496 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3497 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3498 adapter->wol = 0; 3499 } 3500 3501 /* Some vendors want the ability to Use the EEPROM setting as 3502 * enable/disable only, and not for capability 3503 */ 3504 if (((hw->mac.type == e1000_i350) || 3505 (hw->mac.type == e1000_i354)) && 3506 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3508 adapter->wol = 0; 3509 } 3510 if (hw->mac.type == e1000_i350) { 3511 if (((pdev->subsystem_device == 0x5001) || 3512 (pdev->subsystem_device == 0x5002)) && 3513 (hw->bus.func == 0)) { 3514 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3515 adapter->wol = 0; 3516 } 3517 if (pdev->subsystem_device == 0x1F52) 3518 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3519 } 3520 3521 device_set_wakeup_enable(&adapter->pdev->dev, 3522 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3523 3524 /* reset the hardware with the new settings */ 3525 igb_reset(adapter); 3526 3527 /* Init the I2C interface */ 3528 err = igb_init_i2c(adapter); 3529 if (err) { 3530 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3531 goto err_eeprom; 3532 } 3533 3534 /* let the f/w know that the h/w is now under the control of the 3535 * driver. 3536 */ 3537 igb_get_hw_control(adapter); 3538 3539 strcpy(netdev->name, "eth%d"); 3540 err = register_netdev(netdev); 3541 if (err) 3542 goto err_register; 3543 3544 /* carrier off reporting is important to ethtool even BEFORE open */ 3545 netif_carrier_off(netdev); 3546 3547 #ifdef CONFIG_IGB_DCA 3548 if (dca_add_requester(&pdev->dev) == 0) { 3549 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3550 dev_info(&pdev->dev, "DCA enabled\n"); 3551 igb_setup_dca(adapter); 3552 } 3553 3554 #endif 3555 #ifdef CONFIG_IGB_HWMON 3556 /* Initialize the thermal sensor on i350 devices. */ 3557 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3558 u16 ets_word; 3559 3560 /* Read the NVM to determine if this i350 device supports an 3561 * external thermal sensor. 3562 */ 3563 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3564 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3565 adapter->ets = true; 3566 else 3567 adapter->ets = false; 3568 /* Only enable I2C bit banging if an external thermal 3569 * sensor is supported. 3570 */ 3571 if (adapter->ets) 3572 igb_set_i2c_bb(hw); 3573 hw->mac.ops.init_thermal_sensor_thresh(hw); 3574 if (igb_sysfs_init(adapter)) 3575 dev_err(&pdev->dev, 3576 "failed to allocate sysfs resources\n"); 3577 } else { 3578 adapter->ets = false; 3579 } 3580 #endif 3581 /* Check if Media Autosense is enabled */ 3582 adapter->ei = *ei; 3583 if (hw->dev_spec._82575.mas_capable) 3584 igb_init_mas(adapter); 3585 3586 /* do hw tstamp init after resetting */ 3587 igb_ptp_init(adapter); 3588 3589 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3590 /* print bus type/speed/width info, not applicable to i354 */ 3591 if (hw->mac.type != e1000_i354) { 3592 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3593 netdev->name, 3594 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3595 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3596 "unknown"), 3597 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3598 "Width x4" : 3599 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3600 "Width x2" : 3601 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3602 "Width x1" : "unknown"), netdev->dev_addr); 3603 } 3604 3605 if ((hw->mac.type == e1000_82576 && 3606 rd32(E1000_EECD) & E1000_EECD_PRES) || 3607 (hw->mac.type >= e1000_i210 || 3608 igb_get_flash_presence_i210(hw))) { 3609 ret_val = igb_read_part_string(hw, part_str, 3610 E1000_PBANUM_LENGTH); 3611 } else { 3612 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3613 } 3614 3615 if (ret_val) 3616 strcpy(part_str, "Unknown"); 3617 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3618 dev_info(&pdev->dev, 3619 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3620 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3621 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3622 adapter->num_rx_queues, adapter->num_tx_queues); 3623 if (hw->phy.media_type == e1000_media_type_copper) { 3624 switch (hw->mac.type) { 3625 case e1000_i350: 3626 case e1000_i210: 3627 case e1000_i211: 3628 /* Enable EEE for internal copper PHY devices */ 3629 err = igb_set_eee_i350(hw, true, true); 3630 if ((!err) && 3631 (!hw->dev_spec._82575.eee_disable)) { 3632 adapter->eee_advert = 3633 MDIO_EEE_100TX | MDIO_EEE_1000T; 3634 adapter->flags |= IGB_FLAG_EEE; 3635 } 3636 break; 3637 case e1000_i354: 3638 if ((rd32(E1000_CTRL_EXT) & 3639 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3640 err = igb_set_eee_i354(hw, true, true); 3641 if ((!err) && 3642 (!hw->dev_spec._82575.eee_disable)) { 3643 adapter->eee_advert = 3644 MDIO_EEE_100TX | MDIO_EEE_1000T; 3645 adapter->flags |= IGB_FLAG_EEE; 3646 } 3647 } 3648 break; 3649 default: 3650 break; 3651 } 3652 } 3653 3654 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3655 3656 pm_runtime_put_noidle(&pdev->dev); 3657 return 0; 3658 3659 err_register: 3660 igb_release_hw_control(adapter); 3661 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3662 err_eeprom: 3663 if (!igb_check_reset_block(hw)) 3664 igb_reset_phy(hw); 3665 3666 if (hw->flash_address) 3667 iounmap(hw->flash_address); 3668 err_sw_init: 3669 kfree(adapter->mac_table); 3670 kfree(adapter->shadow_vfta); 3671 igb_clear_interrupt_scheme(adapter); 3672 #ifdef CONFIG_PCI_IOV 3673 igb_disable_sriov(pdev, false); 3674 #endif 3675 pci_iounmap(pdev, adapter->io_addr); 3676 err_ioremap: 3677 free_netdev(netdev); 3678 err_alloc_etherdev: 3679 pci_release_mem_regions(pdev); 3680 err_pci_reg: 3681 err_dma: 3682 pci_disable_device(pdev); 3683 return err; 3684 } 3685 3686 #ifdef CONFIG_PCI_IOV 3687 static int igb_sriov_reinit(struct pci_dev *dev) 3688 { 3689 struct net_device *netdev = pci_get_drvdata(dev); 3690 struct igb_adapter *adapter = netdev_priv(netdev); 3691 struct pci_dev *pdev = adapter->pdev; 3692 3693 rtnl_lock(); 3694 3695 if (netif_running(netdev)) 3696 igb_close(netdev); 3697 else 3698 igb_reset(adapter); 3699 3700 igb_clear_interrupt_scheme(adapter); 3701 3702 igb_init_queue_configuration(adapter); 3703 3704 if (igb_init_interrupt_scheme(adapter, true)) { 3705 rtnl_unlock(); 3706 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3707 return -ENOMEM; 3708 } 3709 3710 if (netif_running(netdev)) 3711 igb_open(netdev); 3712 3713 rtnl_unlock(); 3714 3715 return 0; 3716 } 3717 3718 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3719 { 3720 struct net_device *netdev = pci_get_drvdata(pdev); 3721 struct igb_adapter *adapter = netdev_priv(netdev); 3722 struct e1000_hw *hw = &adapter->hw; 3723 unsigned long flags; 3724 3725 /* reclaim resources allocated to VFs */ 3726 if (adapter->vf_data) { 3727 /* disable iov and allow time for transactions to clear */ 3728 if (pci_vfs_assigned(pdev)) { 3729 dev_warn(&pdev->dev, 3730 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3731 return -EPERM; 3732 } else { 3733 pci_disable_sriov(pdev); 3734 msleep(500); 3735 } 3736 spin_lock_irqsave(&adapter->vfs_lock, flags); 3737 kfree(adapter->vf_mac_list); 3738 adapter->vf_mac_list = NULL; 3739 kfree(adapter->vf_data); 3740 adapter->vf_data = NULL; 3741 adapter->vfs_allocated_count = 0; 3742 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3743 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3744 wrfl(); 3745 msleep(100); 3746 dev_info(&pdev->dev, "IOV Disabled\n"); 3747 3748 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3749 adapter->flags |= IGB_FLAG_DMAC; 3750 } 3751 3752 return reinit ? igb_sriov_reinit(pdev) : 0; 3753 } 3754 3755 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3756 { 3757 struct net_device *netdev = pci_get_drvdata(pdev); 3758 struct igb_adapter *adapter = netdev_priv(netdev); 3759 int old_vfs = pci_num_vf(pdev); 3760 struct vf_mac_filter *mac_list; 3761 int err = 0; 3762 int num_vf_mac_filters, i; 3763 3764 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3765 err = -EPERM; 3766 goto out; 3767 } 3768 if (!num_vfs) 3769 goto out; 3770 3771 if (old_vfs) { 3772 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3773 old_vfs, max_vfs); 3774 adapter->vfs_allocated_count = old_vfs; 3775 } else 3776 adapter->vfs_allocated_count = num_vfs; 3777 3778 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3779 sizeof(struct vf_data_storage), GFP_KERNEL); 3780 3781 /* if allocation failed then we do not support SR-IOV */ 3782 if (!adapter->vf_data) { 3783 adapter->vfs_allocated_count = 0; 3784 err = -ENOMEM; 3785 goto out; 3786 } 3787 3788 /* Due to the limited number of RAR entries calculate potential 3789 * number of MAC filters available for the VFs. Reserve entries 3790 * for PF default MAC, PF MAC filters and at least one RAR entry 3791 * for each VF for VF MAC. 3792 */ 3793 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3794 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3795 adapter->vfs_allocated_count); 3796 3797 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3798 sizeof(struct vf_mac_filter), 3799 GFP_KERNEL); 3800 3801 mac_list = adapter->vf_mac_list; 3802 INIT_LIST_HEAD(&adapter->vf_macs.l); 3803 3804 if (adapter->vf_mac_list) { 3805 /* Initialize list of VF MAC filters */ 3806 for (i = 0; i < num_vf_mac_filters; i++) { 3807 mac_list->vf = -1; 3808 mac_list->free = true; 3809 list_add(&mac_list->l, &adapter->vf_macs.l); 3810 mac_list++; 3811 } 3812 } else { 3813 /* If we could not allocate memory for the VF MAC filters 3814 * we can continue without this feature but warn user. 3815 */ 3816 dev_err(&pdev->dev, 3817 "Unable to allocate memory for VF MAC filter list\n"); 3818 } 3819 3820 dev_info(&pdev->dev, "%d VFs allocated\n", 3821 adapter->vfs_allocated_count); 3822 for (i = 0; i < adapter->vfs_allocated_count; i++) 3823 igb_vf_configure(adapter, i); 3824 3825 /* DMA Coalescing is not supported in IOV mode. */ 3826 adapter->flags &= ~IGB_FLAG_DMAC; 3827 3828 if (reinit) { 3829 err = igb_sriov_reinit(pdev); 3830 if (err) 3831 goto err_out; 3832 } 3833 3834 /* only call pci_enable_sriov() if no VFs are allocated already */ 3835 if (!old_vfs) { 3836 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3837 if (err) 3838 goto err_out; 3839 } 3840 3841 goto out; 3842 3843 err_out: 3844 kfree(adapter->vf_mac_list); 3845 adapter->vf_mac_list = NULL; 3846 kfree(adapter->vf_data); 3847 adapter->vf_data = NULL; 3848 adapter->vfs_allocated_count = 0; 3849 out: 3850 return err; 3851 } 3852 3853 #endif 3854 /** 3855 * igb_remove_i2c - Cleanup I2C interface 3856 * @adapter: pointer to adapter structure 3857 **/ 3858 static void igb_remove_i2c(struct igb_adapter *adapter) 3859 { 3860 /* free the adapter bus structure */ 3861 i2c_del_adapter(&adapter->i2c_adap); 3862 } 3863 3864 /** 3865 * igb_remove - Device Removal Routine 3866 * @pdev: PCI device information struct 3867 * 3868 * igb_remove is called by the PCI subsystem to alert the driver 3869 * that it should release a PCI device. The could be caused by a 3870 * Hot-Plug event, or because the driver is going to be removed from 3871 * memory. 3872 **/ 3873 static void igb_remove(struct pci_dev *pdev) 3874 { 3875 struct net_device *netdev = pci_get_drvdata(pdev); 3876 struct igb_adapter *adapter = netdev_priv(netdev); 3877 struct e1000_hw *hw = &adapter->hw; 3878 3879 pm_runtime_get_noresume(&pdev->dev); 3880 #ifdef CONFIG_IGB_HWMON 3881 igb_sysfs_exit(adapter); 3882 #endif 3883 igb_remove_i2c(adapter); 3884 igb_ptp_stop(adapter); 3885 /* The watchdog timer may be rescheduled, so explicitly 3886 * disable watchdog from being rescheduled. 3887 */ 3888 set_bit(__IGB_DOWN, &adapter->state); 3889 timer_delete_sync(&adapter->watchdog_timer); 3890 timer_delete_sync(&adapter->phy_info_timer); 3891 3892 cancel_work_sync(&adapter->reset_task); 3893 cancel_work_sync(&adapter->watchdog_task); 3894 3895 #ifdef CONFIG_IGB_DCA 3896 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3897 dev_info(&pdev->dev, "DCA disabled\n"); 3898 dca_remove_requester(&pdev->dev); 3899 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3900 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3901 } 3902 #endif 3903 3904 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3905 * would have already happened in close and is redundant. 3906 */ 3907 igb_release_hw_control(adapter); 3908 3909 #ifdef CONFIG_PCI_IOV 3910 igb_disable_sriov(pdev, false); 3911 #endif 3912 3913 unregister_netdev(netdev); 3914 3915 igb_clear_interrupt_scheme(adapter); 3916 3917 pci_iounmap(pdev, adapter->io_addr); 3918 if (hw->flash_address) 3919 iounmap(hw->flash_address); 3920 pci_release_mem_regions(pdev); 3921 3922 kfree(adapter->mac_table); 3923 kfree(adapter->shadow_vfta); 3924 free_netdev(netdev); 3925 3926 pci_disable_device(pdev); 3927 } 3928 3929 /** 3930 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3931 * @adapter: board private structure to initialize 3932 * 3933 * This function initializes the vf specific data storage and then attempts to 3934 * allocate the VFs. The reason for ordering it this way is because it is much 3935 * more expensive time wise to disable SR-IOV than it is to allocate and free 3936 * the memory for the VFs. 3937 **/ 3938 static void igb_probe_vfs(struct igb_adapter *adapter) 3939 { 3940 #ifdef CONFIG_PCI_IOV 3941 struct pci_dev *pdev = adapter->pdev; 3942 struct e1000_hw *hw = &adapter->hw; 3943 3944 /* Virtualization features not supported on i210 and 82580 family. */ 3945 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3946 (hw->mac.type == e1000_82580)) 3947 return; 3948 3949 /* Of the below we really only want the effect of getting 3950 * IGB_FLAG_HAS_MSIX set (if available), without which 3951 * igb_enable_sriov() has no effect. 3952 */ 3953 igb_set_interrupt_capability(adapter, true); 3954 igb_reset_interrupt_capability(adapter); 3955 3956 pci_sriov_set_totalvfs(pdev, 7); 3957 igb_enable_sriov(pdev, max_vfs, false); 3958 3959 #endif /* CONFIG_PCI_IOV */ 3960 } 3961 3962 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3963 { 3964 struct e1000_hw *hw = &adapter->hw; 3965 unsigned int max_rss_queues; 3966 3967 /* Determine the maximum number of RSS queues supported. */ 3968 switch (hw->mac.type) { 3969 case e1000_i211: 3970 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3971 break; 3972 case e1000_82575: 3973 case e1000_i210: 3974 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3975 break; 3976 case e1000_i350: 3977 /* I350 cannot do RSS and SR-IOV at the same time */ 3978 if (!!adapter->vfs_allocated_count) { 3979 max_rss_queues = 1; 3980 break; 3981 } 3982 fallthrough; 3983 case e1000_82576: 3984 if (!!adapter->vfs_allocated_count) { 3985 max_rss_queues = 2; 3986 break; 3987 } 3988 fallthrough; 3989 case e1000_82580: 3990 case e1000_i354: 3991 default: 3992 max_rss_queues = IGB_MAX_RX_QUEUES; 3993 break; 3994 } 3995 3996 return max_rss_queues; 3997 } 3998 3999 static void igb_init_queue_configuration(struct igb_adapter *adapter) 4000 { 4001 u32 max_rss_queues; 4002 4003 max_rss_queues = igb_get_max_rss_queues(adapter); 4004 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4005 4006 igb_set_flag_queue_pairs(adapter, max_rss_queues); 4007 } 4008 4009 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4010 const u32 max_rss_queues) 4011 { 4012 struct e1000_hw *hw = &adapter->hw; 4013 4014 /* Determine if we need to pair queues. */ 4015 switch (hw->mac.type) { 4016 case e1000_82575: 4017 case e1000_i211: 4018 /* Device supports enough interrupts without queue pairing. */ 4019 break; 4020 case e1000_82576: 4021 case e1000_82580: 4022 case e1000_i350: 4023 case e1000_i354: 4024 case e1000_i210: 4025 default: 4026 /* If rss_queues > half of max_rss_queues, pair the queues in 4027 * order to conserve interrupts due to limited supply. 4028 */ 4029 if (adapter->rss_queues > (max_rss_queues / 2)) 4030 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4031 else 4032 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4033 break; 4034 } 4035 } 4036 4037 /** 4038 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4039 * @adapter: board private structure to initialize 4040 * 4041 * igb_sw_init initializes the Adapter private data structure. 4042 * Fields are initialized based on PCI device information and 4043 * OS network device settings (MTU size). 4044 **/ 4045 static int igb_sw_init(struct igb_adapter *adapter) 4046 { 4047 struct e1000_hw *hw = &adapter->hw; 4048 struct net_device *netdev = adapter->netdev; 4049 struct pci_dev *pdev = adapter->pdev; 4050 4051 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4052 4053 /* set default ring sizes */ 4054 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4055 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4056 4057 /* set default ITR values */ 4058 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4059 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4060 4061 /* set default work limits */ 4062 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4063 4064 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4065 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4066 4067 spin_lock_init(&adapter->nfc_lock); 4068 spin_lock_init(&adapter->stats64_lock); 4069 4070 /* init spinlock to avoid concurrency of VF resources */ 4071 spin_lock_init(&adapter->vfs_lock); 4072 #ifdef CONFIG_PCI_IOV 4073 switch (hw->mac.type) { 4074 case e1000_82576: 4075 case e1000_i350: 4076 if (max_vfs > 7) { 4077 dev_warn(&pdev->dev, 4078 "Maximum of 7 VFs per PF, using max\n"); 4079 max_vfs = adapter->vfs_allocated_count = 7; 4080 } else 4081 adapter->vfs_allocated_count = max_vfs; 4082 if (adapter->vfs_allocated_count) 4083 dev_warn(&pdev->dev, 4084 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4085 break; 4086 default: 4087 break; 4088 } 4089 #endif /* CONFIG_PCI_IOV */ 4090 4091 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4092 adapter->flags |= IGB_FLAG_HAS_MSIX; 4093 4094 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4095 sizeof(struct igb_mac_addr), 4096 GFP_KERNEL); 4097 if (!adapter->mac_table) 4098 return -ENOMEM; 4099 4100 igb_probe_vfs(adapter); 4101 4102 igb_init_queue_configuration(adapter); 4103 4104 /* Setup and initialize a copy of the hw vlan table array */ 4105 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4106 GFP_KERNEL); 4107 if (!adapter->shadow_vfta) 4108 return -ENOMEM; 4109 4110 /* This call may decrease the number of queues */ 4111 if (igb_init_interrupt_scheme(adapter, true)) { 4112 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4113 return -ENOMEM; 4114 } 4115 4116 /* Explicitly disable IRQ since the NIC can be in any state. */ 4117 igb_irq_disable(adapter); 4118 4119 if (hw->mac.type >= e1000_i350) 4120 adapter->flags &= ~IGB_FLAG_DMAC; 4121 4122 set_bit(__IGB_DOWN, &adapter->state); 4123 return 0; 4124 } 4125 4126 /** 4127 * __igb_open - Called when a network interface is made active 4128 * @netdev: network interface device structure 4129 * @resuming: indicates whether we are in a resume call 4130 * 4131 * Returns 0 on success, negative value on failure 4132 * 4133 * The open entry point is called when a network interface is made 4134 * active by the system (IFF_UP). At this point all resources needed 4135 * for transmit and receive operations are allocated, the interrupt 4136 * handler is registered with the OS, the watchdog timer is started, 4137 * and the stack is notified that the interface is ready. 4138 **/ 4139 static int __igb_open(struct net_device *netdev, bool resuming) 4140 { 4141 struct igb_adapter *adapter = netdev_priv(netdev); 4142 struct pci_dev *pdev = adapter->pdev; 4143 struct e1000_hw *hw = &adapter->hw; 4144 struct napi_struct *napi; 4145 int err; 4146 int i; 4147 4148 /* disallow open during test */ 4149 if (test_bit(__IGB_TESTING, &adapter->state)) { 4150 WARN_ON(resuming); 4151 return -EBUSY; 4152 } 4153 4154 if (!resuming) 4155 pm_runtime_get_sync(&pdev->dev); 4156 4157 netif_carrier_off(netdev); 4158 4159 /* allocate transmit descriptors */ 4160 err = igb_setup_all_tx_resources(adapter); 4161 if (err) 4162 goto err_setup_tx; 4163 4164 /* allocate receive descriptors */ 4165 err = igb_setup_all_rx_resources(adapter); 4166 if (err) 4167 goto err_setup_rx; 4168 4169 igb_power_up_link(adapter); 4170 4171 /* before we allocate an interrupt, we must be ready to handle it. 4172 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4173 * as soon as we call pci_request_irq, so we have to setup our 4174 * clean_rx handler before we do so. 4175 */ 4176 igb_configure(adapter); 4177 4178 err = igb_request_irq(adapter); 4179 if (err) 4180 goto err_req_irq; 4181 4182 /* Notify the stack of the actual queue counts. */ 4183 err = netif_set_real_num_tx_queues(adapter->netdev, 4184 adapter->num_tx_queues); 4185 if (err) 4186 goto err_set_queues; 4187 4188 err = netif_set_real_num_rx_queues(adapter->netdev, 4189 adapter->num_rx_queues); 4190 if (err) 4191 goto err_set_queues; 4192 4193 /* From here on the code is the same as igb_up() */ 4194 clear_bit(__IGB_DOWN, &adapter->state); 4195 4196 for (i = 0; i < adapter->num_q_vectors; i++) { 4197 napi = &adapter->q_vector[i]->napi; 4198 napi_enable(napi); 4199 igb_set_queue_napi(adapter, i, napi); 4200 } 4201 4202 /* Clear any pending interrupts. */ 4203 rd32(E1000_TSICR); 4204 rd32(E1000_ICR); 4205 4206 igb_irq_enable(adapter); 4207 4208 /* notify VFs that reset has been completed */ 4209 if (adapter->vfs_allocated_count) { 4210 u32 reg_data = rd32(E1000_CTRL_EXT); 4211 4212 reg_data |= E1000_CTRL_EXT_PFRSTD; 4213 wr32(E1000_CTRL_EXT, reg_data); 4214 } 4215 4216 netif_tx_start_all_queues(netdev); 4217 4218 if (!resuming) 4219 pm_runtime_put(&pdev->dev); 4220 4221 /* start the watchdog. */ 4222 hw->mac.get_link_status = 1; 4223 schedule_work(&adapter->watchdog_task); 4224 4225 return 0; 4226 4227 err_set_queues: 4228 igb_free_irq(adapter); 4229 err_req_irq: 4230 igb_release_hw_control(adapter); 4231 igb_power_down_link(adapter); 4232 igb_free_all_rx_resources(adapter); 4233 err_setup_rx: 4234 igb_free_all_tx_resources(adapter); 4235 err_setup_tx: 4236 igb_reset(adapter); 4237 if (!resuming) 4238 pm_runtime_put(&pdev->dev); 4239 4240 return err; 4241 } 4242 4243 int igb_open(struct net_device *netdev) 4244 { 4245 return __igb_open(netdev, false); 4246 } 4247 4248 /** 4249 * __igb_close - Disables a network interface 4250 * @netdev: network interface device structure 4251 * @suspending: indicates we are in a suspend call 4252 * 4253 * Returns 0, this is not allowed to fail 4254 * 4255 * The close entry point is called when an interface is de-activated 4256 * by the OS. The hardware is still under the driver's control, but 4257 * needs to be disabled. A global MAC reset is issued to stop the 4258 * hardware, and all transmit and receive resources are freed. 4259 **/ 4260 static int __igb_close(struct net_device *netdev, bool suspending) 4261 { 4262 struct igb_adapter *adapter = netdev_priv(netdev); 4263 struct pci_dev *pdev = adapter->pdev; 4264 4265 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4266 4267 if (!suspending) 4268 pm_runtime_get_sync(&pdev->dev); 4269 4270 igb_down(adapter); 4271 igb_free_irq(adapter); 4272 4273 igb_free_all_tx_resources(adapter); 4274 igb_free_all_rx_resources(adapter); 4275 4276 if (!suspending) 4277 pm_runtime_put_sync(&pdev->dev); 4278 return 0; 4279 } 4280 4281 int igb_close(struct net_device *netdev) 4282 { 4283 if (netif_device_present(netdev) || netdev->dismantle) 4284 return __igb_close(netdev, false); 4285 return 0; 4286 } 4287 4288 /** 4289 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4290 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4291 * 4292 * Return 0 on success, negative on failure 4293 **/ 4294 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4295 { 4296 struct device *dev = tx_ring->dev; 4297 int size; 4298 4299 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4300 4301 tx_ring->tx_buffer_info = vmalloc(size); 4302 if (!tx_ring->tx_buffer_info) 4303 goto err; 4304 4305 /* round up to nearest 4K */ 4306 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4307 tx_ring->size = ALIGN(tx_ring->size, 4096); 4308 4309 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4310 &tx_ring->dma, GFP_KERNEL); 4311 if (!tx_ring->desc) 4312 goto err; 4313 4314 tx_ring->next_to_use = 0; 4315 tx_ring->next_to_clean = 0; 4316 4317 return 0; 4318 4319 err: 4320 vfree(tx_ring->tx_buffer_info); 4321 tx_ring->tx_buffer_info = NULL; 4322 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4323 return -ENOMEM; 4324 } 4325 4326 /** 4327 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4328 * (Descriptors) for all queues 4329 * @adapter: board private structure 4330 * 4331 * Return 0 on success, negative on failure 4332 **/ 4333 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4334 { 4335 struct pci_dev *pdev = adapter->pdev; 4336 int i, err = 0; 4337 4338 for (i = 0; i < adapter->num_tx_queues; i++) { 4339 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4340 if (err) { 4341 dev_err(&pdev->dev, 4342 "Allocation for Tx Queue %u failed\n", i); 4343 for (i--; i >= 0; i--) 4344 igb_free_tx_resources(adapter->tx_ring[i]); 4345 break; 4346 } 4347 } 4348 4349 return err; 4350 } 4351 4352 /** 4353 * igb_setup_tctl - configure the transmit control registers 4354 * @adapter: Board private structure 4355 **/ 4356 void igb_setup_tctl(struct igb_adapter *adapter) 4357 { 4358 struct e1000_hw *hw = &adapter->hw; 4359 u32 tctl; 4360 4361 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4362 wr32(E1000_TXDCTL(0), 0); 4363 4364 /* Program the Transmit Control Register */ 4365 tctl = rd32(E1000_TCTL); 4366 tctl &= ~E1000_TCTL_CT; 4367 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4368 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4369 4370 igb_config_collision_dist(hw); 4371 4372 /* Enable transmits */ 4373 tctl |= E1000_TCTL_EN; 4374 4375 wr32(E1000_TCTL, tctl); 4376 } 4377 4378 /** 4379 * igb_configure_tx_ring - Configure transmit ring after Reset 4380 * @adapter: board private structure 4381 * @ring: tx ring to configure 4382 * 4383 * Configure a transmit ring after a reset. 4384 **/ 4385 void igb_configure_tx_ring(struct igb_adapter *adapter, 4386 struct igb_ring *ring) 4387 { 4388 struct e1000_hw *hw = &adapter->hw; 4389 u32 txdctl = 0; 4390 u64 tdba = ring->dma; 4391 int reg_idx = ring->reg_idx; 4392 4393 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4394 4395 wr32(E1000_TDLEN(reg_idx), 4396 ring->count * sizeof(union e1000_adv_tx_desc)); 4397 wr32(E1000_TDBAL(reg_idx), 4398 tdba & 0x00000000ffffffffULL); 4399 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4400 4401 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4402 wr32(E1000_TDH(reg_idx), 0); 4403 writel(0, ring->tail); 4404 4405 txdctl |= IGB_TX_PTHRESH; 4406 txdctl |= IGB_TX_HTHRESH << 8; 4407 txdctl |= IGB_TX_WTHRESH << 16; 4408 4409 /* reinitialize tx_buffer_info */ 4410 memset(ring->tx_buffer_info, 0, 4411 sizeof(struct igb_tx_buffer) * ring->count); 4412 4413 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4414 wr32(E1000_TXDCTL(reg_idx), txdctl); 4415 } 4416 4417 /** 4418 * igb_configure_tx - Configure transmit Unit after Reset 4419 * @adapter: board private structure 4420 * 4421 * Configure the Tx unit of the MAC after a reset. 4422 **/ 4423 static void igb_configure_tx(struct igb_adapter *adapter) 4424 { 4425 struct e1000_hw *hw = &adapter->hw; 4426 int i; 4427 4428 /* disable the queues */ 4429 for (i = 0; i < adapter->num_tx_queues; i++) 4430 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4431 4432 wrfl(); 4433 usleep_range(10000, 20000); 4434 4435 for (i = 0; i < adapter->num_tx_queues; i++) 4436 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4437 } 4438 4439 /** 4440 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4441 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4442 * 4443 * Returns 0 on success, negative on failure 4444 **/ 4445 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4446 { 4447 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4448 struct device *dev = rx_ring->dev; 4449 int size, res; 4450 4451 /* XDP RX-queue info */ 4452 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4453 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4454 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4455 rx_ring->queue_index, 0); 4456 if (res < 0) { 4457 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4458 rx_ring->queue_index); 4459 return res; 4460 } 4461 4462 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4463 4464 rx_ring->rx_buffer_info = vmalloc(size); 4465 if (!rx_ring->rx_buffer_info) 4466 goto err; 4467 4468 /* Round up to nearest 4K */ 4469 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4470 rx_ring->size = ALIGN(rx_ring->size, 4096); 4471 4472 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4473 &rx_ring->dma, GFP_KERNEL); 4474 if (!rx_ring->desc) 4475 goto err; 4476 4477 rx_ring->next_to_alloc = 0; 4478 rx_ring->next_to_clean = 0; 4479 rx_ring->next_to_use = 0; 4480 4481 rx_ring->xdp_prog = adapter->xdp_prog; 4482 4483 return 0; 4484 4485 err: 4486 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4487 vfree(rx_ring->rx_buffer_info); 4488 rx_ring->rx_buffer_info = NULL; 4489 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4490 return -ENOMEM; 4491 } 4492 4493 /** 4494 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4495 * (Descriptors) for all queues 4496 * @adapter: board private structure 4497 * 4498 * Return 0 on success, negative on failure 4499 **/ 4500 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4501 { 4502 struct pci_dev *pdev = adapter->pdev; 4503 int i, err = 0; 4504 4505 for (i = 0; i < adapter->num_rx_queues; i++) { 4506 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4507 if (err) { 4508 dev_err(&pdev->dev, 4509 "Allocation for Rx Queue %u failed\n", i); 4510 for (i--; i >= 0; i--) 4511 igb_free_rx_resources(adapter->rx_ring[i]); 4512 break; 4513 } 4514 } 4515 4516 return err; 4517 } 4518 4519 /** 4520 * igb_setup_mrqc - configure the multiple receive queue control registers 4521 * @adapter: Board private structure 4522 **/ 4523 static void igb_setup_mrqc(struct igb_adapter *adapter) 4524 { 4525 struct e1000_hw *hw = &adapter->hw; 4526 u32 mrqc, rxcsum; 4527 u32 j, num_rx_queues; 4528 u32 rss_key[10]; 4529 4530 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4531 for (j = 0; j < 10; j++) 4532 wr32(E1000_RSSRK(j), rss_key[j]); 4533 4534 num_rx_queues = adapter->rss_queues; 4535 4536 switch (hw->mac.type) { 4537 case e1000_82576: 4538 /* 82576 supports 2 RSS queues for SR-IOV */ 4539 if (adapter->vfs_allocated_count) 4540 num_rx_queues = 2; 4541 break; 4542 default: 4543 break; 4544 } 4545 4546 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4547 for (j = 0; j < IGB_RETA_SIZE; j++) 4548 adapter->rss_indir_tbl[j] = 4549 (j * num_rx_queues) / IGB_RETA_SIZE; 4550 adapter->rss_indir_tbl_init = num_rx_queues; 4551 } 4552 igb_write_rss_indir_tbl(adapter); 4553 4554 /* Disable raw packet checksumming so that RSS hash is placed in 4555 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4556 * offloads as they are enabled by default 4557 */ 4558 rxcsum = rd32(E1000_RXCSUM); 4559 rxcsum |= E1000_RXCSUM_PCSD; 4560 4561 if (adapter->hw.mac.type >= e1000_82576) 4562 /* Enable Receive Checksum Offload for SCTP */ 4563 rxcsum |= E1000_RXCSUM_CRCOFL; 4564 4565 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4566 wr32(E1000_RXCSUM, rxcsum); 4567 4568 /* Generate RSS hash based on packet types, TCP/UDP 4569 * port numbers and/or IPv4/v6 src and dst addresses 4570 */ 4571 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4572 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4573 E1000_MRQC_RSS_FIELD_IPV6 | 4574 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4575 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4576 4577 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4578 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4579 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4580 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4581 4582 /* If VMDq is enabled then we set the appropriate mode for that, else 4583 * we default to RSS so that an RSS hash is calculated per packet even 4584 * if we are only using one queue 4585 */ 4586 if (adapter->vfs_allocated_count) { 4587 if (hw->mac.type > e1000_82575) { 4588 /* Set the default pool for the PF's first queue */ 4589 u32 vtctl = rd32(E1000_VT_CTL); 4590 4591 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4592 E1000_VT_CTL_DISABLE_DEF_POOL); 4593 vtctl |= adapter->vfs_allocated_count << 4594 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4595 wr32(E1000_VT_CTL, vtctl); 4596 } 4597 if (adapter->rss_queues > 1) 4598 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4599 else 4600 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4601 } else { 4602 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4603 } 4604 igb_vmm_control(adapter); 4605 4606 wr32(E1000_MRQC, mrqc); 4607 } 4608 4609 /** 4610 * igb_setup_rctl - configure the receive control registers 4611 * @adapter: Board private structure 4612 **/ 4613 void igb_setup_rctl(struct igb_adapter *adapter) 4614 { 4615 struct e1000_hw *hw = &adapter->hw; 4616 u32 rctl; 4617 4618 rctl = rd32(E1000_RCTL); 4619 4620 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4621 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4622 4623 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4624 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4625 4626 /* enable stripping of CRC. It's unlikely this will break BMC 4627 * redirection as it did with e1000. Newer features require 4628 * that the HW strips the CRC. 4629 */ 4630 rctl |= E1000_RCTL_SECRC; 4631 4632 /* disable store bad packets and clear size bits. */ 4633 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4634 4635 /* enable LPE to allow for reception of jumbo frames */ 4636 rctl |= E1000_RCTL_LPE; 4637 4638 /* disable queue 0 to prevent tail write w/o re-config */ 4639 wr32(E1000_RXDCTL(0), 0); 4640 4641 /* Attention!!! For SR-IOV PF driver operations you must enable 4642 * queue drop for all VF and PF queues to prevent head of line blocking 4643 * if an un-trusted VF does not provide descriptors to hardware. 4644 */ 4645 if (adapter->vfs_allocated_count) { 4646 /* set all queue drop enable bits */ 4647 wr32(E1000_QDE, ALL_QUEUES); 4648 } 4649 4650 /* This is useful for sniffing bad packets. */ 4651 if (adapter->netdev->features & NETIF_F_RXALL) { 4652 /* UPE and MPE will be handled by normal PROMISC logic 4653 * in e1000e_set_rx_mode 4654 */ 4655 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4656 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4657 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4658 4659 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4660 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4661 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4662 * and that breaks VLANs. 4663 */ 4664 } 4665 4666 wr32(E1000_RCTL, rctl); 4667 } 4668 4669 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4670 int vfn) 4671 { 4672 struct e1000_hw *hw = &adapter->hw; 4673 u32 vmolr; 4674 4675 if (size > MAX_JUMBO_FRAME_SIZE) 4676 size = MAX_JUMBO_FRAME_SIZE; 4677 4678 vmolr = rd32(E1000_VMOLR(vfn)); 4679 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4680 vmolr |= size | E1000_VMOLR_LPE; 4681 wr32(E1000_VMOLR(vfn), vmolr); 4682 4683 return 0; 4684 } 4685 4686 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4687 int vfn, bool enable) 4688 { 4689 struct e1000_hw *hw = &adapter->hw; 4690 u32 val, reg; 4691 4692 if (hw->mac.type < e1000_82576) 4693 return; 4694 4695 if (hw->mac.type == e1000_i350) 4696 reg = E1000_DVMOLR(vfn); 4697 else 4698 reg = E1000_VMOLR(vfn); 4699 4700 val = rd32(reg); 4701 if (enable) 4702 val |= E1000_VMOLR_STRVLAN; 4703 else 4704 val &= ~(E1000_VMOLR_STRVLAN); 4705 wr32(reg, val); 4706 } 4707 4708 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4709 int vfn, bool aupe) 4710 { 4711 struct e1000_hw *hw = &adapter->hw; 4712 u32 vmolr; 4713 4714 /* This register exists only on 82576 and newer so if we are older then 4715 * we should exit and do nothing 4716 */ 4717 if (hw->mac.type < e1000_82576) 4718 return; 4719 4720 vmolr = rd32(E1000_VMOLR(vfn)); 4721 if (aupe) 4722 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4723 else 4724 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4725 4726 /* clear all bits that might not be set */ 4727 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4728 4729 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4730 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4731 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4732 * multicast packets 4733 */ 4734 if (vfn <= adapter->vfs_allocated_count) 4735 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4736 4737 wr32(E1000_VMOLR(vfn), vmolr); 4738 } 4739 4740 /** 4741 * igb_setup_srrctl - configure the split and replication receive control 4742 * registers 4743 * @adapter: Board private structure 4744 * @ring: receive ring to be configured 4745 **/ 4746 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4747 { 4748 struct e1000_hw *hw = &adapter->hw; 4749 int reg_idx = ring->reg_idx; 4750 u32 srrctl = 0; 4751 u32 buf_size; 4752 4753 if (ring->xsk_pool) 4754 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4755 else if (ring_uses_large_buffer(ring)) 4756 buf_size = IGB_RXBUFFER_3072; 4757 else 4758 buf_size = IGB_RXBUFFER_2048; 4759 4760 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4761 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4762 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4763 if (hw->mac.type >= e1000_82580) 4764 srrctl |= E1000_SRRCTL_TIMESTAMP; 4765 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4766 * queues and rx flow control is disabled 4767 */ 4768 if (adapter->vfs_allocated_count || 4769 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4770 adapter->num_rx_queues > 1)) 4771 srrctl |= E1000_SRRCTL_DROP_EN; 4772 4773 wr32(E1000_SRRCTL(reg_idx), srrctl); 4774 } 4775 4776 /** 4777 * igb_configure_rx_ring - Configure a receive ring after Reset 4778 * @adapter: board private structure 4779 * @ring: receive ring to be configured 4780 * 4781 * Configure the Rx unit of the MAC after a reset. 4782 **/ 4783 void igb_configure_rx_ring(struct igb_adapter *adapter, 4784 struct igb_ring *ring) 4785 { 4786 struct e1000_hw *hw = &adapter->hw; 4787 union e1000_adv_rx_desc *rx_desc; 4788 u64 rdba = ring->dma; 4789 int reg_idx = ring->reg_idx; 4790 u32 rxdctl = 0; 4791 4792 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4793 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4794 if (ring->xsk_pool) { 4795 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4796 MEM_TYPE_XSK_BUFF_POOL, 4797 NULL)); 4798 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4799 } else { 4800 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4801 MEM_TYPE_PAGE_SHARED, 4802 NULL)); 4803 } 4804 4805 /* disable the queue */ 4806 wr32(E1000_RXDCTL(reg_idx), 0); 4807 4808 /* Set DMA base address registers */ 4809 wr32(E1000_RDBAL(reg_idx), 4810 rdba & 0x00000000ffffffffULL); 4811 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4812 wr32(E1000_RDLEN(reg_idx), 4813 ring->count * sizeof(union e1000_adv_rx_desc)); 4814 4815 /* initialize head and tail */ 4816 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4817 wr32(E1000_RDH(reg_idx), 0); 4818 writel(0, ring->tail); 4819 4820 /* set descriptor configuration */ 4821 igb_setup_srrctl(adapter, ring); 4822 4823 /* set filtering for VMDQ pools */ 4824 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4825 4826 rxdctl |= IGB_RX_PTHRESH; 4827 rxdctl |= IGB_RX_HTHRESH << 8; 4828 rxdctl |= IGB_RX_WTHRESH << 16; 4829 4830 if (ring->xsk_pool) 4831 memset(ring->rx_buffer_info_zc, 0, 4832 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4833 else 4834 memset(ring->rx_buffer_info, 0, 4835 sizeof(*ring->rx_buffer_info) * ring->count); 4836 4837 /* initialize Rx descriptor 0 */ 4838 rx_desc = IGB_RX_DESC(ring, 0); 4839 rx_desc->wb.upper.length = 0; 4840 4841 /* enable receive descriptor fetching */ 4842 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4843 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4844 } 4845 4846 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4847 struct igb_ring *rx_ring) 4848 { 4849 #if (PAGE_SIZE < 8192) 4850 struct e1000_hw *hw = &adapter->hw; 4851 #endif 4852 4853 /* set build_skb and buffer size flags */ 4854 clear_ring_build_skb_enabled(rx_ring); 4855 clear_ring_uses_large_buffer(rx_ring); 4856 4857 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4858 return; 4859 4860 set_ring_build_skb_enabled(rx_ring); 4861 4862 #if (PAGE_SIZE < 8192) 4863 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4864 IGB_2K_TOO_SMALL_WITH_PADDING || 4865 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4866 set_ring_uses_large_buffer(rx_ring); 4867 #endif 4868 } 4869 4870 /** 4871 * igb_configure_rx - Configure receive Unit after Reset 4872 * @adapter: board private structure 4873 * 4874 * Configure the Rx unit of the MAC after a reset. 4875 **/ 4876 static void igb_configure_rx(struct igb_adapter *adapter) 4877 { 4878 int i; 4879 4880 /* set the correct pool for the PF default MAC address in entry 0 */ 4881 igb_set_default_mac_filter(adapter); 4882 4883 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4884 * the Base and Length of the Rx Descriptor Ring 4885 */ 4886 for (i = 0; i < adapter->num_rx_queues; i++) { 4887 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4888 4889 igb_set_rx_buffer_len(adapter, rx_ring); 4890 igb_configure_rx_ring(adapter, rx_ring); 4891 } 4892 } 4893 4894 /** 4895 * igb_free_tx_resources - Free Tx Resources per Queue 4896 * @tx_ring: Tx descriptor ring for a specific queue 4897 * 4898 * Free all transmit software resources 4899 **/ 4900 void igb_free_tx_resources(struct igb_ring *tx_ring) 4901 { 4902 igb_clean_tx_ring(tx_ring); 4903 4904 vfree(tx_ring->tx_buffer_info); 4905 tx_ring->tx_buffer_info = NULL; 4906 4907 /* if not set, then don't free */ 4908 if (!tx_ring->desc) 4909 return; 4910 4911 dma_free_coherent(tx_ring->dev, tx_ring->size, 4912 tx_ring->desc, tx_ring->dma); 4913 4914 tx_ring->desc = NULL; 4915 } 4916 4917 /** 4918 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4919 * @adapter: board private structure 4920 * 4921 * Free all transmit software resources 4922 **/ 4923 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4924 { 4925 int i; 4926 4927 for (i = 0; i < adapter->num_tx_queues; i++) 4928 if (adapter->tx_ring[i]) 4929 igb_free_tx_resources(adapter->tx_ring[i]); 4930 } 4931 4932 /** 4933 * igb_clean_tx_ring - Free Tx Buffers 4934 * @tx_ring: ring to be cleaned 4935 **/ 4936 void igb_clean_tx_ring(struct igb_ring *tx_ring) 4937 { 4938 u16 i = tx_ring->next_to_clean; 4939 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4940 u32 xsk_frames = 0; 4941 4942 while (i != tx_ring->next_to_use) { 4943 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4944 4945 /* Free all the Tx ring sk_buffs or xdp frames */ 4946 if (tx_buffer->type == IGB_TYPE_SKB) { 4947 dev_kfree_skb_any(tx_buffer->skb); 4948 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4949 xdp_return_frame(tx_buffer->xdpf); 4950 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4951 xsk_frames++; 4952 goto skip_for_xsk; 4953 } 4954 4955 /* unmap skb header data */ 4956 dma_unmap_single(tx_ring->dev, 4957 dma_unmap_addr(tx_buffer, dma), 4958 dma_unmap_len(tx_buffer, len), 4959 DMA_TO_DEVICE); 4960 4961 /* check for eop_desc to determine the end of the packet */ 4962 eop_desc = tx_buffer->next_to_watch; 4963 tx_desc = IGB_TX_DESC(tx_ring, i); 4964 4965 /* unmap remaining buffers */ 4966 while (tx_desc != eop_desc) { 4967 tx_buffer++; 4968 tx_desc++; 4969 i++; 4970 if (unlikely(i == tx_ring->count)) { 4971 i = 0; 4972 tx_buffer = tx_ring->tx_buffer_info; 4973 tx_desc = IGB_TX_DESC(tx_ring, 0); 4974 } 4975 4976 /* unmap any remaining paged data */ 4977 if (dma_unmap_len(tx_buffer, len)) 4978 dma_unmap_page(tx_ring->dev, 4979 dma_unmap_addr(tx_buffer, dma), 4980 dma_unmap_len(tx_buffer, len), 4981 DMA_TO_DEVICE); 4982 } 4983 4984 skip_for_xsk: 4985 tx_buffer->next_to_watch = NULL; 4986 4987 /* move us one more past the eop_desc for start of next pkt */ 4988 tx_buffer++; 4989 i++; 4990 if (unlikely(i == tx_ring->count)) { 4991 i = 0; 4992 tx_buffer = tx_ring->tx_buffer_info; 4993 } 4994 } 4995 4996 /* reset BQL for queue */ 4997 netdev_tx_reset_queue(txring_txq(tx_ring)); 4998 4999 if (tx_ring->xsk_pool && xsk_frames) 5000 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 5001 5002 /* reset next_to_use and next_to_clean */ 5003 tx_ring->next_to_use = 0; 5004 tx_ring->next_to_clean = 0; 5005 } 5006 5007 /** 5008 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 5009 * @adapter: board private structure 5010 **/ 5011 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 5012 { 5013 int i; 5014 5015 for (i = 0; i < adapter->num_tx_queues; i++) 5016 if (adapter->tx_ring[i]) 5017 igb_clean_tx_ring(adapter->tx_ring[i]); 5018 } 5019 5020 /** 5021 * igb_free_rx_resources - Free Rx Resources 5022 * @rx_ring: ring to clean the resources from 5023 * 5024 * Free all receive software resources 5025 **/ 5026 void igb_free_rx_resources(struct igb_ring *rx_ring) 5027 { 5028 igb_clean_rx_ring(rx_ring); 5029 5030 rx_ring->xdp_prog = NULL; 5031 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5032 if (rx_ring->xsk_pool) { 5033 vfree(rx_ring->rx_buffer_info_zc); 5034 rx_ring->rx_buffer_info_zc = NULL; 5035 } else { 5036 vfree(rx_ring->rx_buffer_info); 5037 rx_ring->rx_buffer_info = NULL; 5038 } 5039 5040 /* if not set, then don't free */ 5041 if (!rx_ring->desc) 5042 return; 5043 5044 dma_free_coherent(rx_ring->dev, rx_ring->size, 5045 rx_ring->desc, rx_ring->dma); 5046 5047 rx_ring->desc = NULL; 5048 } 5049 5050 /** 5051 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5052 * @adapter: board private structure 5053 * 5054 * Free all receive software resources 5055 **/ 5056 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5057 { 5058 int i; 5059 5060 for (i = 0; i < adapter->num_rx_queues; i++) 5061 if (adapter->rx_ring[i]) 5062 igb_free_rx_resources(adapter->rx_ring[i]); 5063 } 5064 5065 /** 5066 * igb_clean_rx_ring - Free Rx Buffers per Queue 5067 * @rx_ring: ring to free buffers from 5068 **/ 5069 void igb_clean_rx_ring(struct igb_ring *rx_ring) 5070 { 5071 u16 i = rx_ring->next_to_clean; 5072 5073 dev_kfree_skb(rx_ring->skb); 5074 rx_ring->skb = NULL; 5075 5076 if (rx_ring->xsk_pool) { 5077 igb_clean_rx_ring_zc(rx_ring); 5078 goto skip_for_xsk; 5079 } 5080 5081 /* Free all the Rx ring sk_buffs */ 5082 while (i != rx_ring->next_to_alloc) { 5083 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5084 5085 /* Invalidate cache lines that may have been written to by 5086 * device so that we avoid corrupting memory. 5087 */ 5088 dma_sync_single_range_for_cpu(rx_ring->dev, 5089 buffer_info->dma, 5090 buffer_info->page_offset, 5091 igb_rx_bufsz(rx_ring), 5092 DMA_FROM_DEVICE); 5093 5094 /* free resources associated with mapping */ 5095 dma_unmap_page_attrs(rx_ring->dev, 5096 buffer_info->dma, 5097 igb_rx_pg_size(rx_ring), 5098 DMA_FROM_DEVICE, 5099 IGB_RX_DMA_ATTR); 5100 __page_frag_cache_drain(buffer_info->page, 5101 buffer_info->pagecnt_bias); 5102 5103 i++; 5104 if (i == rx_ring->count) 5105 i = 0; 5106 } 5107 5108 skip_for_xsk: 5109 rx_ring->next_to_alloc = 0; 5110 rx_ring->next_to_clean = 0; 5111 rx_ring->next_to_use = 0; 5112 } 5113 5114 /** 5115 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5116 * @adapter: board private structure 5117 **/ 5118 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5119 { 5120 int i; 5121 5122 for (i = 0; i < adapter->num_rx_queues; i++) 5123 if (adapter->rx_ring[i]) 5124 igb_clean_rx_ring(adapter->rx_ring[i]); 5125 } 5126 5127 /** 5128 * igb_set_mac - Change the Ethernet Address of the NIC 5129 * @netdev: network interface device structure 5130 * @p: pointer to an address structure 5131 * 5132 * Returns 0 on success, negative on failure 5133 **/ 5134 static int igb_set_mac(struct net_device *netdev, void *p) 5135 { 5136 struct igb_adapter *adapter = netdev_priv(netdev); 5137 struct e1000_hw *hw = &adapter->hw; 5138 struct sockaddr *addr = p; 5139 5140 if (!is_valid_ether_addr(addr->sa_data)) 5141 return -EADDRNOTAVAIL; 5142 5143 eth_hw_addr_set(netdev, addr->sa_data); 5144 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5145 5146 /* set the correct pool for the new PF MAC address in entry 0 */ 5147 igb_set_default_mac_filter(adapter); 5148 5149 return 0; 5150 } 5151 5152 /** 5153 * igb_write_mc_addr_list - write multicast addresses to MTA 5154 * @netdev: network interface device structure 5155 * 5156 * Writes multicast address list to the MTA hash table. 5157 * Returns: -ENOMEM on failure 5158 * 0 on no addresses written 5159 * X on writing X addresses to MTA 5160 **/ 5161 static int igb_write_mc_addr_list(struct net_device *netdev) 5162 { 5163 struct igb_adapter *adapter = netdev_priv(netdev); 5164 struct e1000_hw *hw = &adapter->hw; 5165 struct netdev_hw_addr *ha; 5166 u8 *mta_list; 5167 int i; 5168 5169 if (netdev_mc_empty(netdev)) { 5170 /* nothing to program, so clear mc list */ 5171 igb_update_mc_addr_list(hw, NULL, 0); 5172 igb_restore_vf_multicasts(adapter); 5173 return 0; 5174 } 5175 5176 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5177 if (!mta_list) 5178 return -ENOMEM; 5179 5180 /* The shared function expects a packed array of only addresses. */ 5181 i = 0; 5182 netdev_for_each_mc_addr(ha, netdev) 5183 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5184 5185 igb_update_mc_addr_list(hw, mta_list, i); 5186 kfree(mta_list); 5187 5188 return netdev_mc_count(netdev); 5189 } 5190 5191 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5192 { 5193 struct e1000_hw *hw = &adapter->hw; 5194 u32 i, pf_id; 5195 5196 switch (hw->mac.type) { 5197 case e1000_i210: 5198 case e1000_i211: 5199 case e1000_i350: 5200 /* VLAN filtering needed for VLAN prio filter */ 5201 if (adapter->netdev->features & NETIF_F_NTUPLE) 5202 break; 5203 fallthrough; 5204 case e1000_82576: 5205 case e1000_82580: 5206 case e1000_i354: 5207 /* VLAN filtering needed for pool filtering */ 5208 if (adapter->vfs_allocated_count) 5209 break; 5210 fallthrough; 5211 default: 5212 return 1; 5213 } 5214 5215 /* We are already in VLAN promisc, nothing to do */ 5216 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5217 return 0; 5218 5219 if (!adapter->vfs_allocated_count) 5220 goto set_vfta; 5221 5222 /* Add PF to all active pools */ 5223 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5224 5225 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5226 u32 vlvf = rd32(E1000_VLVF(i)); 5227 5228 vlvf |= BIT(pf_id); 5229 wr32(E1000_VLVF(i), vlvf); 5230 } 5231 5232 set_vfta: 5233 /* Set all bits in the VLAN filter table array */ 5234 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5235 hw->mac.ops.write_vfta(hw, i, ~0U); 5236 5237 /* Set flag so we don't redo unnecessary work */ 5238 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5239 5240 return 0; 5241 } 5242 5243 #define VFTA_BLOCK_SIZE 8 5244 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5245 { 5246 struct e1000_hw *hw = &adapter->hw; 5247 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5248 u32 vid_start = vfta_offset * 32; 5249 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5250 u32 i, vid, word, bits, pf_id; 5251 5252 /* guarantee that we don't scrub out management VLAN */ 5253 vid = adapter->mng_vlan_id; 5254 if (vid >= vid_start && vid < vid_end) 5255 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5256 5257 if (!adapter->vfs_allocated_count) 5258 goto set_vfta; 5259 5260 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5261 5262 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5263 u32 vlvf = rd32(E1000_VLVF(i)); 5264 5265 /* pull VLAN ID from VLVF */ 5266 vid = vlvf & VLAN_VID_MASK; 5267 5268 /* only concern ourselves with a certain range */ 5269 if (vid < vid_start || vid >= vid_end) 5270 continue; 5271 5272 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5273 /* record VLAN ID in VFTA */ 5274 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5275 5276 /* if PF is part of this then continue */ 5277 if (test_bit(vid, adapter->active_vlans)) 5278 continue; 5279 } 5280 5281 /* remove PF from the pool */ 5282 bits = ~BIT(pf_id); 5283 bits &= rd32(E1000_VLVF(i)); 5284 wr32(E1000_VLVF(i), bits); 5285 } 5286 5287 set_vfta: 5288 /* extract values from active_vlans and write back to VFTA */ 5289 for (i = VFTA_BLOCK_SIZE; i--;) { 5290 vid = (vfta_offset + i) * 32; 5291 word = vid / BITS_PER_LONG; 5292 bits = vid % BITS_PER_LONG; 5293 5294 vfta[i] |= adapter->active_vlans[word] >> bits; 5295 5296 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5297 } 5298 } 5299 5300 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5301 { 5302 u32 i; 5303 5304 /* We are not in VLAN promisc, nothing to do */ 5305 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5306 return; 5307 5308 /* Set flag so we don't redo unnecessary work */ 5309 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5310 5311 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5312 igb_scrub_vfta(adapter, i); 5313 } 5314 5315 /** 5316 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5317 * @netdev: network interface device structure 5318 * 5319 * The set_rx_mode entry point is called whenever the unicast or multicast 5320 * address lists or the network interface flags are updated. This routine is 5321 * responsible for configuring the hardware for proper unicast, multicast, 5322 * promiscuous mode, and all-multi behavior. 5323 **/ 5324 static void igb_set_rx_mode(struct net_device *netdev) 5325 { 5326 struct igb_adapter *adapter = netdev_priv(netdev); 5327 struct e1000_hw *hw = &adapter->hw; 5328 unsigned int vfn = adapter->vfs_allocated_count; 5329 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5330 int count; 5331 5332 /* Check for Promiscuous and All Multicast modes */ 5333 if (netdev->flags & IFF_PROMISC) { 5334 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5335 vmolr |= E1000_VMOLR_MPME; 5336 5337 /* enable use of UTA filter to force packets to default pool */ 5338 if (hw->mac.type == e1000_82576) 5339 vmolr |= E1000_VMOLR_ROPE; 5340 } else { 5341 if (netdev->flags & IFF_ALLMULTI) { 5342 rctl |= E1000_RCTL_MPE; 5343 vmolr |= E1000_VMOLR_MPME; 5344 } else { 5345 /* Write addresses to the MTA, if the attempt fails 5346 * then we should just turn on promiscuous mode so 5347 * that we can at least receive multicast traffic 5348 */ 5349 count = igb_write_mc_addr_list(netdev); 5350 if (count < 0) { 5351 rctl |= E1000_RCTL_MPE; 5352 vmolr |= E1000_VMOLR_MPME; 5353 } else if (count) { 5354 vmolr |= E1000_VMOLR_ROMPE; 5355 } 5356 } 5357 } 5358 5359 /* Write addresses to available RAR registers, if there is not 5360 * sufficient space to store all the addresses then enable 5361 * unicast promiscuous mode 5362 */ 5363 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5364 rctl |= E1000_RCTL_UPE; 5365 vmolr |= E1000_VMOLR_ROPE; 5366 } 5367 5368 /* enable VLAN filtering by default */ 5369 rctl |= E1000_RCTL_VFE; 5370 5371 /* disable VLAN filtering for modes that require it */ 5372 if ((netdev->flags & IFF_PROMISC) || 5373 (netdev->features & NETIF_F_RXALL)) { 5374 /* if we fail to set all rules then just clear VFE */ 5375 if (igb_vlan_promisc_enable(adapter)) 5376 rctl &= ~E1000_RCTL_VFE; 5377 } else { 5378 igb_vlan_promisc_disable(adapter); 5379 } 5380 5381 /* update state of unicast, multicast, and VLAN filtering modes */ 5382 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5383 E1000_RCTL_VFE); 5384 wr32(E1000_RCTL, rctl); 5385 5386 #if (PAGE_SIZE < 8192) 5387 if (!adapter->vfs_allocated_count) { 5388 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5389 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5390 } 5391 #endif 5392 wr32(E1000_RLPML, rlpml); 5393 5394 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5395 * the VMOLR to enable the appropriate modes. Without this workaround 5396 * we will have issues with VLAN tag stripping not being done for frames 5397 * that are only arriving because we are the default pool 5398 */ 5399 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5400 return; 5401 5402 /* set UTA to appropriate mode */ 5403 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5404 5405 vmolr |= rd32(E1000_VMOLR(vfn)) & 5406 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5407 5408 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5409 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5410 #if (PAGE_SIZE < 8192) 5411 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5412 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5413 else 5414 #endif 5415 vmolr |= MAX_JUMBO_FRAME_SIZE; 5416 vmolr |= E1000_VMOLR_LPE; 5417 5418 wr32(E1000_VMOLR(vfn), vmolr); 5419 5420 igb_restore_vf_multicasts(adapter); 5421 } 5422 5423 static void igb_check_wvbr(struct igb_adapter *adapter) 5424 { 5425 struct e1000_hw *hw = &adapter->hw; 5426 u32 wvbr = 0; 5427 5428 switch (hw->mac.type) { 5429 case e1000_82576: 5430 case e1000_i350: 5431 wvbr = rd32(E1000_WVBR); 5432 if (!wvbr) 5433 return; 5434 break; 5435 default: 5436 break; 5437 } 5438 5439 adapter->wvbr |= wvbr; 5440 } 5441 5442 #define IGB_STAGGERED_QUEUE_OFFSET 8 5443 5444 static void igb_spoof_check(struct igb_adapter *adapter) 5445 { 5446 int j; 5447 5448 if (!adapter->wvbr) 5449 return; 5450 5451 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5452 if (adapter->wvbr & BIT(j) || 5453 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5454 dev_warn(&adapter->pdev->dev, 5455 "Spoof event(s) detected on VF %d\n", j); 5456 adapter->wvbr &= 5457 ~(BIT(j) | 5458 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5459 } 5460 } 5461 } 5462 5463 /* Need to wait a few seconds after link up to get diagnostic information from 5464 * the phy 5465 */ 5466 static void igb_update_phy_info(struct timer_list *t) 5467 { 5468 struct igb_adapter *adapter = timer_container_of(adapter, t, 5469 phy_info_timer); 5470 igb_get_phy_info(&adapter->hw); 5471 } 5472 5473 /** 5474 * igb_has_link - check shared code for link and determine up/down 5475 * @adapter: pointer to driver private info 5476 **/ 5477 bool igb_has_link(struct igb_adapter *adapter) 5478 { 5479 struct e1000_hw *hw = &adapter->hw; 5480 bool link_active = false; 5481 5482 /* get_link_status is set on LSC (link status) interrupt or 5483 * rx sequence error interrupt. get_link_status will stay 5484 * false until the e1000_check_for_link establishes link 5485 * for copper adapters ONLY 5486 */ 5487 switch (hw->phy.media_type) { 5488 case e1000_media_type_copper: 5489 if (!hw->mac.get_link_status) 5490 return true; 5491 fallthrough; 5492 case e1000_media_type_internal_serdes: 5493 hw->mac.ops.check_for_link(hw); 5494 link_active = !hw->mac.get_link_status; 5495 break; 5496 default: 5497 case e1000_media_type_unknown: 5498 break; 5499 } 5500 5501 if (((hw->mac.type == e1000_i210) || 5502 (hw->mac.type == e1000_i211)) && 5503 (hw->phy.id == I210_I_PHY_ID)) { 5504 if (!netif_carrier_ok(adapter->netdev)) { 5505 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5506 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5507 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5508 adapter->link_check_timeout = jiffies; 5509 } 5510 } 5511 5512 return link_active; 5513 } 5514 5515 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5516 { 5517 bool ret = false; 5518 u32 ctrl_ext, thstat; 5519 5520 /* check for thermal sensor event on i350 copper only */ 5521 if (hw->mac.type == e1000_i350) { 5522 thstat = rd32(E1000_THSTAT); 5523 ctrl_ext = rd32(E1000_CTRL_EXT); 5524 5525 if ((hw->phy.media_type == e1000_media_type_copper) && 5526 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5527 ret = !!(thstat & event); 5528 } 5529 5530 return ret; 5531 } 5532 5533 /** 5534 * igb_check_lvmmc - check for malformed packets received 5535 * and indicated in LVMMC register 5536 * @adapter: pointer to adapter 5537 **/ 5538 static void igb_check_lvmmc(struct igb_adapter *adapter) 5539 { 5540 struct e1000_hw *hw = &adapter->hw; 5541 u32 lvmmc; 5542 5543 lvmmc = rd32(E1000_LVMMC); 5544 if (lvmmc) { 5545 if (unlikely(net_ratelimit())) { 5546 netdev_warn(adapter->netdev, 5547 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5548 lvmmc); 5549 } 5550 } 5551 } 5552 5553 /** 5554 * igb_watchdog - Timer Call-back 5555 * @t: pointer to timer_list containing our private info pointer 5556 **/ 5557 static void igb_watchdog(struct timer_list *t) 5558 { 5559 struct igb_adapter *adapter = timer_container_of(adapter, t, 5560 watchdog_timer); 5561 /* Do the rest outside of interrupt context */ 5562 schedule_work(&adapter->watchdog_task); 5563 } 5564 5565 static void igb_watchdog_task(struct work_struct *work) 5566 { 5567 struct igb_adapter *adapter = container_of(work, 5568 struct igb_adapter, 5569 watchdog_task); 5570 struct e1000_hw *hw = &adapter->hw; 5571 struct e1000_phy_info *phy = &hw->phy; 5572 struct net_device *netdev = adapter->netdev; 5573 u32 link; 5574 int i; 5575 u32 connsw; 5576 u16 phy_data, retry_count = 20; 5577 5578 link = igb_has_link(adapter); 5579 5580 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5581 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5582 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5583 else 5584 link = false; 5585 } 5586 5587 /* Force link down if we have fiber to swap to */ 5588 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5589 if (hw->phy.media_type == e1000_media_type_copper) { 5590 connsw = rd32(E1000_CONNSW); 5591 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5592 link = 0; 5593 } 5594 } 5595 if (link) { 5596 /* Perform a reset if the media type changed. */ 5597 if (hw->dev_spec._82575.media_changed) { 5598 hw->dev_spec._82575.media_changed = false; 5599 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5600 igb_reset(adapter); 5601 } 5602 /* Cancel scheduled suspend requests. */ 5603 pm_runtime_resume(netdev->dev.parent); 5604 5605 if (!netif_carrier_ok(netdev)) { 5606 u32 ctrl; 5607 5608 hw->mac.ops.get_speed_and_duplex(hw, 5609 &adapter->link_speed, 5610 &adapter->link_duplex); 5611 5612 ctrl = rd32(E1000_CTRL); 5613 /* Links status message must follow this format */ 5614 netdev_info(netdev, 5615 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5616 netdev->name, 5617 adapter->link_speed, 5618 adapter->link_duplex == FULL_DUPLEX ? 5619 "Full" : "Half", 5620 (ctrl & E1000_CTRL_TFCE) && 5621 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5622 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5623 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5624 5625 /* disable EEE if enabled */ 5626 if ((adapter->flags & IGB_FLAG_EEE) && 5627 (adapter->link_duplex == HALF_DUPLEX)) { 5628 dev_info(&adapter->pdev->dev, 5629 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5630 adapter->hw.dev_spec._82575.eee_disable = true; 5631 adapter->flags &= ~IGB_FLAG_EEE; 5632 } 5633 5634 /* check if SmartSpeed worked */ 5635 igb_check_downshift(hw); 5636 if (phy->speed_downgraded) 5637 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5638 5639 /* check for thermal sensor event */ 5640 if (igb_thermal_sensor_event(hw, 5641 E1000_THSTAT_LINK_THROTTLE)) 5642 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5643 5644 /* adjust timeout factor according to speed/duplex */ 5645 adapter->tx_timeout_factor = 1; 5646 switch (adapter->link_speed) { 5647 case SPEED_10: 5648 adapter->tx_timeout_factor = 14; 5649 break; 5650 case SPEED_100: 5651 /* maybe add some timeout factor ? */ 5652 break; 5653 } 5654 5655 if (adapter->link_speed != SPEED_1000 || 5656 !hw->phy.ops.read_reg) 5657 goto no_wait; 5658 5659 /* wait for Remote receiver status OK */ 5660 retry_read_status: 5661 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5662 &phy_data)) { 5663 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5664 retry_count) { 5665 msleep(100); 5666 retry_count--; 5667 goto retry_read_status; 5668 } else if (!retry_count) { 5669 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5670 } 5671 } else { 5672 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5673 } 5674 no_wait: 5675 netif_carrier_on(netdev); 5676 5677 igb_ping_all_vfs(adapter); 5678 igb_check_vf_rate_limit(adapter); 5679 5680 /* link state has changed, schedule phy info update */ 5681 if (!test_bit(__IGB_DOWN, &adapter->state)) 5682 mod_timer(&adapter->phy_info_timer, 5683 round_jiffies(jiffies + 2 * HZ)); 5684 } 5685 } else { 5686 if (netif_carrier_ok(netdev)) { 5687 adapter->link_speed = 0; 5688 adapter->link_duplex = 0; 5689 5690 /* check for thermal sensor event */ 5691 if (igb_thermal_sensor_event(hw, 5692 E1000_THSTAT_PWR_DOWN)) { 5693 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5694 } 5695 5696 /* Links status message must follow this format */ 5697 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5698 netdev->name); 5699 netif_carrier_off(netdev); 5700 5701 igb_ping_all_vfs(adapter); 5702 5703 /* link state has changed, schedule phy info update */ 5704 if (!test_bit(__IGB_DOWN, &adapter->state)) 5705 mod_timer(&adapter->phy_info_timer, 5706 round_jiffies(jiffies + 2 * HZ)); 5707 5708 /* link is down, time to check for alternate media */ 5709 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5710 igb_check_swap_media(adapter); 5711 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5712 schedule_work(&adapter->reset_task); 5713 /* return immediately */ 5714 return; 5715 } 5716 } 5717 pm_schedule_suspend(netdev->dev.parent, 5718 MSEC_PER_SEC * 5); 5719 5720 /* also check for alternate media here */ 5721 } else if (!netif_carrier_ok(netdev) && 5722 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5723 igb_check_swap_media(adapter); 5724 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5725 schedule_work(&adapter->reset_task); 5726 /* return immediately */ 5727 return; 5728 } 5729 } 5730 } 5731 5732 spin_lock(&adapter->stats64_lock); 5733 igb_update_stats(adapter); 5734 spin_unlock(&adapter->stats64_lock); 5735 5736 for (i = 0; i < adapter->num_tx_queues; i++) { 5737 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5738 if (!netif_carrier_ok(netdev)) { 5739 /* We've lost link, so the controller stops DMA, 5740 * but we've got queued Tx work that's never going 5741 * to get done, so reset controller to flush Tx. 5742 * (Do the reset outside of interrupt context). 5743 */ 5744 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5745 adapter->tx_timeout_count++; 5746 schedule_work(&adapter->reset_task); 5747 /* return immediately since reset is imminent */ 5748 return; 5749 } 5750 } 5751 5752 /* Force detection of hung controller every watchdog period */ 5753 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5754 } 5755 5756 /* Cause software interrupt to ensure Rx ring is cleaned */ 5757 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5758 u32 eics = 0; 5759 5760 for (i = 0; i < adapter->num_q_vectors; i++) { 5761 struct igb_q_vector *q_vector = adapter->q_vector[i]; 5762 struct igb_ring *rx_ring; 5763 5764 if (!q_vector->rx.ring) 5765 continue; 5766 5767 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5768 5769 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5770 eics |= q_vector->eims_value; 5771 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5772 } 5773 } 5774 if (eics) 5775 wr32(E1000_EICS, eics); 5776 } else { 5777 struct igb_ring *rx_ring = adapter->rx_ring[0]; 5778 5779 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5780 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5781 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5782 } 5783 } 5784 5785 igb_spoof_check(adapter); 5786 igb_ptp_rx_hang(adapter); 5787 igb_ptp_tx_hang(adapter); 5788 5789 /* Check LVMMC register on i350/i354 only */ 5790 if ((adapter->hw.mac.type == e1000_i350) || 5791 (adapter->hw.mac.type == e1000_i354)) 5792 igb_check_lvmmc(adapter); 5793 5794 /* Reset the timer */ 5795 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5796 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5797 mod_timer(&adapter->watchdog_timer, 5798 round_jiffies(jiffies + HZ)); 5799 else 5800 mod_timer(&adapter->watchdog_timer, 5801 round_jiffies(jiffies + 2 * HZ)); 5802 } 5803 } 5804 5805 enum latency_range { 5806 lowest_latency = 0, 5807 low_latency = 1, 5808 bulk_latency = 2, 5809 latency_invalid = 255 5810 }; 5811 5812 /** 5813 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5814 * @q_vector: pointer to q_vector 5815 * 5816 * Stores a new ITR value based on strictly on packet size. This 5817 * algorithm is less sophisticated than that used in igb_update_itr, 5818 * due to the difficulty of synchronizing statistics across multiple 5819 * receive rings. The divisors and thresholds used by this function 5820 * were determined based on theoretical maximum wire speed and testing 5821 * data, in order to minimize response time while increasing bulk 5822 * throughput. 5823 * This functionality is controlled by ethtool's coalescing settings. 5824 * NOTE: This function is called only when operating in a multiqueue 5825 * receive environment. 5826 **/ 5827 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5828 { 5829 int new_val = q_vector->itr_val; 5830 int avg_wire_size = 0; 5831 struct igb_adapter *adapter = q_vector->adapter; 5832 unsigned int packets; 5833 5834 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5835 * ints/sec - ITR timer value of 120 ticks. 5836 */ 5837 if (adapter->link_speed != SPEED_1000) { 5838 new_val = IGB_4K_ITR; 5839 goto set_itr_val; 5840 } 5841 5842 packets = q_vector->rx.total_packets; 5843 if (packets) 5844 avg_wire_size = q_vector->rx.total_bytes / packets; 5845 5846 packets = q_vector->tx.total_packets; 5847 if (packets) 5848 avg_wire_size = max_t(u32, avg_wire_size, 5849 q_vector->tx.total_bytes / packets); 5850 5851 /* if avg_wire_size isn't set no work was done */ 5852 if (!avg_wire_size) 5853 goto clear_counts; 5854 5855 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5856 avg_wire_size += 24; 5857 5858 /* Don't starve jumbo frames */ 5859 avg_wire_size = min(avg_wire_size, 3000); 5860 5861 /* Give a little boost to mid-size frames */ 5862 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5863 new_val = avg_wire_size / 3; 5864 else 5865 new_val = avg_wire_size / 2; 5866 5867 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5868 if (new_val < IGB_20K_ITR && 5869 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5870 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5871 new_val = IGB_20K_ITR; 5872 5873 set_itr_val: 5874 if (new_val != q_vector->itr_val) { 5875 q_vector->itr_val = new_val; 5876 q_vector->set_itr = 1; 5877 } 5878 clear_counts: 5879 q_vector->rx.total_bytes = 0; 5880 q_vector->rx.total_packets = 0; 5881 q_vector->tx.total_bytes = 0; 5882 q_vector->tx.total_packets = 0; 5883 } 5884 5885 /** 5886 * igb_update_itr - update the dynamic ITR value based on statistics 5887 * @q_vector: pointer to q_vector 5888 * @ring_container: ring info to update the itr for 5889 * 5890 * Stores a new ITR value based on packets and byte 5891 * counts during the last interrupt. The advantage of per interrupt 5892 * computation is faster updates and more accurate ITR for the current 5893 * traffic pattern. Constants in this function were computed 5894 * based on theoretical maximum wire speed and thresholds were set based 5895 * on testing data as well as attempting to minimize response time 5896 * while increasing bulk throughput. 5897 * This functionality is controlled by ethtool's coalescing settings. 5898 * NOTE: These calculations are only valid when operating in a single- 5899 * queue environment. 5900 **/ 5901 static void igb_update_itr(struct igb_q_vector *q_vector, 5902 struct igb_ring_container *ring_container) 5903 { 5904 unsigned int packets = ring_container->total_packets; 5905 unsigned int bytes = ring_container->total_bytes; 5906 u8 itrval = ring_container->itr; 5907 5908 /* no packets, exit with status unchanged */ 5909 if (packets == 0) 5910 return; 5911 5912 switch (itrval) { 5913 case lowest_latency: 5914 /* handle TSO and jumbo frames */ 5915 if (bytes/packets > 8000) 5916 itrval = bulk_latency; 5917 else if ((packets < 5) && (bytes > 512)) 5918 itrval = low_latency; 5919 break; 5920 case low_latency: /* 50 usec aka 20000 ints/s */ 5921 if (bytes > 10000) { 5922 /* this if handles the TSO accounting */ 5923 if (bytes/packets > 8000) 5924 itrval = bulk_latency; 5925 else if ((packets < 10) || ((bytes/packets) > 1200)) 5926 itrval = bulk_latency; 5927 else if ((packets > 35)) 5928 itrval = lowest_latency; 5929 } else if (bytes/packets > 2000) { 5930 itrval = bulk_latency; 5931 } else if (packets <= 2 && bytes < 512) { 5932 itrval = lowest_latency; 5933 } 5934 break; 5935 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5936 if (bytes > 25000) { 5937 if (packets > 35) 5938 itrval = low_latency; 5939 } else if (bytes < 1500) { 5940 itrval = low_latency; 5941 } 5942 break; 5943 } 5944 5945 /* clear work counters since we have the values we need */ 5946 ring_container->total_bytes = 0; 5947 ring_container->total_packets = 0; 5948 5949 /* write updated itr to ring container */ 5950 ring_container->itr = itrval; 5951 } 5952 5953 static void igb_set_itr(struct igb_q_vector *q_vector) 5954 { 5955 struct igb_adapter *adapter = q_vector->adapter; 5956 u32 new_itr = q_vector->itr_val; 5957 u8 current_itr = 0; 5958 5959 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5960 if (adapter->link_speed != SPEED_1000) { 5961 current_itr = 0; 5962 new_itr = IGB_4K_ITR; 5963 goto set_itr_now; 5964 } 5965 5966 igb_update_itr(q_vector, &q_vector->tx); 5967 igb_update_itr(q_vector, &q_vector->rx); 5968 5969 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5970 5971 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5972 if (current_itr == lowest_latency && 5973 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5974 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5975 current_itr = low_latency; 5976 5977 switch (current_itr) { 5978 /* counts and packets in update_itr are dependent on these numbers */ 5979 case lowest_latency: 5980 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5981 break; 5982 case low_latency: 5983 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5984 break; 5985 case bulk_latency: 5986 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5987 break; 5988 default: 5989 break; 5990 } 5991 5992 set_itr_now: 5993 if (new_itr != q_vector->itr_val) { 5994 /* this attempts to bias the interrupt rate towards Bulk 5995 * by adding intermediate steps when interrupt rate is 5996 * increasing 5997 */ 5998 new_itr = new_itr > q_vector->itr_val ? 5999 max((new_itr * q_vector->itr_val) / 6000 (new_itr + (q_vector->itr_val >> 2)), 6001 new_itr) : new_itr; 6002 /* Don't write the value here; it resets the adapter's 6003 * internal timer, and causes us to delay far longer than 6004 * we should between interrupts. Instead, we write the ITR 6005 * value at the beginning of the next interrupt so the timing 6006 * ends up being correct. 6007 */ 6008 q_vector->itr_val = new_itr; 6009 q_vector->set_itr = 1; 6010 } 6011 } 6012 6013 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 6014 struct igb_tx_buffer *first, 6015 u32 vlan_macip_lens, u32 type_tucmd, 6016 u32 mss_l4len_idx) 6017 { 6018 struct e1000_adv_tx_context_desc *context_desc; 6019 u16 i = tx_ring->next_to_use; 6020 struct timespec64 ts; 6021 6022 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 6023 6024 i++; 6025 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 6026 6027 /* set bits to identify this as an advanced context descriptor */ 6028 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 6029 6030 /* For 82575, context index must be unique per ring. */ 6031 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6032 mss_l4len_idx |= tx_ring->reg_idx << 4; 6033 6034 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 6035 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 6036 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 6037 6038 /* We assume there is always a valid tx time available. Invalid times 6039 * should have been handled by the upper layers. 6040 */ 6041 if (tx_ring->launchtime_enable) { 6042 ts = ktime_to_timespec64(first->skb->tstamp); 6043 skb_txtime_consumed(first->skb); 6044 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 6045 } else { 6046 context_desc->seqnum_seed = 0; 6047 } 6048 } 6049 6050 static int igb_tso(struct igb_ring *tx_ring, 6051 struct igb_tx_buffer *first, 6052 u8 *hdr_len) 6053 { 6054 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6055 struct sk_buff *skb = first->skb; 6056 union { 6057 struct iphdr *v4; 6058 struct ipv6hdr *v6; 6059 unsigned char *hdr; 6060 } ip; 6061 union { 6062 struct tcphdr *tcp; 6063 struct udphdr *udp; 6064 unsigned char *hdr; 6065 } l4; 6066 u32 paylen, l4_offset; 6067 int err; 6068 6069 if (skb->ip_summed != CHECKSUM_PARTIAL) 6070 return 0; 6071 6072 if (!skb_is_gso(skb)) 6073 return 0; 6074 6075 err = skb_cow_head(skb, 0); 6076 if (err < 0) 6077 return err; 6078 6079 ip.hdr = skb_network_header(skb); 6080 l4.hdr = skb_checksum_start(skb); 6081 6082 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6083 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6084 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6085 6086 /* initialize outer IP header fields */ 6087 if (ip.v4->version == 4) { 6088 unsigned char *csum_start = skb_checksum_start(skb); 6089 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6090 6091 /* IP header will have to cancel out any data that 6092 * is not a part of the outer IP header 6093 */ 6094 ip.v4->check = csum_fold(csum_partial(trans_start, 6095 csum_start - trans_start, 6096 0)); 6097 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6098 6099 ip.v4->tot_len = 0; 6100 first->tx_flags |= IGB_TX_FLAGS_TSO | 6101 IGB_TX_FLAGS_CSUM | 6102 IGB_TX_FLAGS_IPV4; 6103 } else { 6104 ip.v6->payload_len = 0; 6105 first->tx_flags |= IGB_TX_FLAGS_TSO | 6106 IGB_TX_FLAGS_CSUM; 6107 } 6108 6109 /* determine offset of inner transport header */ 6110 l4_offset = l4.hdr - skb->data; 6111 6112 /* remove payload length from inner checksum */ 6113 paylen = skb->len - l4_offset; 6114 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6115 /* compute length of segmentation header */ 6116 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6117 csum_replace_by_diff(&l4.tcp->check, 6118 (__force __wsum)htonl(paylen)); 6119 } else { 6120 /* compute length of segmentation header */ 6121 *hdr_len = sizeof(*l4.udp) + l4_offset; 6122 csum_replace_by_diff(&l4.udp->check, 6123 (__force __wsum)htonl(paylen)); 6124 } 6125 6126 /* update gso size and bytecount with header size */ 6127 first->gso_segs = skb_shinfo(skb)->gso_segs; 6128 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6129 6130 /* MSS L4LEN IDX */ 6131 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6132 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6133 6134 /* VLAN MACLEN IPLEN */ 6135 vlan_macip_lens = l4.hdr - ip.hdr; 6136 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6137 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6138 6139 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6140 type_tucmd, mss_l4len_idx); 6141 6142 return 1; 6143 } 6144 6145 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6146 { 6147 struct sk_buff *skb = first->skb; 6148 u32 vlan_macip_lens = 0; 6149 u32 type_tucmd = 0; 6150 6151 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6152 csum_failed: 6153 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6154 !tx_ring->launchtime_enable) 6155 return; 6156 goto no_csum; 6157 } 6158 6159 switch (skb->csum_offset) { 6160 case offsetof(struct tcphdr, check): 6161 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6162 fallthrough; 6163 case offsetof(struct udphdr, check): 6164 break; 6165 case offsetof(struct sctphdr, checksum): 6166 /* validate that this is actually an SCTP request */ 6167 if (skb_csum_is_sctp(skb)) { 6168 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6169 break; 6170 } 6171 fallthrough; 6172 default: 6173 skb_checksum_help(skb); 6174 goto csum_failed; 6175 } 6176 6177 /* update TX checksum flag */ 6178 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6179 vlan_macip_lens = skb_checksum_start_offset(skb) - 6180 skb_network_offset(skb); 6181 no_csum: 6182 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6183 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6184 6185 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6186 } 6187 6188 #define IGB_SET_FLAG(_input, _flag, _result) \ 6189 ((_flag <= _result) ? \ 6190 ((u32)(_input & _flag) * (_result / _flag)) : \ 6191 ((u32)(_input & _flag) / (_flag / _result))) 6192 6193 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6194 { 6195 /* set type for advanced descriptor with frame checksum insertion */ 6196 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6197 E1000_ADVTXD_DCMD_DEXT | 6198 E1000_ADVTXD_DCMD_IFCS; 6199 6200 /* set HW vlan bit if vlan is present */ 6201 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6202 (E1000_ADVTXD_DCMD_VLE)); 6203 6204 /* set segmentation bits for TSO */ 6205 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6206 (E1000_ADVTXD_DCMD_TSE)); 6207 6208 /* set timestamp bit if present */ 6209 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6210 (E1000_ADVTXD_MAC_TSTAMP)); 6211 6212 /* insert frame checksum */ 6213 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6214 6215 return cmd_type; 6216 } 6217 6218 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6219 union e1000_adv_tx_desc *tx_desc, 6220 u32 tx_flags, unsigned int paylen) 6221 { 6222 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6223 6224 /* 82575 requires a unique index per ring */ 6225 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6226 olinfo_status |= tx_ring->reg_idx << 4; 6227 6228 /* insert L4 checksum */ 6229 olinfo_status |= IGB_SET_FLAG(tx_flags, 6230 IGB_TX_FLAGS_CSUM, 6231 (E1000_TXD_POPTS_TXSM << 8)); 6232 6233 /* insert IPv4 checksum */ 6234 olinfo_status |= IGB_SET_FLAG(tx_flags, 6235 IGB_TX_FLAGS_IPV4, 6236 (E1000_TXD_POPTS_IXSM << 8)); 6237 6238 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6239 } 6240 6241 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6242 { 6243 struct net_device *netdev = tx_ring->netdev; 6244 6245 netif_stop_subqueue(netdev, tx_ring->queue_index); 6246 6247 /* Herbert's original patch had: 6248 * smp_mb__after_netif_stop_queue(); 6249 * but since that doesn't exist yet, just open code it. 6250 */ 6251 smp_mb(); 6252 6253 /* We need to check again in a case another CPU has just 6254 * made room available. 6255 */ 6256 if (igb_desc_unused(tx_ring) < size) 6257 return -EBUSY; 6258 6259 /* A reprieve! */ 6260 netif_wake_subqueue(netdev, tx_ring->queue_index); 6261 6262 u64_stats_update_begin(&tx_ring->tx_syncp2); 6263 tx_ring->tx_stats.restart_queue2++; 6264 u64_stats_update_end(&tx_ring->tx_syncp2); 6265 6266 return 0; 6267 } 6268 6269 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6270 { 6271 if (igb_desc_unused(tx_ring) >= size) 6272 return 0; 6273 return __igb_maybe_stop_tx(tx_ring, size); 6274 } 6275 6276 static int igb_tx_map(struct igb_ring *tx_ring, 6277 struct igb_tx_buffer *first, 6278 const u8 hdr_len) 6279 { 6280 struct sk_buff *skb = first->skb; 6281 struct igb_tx_buffer *tx_buffer; 6282 union e1000_adv_tx_desc *tx_desc; 6283 skb_frag_t *frag; 6284 dma_addr_t dma; 6285 unsigned int data_len, size; 6286 u32 tx_flags = first->tx_flags; 6287 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6288 u16 i = tx_ring->next_to_use; 6289 6290 tx_desc = IGB_TX_DESC(tx_ring, i); 6291 6292 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6293 6294 size = skb_headlen(skb); 6295 data_len = skb->data_len; 6296 6297 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6298 6299 tx_buffer = first; 6300 6301 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6302 if (dma_mapping_error(tx_ring->dev, dma)) 6303 goto dma_error; 6304 6305 /* record length, and DMA address */ 6306 dma_unmap_len_set(tx_buffer, len, size); 6307 dma_unmap_addr_set(tx_buffer, dma, dma); 6308 6309 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6310 6311 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6312 tx_desc->read.cmd_type_len = 6313 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6314 6315 i++; 6316 tx_desc++; 6317 if (i == tx_ring->count) { 6318 tx_desc = IGB_TX_DESC(tx_ring, 0); 6319 i = 0; 6320 } 6321 tx_desc->read.olinfo_status = 0; 6322 6323 dma += IGB_MAX_DATA_PER_TXD; 6324 size -= IGB_MAX_DATA_PER_TXD; 6325 6326 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6327 } 6328 6329 if (likely(!data_len)) 6330 break; 6331 6332 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6333 6334 i++; 6335 tx_desc++; 6336 if (i == tx_ring->count) { 6337 tx_desc = IGB_TX_DESC(tx_ring, 0); 6338 i = 0; 6339 } 6340 tx_desc->read.olinfo_status = 0; 6341 6342 size = skb_frag_size(frag); 6343 data_len -= size; 6344 6345 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6346 size, DMA_TO_DEVICE); 6347 6348 tx_buffer = &tx_ring->tx_buffer_info[i]; 6349 } 6350 6351 /* write last descriptor with RS and EOP bits */ 6352 cmd_type |= size | IGB_TXD_DCMD; 6353 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6354 6355 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6356 6357 /* set the timestamp */ 6358 first->time_stamp = jiffies; 6359 6360 skb_tx_timestamp(skb); 6361 6362 /* Force memory writes to complete before letting h/w know there 6363 * are new descriptors to fetch. (Only applicable for weak-ordered 6364 * memory model archs, such as IA-64). 6365 * 6366 * We also need this memory barrier to make certain all of the 6367 * status bits have been updated before next_to_watch is written. 6368 */ 6369 dma_wmb(); 6370 6371 /* set next_to_watch value indicating a packet is present */ 6372 first->next_to_watch = tx_desc; 6373 6374 i++; 6375 if (i == tx_ring->count) 6376 i = 0; 6377 6378 tx_ring->next_to_use = i; 6379 6380 /* Make sure there is space in the ring for the next send. */ 6381 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6382 6383 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6384 writel(i, tx_ring->tail); 6385 } 6386 return 0; 6387 6388 dma_error: 6389 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6390 tx_buffer = &tx_ring->tx_buffer_info[i]; 6391 6392 /* clear dma mappings for failed tx_buffer_info map */ 6393 while (tx_buffer != first) { 6394 if (dma_unmap_len(tx_buffer, len)) 6395 dma_unmap_page(tx_ring->dev, 6396 dma_unmap_addr(tx_buffer, dma), 6397 dma_unmap_len(tx_buffer, len), 6398 DMA_TO_DEVICE); 6399 dma_unmap_len_set(tx_buffer, len, 0); 6400 6401 if (i-- == 0) 6402 i += tx_ring->count; 6403 tx_buffer = &tx_ring->tx_buffer_info[i]; 6404 } 6405 6406 if (dma_unmap_len(tx_buffer, len)) 6407 dma_unmap_single(tx_ring->dev, 6408 dma_unmap_addr(tx_buffer, dma), 6409 dma_unmap_len(tx_buffer, len), 6410 DMA_TO_DEVICE); 6411 dma_unmap_len_set(tx_buffer, len, 0); 6412 6413 dev_kfree_skb_any(tx_buffer->skb); 6414 tx_buffer->skb = NULL; 6415 6416 tx_ring->next_to_use = i; 6417 6418 return -1; 6419 } 6420 6421 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6422 struct igb_ring *tx_ring, 6423 struct xdp_frame *xdpf) 6424 { 6425 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6426 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6427 u16 count, i, index = tx_ring->next_to_use; 6428 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6429 struct igb_tx_buffer *tx_buffer = tx_head; 6430 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6431 u32 len = xdpf->len, cmd_type, olinfo_status; 6432 void *data = xdpf->data; 6433 6434 count = TXD_USE_COUNT(len); 6435 for (i = 0; i < nr_frags; i++) 6436 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6437 6438 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6439 return IGB_XDP_CONSUMED; 6440 6441 i = 0; 6442 /* record the location of the first descriptor for this packet */ 6443 tx_head->bytecount = xdp_get_frame_len(xdpf); 6444 tx_head->type = IGB_TYPE_XDP; 6445 tx_head->gso_segs = 1; 6446 tx_head->xdpf = xdpf; 6447 6448 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6449 /* 82575 requires a unique index per ring */ 6450 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6451 olinfo_status |= tx_ring->reg_idx << 4; 6452 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6453 6454 for (;;) { 6455 dma_addr_t dma; 6456 6457 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6458 if (dma_mapping_error(tx_ring->dev, dma)) 6459 goto unmap; 6460 6461 /* record length, and DMA address */ 6462 dma_unmap_len_set(tx_buffer, len, len); 6463 dma_unmap_addr_set(tx_buffer, dma, dma); 6464 6465 /* put descriptor type bits */ 6466 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6467 E1000_ADVTXD_DCMD_IFCS | len; 6468 6469 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6470 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6471 6472 tx_buffer->protocol = 0; 6473 6474 if (++index == tx_ring->count) 6475 index = 0; 6476 6477 if (i == nr_frags) 6478 break; 6479 6480 tx_buffer = &tx_ring->tx_buffer_info[index]; 6481 tx_desc = IGB_TX_DESC(tx_ring, index); 6482 tx_desc->read.olinfo_status = 0; 6483 6484 data = skb_frag_address(&sinfo->frags[i]); 6485 len = skb_frag_size(&sinfo->frags[i]); 6486 i++; 6487 } 6488 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6489 6490 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6491 /* set the timestamp */ 6492 tx_head->time_stamp = jiffies; 6493 6494 /* Avoid any potential race with xdp_xmit and cleanup */ 6495 smp_wmb(); 6496 6497 /* set next_to_watch value indicating a packet is present */ 6498 tx_head->next_to_watch = tx_desc; 6499 tx_ring->next_to_use = index; 6500 6501 /* Make sure there is space in the ring for the next send. */ 6502 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6503 6504 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6505 writel(index, tx_ring->tail); 6506 6507 return IGB_XDP_TX; 6508 6509 unmap: 6510 for (;;) { 6511 tx_buffer = &tx_ring->tx_buffer_info[index]; 6512 if (dma_unmap_len(tx_buffer, len)) 6513 dma_unmap_page(tx_ring->dev, 6514 dma_unmap_addr(tx_buffer, dma), 6515 dma_unmap_len(tx_buffer, len), 6516 DMA_TO_DEVICE); 6517 dma_unmap_len_set(tx_buffer, len, 0); 6518 if (tx_buffer == tx_head) 6519 break; 6520 6521 if (!index) 6522 index += tx_ring->count; 6523 index--; 6524 } 6525 6526 return IGB_XDP_CONSUMED; 6527 } 6528 6529 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6530 struct igb_ring *tx_ring) 6531 { 6532 struct igb_tx_buffer *first; 6533 int tso; 6534 u32 tx_flags = 0; 6535 unsigned short f; 6536 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6537 __be16 protocol = vlan_get_protocol(skb); 6538 u8 hdr_len = 0; 6539 6540 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6541 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6542 * + 2 desc gap to keep tail from touching head, 6543 * + 1 desc for context descriptor, 6544 * otherwise try next time 6545 */ 6546 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6547 count += TXD_USE_COUNT(skb_frag_size( 6548 &skb_shinfo(skb)->frags[f])); 6549 6550 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6551 /* this is a hard error */ 6552 return NETDEV_TX_BUSY; 6553 } 6554 6555 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6556 return NETDEV_TX_BUSY; 6557 6558 /* record the location of the first descriptor for this packet */ 6559 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6560 first->type = IGB_TYPE_SKB; 6561 first->skb = skb; 6562 first->bytecount = skb->len; 6563 first->gso_segs = 1; 6564 6565 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6566 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6567 6568 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6569 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6570 &adapter->state)) { 6571 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6572 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6573 6574 adapter->ptp_tx_skb = skb_get(skb); 6575 adapter->ptp_tx_start = jiffies; 6576 if (adapter->hw.mac.type == e1000_82576) 6577 schedule_work(&adapter->ptp_tx_work); 6578 } else { 6579 adapter->tx_hwtstamp_skipped++; 6580 } 6581 } 6582 6583 if (skb_vlan_tag_present(skb)) { 6584 tx_flags |= IGB_TX_FLAGS_VLAN; 6585 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6586 } 6587 6588 /* record initial flags and protocol */ 6589 first->tx_flags = tx_flags; 6590 first->protocol = protocol; 6591 6592 tso = igb_tso(tx_ring, first, &hdr_len); 6593 if (tso < 0) 6594 goto out_drop; 6595 else if (!tso) 6596 igb_tx_csum(tx_ring, first); 6597 6598 if (igb_tx_map(tx_ring, first, hdr_len)) 6599 goto cleanup_tx_tstamp; 6600 6601 return NETDEV_TX_OK; 6602 6603 out_drop: 6604 dev_kfree_skb_any(first->skb); 6605 first->skb = NULL; 6606 cleanup_tx_tstamp: 6607 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6608 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6609 6610 dev_kfree_skb_any(adapter->ptp_tx_skb); 6611 adapter->ptp_tx_skb = NULL; 6612 if (adapter->hw.mac.type == e1000_82576) 6613 cancel_work_sync(&adapter->ptp_tx_work); 6614 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6615 } 6616 6617 return NETDEV_TX_OK; 6618 } 6619 6620 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6621 struct sk_buff *skb) 6622 { 6623 unsigned int r_idx = skb->queue_mapping; 6624 6625 if (r_idx >= adapter->num_tx_queues) 6626 r_idx = r_idx % adapter->num_tx_queues; 6627 6628 return adapter->tx_ring[r_idx]; 6629 } 6630 6631 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6632 struct net_device *netdev) 6633 { 6634 struct igb_adapter *adapter = netdev_priv(netdev); 6635 6636 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6637 * in order to meet this minimum size requirement. 6638 */ 6639 if (skb_put_padto(skb, 17)) 6640 return NETDEV_TX_OK; 6641 6642 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6643 } 6644 6645 /** 6646 * igb_tx_timeout - Respond to a Tx Hang 6647 * @netdev: network interface device structure 6648 * @txqueue: number of the Tx queue that hung (unused) 6649 **/ 6650 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6651 { 6652 struct igb_adapter *adapter = netdev_priv(netdev); 6653 struct e1000_hw *hw = &adapter->hw; 6654 6655 /* Do the reset outside of interrupt context */ 6656 adapter->tx_timeout_count++; 6657 6658 if (hw->mac.type >= e1000_82580) 6659 hw->dev_spec._82575.global_device_reset = true; 6660 6661 schedule_work(&adapter->reset_task); 6662 wr32(E1000_EICS, 6663 (adapter->eims_enable_mask & ~adapter->eims_other)); 6664 } 6665 6666 static void igb_reset_task(struct work_struct *work) 6667 { 6668 struct igb_adapter *adapter; 6669 adapter = container_of(work, struct igb_adapter, reset_task); 6670 6671 rtnl_lock(); 6672 /* If we're already down or resetting, just bail */ 6673 if (test_bit(__IGB_DOWN, &adapter->state) || 6674 test_bit(__IGB_RESETTING, &adapter->state)) { 6675 rtnl_unlock(); 6676 return; 6677 } 6678 6679 igb_dump(adapter); 6680 netdev_err(adapter->netdev, "Reset adapter\n"); 6681 igb_reinit_locked(adapter); 6682 rtnl_unlock(); 6683 } 6684 6685 /** 6686 * igb_get_stats64 - Get System Network Statistics 6687 * @netdev: network interface device structure 6688 * @stats: rtnl_link_stats64 pointer 6689 **/ 6690 static void igb_get_stats64(struct net_device *netdev, 6691 struct rtnl_link_stats64 *stats) 6692 { 6693 struct igb_adapter *adapter = netdev_priv(netdev); 6694 6695 spin_lock(&adapter->stats64_lock); 6696 igb_update_stats(adapter); 6697 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6698 spin_unlock(&adapter->stats64_lock); 6699 } 6700 6701 /** 6702 * igb_change_mtu - Change the Maximum Transfer Unit 6703 * @netdev: network interface device structure 6704 * @new_mtu: new value for maximum frame size 6705 * 6706 * Returns 0 on success, negative on failure 6707 **/ 6708 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6709 { 6710 struct igb_adapter *adapter = netdev_priv(netdev); 6711 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6712 6713 if (igb_xdp_is_enabled(adapter)) { 6714 int i; 6715 6716 for (i = 0; i < adapter->num_rx_queues; i++) { 6717 struct igb_ring *ring = adapter->rx_ring[i]; 6718 6719 if (max_frame > igb_rx_bufsz(ring)) { 6720 netdev_warn(adapter->netdev, 6721 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6722 max_frame); 6723 return -EINVAL; 6724 } 6725 } 6726 } 6727 6728 /* adjust max frame to be at least the size of a standard frame */ 6729 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6730 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6731 6732 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6733 usleep_range(1000, 2000); 6734 6735 /* igb_down has a dependency on max_frame_size */ 6736 adapter->max_frame_size = max_frame; 6737 6738 if (netif_running(netdev)) 6739 igb_down(adapter); 6740 6741 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6742 netdev->mtu, new_mtu); 6743 WRITE_ONCE(netdev->mtu, new_mtu); 6744 6745 if (netif_running(netdev)) 6746 igb_up(adapter); 6747 else 6748 igb_reset(adapter); 6749 6750 clear_bit(__IGB_RESETTING, &adapter->state); 6751 6752 return 0; 6753 } 6754 6755 /** 6756 * igb_update_stats - Update the board statistics counters 6757 * @adapter: board private structure 6758 **/ 6759 void igb_update_stats(struct igb_adapter *adapter) 6760 { 6761 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6762 struct e1000_hw *hw = &adapter->hw; 6763 struct pci_dev *pdev = adapter->pdev; 6764 u32 reg, mpc; 6765 int i; 6766 u64 bytes, packets; 6767 unsigned int start; 6768 u64 _bytes, _packets; 6769 6770 /* Prevent stats update while adapter is being reset, or if the pci 6771 * connection is down. 6772 */ 6773 if (adapter->link_speed == 0) 6774 return; 6775 if (pci_channel_offline(pdev)) 6776 return; 6777 6778 bytes = 0; 6779 packets = 0; 6780 6781 rcu_read_lock(); 6782 for (i = 0; i < adapter->num_rx_queues; i++) { 6783 struct igb_ring *ring = adapter->rx_ring[i]; 6784 u32 rqdpc = rd32(E1000_RQDPC(i)); 6785 if (hw->mac.type >= e1000_i210) 6786 wr32(E1000_RQDPC(i), 0); 6787 6788 if (rqdpc) { 6789 ring->rx_stats.drops += rqdpc; 6790 net_stats->rx_fifo_errors += rqdpc; 6791 } 6792 6793 do { 6794 start = u64_stats_fetch_begin(&ring->rx_syncp); 6795 _bytes = ring->rx_stats.bytes; 6796 _packets = ring->rx_stats.packets; 6797 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6798 bytes += _bytes; 6799 packets += _packets; 6800 } 6801 6802 net_stats->rx_bytes = bytes; 6803 net_stats->rx_packets = packets; 6804 6805 bytes = 0; 6806 packets = 0; 6807 for (i = 0; i < adapter->num_tx_queues; i++) { 6808 struct igb_ring *ring = adapter->tx_ring[i]; 6809 do { 6810 start = u64_stats_fetch_begin(&ring->tx_syncp); 6811 _bytes = ring->tx_stats.bytes; 6812 _packets = ring->tx_stats.packets; 6813 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6814 bytes += _bytes; 6815 packets += _packets; 6816 } 6817 net_stats->tx_bytes = bytes; 6818 net_stats->tx_packets = packets; 6819 rcu_read_unlock(); 6820 6821 /* read stats registers */ 6822 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6823 adapter->stats.gprc += rd32(E1000_GPRC); 6824 adapter->stats.gorc += rd32(E1000_GORCL); 6825 rd32(E1000_GORCH); /* clear GORCL */ 6826 adapter->stats.bprc += rd32(E1000_BPRC); 6827 adapter->stats.mprc += rd32(E1000_MPRC); 6828 adapter->stats.roc += rd32(E1000_ROC); 6829 6830 adapter->stats.prc64 += rd32(E1000_PRC64); 6831 adapter->stats.prc127 += rd32(E1000_PRC127); 6832 adapter->stats.prc255 += rd32(E1000_PRC255); 6833 adapter->stats.prc511 += rd32(E1000_PRC511); 6834 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6835 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6836 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6837 adapter->stats.sec += rd32(E1000_SEC); 6838 6839 mpc = rd32(E1000_MPC); 6840 adapter->stats.mpc += mpc; 6841 net_stats->rx_fifo_errors += mpc; 6842 adapter->stats.scc += rd32(E1000_SCC); 6843 adapter->stats.ecol += rd32(E1000_ECOL); 6844 adapter->stats.mcc += rd32(E1000_MCC); 6845 adapter->stats.latecol += rd32(E1000_LATECOL); 6846 adapter->stats.dc += rd32(E1000_DC); 6847 adapter->stats.rlec += rd32(E1000_RLEC); 6848 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6849 adapter->stats.xontxc += rd32(E1000_XONTXC); 6850 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6851 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6852 adapter->stats.fcruc += rd32(E1000_FCRUC); 6853 adapter->stats.gptc += rd32(E1000_GPTC); 6854 adapter->stats.gotc += rd32(E1000_GOTCL); 6855 rd32(E1000_GOTCH); /* clear GOTCL */ 6856 adapter->stats.rnbc += rd32(E1000_RNBC); 6857 adapter->stats.ruc += rd32(E1000_RUC); 6858 adapter->stats.rfc += rd32(E1000_RFC); 6859 adapter->stats.rjc += rd32(E1000_RJC); 6860 adapter->stats.tor += rd32(E1000_TORH); 6861 adapter->stats.tot += rd32(E1000_TOTH); 6862 adapter->stats.tpr += rd32(E1000_TPR); 6863 6864 adapter->stats.ptc64 += rd32(E1000_PTC64); 6865 adapter->stats.ptc127 += rd32(E1000_PTC127); 6866 adapter->stats.ptc255 += rd32(E1000_PTC255); 6867 adapter->stats.ptc511 += rd32(E1000_PTC511); 6868 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6869 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6870 6871 adapter->stats.mptc += rd32(E1000_MPTC); 6872 adapter->stats.bptc += rd32(E1000_BPTC); 6873 6874 adapter->stats.tpt += rd32(E1000_TPT); 6875 adapter->stats.colc += rd32(E1000_COLC); 6876 6877 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6878 /* read internal phy specific stats */ 6879 reg = rd32(E1000_CTRL_EXT); 6880 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6881 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6882 6883 /* this stat has invalid values on i210/i211 */ 6884 if ((hw->mac.type != e1000_i210) && 6885 (hw->mac.type != e1000_i211)) 6886 adapter->stats.tncrs += rd32(E1000_TNCRS); 6887 } 6888 6889 adapter->stats.tsctc += rd32(E1000_TSCTC); 6890 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6891 6892 adapter->stats.iac += rd32(E1000_IAC); 6893 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6894 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6895 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6896 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6897 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6898 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6899 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6900 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6901 6902 /* Fill out the OS statistics structure */ 6903 net_stats->multicast = adapter->stats.mprc; 6904 net_stats->collisions = adapter->stats.colc; 6905 6906 /* Rx Errors */ 6907 6908 /* RLEC on some newer hardware can be incorrect so build 6909 * our own version based on RUC and ROC 6910 */ 6911 net_stats->rx_errors = adapter->stats.rxerrc + 6912 adapter->stats.crcerrs + adapter->stats.algnerrc + 6913 adapter->stats.ruc + adapter->stats.roc + 6914 adapter->stats.cexterr; 6915 net_stats->rx_length_errors = adapter->stats.ruc + 6916 adapter->stats.roc; 6917 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6918 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6919 net_stats->rx_missed_errors = adapter->stats.mpc; 6920 6921 /* Tx Errors */ 6922 net_stats->tx_errors = adapter->stats.ecol + 6923 adapter->stats.latecol; 6924 net_stats->tx_aborted_errors = adapter->stats.ecol; 6925 net_stats->tx_window_errors = adapter->stats.latecol; 6926 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6927 6928 /* Tx Dropped needs to be maintained elsewhere */ 6929 6930 /* Management Stats */ 6931 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6932 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6933 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6934 6935 /* OS2BMC Stats */ 6936 reg = rd32(E1000_MANC); 6937 if (reg & E1000_MANC_EN_BMC2OS) { 6938 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6939 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6940 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6941 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6942 } 6943 } 6944 6945 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6946 { 6947 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6948 struct e1000_hw *hw = &adapter->hw; 6949 struct timespec64 ts; 6950 u32 tsauxc; 6951 6952 if (pin < 0 || pin >= IGB_N_SDP) 6953 return; 6954 6955 spin_lock(&adapter->tmreg_lock); 6956 6957 if (hw->mac.type == e1000_82580 || 6958 hw->mac.type == e1000_i354 || 6959 hw->mac.type == e1000_i350) { 6960 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6961 u32 systiml, systimh, level_mask, level, rem; 6962 u64 systim, now; 6963 6964 /* read systim registers in sequence */ 6965 rd32(E1000_SYSTIMR); 6966 systiml = rd32(E1000_SYSTIML); 6967 systimh = rd32(E1000_SYSTIMH); 6968 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6969 now = timecounter_cyc2time(&adapter->tc, systim); 6970 6971 if (pin < 2) { 6972 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6973 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6974 } else { 6975 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6976 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6977 } 6978 6979 div_u64_rem(now, ns, &rem); 6980 systim = systim + (ns - rem); 6981 6982 /* synchronize pin level with rising/falling edges */ 6983 div_u64_rem(now, ns << 1, &rem); 6984 if (rem < ns) { 6985 /* first half of period */ 6986 if (level == 0) { 6987 /* output is already low, skip this period */ 6988 systim += ns; 6989 pr_notice("igb: periodic output on %s missed falling edge\n", 6990 adapter->sdp_config[pin].name); 6991 } 6992 } else { 6993 /* second half of period */ 6994 if (level == 1) { 6995 /* output is already high, skip this period */ 6996 systim += ns; 6997 pr_notice("igb: periodic output on %s missed rising edge\n", 6998 adapter->sdp_config[pin].name); 6999 } 7000 } 7001 7002 /* for this chip family tv_sec is the upper part of the binary value, 7003 * so not seconds 7004 */ 7005 ts.tv_nsec = (u32)systim; 7006 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 7007 } else { 7008 ts = timespec64_add(adapter->perout[tsintr_tt].start, 7009 adapter->perout[tsintr_tt].period); 7010 } 7011 7012 /* u32 conversion of tv_sec is safe until y2106 */ 7013 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 7014 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 7015 tsauxc = rd32(E1000_TSAUXC); 7016 tsauxc |= TSAUXC_EN_TT0; 7017 wr32(E1000_TSAUXC, tsauxc); 7018 adapter->perout[tsintr_tt].start = ts; 7019 7020 spin_unlock(&adapter->tmreg_lock); 7021 } 7022 7023 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 7024 { 7025 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 7026 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 7027 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 7028 struct e1000_hw *hw = &adapter->hw; 7029 struct ptp_clock_event event; 7030 struct timespec64 ts; 7031 unsigned long flags; 7032 7033 if (pin < 0 || pin >= IGB_N_SDP) 7034 return; 7035 7036 if (hw->mac.type == e1000_82580 || 7037 hw->mac.type == e1000_i354 || 7038 hw->mac.type == e1000_i350) { 7039 u64 ns = rd32(auxstmpl); 7040 7041 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 7042 spin_lock_irqsave(&adapter->tmreg_lock, flags); 7043 ns = timecounter_cyc2time(&adapter->tc, ns); 7044 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 7045 ts = ns_to_timespec64(ns); 7046 } else { 7047 ts.tv_nsec = rd32(auxstmpl); 7048 ts.tv_sec = rd32(auxstmph); 7049 } 7050 7051 event.type = PTP_CLOCK_EXTTS; 7052 event.index = tsintr_tt; 7053 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7054 ptp_clock_event(adapter->ptp_clock, &event); 7055 } 7056 7057 static void igb_tsync_interrupt(struct igb_adapter *adapter) 7058 { 7059 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7060 TSINTR_TT0 | TSINTR_TT1 | 7061 TSINTR_AUTT0 | TSINTR_AUTT1); 7062 struct e1000_hw *hw = &adapter->hw; 7063 u32 tsicr = rd32(E1000_TSICR); 7064 struct ptp_clock_event event; 7065 7066 if (hw->mac.type == e1000_82580) { 7067 /* 82580 has a hardware bug that requires an explicit 7068 * write to clear the TimeSync interrupt cause. 7069 */ 7070 wr32(E1000_TSICR, tsicr & mask); 7071 } 7072 7073 if (tsicr & TSINTR_SYS_WRAP) { 7074 event.type = PTP_CLOCK_PPS; 7075 if (adapter->ptp_caps.pps) 7076 ptp_clock_event(adapter->ptp_clock, &event); 7077 } 7078 7079 if (tsicr & E1000_TSICR_TXTS) { 7080 /* retrieve hardware timestamp */ 7081 schedule_work(&adapter->ptp_tx_work); 7082 } 7083 7084 if (tsicr & TSINTR_TT0) 7085 igb_perout(adapter, 0); 7086 7087 if (tsicr & TSINTR_TT1) 7088 igb_perout(adapter, 1); 7089 7090 if (tsicr & TSINTR_AUTT0) 7091 igb_extts(adapter, 0); 7092 7093 if (tsicr & TSINTR_AUTT1) 7094 igb_extts(adapter, 1); 7095 } 7096 7097 static irqreturn_t igb_msix_other(int irq, void *data) 7098 { 7099 struct igb_adapter *adapter = data; 7100 struct e1000_hw *hw = &adapter->hw; 7101 u32 icr = rd32(E1000_ICR); 7102 /* reading ICR causes bit 31 of EICR to be cleared */ 7103 7104 if (icr & E1000_ICR_DRSTA) 7105 schedule_work(&adapter->reset_task); 7106 7107 if (icr & E1000_ICR_DOUTSYNC) { 7108 /* HW is reporting DMA is out of sync */ 7109 adapter->stats.doosync++; 7110 /* The DMA Out of Sync is also indication of a spoof event 7111 * in IOV mode. Check the Wrong VM Behavior register to 7112 * see if it is really a spoof event. 7113 */ 7114 igb_check_wvbr(adapter); 7115 } 7116 7117 /* Check for a mailbox event */ 7118 if (icr & E1000_ICR_VMMB) 7119 igb_msg_task(adapter); 7120 7121 if (icr & E1000_ICR_LSC) { 7122 hw->mac.get_link_status = 1; 7123 /* guard against interrupt when we're going down */ 7124 if (!test_bit(__IGB_DOWN, &adapter->state)) 7125 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7126 } 7127 7128 if (icr & E1000_ICR_TS) 7129 igb_tsync_interrupt(adapter); 7130 7131 wr32(E1000_EIMS, adapter->eims_other); 7132 7133 return IRQ_HANDLED; 7134 } 7135 7136 static void igb_write_itr(struct igb_q_vector *q_vector) 7137 { 7138 struct igb_adapter *adapter = q_vector->adapter; 7139 u32 itr_val = q_vector->itr_val & 0x7FFC; 7140 7141 if (!q_vector->set_itr) 7142 return; 7143 7144 if (!itr_val) 7145 itr_val = 0x4; 7146 7147 if (adapter->hw.mac.type == e1000_82575) 7148 itr_val |= itr_val << 16; 7149 else 7150 itr_val |= E1000_EITR_CNT_IGNR; 7151 7152 writel(itr_val, q_vector->itr_register); 7153 q_vector->set_itr = 0; 7154 } 7155 7156 static irqreturn_t igb_msix_ring(int irq, void *data) 7157 { 7158 struct igb_q_vector *q_vector = data; 7159 7160 /* Write the ITR value calculated from the previous interrupt. */ 7161 igb_write_itr(q_vector); 7162 7163 napi_schedule(&q_vector->napi); 7164 7165 return IRQ_HANDLED; 7166 } 7167 7168 #ifdef CONFIG_IGB_DCA 7169 static void igb_update_tx_dca(struct igb_adapter *adapter, 7170 struct igb_ring *tx_ring, 7171 int cpu) 7172 { 7173 struct e1000_hw *hw = &adapter->hw; 7174 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7175 7176 if (hw->mac.type != e1000_82575) 7177 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7178 7179 /* We can enable relaxed ordering for reads, but not writes when 7180 * DCA is enabled. This is due to a known issue in some chipsets 7181 * which will cause the DCA tag to be cleared. 7182 */ 7183 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7184 E1000_DCA_TXCTRL_DATA_RRO_EN | 7185 E1000_DCA_TXCTRL_DESC_DCA_EN; 7186 7187 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7188 } 7189 7190 static void igb_update_rx_dca(struct igb_adapter *adapter, 7191 struct igb_ring *rx_ring, 7192 int cpu) 7193 { 7194 struct e1000_hw *hw = &adapter->hw; 7195 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7196 7197 if (hw->mac.type != e1000_82575) 7198 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7199 7200 /* We can enable relaxed ordering for reads, but not writes when 7201 * DCA is enabled. This is due to a known issue in some chipsets 7202 * which will cause the DCA tag to be cleared. 7203 */ 7204 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7205 E1000_DCA_RXCTRL_DESC_DCA_EN; 7206 7207 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7208 } 7209 7210 static void igb_update_dca(struct igb_q_vector *q_vector) 7211 { 7212 struct igb_adapter *adapter = q_vector->adapter; 7213 int cpu = get_cpu(); 7214 7215 if (q_vector->cpu == cpu) 7216 goto out_no_update; 7217 7218 if (q_vector->tx.ring) 7219 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7220 7221 if (q_vector->rx.ring) 7222 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7223 7224 q_vector->cpu = cpu; 7225 out_no_update: 7226 put_cpu(); 7227 } 7228 7229 static void igb_setup_dca(struct igb_adapter *adapter) 7230 { 7231 struct e1000_hw *hw = &adapter->hw; 7232 int i; 7233 7234 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7235 return; 7236 7237 /* Always use CB2 mode, difference is masked in the CB driver. */ 7238 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7239 7240 for (i = 0; i < adapter->num_q_vectors; i++) { 7241 adapter->q_vector[i]->cpu = -1; 7242 igb_update_dca(adapter->q_vector[i]); 7243 } 7244 } 7245 7246 static int __igb_notify_dca(struct device *dev, void *data) 7247 { 7248 struct net_device *netdev = dev_get_drvdata(dev); 7249 struct igb_adapter *adapter = netdev_priv(netdev); 7250 struct pci_dev *pdev = adapter->pdev; 7251 struct e1000_hw *hw = &adapter->hw; 7252 unsigned long event = *(unsigned long *)data; 7253 7254 switch (event) { 7255 case DCA_PROVIDER_ADD: 7256 /* if already enabled, don't do it again */ 7257 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7258 break; 7259 if (dca_add_requester(dev) == 0) { 7260 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7261 dev_info(&pdev->dev, "DCA enabled\n"); 7262 igb_setup_dca(adapter); 7263 break; 7264 } 7265 fallthrough; /* since DCA is disabled. */ 7266 case DCA_PROVIDER_REMOVE: 7267 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7268 /* without this a class_device is left 7269 * hanging around in the sysfs model 7270 */ 7271 dca_remove_requester(dev); 7272 dev_info(&pdev->dev, "DCA disabled\n"); 7273 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7274 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7275 } 7276 break; 7277 } 7278 7279 return 0; 7280 } 7281 7282 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7283 void *p) 7284 { 7285 int ret_val; 7286 7287 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7288 __igb_notify_dca); 7289 7290 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7291 } 7292 #endif /* CONFIG_IGB_DCA */ 7293 7294 #ifdef CONFIG_PCI_IOV 7295 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7296 { 7297 unsigned char mac_addr[ETH_ALEN]; 7298 7299 eth_zero_addr(mac_addr); 7300 igb_set_vf_mac(adapter, vf, mac_addr); 7301 7302 /* By default spoof check is enabled for all VFs */ 7303 adapter->vf_data[vf].spoofchk_enabled = true; 7304 7305 /* By default VFs are not trusted */ 7306 adapter->vf_data[vf].trusted = false; 7307 7308 return 0; 7309 } 7310 7311 #endif 7312 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7313 { 7314 struct e1000_hw *hw = &adapter->hw; 7315 u32 ping; 7316 int i; 7317 7318 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7319 ping = E1000_PF_CONTROL_MSG; 7320 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7321 ping |= E1000_VT_MSGTYPE_CTS; 7322 igb_write_mbx(hw, &ping, 1, i); 7323 } 7324 } 7325 7326 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7327 { 7328 struct e1000_hw *hw = &adapter->hw; 7329 u32 vmolr = rd32(E1000_VMOLR(vf)); 7330 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7331 7332 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7333 IGB_VF_FLAG_MULTI_PROMISC); 7334 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7335 7336 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7337 vmolr |= E1000_VMOLR_MPME; 7338 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7339 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7340 } else { 7341 /* if we have hashes and we are clearing a multicast promisc 7342 * flag we need to write the hashes to the MTA as this step 7343 * was previously skipped 7344 */ 7345 if (vf_data->num_vf_mc_hashes > 30) { 7346 vmolr |= E1000_VMOLR_MPME; 7347 } else if (vf_data->num_vf_mc_hashes) { 7348 int j; 7349 7350 vmolr |= E1000_VMOLR_ROMPE; 7351 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7352 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7353 } 7354 } 7355 7356 wr32(E1000_VMOLR(vf), vmolr); 7357 7358 /* there are flags left unprocessed, likely not supported */ 7359 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7360 return -EINVAL; 7361 7362 return 0; 7363 } 7364 7365 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7366 u32 *msgbuf, u32 vf) 7367 { 7368 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7369 u16 *hash_list = (u16 *)&msgbuf[1]; 7370 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7371 int i; 7372 7373 /* salt away the number of multicast addresses assigned 7374 * to this VF for later use to restore when the PF multi cast 7375 * list changes 7376 */ 7377 vf_data->num_vf_mc_hashes = n; 7378 7379 /* only up to 30 hash values supported */ 7380 if (n > 30) 7381 n = 30; 7382 7383 /* store the hashes for later use */ 7384 for (i = 0; i < n; i++) 7385 vf_data->vf_mc_hashes[i] = hash_list[i]; 7386 7387 /* Flush and reset the mta with the new values */ 7388 igb_set_rx_mode(adapter->netdev); 7389 7390 return 0; 7391 } 7392 7393 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7394 { 7395 struct e1000_hw *hw = &adapter->hw; 7396 struct vf_data_storage *vf_data; 7397 int i, j; 7398 7399 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7400 u32 vmolr = rd32(E1000_VMOLR(i)); 7401 7402 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7403 7404 vf_data = &adapter->vf_data[i]; 7405 7406 if ((vf_data->num_vf_mc_hashes > 30) || 7407 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7408 vmolr |= E1000_VMOLR_MPME; 7409 } else if (vf_data->num_vf_mc_hashes) { 7410 vmolr |= E1000_VMOLR_ROMPE; 7411 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7412 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7413 } 7414 wr32(E1000_VMOLR(i), vmolr); 7415 } 7416 } 7417 7418 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7419 { 7420 struct e1000_hw *hw = &adapter->hw; 7421 u32 pool_mask, vlvf_mask, i; 7422 7423 /* create mask for VF and other pools */ 7424 pool_mask = E1000_VLVF_POOLSEL_MASK; 7425 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7426 7427 /* drop PF from pool bits */ 7428 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7429 adapter->vfs_allocated_count); 7430 7431 /* Find the vlan filter for this id */ 7432 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7433 u32 vlvf = rd32(E1000_VLVF(i)); 7434 u32 vfta_mask, vid, vfta; 7435 7436 /* remove the vf from the pool */ 7437 if (!(vlvf & vlvf_mask)) 7438 continue; 7439 7440 /* clear out bit from VLVF */ 7441 vlvf ^= vlvf_mask; 7442 7443 /* if other pools are present, just remove ourselves */ 7444 if (vlvf & pool_mask) 7445 goto update_vlvfb; 7446 7447 /* if PF is present, leave VFTA */ 7448 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7449 goto update_vlvf; 7450 7451 vid = vlvf & E1000_VLVF_VLANID_MASK; 7452 vfta_mask = BIT(vid % 32); 7453 7454 /* clear bit from VFTA */ 7455 vfta = adapter->shadow_vfta[vid / 32]; 7456 if (vfta & vfta_mask) 7457 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7458 update_vlvf: 7459 /* clear pool selection enable */ 7460 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7461 vlvf &= E1000_VLVF_POOLSEL_MASK; 7462 else 7463 vlvf = 0; 7464 update_vlvfb: 7465 /* clear pool bits */ 7466 wr32(E1000_VLVF(i), vlvf); 7467 } 7468 } 7469 7470 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7471 { 7472 u32 vlvf; 7473 int idx; 7474 7475 /* short cut the special case */ 7476 if (vlan == 0) 7477 return 0; 7478 7479 /* Search for the VLAN id in the VLVF entries */ 7480 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7481 vlvf = rd32(E1000_VLVF(idx)); 7482 if ((vlvf & VLAN_VID_MASK) == vlan) 7483 break; 7484 } 7485 7486 return idx; 7487 } 7488 7489 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7490 { 7491 struct e1000_hw *hw = &adapter->hw; 7492 u32 bits, pf_id; 7493 int idx; 7494 7495 idx = igb_find_vlvf_entry(hw, vid); 7496 if (!idx) 7497 return; 7498 7499 /* See if any other pools are set for this VLAN filter 7500 * entry other than the PF. 7501 */ 7502 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7503 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7504 bits &= rd32(E1000_VLVF(idx)); 7505 7506 /* Disable the filter so this falls into the default pool. */ 7507 if (!bits) { 7508 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7509 wr32(E1000_VLVF(idx), BIT(pf_id)); 7510 else 7511 wr32(E1000_VLVF(idx), 0); 7512 } 7513 } 7514 7515 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7516 bool add, u32 vf) 7517 { 7518 int pf_id = adapter->vfs_allocated_count; 7519 struct e1000_hw *hw = &adapter->hw; 7520 int err; 7521 7522 /* If VLAN overlaps with one the PF is currently monitoring make 7523 * sure that we are able to allocate a VLVF entry. This may be 7524 * redundant but it guarantees PF will maintain visibility to 7525 * the VLAN. 7526 */ 7527 if (add && test_bit(vid, adapter->active_vlans)) { 7528 err = igb_vfta_set(hw, vid, pf_id, true, false); 7529 if (err) 7530 return err; 7531 } 7532 7533 err = igb_vfta_set(hw, vid, vf, add, false); 7534 7535 if (add && !err) 7536 return err; 7537 7538 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7539 * we may need to drop the PF pool bit in order to allow us to free 7540 * up the VLVF resources. 7541 */ 7542 if (test_bit(vid, adapter->active_vlans) || 7543 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7544 igb_update_pf_vlvf(adapter, vid); 7545 7546 return err; 7547 } 7548 7549 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7550 { 7551 struct e1000_hw *hw = &adapter->hw; 7552 7553 if (vid) 7554 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7555 else 7556 wr32(E1000_VMVIR(vf), 0); 7557 } 7558 7559 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7560 u16 vlan, u8 qos) 7561 { 7562 int err; 7563 7564 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7565 if (err) 7566 return err; 7567 7568 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7569 igb_set_vmolr(adapter, vf, !vlan); 7570 7571 /* revoke access to previous VLAN */ 7572 if (vlan != adapter->vf_data[vf].pf_vlan) 7573 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7574 false, vf); 7575 7576 adapter->vf_data[vf].pf_vlan = vlan; 7577 adapter->vf_data[vf].pf_qos = qos; 7578 igb_set_vf_vlan_strip(adapter, vf, true); 7579 dev_info(&adapter->pdev->dev, 7580 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7581 if (test_bit(__IGB_DOWN, &adapter->state)) { 7582 dev_warn(&adapter->pdev->dev, 7583 "The VF VLAN has been set, but the PF device is not up.\n"); 7584 dev_warn(&adapter->pdev->dev, 7585 "Bring the PF device up before attempting to use the VF device.\n"); 7586 } 7587 7588 return err; 7589 } 7590 7591 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7592 { 7593 /* Restore tagless access via VLAN 0 */ 7594 igb_set_vf_vlan(adapter, 0, true, vf); 7595 7596 igb_set_vmvir(adapter, 0, vf); 7597 igb_set_vmolr(adapter, vf, true); 7598 7599 /* Remove any PF assigned VLAN */ 7600 if (adapter->vf_data[vf].pf_vlan) 7601 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7602 false, vf); 7603 7604 adapter->vf_data[vf].pf_vlan = 0; 7605 adapter->vf_data[vf].pf_qos = 0; 7606 igb_set_vf_vlan_strip(adapter, vf, false); 7607 7608 return 0; 7609 } 7610 7611 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7612 u16 vlan, u8 qos, __be16 vlan_proto) 7613 { 7614 struct igb_adapter *adapter = netdev_priv(netdev); 7615 7616 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7617 return -EINVAL; 7618 7619 if (vlan_proto != htons(ETH_P_8021Q)) 7620 return -EPROTONOSUPPORT; 7621 7622 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7623 igb_disable_port_vlan(adapter, vf); 7624 } 7625 7626 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7627 { 7628 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7629 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7630 int ret; 7631 7632 if (adapter->vf_data[vf].pf_vlan) 7633 return -1; 7634 7635 /* VLAN 0 is a special case, don't allow it to be removed */ 7636 if (!vid && !add) 7637 return 0; 7638 7639 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7640 if (!ret) 7641 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7642 return ret; 7643 } 7644 7645 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7646 { 7647 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7648 7649 /* clear flags - except flag that indicates PF has set the MAC */ 7650 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7651 vf_data->last_nack = jiffies; 7652 7653 /* reset vlans for device */ 7654 igb_clear_vf_vfta(adapter, vf); 7655 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7656 igb_set_vmvir(adapter, vf_data->pf_vlan | 7657 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7658 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7659 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7660 7661 /* reset multicast table array for vf */ 7662 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7663 7664 /* Flush and reset the mta with the new values */ 7665 igb_set_rx_mode(adapter->netdev); 7666 } 7667 7668 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7669 { 7670 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7671 7672 /* clear mac address as we were hotplug removed/added */ 7673 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7674 eth_zero_addr(vf_mac); 7675 7676 /* process remaining reset events */ 7677 igb_vf_reset(adapter, vf); 7678 } 7679 7680 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7681 { 7682 struct e1000_hw *hw = &adapter->hw; 7683 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7684 u32 reg, msgbuf[3] = {}; 7685 u8 *addr = (u8 *)(&msgbuf[1]); 7686 7687 /* process all the same items cleared in a function level reset */ 7688 igb_vf_reset(adapter, vf); 7689 7690 /* set vf mac address */ 7691 igb_set_vf_mac(adapter, vf, vf_mac); 7692 7693 /* enable transmit and receive for vf */ 7694 reg = rd32(E1000_VFTE); 7695 wr32(E1000_VFTE, reg | BIT(vf)); 7696 reg = rd32(E1000_VFRE); 7697 wr32(E1000_VFRE, reg | BIT(vf)); 7698 7699 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7700 7701 /* reply to reset with ack and vf mac address */ 7702 if (!is_zero_ether_addr(vf_mac)) { 7703 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7704 memcpy(addr, vf_mac, ETH_ALEN); 7705 } else { 7706 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7707 } 7708 igb_write_mbx(hw, msgbuf, 3, vf); 7709 } 7710 7711 static void igb_flush_mac_table(struct igb_adapter *adapter) 7712 { 7713 struct e1000_hw *hw = &adapter->hw; 7714 int i; 7715 7716 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7717 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7718 eth_zero_addr(adapter->mac_table[i].addr); 7719 adapter->mac_table[i].queue = 0; 7720 igb_rar_set_index(adapter, i); 7721 } 7722 } 7723 7724 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7725 { 7726 struct e1000_hw *hw = &adapter->hw; 7727 /* do not count rar entries reserved for VFs MAC addresses */ 7728 int rar_entries = hw->mac.rar_entry_count - 7729 adapter->vfs_allocated_count; 7730 int i, count = 0; 7731 7732 for (i = 0; i < rar_entries; i++) { 7733 /* do not count default entries */ 7734 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7735 continue; 7736 7737 /* do not count "in use" entries for different queues */ 7738 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7739 (adapter->mac_table[i].queue != queue)) 7740 continue; 7741 7742 count++; 7743 } 7744 7745 return count; 7746 } 7747 7748 /* Set default MAC address for the PF in the first RAR entry */ 7749 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7750 { 7751 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7752 7753 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7754 mac_table->queue = adapter->vfs_allocated_count; 7755 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7756 7757 igb_rar_set_index(adapter, 0); 7758 } 7759 7760 /* If the filter to be added and an already existing filter express 7761 * the same address and address type, it should be possible to only 7762 * override the other configurations, for example the queue to steer 7763 * traffic. 7764 */ 7765 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7766 const u8 *addr, const u8 flags) 7767 { 7768 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7769 return true; 7770 7771 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7772 (flags & IGB_MAC_STATE_SRC_ADDR)) 7773 return false; 7774 7775 if (!ether_addr_equal(addr, entry->addr)) 7776 return false; 7777 7778 return true; 7779 } 7780 7781 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7782 * 'flags' is used to indicate what kind of match is made, match is by 7783 * default for the destination address, if matching by source address 7784 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7785 */ 7786 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7787 const u8 *addr, const u8 queue, 7788 const u8 flags) 7789 { 7790 struct e1000_hw *hw = &adapter->hw; 7791 int rar_entries = hw->mac.rar_entry_count - 7792 adapter->vfs_allocated_count; 7793 int i; 7794 7795 if (is_zero_ether_addr(addr)) 7796 return -EINVAL; 7797 7798 /* Search for the first empty entry in the MAC table. 7799 * Do not touch entries at the end of the table reserved for the VF MAC 7800 * addresses. 7801 */ 7802 for (i = 0; i < rar_entries; i++) { 7803 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7804 addr, flags)) 7805 continue; 7806 7807 ether_addr_copy(adapter->mac_table[i].addr, addr); 7808 adapter->mac_table[i].queue = queue; 7809 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7810 7811 igb_rar_set_index(adapter, i); 7812 return i; 7813 } 7814 7815 return -ENOSPC; 7816 } 7817 7818 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7819 const u8 queue) 7820 { 7821 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7822 } 7823 7824 /* Remove a MAC filter for 'addr' directing matching traffic to 7825 * 'queue', 'flags' is used to indicate what kind of match need to be 7826 * removed, match is by default for the destination address, if 7827 * matching by source address is to be removed the flag 7828 * IGB_MAC_STATE_SRC_ADDR can be used. 7829 */ 7830 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7831 const u8 *addr, const u8 queue, 7832 const u8 flags) 7833 { 7834 struct e1000_hw *hw = &adapter->hw; 7835 int rar_entries = hw->mac.rar_entry_count - 7836 adapter->vfs_allocated_count; 7837 int i; 7838 7839 if (is_zero_ether_addr(addr)) 7840 return -EINVAL; 7841 7842 /* Search for matching entry in the MAC table based on given address 7843 * and queue. Do not touch entries at the end of the table reserved 7844 * for the VF MAC addresses. 7845 */ 7846 for (i = 0; i < rar_entries; i++) { 7847 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7848 continue; 7849 if ((adapter->mac_table[i].state & flags) != flags) 7850 continue; 7851 if (adapter->mac_table[i].queue != queue) 7852 continue; 7853 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7854 continue; 7855 7856 /* When a filter for the default address is "deleted", 7857 * we return it to its initial configuration 7858 */ 7859 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7860 adapter->mac_table[i].state = 7861 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7862 adapter->mac_table[i].queue = 7863 adapter->vfs_allocated_count; 7864 } else { 7865 adapter->mac_table[i].state = 0; 7866 adapter->mac_table[i].queue = 0; 7867 eth_zero_addr(adapter->mac_table[i].addr); 7868 } 7869 7870 igb_rar_set_index(adapter, i); 7871 return 0; 7872 } 7873 7874 return -ENOENT; 7875 } 7876 7877 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7878 const u8 queue) 7879 { 7880 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7881 } 7882 7883 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7884 const u8 *addr, u8 queue, u8 flags) 7885 { 7886 struct e1000_hw *hw = &adapter->hw; 7887 7888 /* In theory, this should be supported on 82575 as well, but 7889 * that part wasn't easily accessible during development. 7890 */ 7891 if (hw->mac.type != e1000_i210) 7892 return -EOPNOTSUPP; 7893 7894 return igb_add_mac_filter_flags(adapter, addr, queue, 7895 IGB_MAC_STATE_QUEUE_STEERING | flags); 7896 } 7897 7898 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7899 const u8 *addr, u8 queue, u8 flags) 7900 { 7901 return igb_del_mac_filter_flags(adapter, addr, queue, 7902 IGB_MAC_STATE_QUEUE_STEERING | flags); 7903 } 7904 7905 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7906 { 7907 struct igb_adapter *adapter = netdev_priv(netdev); 7908 int ret; 7909 7910 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7911 7912 return min_t(int, ret, 0); 7913 } 7914 7915 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7916 { 7917 struct igb_adapter *adapter = netdev_priv(netdev); 7918 7919 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7920 7921 return 0; 7922 } 7923 7924 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7925 const u32 info, const u8 *addr) 7926 { 7927 struct pci_dev *pdev = adapter->pdev; 7928 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7929 struct vf_mac_filter *entry; 7930 bool found = false; 7931 int ret = 0; 7932 7933 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7934 !vf_data->trusted) { 7935 dev_warn(&pdev->dev, 7936 "VF %d requested MAC filter but is administratively denied\n", 7937 vf); 7938 return -EINVAL; 7939 } 7940 if (!is_valid_ether_addr(addr)) { 7941 dev_warn(&pdev->dev, 7942 "VF %d attempted to set invalid MAC filter\n", 7943 vf); 7944 return -EINVAL; 7945 } 7946 7947 switch (info) { 7948 case E1000_VF_MAC_FILTER_CLR: 7949 /* remove all unicast MAC filters related to the current VF */ 7950 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7951 if (entry->vf == vf) { 7952 entry->vf = -1; 7953 entry->free = true; 7954 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7955 } 7956 } 7957 break; 7958 case E1000_VF_MAC_FILTER_ADD: 7959 /* try to find empty slot in the list */ 7960 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7961 if (entry->free) { 7962 found = true; 7963 break; 7964 } 7965 } 7966 7967 if (found) { 7968 entry->free = false; 7969 entry->vf = vf; 7970 ether_addr_copy(entry->vf_mac, addr); 7971 7972 ret = igb_add_mac_filter(adapter, addr, vf); 7973 ret = min_t(int, ret, 0); 7974 } else { 7975 ret = -ENOSPC; 7976 } 7977 7978 if (ret == -ENOSPC) 7979 dev_warn(&pdev->dev, 7980 "VF %d has requested MAC filter but there is no space for it\n", 7981 vf); 7982 break; 7983 default: 7984 ret = -EINVAL; 7985 break; 7986 } 7987 7988 return ret; 7989 } 7990 7991 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7992 { 7993 struct pci_dev *pdev = adapter->pdev; 7994 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7995 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7996 7997 /* The VF MAC Address is stored in a packed array of bytes 7998 * starting at the second 32 bit word of the msg array 7999 */ 8000 unsigned char *addr = (unsigned char *)&msg[1]; 8001 int ret = 0; 8002 8003 if (!info) { 8004 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 8005 !vf_data->trusted) { 8006 dev_warn(&pdev->dev, 8007 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 8008 vf); 8009 return -EINVAL; 8010 } 8011 8012 if (!is_valid_ether_addr(addr)) { 8013 dev_warn(&pdev->dev, 8014 "VF %d attempted to set invalid MAC\n", 8015 vf); 8016 return -EINVAL; 8017 } 8018 8019 ret = igb_set_vf_mac(adapter, vf, addr); 8020 } else { 8021 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 8022 } 8023 8024 return ret; 8025 } 8026 8027 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 8028 { 8029 struct e1000_hw *hw = &adapter->hw; 8030 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8031 u32 msg = E1000_VT_MSGTYPE_NACK; 8032 8033 /* if device isn't clear to send it shouldn't be reading either */ 8034 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 8035 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 8036 igb_write_mbx(hw, &msg, 1, vf); 8037 vf_data->last_nack = jiffies; 8038 } 8039 } 8040 8041 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 8042 { 8043 struct pci_dev *pdev = adapter->pdev; 8044 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 8045 struct e1000_hw *hw = &adapter->hw; 8046 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8047 s32 retval; 8048 8049 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8050 8051 if (retval) { 8052 /* if receive failed revoke VF CTS stats and restart init */ 8053 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8054 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8055 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8056 goto unlock; 8057 goto out; 8058 } 8059 8060 /* this is a message we already processed, do nothing */ 8061 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8062 goto unlock; 8063 8064 /* until the vf completes a reset it should not be 8065 * allowed to start any configuration. 8066 */ 8067 if (msgbuf[0] == E1000_VF_RESET) { 8068 /* unlocks mailbox */ 8069 igb_vf_reset_msg(adapter, vf); 8070 return; 8071 } 8072 8073 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8074 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8075 goto unlock; 8076 retval = -1; 8077 goto out; 8078 } 8079 8080 switch ((msgbuf[0] & 0xFFFF)) { 8081 case E1000_VF_SET_MAC_ADDR: 8082 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8083 break; 8084 case E1000_VF_SET_PROMISC: 8085 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8086 break; 8087 case E1000_VF_SET_MULTICAST: 8088 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8089 break; 8090 case E1000_VF_SET_LPE: 8091 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8092 break; 8093 case E1000_VF_SET_VLAN: 8094 retval = -1; 8095 if (vf_data->pf_vlan) 8096 dev_warn(&pdev->dev, 8097 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8098 vf); 8099 else 8100 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8101 break; 8102 default: 8103 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8104 retval = -1; 8105 break; 8106 } 8107 8108 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8109 out: 8110 /* notify the VF of the results of what it sent us */ 8111 if (retval) 8112 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8113 else 8114 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8115 8116 /* unlocks mailbox */ 8117 igb_write_mbx(hw, msgbuf, 1, vf); 8118 return; 8119 8120 unlock: 8121 igb_unlock_mbx(hw, vf); 8122 } 8123 8124 static void igb_msg_task(struct igb_adapter *adapter) 8125 { 8126 struct e1000_hw *hw = &adapter->hw; 8127 unsigned long flags; 8128 u32 vf; 8129 8130 spin_lock_irqsave(&adapter->vfs_lock, flags); 8131 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8132 /* process any reset requests */ 8133 if (!igb_check_for_rst(hw, vf)) 8134 igb_vf_reset_event(adapter, vf); 8135 8136 /* process any messages pending */ 8137 if (!igb_check_for_msg(hw, vf)) 8138 igb_rcv_msg_from_vf(adapter, vf); 8139 8140 /* process any acks */ 8141 if (!igb_check_for_ack(hw, vf)) 8142 igb_rcv_ack_from_vf(adapter, vf); 8143 } 8144 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8145 } 8146 8147 /** 8148 * igb_set_uta - Set unicast filter table address 8149 * @adapter: board private structure 8150 * @set: boolean indicating if we are setting or clearing bits 8151 * 8152 * The unicast table address is a register array of 32-bit registers. 8153 * The table is meant to be used in a way similar to how the MTA is used 8154 * however due to certain limitations in the hardware it is necessary to 8155 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8156 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8157 **/ 8158 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8159 { 8160 struct e1000_hw *hw = &adapter->hw; 8161 u32 uta = set ? ~0 : 0; 8162 int i; 8163 8164 /* we only need to do this if VMDq is enabled */ 8165 if (!adapter->vfs_allocated_count) 8166 return; 8167 8168 for (i = hw->mac.uta_reg_count; i--;) 8169 array_wr32(E1000_UTA, i, uta); 8170 } 8171 8172 /** 8173 * igb_intr_msi - Interrupt Handler 8174 * @irq: interrupt number 8175 * @data: pointer to a network interface device structure 8176 **/ 8177 static irqreturn_t igb_intr_msi(int irq, void *data) 8178 { 8179 struct igb_adapter *adapter = data; 8180 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8181 struct e1000_hw *hw = &adapter->hw; 8182 /* read ICR disables interrupts using IAM */ 8183 u32 icr = rd32(E1000_ICR); 8184 8185 igb_write_itr(q_vector); 8186 8187 if (icr & E1000_ICR_DRSTA) 8188 schedule_work(&adapter->reset_task); 8189 8190 if (icr & E1000_ICR_DOUTSYNC) { 8191 /* HW is reporting DMA is out of sync */ 8192 adapter->stats.doosync++; 8193 } 8194 8195 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8196 hw->mac.get_link_status = 1; 8197 if (!test_bit(__IGB_DOWN, &adapter->state)) 8198 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8199 } 8200 8201 if (icr & E1000_ICR_TS) 8202 igb_tsync_interrupt(adapter); 8203 8204 napi_schedule(&q_vector->napi); 8205 8206 return IRQ_HANDLED; 8207 } 8208 8209 /** 8210 * igb_intr - Legacy Interrupt Handler 8211 * @irq: interrupt number 8212 * @data: pointer to a network interface device structure 8213 **/ 8214 static irqreturn_t igb_intr(int irq, void *data) 8215 { 8216 struct igb_adapter *adapter = data; 8217 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8218 struct e1000_hw *hw = &adapter->hw; 8219 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8220 * need for the IMC write 8221 */ 8222 u32 icr = rd32(E1000_ICR); 8223 8224 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8225 * not set, then the adapter didn't send an interrupt 8226 */ 8227 if (!(icr & E1000_ICR_INT_ASSERTED)) 8228 return IRQ_NONE; 8229 8230 igb_write_itr(q_vector); 8231 8232 if (icr & E1000_ICR_DRSTA) 8233 schedule_work(&adapter->reset_task); 8234 8235 if (icr & E1000_ICR_DOUTSYNC) { 8236 /* HW is reporting DMA is out of sync */ 8237 adapter->stats.doosync++; 8238 } 8239 8240 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8241 hw->mac.get_link_status = 1; 8242 /* guard against interrupt when we're going down */ 8243 if (!test_bit(__IGB_DOWN, &adapter->state)) 8244 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8245 } 8246 8247 if (icr & E1000_ICR_TS) 8248 igb_tsync_interrupt(adapter); 8249 8250 napi_schedule(&q_vector->napi); 8251 8252 return IRQ_HANDLED; 8253 } 8254 8255 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8256 { 8257 struct igb_adapter *adapter = q_vector->adapter; 8258 struct e1000_hw *hw = &adapter->hw; 8259 8260 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8261 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8262 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8263 igb_set_itr(q_vector); 8264 else 8265 igb_update_ring_itr(q_vector); 8266 } 8267 8268 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8269 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8270 wr32(E1000_EIMS, q_vector->eims_value); 8271 else 8272 igb_irq_enable(adapter); 8273 } 8274 } 8275 8276 /** 8277 * igb_poll - NAPI Rx polling callback 8278 * @napi: napi polling structure 8279 * @budget: count of how many packets we should handle 8280 **/ 8281 static int igb_poll(struct napi_struct *napi, int budget) 8282 { 8283 struct igb_q_vector *q_vector = container_of(napi, 8284 struct igb_q_vector, 8285 napi); 8286 struct xsk_buff_pool *xsk_pool; 8287 bool clean_complete = true; 8288 int work_done = 0; 8289 8290 #ifdef CONFIG_IGB_DCA 8291 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8292 igb_update_dca(q_vector); 8293 #endif 8294 if (q_vector->tx.ring) 8295 clean_complete = igb_clean_tx_irq(q_vector, budget); 8296 8297 if (q_vector->rx.ring) { 8298 int cleaned; 8299 8300 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8301 cleaned = xsk_pool ? 8302 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8303 igb_clean_rx_irq(q_vector, budget); 8304 8305 work_done += cleaned; 8306 if (cleaned >= budget) 8307 clean_complete = false; 8308 } 8309 8310 /* If all work not completed, return budget and keep polling */ 8311 if (!clean_complete) 8312 return budget; 8313 8314 /* Exit the polling mode, but don't re-enable interrupts if stack might 8315 * poll us due to busy-polling 8316 */ 8317 if (likely(napi_complete_done(napi, work_done))) 8318 igb_ring_irq_enable(q_vector); 8319 8320 return work_done; 8321 } 8322 8323 /** 8324 * igb_clean_tx_irq - Reclaim resources after transmit completes 8325 * @q_vector: pointer to q_vector containing needed info 8326 * @napi_budget: Used to determine if we are in netpoll 8327 * 8328 * returns true if ring is completely cleaned 8329 **/ 8330 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8331 { 8332 unsigned int total_bytes = 0, total_packets = 0; 8333 struct igb_adapter *adapter = q_vector->adapter; 8334 unsigned int budget = q_vector->tx.work_limit; 8335 struct igb_ring *tx_ring = q_vector->tx.ring; 8336 unsigned int i = tx_ring->next_to_clean; 8337 union e1000_adv_tx_desc *tx_desc; 8338 struct igb_tx_buffer *tx_buffer; 8339 struct xsk_buff_pool *xsk_pool; 8340 int cpu = smp_processor_id(); 8341 bool xsk_xmit_done = true; 8342 struct netdev_queue *nq; 8343 u32 xsk_frames = 0; 8344 8345 if (test_bit(__IGB_DOWN, &adapter->state)) 8346 return true; 8347 8348 tx_buffer = &tx_ring->tx_buffer_info[i]; 8349 tx_desc = IGB_TX_DESC(tx_ring, i); 8350 i -= tx_ring->count; 8351 8352 do { 8353 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8354 8355 /* if next_to_watch is not set then there is no work pending */ 8356 if (!eop_desc) 8357 break; 8358 8359 /* prevent any other reads prior to eop_desc */ 8360 smp_rmb(); 8361 8362 /* if DD is not set pending work has not been completed */ 8363 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8364 break; 8365 8366 /* clear next_to_watch to prevent false hangs */ 8367 tx_buffer->next_to_watch = NULL; 8368 8369 /* update the statistics for this packet */ 8370 total_bytes += tx_buffer->bytecount; 8371 total_packets += tx_buffer->gso_segs; 8372 8373 /* free the skb */ 8374 if (tx_buffer->type == IGB_TYPE_SKB) { 8375 napi_consume_skb(tx_buffer->skb, napi_budget); 8376 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8377 xdp_return_frame(tx_buffer->xdpf); 8378 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8379 xsk_frames++; 8380 goto skip_for_xsk; 8381 } 8382 8383 /* unmap skb header data */ 8384 dma_unmap_single(tx_ring->dev, 8385 dma_unmap_addr(tx_buffer, dma), 8386 dma_unmap_len(tx_buffer, len), 8387 DMA_TO_DEVICE); 8388 8389 /* clear tx_buffer data */ 8390 dma_unmap_len_set(tx_buffer, len, 0); 8391 8392 /* clear last DMA location and unmap remaining buffers */ 8393 while (tx_desc != eop_desc) { 8394 tx_buffer++; 8395 tx_desc++; 8396 i++; 8397 if (unlikely(!i)) { 8398 i -= tx_ring->count; 8399 tx_buffer = tx_ring->tx_buffer_info; 8400 tx_desc = IGB_TX_DESC(tx_ring, 0); 8401 } 8402 8403 /* unmap any remaining paged data */ 8404 if (dma_unmap_len(tx_buffer, len)) { 8405 dma_unmap_page(tx_ring->dev, 8406 dma_unmap_addr(tx_buffer, dma), 8407 dma_unmap_len(tx_buffer, len), 8408 DMA_TO_DEVICE); 8409 dma_unmap_len_set(tx_buffer, len, 0); 8410 } 8411 } 8412 8413 skip_for_xsk: 8414 /* move us one more past the eop_desc for start of next pkt */ 8415 tx_buffer++; 8416 tx_desc++; 8417 i++; 8418 if (unlikely(!i)) { 8419 i -= tx_ring->count; 8420 tx_buffer = tx_ring->tx_buffer_info; 8421 tx_desc = IGB_TX_DESC(tx_ring, 0); 8422 } 8423 8424 /* issue prefetch for next Tx descriptor */ 8425 prefetch(tx_desc); 8426 8427 /* update budget accounting */ 8428 budget--; 8429 } while (likely(budget)); 8430 8431 netdev_tx_completed_queue(txring_txq(tx_ring), 8432 total_packets, total_bytes); 8433 i += tx_ring->count; 8434 tx_ring->next_to_clean = i; 8435 u64_stats_update_begin(&tx_ring->tx_syncp); 8436 tx_ring->tx_stats.bytes += total_bytes; 8437 tx_ring->tx_stats.packets += total_packets; 8438 u64_stats_update_end(&tx_ring->tx_syncp); 8439 q_vector->tx.total_bytes += total_bytes; 8440 q_vector->tx.total_packets += total_packets; 8441 8442 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8443 if (xsk_pool) { 8444 if (xsk_frames) 8445 xsk_tx_completed(xsk_pool, xsk_frames); 8446 if (xsk_uses_need_wakeup(xsk_pool)) 8447 xsk_set_tx_need_wakeup(xsk_pool); 8448 8449 nq = txring_txq(tx_ring); 8450 __netif_tx_lock(nq, cpu); 8451 /* Avoid transmit queue timeout since we share it with the slow path */ 8452 txq_trans_cond_update(nq); 8453 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8454 __netif_tx_unlock(nq); 8455 } 8456 8457 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8458 struct e1000_hw *hw = &adapter->hw; 8459 8460 /* Detect a transmit hang in hardware, this serializes the 8461 * check with the clearing of time_stamp and movement of i 8462 */ 8463 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8464 if (tx_buffer->next_to_watch && 8465 time_after(jiffies, tx_buffer->time_stamp + 8466 (adapter->tx_timeout_factor * HZ)) && 8467 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8468 8469 /* detected Tx unit hang */ 8470 dev_err(tx_ring->dev, 8471 "Detected Tx Unit Hang\n" 8472 " Tx Queue <%d>\n" 8473 " TDH <%x>\n" 8474 " TDT <%x>\n" 8475 " next_to_use <%x>\n" 8476 " next_to_clean <%x>\n" 8477 "buffer_info[next_to_clean]\n" 8478 " time_stamp <%lx>\n" 8479 " next_to_watch <%p>\n" 8480 " jiffies <%lx>\n" 8481 " desc.status <%x>\n", 8482 tx_ring->queue_index, 8483 rd32(E1000_TDH(tx_ring->reg_idx)), 8484 readl(tx_ring->tail), 8485 tx_ring->next_to_use, 8486 tx_ring->next_to_clean, 8487 tx_buffer->time_stamp, 8488 tx_buffer->next_to_watch, 8489 jiffies, 8490 tx_buffer->next_to_watch->wb.status); 8491 netif_stop_subqueue(tx_ring->netdev, 8492 tx_ring->queue_index); 8493 8494 /* we are about to reset, no point in enabling stuff */ 8495 return true; 8496 } 8497 } 8498 8499 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8500 if (unlikely(total_packets && 8501 netif_carrier_ok(tx_ring->netdev) && 8502 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8503 /* Make sure that anybody stopping the queue after this 8504 * sees the new next_to_clean. 8505 */ 8506 smp_mb(); 8507 if (__netif_subqueue_stopped(tx_ring->netdev, 8508 tx_ring->queue_index) && 8509 !(test_bit(__IGB_DOWN, &adapter->state))) { 8510 netif_wake_subqueue(tx_ring->netdev, 8511 tx_ring->queue_index); 8512 8513 u64_stats_update_begin(&tx_ring->tx_syncp); 8514 tx_ring->tx_stats.restart_queue++; 8515 u64_stats_update_end(&tx_ring->tx_syncp); 8516 } 8517 } 8518 8519 return !!budget && xsk_xmit_done; 8520 } 8521 8522 /** 8523 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8524 * @rx_ring: rx descriptor ring to store buffers on 8525 * @old_buff: donor buffer to have page reused 8526 * 8527 * Synchronizes page for reuse by the adapter 8528 **/ 8529 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8530 struct igb_rx_buffer *old_buff) 8531 { 8532 struct igb_rx_buffer *new_buff; 8533 u16 nta = rx_ring->next_to_alloc; 8534 8535 new_buff = &rx_ring->rx_buffer_info[nta]; 8536 8537 /* update, and store next to alloc */ 8538 nta++; 8539 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8540 8541 /* Transfer page from old buffer to new buffer. 8542 * Move each member individually to avoid possible store 8543 * forwarding stalls. 8544 */ 8545 new_buff->dma = old_buff->dma; 8546 new_buff->page = old_buff->page; 8547 new_buff->page_offset = old_buff->page_offset; 8548 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8549 } 8550 8551 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8552 int rx_buf_pgcnt) 8553 { 8554 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8555 struct page *page = rx_buffer->page; 8556 8557 /* avoid re-using remote and pfmemalloc pages */ 8558 if (!dev_page_is_reusable(page)) 8559 return false; 8560 8561 #if (PAGE_SIZE < 8192) 8562 /* if we are only owner of page we can reuse it */ 8563 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8564 return false; 8565 #else 8566 #define IGB_LAST_OFFSET \ 8567 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8568 8569 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8570 return false; 8571 #endif 8572 8573 /* If we have drained the page fragment pool we need to update 8574 * the pagecnt_bias and page count so that we fully restock the 8575 * number of references the driver holds. 8576 */ 8577 if (unlikely(pagecnt_bias == 1)) { 8578 page_ref_add(page, USHRT_MAX - 1); 8579 rx_buffer->pagecnt_bias = USHRT_MAX; 8580 } 8581 8582 return true; 8583 } 8584 8585 /** 8586 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8587 * @rx_ring: rx descriptor ring to transact packets on 8588 * @rx_buffer: buffer containing page to add 8589 * @skb: sk_buff to place the data into 8590 * @size: size of buffer to be added 8591 * 8592 * This function will add the data contained in rx_buffer->page to the skb. 8593 **/ 8594 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8595 struct igb_rx_buffer *rx_buffer, 8596 struct sk_buff *skb, 8597 unsigned int size) 8598 { 8599 #if (PAGE_SIZE < 8192) 8600 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8601 #else 8602 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8603 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8604 SKB_DATA_ALIGN(size); 8605 #endif 8606 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8607 rx_buffer->page_offset, size, truesize); 8608 #if (PAGE_SIZE < 8192) 8609 rx_buffer->page_offset ^= truesize; 8610 #else 8611 rx_buffer->page_offset += truesize; 8612 #endif 8613 } 8614 8615 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8616 struct igb_rx_buffer *rx_buffer, 8617 struct xdp_buff *xdp, 8618 ktime_t timestamp) 8619 { 8620 #if (PAGE_SIZE < 8192) 8621 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8622 #else 8623 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8624 xdp->data_hard_start); 8625 #endif 8626 unsigned int size = xdp->data_end - xdp->data; 8627 unsigned int headlen; 8628 struct sk_buff *skb; 8629 8630 /* prefetch first cache line of first page */ 8631 net_prefetch(xdp->data); 8632 8633 /* allocate a skb to store the frags */ 8634 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8635 if (unlikely(!skb)) 8636 return NULL; 8637 8638 if (timestamp) 8639 skb_hwtstamps(skb)->hwtstamp = timestamp; 8640 8641 /* Determine available headroom for copy */ 8642 headlen = size; 8643 if (headlen > IGB_RX_HDR_LEN) 8644 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8645 8646 /* align pull length to size of long to optimize memcpy performance */ 8647 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8648 8649 /* update all of the pointers */ 8650 size -= headlen; 8651 if (size) { 8652 skb_add_rx_frag(skb, 0, rx_buffer->page, 8653 (xdp->data + headlen) - page_address(rx_buffer->page), 8654 size, truesize); 8655 #if (PAGE_SIZE < 8192) 8656 rx_buffer->page_offset ^= truesize; 8657 #else 8658 rx_buffer->page_offset += truesize; 8659 #endif 8660 } else { 8661 rx_buffer->pagecnt_bias++; 8662 } 8663 8664 return skb; 8665 } 8666 8667 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8668 struct igb_rx_buffer *rx_buffer, 8669 struct xdp_buff *xdp, 8670 ktime_t timestamp) 8671 { 8672 #if (PAGE_SIZE < 8192) 8673 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8674 #else 8675 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8676 SKB_DATA_ALIGN(xdp->data_end - 8677 xdp->data_hard_start); 8678 #endif 8679 unsigned int metasize = xdp->data - xdp->data_meta; 8680 struct sk_buff *skb; 8681 8682 /* prefetch first cache line of first page */ 8683 net_prefetch(xdp->data_meta); 8684 8685 /* build an skb around the page buffer */ 8686 skb = napi_build_skb(xdp->data_hard_start, truesize); 8687 if (unlikely(!skb)) 8688 return NULL; 8689 8690 /* update pointers within the skb to store the data */ 8691 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8692 __skb_put(skb, xdp->data_end - xdp->data); 8693 8694 if (metasize) 8695 skb_metadata_set(skb, metasize); 8696 8697 if (timestamp) 8698 skb_hwtstamps(skb)->hwtstamp = timestamp; 8699 8700 /* update buffer offset */ 8701 #if (PAGE_SIZE < 8192) 8702 rx_buffer->page_offset ^= truesize; 8703 #else 8704 rx_buffer->page_offset += truesize; 8705 #endif 8706 8707 return skb; 8708 } 8709 8710 static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8711 struct xdp_buff *xdp) 8712 { 8713 int err, result = IGB_XDP_PASS; 8714 struct bpf_prog *xdp_prog; 8715 u32 act; 8716 8717 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8718 8719 if (!xdp_prog) 8720 goto xdp_out; 8721 8722 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8723 8724 act = bpf_prog_run_xdp(xdp_prog, xdp); 8725 switch (act) { 8726 case XDP_PASS: 8727 break; 8728 case XDP_TX: 8729 result = igb_xdp_xmit_back(adapter, xdp); 8730 if (result == IGB_XDP_CONSUMED) 8731 goto out_failure; 8732 break; 8733 case XDP_REDIRECT: 8734 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8735 if (err) 8736 goto out_failure; 8737 result = IGB_XDP_REDIR; 8738 break; 8739 default: 8740 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8741 fallthrough; 8742 case XDP_ABORTED: 8743 out_failure: 8744 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8745 fallthrough; 8746 case XDP_DROP: 8747 result = IGB_XDP_CONSUMED; 8748 break; 8749 } 8750 xdp_out: 8751 return result; 8752 } 8753 8754 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8755 unsigned int size) 8756 { 8757 unsigned int truesize; 8758 8759 #if (PAGE_SIZE < 8192) 8760 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8761 #else 8762 truesize = ring_uses_build_skb(rx_ring) ? 8763 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8764 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8765 SKB_DATA_ALIGN(size); 8766 #endif 8767 return truesize; 8768 } 8769 8770 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8771 struct igb_rx_buffer *rx_buffer, 8772 unsigned int size) 8773 { 8774 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8775 #if (PAGE_SIZE < 8192) 8776 rx_buffer->page_offset ^= truesize; 8777 #else 8778 rx_buffer->page_offset += truesize; 8779 #endif 8780 } 8781 8782 static inline void igb_rx_checksum(struct igb_ring *ring, 8783 union e1000_adv_rx_desc *rx_desc, 8784 struct sk_buff *skb) 8785 { 8786 skb_checksum_none_assert(skb); 8787 8788 /* Ignore Checksum bit is set */ 8789 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8790 return; 8791 8792 /* Rx checksum disabled via ethtool */ 8793 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8794 return; 8795 8796 /* TCP/UDP checksum error bit is set */ 8797 if (igb_test_staterr(rx_desc, 8798 E1000_RXDEXT_STATERR_TCPE | 8799 E1000_RXDEXT_STATERR_IPE)) { 8800 /* work around errata with sctp packets where the TCPE aka 8801 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8802 * packets, (aka let the stack check the crc32c) 8803 */ 8804 if (!((skb->len == 60) && 8805 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8806 u64_stats_update_begin(&ring->rx_syncp); 8807 ring->rx_stats.csum_err++; 8808 u64_stats_update_end(&ring->rx_syncp); 8809 } 8810 /* let the stack verify checksum errors */ 8811 return; 8812 } 8813 /* It must be a TCP or UDP packet with a valid checksum */ 8814 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8815 E1000_RXD_STAT_UDPCS)) 8816 skb->ip_summed = CHECKSUM_UNNECESSARY; 8817 8818 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8819 le32_to_cpu(rx_desc->wb.upper.status_error)); 8820 } 8821 8822 static inline void igb_rx_hash(struct igb_ring *ring, 8823 union e1000_adv_rx_desc *rx_desc, 8824 struct sk_buff *skb) 8825 { 8826 if (ring->netdev->features & NETIF_F_RXHASH) 8827 skb_set_hash(skb, 8828 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8829 PKT_HASH_TYPE_L3); 8830 } 8831 8832 /** 8833 * igb_is_non_eop - process handling of non-EOP buffers 8834 * @rx_ring: Rx ring being processed 8835 * @rx_desc: Rx descriptor for current buffer 8836 * 8837 * This function updates next to clean. If the buffer is an EOP buffer 8838 * this function exits returning false, otherwise it will place the 8839 * sk_buff in the next buffer to be chained and return true indicating 8840 * that this is in fact a non-EOP buffer. 8841 **/ 8842 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8843 union e1000_adv_rx_desc *rx_desc) 8844 { 8845 u32 ntc = rx_ring->next_to_clean + 1; 8846 8847 /* fetch, update, and store next to clean */ 8848 ntc = (ntc < rx_ring->count) ? ntc : 0; 8849 rx_ring->next_to_clean = ntc; 8850 8851 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8852 8853 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8854 return false; 8855 8856 return true; 8857 } 8858 8859 /** 8860 * igb_cleanup_headers - Correct corrupted or empty headers 8861 * @rx_ring: rx descriptor ring packet is being transacted on 8862 * @rx_desc: pointer to the EOP Rx descriptor 8863 * @skb: pointer to current skb being fixed 8864 * 8865 * Address the case where we are pulling data in on pages only 8866 * and as such no data is present in the skb header. 8867 * 8868 * In addition if skb is not at least 60 bytes we need to pad it so that 8869 * it is large enough to qualify as a valid Ethernet frame. 8870 * 8871 * Returns true if an error was encountered and skb was freed. 8872 **/ 8873 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8874 union e1000_adv_rx_desc *rx_desc, 8875 struct sk_buff *skb) 8876 { 8877 if (unlikely((igb_test_staterr(rx_desc, 8878 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8879 struct net_device *netdev = rx_ring->netdev; 8880 if (!(netdev->features & NETIF_F_RXALL)) { 8881 dev_kfree_skb_any(skb); 8882 return true; 8883 } 8884 } 8885 8886 /* if eth_skb_pad returns an error the skb was freed */ 8887 if (eth_skb_pad(skb)) 8888 return true; 8889 8890 return false; 8891 } 8892 8893 /** 8894 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8895 * @rx_ring: rx descriptor ring packet is being transacted on 8896 * @rx_desc: pointer to the EOP Rx descriptor 8897 * @skb: pointer to current skb being populated 8898 * 8899 * This function checks the ring, descriptor, and packet information in 8900 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8901 * other fields within the skb. 8902 **/ 8903 void igb_process_skb_fields(struct igb_ring *rx_ring, 8904 union e1000_adv_rx_desc *rx_desc, 8905 struct sk_buff *skb) 8906 { 8907 struct net_device *dev = rx_ring->netdev; 8908 8909 igb_rx_hash(rx_ring, rx_desc, skb); 8910 8911 igb_rx_checksum(rx_ring, rx_desc, skb); 8912 8913 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8914 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8915 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8916 8917 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8918 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8919 u16 vid; 8920 8921 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8922 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8923 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8924 else 8925 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8926 8927 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8928 } 8929 8930 skb_record_rx_queue(skb, rx_ring->queue_index); 8931 8932 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8933 } 8934 8935 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8936 { 8937 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8938 } 8939 8940 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8941 const unsigned int size, int *rx_buf_pgcnt) 8942 { 8943 struct igb_rx_buffer *rx_buffer; 8944 8945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8946 *rx_buf_pgcnt = 8947 #if (PAGE_SIZE < 8192) 8948 page_count(rx_buffer->page); 8949 #else 8950 0; 8951 #endif 8952 prefetchw(rx_buffer->page); 8953 8954 /* we are reusing so sync this buffer for CPU use */ 8955 dma_sync_single_range_for_cpu(rx_ring->dev, 8956 rx_buffer->dma, 8957 rx_buffer->page_offset, 8958 size, 8959 DMA_FROM_DEVICE); 8960 8961 rx_buffer->pagecnt_bias--; 8962 8963 return rx_buffer; 8964 } 8965 8966 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8967 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8968 { 8969 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8970 /* hand second half of page back to the ring */ 8971 igb_reuse_rx_page(rx_ring, rx_buffer); 8972 } else { 8973 /* We are not reusing the buffer so unmap it and free 8974 * any references we are holding to it 8975 */ 8976 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8977 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8978 IGB_RX_DMA_ATTR); 8979 __page_frag_cache_drain(rx_buffer->page, 8980 rx_buffer->pagecnt_bias); 8981 } 8982 8983 /* clear contents of rx_buffer */ 8984 rx_buffer->page = NULL; 8985 } 8986 8987 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8988 { 8989 int cpu = smp_processor_id(); 8990 struct netdev_queue *nq; 8991 8992 if (status & IGB_XDP_REDIR) 8993 xdp_do_flush(); 8994 8995 if (status & IGB_XDP_TX) { 8996 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8997 8998 nq = txring_txq(tx_ring); 8999 __netif_tx_lock(nq, cpu); 9000 igb_xdp_ring_update_tail(tx_ring); 9001 __netif_tx_unlock(nq); 9002 } 9003 } 9004 9005 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 9006 unsigned int bytes) 9007 { 9008 struct igb_ring *ring = q_vector->rx.ring; 9009 9010 u64_stats_update_begin(&ring->rx_syncp); 9011 ring->rx_stats.packets += packets; 9012 ring->rx_stats.bytes += bytes; 9013 u64_stats_update_end(&ring->rx_syncp); 9014 9015 q_vector->rx.total_packets += packets; 9016 q_vector->rx.total_bytes += bytes; 9017 } 9018 9019 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 9020 { 9021 unsigned int total_bytes = 0, total_packets = 0; 9022 struct igb_adapter *adapter = q_vector->adapter; 9023 struct igb_ring *rx_ring = q_vector->rx.ring; 9024 u16 cleaned_count = igb_desc_unused(rx_ring); 9025 struct sk_buff *skb = rx_ring->skb; 9026 unsigned int xdp_xmit = 0; 9027 struct xdp_buff xdp; 9028 u32 frame_sz = 0; 9029 int rx_buf_pgcnt; 9030 int xdp_res = 0; 9031 9032 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 9033 #if (PAGE_SIZE < 8192) 9034 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 9035 #endif 9036 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 9037 9038 while (likely(total_packets < budget)) { 9039 union e1000_adv_rx_desc *rx_desc; 9040 struct igb_rx_buffer *rx_buffer; 9041 ktime_t timestamp = 0; 9042 int pkt_offset = 0; 9043 unsigned int size; 9044 void *pktbuf; 9045 9046 /* return some buffers to hardware, one at a time is too slow */ 9047 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 9048 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9049 cleaned_count = 0; 9050 } 9051 9052 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9053 size = le16_to_cpu(rx_desc->wb.upper.length); 9054 if (!size) 9055 break; 9056 9057 /* This memory barrier is needed to keep us from reading 9058 * any other fields out of the rx_desc until we know the 9059 * descriptor has been written back 9060 */ 9061 dma_rmb(); 9062 9063 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9064 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9065 9066 /* pull rx packet timestamp if available and valid */ 9067 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9068 int ts_hdr_len; 9069 9070 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9071 pktbuf, ×tamp); 9072 9073 pkt_offset += ts_hdr_len; 9074 size -= ts_hdr_len; 9075 } 9076 9077 /* retrieve a buffer from the ring */ 9078 if (!skb) { 9079 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9080 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9081 9082 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9083 xdp_buff_clear_frags_flag(&xdp); 9084 #if (PAGE_SIZE > 4096) 9085 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9086 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9087 #endif 9088 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9089 } 9090 9091 if (xdp_res) { 9092 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9093 xdp_xmit |= xdp_res; 9094 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9095 } else { 9096 rx_buffer->pagecnt_bias++; 9097 } 9098 total_packets++; 9099 total_bytes += size; 9100 } else if (skb) 9101 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9102 else if (ring_uses_build_skb(rx_ring)) 9103 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9104 timestamp); 9105 else 9106 skb = igb_construct_skb(rx_ring, rx_buffer, 9107 &xdp, timestamp); 9108 9109 /* exit if we failed to retrieve a buffer */ 9110 if (!xdp_res && !skb) { 9111 rx_ring->rx_stats.alloc_failed++; 9112 rx_buffer->pagecnt_bias++; 9113 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9114 break; 9115 } 9116 9117 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9118 cleaned_count++; 9119 9120 /* fetch next buffer in frame if non-eop */ 9121 if (igb_is_non_eop(rx_ring, rx_desc)) 9122 continue; 9123 9124 /* verify the packet layout is correct */ 9125 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9126 skb = NULL; 9127 continue; 9128 } 9129 9130 /* probably a little skewed due to removing CRC */ 9131 total_bytes += skb->len; 9132 9133 /* populate checksum, timestamp, VLAN, and protocol */ 9134 igb_process_skb_fields(rx_ring, rx_desc, skb); 9135 9136 napi_gro_receive(&q_vector->napi, skb); 9137 9138 /* reset skb pointer */ 9139 skb = NULL; 9140 9141 /* update budget accounting */ 9142 total_packets++; 9143 } 9144 9145 /* place incomplete frames back on ring for completion */ 9146 rx_ring->skb = skb; 9147 9148 if (xdp_xmit) 9149 igb_finalize_xdp(adapter, xdp_xmit); 9150 9151 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9152 9153 if (cleaned_count) 9154 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9155 9156 return total_packets; 9157 } 9158 9159 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9160 struct igb_rx_buffer *bi) 9161 { 9162 struct page *page = bi->page; 9163 dma_addr_t dma; 9164 9165 /* since we are recycling buffers we should seldom need to alloc */ 9166 if (likely(page)) 9167 return true; 9168 9169 /* alloc new page for storage */ 9170 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9171 if (unlikely(!page)) { 9172 rx_ring->rx_stats.alloc_failed++; 9173 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9174 return false; 9175 } 9176 9177 /* map page for use */ 9178 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9179 igb_rx_pg_size(rx_ring), 9180 DMA_FROM_DEVICE, 9181 IGB_RX_DMA_ATTR); 9182 9183 /* if mapping failed free memory back to system since 9184 * there isn't much point in holding memory we can't use 9185 */ 9186 if (dma_mapping_error(rx_ring->dev, dma)) { 9187 __free_pages(page, igb_rx_pg_order(rx_ring)); 9188 9189 rx_ring->rx_stats.alloc_failed++; 9190 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9191 return false; 9192 } 9193 9194 bi->dma = dma; 9195 bi->page = page; 9196 bi->page_offset = igb_rx_offset(rx_ring); 9197 page_ref_add(page, USHRT_MAX - 1); 9198 bi->pagecnt_bias = USHRT_MAX; 9199 9200 return true; 9201 } 9202 9203 /** 9204 * igb_alloc_rx_buffers - Replace used receive buffers 9205 * @rx_ring: rx descriptor ring to allocate new receive buffers 9206 * @cleaned_count: count of buffers to allocate 9207 **/ 9208 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9209 { 9210 union e1000_adv_rx_desc *rx_desc; 9211 struct igb_rx_buffer *bi; 9212 u16 i = rx_ring->next_to_use; 9213 u16 bufsz; 9214 9215 /* nothing to do */ 9216 if (!cleaned_count) 9217 return; 9218 9219 rx_desc = IGB_RX_DESC(rx_ring, i); 9220 bi = &rx_ring->rx_buffer_info[i]; 9221 i -= rx_ring->count; 9222 9223 bufsz = igb_rx_bufsz(rx_ring); 9224 9225 do { 9226 if (!igb_alloc_mapped_page(rx_ring, bi)) 9227 break; 9228 9229 /* sync the buffer for use by the device */ 9230 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9231 bi->page_offset, bufsz, 9232 DMA_FROM_DEVICE); 9233 9234 /* Refresh the desc even if buffer_addrs didn't change 9235 * because each write-back erases this info. 9236 */ 9237 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9238 9239 rx_desc++; 9240 bi++; 9241 i++; 9242 if (unlikely(!i)) { 9243 rx_desc = IGB_RX_DESC(rx_ring, 0); 9244 bi = rx_ring->rx_buffer_info; 9245 i -= rx_ring->count; 9246 } 9247 9248 /* clear the length for the next_to_use descriptor */ 9249 rx_desc->wb.upper.length = 0; 9250 9251 cleaned_count--; 9252 } while (cleaned_count); 9253 9254 i += rx_ring->count; 9255 9256 if (rx_ring->next_to_use != i) { 9257 /* record the next descriptor to use */ 9258 rx_ring->next_to_use = i; 9259 9260 /* update next to alloc since we have filled the ring */ 9261 rx_ring->next_to_alloc = i; 9262 9263 /* Force memory writes to complete before letting h/w 9264 * know there are new descriptors to fetch. (Only 9265 * applicable for weak-ordered memory model archs, 9266 * such as IA-64). 9267 */ 9268 dma_wmb(); 9269 writel(i, rx_ring->tail); 9270 } 9271 } 9272 9273 /** 9274 * igb_mii_ioctl - 9275 * @netdev: pointer to netdev struct 9276 * @ifr: interface structure 9277 * @cmd: ioctl command to execute 9278 **/ 9279 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9280 { 9281 struct igb_adapter *adapter = netdev_priv(netdev); 9282 struct mii_ioctl_data *data = if_mii(ifr); 9283 9284 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9285 return -EOPNOTSUPP; 9286 9287 switch (cmd) { 9288 case SIOCGMIIPHY: 9289 data->phy_id = adapter->hw.phy.addr; 9290 break; 9291 case SIOCGMIIREG: 9292 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9293 &data->val_out)) 9294 return -EIO; 9295 break; 9296 case SIOCSMIIREG: 9297 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9298 data->val_in)) 9299 return -EIO; 9300 break; 9301 default: 9302 return -EOPNOTSUPP; 9303 } 9304 return 0; 9305 } 9306 9307 /** 9308 * igb_ioctl - 9309 * @netdev: pointer to netdev struct 9310 * @ifr: interface structure 9311 * @cmd: ioctl command to execute 9312 **/ 9313 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9314 { 9315 switch (cmd) { 9316 case SIOCGMIIPHY: 9317 case SIOCGMIIREG: 9318 case SIOCSMIIREG: 9319 return igb_mii_ioctl(netdev, ifr, cmd); 9320 default: 9321 return -EOPNOTSUPP; 9322 } 9323 } 9324 9325 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9326 { 9327 struct igb_adapter *adapter = hw->back; 9328 9329 pci_read_config_word(adapter->pdev, reg, value); 9330 } 9331 9332 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9333 { 9334 struct igb_adapter *adapter = hw->back; 9335 9336 pci_write_config_word(adapter->pdev, reg, *value); 9337 } 9338 9339 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9340 { 9341 struct igb_adapter *adapter = hw->back; 9342 9343 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9344 return -E1000_ERR_CONFIG; 9345 9346 return 0; 9347 } 9348 9349 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9350 { 9351 struct igb_adapter *adapter = hw->back; 9352 9353 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9354 return -E1000_ERR_CONFIG; 9355 9356 return 0; 9357 } 9358 9359 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9360 { 9361 struct igb_adapter *adapter = netdev_priv(netdev); 9362 struct e1000_hw *hw = &adapter->hw; 9363 u32 ctrl, rctl; 9364 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9365 9366 if (enable) { 9367 /* enable VLAN tag insert/strip */ 9368 ctrl = rd32(E1000_CTRL); 9369 ctrl |= E1000_CTRL_VME; 9370 wr32(E1000_CTRL, ctrl); 9371 9372 /* Disable CFI check */ 9373 rctl = rd32(E1000_RCTL); 9374 rctl &= ~E1000_RCTL_CFIEN; 9375 wr32(E1000_RCTL, rctl); 9376 } else { 9377 /* disable VLAN tag insert/strip */ 9378 ctrl = rd32(E1000_CTRL); 9379 ctrl &= ~E1000_CTRL_VME; 9380 wr32(E1000_CTRL, ctrl); 9381 } 9382 9383 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9384 } 9385 9386 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9387 __be16 proto, u16 vid) 9388 { 9389 struct igb_adapter *adapter = netdev_priv(netdev); 9390 struct e1000_hw *hw = &adapter->hw; 9391 int pf_id = adapter->vfs_allocated_count; 9392 9393 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9394 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9395 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9396 9397 set_bit(vid, adapter->active_vlans); 9398 9399 return 0; 9400 } 9401 9402 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9403 __be16 proto, u16 vid) 9404 { 9405 struct igb_adapter *adapter = netdev_priv(netdev); 9406 int pf_id = adapter->vfs_allocated_count; 9407 struct e1000_hw *hw = &adapter->hw; 9408 9409 /* remove VID from filter table */ 9410 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9411 igb_vfta_set(hw, vid, pf_id, false, true); 9412 9413 clear_bit(vid, adapter->active_vlans); 9414 9415 return 0; 9416 } 9417 9418 static void igb_restore_vlan(struct igb_adapter *adapter) 9419 { 9420 u16 vid = 1; 9421 9422 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9423 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9424 9425 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9426 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9427 } 9428 9429 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9430 { 9431 struct pci_dev *pdev = adapter->pdev; 9432 struct e1000_mac_info *mac = &adapter->hw.mac; 9433 9434 mac->autoneg = 0; 9435 9436 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9437 * for the switch() below to work 9438 */ 9439 if ((spd & 1) || (dplx & ~1)) 9440 goto err_inval; 9441 9442 /* Fiber NIC's only allow 1000 gbps Full duplex 9443 * and 100Mbps Full duplex for 100baseFx sfp 9444 */ 9445 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9446 switch (spd + dplx) { 9447 case SPEED_10 + DUPLEX_HALF: 9448 case SPEED_10 + DUPLEX_FULL: 9449 case SPEED_100 + DUPLEX_HALF: 9450 goto err_inval; 9451 default: 9452 break; 9453 } 9454 } 9455 9456 switch (spd + dplx) { 9457 case SPEED_10 + DUPLEX_HALF: 9458 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9459 break; 9460 case SPEED_10 + DUPLEX_FULL: 9461 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9462 break; 9463 case SPEED_100 + DUPLEX_HALF: 9464 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9465 break; 9466 case SPEED_100 + DUPLEX_FULL: 9467 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9468 break; 9469 case SPEED_1000 + DUPLEX_FULL: 9470 mac->autoneg = 1; 9471 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9472 break; 9473 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9474 default: 9475 goto err_inval; 9476 } 9477 9478 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9479 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9480 9481 return 0; 9482 9483 err_inval: 9484 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9485 return -EINVAL; 9486 } 9487 9488 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9489 bool runtime) 9490 { 9491 struct net_device *netdev = pci_get_drvdata(pdev); 9492 struct igb_adapter *adapter = netdev_priv(netdev); 9493 struct e1000_hw *hw = &adapter->hw; 9494 u32 ctrl, rctl, status; 9495 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9496 bool wake; 9497 9498 rtnl_lock(); 9499 netif_device_detach(netdev); 9500 9501 if (netif_running(netdev)) 9502 __igb_close(netdev, true); 9503 9504 igb_ptp_suspend(adapter); 9505 9506 igb_clear_interrupt_scheme(adapter); 9507 rtnl_unlock(); 9508 9509 status = rd32(E1000_STATUS); 9510 if (status & E1000_STATUS_LU) 9511 wufc &= ~E1000_WUFC_LNKC; 9512 9513 if (wufc) { 9514 igb_setup_rctl(adapter); 9515 igb_set_rx_mode(netdev); 9516 9517 /* turn on all-multi mode if wake on multicast is enabled */ 9518 if (wufc & E1000_WUFC_MC) { 9519 rctl = rd32(E1000_RCTL); 9520 rctl |= E1000_RCTL_MPE; 9521 wr32(E1000_RCTL, rctl); 9522 } 9523 9524 ctrl = rd32(E1000_CTRL); 9525 ctrl |= E1000_CTRL_ADVD3WUC; 9526 wr32(E1000_CTRL, ctrl); 9527 9528 /* Allow time for pending master requests to run */ 9529 igb_disable_pcie_master(hw); 9530 9531 wr32(E1000_WUC, E1000_WUC_PME_EN); 9532 wr32(E1000_WUFC, wufc); 9533 } else { 9534 wr32(E1000_WUC, 0); 9535 wr32(E1000_WUFC, 0); 9536 } 9537 9538 wake = wufc || adapter->en_mng_pt; 9539 if (!wake) 9540 igb_power_down_link(adapter); 9541 else 9542 igb_power_up_link(adapter); 9543 9544 if (enable_wake) 9545 *enable_wake = wake; 9546 9547 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9548 * would have already happened in close and is redundant. 9549 */ 9550 igb_release_hw_control(adapter); 9551 9552 pci_disable_device(pdev); 9553 9554 return 0; 9555 } 9556 9557 static void igb_deliver_wake_packet(struct net_device *netdev) 9558 { 9559 struct igb_adapter *adapter = netdev_priv(netdev); 9560 struct e1000_hw *hw = &adapter->hw; 9561 struct sk_buff *skb; 9562 u32 wupl; 9563 9564 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9565 9566 /* WUPM stores only the first 128 bytes of the wake packet. 9567 * Read the packet only if we have the whole thing. 9568 */ 9569 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9570 return; 9571 9572 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9573 if (!skb) 9574 return; 9575 9576 skb_put(skb, wupl); 9577 9578 /* Ensure reads are 32-bit aligned */ 9579 wupl = roundup(wupl, 4); 9580 9581 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9582 9583 skb->protocol = eth_type_trans(skb, netdev); 9584 netif_rx(skb); 9585 } 9586 9587 static int igb_suspend(struct device *dev) 9588 { 9589 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9590 } 9591 9592 static int __igb_resume(struct device *dev, bool rpm) 9593 { 9594 struct pci_dev *pdev = to_pci_dev(dev); 9595 struct net_device *netdev = pci_get_drvdata(pdev); 9596 struct igb_adapter *adapter = netdev_priv(netdev); 9597 struct e1000_hw *hw = &adapter->hw; 9598 u32 err, val; 9599 9600 pci_set_power_state(pdev, PCI_D0); 9601 pci_restore_state(pdev); 9602 pci_save_state(pdev); 9603 9604 if (!pci_device_is_present(pdev)) 9605 return -ENODEV; 9606 err = pci_enable_device_mem(pdev); 9607 if (err) { 9608 dev_err(&pdev->dev, 9609 "igb: Cannot enable PCI device from suspend\n"); 9610 return err; 9611 } 9612 pci_set_master(pdev); 9613 9614 pci_enable_wake(pdev, PCI_D3hot, 0); 9615 pci_enable_wake(pdev, PCI_D3cold, 0); 9616 9617 if (igb_init_interrupt_scheme(adapter, true)) { 9618 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9619 return -ENOMEM; 9620 } 9621 9622 igb_reset(adapter); 9623 9624 /* let the f/w know that the h/w is now under the control of the 9625 * driver. 9626 */ 9627 igb_get_hw_control(adapter); 9628 9629 val = rd32(E1000_WUS); 9630 if (val & WAKE_PKT_WUS) 9631 igb_deliver_wake_packet(netdev); 9632 9633 wr32(E1000_WUS, ~0); 9634 9635 if (!rpm) 9636 rtnl_lock(); 9637 if (!err && netif_running(netdev)) 9638 err = __igb_open(netdev, true); 9639 9640 if (!err) 9641 netif_device_attach(netdev); 9642 if (!rpm) 9643 rtnl_unlock(); 9644 9645 return err; 9646 } 9647 9648 static int igb_resume(struct device *dev) 9649 { 9650 return __igb_resume(dev, false); 9651 } 9652 9653 static int igb_runtime_idle(struct device *dev) 9654 { 9655 struct net_device *netdev = dev_get_drvdata(dev); 9656 struct igb_adapter *adapter = netdev_priv(netdev); 9657 9658 if (!igb_has_link(adapter)) 9659 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9660 9661 return -EBUSY; 9662 } 9663 9664 static int igb_runtime_suspend(struct device *dev) 9665 { 9666 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9667 } 9668 9669 static int igb_runtime_resume(struct device *dev) 9670 { 9671 return __igb_resume(dev, true); 9672 } 9673 9674 static void igb_shutdown(struct pci_dev *pdev) 9675 { 9676 bool wake; 9677 9678 __igb_shutdown(pdev, &wake, 0); 9679 9680 if (system_state == SYSTEM_POWER_OFF) { 9681 pci_wake_from_d3(pdev, wake); 9682 pci_set_power_state(pdev, PCI_D3hot); 9683 } 9684 } 9685 9686 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9687 { 9688 #ifdef CONFIG_PCI_IOV 9689 int err; 9690 9691 if (num_vfs == 0) { 9692 return igb_disable_sriov(dev, true); 9693 } else { 9694 err = igb_enable_sriov(dev, num_vfs, true); 9695 return err ? err : num_vfs; 9696 } 9697 #endif 9698 return 0; 9699 } 9700 9701 /** 9702 * igb_io_error_detected - called when PCI error is detected 9703 * @pdev: Pointer to PCI device 9704 * @state: The current pci connection state 9705 * 9706 * This function is called after a PCI bus error affecting 9707 * this device has been detected. 9708 **/ 9709 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9710 pci_channel_state_t state) 9711 { 9712 struct net_device *netdev = pci_get_drvdata(pdev); 9713 struct igb_adapter *adapter = netdev_priv(netdev); 9714 9715 if (state == pci_channel_io_normal) { 9716 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9717 return PCI_ERS_RESULT_CAN_RECOVER; 9718 } 9719 9720 netif_device_detach(netdev); 9721 9722 if (state == pci_channel_io_perm_failure) 9723 return PCI_ERS_RESULT_DISCONNECT; 9724 9725 rtnl_lock(); 9726 if (netif_running(netdev)) 9727 igb_down(adapter); 9728 rtnl_unlock(); 9729 9730 pci_disable_device(pdev); 9731 9732 /* Request a slot reset. */ 9733 return PCI_ERS_RESULT_NEED_RESET; 9734 } 9735 9736 /** 9737 * igb_io_slot_reset - called after the pci bus has been reset. 9738 * @pdev: Pointer to PCI device 9739 * 9740 * Restart the card from scratch, as if from a cold-boot. Implementation 9741 * resembles the first-half of the __igb_resume routine. 9742 **/ 9743 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9744 { 9745 struct net_device *netdev = pci_get_drvdata(pdev); 9746 struct igb_adapter *adapter = netdev_priv(netdev); 9747 struct e1000_hw *hw = &adapter->hw; 9748 pci_ers_result_t result; 9749 9750 if (pci_enable_device_mem(pdev)) { 9751 dev_err(&pdev->dev, 9752 "Cannot re-enable PCI device after reset.\n"); 9753 result = PCI_ERS_RESULT_DISCONNECT; 9754 } else { 9755 pci_set_master(pdev); 9756 pci_restore_state(pdev); 9757 pci_save_state(pdev); 9758 9759 pci_enable_wake(pdev, PCI_D3hot, 0); 9760 pci_enable_wake(pdev, PCI_D3cold, 0); 9761 9762 /* In case of PCI error, adapter lose its HW address 9763 * so we should re-assign it here. 9764 */ 9765 hw->hw_addr = adapter->io_addr; 9766 9767 igb_reset(adapter); 9768 wr32(E1000_WUS, ~0); 9769 result = PCI_ERS_RESULT_RECOVERED; 9770 } 9771 9772 return result; 9773 } 9774 9775 /** 9776 * igb_io_resume - called when traffic can start flowing again. 9777 * @pdev: Pointer to PCI device 9778 * 9779 * This callback is called when the error recovery driver tells us that 9780 * its OK to resume normal operation. Implementation resembles the 9781 * second-half of the __igb_resume routine. 9782 */ 9783 static void igb_io_resume(struct pci_dev *pdev) 9784 { 9785 struct net_device *netdev = pci_get_drvdata(pdev); 9786 struct igb_adapter *adapter = netdev_priv(netdev); 9787 9788 rtnl_lock(); 9789 if (netif_running(netdev)) { 9790 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9791 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9792 rtnl_unlock(); 9793 return; 9794 } 9795 9796 if (igb_up(adapter)) { 9797 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9798 rtnl_unlock(); 9799 return; 9800 } 9801 } 9802 rtnl_unlock(); 9803 9804 netif_device_attach(netdev); 9805 9806 /* let the f/w know that the h/w is now under the control of the 9807 * driver. 9808 */ 9809 igb_get_hw_control(adapter); 9810 } 9811 9812 /** 9813 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9814 * @adapter: Pointer to adapter structure 9815 * @index: Index of the RAR entry which need to be synced with MAC table 9816 **/ 9817 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9818 { 9819 struct e1000_hw *hw = &adapter->hw; 9820 u32 rar_low, rar_high; 9821 u8 *addr = adapter->mac_table[index].addr; 9822 9823 /* HW expects these to be in network order when they are plugged 9824 * into the registers which are little endian. In order to guarantee 9825 * that ordering we need to do an leXX_to_cpup here in order to be 9826 * ready for the byteswap that occurs with writel 9827 */ 9828 rar_low = le32_to_cpup((__le32 *)(addr)); 9829 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9830 9831 /* Indicate to hardware the Address is Valid. */ 9832 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9833 if (is_valid_ether_addr(addr)) 9834 rar_high |= E1000_RAH_AV; 9835 9836 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9837 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9838 9839 switch (hw->mac.type) { 9840 case e1000_82575: 9841 case e1000_i210: 9842 if (adapter->mac_table[index].state & 9843 IGB_MAC_STATE_QUEUE_STEERING) 9844 rar_high |= E1000_RAH_QSEL_ENABLE; 9845 9846 rar_high |= E1000_RAH_POOL_1 * 9847 adapter->mac_table[index].queue; 9848 break; 9849 default: 9850 rar_high |= E1000_RAH_POOL_1 << 9851 adapter->mac_table[index].queue; 9852 break; 9853 } 9854 } 9855 9856 wr32(E1000_RAL(index), rar_low); 9857 wrfl(); 9858 wr32(E1000_RAH(index), rar_high); 9859 wrfl(); 9860 } 9861 9862 static int igb_set_vf_mac(struct igb_adapter *adapter, 9863 int vf, unsigned char *mac_addr) 9864 { 9865 struct e1000_hw *hw = &adapter->hw; 9866 /* VF MAC addresses start at end of receive addresses and moves 9867 * towards the first, as a result a collision should not be possible 9868 */ 9869 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9870 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9871 9872 ether_addr_copy(vf_mac_addr, mac_addr); 9873 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9874 adapter->mac_table[rar_entry].queue = vf; 9875 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9876 igb_rar_set_index(adapter, rar_entry); 9877 9878 return 0; 9879 } 9880 9881 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9882 { 9883 struct igb_adapter *adapter = netdev_priv(netdev); 9884 9885 if (vf >= adapter->vfs_allocated_count) 9886 return -EINVAL; 9887 9888 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9889 * flag and allows to overwrite the MAC via VF netdev. This 9890 * is necessary to allow libvirt a way to restore the original 9891 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9892 * down a VM. 9893 */ 9894 if (is_zero_ether_addr(mac)) { 9895 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9896 dev_info(&adapter->pdev->dev, 9897 "remove administratively set MAC on VF %d\n", 9898 vf); 9899 } else if (is_valid_ether_addr(mac)) { 9900 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9901 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9902 mac, vf); 9903 dev_info(&adapter->pdev->dev, 9904 "Reload the VF driver to make this change effective."); 9905 /* Generate additional warning if PF is down */ 9906 if (test_bit(__IGB_DOWN, &adapter->state)) { 9907 dev_warn(&adapter->pdev->dev, 9908 "The VF MAC address has been set, but the PF device is not up.\n"); 9909 dev_warn(&adapter->pdev->dev, 9910 "Bring the PF device up before attempting to use the VF device.\n"); 9911 } 9912 } else { 9913 return -EINVAL; 9914 } 9915 return igb_set_vf_mac(adapter, vf, mac); 9916 } 9917 9918 static int igb_link_mbps(int internal_link_speed) 9919 { 9920 switch (internal_link_speed) { 9921 case SPEED_100: 9922 return 100; 9923 case SPEED_1000: 9924 return 1000; 9925 default: 9926 return 0; 9927 } 9928 } 9929 9930 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9931 int link_speed) 9932 { 9933 int rf_dec, rf_int; 9934 u32 bcnrc_val; 9935 9936 if (tx_rate != 0) { 9937 /* Calculate the rate factor values to set */ 9938 rf_int = link_speed / tx_rate; 9939 rf_dec = (link_speed - (rf_int * tx_rate)); 9940 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9941 tx_rate; 9942 9943 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9944 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9945 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9946 } else { 9947 bcnrc_val = 0; 9948 } 9949 9950 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9951 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9952 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9953 */ 9954 wr32(E1000_RTTBCNRM, 0x14); 9955 wr32(E1000_RTTBCNRC, bcnrc_val); 9956 } 9957 9958 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9959 { 9960 int actual_link_speed, i; 9961 bool reset_rate = false; 9962 9963 /* VF TX rate limit was not set or not supported */ 9964 if ((adapter->vf_rate_link_speed == 0) || 9965 (adapter->hw.mac.type != e1000_82576)) 9966 return; 9967 9968 actual_link_speed = igb_link_mbps(adapter->link_speed); 9969 if (actual_link_speed != adapter->vf_rate_link_speed) { 9970 reset_rate = true; 9971 adapter->vf_rate_link_speed = 0; 9972 dev_info(&adapter->pdev->dev, 9973 "Link speed has been changed. VF Transmit rate is disabled\n"); 9974 } 9975 9976 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9977 if (reset_rate) 9978 adapter->vf_data[i].tx_rate = 0; 9979 9980 igb_set_vf_rate_limit(&adapter->hw, i, 9981 adapter->vf_data[i].tx_rate, 9982 actual_link_speed); 9983 } 9984 } 9985 9986 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9987 int min_tx_rate, int max_tx_rate) 9988 { 9989 struct igb_adapter *adapter = netdev_priv(netdev); 9990 struct e1000_hw *hw = &adapter->hw; 9991 int actual_link_speed; 9992 9993 if (hw->mac.type != e1000_82576) 9994 return -EOPNOTSUPP; 9995 9996 if (min_tx_rate) 9997 return -EINVAL; 9998 9999 actual_link_speed = igb_link_mbps(adapter->link_speed); 10000 if ((vf >= adapter->vfs_allocated_count) || 10001 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 10002 (max_tx_rate < 0) || 10003 (max_tx_rate > actual_link_speed)) 10004 return -EINVAL; 10005 10006 adapter->vf_rate_link_speed = actual_link_speed; 10007 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 10008 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 10009 10010 return 0; 10011 } 10012 10013 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 10014 bool setting) 10015 { 10016 struct igb_adapter *adapter = netdev_priv(netdev); 10017 struct e1000_hw *hw = &adapter->hw; 10018 u32 reg_val, reg_offset; 10019 10020 if (!adapter->vfs_allocated_count) 10021 return -EOPNOTSUPP; 10022 10023 if (vf >= adapter->vfs_allocated_count) 10024 return -EINVAL; 10025 10026 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 10027 reg_val = rd32(reg_offset); 10028 if (setting) 10029 reg_val |= (BIT(vf) | 10030 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10031 else 10032 reg_val &= ~(BIT(vf) | 10033 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10034 wr32(reg_offset, reg_val); 10035 10036 adapter->vf_data[vf].spoofchk_enabled = setting; 10037 return 0; 10038 } 10039 10040 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 10041 { 10042 struct igb_adapter *adapter = netdev_priv(netdev); 10043 10044 if (vf >= adapter->vfs_allocated_count) 10045 return -EINVAL; 10046 if (adapter->vf_data[vf].trusted == setting) 10047 return 0; 10048 10049 adapter->vf_data[vf].trusted = setting; 10050 10051 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 10052 vf, setting ? "" : "not "); 10053 return 0; 10054 } 10055 10056 static int igb_ndo_get_vf_config(struct net_device *netdev, 10057 int vf, struct ifla_vf_info *ivi) 10058 { 10059 struct igb_adapter *adapter = netdev_priv(netdev); 10060 if (vf >= adapter->vfs_allocated_count) 10061 return -EINVAL; 10062 ivi->vf = vf; 10063 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10064 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10065 ivi->min_tx_rate = 0; 10066 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10067 ivi->qos = adapter->vf_data[vf].pf_qos; 10068 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10069 ivi->trusted = adapter->vf_data[vf].trusted; 10070 return 0; 10071 } 10072 10073 static void igb_vmm_control(struct igb_adapter *adapter) 10074 { 10075 struct e1000_hw *hw = &adapter->hw; 10076 u32 reg; 10077 10078 switch (hw->mac.type) { 10079 case e1000_82575: 10080 case e1000_i210: 10081 case e1000_i211: 10082 case e1000_i354: 10083 default: 10084 /* replication is not supported for 82575 */ 10085 return; 10086 case e1000_82576: 10087 /* notify HW that the MAC is adding vlan tags */ 10088 reg = rd32(E1000_DTXCTL); 10089 reg |= E1000_DTXCTL_VLAN_ADDED; 10090 wr32(E1000_DTXCTL, reg); 10091 fallthrough; 10092 case e1000_82580: 10093 /* enable replication vlan tag stripping */ 10094 reg = rd32(E1000_RPLOLR); 10095 reg |= E1000_RPLOLR_STRVLAN; 10096 wr32(E1000_RPLOLR, reg); 10097 fallthrough; 10098 case e1000_i350: 10099 /* none of the above registers are supported by i350 */ 10100 break; 10101 } 10102 10103 if (adapter->vfs_allocated_count) { 10104 igb_vmdq_set_loopback_pf(hw, true); 10105 igb_vmdq_set_replication_pf(hw, true); 10106 igb_vmdq_set_anti_spoofing_pf(hw, true, 10107 adapter->vfs_allocated_count); 10108 } else { 10109 igb_vmdq_set_loopback_pf(hw, false); 10110 igb_vmdq_set_replication_pf(hw, false); 10111 } 10112 } 10113 10114 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10115 { 10116 struct e1000_hw *hw = &adapter->hw; 10117 u32 dmac_thr; 10118 u16 hwm; 10119 u32 reg; 10120 10121 if (hw->mac.type > e1000_82580) { 10122 if (adapter->flags & IGB_FLAG_DMAC) { 10123 /* force threshold to 0. */ 10124 wr32(E1000_DMCTXTH, 0); 10125 10126 /* DMA Coalescing high water mark needs to be greater 10127 * than the Rx threshold. Set hwm to PBA - max frame 10128 * size in 16B units, capping it at PBA - 6KB. 10129 */ 10130 hwm = 64 * (pba - 6); 10131 reg = rd32(E1000_FCRTC); 10132 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10133 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10134 wr32(E1000_FCRTC, reg); 10135 10136 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10137 * frame size, capping it at PBA - 10KB. 10138 */ 10139 dmac_thr = pba - 10; 10140 reg = rd32(E1000_DMACR); 10141 reg &= ~E1000_DMACR_DMACTHR_MASK; 10142 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10143 10144 /* transition to L0x or L1 if available..*/ 10145 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10146 10147 /* watchdog timer= +-1000 usec in 32usec intervals */ 10148 reg |= (1000 >> 5); 10149 10150 /* Disable BMC-to-OS Watchdog Enable */ 10151 if (hw->mac.type != e1000_i354) 10152 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10153 wr32(E1000_DMACR, reg); 10154 10155 /* no lower threshold to disable 10156 * coalescing(smart fifb)-UTRESH=0 10157 */ 10158 wr32(E1000_DMCRTRH, 0); 10159 10160 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10161 10162 wr32(E1000_DMCTLX, reg); 10163 10164 /* free space in tx packet buffer to wake from 10165 * DMA coal 10166 */ 10167 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10168 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10169 } 10170 10171 if (hw->mac.type >= e1000_i210 || 10172 (adapter->flags & IGB_FLAG_DMAC)) { 10173 reg = rd32(E1000_PCIEMISC); 10174 reg |= E1000_PCIEMISC_LX_DECISION; 10175 wr32(E1000_PCIEMISC, reg); 10176 } /* endif adapter->dmac is not disabled */ 10177 } else if (hw->mac.type == e1000_82580) { 10178 u32 reg = rd32(E1000_PCIEMISC); 10179 10180 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10181 wr32(E1000_DMACR, 0); 10182 } 10183 } 10184 10185 /** 10186 * igb_read_i2c_byte - Reads 8 bit word over I2C 10187 * @hw: pointer to hardware structure 10188 * @byte_offset: byte offset to read 10189 * @dev_addr: device address 10190 * @data: value read 10191 * 10192 * Performs byte read operation over I2C interface at 10193 * a specified device address. 10194 **/ 10195 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10196 u8 dev_addr, u8 *data) 10197 { 10198 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10199 struct i2c_client *this_client = adapter->i2c_client; 10200 s32 status; 10201 u16 swfw_mask = 0; 10202 10203 if (!this_client) 10204 return E1000_ERR_I2C; 10205 10206 swfw_mask = E1000_SWFW_PHY0_SM; 10207 10208 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10209 return E1000_ERR_SWFW_SYNC; 10210 10211 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10212 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10213 10214 if (status < 0) 10215 return E1000_ERR_I2C; 10216 else { 10217 *data = status; 10218 return 0; 10219 } 10220 } 10221 10222 /** 10223 * igb_write_i2c_byte - Writes 8 bit word over I2C 10224 * @hw: pointer to hardware structure 10225 * @byte_offset: byte offset to write 10226 * @dev_addr: device address 10227 * @data: value to write 10228 * 10229 * Performs byte write operation over I2C interface at 10230 * a specified device address. 10231 **/ 10232 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10233 u8 dev_addr, u8 data) 10234 { 10235 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10236 struct i2c_client *this_client = adapter->i2c_client; 10237 s32 status; 10238 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10239 10240 if (!this_client) 10241 return E1000_ERR_I2C; 10242 10243 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10244 return E1000_ERR_SWFW_SYNC; 10245 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10246 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10247 10248 if (status) 10249 return E1000_ERR_I2C; 10250 else 10251 return 0; 10252 10253 } 10254 10255 int igb_reinit_queues(struct igb_adapter *adapter) 10256 { 10257 struct net_device *netdev = adapter->netdev; 10258 struct pci_dev *pdev = adapter->pdev; 10259 int err = 0; 10260 10261 if (netif_running(netdev)) 10262 igb_close(netdev); 10263 10264 igb_reset_interrupt_capability(adapter); 10265 10266 if (igb_init_interrupt_scheme(adapter, true)) { 10267 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10268 return -ENOMEM; 10269 } 10270 10271 if (netif_running(netdev)) 10272 err = igb_open(netdev); 10273 10274 return err; 10275 } 10276 10277 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10278 { 10279 struct igb_nfc_filter *rule; 10280 10281 spin_lock(&adapter->nfc_lock); 10282 10283 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10284 igb_erase_filter(adapter, rule); 10285 10286 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10287 igb_erase_filter(adapter, rule); 10288 10289 spin_unlock(&adapter->nfc_lock); 10290 } 10291 10292 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10293 { 10294 struct igb_nfc_filter *rule; 10295 10296 spin_lock(&adapter->nfc_lock); 10297 10298 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10299 igb_add_filter(adapter, rule); 10300 10301 spin_unlock(&adapter->nfc_lock); 10302 } 10303 10304 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10305 igb_runtime_suspend, igb_runtime_resume, 10306 igb_runtime_idle); 10307 10308 static struct pci_driver igb_driver = { 10309 .name = igb_driver_name, 10310 .id_table = igb_pci_tbl, 10311 .probe = igb_probe, 10312 .remove = igb_remove, 10313 .driver.pm = pm_ptr(&igb_pm_ops), 10314 .shutdown = igb_shutdown, 10315 .sriov_configure = igb_pci_sriov_configure, 10316 .err_handler = &igb_err_handler 10317 }; 10318 10319 /* igb_main.c */ 10320