1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 /* ethtool support for igb */ 29 30 #include <linux/vmalloc.h> 31 #include <linux/netdevice.h> 32 #include <linux/pci.h> 33 #include <linux/delay.h> 34 #include <linux/interrupt.h> 35 #include <linux/if_ether.h> 36 #include <linux/ethtool.h> 37 #include <linux/sched.h> 38 #include <linux/slab.h> 39 #include <linux/pm_runtime.h> 40 41 #include "igb.h" 42 43 struct igb_stats { 44 char stat_string[ETH_GSTRING_LEN]; 45 int sizeof_stat; 46 int stat_offset; 47 }; 48 49 #define IGB_STAT(_name, _stat) { \ 50 .stat_string = _name, \ 51 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 52 .stat_offset = offsetof(struct igb_adapter, _stat) \ 53 } 54 static const struct igb_stats igb_gstrings_stats[] = { 55 IGB_STAT("rx_packets", stats.gprc), 56 IGB_STAT("tx_packets", stats.gptc), 57 IGB_STAT("rx_bytes", stats.gorc), 58 IGB_STAT("tx_bytes", stats.gotc), 59 IGB_STAT("rx_broadcast", stats.bprc), 60 IGB_STAT("tx_broadcast", stats.bptc), 61 IGB_STAT("rx_multicast", stats.mprc), 62 IGB_STAT("tx_multicast", stats.mptc), 63 IGB_STAT("multicast", stats.mprc), 64 IGB_STAT("collisions", stats.colc), 65 IGB_STAT("rx_crc_errors", stats.crcerrs), 66 IGB_STAT("rx_no_buffer_count", stats.rnbc), 67 IGB_STAT("rx_missed_errors", stats.mpc), 68 IGB_STAT("tx_aborted_errors", stats.ecol), 69 IGB_STAT("tx_carrier_errors", stats.tncrs), 70 IGB_STAT("tx_window_errors", stats.latecol), 71 IGB_STAT("tx_abort_late_coll", stats.latecol), 72 IGB_STAT("tx_deferred_ok", stats.dc), 73 IGB_STAT("tx_single_coll_ok", stats.scc), 74 IGB_STAT("tx_multi_coll_ok", stats.mcc), 75 IGB_STAT("tx_timeout_count", tx_timeout_count), 76 IGB_STAT("rx_long_length_errors", stats.roc), 77 IGB_STAT("rx_short_length_errors", stats.ruc), 78 IGB_STAT("rx_align_errors", stats.algnerrc), 79 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 80 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 81 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 82 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 83 IGB_STAT("tx_flow_control_xon", stats.xontxc), 84 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 85 IGB_STAT("rx_long_byte_count", stats.gorc), 86 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 87 IGB_STAT("tx_smbus", stats.mgptc), 88 IGB_STAT("rx_smbus", stats.mgprc), 89 IGB_STAT("dropped_smbus", stats.mgpdc), 90 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 91 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 92 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 93 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 94 }; 95 96 #define IGB_NETDEV_STAT(_net_stat) { \ 97 .stat_string = __stringify(_net_stat), \ 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 100 } 101 static const struct igb_stats igb_gstrings_net_stats[] = { 102 IGB_NETDEV_STAT(rx_errors), 103 IGB_NETDEV_STAT(tx_errors), 104 IGB_NETDEV_STAT(tx_dropped), 105 IGB_NETDEV_STAT(rx_length_errors), 106 IGB_NETDEV_STAT(rx_over_errors), 107 IGB_NETDEV_STAT(rx_frame_errors), 108 IGB_NETDEV_STAT(rx_fifo_errors), 109 IGB_NETDEV_STAT(tx_fifo_errors), 110 IGB_NETDEV_STAT(tx_heartbeat_errors) 111 }; 112 113 #define IGB_GLOBAL_STATS_LEN \ 114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 115 #define IGB_NETDEV_STATS_LEN \ 116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 117 #define IGB_RX_QUEUE_STATS_LEN \ 118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 119 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 121 122 #define IGB_QUEUE_STATS_LEN \ 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 124 IGB_RX_QUEUE_STATS_LEN) + \ 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 126 IGB_TX_QUEUE_STATS_LEN)) 127 #define IGB_STATS_LEN \ 128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 129 130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 131 "Register test (offline)", "Eeprom test (offline)", 132 "Interrupt test (offline)", "Loopback test (offline)", 133 "Link test (on/offline)" 134 }; 135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 136 137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 138 { 139 struct igb_adapter *adapter = netdev_priv(netdev); 140 struct e1000_hw *hw = &adapter->hw; 141 u32 status; 142 143 if (hw->phy.media_type == e1000_media_type_copper) { 144 145 ecmd->supported = (SUPPORTED_10baseT_Half | 146 SUPPORTED_10baseT_Full | 147 SUPPORTED_100baseT_Half | 148 SUPPORTED_100baseT_Full | 149 SUPPORTED_1000baseT_Full| 150 SUPPORTED_Autoneg | 151 SUPPORTED_TP); 152 ecmd->advertising = (ADVERTISED_TP | 153 ADVERTISED_Pause); 154 155 if (hw->mac.autoneg == 1) { 156 ecmd->advertising |= ADVERTISED_Autoneg; 157 /* the e1000 autoneg seems to match ethtool nicely */ 158 ecmd->advertising |= hw->phy.autoneg_advertised; 159 } 160 161 ecmd->port = PORT_TP; 162 ecmd->phy_address = hw->phy.addr; 163 } else { 164 ecmd->supported = (SUPPORTED_1000baseT_Full | 165 SUPPORTED_FIBRE | 166 SUPPORTED_Autoneg); 167 168 ecmd->advertising = (ADVERTISED_1000baseT_Full | 169 ADVERTISED_FIBRE | 170 ADVERTISED_Autoneg | 171 ADVERTISED_Pause); 172 173 ecmd->port = PORT_FIBRE; 174 } 175 176 ecmd->transceiver = XCVR_INTERNAL; 177 178 status = rd32(E1000_STATUS); 179 180 if (status & E1000_STATUS_LU) { 181 182 if ((status & E1000_STATUS_SPEED_1000) || 183 hw->phy.media_type != e1000_media_type_copper) 184 ethtool_cmd_speed_set(ecmd, SPEED_1000); 185 else if (status & E1000_STATUS_SPEED_100) 186 ethtool_cmd_speed_set(ecmd, SPEED_100); 187 else 188 ethtool_cmd_speed_set(ecmd, SPEED_10); 189 190 if ((status & E1000_STATUS_FD) || 191 hw->phy.media_type != e1000_media_type_copper) 192 ecmd->duplex = DUPLEX_FULL; 193 else 194 ecmd->duplex = DUPLEX_HALF; 195 } else { 196 ethtool_cmd_speed_set(ecmd, -1); 197 ecmd->duplex = -1; 198 } 199 200 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 201 return 0; 202 } 203 204 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 205 { 206 struct igb_adapter *adapter = netdev_priv(netdev); 207 struct e1000_hw *hw = &adapter->hw; 208 209 /* When SoL/IDER sessions are active, autoneg/speed/duplex 210 * cannot be changed */ 211 if (igb_check_reset_block(hw)) { 212 dev_err(&adapter->pdev->dev, "Cannot change link " 213 "characteristics when SoL/IDER is active.\n"); 214 return -EINVAL; 215 } 216 217 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 218 msleep(1); 219 220 if (ecmd->autoneg == AUTONEG_ENABLE) { 221 hw->mac.autoneg = 1; 222 hw->phy.autoneg_advertised = ecmd->advertising | 223 ADVERTISED_TP | 224 ADVERTISED_Autoneg; 225 ecmd->advertising = hw->phy.autoneg_advertised; 226 if (adapter->fc_autoneg) 227 hw->fc.requested_mode = e1000_fc_default; 228 } else { 229 u32 speed = ethtool_cmd_speed(ecmd); 230 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 231 clear_bit(__IGB_RESETTING, &adapter->state); 232 return -EINVAL; 233 } 234 } 235 236 /* reset the link */ 237 if (netif_running(adapter->netdev)) { 238 igb_down(adapter); 239 igb_up(adapter); 240 } else 241 igb_reset(adapter); 242 243 clear_bit(__IGB_RESETTING, &adapter->state); 244 return 0; 245 } 246 247 static u32 igb_get_link(struct net_device *netdev) 248 { 249 struct igb_adapter *adapter = netdev_priv(netdev); 250 struct e1000_mac_info *mac = &adapter->hw.mac; 251 252 /* 253 * If the link is not reported up to netdev, interrupts are disabled, 254 * and so the physical link state may have changed since we last 255 * looked. Set get_link_status to make sure that the true link 256 * state is interrogated, rather than pulling a cached and possibly 257 * stale link state from the driver. 258 */ 259 if (!netif_carrier_ok(netdev)) 260 mac->get_link_status = 1; 261 262 return igb_has_link(adapter); 263 } 264 265 static void igb_get_pauseparam(struct net_device *netdev, 266 struct ethtool_pauseparam *pause) 267 { 268 struct igb_adapter *adapter = netdev_priv(netdev); 269 struct e1000_hw *hw = &adapter->hw; 270 271 pause->autoneg = 272 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 273 274 if (hw->fc.current_mode == e1000_fc_rx_pause) 275 pause->rx_pause = 1; 276 else if (hw->fc.current_mode == e1000_fc_tx_pause) 277 pause->tx_pause = 1; 278 else if (hw->fc.current_mode == e1000_fc_full) { 279 pause->rx_pause = 1; 280 pause->tx_pause = 1; 281 } 282 } 283 284 static int igb_set_pauseparam(struct net_device *netdev, 285 struct ethtool_pauseparam *pause) 286 { 287 struct igb_adapter *adapter = netdev_priv(netdev); 288 struct e1000_hw *hw = &adapter->hw; 289 int retval = 0; 290 291 adapter->fc_autoneg = pause->autoneg; 292 293 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 294 msleep(1); 295 296 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 297 hw->fc.requested_mode = e1000_fc_default; 298 if (netif_running(adapter->netdev)) { 299 igb_down(adapter); 300 igb_up(adapter); 301 } else { 302 igb_reset(adapter); 303 } 304 } else { 305 if (pause->rx_pause && pause->tx_pause) 306 hw->fc.requested_mode = e1000_fc_full; 307 else if (pause->rx_pause && !pause->tx_pause) 308 hw->fc.requested_mode = e1000_fc_rx_pause; 309 else if (!pause->rx_pause && pause->tx_pause) 310 hw->fc.requested_mode = e1000_fc_tx_pause; 311 else if (!pause->rx_pause && !pause->tx_pause) 312 hw->fc.requested_mode = e1000_fc_none; 313 314 hw->fc.current_mode = hw->fc.requested_mode; 315 316 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 317 igb_force_mac_fc(hw) : igb_setup_link(hw)); 318 } 319 320 clear_bit(__IGB_RESETTING, &adapter->state); 321 return retval; 322 } 323 324 static u32 igb_get_msglevel(struct net_device *netdev) 325 { 326 struct igb_adapter *adapter = netdev_priv(netdev); 327 return adapter->msg_enable; 328 } 329 330 static void igb_set_msglevel(struct net_device *netdev, u32 data) 331 { 332 struct igb_adapter *adapter = netdev_priv(netdev); 333 adapter->msg_enable = data; 334 } 335 336 static int igb_get_regs_len(struct net_device *netdev) 337 { 338 #define IGB_REGS_LEN 739 339 return IGB_REGS_LEN * sizeof(u32); 340 } 341 342 static void igb_get_regs(struct net_device *netdev, 343 struct ethtool_regs *regs, void *p) 344 { 345 struct igb_adapter *adapter = netdev_priv(netdev); 346 struct e1000_hw *hw = &adapter->hw; 347 u32 *regs_buff = p; 348 u8 i; 349 350 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 351 352 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 353 354 /* General Registers */ 355 regs_buff[0] = rd32(E1000_CTRL); 356 regs_buff[1] = rd32(E1000_STATUS); 357 regs_buff[2] = rd32(E1000_CTRL_EXT); 358 regs_buff[3] = rd32(E1000_MDIC); 359 regs_buff[4] = rd32(E1000_SCTL); 360 regs_buff[5] = rd32(E1000_CONNSW); 361 regs_buff[6] = rd32(E1000_VET); 362 regs_buff[7] = rd32(E1000_LEDCTL); 363 regs_buff[8] = rd32(E1000_PBA); 364 regs_buff[9] = rd32(E1000_PBS); 365 regs_buff[10] = rd32(E1000_FRTIMER); 366 regs_buff[11] = rd32(E1000_TCPTIMER); 367 368 /* NVM Register */ 369 regs_buff[12] = rd32(E1000_EECD); 370 371 /* Interrupt */ 372 /* Reading EICS for EICR because they read the 373 * same but EICS does not clear on read */ 374 regs_buff[13] = rd32(E1000_EICS); 375 regs_buff[14] = rd32(E1000_EICS); 376 regs_buff[15] = rd32(E1000_EIMS); 377 regs_buff[16] = rd32(E1000_EIMC); 378 regs_buff[17] = rd32(E1000_EIAC); 379 regs_buff[18] = rd32(E1000_EIAM); 380 /* Reading ICS for ICR because they read the 381 * same but ICS does not clear on read */ 382 regs_buff[19] = rd32(E1000_ICS); 383 regs_buff[20] = rd32(E1000_ICS); 384 regs_buff[21] = rd32(E1000_IMS); 385 regs_buff[22] = rd32(E1000_IMC); 386 regs_buff[23] = rd32(E1000_IAC); 387 regs_buff[24] = rd32(E1000_IAM); 388 regs_buff[25] = rd32(E1000_IMIRVP); 389 390 /* Flow Control */ 391 regs_buff[26] = rd32(E1000_FCAL); 392 regs_buff[27] = rd32(E1000_FCAH); 393 regs_buff[28] = rd32(E1000_FCTTV); 394 regs_buff[29] = rd32(E1000_FCRTL); 395 regs_buff[30] = rd32(E1000_FCRTH); 396 regs_buff[31] = rd32(E1000_FCRTV); 397 398 /* Receive */ 399 regs_buff[32] = rd32(E1000_RCTL); 400 regs_buff[33] = rd32(E1000_RXCSUM); 401 regs_buff[34] = rd32(E1000_RLPML); 402 regs_buff[35] = rd32(E1000_RFCTL); 403 regs_buff[36] = rd32(E1000_MRQC); 404 regs_buff[37] = rd32(E1000_VT_CTL); 405 406 /* Transmit */ 407 regs_buff[38] = rd32(E1000_TCTL); 408 regs_buff[39] = rd32(E1000_TCTL_EXT); 409 regs_buff[40] = rd32(E1000_TIPG); 410 regs_buff[41] = rd32(E1000_DTXCTL); 411 412 /* Wake Up */ 413 regs_buff[42] = rd32(E1000_WUC); 414 regs_buff[43] = rd32(E1000_WUFC); 415 regs_buff[44] = rd32(E1000_WUS); 416 regs_buff[45] = rd32(E1000_IPAV); 417 regs_buff[46] = rd32(E1000_WUPL); 418 419 /* MAC */ 420 regs_buff[47] = rd32(E1000_PCS_CFG0); 421 regs_buff[48] = rd32(E1000_PCS_LCTL); 422 regs_buff[49] = rd32(E1000_PCS_LSTAT); 423 regs_buff[50] = rd32(E1000_PCS_ANADV); 424 regs_buff[51] = rd32(E1000_PCS_LPAB); 425 regs_buff[52] = rd32(E1000_PCS_NPTX); 426 regs_buff[53] = rd32(E1000_PCS_LPABNP); 427 428 /* Statistics */ 429 regs_buff[54] = adapter->stats.crcerrs; 430 regs_buff[55] = adapter->stats.algnerrc; 431 regs_buff[56] = adapter->stats.symerrs; 432 regs_buff[57] = adapter->stats.rxerrc; 433 regs_buff[58] = adapter->stats.mpc; 434 regs_buff[59] = adapter->stats.scc; 435 regs_buff[60] = adapter->stats.ecol; 436 regs_buff[61] = adapter->stats.mcc; 437 regs_buff[62] = adapter->stats.latecol; 438 regs_buff[63] = adapter->stats.colc; 439 regs_buff[64] = adapter->stats.dc; 440 regs_buff[65] = adapter->stats.tncrs; 441 regs_buff[66] = adapter->stats.sec; 442 regs_buff[67] = adapter->stats.htdpmc; 443 regs_buff[68] = adapter->stats.rlec; 444 regs_buff[69] = adapter->stats.xonrxc; 445 regs_buff[70] = adapter->stats.xontxc; 446 regs_buff[71] = adapter->stats.xoffrxc; 447 regs_buff[72] = adapter->stats.xofftxc; 448 regs_buff[73] = adapter->stats.fcruc; 449 regs_buff[74] = adapter->stats.prc64; 450 regs_buff[75] = adapter->stats.prc127; 451 regs_buff[76] = adapter->stats.prc255; 452 regs_buff[77] = adapter->stats.prc511; 453 regs_buff[78] = adapter->stats.prc1023; 454 regs_buff[79] = adapter->stats.prc1522; 455 regs_buff[80] = adapter->stats.gprc; 456 regs_buff[81] = adapter->stats.bprc; 457 regs_buff[82] = adapter->stats.mprc; 458 regs_buff[83] = adapter->stats.gptc; 459 regs_buff[84] = adapter->stats.gorc; 460 regs_buff[86] = adapter->stats.gotc; 461 regs_buff[88] = adapter->stats.rnbc; 462 regs_buff[89] = adapter->stats.ruc; 463 regs_buff[90] = adapter->stats.rfc; 464 regs_buff[91] = adapter->stats.roc; 465 regs_buff[92] = adapter->stats.rjc; 466 regs_buff[93] = adapter->stats.mgprc; 467 regs_buff[94] = adapter->stats.mgpdc; 468 regs_buff[95] = adapter->stats.mgptc; 469 regs_buff[96] = adapter->stats.tor; 470 regs_buff[98] = adapter->stats.tot; 471 regs_buff[100] = adapter->stats.tpr; 472 regs_buff[101] = adapter->stats.tpt; 473 regs_buff[102] = adapter->stats.ptc64; 474 regs_buff[103] = adapter->stats.ptc127; 475 regs_buff[104] = adapter->stats.ptc255; 476 regs_buff[105] = adapter->stats.ptc511; 477 regs_buff[106] = adapter->stats.ptc1023; 478 regs_buff[107] = adapter->stats.ptc1522; 479 regs_buff[108] = adapter->stats.mptc; 480 regs_buff[109] = adapter->stats.bptc; 481 regs_buff[110] = adapter->stats.tsctc; 482 regs_buff[111] = adapter->stats.iac; 483 regs_buff[112] = adapter->stats.rpthc; 484 regs_buff[113] = adapter->stats.hgptc; 485 regs_buff[114] = adapter->stats.hgorc; 486 regs_buff[116] = adapter->stats.hgotc; 487 regs_buff[118] = adapter->stats.lenerrs; 488 regs_buff[119] = adapter->stats.scvpc; 489 regs_buff[120] = adapter->stats.hrmpc; 490 491 for (i = 0; i < 4; i++) 492 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 493 for (i = 0; i < 4; i++) 494 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 495 for (i = 0; i < 4; i++) 496 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 497 for (i = 0; i < 4; i++) 498 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 499 for (i = 0; i < 4; i++) 500 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 501 for (i = 0; i < 4; i++) 502 regs_buff[141 + i] = rd32(E1000_RDH(i)); 503 for (i = 0; i < 4; i++) 504 regs_buff[145 + i] = rd32(E1000_RDT(i)); 505 for (i = 0; i < 4; i++) 506 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 507 508 for (i = 0; i < 10; i++) 509 regs_buff[153 + i] = rd32(E1000_EITR(i)); 510 for (i = 0; i < 8; i++) 511 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 512 for (i = 0; i < 8; i++) 513 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 514 for (i = 0; i < 16; i++) 515 regs_buff[179 + i] = rd32(E1000_RAL(i)); 516 for (i = 0; i < 16; i++) 517 regs_buff[195 + i] = rd32(E1000_RAH(i)); 518 519 for (i = 0; i < 4; i++) 520 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 521 for (i = 0; i < 4; i++) 522 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 523 for (i = 0; i < 4; i++) 524 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 525 for (i = 0; i < 4; i++) 526 regs_buff[223 + i] = rd32(E1000_TDH(i)); 527 for (i = 0; i < 4; i++) 528 regs_buff[227 + i] = rd32(E1000_TDT(i)); 529 for (i = 0; i < 4; i++) 530 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 531 for (i = 0; i < 4; i++) 532 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 533 for (i = 0; i < 4; i++) 534 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 535 for (i = 0; i < 4; i++) 536 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 537 538 for (i = 0; i < 4; i++) 539 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 540 for (i = 0; i < 4; i++) 541 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 542 for (i = 0; i < 32; i++) 543 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 544 for (i = 0; i < 128; i++) 545 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 546 for (i = 0; i < 128; i++) 547 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 548 for (i = 0; i < 4; i++) 549 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 550 551 regs_buff[547] = rd32(E1000_TDFH); 552 regs_buff[548] = rd32(E1000_TDFT); 553 regs_buff[549] = rd32(E1000_TDFHS); 554 regs_buff[550] = rd32(E1000_TDFPC); 555 556 if (hw->mac.type > e1000_82580) { 557 regs_buff[551] = adapter->stats.o2bgptc; 558 regs_buff[552] = adapter->stats.b2ospc; 559 regs_buff[553] = adapter->stats.o2bspc; 560 regs_buff[554] = adapter->stats.b2ogprc; 561 } 562 563 if (hw->mac.type != e1000_82576) 564 return; 565 for (i = 0; i < 12; i++) 566 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 567 for (i = 0; i < 4; i++) 568 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 569 for (i = 0; i < 12; i++) 570 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 571 for (i = 0; i < 12; i++) 572 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 573 for (i = 0; i < 12; i++) 574 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 575 for (i = 0; i < 12; i++) 576 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 577 for (i = 0; i < 12; i++) 578 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 579 for (i = 0; i < 12; i++) 580 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 581 582 for (i = 0; i < 12; i++) 583 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 584 for (i = 0; i < 12; i++) 585 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 586 for (i = 0; i < 12; i++) 587 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 588 for (i = 0; i < 12; i++) 589 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 590 for (i = 0; i < 12; i++) 591 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 592 for (i = 0; i < 12; i++) 593 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 594 for (i = 0; i < 12; i++) 595 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 596 for (i = 0; i < 12; i++) 597 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 598 } 599 600 static int igb_get_eeprom_len(struct net_device *netdev) 601 { 602 struct igb_adapter *adapter = netdev_priv(netdev); 603 return adapter->hw.nvm.word_size * 2; 604 } 605 606 static int igb_get_eeprom(struct net_device *netdev, 607 struct ethtool_eeprom *eeprom, u8 *bytes) 608 { 609 struct igb_adapter *adapter = netdev_priv(netdev); 610 struct e1000_hw *hw = &adapter->hw; 611 u16 *eeprom_buff; 612 int first_word, last_word; 613 int ret_val = 0; 614 u16 i; 615 616 if (eeprom->len == 0) 617 return -EINVAL; 618 619 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 620 621 first_word = eeprom->offset >> 1; 622 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 623 624 eeprom_buff = kmalloc(sizeof(u16) * 625 (last_word - first_word + 1), GFP_KERNEL); 626 if (!eeprom_buff) 627 return -ENOMEM; 628 629 if (hw->nvm.type == e1000_nvm_eeprom_spi) 630 ret_val = hw->nvm.ops.read(hw, first_word, 631 last_word - first_word + 1, 632 eeprom_buff); 633 else { 634 for (i = 0; i < last_word - first_word + 1; i++) { 635 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 636 &eeprom_buff[i]); 637 if (ret_val) 638 break; 639 } 640 } 641 642 /* Device's eeprom is always little-endian, word addressable */ 643 for (i = 0; i < last_word - first_word + 1; i++) 644 le16_to_cpus(&eeprom_buff[i]); 645 646 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 647 eeprom->len); 648 kfree(eeprom_buff); 649 650 return ret_val; 651 } 652 653 static int igb_set_eeprom(struct net_device *netdev, 654 struct ethtool_eeprom *eeprom, u8 *bytes) 655 { 656 struct igb_adapter *adapter = netdev_priv(netdev); 657 struct e1000_hw *hw = &adapter->hw; 658 u16 *eeprom_buff; 659 void *ptr; 660 int max_len, first_word, last_word, ret_val = 0; 661 u16 i; 662 663 if (eeprom->len == 0) 664 return -EOPNOTSUPP; 665 666 if (hw->mac.type == e1000_i211) 667 return -EOPNOTSUPP; 668 669 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 670 return -EFAULT; 671 672 max_len = hw->nvm.word_size * 2; 673 674 first_word = eeprom->offset >> 1; 675 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 676 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 677 if (!eeprom_buff) 678 return -ENOMEM; 679 680 ptr = (void *)eeprom_buff; 681 682 if (eeprom->offset & 1) { 683 /* need read/modify/write of first changed EEPROM word */ 684 /* only the second byte of the word is being modified */ 685 ret_val = hw->nvm.ops.read(hw, first_word, 1, 686 &eeprom_buff[0]); 687 ptr++; 688 } 689 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 690 /* need read/modify/write of last changed EEPROM word */ 691 /* only the first byte of the word is being modified */ 692 ret_val = hw->nvm.ops.read(hw, last_word, 1, 693 &eeprom_buff[last_word - first_word]); 694 } 695 696 /* Device's eeprom is always little-endian, word addressable */ 697 for (i = 0; i < last_word - first_word + 1; i++) 698 le16_to_cpus(&eeprom_buff[i]); 699 700 memcpy(ptr, bytes, eeprom->len); 701 702 for (i = 0; i < last_word - first_word + 1; i++) 703 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 704 705 ret_val = hw->nvm.ops.write(hw, first_word, 706 last_word - first_word + 1, eeprom_buff); 707 708 /* Update the checksum over the first part of the EEPROM if needed 709 * and flush shadow RAM for 82573 controllers */ 710 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) 711 hw->nvm.ops.update(hw); 712 713 kfree(eeprom_buff); 714 return ret_val; 715 } 716 717 static void igb_get_drvinfo(struct net_device *netdev, 718 struct ethtool_drvinfo *drvinfo) 719 { 720 struct igb_adapter *adapter = netdev_priv(netdev); 721 u16 eeprom_data; 722 723 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 724 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 725 726 /* EEPROM image version # is reported as firmware version # for 727 * 82575 controllers */ 728 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data); 729 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 730 "%d.%d-%d", 731 (eeprom_data & 0xF000) >> 12, 732 (eeprom_data & 0x0FF0) >> 4, 733 eeprom_data & 0x000F); 734 735 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 736 sizeof(drvinfo->bus_info)); 737 drvinfo->n_stats = IGB_STATS_LEN; 738 drvinfo->testinfo_len = IGB_TEST_LEN; 739 drvinfo->regdump_len = igb_get_regs_len(netdev); 740 drvinfo->eedump_len = igb_get_eeprom_len(netdev); 741 } 742 743 static void igb_get_ringparam(struct net_device *netdev, 744 struct ethtool_ringparam *ring) 745 { 746 struct igb_adapter *adapter = netdev_priv(netdev); 747 748 ring->rx_max_pending = IGB_MAX_RXD; 749 ring->tx_max_pending = IGB_MAX_TXD; 750 ring->rx_pending = adapter->rx_ring_count; 751 ring->tx_pending = adapter->tx_ring_count; 752 } 753 754 static int igb_set_ringparam(struct net_device *netdev, 755 struct ethtool_ringparam *ring) 756 { 757 struct igb_adapter *adapter = netdev_priv(netdev); 758 struct igb_ring *temp_ring; 759 int i, err = 0; 760 u16 new_rx_count, new_tx_count; 761 762 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 763 return -EINVAL; 764 765 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 766 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 767 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 768 769 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 770 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 771 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 772 773 if ((new_tx_count == adapter->tx_ring_count) && 774 (new_rx_count == adapter->rx_ring_count)) { 775 /* nothing to do */ 776 return 0; 777 } 778 779 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 780 msleep(1); 781 782 if (!netif_running(adapter->netdev)) { 783 for (i = 0; i < adapter->num_tx_queues; i++) 784 adapter->tx_ring[i]->count = new_tx_count; 785 for (i = 0; i < adapter->num_rx_queues; i++) 786 adapter->rx_ring[i]->count = new_rx_count; 787 adapter->tx_ring_count = new_tx_count; 788 adapter->rx_ring_count = new_rx_count; 789 goto clear_reset; 790 } 791 792 if (adapter->num_tx_queues > adapter->num_rx_queues) 793 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring)); 794 else 795 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring)); 796 797 if (!temp_ring) { 798 err = -ENOMEM; 799 goto clear_reset; 800 } 801 802 igb_down(adapter); 803 804 /* 805 * We can't just free everything and then setup again, 806 * because the ISRs in MSI-X mode get passed pointers 807 * to the tx and rx ring structs. 808 */ 809 if (new_tx_count != adapter->tx_ring_count) { 810 for (i = 0; i < adapter->num_tx_queues; i++) { 811 memcpy(&temp_ring[i], adapter->tx_ring[i], 812 sizeof(struct igb_ring)); 813 814 temp_ring[i].count = new_tx_count; 815 err = igb_setup_tx_resources(&temp_ring[i]); 816 if (err) { 817 while (i) { 818 i--; 819 igb_free_tx_resources(&temp_ring[i]); 820 } 821 goto err_setup; 822 } 823 } 824 825 for (i = 0; i < adapter->num_tx_queues; i++) { 826 igb_free_tx_resources(adapter->tx_ring[i]); 827 828 memcpy(adapter->tx_ring[i], &temp_ring[i], 829 sizeof(struct igb_ring)); 830 } 831 832 adapter->tx_ring_count = new_tx_count; 833 } 834 835 if (new_rx_count != adapter->rx_ring_count) { 836 for (i = 0; i < adapter->num_rx_queues; i++) { 837 memcpy(&temp_ring[i], adapter->rx_ring[i], 838 sizeof(struct igb_ring)); 839 840 temp_ring[i].count = new_rx_count; 841 err = igb_setup_rx_resources(&temp_ring[i]); 842 if (err) { 843 while (i) { 844 i--; 845 igb_free_rx_resources(&temp_ring[i]); 846 } 847 goto err_setup; 848 } 849 850 } 851 852 for (i = 0; i < adapter->num_rx_queues; i++) { 853 igb_free_rx_resources(adapter->rx_ring[i]); 854 855 memcpy(adapter->rx_ring[i], &temp_ring[i], 856 sizeof(struct igb_ring)); 857 } 858 859 adapter->rx_ring_count = new_rx_count; 860 } 861 err_setup: 862 igb_up(adapter); 863 vfree(temp_ring); 864 clear_reset: 865 clear_bit(__IGB_RESETTING, &adapter->state); 866 return err; 867 } 868 869 /* ethtool register test data */ 870 struct igb_reg_test { 871 u16 reg; 872 u16 reg_offset; 873 u16 array_len; 874 u16 test_type; 875 u32 mask; 876 u32 write; 877 }; 878 879 /* In the hardware, registers are laid out either singly, in arrays 880 * spaced 0x100 bytes apart, or in contiguous tables. We assume 881 * most tests take place on arrays or single registers (handled 882 * as a single-element array) and special-case the tables. 883 * Table tests are always pattern tests. 884 * 885 * We also make provision for some required setup steps by specifying 886 * registers to be written without any read-back testing. 887 */ 888 889 #define PATTERN_TEST 1 890 #define SET_READ_TEST 2 891 #define WRITE_NO_TEST 3 892 #define TABLE32_TEST 4 893 #define TABLE64_TEST_LO 5 894 #define TABLE64_TEST_HI 6 895 896 /* i210 reg test */ 897 static struct igb_reg_test reg_test_i210[] = { 898 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 899 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 900 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 901 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 902 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 903 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 904 /* RDH is read-only for i210, only test RDT. */ 905 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 906 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 907 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 908 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 909 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 910 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 911 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 912 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 913 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 914 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 915 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 916 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 917 { E1000_RA, 0, 16, TABLE64_TEST_LO, 918 0xFFFFFFFF, 0xFFFFFFFF }, 919 { E1000_RA, 0, 16, TABLE64_TEST_HI, 920 0x900FFFFF, 0xFFFFFFFF }, 921 { E1000_MTA, 0, 128, TABLE32_TEST, 922 0xFFFFFFFF, 0xFFFFFFFF }, 923 { 0, 0, 0, 0, 0 } 924 }; 925 926 /* i350 reg test */ 927 static struct igb_reg_test reg_test_i350[] = { 928 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 929 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 930 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 931 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 932 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 933 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 934 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 935 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 936 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 937 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 938 /* RDH is read-only for i350, only test RDT. */ 939 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 940 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 941 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 942 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 943 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 944 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 945 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 946 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 947 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 948 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 949 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 950 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 951 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 952 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 953 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 954 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 955 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 956 { E1000_RA, 0, 16, TABLE64_TEST_LO, 957 0xFFFFFFFF, 0xFFFFFFFF }, 958 { E1000_RA, 0, 16, TABLE64_TEST_HI, 959 0xC3FFFFFF, 0xFFFFFFFF }, 960 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 961 0xFFFFFFFF, 0xFFFFFFFF }, 962 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 963 0xC3FFFFFF, 0xFFFFFFFF }, 964 { E1000_MTA, 0, 128, TABLE32_TEST, 965 0xFFFFFFFF, 0xFFFFFFFF }, 966 { 0, 0, 0, 0 } 967 }; 968 969 /* 82580 reg test */ 970 static struct igb_reg_test reg_test_82580[] = { 971 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 972 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 973 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 974 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 975 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 976 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 977 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 978 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 979 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 980 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 981 /* RDH is read-only for 82580, only test RDT. */ 982 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 983 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 984 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 985 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 986 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 987 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 988 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 989 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 990 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 991 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 992 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 993 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 994 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 995 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 996 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 997 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 998 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 999 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1000 0xFFFFFFFF, 0xFFFFFFFF }, 1001 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1002 0x83FFFFFF, 0xFFFFFFFF }, 1003 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1004 0xFFFFFFFF, 0xFFFFFFFF }, 1005 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1006 0x83FFFFFF, 0xFFFFFFFF }, 1007 { E1000_MTA, 0, 128, TABLE32_TEST, 1008 0xFFFFFFFF, 0xFFFFFFFF }, 1009 { 0, 0, 0, 0 } 1010 }; 1011 1012 /* 82576 reg test */ 1013 static struct igb_reg_test reg_test_82576[] = { 1014 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1015 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1016 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1017 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1018 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1019 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1020 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1021 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1022 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1023 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1024 /* Enable all RX queues before testing. */ 1025 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1026 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1027 /* RDH is read-only for 82576, only test RDT. */ 1028 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1029 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1030 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1031 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1032 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1033 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1034 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1035 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1036 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1037 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1038 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1039 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1040 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1041 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1042 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1043 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1044 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1045 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1046 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1047 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1048 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1049 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1050 { 0, 0, 0, 0 } 1051 }; 1052 1053 /* 82575 register test */ 1054 static struct igb_reg_test reg_test_82575[] = { 1055 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1056 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1057 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1058 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1059 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1060 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1061 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1062 /* Enable all four RX queues before testing. */ 1063 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1064 /* RDH is read-only for 82575, only test RDT. */ 1065 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1066 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1067 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1068 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1069 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1070 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1071 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1072 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1073 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1074 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1075 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1076 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1077 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1078 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1079 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1080 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1081 { 0, 0, 0, 0 } 1082 }; 1083 1084 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1085 int reg, u32 mask, u32 write) 1086 { 1087 struct e1000_hw *hw = &adapter->hw; 1088 u32 pat, val; 1089 static const u32 _test[] = 1090 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1091 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1092 wr32(reg, (_test[pat] & write)); 1093 val = rd32(reg) & mask; 1094 if (val != (_test[pat] & write & mask)) { 1095 dev_err(&adapter->pdev->dev, "pattern test reg %04X " 1096 "failed: got 0x%08X expected 0x%08X\n", 1097 reg, val, (_test[pat] & write & mask)); 1098 *data = reg; 1099 return 1; 1100 } 1101 } 1102 1103 return 0; 1104 } 1105 1106 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1107 int reg, u32 mask, u32 write) 1108 { 1109 struct e1000_hw *hw = &adapter->hw; 1110 u32 val; 1111 wr32(reg, write & mask); 1112 val = rd32(reg); 1113 if ((write & mask) != (val & mask)) { 1114 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:" 1115 " got 0x%08X expected 0x%08X\n", reg, 1116 (val & mask), (write & mask)); 1117 *data = reg; 1118 return 1; 1119 } 1120 1121 return 0; 1122 } 1123 1124 #define REG_PATTERN_TEST(reg, mask, write) \ 1125 do { \ 1126 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1127 return 1; \ 1128 } while (0) 1129 1130 #define REG_SET_AND_CHECK(reg, mask, write) \ 1131 do { \ 1132 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1133 return 1; \ 1134 } while (0) 1135 1136 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1137 { 1138 struct e1000_hw *hw = &adapter->hw; 1139 struct igb_reg_test *test; 1140 u32 value, before, after; 1141 u32 i, toggle; 1142 1143 switch (adapter->hw.mac.type) { 1144 case e1000_i350: 1145 test = reg_test_i350; 1146 toggle = 0x7FEFF3FF; 1147 break; 1148 case e1000_i210: 1149 case e1000_i211: 1150 test = reg_test_i210; 1151 toggle = 0x7FEFF3FF; 1152 break; 1153 case e1000_82580: 1154 test = reg_test_82580; 1155 toggle = 0x7FEFF3FF; 1156 break; 1157 case e1000_82576: 1158 test = reg_test_82576; 1159 toggle = 0x7FFFF3FF; 1160 break; 1161 default: 1162 test = reg_test_82575; 1163 toggle = 0x7FFFF3FF; 1164 break; 1165 } 1166 1167 /* Because the status register is such a special case, 1168 * we handle it separately from the rest of the register 1169 * tests. Some bits are read-only, some toggle, and some 1170 * are writable on newer MACs. 1171 */ 1172 before = rd32(E1000_STATUS); 1173 value = (rd32(E1000_STATUS) & toggle); 1174 wr32(E1000_STATUS, toggle); 1175 after = rd32(E1000_STATUS) & toggle; 1176 if (value != after) { 1177 dev_err(&adapter->pdev->dev, "failed STATUS register test " 1178 "got: 0x%08X expected: 0x%08X\n", after, value); 1179 *data = 1; 1180 return 1; 1181 } 1182 /* restore previous status */ 1183 wr32(E1000_STATUS, before); 1184 1185 /* Perform the remainder of the register test, looping through 1186 * the test table until we either fail or reach the null entry. 1187 */ 1188 while (test->reg) { 1189 for (i = 0; i < test->array_len; i++) { 1190 switch (test->test_type) { 1191 case PATTERN_TEST: 1192 REG_PATTERN_TEST(test->reg + 1193 (i * test->reg_offset), 1194 test->mask, 1195 test->write); 1196 break; 1197 case SET_READ_TEST: 1198 REG_SET_AND_CHECK(test->reg + 1199 (i * test->reg_offset), 1200 test->mask, 1201 test->write); 1202 break; 1203 case WRITE_NO_TEST: 1204 writel(test->write, 1205 (adapter->hw.hw_addr + test->reg) 1206 + (i * test->reg_offset)); 1207 break; 1208 case TABLE32_TEST: 1209 REG_PATTERN_TEST(test->reg + (i * 4), 1210 test->mask, 1211 test->write); 1212 break; 1213 case TABLE64_TEST_LO: 1214 REG_PATTERN_TEST(test->reg + (i * 8), 1215 test->mask, 1216 test->write); 1217 break; 1218 case TABLE64_TEST_HI: 1219 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1220 test->mask, 1221 test->write); 1222 break; 1223 } 1224 } 1225 test++; 1226 } 1227 1228 *data = 0; 1229 return 0; 1230 } 1231 1232 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1233 { 1234 *data = 0; 1235 1236 /* Validate eeprom on all parts but i211 */ 1237 if (adapter->hw.mac.type != e1000_i211) { 1238 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1239 *data = 2; 1240 } 1241 1242 return *data; 1243 } 1244 1245 static irqreturn_t igb_test_intr(int irq, void *data) 1246 { 1247 struct igb_adapter *adapter = (struct igb_adapter *) data; 1248 struct e1000_hw *hw = &adapter->hw; 1249 1250 adapter->test_icr |= rd32(E1000_ICR); 1251 1252 return IRQ_HANDLED; 1253 } 1254 1255 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1256 { 1257 struct e1000_hw *hw = &adapter->hw; 1258 struct net_device *netdev = adapter->netdev; 1259 u32 mask, ics_mask, i = 0, shared_int = true; 1260 u32 irq = adapter->pdev->irq; 1261 1262 *data = 0; 1263 1264 /* Hook up test interrupt handler just for this test */ 1265 if (adapter->msix_entries) { 1266 if (request_irq(adapter->msix_entries[0].vector, 1267 igb_test_intr, 0, netdev->name, adapter)) { 1268 *data = 1; 1269 return -1; 1270 } 1271 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1272 shared_int = false; 1273 if (request_irq(irq, 1274 igb_test_intr, 0, netdev->name, adapter)) { 1275 *data = 1; 1276 return -1; 1277 } 1278 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1279 netdev->name, adapter)) { 1280 shared_int = false; 1281 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1282 netdev->name, adapter)) { 1283 *data = 1; 1284 return -1; 1285 } 1286 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1287 (shared_int ? "shared" : "unshared")); 1288 1289 /* Disable all the interrupts */ 1290 wr32(E1000_IMC, ~0); 1291 wrfl(); 1292 msleep(10); 1293 1294 /* Define all writable bits for ICS */ 1295 switch (hw->mac.type) { 1296 case e1000_82575: 1297 ics_mask = 0x37F47EDD; 1298 break; 1299 case e1000_82576: 1300 ics_mask = 0x77D4FBFD; 1301 break; 1302 case e1000_82580: 1303 ics_mask = 0x77DCFED5; 1304 break; 1305 case e1000_i350: 1306 case e1000_i210: 1307 case e1000_i211: 1308 ics_mask = 0x77DCFED5; 1309 break; 1310 default: 1311 ics_mask = 0x7FFFFFFF; 1312 break; 1313 } 1314 1315 /* Test each interrupt */ 1316 for (; i < 31; i++) { 1317 /* Interrupt to test */ 1318 mask = 1 << i; 1319 1320 if (!(mask & ics_mask)) 1321 continue; 1322 1323 if (!shared_int) { 1324 /* Disable the interrupt to be reported in 1325 * the cause register and then force the same 1326 * interrupt and see if one gets posted. If 1327 * an interrupt was posted to the bus, the 1328 * test failed. 1329 */ 1330 adapter->test_icr = 0; 1331 1332 /* Flush any pending interrupts */ 1333 wr32(E1000_ICR, ~0); 1334 1335 wr32(E1000_IMC, mask); 1336 wr32(E1000_ICS, mask); 1337 wrfl(); 1338 msleep(10); 1339 1340 if (adapter->test_icr & mask) { 1341 *data = 3; 1342 break; 1343 } 1344 } 1345 1346 /* Enable the interrupt to be reported in 1347 * the cause register and then force the same 1348 * interrupt and see if one gets posted. If 1349 * an interrupt was not posted to the bus, the 1350 * test failed. 1351 */ 1352 adapter->test_icr = 0; 1353 1354 /* Flush any pending interrupts */ 1355 wr32(E1000_ICR, ~0); 1356 1357 wr32(E1000_IMS, mask); 1358 wr32(E1000_ICS, mask); 1359 wrfl(); 1360 msleep(10); 1361 1362 if (!(adapter->test_icr & mask)) { 1363 *data = 4; 1364 break; 1365 } 1366 1367 if (!shared_int) { 1368 /* Disable the other interrupts to be reported in 1369 * the cause register and then force the other 1370 * interrupts and see if any get posted. If 1371 * an interrupt was posted to the bus, the 1372 * test failed. 1373 */ 1374 adapter->test_icr = 0; 1375 1376 /* Flush any pending interrupts */ 1377 wr32(E1000_ICR, ~0); 1378 1379 wr32(E1000_IMC, ~mask); 1380 wr32(E1000_ICS, ~mask); 1381 wrfl(); 1382 msleep(10); 1383 1384 if (adapter->test_icr & mask) { 1385 *data = 5; 1386 break; 1387 } 1388 } 1389 } 1390 1391 /* Disable all the interrupts */ 1392 wr32(E1000_IMC, ~0); 1393 wrfl(); 1394 msleep(10); 1395 1396 /* Unhook test interrupt handler */ 1397 if (adapter->msix_entries) 1398 free_irq(adapter->msix_entries[0].vector, adapter); 1399 else 1400 free_irq(irq, adapter); 1401 1402 return *data; 1403 } 1404 1405 static void igb_free_desc_rings(struct igb_adapter *adapter) 1406 { 1407 igb_free_tx_resources(&adapter->test_tx_ring); 1408 igb_free_rx_resources(&adapter->test_rx_ring); 1409 } 1410 1411 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1412 { 1413 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1414 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1415 struct e1000_hw *hw = &adapter->hw; 1416 int ret_val; 1417 1418 /* Setup Tx descriptor ring and Tx buffers */ 1419 tx_ring->count = IGB_DEFAULT_TXD; 1420 tx_ring->dev = &adapter->pdev->dev; 1421 tx_ring->netdev = adapter->netdev; 1422 tx_ring->reg_idx = adapter->vfs_allocated_count; 1423 1424 if (igb_setup_tx_resources(tx_ring)) { 1425 ret_val = 1; 1426 goto err_nomem; 1427 } 1428 1429 igb_setup_tctl(adapter); 1430 igb_configure_tx_ring(adapter, tx_ring); 1431 1432 /* Setup Rx descriptor ring and Rx buffers */ 1433 rx_ring->count = IGB_DEFAULT_RXD; 1434 rx_ring->dev = &adapter->pdev->dev; 1435 rx_ring->netdev = adapter->netdev; 1436 rx_ring->reg_idx = adapter->vfs_allocated_count; 1437 1438 if (igb_setup_rx_resources(rx_ring)) { 1439 ret_val = 3; 1440 goto err_nomem; 1441 } 1442 1443 /* set the default queue to queue 0 of PF */ 1444 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1445 1446 /* enable receive ring */ 1447 igb_setup_rctl(adapter); 1448 igb_configure_rx_ring(adapter, rx_ring); 1449 1450 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1451 1452 return 0; 1453 1454 err_nomem: 1455 igb_free_desc_rings(adapter); 1456 return ret_val; 1457 } 1458 1459 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1460 { 1461 struct e1000_hw *hw = &adapter->hw; 1462 1463 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1464 igb_write_phy_reg(hw, 29, 0x001F); 1465 igb_write_phy_reg(hw, 30, 0x8FFC); 1466 igb_write_phy_reg(hw, 29, 0x001A); 1467 igb_write_phy_reg(hw, 30, 0x8FF0); 1468 } 1469 1470 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1471 { 1472 struct e1000_hw *hw = &adapter->hw; 1473 u32 ctrl_reg = 0; 1474 u16 phy_reg = 0; 1475 1476 hw->mac.autoneg = false; 1477 1478 switch (hw->phy.type) { 1479 case e1000_phy_m88: 1480 /* Auto-MDI/MDIX Off */ 1481 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1482 /* reset to update Auto-MDI/MDIX */ 1483 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1484 /* autoneg off */ 1485 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1486 break; 1487 case e1000_phy_82580: 1488 /* enable MII loopback */ 1489 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1490 break; 1491 case e1000_phy_i210: 1492 /* set loopback speed in PHY */ 1493 igb_read_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2), 1494 &phy_reg); 1495 phy_reg |= GS40G_MAC_SPEED_1G; 1496 igb_write_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2), 1497 phy_reg); 1498 ctrl_reg = rd32(E1000_CTRL_EXT); 1499 default: 1500 break; 1501 } 1502 1503 /* force 1000, set loopback */ 1504 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1505 1506 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1507 ctrl_reg = rd32(E1000_CTRL); 1508 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1509 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1510 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1511 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1512 E1000_CTRL_FD | /* Force Duplex to FULL */ 1513 E1000_CTRL_SLU); /* Set link up enable bit */ 1514 1515 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210)) 1516 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1517 1518 wr32(E1000_CTRL, ctrl_reg); 1519 1520 /* Disable the receiver on the PHY so when a cable is plugged in, the 1521 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1522 */ 1523 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210)) 1524 igb_phy_disable_receiver(adapter); 1525 1526 udelay(500); 1527 1528 return 0; 1529 } 1530 1531 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1532 { 1533 return igb_integrated_phy_loopback(adapter); 1534 } 1535 1536 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u32 reg; 1540 1541 reg = rd32(E1000_CTRL_EXT); 1542 1543 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1544 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1545 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1546 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1547 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1548 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1549 1550 /* Enable DH89xxCC MPHY for near end loopback */ 1551 reg = rd32(E1000_MPHY_ADDR_CTL); 1552 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1553 E1000_MPHY_PCS_CLK_REG_OFFSET; 1554 wr32(E1000_MPHY_ADDR_CTL, reg); 1555 1556 reg = rd32(E1000_MPHY_DATA); 1557 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1558 wr32(E1000_MPHY_DATA, reg); 1559 } 1560 1561 reg = rd32(E1000_RCTL); 1562 reg |= E1000_RCTL_LBM_TCVR; 1563 wr32(E1000_RCTL, reg); 1564 1565 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1566 1567 reg = rd32(E1000_CTRL); 1568 reg &= ~(E1000_CTRL_RFCE | 1569 E1000_CTRL_TFCE | 1570 E1000_CTRL_LRST); 1571 reg |= E1000_CTRL_SLU | 1572 E1000_CTRL_FD; 1573 wr32(E1000_CTRL, reg); 1574 1575 /* Unset switch control to serdes energy detect */ 1576 reg = rd32(E1000_CONNSW); 1577 reg &= ~E1000_CONNSW_ENRGSRC; 1578 wr32(E1000_CONNSW, reg); 1579 1580 /* Set PCS register for forced speed */ 1581 reg = rd32(E1000_PCS_LCTL); 1582 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1583 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1584 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1585 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1586 E1000_PCS_LCTL_FSD | /* Force Speed */ 1587 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1588 wr32(E1000_PCS_LCTL, reg); 1589 1590 return 0; 1591 } 1592 1593 return igb_set_phy_loopback(adapter); 1594 } 1595 1596 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1597 { 1598 struct e1000_hw *hw = &adapter->hw; 1599 u32 rctl; 1600 u16 phy_reg; 1601 1602 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1603 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1604 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1605 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1606 u32 reg; 1607 1608 /* Disable near end loopback on DH89xxCC */ 1609 reg = rd32(E1000_MPHY_ADDR_CTL); 1610 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1611 E1000_MPHY_PCS_CLK_REG_OFFSET; 1612 wr32(E1000_MPHY_ADDR_CTL, reg); 1613 1614 reg = rd32(E1000_MPHY_DATA); 1615 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1616 wr32(E1000_MPHY_DATA, reg); 1617 } 1618 1619 rctl = rd32(E1000_RCTL); 1620 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1621 wr32(E1000_RCTL, rctl); 1622 1623 hw->mac.autoneg = true; 1624 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1625 if (phy_reg & MII_CR_LOOPBACK) { 1626 phy_reg &= ~MII_CR_LOOPBACK; 1627 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1628 igb_phy_sw_reset(hw); 1629 } 1630 } 1631 1632 static void igb_create_lbtest_frame(struct sk_buff *skb, 1633 unsigned int frame_size) 1634 { 1635 memset(skb->data, 0xFF, frame_size); 1636 frame_size /= 2; 1637 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1638 memset(&skb->data[frame_size + 10], 0xBE, 1); 1639 memset(&skb->data[frame_size + 12], 0xAF, 1); 1640 } 1641 1642 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) 1643 { 1644 frame_size /= 2; 1645 if (*(skb->data + 3) == 0xFF) { 1646 if ((*(skb->data + frame_size + 10) == 0xBE) && 1647 (*(skb->data + frame_size + 12) == 0xAF)) { 1648 return 0; 1649 } 1650 } 1651 return 13; 1652 } 1653 1654 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1655 struct igb_ring *tx_ring, 1656 unsigned int size) 1657 { 1658 union e1000_adv_rx_desc *rx_desc; 1659 struct igb_rx_buffer *rx_buffer_info; 1660 struct igb_tx_buffer *tx_buffer_info; 1661 struct netdev_queue *txq; 1662 u16 rx_ntc, tx_ntc, count = 0; 1663 unsigned int total_bytes = 0, total_packets = 0; 1664 1665 /* initialize next to clean and descriptor values */ 1666 rx_ntc = rx_ring->next_to_clean; 1667 tx_ntc = tx_ring->next_to_clean; 1668 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1669 1670 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1671 /* check rx buffer */ 1672 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1673 1674 /* unmap rx buffer, will be remapped by alloc_rx_buffers */ 1675 dma_unmap_single(rx_ring->dev, 1676 rx_buffer_info->dma, 1677 IGB_RX_HDR_LEN, 1678 DMA_FROM_DEVICE); 1679 rx_buffer_info->dma = 0; 1680 1681 /* verify contents of skb */ 1682 if (!igb_check_lbtest_frame(rx_buffer_info->skb, size)) 1683 count++; 1684 1685 /* unmap buffer on tx side */ 1686 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1687 total_bytes += tx_buffer_info->bytecount; 1688 total_packets += tx_buffer_info->gso_segs; 1689 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1690 1691 /* increment rx/tx next to clean counters */ 1692 rx_ntc++; 1693 if (rx_ntc == rx_ring->count) 1694 rx_ntc = 0; 1695 tx_ntc++; 1696 if (tx_ntc == tx_ring->count) 1697 tx_ntc = 0; 1698 1699 /* fetch next descriptor */ 1700 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1701 } 1702 1703 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1704 netdev_tx_completed_queue(txq, total_packets, total_bytes); 1705 1706 /* re-map buffers to ring, store next to clean values */ 1707 igb_alloc_rx_buffers(rx_ring, count); 1708 rx_ring->next_to_clean = rx_ntc; 1709 tx_ring->next_to_clean = tx_ntc; 1710 1711 return count; 1712 } 1713 1714 static int igb_run_loopback_test(struct igb_adapter *adapter) 1715 { 1716 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1717 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1718 u16 i, j, lc, good_cnt; 1719 int ret_val = 0; 1720 unsigned int size = IGB_RX_HDR_LEN; 1721 netdev_tx_t tx_ret_val; 1722 struct sk_buff *skb; 1723 1724 /* allocate test skb */ 1725 skb = alloc_skb(size, GFP_KERNEL); 1726 if (!skb) 1727 return 11; 1728 1729 /* place data into test skb */ 1730 igb_create_lbtest_frame(skb, size); 1731 skb_put(skb, size); 1732 1733 /* 1734 * Calculate the loop count based on the largest descriptor ring 1735 * The idea is to wrap the largest ring a number of times using 64 1736 * send/receive pairs during each loop 1737 */ 1738 1739 if (rx_ring->count <= tx_ring->count) 1740 lc = ((tx_ring->count / 64) * 2) + 1; 1741 else 1742 lc = ((rx_ring->count / 64) * 2) + 1; 1743 1744 for (j = 0; j <= lc; j++) { /* loop count loop */ 1745 /* reset count of good packets */ 1746 good_cnt = 0; 1747 1748 /* place 64 packets on the transmit queue*/ 1749 for (i = 0; i < 64; i++) { 1750 skb_get(skb); 1751 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1752 if (tx_ret_val == NETDEV_TX_OK) 1753 good_cnt++; 1754 } 1755 1756 if (good_cnt != 64) { 1757 ret_val = 12; 1758 break; 1759 } 1760 1761 /* allow 200 milliseconds for packets to go from tx to rx */ 1762 msleep(200); 1763 1764 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1765 if (good_cnt != 64) { 1766 ret_val = 13; 1767 break; 1768 } 1769 } /* end loop count loop */ 1770 1771 /* free the original skb */ 1772 kfree_skb(skb); 1773 1774 return ret_val; 1775 } 1776 1777 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1778 { 1779 /* PHY loopback cannot be performed if SoL/IDER 1780 * sessions are active */ 1781 if (igb_check_reset_block(&adapter->hw)) { 1782 dev_err(&adapter->pdev->dev, 1783 "Cannot do PHY loopback test " 1784 "when SoL/IDER is active.\n"); 1785 *data = 0; 1786 goto out; 1787 } 1788 if ((adapter->hw.mac.type == e1000_i210) 1789 || (adapter->hw.mac.type == e1000_i210)) { 1790 dev_err(&adapter->pdev->dev, 1791 "Loopback test not supported " 1792 "on this part at this time.\n"); 1793 *data = 0; 1794 goto out; 1795 } 1796 *data = igb_setup_desc_rings(adapter); 1797 if (*data) 1798 goto out; 1799 *data = igb_setup_loopback_test(adapter); 1800 if (*data) 1801 goto err_loopback; 1802 *data = igb_run_loopback_test(adapter); 1803 igb_loopback_cleanup(adapter); 1804 1805 err_loopback: 1806 igb_free_desc_rings(adapter); 1807 out: 1808 return *data; 1809 } 1810 1811 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1812 { 1813 struct e1000_hw *hw = &adapter->hw; 1814 *data = 0; 1815 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1816 int i = 0; 1817 hw->mac.serdes_has_link = false; 1818 1819 /* On some blade server designs, link establishment 1820 * could take as long as 2-3 minutes */ 1821 do { 1822 hw->mac.ops.check_for_link(&adapter->hw); 1823 if (hw->mac.serdes_has_link) 1824 return *data; 1825 msleep(20); 1826 } while (i++ < 3750); 1827 1828 *data = 1; 1829 } else { 1830 hw->mac.ops.check_for_link(&adapter->hw); 1831 if (hw->mac.autoneg) 1832 msleep(4000); 1833 1834 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1835 *data = 1; 1836 } 1837 return *data; 1838 } 1839 1840 static void igb_diag_test(struct net_device *netdev, 1841 struct ethtool_test *eth_test, u64 *data) 1842 { 1843 struct igb_adapter *adapter = netdev_priv(netdev); 1844 u16 autoneg_advertised; 1845 u8 forced_speed_duplex, autoneg; 1846 bool if_running = netif_running(netdev); 1847 1848 set_bit(__IGB_TESTING, &adapter->state); 1849 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1850 /* Offline tests */ 1851 1852 /* save speed, duplex, autoneg settings */ 1853 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 1854 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 1855 autoneg = adapter->hw.mac.autoneg; 1856 1857 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 1858 1859 /* power up link for link test */ 1860 igb_power_up_link(adapter); 1861 1862 /* Link test performed before hardware reset so autoneg doesn't 1863 * interfere with test result */ 1864 if (igb_link_test(adapter, &data[4])) 1865 eth_test->flags |= ETH_TEST_FL_FAILED; 1866 1867 if (if_running) 1868 /* indicate we're in test mode */ 1869 dev_close(netdev); 1870 else 1871 igb_reset(adapter); 1872 1873 if (igb_reg_test(adapter, &data[0])) 1874 eth_test->flags |= ETH_TEST_FL_FAILED; 1875 1876 igb_reset(adapter); 1877 if (igb_eeprom_test(adapter, &data[1])) 1878 eth_test->flags |= ETH_TEST_FL_FAILED; 1879 1880 igb_reset(adapter); 1881 if (igb_intr_test(adapter, &data[2])) 1882 eth_test->flags |= ETH_TEST_FL_FAILED; 1883 1884 igb_reset(adapter); 1885 /* power up link for loopback test */ 1886 igb_power_up_link(adapter); 1887 if (igb_loopback_test(adapter, &data[3])) 1888 eth_test->flags |= ETH_TEST_FL_FAILED; 1889 1890 /* restore speed, duplex, autoneg settings */ 1891 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 1892 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 1893 adapter->hw.mac.autoneg = autoneg; 1894 1895 /* force this routine to wait until autoneg complete/timeout */ 1896 adapter->hw.phy.autoneg_wait_to_complete = true; 1897 igb_reset(adapter); 1898 adapter->hw.phy.autoneg_wait_to_complete = false; 1899 1900 clear_bit(__IGB_TESTING, &adapter->state); 1901 if (if_running) 1902 dev_open(netdev); 1903 } else { 1904 dev_info(&adapter->pdev->dev, "online testing starting\n"); 1905 1906 /* PHY is powered down when interface is down */ 1907 if (if_running && igb_link_test(adapter, &data[4])) 1908 eth_test->flags |= ETH_TEST_FL_FAILED; 1909 else 1910 data[4] = 0; 1911 1912 /* Online tests aren't run; pass by default */ 1913 data[0] = 0; 1914 data[1] = 0; 1915 data[2] = 0; 1916 data[3] = 0; 1917 1918 clear_bit(__IGB_TESTING, &adapter->state); 1919 } 1920 msleep_interruptible(4 * 1000); 1921 } 1922 1923 static int igb_wol_exclusion(struct igb_adapter *adapter, 1924 struct ethtool_wolinfo *wol) 1925 { 1926 struct e1000_hw *hw = &adapter->hw; 1927 int retval = 1; /* fail by default */ 1928 1929 switch (hw->device_id) { 1930 case E1000_DEV_ID_82575GB_QUAD_COPPER: 1931 /* WoL not supported */ 1932 wol->supported = 0; 1933 break; 1934 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1935 case E1000_DEV_ID_82576_FIBER: 1936 case E1000_DEV_ID_82576_SERDES: 1937 /* Wake events not supported on port B */ 1938 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { 1939 wol->supported = 0; 1940 break; 1941 } 1942 /* return success for non excluded adapter ports */ 1943 retval = 0; 1944 break; 1945 case E1000_DEV_ID_82576_QUAD_COPPER: 1946 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 1947 /* quad port adapters only support WoL on port A */ 1948 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { 1949 wol->supported = 0; 1950 break; 1951 } 1952 /* return success for non excluded adapter ports */ 1953 retval = 0; 1954 break; 1955 default: 1956 /* dual port cards only support WoL on port A from now on 1957 * unless it was enabled in the eeprom for port B 1958 * so exclude FUNC_1 ports from having WoL enabled */ 1959 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) && 1960 !adapter->eeprom_wol) { 1961 wol->supported = 0; 1962 break; 1963 } 1964 1965 retval = 0; 1966 } 1967 1968 return retval; 1969 } 1970 1971 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1972 { 1973 struct igb_adapter *adapter = netdev_priv(netdev); 1974 1975 wol->supported = WAKE_UCAST | WAKE_MCAST | 1976 WAKE_BCAST | WAKE_MAGIC | 1977 WAKE_PHY; 1978 wol->wolopts = 0; 1979 1980 /* this function will set ->supported = 0 and return 1 if wol is not 1981 * supported by this hardware */ 1982 if (igb_wol_exclusion(adapter, wol) || 1983 !device_can_wakeup(&adapter->pdev->dev)) 1984 return; 1985 1986 /* apply any specific unsupported masks here */ 1987 switch (adapter->hw.device_id) { 1988 default: 1989 break; 1990 } 1991 1992 if (adapter->wol & E1000_WUFC_EX) 1993 wol->wolopts |= WAKE_UCAST; 1994 if (adapter->wol & E1000_WUFC_MC) 1995 wol->wolopts |= WAKE_MCAST; 1996 if (adapter->wol & E1000_WUFC_BC) 1997 wol->wolopts |= WAKE_BCAST; 1998 if (adapter->wol & E1000_WUFC_MAG) 1999 wol->wolopts |= WAKE_MAGIC; 2000 if (adapter->wol & E1000_WUFC_LNKC) 2001 wol->wolopts |= WAKE_PHY; 2002 } 2003 2004 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2005 { 2006 struct igb_adapter *adapter = netdev_priv(netdev); 2007 2008 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2009 return -EOPNOTSUPP; 2010 2011 if (igb_wol_exclusion(adapter, wol) || 2012 !device_can_wakeup(&adapter->pdev->dev)) 2013 return wol->wolopts ? -EOPNOTSUPP : 0; 2014 2015 /* these settings will always override what we currently have */ 2016 adapter->wol = 0; 2017 2018 if (wol->wolopts & WAKE_UCAST) 2019 adapter->wol |= E1000_WUFC_EX; 2020 if (wol->wolopts & WAKE_MCAST) 2021 adapter->wol |= E1000_WUFC_MC; 2022 if (wol->wolopts & WAKE_BCAST) 2023 adapter->wol |= E1000_WUFC_BC; 2024 if (wol->wolopts & WAKE_MAGIC) 2025 adapter->wol |= E1000_WUFC_MAG; 2026 if (wol->wolopts & WAKE_PHY) 2027 adapter->wol |= E1000_WUFC_LNKC; 2028 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2029 2030 return 0; 2031 } 2032 2033 /* bit defines for adapter->led_status */ 2034 #define IGB_LED_ON 0 2035 2036 static int igb_set_phys_id(struct net_device *netdev, 2037 enum ethtool_phys_id_state state) 2038 { 2039 struct igb_adapter *adapter = netdev_priv(netdev); 2040 struct e1000_hw *hw = &adapter->hw; 2041 2042 switch (state) { 2043 case ETHTOOL_ID_ACTIVE: 2044 igb_blink_led(hw); 2045 return 2; 2046 case ETHTOOL_ID_ON: 2047 igb_blink_led(hw); 2048 break; 2049 case ETHTOOL_ID_OFF: 2050 igb_led_off(hw); 2051 break; 2052 case ETHTOOL_ID_INACTIVE: 2053 igb_led_off(hw); 2054 clear_bit(IGB_LED_ON, &adapter->led_status); 2055 igb_cleanup_led(hw); 2056 break; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static int igb_set_coalesce(struct net_device *netdev, 2063 struct ethtool_coalesce *ec) 2064 { 2065 struct igb_adapter *adapter = netdev_priv(netdev); 2066 int i; 2067 2068 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2069 ((ec->rx_coalesce_usecs > 3) && 2070 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2071 (ec->rx_coalesce_usecs == 2)) 2072 return -EINVAL; 2073 2074 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2075 ((ec->tx_coalesce_usecs > 3) && 2076 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2077 (ec->tx_coalesce_usecs == 2)) 2078 return -EINVAL; 2079 2080 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2081 return -EINVAL; 2082 2083 /* If ITR is disabled, disable DMAC */ 2084 if (ec->rx_coalesce_usecs == 0) { 2085 if (adapter->flags & IGB_FLAG_DMAC) 2086 adapter->flags &= ~IGB_FLAG_DMAC; 2087 } 2088 2089 /* convert to rate of irq's per second */ 2090 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2091 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2092 else 2093 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2094 2095 /* convert to rate of irq's per second */ 2096 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2097 adapter->tx_itr_setting = adapter->rx_itr_setting; 2098 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2099 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2100 else 2101 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2102 2103 for (i = 0; i < adapter->num_q_vectors; i++) { 2104 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2105 q_vector->tx.work_limit = adapter->tx_work_limit; 2106 if (q_vector->rx.ring) 2107 q_vector->itr_val = adapter->rx_itr_setting; 2108 else 2109 q_vector->itr_val = adapter->tx_itr_setting; 2110 if (q_vector->itr_val && q_vector->itr_val <= 3) 2111 q_vector->itr_val = IGB_START_ITR; 2112 q_vector->set_itr = 1; 2113 } 2114 2115 return 0; 2116 } 2117 2118 static int igb_get_coalesce(struct net_device *netdev, 2119 struct ethtool_coalesce *ec) 2120 { 2121 struct igb_adapter *adapter = netdev_priv(netdev); 2122 2123 if (adapter->rx_itr_setting <= 3) 2124 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2125 else 2126 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2127 2128 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2129 if (adapter->tx_itr_setting <= 3) 2130 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2131 else 2132 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int igb_nway_reset(struct net_device *netdev) 2139 { 2140 struct igb_adapter *adapter = netdev_priv(netdev); 2141 if (netif_running(netdev)) 2142 igb_reinit_locked(adapter); 2143 return 0; 2144 } 2145 2146 static int igb_get_sset_count(struct net_device *netdev, int sset) 2147 { 2148 switch (sset) { 2149 case ETH_SS_STATS: 2150 return IGB_STATS_LEN; 2151 case ETH_SS_TEST: 2152 return IGB_TEST_LEN; 2153 default: 2154 return -ENOTSUPP; 2155 } 2156 } 2157 2158 static void igb_get_ethtool_stats(struct net_device *netdev, 2159 struct ethtool_stats *stats, u64 *data) 2160 { 2161 struct igb_adapter *adapter = netdev_priv(netdev); 2162 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2163 unsigned int start; 2164 struct igb_ring *ring; 2165 int i, j; 2166 char *p; 2167 2168 spin_lock(&adapter->stats64_lock); 2169 igb_update_stats(adapter, net_stats); 2170 2171 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2172 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2173 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2174 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2175 } 2176 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2177 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2178 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2179 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2180 } 2181 for (j = 0; j < adapter->num_tx_queues; j++) { 2182 u64 restart2; 2183 2184 ring = adapter->tx_ring[j]; 2185 do { 2186 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 2187 data[i] = ring->tx_stats.packets; 2188 data[i+1] = ring->tx_stats.bytes; 2189 data[i+2] = ring->tx_stats.restart_queue; 2190 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 2191 do { 2192 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); 2193 restart2 = ring->tx_stats.restart_queue2; 2194 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); 2195 data[i+2] += restart2; 2196 2197 i += IGB_TX_QUEUE_STATS_LEN; 2198 } 2199 for (j = 0; j < adapter->num_rx_queues; j++) { 2200 ring = adapter->rx_ring[j]; 2201 do { 2202 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 2203 data[i] = ring->rx_stats.packets; 2204 data[i+1] = ring->rx_stats.bytes; 2205 data[i+2] = ring->rx_stats.drops; 2206 data[i+3] = ring->rx_stats.csum_err; 2207 data[i+4] = ring->rx_stats.alloc_failed; 2208 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 2209 i += IGB_RX_QUEUE_STATS_LEN; 2210 } 2211 spin_unlock(&adapter->stats64_lock); 2212 } 2213 2214 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2215 { 2216 struct igb_adapter *adapter = netdev_priv(netdev); 2217 u8 *p = data; 2218 int i; 2219 2220 switch (stringset) { 2221 case ETH_SS_TEST: 2222 memcpy(data, *igb_gstrings_test, 2223 IGB_TEST_LEN*ETH_GSTRING_LEN); 2224 break; 2225 case ETH_SS_STATS: 2226 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2227 memcpy(p, igb_gstrings_stats[i].stat_string, 2228 ETH_GSTRING_LEN); 2229 p += ETH_GSTRING_LEN; 2230 } 2231 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2232 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2233 ETH_GSTRING_LEN); 2234 p += ETH_GSTRING_LEN; 2235 } 2236 for (i = 0; i < adapter->num_tx_queues; i++) { 2237 sprintf(p, "tx_queue_%u_packets", i); 2238 p += ETH_GSTRING_LEN; 2239 sprintf(p, "tx_queue_%u_bytes", i); 2240 p += ETH_GSTRING_LEN; 2241 sprintf(p, "tx_queue_%u_restart", i); 2242 p += ETH_GSTRING_LEN; 2243 } 2244 for (i = 0; i < adapter->num_rx_queues; i++) { 2245 sprintf(p, "rx_queue_%u_packets", i); 2246 p += ETH_GSTRING_LEN; 2247 sprintf(p, "rx_queue_%u_bytes", i); 2248 p += ETH_GSTRING_LEN; 2249 sprintf(p, "rx_queue_%u_drops", i); 2250 p += ETH_GSTRING_LEN; 2251 sprintf(p, "rx_queue_%u_csum_err", i); 2252 p += ETH_GSTRING_LEN; 2253 sprintf(p, "rx_queue_%u_alloc_failed", i); 2254 p += ETH_GSTRING_LEN; 2255 } 2256 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2257 break; 2258 } 2259 } 2260 2261 static int igb_ethtool_begin(struct net_device *netdev) 2262 { 2263 struct igb_adapter *adapter = netdev_priv(netdev); 2264 pm_runtime_get_sync(&adapter->pdev->dev); 2265 return 0; 2266 } 2267 2268 static void igb_ethtool_complete(struct net_device *netdev) 2269 { 2270 struct igb_adapter *adapter = netdev_priv(netdev); 2271 pm_runtime_put(&adapter->pdev->dev); 2272 } 2273 2274 static const struct ethtool_ops igb_ethtool_ops = { 2275 .get_settings = igb_get_settings, 2276 .set_settings = igb_set_settings, 2277 .get_drvinfo = igb_get_drvinfo, 2278 .get_regs_len = igb_get_regs_len, 2279 .get_regs = igb_get_regs, 2280 .get_wol = igb_get_wol, 2281 .set_wol = igb_set_wol, 2282 .get_msglevel = igb_get_msglevel, 2283 .set_msglevel = igb_set_msglevel, 2284 .nway_reset = igb_nway_reset, 2285 .get_link = igb_get_link, 2286 .get_eeprom_len = igb_get_eeprom_len, 2287 .get_eeprom = igb_get_eeprom, 2288 .set_eeprom = igb_set_eeprom, 2289 .get_ringparam = igb_get_ringparam, 2290 .set_ringparam = igb_set_ringparam, 2291 .get_pauseparam = igb_get_pauseparam, 2292 .set_pauseparam = igb_set_pauseparam, 2293 .self_test = igb_diag_test, 2294 .get_strings = igb_get_strings, 2295 .set_phys_id = igb_set_phys_id, 2296 .get_sset_count = igb_get_sset_count, 2297 .get_ethtool_stats = igb_get_ethtool_stats, 2298 .get_coalesce = igb_get_coalesce, 2299 .set_coalesce = igb_set_coalesce, 2300 .begin = igb_ethtool_begin, 2301 .complete = igb_ethtool_complete, 2302 }; 2303 2304 void igb_set_ethtool_ops(struct net_device *netdev) 2305 { 2306 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); 2307 } 2308