1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* ethtool support for igb */ 5 6 #include <linux/vmalloc.h> 7 #include <linux/netdevice.h> 8 #include <linux/pci.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/if_ether.h> 12 #include <linux/ethtool.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/highmem.h> 17 #include <linux/mdio.h> 18 19 #include "igb.h" 20 21 struct igb_stats { 22 char stat_string[ETH_GSTRING_LEN]; 23 int sizeof_stat; 24 int stat_offset; 25 }; 26 27 #define IGB_STAT(_name, _stat) { \ 28 .stat_string = _name, \ 29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \ 30 .stat_offset = offsetof(struct igb_adapter, _stat) \ 31 } 32 static const struct igb_stats igb_gstrings_stats[] = { 33 IGB_STAT("rx_packets", stats.gprc), 34 IGB_STAT("tx_packets", stats.gptc), 35 IGB_STAT("rx_bytes", stats.gorc), 36 IGB_STAT("tx_bytes", stats.gotc), 37 IGB_STAT("rx_broadcast", stats.bprc), 38 IGB_STAT("tx_broadcast", stats.bptc), 39 IGB_STAT("rx_multicast", stats.mprc), 40 IGB_STAT("tx_multicast", stats.mptc), 41 IGB_STAT("multicast", stats.mprc), 42 IGB_STAT("collisions", stats.colc), 43 IGB_STAT("rx_crc_errors", stats.crcerrs), 44 IGB_STAT("rx_no_buffer_count", stats.rnbc), 45 IGB_STAT("rx_missed_errors", stats.mpc), 46 IGB_STAT("tx_aborted_errors", stats.ecol), 47 IGB_STAT("tx_carrier_errors", stats.tncrs), 48 IGB_STAT("tx_window_errors", stats.latecol), 49 IGB_STAT("tx_abort_late_coll", stats.latecol), 50 IGB_STAT("tx_deferred_ok", stats.dc), 51 IGB_STAT("tx_single_coll_ok", stats.scc), 52 IGB_STAT("tx_multi_coll_ok", stats.mcc), 53 IGB_STAT("tx_timeout_count", tx_timeout_count), 54 IGB_STAT("rx_long_length_errors", stats.roc), 55 IGB_STAT("rx_short_length_errors", stats.ruc), 56 IGB_STAT("rx_align_errors", stats.algnerrc), 57 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 59 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 61 IGB_STAT("tx_flow_control_xon", stats.xontxc), 62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 63 IGB_STAT("rx_long_byte_count", stats.gorc), 64 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 65 IGB_STAT("tx_smbus", stats.mgptc), 66 IGB_STAT("rx_smbus", stats.mgprc), 67 IGB_STAT("dropped_smbus", stats.mgpdc), 68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped), 74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 75 }; 76 77 #define IGB_NETDEV_STAT(_net_stat) { \ 78 .stat_string = __stringify(_net_stat), \ 79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \ 80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 81 } 82 static const struct igb_stats igb_gstrings_net_stats[] = { 83 IGB_NETDEV_STAT(rx_errors), 84 IGB_NETDEV_STAT(tx_errors), 85 IGB_NETDEV_STAT(tx_dropped), 86 IGB_NETDEV_STAT(rx_length_errors), 87 IGB_NETDEV_STAT(rx_over_errors), 88 IGB_NETDEV_STAT(rx_frame_errors), 89 IGB_NETDEV_STAT(rx_fifo_errors), 90 IGB_NETDEV_STAT(tx_fifo_errors), 91 IGB_NETDEV_STAT(tx_heartbeat_errors) 92 }; 93 94 #define IGB_GLOBAL_STATS_LEN \ 95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 96 #define IGB_NETDEV_STATS_LEN \ 97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 98 #define IGB_RX_QUEUE_STATS_LEN \ 99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 100 101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 102 103 #define IGB_QUEUE_STATS_LEN \ 104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 105 IGB_RX_QUEUE_STATS_LEN) + \ 106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 107 IGB_TX_QUEUE_STATS_LEN)) 108 #define IGB_STATS_LEN \ 109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 110 111 enum igb_diagnostics_results { 112 TEST_REG = 0, 113 TEST_EEP, 114 TEST_IRQ, 115 TEST_LOOP, 116 TEST_LINK 117 }; 118 119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 120 [TEST_REG] = "Register test (offline)", 121 [TEST_EEP] = "Eeprom test (offline)", 122 [TEST_IRQ] = "Interrupt test (offline)", 123 [TEST_LOOP] = "Loopback test (offline)", 124 [TEST_LINK] = "Link test (on/offline)" 125 }; 126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 127 128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = { 129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) 130 "legacy-rx", 131 }; 132 133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings) 134 135 static int igb_get_link_ksettings(struct net_device *netdev, 136 struct ethtool_link_ksettings *cmd) 137 { 138 struct igb_adapter *adapter = netdev_priv(netdev); 139 struct e1000_hw *hw = &adapter->hw; 140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 142 u32 status; 143 u32 speed; 144 u32 supported, advertising; 145 146 status = pm_runtime_suspended(&adapter->pdev->dev) ? 147 0 : rd32(E1000_STATUS); 148 if (hw->phy.media_type == e1000_media_type_copper) { 149 150 supported = (SUPPORTED_10baseT_Half | 151 SUPPORTED_10baseT_Full | 152 SUPPORTED_100baseT_Half | 153 SUPPORTED_100baseT_Full | 154 SUPPORTED_1000baseT_Full| 155 SUPPORTED_Autoneg | 156 SUPPORTED_TP | 157 SUPPORTED_Pause); 158 advertising = ADVERTISED_TP; 159 160 if (hw->mac.autoneg == 1) { 161 advertising |= ADVERTISED_Autoneg; 162 /* the e1000 autoneg seems to match ethtool nicely */ 163 advertising |= hw->phy.autoneg_advertised; 164 } 165 166 cmd->base.port = PORT_TP; 167 cmd->base.phy_address = hw->phy.addr; 168 } else { 169 supported = (SUPPORTED_FIBRE | 170 SUPPORTED_1000baseKX_Full | 171 SUPPORTED_Autoneg | 172 SUPPORTED_Pause); 173 advertising = (ADVERTISED_FIBRE | 174 ADVERTISED_1000baseKX_Full); 175 if (hw->mac.type == e1000_i354) { 176 if ((hw->device_id == 177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 178 !(status & E1000_STATUS_2P5_SKU_OVER)) { 179 supported |= SUPPORTED_2500baseX_Full; 180 supported &= ~SUPPORTED_1000baseKX_Full; 181 advertising |= ADVERTISED_2500baseX_Full; 182 advertising &= ~ADVERTISED_1000baseKX_Full; 183 } 184 } 185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { 186 supported |= SUPPORTED_100baseT_Full; 187 advertising |= ADVERTISED_100baseT_Full; 188 } 189 if (hw->mac.autoneg == 1) 190 advertising |= ADVERTISED_Autoneg; 191 192 cmd->base.port = PORT_FIBRE; 193 } 194 if (hw->mac.autoneg != 1) 195 advertising &= ~(ADVERTISED_Pause | 196 ADVERTISED_Asym_Pause); 197 198 switch (hw->fc.requested_mode) { 199 case e1000_fc_full: 200 advertising |= ADVERTISED_Pause; 201 break; 202 case e1000_fc_rx_pause: 203 advertising |= (ADVERTISED_Pause | 204 ADVERTISED_Asym_Pause); 205 break; 206 case e1000_fc_tx_pause: 207 advertising |= ADVERTISED_Asym_Pause; 208 break; 209 default: 210 advertising &= ~(ADVERTISED_Pause | 211 ADVERTISED_Asym_Pause); 212 } 213 if (status & E1000_STATUS_LU) { 214 if ((status & E1000_STATUS_2P5_SKU) && 215 !(status & E1000_STATUS_2P5_SKU_OVER)) { 216 speed = SPEED_2500; 217 } else if (status & E1000_STATUS_SPEED_1000) { 218 speed = SPEED_1000; 219 } else if (status & E1000_STATUS_SPEED_100) { 220 speed = SPEED_100; 221 } else { 222 speed = SPEED_10; 223 } 224 if ((status & E1000_STATUS_FD) || 225 hw->phy.media_type != e1000_media_type_copper) 226 cmd->base.duplex = DUPLEX_FULL; 227 else 228 cmd->base.duplex = DUPLEX_HALF; 229 } else { 230 speed = SPEED_UNKNOWN; 231 cmd->base.duplex = DUPLEX_UNKNOWN; 232 } 233 cmd->base.speed = speed; 234 if ((hw->phy.media_type == e1000_media_type_fiber) || 235 hw->mac.autoneg) 236 cmd->base.autoneg = AUTONEG_ENABLE; 237 else 238 cmd->base.autoneg = AUTONEG_DISABLE; 239 240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 241 if (hw->phy.media_type == e1000_media_type_copper) 242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 243 ETH_TP_MDI; 244 else 245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 246 247 if (hw->phy.mdix == AUTO_ALL_MODES) 248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 249 else 250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; 251 252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 253 supported); 254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 255 advertising); 256 257 return 0; 258 } 259 260 static int igb_set_link_ksettings(struct net_device *netdev, 261 const struct ethtool_link_ksettings *cmd) 262 { 263 struct igb_adapter *adapter = netdev_priv(netdev); 264 struct e1000_hw *hw = &adapter->hw; 265 u32 advertising; 266 267 /* When SoL/IDER sessions are active, autoneg/speed/duplex 268 * cannot be changed 269 */ 270 if (igb_check_reset_block(hw)) { 271 dev_err(&adapter->pdev->dev, 272 "Cannot change link characteristics when SoL/IDER is active.\n"); 273 return -EINVAL; 274 } 275 276 /* MDI setting is only allowed when autoneg enabled because 277 * some hardware doesn't allow MDI setting when speed or 278 * duplex is forced. 279 */ 280 if (cmd->base.eth_tp_mdix_ctrl) { 281 if (hw->phy.media_type != e1000_media_type_copper) 282 return -EOPNOTSUPP; 283 284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 285 (cmd->base.autoneg != AUTONEG_ENABLE)) { 286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 287 return -EINVAL; 288 } 289 } 290 291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 292 usleep_range(1000, 2000); 293 294 ethtool_convert_link_mode_to_legacy_u32(&advertising, 295 cmd->link_modes.advertising); 296 297 if (cmd->base.autoneg == AUTONEG_ENABLE) { 298 hw->mac.autoneg = 1; 299 if (hw->phy.media_type == e1000_media_type_fiber) { 300 hw->phy.autoneg_advertised = advertising | 301 ADVERTISED_FIBRE | 302 ADVERTISED_Autoneg; 303 switch (adapter->link_speed) { 304 case SPEED_2500: 305 hw->phy.autoneg_advertised = 306 ADVERTISED_2500baseX_Full; 307 break; 308 case SPEED_1000: 309 hw->phy.autoneg_advertised = 310 ADVERTISED_1000baseT_Full; 311 break; 312 case SPEED_100: 313 hw->phy.autoneg_advertised = 314 ADVERTISED_100baseT_Full; 315 break; 316 default: 317 break; 318 } 319 } else { 320 hw->phy.autoneg_advertised = advertising | 321 ADVERTISED_TP | 322 ADVERTISED_Autoneg; 323 } 324 advertising = hw->phy.autoneg_advertised; 325 if (adapter->fc_autoneg) 326 hw->fc.requested_mode = e1000_fc_default; 327 } else { 328 u32 speed = cmd->base.speed; 329 /* calling this overrides forced MDI setting */ 330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { 331 clear_bit(__IGB_RESETTING, &adapter->state); 332 return -EINVAL; 333 } 334 } 335 336 /* MDI-X => 2; MDI => 1; Auto => 3 */ 337 if (cmd->base.eth_tp_mdix_ctrl) { 338 /* fix up the value for auto (3 => 0) as zero is mapped 339 * internally to auto 340 */ 341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 342 hw->phy.mdix = AUTO_ALL_MODES; 343 else 344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; 345 } 346 347 /* reset the link */ 348 if (netif_running(adapter->netdev)) { 349 igb_down(adapter); 350 igb_up(adapter); 351 } else 352 igb_reset(adapter); 353 354 clear_bit(__IGB_RESETTING, &adapter->state); 355 return 0; 356 } 357 358 static u32 igb_get_link(struct net_device *netdev) 359 { 360 struct igb_adapter *adapter = netdev_priv(netdev); 361 struct e1000_mac_info *mac = &adapter->hw.mac; 362 363 /* If the link is not reported up to netdev, interrupts are disabled, 364 * and so the physical link state may have changed since we last 365 * looked. Set get_link_status to make sure that the true link 366 * state is interrogated, rather than pulling a cached and possibly 367 * stale link state from the driver. 368 */ 369 if (!netif_carrier_ok(netdev)) 370 mac->get_link_status = 1; 371 372 return igb_has_link(adapter); 373 } 374 375 static void igb_get_pauseparam(struct net_device *netdev, 376 struct ethtool_pauseparam *pause) 377 { 378 struct igb_adapter *adapter = netdev_priv(netdev); 379 struct e1000_hw *hw = &adapter->hw; 380 381 pause->autoneg = 382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 383 384 if (hw->fc.current_mode == e1000_fc_rx_pause) 385 pause->rx_pause = 1; 386 else if (hw->fc.current_mode == e1000_fc_tx_pause) 387 pause->tx_pause = 1; 388 else if (hw->fc.current_mode == e1000_fc_full) { 389 pause->rx_pause = 1; 390 pause->tx_pause = 1; 391 } 392 } 393 394 static int igb_set_pauseparam(struct net_device *netdev, 395 struct ethtool_pauseparam *pause) 396 { 397 struct igb_adapter *adapter = netdev_priv(netdev); 398 struct e1000_hw *hw = &adapter->hw; 399 int retval = 0; 400 int i; 401 402 /* 100basefx does not support setting link flow control */ 403 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 404 return -EINVAL; 405 406 adapter->fc_autoneg = pause->autoneg; 407 408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 409 usleep_range(1000, 2000); 410 411 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 412 hw->fc.requested_mode = e1000_fc_default; 413 if (netif_running(adapter->netdev)) { 414 igb_down(adapter); 415 igb_up(adapter); 416 } else { 417 igb_reset(adapter); 418 } 419 } else { 420 if (pause->rx_pause && pause->tx_pause) 421 hw->fc.requested_mode = e1000_fc_full; 422 else if (pause->rx_pause && !pause->tx_pause) 423 hw->fc.requested_mode = e1000_fc_rx_pause; 424 else if (!pause->rx_pause && pause->tx_pause) 425 hw->fc.requested_mode = e1000_fc_tx_pause; 426 else if (!pause->rx_pause && !pause->tx_pause) 427 hw->fc.requested_mode = e1000_fc_none; 428 429 hw->fc.current_mode = hw->fc.requested_mode; 430 431 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 432 igb_force_mac_fc(hw) : igb_setup_link(hw)); 433 434 /* Make sure SRRCTL considers new fc settings for each ring */ 435 for (i = 0; i < adapter->num_rx_queues; i++) { 436 struct igb_ring *ring = adapter->rx_ring[i]; 437 438 igb_setup_srrctl(adapter, ring); 439 } 440 } 441 442 clear_bit(__IGB_RESETTING, &adapter->state); 443 return retval; 444 } 445 446 static u32 igb_get_msglevel(struct net_device *netdev) 447 { 448 struct igb_adapter *adapter = netdev_priv(netdev); 449 return adapter->msg_enable; 450 } 451 452 static void igb_set_msglevel(struct net_device *netdev, u32 data) 453 { 454 struct igb_adapter *adapter = netdev_priv(netdev); 455 adapter->msg_enable = data; 456 } 457 458 static int igb_get_regs_len(struct net_device *netdev) 459 { 460 #define IGB_REGS_LEN 740 461 return IGB_REGS_LEN * sizeof(u32); 462 } 463 464 static void igb_get_regs(struct net_device *netdev, 465 struct ethtool_regs *regs, void *p) 466 { 467 struct igb_adapter *adapter = netdev_priv(netdev); 468 struct e1000_hw *hw = &adapter->hw; 469 u32 *regs_buff = p; 470 u8 i; 471 472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 473 474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 475 476 /* General Registers */ 477 regs_buff[0] = rd32(E1000_CTRL); 478 regs_buff[1] = rd32(E1000_STATUS); 479 regs_buff[2] = rd32(E1000_CTRL_EXT); 480 regs_buff[3] = rd32(E1000_MDIC); 481 regs_buff[4] = rd32(E1000_SCTL); 482 regs_buff[5] = rd32(E1000_CONNSW); 483 regs_buff[6] = rd32(E1000_VET); 484 regs_buff[7] = rd32(E1000_LEDCTL); 485 regs_buff[8] = rd32(E1000_PBA); 486 regs_buff[9] = rd32(E1000_PBS); 487 regs_buff[10] = rd32(E1000_FRTIMER); 488 regs_buff[11] = rd32(E1000_TCPTIMER); 489 490 /* NVM Register */ 491 regs_buff[12] = rd32(E1000_EECD); 492 493 /* Interrupt */ 494 /* Reading EICS for EICR because they read the 495 * same but EICS does not clear on read 496 */ 497 regs_buff[13] = rd32(E1000_EICS); 498 regs_buff[14] = rd32(E1000_EICS); 499 regs_buff[15] = rd32(E1000_EIMS); 500 regs_buff[16] = rd32(E1000_EIMC); 501 regs_buff[17] = rd32(E1000_EIAC); 502 regs_buff[18] = rd32(E1000_EIAM); 503 /* Reading ICS for ICR because they read the 504 * same but ICS does not clear on read 505 */ 506 regs_buff[19] = rd32(E1000_ICS); 507 regs_buff[20] = rd32(E1000_ICS); 508 regs_buff[21] = rd32(E1000_IMS); 509 regs_buff[22] = rd32(E1000_IMC); 510 regs_buff[23] = rd32(E1000_IAC); 511 regs_buff[24] = rd32(E1000_IAM); 512 regs_buff[25] = rd32(E1000_IMIRVP); 513 514 /* Flow Control */ 515 regs_buff[26] = rd32(E1000_FCAL); 516 regs_buff[27] = rd32(E1000_FCAH); 517 regs_buff[28] = rd32(E1000_FCTTV); 518 regs_buff[29] = rd32(E1000_FCRTL); 519 regs_buff[30] = rd32(E1000_FCRTH); 520 regs_buff[31] = rd32(E1000_FCRTV); 521 522 /* Receive */ 523 regs_buff[32] = rd32(E1000_RCTL); 524 regs_buff[33] = rd32(E1000_RXCSUM); 525 regs_buff[34] = rd32(E1000_RLPML); 526 regs_buff[35] = rd32(E1000_RFCTL); 527 regs_buff[36] = rd32(E1000_MRQC); 528 regs_buff[37] = rd32(E1000_VT_CTL); 529 530 /* Transmit */ 531 regs_buff[38] = rd32(E1000_TCTL); 532 regs_buff[39] = rd32(E1000_TCTL_EXT); 533 regs_buff[40] = rd32(E1000_TIPG); 534 regs_buff[41] = rd32(E1000_DTXCTL); 535 536 /* Wake Up */ 537 regs_buff[42] = rd32(E1000_WUC); 538 regs_buff[43] = rd32(E1000_WUFC); 539 regs_buff[44] = rd32(E1000_WUS); 540 regs_buff[45] = rd32(E1000_IPAV); 541 regs_buff[46] = rd32(E1000_WUPL); 542 543 /* MAC */ 544 regs_buff[47] = rd32(E1000_PCS_CFG0); 545 regs_buff[48] = rd32(E1000_PCS_LCTL); 546 regs_buff[49] = rd32(E1000_PCS_LSTAT); 547 regs_buff[50] = rd32(E1000_PCS_ANADV); 548 regs_buff[51] = rd32(E1000_PCS_LPAB); 549 regs_buff[52] = rd32(E1000_PCS_NPTX); 550 regs_buff[53] = rd32(E1000_PCS_LPABNP); 551 552 /* Statistics */ 553 regs_buff[54] = adapter->stats.crcerrs; 554 regs_buff[55] = adapter->stats.algnerrc; 555 regs_buff[56] = adapter->stats.symerrs; 556 regs_buff[57] = adapter->stats.rxerrc; 557 regs_buff[58] = adapter->stats.mpc; 558 regs_buff[59] = adapter->stats.scc; 559 regs_buff[60] = adapter->stats.ecol; 560 regs_buff[61] = adapter->stats.mcc; 561 regs_buff[62] = adapter->stats.latecol; 562 regs_buff[63] = adapter->stats.colc; 563 regs_buff[64] = adapter->stats.dc; 564 regs_buff[65] = adapter->stats.tncrs; 565 regs_buff[66] = adapter->stats.sec; 566 regs_buff[67] = adapter->stats.htdpmc; 567 regs_buff[68] = adapter->stats.rlec; 568 regs_buff[69] = adapter->stats.xonrxc; 569 regs_buff[70] = adapter->stats.xontxc; 570 regs_buff[71] = adapter->stats.xoffrxc; 571 regs_buff[72] = adapter->stats.xofftxc; 572 regs_buff[73] = adapter->stats.fcruc; 573 regs_buff[74] = adapter->stats.prc64; 574 regs_buff[75] = adapter->stats.prc127; 575 regs_buff[76] = adapter->stats.prc255; 576 regs_buff[77] = adapter->stats.prc511; 577 regs_buff[78] = adapter->stats.prc1023; 578 regs_buff[79] = adapter->stats.prc1522; 579 regs_buff[80] = adapter->stats.gprc; 580 regs_buff[81] = adapter->stats.bprc; 581 regs_buff[82] = adapter->stats.mprc; 582 regs_buff[83] = adapter->stats.gptc; 583 regs_buff[84] = adapter->stats.gorc; 584 regs_buff[86] = adapter->stats.gotc; 585 regs_buff[88] = adapter->stats.rnbc; 586 regs_buff[89] = adapter->stats.ruc; 587 regs_buff[90] = adapter->stats.rfc; 588 regs_buff[91] = adapter->stats.roc; 589 regs_buff[92] = adapter->stats.rjc; 590 regs_buff[93] = adapter->stats.mgprc; 591 regs_buff[94] = adapter->stats.mgpdc; 592 regs_buff[95] = adapter->stats.mgptc; 593 regs_buff[96] = adapter->stats.tor; 594 regs_buff[98] = adapter->stats.tot; 595 regs_buff[100] = adapter->stats.tpr; 596 regs_buff[101] = adapter->stats.tpt; 597 regs_buff[102] = adapter->stats.ptc64; 598 regs_buff[103] = adapter->stats.ptc127; 599 regs_buff[104] = adapter->stats.ptc255; 600 regs_buff[105] = adapter->stats.ptc511; 601 regs_buff[106] = adapter->stats.ptc1023; 602 regs_buff[107] = adapter->stats.ptc1522; 603 regs_buff[108] = adapter->stats.mptc; 604 regs_buff[109] = adapter->stats.bptc; 605 regs_buff[110] = adapter->stats.tsctc; 606 regs_buff[111] = adapter->stats.iac; 607 regs_buff[112] = adapter->stats.rpthc; 608 regs_buff[113] = adapter->stats.hgptc; 609 regs_buff[114] = adapter->stats.hgorc; 610 regs_buff[116] = adapter->stats.hgotc; 611 regs_buff[118] = adapter->stats.lenerrs; 612 regs_buff[119] = adapter->stats.scvpc; 613 regs_buff[120] = adapter->stats.hrmpc; 614 615 for (i = 0; i < 4; i++) 616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 617 for (i = 0; i < 4; i++) 618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 619 for (i = 0; i < 4; i++) 620 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 621 for (i = 0; i < 4; i++) 622 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 623 for (i = 0; i < 4; i++) 624 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 625 for (i = 0; i < 4; i++) 626 regs_buff[141 + i] = rd32(E1000_RDH(i)); 627 for (i = 0; i < 4; i++) 628 regs_buff[145 + i] = rd32(E1000_RDT(i)); 629 for (i = 0; i < 4; i++) 630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 631 632 for (i = 0; i < 10; i++) 633 regs_buff[153 + i] = rd32(E1000_EITR(i)); 634 for (i = 0; i < 8; i++) 635 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 636 for (i = 0; i < 8; i++) 637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 638 for (i = 0; i < 16; i++) 639 regs_buff[179 + i] = rd32(E1000_RAL(i)); 640 for (i = 0; i < 16; i++) 641 regs_buff[195 + i] = rd32(E1000_RAH(i)); 642 643 for (i = 0; i < 4; i++) 644 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 645 for (i = 0; i < 4; i++) 646 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 647 for (i = 0; i < 4; i++) 648 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 649 for (i = 0; i < 4; i++) 650 regs_buff[223 + i] = rd32(E1000_TDH(i)); 651 for (i = 0; i < 4; i++) 652 regs_buff[227 + i] = rd32(E1000_TDT(i)); 653 for (i = 0; i < 4; i++) 654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 655 for (i = 0; i < 4; i++) 656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 657 for (i = 0; i < 4; i++) 658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 659 for (i = 0; i < 4; i++) 660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 661 662 for (i = 0; i < 4; i++) 663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 664 for (i = 0; i < 4; i++) 665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 666 for (i = 0; i < 32; i++) 667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 668 for (i = 0; i < 128; i++) 669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 670 for (i = 0; i < 128; i++) 671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 672 for (i = 0; i < 4; i++) 673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 674 675 regs_buff[547] = rd32(E1000_TDFH); 676 regs_buff[548] = rd32(E1000_TDFT); 677 regs_buff[549] = rd32(E1000_TDFHS); 678 regs_buff[550] = rd32(E1000_TDFPC); 679 680 if (hw->mac.type > e1000_82580) { 681 regs_buff[551] = adapter->stats.o2bgptc; 682 regs_buff[552] = adapter->stats.b2ospc; 683 regs_buff[553] = adapter->stats.o2bspc; 684 regs_buff[554] = adapter->stats.b2ogprc; 685 } 686 687 if (hw->mac.type == e1000_82576) { 688 for (i = 0; i < 12; i++) 689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 690 for (i = 0; i < 4; i++) 691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 692 for (i = 0; i < 12; i++) 693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 694 for (i = 0; i < 12; i++) 695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 696 for (i = 0; i < 12; i++) 697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 698 for (i = 0; i < 12; i++) 699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 700 for (i = 0; i < 12; i++) 701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 702 for (i = 0; i < 12; i++) 703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 704 705 for (i = 0; i < 12; i++) 706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 713 for (i = 0; i < 12; i++) 714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 715 for (i = 0; i < 12; i++) 716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 717 for (i = 0; i < 12; i++) 718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 719 for (i = 0; i < 12; i++) 720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 721 } 722 723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) 724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY); 725 } 726 727 static int igb_get_eeprom_len(struct net_device *netdev) 728 { 729 struct igb_adapter *adapter = netdev_priv(netdev); 730 return adapter->hw.nvm.word_size * 2; 731 } 732 733 static int igb_get_eeprom(struct net_device *netdev, 734 struct ethtool_eeprom *eeprom, u8 *bytes) 735 { 736 struct igb_adapter *adapter = netdev_priv(netdev); 737 struct e1000_hw *hw = &adapter->hw; 738 u16 *eeprom_buff; 739 int first_word, last_word; 740 int ret_val = 0; 741 u16 i; 742 743 if (eeprom->len == 0) 744 return -EINVAL; 745 746 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 747 748 first_word = eeprom->offset >> 1; 749 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 750 751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 752 GFP_KERNEL); 753 if (!eeprom_buff) 754 return -ENOMEM; 755 756 if (hw->nvm.type == e1000_nvm_eeprom_spi) 757 ret_val = hw->nvm.ops.read(hw, first_word, 758 last_word - first_word + 1, 759 eeprom_buff); 760 else { 761 for (i = 0; i < last_word - first_word + 1; i++) { 762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 763 &eeprom_buff[i]); 764 if (ret_val) 765 break; 766 } 767 } 768 769 /* Device's eeprom is always little-endian, word addressable */ 770 for (i = 0; i < last_word - first_word + 1; i++) 771 le16_to_cpus(&eeprom_buff[i]); 772 773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 774 eeprom->len); 775 kfree(eeprom_buff); 776 777 return ret_val; 778 } 779 780 static int igb_set_eeprom(struct net_device *netdev, 781 struct ethtool_eeprom *eeprom, u8 *bytes) 782 { 783 struct igb_adapter *adapter = netdev_priv(netdev); 784 struct e1000_hw *hw = &adapter->hw; 785 u16 *eeprom_buff; 786 void *ptr; 787 int max_len, first_word, last_word, ret_val = 0; 788 u16 i; 789 790 if (eeprom->len == 0) 791 return -EOPNOTSUPP; 792 793 if ((hw->mac.type >= e1000_i210) && 794 !igb_get_flash_presence_i210(hw)) { 795 return -EOPNOTSUPP; 796 } 797 798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 799 return -EFAULT; 800 801 max_len = hw->nvm.word_size * 2; 802 803 first_word = eeprom->offset >> 1; 804 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 805 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 806 if (!eeprom_buff) 807 return -ENOMEM; 808 809 ptr = (void *)eeprom_buff; 810 811 if (eeprom->offset & 1) { 812 /* need read/modify/write of first changed EEPROM word 813 * only the second byte of the word is being modified 814 */ 815 ret_val = hw->nvm.ops.read(hw, first_word, 1, 816 &eeprom_buff[0]); 817 ptr++; 818 } 819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 820 /* need read/modify/write of last changed EEPROM word 821 * only the first byte of the word is being modified 822 */ 823 ret_val = hw->nvm.ops.read(hw, last_word, 1, 824 &eeprom_buff[last_word - first_word]); 825 } 826 827 /* Device's eeprom is always little-endian, word addressable */ 828 for (i = 0; i < last_word - first_word + 1; i++) 829 le16_to_cpus(&eeprom_buff[i]); 830 831 memcpy(ptr, bytes, eeprom->len); 832 833 for (i = 0; i < last_word - first_word + 1; i++) 834 cpu_to_le16s(&eeprom_buff[i]); 835 836 ret_val = hw->nvm.ops.write(hw, first_word, 837 last_word - first_word + 1, eeprom_buff); 838 839 /* Update the checksum if nvm write succeeded */ 840 if (ret_val == 0) 841 hw->nvm.ops.update(hw); 842 843 igb_set_fw_version(adapter); 844 kfree(eeprom_buff); 845 return ret_val; 846 } 847 848 static void igb_get_drvinfo(struct net_device *netdev, 849 struct ethtool_drvinfo *drvinfo) 850 { 851 struct igb_adapter *adapter = netdev_priv(netdev); 852 853 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 854 855 /* EEPROM image version # is reported as firmware version # for 856 * 82575 controllers 857 */ 858 strlcpy(drvinfo->fw_version, adapter->fw_version, 859 sizeof(drvinfo->fw_version)); 860 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 861 sizeof(drvinfo->bus_info)); 862 863 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN; 864 } 865 866 static void igb_get_ringparam(struct net_device *netdev, 867 struct ethtool_ringparam *ring, 868 struct kernel_ethtool_ringparam *kernel_ring, 869 struct netlink_ext_ack *extack) 870 { 871 struct igb_adapter *adapter = netdev_priv(netdev); 872 873 ring->rx_max_pending = IGB_MAX_RXD; 874 ring->tx_max_pending = IGB_MAX_TXD; 875 ring->rx_pending = adapter->rx_ring_count; 876 ring->tx_pending = adapter->tx_ring_count; 877 } 878 879 static int igb_set_ringparam(struct net_device *netdev, 880 struct ethtool_ringparam *ring, 881 struct kernel_ethtool_ringparam *kernel_ring, 882 struct netlink_ext_ack *extack) 883 { 884 struct igb_adapter *adapter = netdev_priv(netdev); 885 struct igb_ring *temp_ring; 886 int i, err = 0; 887 u16 new_rx_count, new_tx_count; 888 889 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 890 return -EINVAL; 891 892 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 893 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 894 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 895 896 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 897 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 898 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 899 900 if ((new_tx_count == adapter->tx_ring_count) && 901 (new_rx_count == adapter->rx_ring_count)) { 902 /* nothing to do */ 903 return 0; 904 } 905 906 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 907 usleep_range(1000, 2000); 908 909 if (!netif_running(adapter->netdev)) { 910 for (i = 0; i < adapter->num_tx_queues; i++) 911 adapter->tx_ring[i]->count = new_tx_count; 912 for (i = 0; i < adapter->num_rx_queues; i++) 913 adapter->rx_ring[i]->count = new_rx_count; 914 adapter->tx_ring_count = new_tx_count; 915 adapter->rx_ring_count = new_rx_count; 916 goto clear_reset; 917 } 918 919 if (adapter->num_tx_queues > adapter->num_rx_queues) 920 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 921 adapter->num_tx_queues)); 922 else 923 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 924 adapter->num_rx_queues)); 925 926 if (!temp_ring) { 927 err = -ENOMEM; 928 goto clear_reset; 929 } 930 931 igb_down(adapter); 932 933 /* We can't just free everything and then setup again, 934 * because the ISRs in MSI-X mode get passed pointers 935 * to the Tx and Rx ring structs. 936 */ 937 if (new_tx_count != adapter->tx_ring_count) { 938 for (i = 0; i < adapter->num_tx_queues; i++) { 939 memcpy(&temp_ring[i], adapter->tx_ring[i], 940 sizeof(struct igb_ring)); 941 942 temp_ring[i].count = new_tx_count; 943 err = igb_setup_tx_resources(&temp_ring[i]); 944 if (err) { 945 while (i) { 946 i--; 947 igb_free_tx_resources(&temp_ring[i]); 948 } 949 goto err_setup; 950 } 951 } 952 953 for (i = 0; i < adapter->num_tx_queues; i++) { 954 igb_free_tx_resources(adapter->tx_ring[i]); 955 956 memcpy(adapter->tx_ring[i], &temp_ring[i], 957 sizeof(struct igb_ring)); 958 } 959 960 adapter->tx_ring_count = new_tx_count; 961 } 962 963 if (new_rx_count != adapter->rx_ring_count) { 964 for (i = 0; i < adapter->num_rx_queues; i++) { 965 memcpy(&temp_ring[i], adapter->rx_ring[i], 966 sizeof(struct igb_ring)); 967 968 /* Clear copied XDP RX-queue info */ 969 memset(&temp_ring[i].xdp_rxq, 0, 970 sizeof(temp_ring[i].xdp_rxq)); 971 972 temp_ring[i].count = new_rx_count; 973 err = igb_setup_rx_resources(&temp_ring[i]); 974 if (err) { 975 while (i) { 976 i--; 977 igb_free_rx_resources(&temp_ring[i]); 978 } 979 goto err_setup; 980 } 981 982 } 983 984 for (i = 0; i < adapter->num_rx_queues; i++) { 985 igb_free_rx_resources(adapter->rx_ring[i]); 986 987 memcpy(adapter->rx_ring[i], &temp_ring[i], 988 sizeof(struct igb_ring)); 989 } 990 991 adapter->rx_ring_count = new_rx_count; 992 } 993 err_setup: 994 igb_up(adapter); 995 vfree(temp_ring); 996 clear_reset: 997 clear_bit(__IGB_RESETTING, &adapter->state); 998 return err; 999 } 1000 1001 /* ethtool register test data */ 1002 struct igb_reg_test { 1003 u16 reg; 1004 u16 reg_offset; 1005 u16 array_len; 1006 u16 test_type; 1007 u32 mask; 1008 u32 write; 1009 }; 1010 1011 /* In the hardware, registers are laid out either singly, in arrays 1012 * spaced 0x100 bytes apart, or in contiguous tables. We assume 1013 * most tests take place on arrays or single registers (handled 1014 * as a single-element array) and special-case the tables. 1015 * Table tests are always pattern tests. 1016 * 1017 * We also make provision for some required setup steps by specifying 1018 * registers to be written without any read-back testing. 1019 */ 1020 1021 #define PATTERN_TEST 1 1022 #define SET_READ_TEST 2 1023 #define WRITE_NO_TEST 3 1024 #define TABLE32_TEST 4 1025 #define TABLE64_TEST_LO 5 1026 #define TABLE64_TEST_HI 6 1027 1028 /* i210 reg test */ 1029 static struct igb_reg_test reg_test_i210[] = { 1030 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1031 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1032 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1033 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1034 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1035 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1036 /* RDH is read-only for i210, only test RDT. */ 1037 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1038 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1039 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1040 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1041 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1042 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1043 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1044 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1045 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1046 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1047 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1048 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1049 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1050 0xFFFFFFFF, 0xFFFFFFFF }, 1051 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1052 0x900FFFFF, 0xFFFFFFFF }, 1053 { E1000_MTA, 0, 128, TABLE32_TEST, 1054 0xFFFFFFFF, 0xFFFFFFFF }, 1055 { 0, 0, 0, 0, 0 } 1056 }; 1057 1058 /* i350 reg test */ 1059 static struct igb_reg_test reg_test_i350[] = { 1060 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1061 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1062 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1063 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1064 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1065 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1066 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1067 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1068 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1069 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1070 /* RDH is read-only for i350, only test RDT. */ 1071 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1072 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1073 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1074 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1075 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1076 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1077 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1078 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1079 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1080 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1081 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1082 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1083 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1084 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1085 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1086 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1087 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1088 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1089 0xFFFFFFFF, 0xFFFFFFFF }, 1090 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1091 0xC3FFFFFF, 0xFFFFFFFF }, 1092 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1093 0xFFFFFFFF, 0xFFFFFFFF }, 1094 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1095 0xC3FFFFFF, 0xFFFFFFFF }, 1096 { E1000_MTA, 0, 128, TABLE32_TEST, 1097 0xFFFFFFFF, 0xFFFFFFFF }, 1098 { 0, 0, 0, 0 } 1099 }; 1100 1101 /* 82580 reg test */ 1102 static struct igb_reg_test reg_test_82580[] = { 1103 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1104 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1105 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1106 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1107 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1108 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1109 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1110 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1111 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1112 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1113 /* RDH is read-only for 82580, only test RDT. */ 1114 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1115 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1116 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1117 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1118 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1119 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1120 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1121 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1122 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1123 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1124 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1125 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1126 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1127 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1128 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1129 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1130 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1131 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1132 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1134 0x83FFFFFF, 0xFFFFFFFF }, 1135 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1136 0xFFFFFFFF, 0xFFFFFFFF }, 1137 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1138 0x83FFFFFF, 0xFFFFFFFF }, 1139 { E1000_MTA, 0, 128, TABLE32_TEST, 1140 0xFFFFFFFF, 0xFFFFFFFF }, 1141 { 0, 0, 0, 0 } 1142 }; 1143 1144 /* 82576 reg test */ 1145 static struct igb_reg_test reg_test_82576[] = { 1146 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1147 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1148 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1149 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1150 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1151 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1152 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1153 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1154 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1155 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1156 /* Enable all RX queues before testing. */ 1157 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1158 E1000_RXDCTL_QUEUE_ENABLE }, 1159 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1160 E1000_RXDCTL_QUEUE_ENABLE }, 1161 /* RDH is read-only for 82576, only test RDT. */ 1162 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1163 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1164 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1165 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1166 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1167 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1168 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1169 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1170 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1171 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1172 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1173 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1174 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1175 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1176 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1177 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1178 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1179 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1180 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1181 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1182 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1183 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1184 { 0, 0, 0, 0 } 1185 }; 1186 1187 /* 82575 register test */ 1188 static struct igb_reg_test reg_test_82575[] = { 1189 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1190 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1191 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1192 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1193 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1194 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1195 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1196 /* Enable all four RX queues before testing. */ 1197 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1198 E1000_RXDCTL_QUEUE_ENABLE }, 1199 /* RDH is read-only for 82575, only test RDT. */ 1200 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1201 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1202 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1203 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1204 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1205 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1206 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1207 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1208 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1209 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1210 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1211 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1212 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1213 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1214 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1215 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1216 { 0, 0, 0, 0 } 1217 }; 1218 1219 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1220 int reg, u32 mask, u32 write) 1221 { 1222 struct e1000_hw *hw = &adapter->hw; 1223 u32 pat, val; 1224 static const u32 _test[] = { 1225 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1226 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1227 wr32(reg, (_test[pat] & write)); 1228 val = rd32(reg) & mask; 1229 if (val != (_test[pat] & write & mask)) { 1230 dev_err(&adapter->pdev->dev, 1231 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1232 reg, val, (_test[pat] & write & mask)); 1233 *data = reg; 1234 return true; 1235 } 1236 } 1237 1238 return false; 1239 } 1240 1241 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1242 int reg, u32 mask, u32 write) 1243 { 1244 struct e1000_hw *hw = &adapter->hw; 1245 u32 val; 1246 1247 wr32(reg, write & mask); 1248 val = rd32(reg); 1249 if ((write & mask) != (val & mask)) { 1250 dev_err(&adapter->pdev->dev, 1251 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1252 reg, (val & mask), (write & mask)); 1253 *data = reg; 1254 return true; 1255 } 1256 1257 return false; 1258 } 1259 1260 #define REG_PATTERN_TEST(reg, mask, write) \ 1261 do { \ 1262 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1263 return 1; \ 1264 } while (0) 1265 1266 #define REG_SET_AND_CHECK(reg, mask, write) \ 1267 do { \ 1268 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1269 return 1; \ 1270 } while (0) 1271 1272 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1273 { 1274 struct e1000_hw *hw = &adapter->hw; 1275 struct igb_reg_test *test; 1276 u32 value, before, after; 1277 u32 i, toggle; 1278 1279 switch (adapter->hw.mac.type) { 1280 case e1000_i350: 1281 case e1000_i354: 1282 test = reg_test_i350; 1283 toggle = 0x7FEFF3FF; 1284 break; 1285 case e1000_i210: 1286 case e1000_i211: 1287 test = reg_test_i210; 1288 toggle = 0x7FEFF3FF; 1289 break; 1290 case e1000_82580: 1291 test = reg_test_82580; 1292 toggle = 0x7FEFF3FF; 1293 break; 1294 case e1000_82576: 1295 test = reg_test_82576; 1296 toggle = 0x7FFFF3FF; 1297 break; 1298 default: 1299 test = reg_test_82575; 1300 toggle = 0x7FFFF3FF; 1301 break; 1302 } 1303 1304 /* Because the status register is such a special case, 1305 * we handle it separately from the rest of the register 1306 * tests. Some bits are read-only, some toggle, and some 1307 * are writable on newer MACs. 1308 */ 1309 before = rd32(E1000_STATUS); 1310 value = (rd32(E1000_STATUS) & toggle); 1311 wr32(E1000_STATUS, toggle); 1312 after = rd32(E1000_STATUS) & toggle; 1313 if (value != after) { 1314 dev_err(&adapter->pdev->dev, 1315 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1316 after, value); 1317 *data = 1; 1318 return 1; 1319 } 1320 /* restore previous status */ 1321 wr32(E1000_STATUS, before); 1322 1323 /* Perform the remainder of the register test, looping through 1324 * the test table until we either fail or reach the null entry. 1325 */ 1326 while (test->reg) { 1327 for (i = 0; i < test->array_len; i++) { 1328 switch (test->test_type) { 1329 case PATTERN_TEST: 1330 REG_PATTERN_TEST(test->reg + 1331 (i * test->reg_offset), 1332 test->mask, 1333 test->write); 1334 break; 1335 case SET_READ_TEST: 1336 REG_SET_AND_CHECK(test->reg + 1337 (i * test->reg_offset), 1338 test->mask, 1339 test->write); 1340 break; 1341 case WRITE_NO_TEST: 1342 writel(test->write, 1343 (adapter->hw.hw_addr + test->reg) 1344 + (i * test->reg_offset)); 1345 break; 1346 case TABLE32_TEST: 1347 REG_PATTERN_TEST(test->reg + (i * 4), 1348 test->mask, 1349 test->write); 1350 break; 1351 case TABLE64_TEST_LO: 1352 REG_PATTERN_TEST(test->reg + (i * 8), 1353 test->mask, 1354 test->write); 1355 break; 1356 case TABLE64_TEST_HI: 1357 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1358 test->mask, 1359 test->write); 1360 break; 1361 } 1362 } 1363 test++; 1364 } 1365 1366 *data = 0; 1367 return 0; 1368 } 1369 1370 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1371 { 1372 struct e1000_hw *hw = &adapter->hw; 1373 1374 *data = 0; 1375 1376 /* Validate eeprom on all parts but flashless */ 1377 switch (hw->mac.type) { 1378 case e1000_i210: 1379 case e1000_i211: 1380 if (igb_get_flash_presence_i210(hw)) { 1381 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1382 *data = 2; 1383 } 1384 break; 1385 default: 1386 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1387 *data = 2; 1388 break; 1389 } 1390 1391 return *data; 1392 } 1393 1394 static irqreturn_t igb_test_intr(int irq, void *data) 1395 { 1396 struct igb_adapter *adapter = (struct igb_adapter *) data; 1397 struct e1000_hw *hw = &adapter->hw; 1398 1399 adapter->test_icr |= rd32(E1000_ICR); 1400 1401 return IRQ_HANDLED; 1402 } 1403 1404 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1405 { 1406 struct e1000_hw *hw = &adapter->hw; 1407 struct net_device *netdev = adapter->netdev; 1408 u32 mask, ics_mask, i = 0, shared_int = true; 1409 u32 irq = adapter->pdev->irq; 1410 1411 *data = 0; 1412 1413 /* Hook up test interrupt handler just for this test */ 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1415 if (request_irq(adapter->msix_entries[0].vector, 1416 igb_test_intr, 0, netdev->name, adapter)) { 1417 *data = 1; 1418 return -1; 1419 } 1420 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1421 shared_int = false; 1422 if (request_irq(irq, 1423 igb_test_intr, 0, netdev->name, adapter)) { 1424 *data = 1; 1425 return -1; 1426 } 1427 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1428 netdev->name, adapter)) { 1429 shared_int = false; 1430 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1431 netdev->name, adapter)) { 1432 *data = 1; 1433 return -1; 1434 } 1435 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1436 (shared_int ? "shared" : "unshared")); 1437 1438 /* Disable all the interrupts */ 1439 wr32(E1000_IMC, ~0); 1440 wrfl(); 1441 usleep_range(10000, 11000); 1442 1443 /* Define all writable bits for ICS */ 1444 switch (hw->mac.type) { 1445 case e1000_82575: 1446 ics_mask = 0x37F47EDD; 1447 break; 1448 case e1000_82576: 1449 ics_mask = 0x77D4FBFD; 1450 break; 1451 case e1000_82580: 1452 ics_mask = 0x77DCFED5; 1453 break; 1454 case e1000_i350: 1455 case e1000_i354: 1456 case e1000_i210: 1457 case e1000_i211: 1458 ics_mask = 0x77DCFED5; 1459 break; 1460 default: 1461 ics_mask = 0x7FFFFFFF; 1462 break; 1463 } 1464 1465 /* Test each interrupt */ 1466 for (; i < 31; i++) { 1467 /* Interrupt to test */ 1468 mask = BIT(i); 1469 1470 if (!(mask & ics_mask)) 1471 continue; 1472 1473 if (!shared_int) { 1474 /* Disable the interrupt to be reported in 1475 * the cause register and then force the same 1476 * interrupt and see if one gets posted. If 1477 * an interrupt was posted to the bus, the 1478 * test failed. 1479 */ 1480 adapter->test_icr = 0; 1481 1482 /* Flush any pending interrupts */ 1483 wr32(E1000_ICR, ~0); 1484 1485 wr32(E1000_IMC, mask); 1486 wr32(E1000_ICS, mask); 1487 wrfl(); 1488 usleep_range(10000, 11000); 1489 1490 if (adapter->test_icr & mask) { 1491 *data = 3; 1492 break; 1493 } 1494 } 1495 1496 /* Enable the interrupt to be reported in 1497 * the cause register and then force the same 1498 * interrupt and see if one gets posted. If 1499 * an interrupt was not posted to the bus, the 1500 * test failed. 1501 */ 1502 adapter->test_icr = 0; 1503 1504 /* Flush any pending interrupts */ 1505 wr32(E1000_ICR, ~0); 1506 1507 wr32(E1000_IMS, mask); 1508 wr32(E1000_ICS, mask); 1509 wrfl(); 1510 usleep_range(10000, 11000); 1511 1512 if (!(adapter->test_icr & mask)) { 1513 *data = 4; 1514 break; 1515 } 1516 1517 if (!shared_int) { 1518 /* Disable the other interrupts to be reported in 1519 * the cause register and then force the other 1520 * interrupts and see if any get posted. If 1521 * an interrupt was posted to the bus, the 1522 * test failed. 1523 */ 1524 adapter->test_icr = 0; 1525 1526 /* Flush any pending interrupts */ 1527 wr32(E1000_ICR, ~0); 1528 1529 wr32(E1000_IMC, ~mask); 1530 wr32(E1000_ICS, ~mask); 1531 wrfl(); 1532 usleep_range(10000, 11000); 1533 1534 if (adapter->test_icr & mask) { 1535 *data = 5; 1536 break; 1537 } 1538 } 1539 } 1540 1541 /* Disable all the interrupts */ 1542 wr32(E1000_IMC, ~0); 1543 wrfl(); 1544 usleep_range(10000, 11000); 1545 1546 /* Unhook test interrupt handler */ 1547 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1548 free_irq(adapter->msix_entries[0].vector, adapter); 1549 else 1550 free_irq(irq, adapter); 1551 1552 return *data; 1553 } 1554 1555 static void igb_free_desc_rings(struct igb_adapter *adapter) 1556 { 1557 igb_free_tx_resources(&adapter->test_tx_ring); 1558 igb_free_rx_resources(&adapter->test_rx_ring); 1559 } 1560 1561 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1562 { 1563 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1564 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1565 struct e1000_hw *hw = &adapter->hw; 1566 int ret_val; 1567 1568 /* Setup Tx descriptor ring and Tx buffers */ 1569 tx_ring->count = IGB_DEFAULT_TXD; 1570 tx_ring->dev = &adapter->pdev->dev; 1571 tx_ring->netdev = adapter->netdev; 1572 tx_ring->reg_idx = adapter->vfs_allocated_count; 1573 1574 if (igb_setup_tx_resources(tx_ring)) { 1575 ret_val = 1; 1576 goto err_nomem; 1577 } 1578 1579 igb_setup_tctl(adapter); 1580 igb_configure_tx_ring(adapter, tx_ring); 1581 1582 /* Setup Rx descriptor ring and Rx buffers */ 1583 rx_ring->count = IGB_DEFAULT_RXD; 1584 rx_ring->dev = &adapter->pdev->dev; 1585 rx_ring->netdev = adapter->netdev; 1586 rx_ring->reg_idx = adapter->vfs_allocated_count; 1587 1588 if (igb_setup_rx_resources(rx_ring)) { 1589 ret_val = 3; 1590 goto err_nomem; 1591 } 1592 1593 /* set the default queue to queue 0 of PF */ 1594 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1595 1596 /* enable receive ring */ 1597 igb_setup_rctl(adapter); 1598 igb_configure_rx_ring(adapter, rx_ring); 1599 1600 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1601 1602 return 0; 1603 1604 err_nomem: 1605 igb_free_desc_rings(adapter); 1606 return ret_val; 1607 } 1608 1609 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1610 { 1611 struct e1000_hw *hw = &adapter->hw; 1612 1613 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1614 igb_write_phy_reg(hw, 29, 0x001F); 1615 igb_write_phy_reg(hw, 30, 0x8FFC); 1616 igb_write_phy_reg(hw, 29, 0x001A); 1617 igb_write_phy_reg(hw, 30, 0x8FF0); 1618 } 1619 1620 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1621 { 1622 struct e1000_hw *hw = &adapter->hw; 1623 u32 ctrl_reg = 0; 1624 1625 hw->mac.autoneg = false; 1626 1627 if (hw->phy.type == e1000_phy_m88) { 1628 if (hw->phy.id != I210_I_PHY_ID) { 1629 /* Auto-MDI/MDIX Off */ 1630 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1631 /* reset to update Auto-MDI/MDIX */ 1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1633 /* autoneg off */ 1634 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1635 } else { 1636 /* force 1000, set loopback */ 1637 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1638 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1639 } 1640 } else if (hw->phy.type == e1000_phy_82580) { 1641 /* enable MII loopback */ 1642 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1643 } 1644 1645 /* add small delay to avoid loopback test failure */ 1646 msleep(50); 1647 1648 /* force 1000, set loopback */ 1649 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1650 1651 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1652 ctrl_reg = rd32(E1000_CTRL); 1653 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1654 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1655 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1656 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1657 E1000_CTRL_FD | /* Force Duplex to FULL */ 1658 E1000_CTRL_SLU); /* Set link up enable bit */ 1659 1660 if (hw->phy.type == e1000_phy_m88) 1661 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1662 1663 wr32(E1000_CTRL, ctrl_reg); 1664 1665 /* Disable the receiver on the PHY so when a cable is plugged in, the 1666 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1667 */ 1668 if (hw->phy.type == e1000_phy_m88) 1669 igb_phy_disable_receiver(adapter); 1670 1671 msleep(500); 1672 return 0; 1673 } 1674 1675 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1676 { 1677 return igb_integrated_phy_loopback(adapter); 1678 } 1679 1680 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1681 { 1682 struct e1000_hw *hw = &adapter->hw; 1683 u32 reg; 1684 1685 reg = rd32(E1000_CTRL_EXT); 1686 1687 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1688 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1689 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1690 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1691 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1693 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1694 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1695 /* Enable DH89xxCC MPHY for near end loopback */ 1696 reg = rd32(E1000_MPHY_ADDR_CTL); 1697 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1698 E1000_MPHY_PCS_CLK_REG_OFFSET; 1699 wr32(E1000_MPHY_ADDR_CTL, reg); 1700 1701 reg = rd32(E1000_MPHY_DATA); 1702 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1703 wr32(E1000_MPHY_DATA, reg); 1704 } 1705 1706 reg = rd32(E1000_RCTL); 1707 reg |= E1000_RCTL_LBM_TCVR; 1708 wr32(E1000_RCTL, reg); 1709 1710 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1711 1712 reg = rd32(E1000_CTRL); 1713 reg &= ~(E1000_CTRL_RFCE | 1714 E1000_CTRL_TFCE | 1715 E1000_CTRL_LRST); 1716 reg |= E1000_CTRL_SLU | 1717 E1000_CTRL_FD; 1718 wr32(E1000_CTRL, reg); 1719 1720 /* Unset switch control to serdes energy detect */ 1721 reg = rd32(E1000_CONNSW); 1722 reg &= ~E1000_CONNSW_ENRGSRC; 1723 wr32(E1000_CONNSW, reg); 1724 1725 /* Unset sigdetect for SERDES loopback on 1726 * 82580 and newer devices. 1727 */ 1728 if (hw->mac.type >= e1000_82580) { 1729 reg = rd32(E1000_PCS_CFG0); 1730 reg |= E1000_PCS_CFG_IGN_SD; 1731 wr32(E1000_PCS_CFG0, reg); 1732 } 1733 1734 /* Set PCS register for forced speed */ 1735 reg = rd32(E1000_PCS_LCTL); 1736 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1737 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1738 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1739 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1740 E1000_PCS_LCTL_FSD | /* Force Speed */ 1741 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1742 wr32(E1000_PCS_LCTL, reg); 1743 1744 return 0; 1745 } 1746 1747 return igb_set_phy_loopback(adapter); 1748 } 1749 1750 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1751 { 1752 struct e1000_hw *hw = &adapter->hw; 1753 u32 rctl; 1754 u16 phy_reg; 1755 1756 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1757 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1758 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1759 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1760 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1761 u32 reg; 1762 1763 /* Disable near end loopback on DH89xxCC */ 1764 reg = rd32(E1000_MPHY_ADDR_CTL); 1765 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1766 E1000_MPHY_PCS_CLK_REG_OFFSET; 1767 wr32(E1000_MPHY_ADDR_CTL, reg); 1768 1769 reg = rd32(E1000_MPHY_DATA); 1770 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1771 wr32(E1000_MPHY_DATA, reg); 1772 } 1773 1774 rctl = rd32(E1000_RCTL); 1775 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1776 wr32(E1000_RCTL, rctl); 1777 1778 hw->mac.autoneg = true; 1779 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1780 if (phy_reg & MII_CR_LOOPBACK) { 1781 phy_reg &= ~MII_CR_LOOPBACK; 1782 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1783 igb_phy_sw_reset(hw); 1784 } 1785 } 1786 1787 static void igb_create_lbtest_frame(struct sk_buff *skb, 1788 unsigned int frame_size) 1789 { 1790 memset(skb->data, 0xFF, frame_size); 1791 frame_size /= 2; 1792 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1793 skb->data[frame_size + 10] = 0xBE; 1794 skb->data[frame_size + 12] = 0xAF; 1795 } 1796 1797 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1798 unsigned int frame_size) 1799 { 1800 unsigned char *data; 1801 bool match = true; 1802 1803 frame_size >>= 1; 1804 1805 data = kmap(rx_buffer->page); 1806 1807 if (data[3] != 0xFF || 1808 data[frame_size + 10] != 0xBE || 1809 data[frame_size + 12] != 0xAF) 1810 match = false; 1811 1812 kunmap(rx_buffer->page); 1813 1814 return match; 1815 } 1816 1817 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1818 struct igb_ring *tx_ring, 1819 unsigned int size) 1820 { 1821 union e1000_adv_rx_desc *rx_desc; 1822 struct igb_rx_buffer *rx_buffer_info; 1823 struct igb_tx_buffer *tx_buffer_info; 1824 u16 rx_ntc, tx_ntc, count = 0; 1825 1826 /* initialize next to clean and descriptor values */ 1827 rx_ntc = rx_ring->next_to_clean; 1828 tx_ntc = tx_ring->next_to_clean; 1829 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1830 1831 while (rx_desc->wb.upper.length) { 1832 /* check Rx buffer */ 1833 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1834 1835 /* sync Rx buffer for CPU read */ 1836 dma_sync_single_for_cpu(rx_ring->dev, 1837 rx_buffer_info->dma, 1838 size, 1839 DMA_FROM_DEVICE); 1840 1841 /* verify contents of skb */ 1842 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1843 count++; 1844 1845 /* sync Rx buffer for device write */ 1846 dma_sync_single_for_device(rx_ring->dev, 1847 rx_buffer_info->dma, 1848 size, 1849 DMA_FROM_DEVICE); 1850 1851 /* unmap buffer on Tx side */ 1852 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1853 1854 /* Free all the Tx ring sk_buffs */ 1855 dev_kfree_skb_any(tx_buffer_info->skb); 1856 1857 /* unmap skb header data */ 1858 dma_unmap_single(tx_ring->dev, 1859 dma_unmap_addr(tx_buffer_info, dma), 1860 dma_unmap_len(tx_buffer_info, len), 1861 DMA_TO_DEVICE); 1862 dma_unmap_len_set(tx_buffer_info, len, 0); 1863 1864 /* increment Rx/Tx next to clean counters */ 1865 rx_ntc++; 1866 if (rx_ntc == rx_ring->count) 1867 rx_ntc = 0; 1868 tx_ntc++; 1869 if (tx_ntc == tx_ring->count) 1870 tx_ntc = 0; 1871 1872 /* fetch next descriptor */ 1873 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1874 } 1875 1876 netdev_tx_reset_queue(txring_txq(tx_ring)); 1877 1878 /* re-map buffers to ring, store next to clean values */ 1879 igb_alloc_rx_buffers(rx_ring, count); 1880 rx_ring->next_to_clean = rx_ntc; 1881 tx_ring->next_to_clean = tx_ntc; 1882 1883 return count; 1884 } 1885 1886 static int igb_run_loopback_test(struct igb_adapter *adapter) 1887 { 1888 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1889 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1890 u16 i, j, lc, good_cnt; 1891 int ret_val = 0; 1892 unsigned int size = IGB_RX_HDR_LEN; 1893 netdev_tx_t tx_ret_val; 1894 struct sk_buff *skb; 1895 1896 /* allocate test skb */ 1897 skb = alloc_skb(size, GFP_KERNEL); 1898 if (!skb) 1899 return 11; 1900 1901 /* place data into test skb */ 1902 igb_create_lbtest_frame(skb, size); 1903 skb_put(skb, size); 1904 1905 /* Calculate the loop count based on the largest descriptor ring 1906 * The idea is to wrap the largest ring a number of times using 64 1907 * send/receive pairs during each loop 1908 */ 1909 1910 if (rx_ring->count <= tx_ring->count) 1911 lc = ((tx_ring->count / 64) * 2) + 1; 1912 else 1913 lc = ((rx_ring->count / 64) * 2) + 1; 1914 1915 for (j = 0; j <= lc; j++) { /* loop count loop */ 1916 /* reset count of good packets */ 1917 good_cnt = 0; 1918 1919 /* place 64 packets on the transmit queue*/ 1920 for (i = 0; i < 64; i++) { 1921 skb_get(skb); 1922 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1923 if (tx_ret_val == NETDEV_TX_OK) 1924 good_cnt++; 1925 } 1926 1927 if (good_cnt != 64) { 1928 ret_val = 12; 1929 break; 1930 } 1931 1932 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1933 msleep(200); 1934 1935 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1936 if (good_cnt != 64) { 1937 ret_val = 13; 1938 break; 1939 } 1940 } /* end loop count loop */ 1941 1942 /* free the original skb */ 1943 kfree_skb(skb); 1944 1945 return ret_val; 1946 } 1947 1948 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1949 { 1950 /* PHY loopback cannot be performed if SoL/IDER 1951 * sessions are active 1952 */ 1953 if (igb_check_reset_block(&adapter->hw)) { 1954 dev_err(&adapter->pdev->dev, 1955 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1956 *data = 0; 1957 goto out; 1958 } 1959 1960 if (adapter->hw.mac.type == e1000_i354) { 1961 dev_info(&adapter->pdev->dev, 1962 "Loopback test not supported on i354.\n"); 1963 *data = 0; 1964 goto out; 1965 } 1966 *data = igb_setup_desc_rings(adapter); 1967 if (*data) 1968 goto out; 1969 *data = igb_setup_loopback_test(adapter); 1970 if (*data) 1971 goto err_loopback; 1972 *data = igb_run_loopback_test(adapter); 1973 igb_loopback_cleanup(adapter); 1974 1975 err_loopback: 1976 igb_free_desc_rings(adapter); 1977 out: 1978 return *data; 1979 } 1980 1981 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1982 { 1983 struct e1000_hw *hw = &adapter->hw; 1984 *data = 0; 1985 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1986 int i = 0; 1987 1988 hw->mac.serdes_has_link = false; 1989 1990 /* On some blade server designs, link establishment 1991 * could take as long as 2-3 minutes 1992 */ 1993 do { 1994 hw->mac.ops.check_for_link(&adapter->hw); 1995 if (hw->mac.serdes_has_link) 1996 return *data; 1997 msleep(20); 1998 } while (i++ < 3750); 1999 2000 *data = 1; 2001 } else { 2002 hw->mac.ops.check_for_link(&adapter->hw); 2003 if (hw->mac.autoneg) 2004 msleep(5000); 2005 2006 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 2007 *data = 1; 2008 } 2009 return *data; 2010 } 2011 2012 static void igb_diag_test(struct net_device *netdev, 2013 struct ethtool_test *eth_test, u64 *data) 2014 { 2015 struct igb_adapter *adapter = netdev_priv(netdev); 2016 u16 autoneg_advertised; 2017 u8 forced_speed_duplex, autoneg; 2018 bool if_running = netif_running(netdev); 2019 2020 set_bit(__IGB_TESTING, &adapter->state); 2021 2022 /* can't do offline tests on media switching devices */ 2023 if (adapter->hw.dev_spec._82575.mas_capable) 2024 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 2025 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2026 /* Offline tests */ 2027 2028 /* save speed, duplex, autoneg settings */ 2029 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2030 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2031 autoneg = adapter->hw.mac.autoneg; 2032 2033 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2034 2035 /* power up link for link test */ 2036 igb_power_up_link(adapter); 2037 2038 /* Link test performed before hardware reset so autoneg doesn't 2039 * interfere with test result 2040 */ 2041 if (igb_link_test(adapter, &data[TEST_LINK])) 2042 eth_test->flags |= ETH_TEST_FL_FAILED; 2043 2044 if (if_running) 2045 /* indicate we're in test mode */ 2046 igb_close(netdev); 2047 else 2048 igb_reset(adapter); 2049 2050 if (igb_reg_test(adapter, &data[TEST_REG])) 2051 eth_test->flags |= ETH_TEST_FL_FAILED; 2052 2053 igb_reset(adapter); 2054 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2055 eth_test->flags |= ETH_TEST_FL_FAILED; 2056 2057 igb_reset(adapter); 2058 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2059 eth_test->flags |= ETH_TEST_FL_FAILED; 2060 2061 igb_reset(adapter); 2062 /* power up link for loopback test */ 2063 igb_power_up_link(adapter); 2064 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2065 eth_test->flags |= ETH_TEST_FL_FAILED; 2066 2067 /* restore speed, duplex, autoneg settings */ 2068 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2069 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2070 adapter->hw.mac.autoneg = autoneg; 2071 2072 /* force this routine to wait until autoneg complete/timeout */ 2073 adapter->hw.phy.autoneg_wait_to_complete = true; 2074 igb_reset(adapter); 2075 adapter->hw.phy.autoneg_wait_to_complete = false; 2076 2077 clear_bit(__IGB_TESTING, &adapter->state); 2078 if (if_running) 2079 igb_open(netdev); 2080 } else { 2081 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2082 2083 /* PHY is powered down when interface is down */ 2084 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2085 eth_test->flags |= ETH_TEST_FL_FAILED; 2086 else 2087 data[TEST_LINK] = 0; 2088 2089 /* Online tests aren't run; pass by default */ 2090 data[TEST_REG] = 0; 2091 data[TEST_EEP] = 0; 2092 data[TEST_IRQ] = 0; 2093 data[TEST_LOOP] = 0; 2094 2095 clear_bit(__IGB_TESTING, &adapter->state); 2096 } 2097 msleep_interruptible(4 * 1000); 2098 } 2099 2100 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2101 { 2102 struct igb_adapter *adapter = netdev_priv(netdev); 2103 2104 wol->wolopts = 0; 2105 2106 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2107 return; 2108 2109 wol->supported = WAKE_UCAST | WAKE_MCAST | 2110 WAKE_BCAST | WAKE_MAGIC | 2111 WAKE_PHY; 2112 2113 /* apply any specific unsupported masks here */ 2114 switch (adapter->hw.device_id) { 2115 default: 2116 break; 2117 } 2118 2119 if (adapter->wol & E1000_WUFC_EX) 2120 wol->wolopts |= WAKE_UCAST; 2121 if (adapter->wol & E1000_WUFC_MC) 2122 wol->wolopts |= WAKE_MCAST; 2123 if (adapter->wol & E1000_WUFC_BC) 2124 wol->wolopts |= WAKE_BCAST; 2125 if (adapter->wol & E1000_WUFC_MAG) 2126 wol->wolopts |= WAKE_MAGIC; 2127 if (adapter->wol & E1000_WUFC_LNKC) 2128 wol->wolopts |= WAKE_PHY; 2129 } 2130 2131 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2132 { 2133 struct igb_adapter *adapter = netdev_priv(netdev); 2134 2135 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER)) 2136 return -EOPNOTSUPP; 2137 2138 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2139 return wol->wolopts ? -EOPNOTSUPP : 0; 2140 2141 /* these settings will always override what we currently have */ 2142 adapter->wol = 0; 2143 2144 if (wol->wolopts & WAKE_UCAST) 2145 adapter->wol |= E1000_WUFC_EX; 2146 if (wol->wolopts & WAKE_MCAST) 2147 adapter->wol |= E1000_WUFC_MC; 2148 if (wol->wolopts & WAKE_BCAST) 2149 adapter->wol |= E1000_WUFC_BC; 2150 if (wol->wolopts & WAKE_MAGIC) 2151 adapter->wol |= E1000_WUFC_MAG; 2152 if (wol->wolopts & WAKE_PHY) 2153 adapter->wol |= E1000_WUFC_LNKC; 2154 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2155 2156 return 0; 2157 } 2158 2159 /* bit defines for adapter->led_status */ 2160 #define IGB_LED_ON 0 2161 2162 static int igb_set_phys_id(struct net_device *netdev, 2163 enum ethtool_phys_id_state state) 2164 { 2165 struct igb_adapter *adapter = netdev_priv(netdev); 2166 struct e1000_hw *hw = &adapter->hw; 2167 2168 switch (state) { 2169 case ETHTOOL_ID_ACTIVE: 2170 igb_blink_led(hw); 2171 return 2; 2172 case ETHTOOL_ID_ON: 2173 igb_blink_led(hw); 2174 break; 2175 case ETHTOOL_ID_OFF: 2176 igb_led_off(hw); 2177 break; 2178 case ETHTOOL_ID_INACTIVE: 2179 igb_led_off(hw); 2180 clear_bit(IGB_LED_ON, &adapter->led_status); 2181 igb_cleanup_led(hw); 2182 break; 2183 } 2184 2185 return 0; 2186 } 2187 2188 static int igb_set_coalesce(struct net_device *netdev, 2189 struct ethtool_coalesce *ec, 2190 struct kernel_ethtool_coalesce *kernel_coal, 2191 struct netlink_ext_ack *extack) 2192 { 2193 struct igb_adapter *adapter = netdev_priv(netdev); 2194 int i; 2195 2196 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2197 ((ec->rx_coalesce_usecs > 3) && 2198 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2199 (ec->rx_coalesce_usecs == 2)) 2200 return -EINVAL; 2201 2202 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2203 ((ec->tx_coalesce_usecs > 3) && 2204 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2205 (ec->tx_coalesce_usecs == 2)) 2206 return -EINVAL; 2207 2208 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2209 return -EINVAL; 2210 2211 /* If ITR is disabled, disable DMAC */ 2212 if (ec->rx_coalesce_usecs == 0) { 2213 if (adapter->flags & IGB_FLAG_DMAC) 2214 adapter->flags &= ~IGB_FLAG_DMAC; 2215 } 2216 2217 /* convert to rate of irq's per second */ 2218 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2219 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2220 else 2221 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2222 2223 /* convert to rate of irq's per second */ 2224 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2225 adapter->tx_itr_setting = adapter->rx_itr_setting; 2226 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2227 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2228 else 2229 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2230 2231 for (i = 0; i < adapter->num_q_vectors; i++) { 2232 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2233 q_vector->tx.work_limit = adapter->tx_work_limit; 2234 if (q_vector->rx.ring) 2235 q_vector->itr_val = adapter->rx_itr_setting; 2236 else 2237 q_vector->itr_val = adapter->tx_itr_setting; 2238 if (q_vector->itr_val && q_vector->itr_val <= 3) 2239 q_vector->itr_val = IGB_START_ITR; 2240 q_vector->set_itr = 1; 2241 } 2242 2243 return 0; 2244 } 2245 2246 static int igb_get_coalesce(struct net_device *netdev, 2247 struct ethtool_coalesce *ec, 2248 struct kernel_ethtool_coalesce *kernel_coal, 2249 struct netlink_ext_ack *extack) 2250 { 2251 struct igb_adapter *adapter = netdev_priv(netdev); 2252 2253 if (adapter->rx_itr_setting <= 3) 2254 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2255 else 2256 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2257 2258 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2259 if (adapter->tx_itr_setting <= 3) 2260 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2261 else 2262 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2263 } 2264 2265 return 0; 2266 } 2267 2268 static int igb_nway_reset(struct net_device *netdev) 2269 { 2270 struct igb_adapter *adapter = netdev_priv(netdev); 2271 if (netif_running(netdev)) 2272 igb_reinit_locked(adapter); 2273 return 0; 2274 } 2275 2276 static int igb_get_sset_count(struct net_device *netdev, int sset) 2277 { 2278 switch (sset) { 2279 case ETH_SS_STATS: 2280 return IGB_STATS_LEN; 2281 case ETH_SS_TEST: 2282 return IGB_TEST_LEN; 2283 case ETH_SS_PRIV_FLAGS: 2284 return IGB_PRIV_FLAGS_STR_LEN; 2285 default: 2286 return -ENOTSUPP; 2287 } 2288 } 2289 2290 static void igb_get_ethtool_stats(struct net_device *netdev, 2291 struct ethtool_stats *stats, u64 *data) 2292 { 2293 struct igb_adapter *adapter = netdev_priv(netdev); 2294 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2295 unsigned int start; 2296 struct igb_ring *ring; 2297 int i, j; 2298 char *p; 2299 2300 spin_lock(&adapter->stats64_lock); 2301 igb_update_stats(adapter); 2302 2303 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2304 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2305 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2306 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2307 } 2308 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2309 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2310 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2311 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2312 } 2313 for (j = 0; j < adapter->num_tx_queues; j++) { 2314 u64 restart2; 2315 2316 ring = adapter->tx_ring[j]; 2317 do { 2318 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2319 data[i] = ring->tx_stats.packets; 2320 data[i+1] = ring->tx_stats.bytes; 2321 data[i+2] = ring->tx_stats.restart_queue; 2322 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2323 do { 2324 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2325 restart2 = ring->tx_stats.restart_queue2; 2326 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2327 data[i+2] += restart2; 2328 2329 i += IGB_TX_QUEUE_STATS_LEN; 2330 } 2331 for (j = 0; j < adapter->num_rx_queues; j++) { 2332 ring = adapter->rx_ring[j]; 2333 do { 2334 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2335 data[i] = ring->rx_stats.packets; 2336 data[i+1] = ring->rx_stats.bytes; 2337 data[i+2] = ring->rx_stats.drops; 2338 data[i+3] = ring->rx_stats.csum_err; 2339 data[i+4] = ring->rx_stats.alloc_failed; 2340 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2341 i += IGB_RX_QUEUE_STATS_LEN; 2342 } 2343 spin_unlock(&adapter->stats64_lock); 2344 } 2345 2346 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2347 { 2348 struct igb_adapter *adapter = netdev_priv(netdev); 2349 u8 *p = data; 2350 int i; 2351 2352 switch (stringset) { 2353 case ETH_SS_TEST: 2354 memcpy(data, igb_gstrings_test, sizeof(igb_gstrings_test)); 2355 break; 2356 case ETH_SS_STATS: 2357 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) 2358 ethtool_sprintf(&p, 2359 igb_gstrings_stats[i].stat_string); 2360 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) 2361 ethtool_sprintf(&p, 2362 igb_gstrings_net_stats[i].stat_string); 2363 for (i = 0; i < adapter->num_tx_queues; i++) { 2364 ethtool_sprintf(&p, "tx_queue_%u_packets", i); 2365 ethtool_sprintf(&p, "tx_queue_%u_bytes", i); 2366 ethtool_sprintf(&p, "tx_queue_%u_restart", i); 2367 } 2368 for (i = 0; i < adapter->num_rx_queues; i++) { 2369 ethtool_sprintf(&p, "rx_queue_%u_packets", i); 2370 ethtool_sprintf(&p, "rx_queue_%u_bytes", i); 2371 ethtool_sprintf(&p, "rx_queue_%u_drops", i); 2372 ethtool_sprintf(&p, "rx_queue_%u_csum_err", i); 2373 ethtool_sprintf(&p, "rx_queue_%u_alloc_failed", i); 2374 } 2375 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2376 break; 2377 case ETH_SS_PRIV_FLAGS: 2378 memcpy(data, igb_priv_flags_strings, 2379 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 2380 break; 2381 } 2382 } 2383 2384 static int igb_get_ts_info(struct net_device *dev, 2385 struct ethtool_ts_info *info) 2386 { 2387 struct igb_adapter *adapter = netdev_priv(dev); 2388 2389 if (adapter->ptp_clock) 2390 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2391 else 2392 info->phc_index = -1; 2393 2394 switch (adapter->hw.mac.type) { 2395 case e1000_82575: 2396 info->so_timestamping = 2397 SOF_TIMESTAMPING_TX_SOFTWARE | 2398 SOF_TIMESTAMPING_RX_SOFTWARE | 2399 SOF_TIMESTAMPING_SOFTWARE; 2400 return 0; 2401 case e1000_82576: 2402 case e1000_82580: 2403 case e1000_i350: 2404 case e1000_i354: 2405 case e1000_i210: 2406 case e1000_i211: 2407 info->so_timestamping = 2408 SOF_TIMESTAMPING_TX_SOFTWARE | 2409 SOF_TIMESTAMPING_RX_SOFTWARE | 2410 SOF_TIMESTAMPING_SOFTWARE | 2411 SOF_TIMESTAMPING_TX_HARDWARE | 2412 SOF_TIMESTAMPING_RX_HARDWARE | 2413 SOF_TIMESTAMPING_RAW_HARDWARE; 2414 2415 info->tx_types = 2416 BIT(HWTSTAMP_TX_OFF) | 2417 BIT(HWTSTAMP_TX_ON); 2418 2419 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2420 2421 /* 82576 does not support timestamping all packets. */ 2422 if (adapter->hw.mac.type >= e1000_82580) 2423 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2424 else 2425 info->rx_filters |= 2426 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2427 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2428 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2429 2430 return 0; 2431 default: 2432 return -EOPNOTSUPP; 2433 } 2434 } 2435 2436 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2437 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2438 struct ethtool_rxnfc *cmd) 2439 { 2440 struct ethtool_rx_flow_spec *fsp = &cmd->fs; 2441 struct igb_nfc_filter *rule = NULL; 2442 2443 /* report total rule count */ 2444 cmd->data = IGB_MAX_RXNFC_FILTERS; 2445 2446 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2447 if (fsp->location <= rule->sw_idx) 2448 break; 2449 } 2450 2451 if (!rule || fsp->location != rule->sw_idx) 2452 return -EINVAL; 2453 2454 if (rule->filter.match_flags) { 2455 fsp->flow_type = ETHER_FLOW; 2456 fsp->ring_cookie = rule->action; 2457 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2458 fsp->h_u.ether_spec.h_proto = rule->filter.etype; 2459 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; 2460 } 2461 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) { 2462 fsp->flow_type |= FLOW_EXT; 2463 fsp->h_ext.vlan_tci = rule->filter.vlan_tci; 2464 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK); 2465 } 2466 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2467 ether_addr_copy(fsp->h_u.ether_spec.h_dest, 2468 rule->filter.dst_addr); 2469 /* As we only support matching by the full 2470 * mask, return the mask to userspace 2471 */ 2472 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest); 2473 } 2474 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2475 ether_addr_copy(fsp->h_u.ether_spec.h_source, 2476 rule->filter.src_addr); 2477 /* As we only support matching by the full 2478 * mask, return the mask to userspace 2479 */ 2480 eth_broadcast_addr(fsp->m_u.ether_spec.h_source); 2481 } 2482 2483 return 0; 2484 } 2485 return -EINVAL; 2486 } 2487 2488 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter, 2489 struct ethtool_rxnfc *cmd, 2490 u32 *rule_locs) 2491 { 2492 struct igb_nfc_filter *rule; 2493 int cnt = 0; 2494 2495 /* report total rule count */ 2496 cmd->data = IGB_MAX_RXNFC_FILTERS; 2497 2498 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2499 if (cnt == cmd->rule_cnt) 2500 return -EMSGSIZE; 2501 rule_locs[cnt] = rule->sw_idx; 2502 cnt++; 2503 } 2504 2505 cmd->rule_cnt = cnt; 2506 2507 return 0; 2508 } 2509 2510 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2511 struct ethtool_rxnfc *cmd) 2512 { 2513 cmd->data = 0; 2514 2515 /* Report default options for RSS on igb */ 2516 switch (cmd->flow_type) { 2517 case TCP_V4_FLOW: 2518 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2519 fallthrough; 2520 case UDP_V4_FLOW: 2521 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2522 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2523 fallthrough; 2524 case SCTP_V4_FLOW: 2525 case AH_ESP_V4_FLOW: 2526 case AH_V4_FLOW: 2527 case ESP_V4_FLOW: 2528 case IPV4_FLOW: 2529 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2530 break; 2531 case TCP_V6_FLOW: 2532 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2533 fallthrough; 2534 case UDP_V6_FLOW: 2535 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2536 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2537 fallthrough; 2538 case SCTP_V6_FLOW: 2539 case AH_ESP_V6_FLOW: 2540 case AH_V6_FLOW: 2541 case ESP_V6_FLOW: 2542 case IPV6_FLOW: 2543 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2544 break; 2545 default: 2546 return -EINVAL; 2547 } 2548 2549 return 0; 2550 } 2551 2552 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2553 u32 *rule_locs) 2554 { 2555 struct igb_adapter *adapter = netdev_priv(dev); 2556 int ret = -EOPNOTSUPP; 2557 2558 switch (cmd->cmd) { 2559 case ETHTOOL_GRXRINGS: 2560 cmd->data = adapter->num_rx_queues; 2561 ret = 0; 2562 break; 2563 case ETHTOOL_GRXCLSRLCNT: 2564 cmd->rule_cnt = adapter->nfc_filter_count; 2565 ret = 0; 2566 break; 2567 case ETHTOOL_GRXCLSRULE: 2568 ret = igb_get_ethtool_nfc_entry(adapter, cmd); 2569 break; 2570 case ETHTOOL_GRXCLSRLALL: 2571 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs); 2572 break; 2573 case ETHTOOL_GRXFH: 2574 ret = igb_get_rss_hash_opts(adapter, cmd); 2575 break; 2576 default: 2577 break; 2578 } 2579 2580 return ret; 2581 } 2582 2583 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2584 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2585 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2586 struct ethtool_rxnfc *nfc) 2587 { 2588 u32 flags = adapter->flags; 2589 2590 /* RSS does not support anything other than hashing 2591 * to queues on src and dst IPs and ports 2592 */ 2593 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2594 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2595 return -EINVAL; 2596 2597 switch (nfc->flow_type) { 2598 case TCP_V4_FLOW: 2599 case TCP_V6_FLOW: 2600 if (!(nfc->data & RXH_IP_SRC) || 2601 !(nfc->data & RXH_IP_DST) || 2602 !(nfc->data & RXH_L4_B_0_1) || 2603 !(nfc->data & RXH_L4_B_2_3)) 2604 return -EINVAL; 2605 break; 2606 case UDP_V4_FLOW: 2607 if (!(nfc->data & RXH_IP_SRC) || 2608 !(nfc->data & RXH_IP_DST)) 2609 return -EINVAL; 2610 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2611 case 0: 2612 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2613 break; 2614 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2615 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2616 break; 2617 default: 2618 return -EINVAL; 2619 } 2620 break; 2621 case UDP_V6_FLOW: 2622 if (!(nfc->data & RXH_IP_SRC) || 2623 !(nfc->data & RXH_IP_DST)) 2624 return -EINVAL; 2625 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2626 case 0: 2627 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2628 break; 2629 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2630 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2631 break; 2632 default: 2633 return -EINVAL; 2634 } 2635 break; 2636 case AH_ESP_V4_FLOW: 2637 case AH_V4_FLOW: 2638 case ESP_V4_FLOW: 2639 case SCTP_V4_FLOW: 2640 case AH_ESP_V6_FLOW: 2641 case AH_V6_FLOW: 2642 case ESP_V6_FLOW: 2643 case SCTP_V6_FLOW: 2644 if (!(nfc->data & RXH_IP_SRC) || 2645 !(nfc->data & RXH_IP_DST) || 2646 (nfc->data & RXH_L4_B_0_1) || 2647 (nfc->data & RXH_L4_B_2_3)) 2648 return -EINVAL; 2649 break; 2650 default: 2651 return -EINVAL; 2652 } 2653 2654 /* if we changed something we need to update flags */ 2655 if (flags != adapter->flags) { 2656 struct e1000_hw *hw = &adapter->hw; 2657 u32 mrqc = rd32(E1000_MRQC); 2658 2659 if ((flags & UDP_RSS_FLAGS) && 2660 !(adapter->flags & UDP_RSS_FLAGS)) 2661 dev_err(&adapter->pdev->dev, 2662 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2663 2664 adapter->flags = flags; 2665 2666 /* Perform hash on these packet types */ 2667 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2668 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2669 E1000_MRQC_RSS_FIELD_IPV6 | 2670 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2671 2672 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2673 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2674 2675 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2676 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2677 2678 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2679 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2680 2681 wr32(E1000_MRQC, mrqc); 2682 } 2683 2684 return 0; 2685 } 2686 2687 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter, 2688 struct igb_nfc_filter *input) 2689 { 2690 struct e1000_hw *hw = &adapter->hw; 2691 u8 i; 2692 u32 etqf; 2693 u16 etype; 2694 2695 /* find an empty etype filter register */ 2696 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { 2697 if (!adapter->etype_bitmap[i]) 2698 break; 2699 } 2700 if (i == MAX_ETYPE_FILTER) { 2701 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n"); 2702 return -EINVAL; 2703 } 2704 2705 adapter->etype_bitmap[i] = true; 2706 2707 etqf = rd32(E1000_ETQF(i)); 2708 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK); 2709 2710 etqf |= E1000_ETQF_FILTER_ENABLE; 2711 etqf &= ~E1000_ETQF_ETYPE_MASK; 2712 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2713 2714 etqf &= ~E1000_ETQF_QUEUE_MASK; 2715 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2716 & E1000_ETQF_QUEUE_MASK); 2717 etqf |= E1000_ETQF_QUEUE_ENABLE; 2718 2719 wr32(E1000_ETQF(i), etqf); 2720 2721 input->etype_reg_index = i; 2722 2723 return 0; 2724 } 2725 2726 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter, 2727 struct igb_nfc_filter *input) 2728 { 2729 struct e1000_hw *hw = &adapter->hw; 2730 u8 vlan_priority; 2731 u16 queue_index; 2732 u32 vlapqf; 2733 2734 vlapqf = rd32(E1000_VLAPQF); 2735 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2736 >> VLAN_PRIO_SHIFT; 2737 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2738 2739 /* check whether this vlan prio is already set */ 2740 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) && 2741 (queue_index != input->action)) { 2742 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n"); 2743 return -EEXIST; 2744 } 2745 2746 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority); 2747 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action); 2748 2749 wr32(E1000_VLAPQF, vlapqf); 2750 2751 return 0; 2752 } 2753 2754 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2755 { 2756 struct e1000_hw *hw = &adapter->hw; 2757 int err = -EINVAL; 2758 2759 if (hw->mac.type == e1000_i210 && 2760 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) { 2761 dev_err(&adapter->pdev->dev, 2762 "i210 doesn't support flow classification rules specifying only source addresses.\n"); 2763 return -EOPNOTSUPP; 2764 } 2765 2766 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2767 err = igb_rxnfc_write_etype_filter(adapter, input); 2768 if (err) 2769 return err; 2770 } 2771 2772 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2773 err = igb_add_mac_steering_filter(adapter, 2774 input->filter.dst_addr, 2775 input->action, 0); 2776 err = min_t(int, err, 0); 2777 if (err) 2778 return err; 2779 } 2780 2781 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2782 err = igb_add_mac_steering_filter(adapter, 2783 input->filter.src_addr, 2784 input->action, 2785 IGB_MAC_STATE_SRC_ADDR); 2786 err = min_t(int, err, 0); 2787 if (err) 2788 return err; 2789 } 2790 2791 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2792 err = igb_rxnfc_write_vlan_prio_filter(adapter, input); 2793 2794 return err; 2795 } 2796 2797 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter, 2798 u16 reg_index) 2799 { 2800 struct e1000_hw *hw = &adapter->hw; 2801 u32 etqf = rd32(E1000_ETQF(reg_index)); 2802 2803 etqf &= ~E1000_ETQF_QUEUE_ENABLE; 2804 etqf &= ~E1000_ETQF_QUEUE_MASK; 2805 etqf &= ~E1000_ETQF_FILTER_ENABLE; 2806 2807 wr32(E1000_ETQF(reg_index), etqf); 2808 2809 adapter->etype_bitmap[reg_index] = false; 2810 } 2811 2812 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter, 2813 u16 vlan_tci) 2814 { 2815 struct e1000_hw *hw = &adapter->hw; 2816 u8 vlan_priority; 2817 u32 vlapqf; 2818 2819 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2820 2821 vlapqf = rd32(E1000_VLAPQF); 2822 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority); 2823 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority, 2824 E1000_VLAPQF_QUEUE_MASK); 2825 2826 wr32(E1000_VLAPQF, vlapqf); 2827 } 2828 2829 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2830 { 2831 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) 2832 igb_clear_etype_filter_regs(adapter, 2833 input->etype_reg_index); 2834 2835 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2836 igb_clear_vlan_prio_filter(adapter, 2837 ntohs(input->filter.vlan_tci)); 2838 2839 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) 2840 igb_del_mac_steering_filter(adapter, input->filter.src_addr, 2841 input->action, 2842 IGB_MAC_STATE_SRC_ADDR); 2843 2844 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) 2845 igb_del_mac_steering_filter(adapter, input->filter.dst_addr, 2846 input->action, 0); 2847 2848 return 0; 2849 } 2850 2851 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter, 2852 struct igb_nfc_filter *input, 2853 u16 sw_idx) 2854 { 2855 struct igb_nfc_filter *rule, *parent; 2856 int err = -EINVAL; 2857 2858 parent = NULL; 2859 rule = NULL; 2860 2861 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2862 /* hash found, or no matching entry */ 2863 if (rule->sw_idx >= sw_idx) 2864 break; 2865 parent = rule; 2866 } 2867 2868 /* if there is an old rule occupying our place remove it */ 2869 if (rule && (rule->sw_idx == sw_idx)) { 2870 if (!input) 2871 err = igb_erase_filter(adapter, rule); 2872 2873 hlist_del(&rule->nfc_node); 2874 kfree(rule); 2875 adapter->nfc_filter_count--; 2876 } 2877 2878 /* If no input this was a delete, err should be 0 if a rule was 2879 * successfully found and removed from the list else -EINVAL 2880 */ 2881 if (!input) 2882 return err; 2883 2884 /* initialize node */ 2885 INIT_HLIST_NODE(&input->nfc_node); 2886 2887 /* add filter to the list */ 2888 if (parent) 2889 hlist_add_behind(&input->nfc_node, &parent->nfc_node); 2890 else 2891 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list); 2892 2893 /* update counts */ 2894 adapter->nfc_filter_count++; 2895 2896 return 0; 2897 } 2898 2899 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, 2900 struct ethtool_rxnfc *cmd) 2901 { 2902 struct net_device *netdev = adapter->netdev; 2903 struct ethtool_rx_flow_spec *fsp = 2904 (struct ethtool_rx_flow_spec *)&cmd->fs; 2905 struct igb_nfc_filter *input, *rule; 2906 int err = 0; 2907 2908 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 2909 return -EOPNOTSUPP; 2910 2911 /* Don't allow programming if the action is a queue greater than 2912 * the number of online Rx queues. 2913 */ 2914 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) || 2915 (fsp->ring_cookie >= adapter->num_rx_queues)) { 2916 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n"); 2917 return -EINVAL; 2918 } 2919 2920 /* Don't allow indexes to exist outside of available space */ 2921 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) { 2922 dev_err(&adapter->pdev->dev, "Location out of range\n"); 2923 return -EINVAL; 2924 } 2925 2926 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW) 2927 return -EINVAL; 2928 2929 input = kzalloc(sizeof(*input), GFP_KERNEL); 2930 if (!input) 2931 return -ENOMEM; 2932 2933 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) { 2934 input->filter.etype = fsp->h_u.ether_spec.h_proto; 2935 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE; 2936 } 2937 2938 /* Only support matching addresses by the full mask */ 2939 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) { 2940 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR; 2941 ether_addr_copy(input->filter.src_addr, 2942 fsp->h_u.ether_spec.h_source); 2943 } 2944 2945 /* Only support matching addresses by the full mask */ 2946 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) { 2947 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR; 2948 ether_addr_copy(input->filter.dst_addr, 2949 fsp->h_u.ether_spec.h_dest); 2950 } 2951 2952 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) { 2953 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) { 2954 err = -EINVAL; 2955 goto err_out; 2956 } 2957 input->filter.vlan_tci = fsp->h_ext.vlan_tci; 2958 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2959 } 2960 2961 input->action = fsp->ring_cookie; 2962 input->sw_idx = fsp->location; 2963 2964 spin_lock(&adapter->nfc_lock); 2965 2966 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2967 if (!memcmp(&input->filter, &rule->filter, 2968 sizeof(input->filter))) { 2969 err = -EEXIST; 2970 dev_err(&adapter->pdev->dev, 2971 "ethtool: this filter is already set\n"); 2972 goto err_out_w_lock; 2973 } 2974 } 2975 2976 err = igb_add_filter(adapter, input); 2977 if (err) 2978 goto err_out_w_lock; 2979 2980 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); 2981 2982 spin_unlock(&adapter->nfc_lock); 2983 return 0; 2984 2985 err_out_w_lock: 2986 spin_unlock(&adapter->nfc_lock); 2987 err_out: 2988 kfree(input); 2989 return err; 2990 } 2991 2992 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter, 2993 struct ethtool_rxnfc *cmd) 2994 { 2995 struct ethtool_rx_flow_spec *fsp = 2996 (struct ethtool_rx_flow_spec *)&cmd->fs; 2997 int err; 2998 2999 spin_lock(&adapter->nfc_lock); 3000 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location); 3001 spin_unlock(&adapter->nfc_lock); 3002 3003 return err; 3004 } 3005 3006 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3007 { 3008 struct igb_adapter *adapter = netdev_priv(dev); 3009 int ret = -EOPNOTSUPP; 3010 3011 switch (cmd->cmd) { 3012 case ETHTOOL_SRXFH: 3013 ret = igb_set_rss_hash_opt(adapter, cmd); 3014 break; 3015 case ETHTOOL_SRXCLSRLINS: 3016 ret = igb_add_ethtool_nfc_entry(adapter, cmd); 3017 break; 3018 case ETHTOOL_SRXCLSRLDEL: 3019 ret = igb_del_ethtool_nfc_entry(adapter, cmd); 3020 break; 3021 default: 3022 break; 3023 } 3024 3025 return ret; 3026 } 3027 3028 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3029 { 3030 struct igb_adapter *adapter = netdev_priv(netdev); 3031 struct e1000_hw *hw = &adapter->hw; 3032 u32 ret_val; 3033 u16 phy_data; 3034 3035 if ((hw->mac.type < e1000_i350) || 3036 (hw->phy.media_type != e1000_media_type_copper)) 3037 return -EOPNOTSUPP; 3038 3039 edata->supported = (SUPPORTED_1000baseT_Full | 3040 SUPPORTED_100baseT_Full); 3041 if (!hw->dev_spec._82575.eee_disable) 3042 edata->advertised = 3043 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 3044 3045 /* The IPCNFG and EEER registers are not supported on I354. */ 3046 if (hw->mac.type == e1000_i354) { 3047 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 3048 } else { 3049 u32 eeer; 3050 3051 eeer = rd32(E1000_EEER); 3052 3053 /* EEE status on negotiated link */ 3054 if (eeer & E1000_EEER_EEE_NEG) 3055 edata->eee_active = true; 3056 3057 if (eeer & E1000_EEER_TX_LPI_EN) 3058 edata->tx_lpi_enabled = true; 3059 } 3060 3061 /* EEE Link Partner Advertised */ 3062 switch (hw->mac.type) { 3063 case e1000_i350: 3064 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 3065 &phy_data); 3066 if (ret_val) 3067 return -ENODATA; 3068 3069 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3070 break; 3071 case e1000_i354: 3072 case e1000_i210: 3073 case e1000_i211: 3074 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 3075 E1000_EEE_LP_ADV_DEV_I210, 3076 &phy_data); 3077 if (ret_val) 3078 return -ENODATA; 3079 3080 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3081 3082 break; 3083 default: 3084 break; 3085 } 3086 3087 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 3088 3089 if ((hw->mac.type == e1000_i354) && 3090 (edata->eee_enabled)) 3091 edata->tx_lpi_enabled = true; 3092 3093 /* Report correct negotiated EEE status for devices that 3094 * wrongly report EEE at half-duplex 3095 */ 3096 if (adapter->link_duplex == HALF_DUPLEX) { 3097 edata->eee_enabled = false; 3098 edata->eee_active = false; 3099 edata->tx_lpi_enabled = false; 3100 edata->advertised &= ~edata->advertised; 3101 } 3102 3103 return 0; 3104 } 3105 3106 static int igb_set_eee(struct net_device *netdev, 3107 struct ethtool_eee *edata) 3108 { 3109 struct igb_adapter *adapter = netdev_priv(netdev); 3110 struct e1000_hw *hw = &adapter->hw; 3111 struct ethtool_eee eee_curr; 3112 bool adv1g_eee = true, adv100m_eee = true; 3113 s32 ret_val; 3114 3115 if ((hw->mac.type < e1000_i350) || 3116 (hw->phy.media_type != e1000_media_type_copper)) 3117 return -EOPNOTSUPP; 3118 3119 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 3120 3121 ret_val = igb_get_eee(netdev, &eee_curr); 3122 if (ret_val) 3123 return ret_val; 3124 3125 if (eee_curr.eee_enabled) { 3126 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 3127 dev_err(&adapter->pdev->dev, 3128 "Setting EEE tx-lpi is not supported\n"); 3129 return -EINVAL; 3130 } 3131 3132 /* Tx LPI timer is not implemented currently */ 3133 if (edata->tx_lpi_timer) { 3134 dev_err(&adapter->pdev->dev, 3135 "Setting EEE Tx LPI timer is not supported\n"); 3136 return -EINVAL; 3137 } 3138 3139 if (!edata->advertised || (edata->advertised & 3140 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 3141 dev_err(&adapter->pdev->dev, 3142 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 3143 return -EINVAL; 3144 } 3145 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 3146 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 3147 3148 } else if (!edata->eee_enabled) { 3149 dev_err(&adapter->pdev->dev, 3150 "Setting EEE options are not supported with EEE disabled\n"); 3151 return -EINVAL; 3152 } 3153 3154 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 3155 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 3156 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 3157 adapter->flags |= IGB_FLAG_EEE; 3158 3159 /* reset link */ 3160 if (netif_running(netdev)) 3161 igb_reinit_locked(adapter); 3162 else 3163 igb_reset(adapter); 3164 } 3165 3166 if (hw->mac.type == e1000_i354) 3167 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 3168 else 3169 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 3170 3171 if (ret_val) { 3172 dev_err(&adapter->pdev->dev, 3173 "Problem setting EEE advertisement options\n"); 3174 return -EINVAL; 3175 } 3176 3177 return 0; 3178 } 3179 3180 static int igb_get_module_info(struct net_device *netdev, 3181 struct ethtool_modinfo *modinfo) 3182 { 3183 struct igb_adapter *adapter = netdev_priv(netdev); 3184 struct e1000_hw *hw = &adapter->hw; 3185 u32 status = 0; 3186 u16 sff8472_rev, addr_mode; 3187 bool page_swap = false; 3188 3189 if ((hw->phy.media_type == e1000_media_type_copper) || 3190 (hw->phy.media_type == e1000_media_type_unknown)) 3191 return -EOPNOTSUPP; 3192 3193 /* Check whether we support SFF-8472 or not */ 3194 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 3195 if (status) 3196 return -EIO; 3197 3198 /* addressing mode is not supported */ 3199 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 3200 if (status) 3201 return -EIO; 3202 3203 /* addressing mode is not supported */ 3204 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 3205 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3206 page_swap = true; 3207 } 3208 3209 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 3210 /* We have an SFP, but it does not support SFF-8472 */ 3211 modinfo->type = ETH_MODULE_SFF_8079; 3212 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3213 } else { 3214 /* We have an SFP which supports a revision of SFF-8472 */ 3215 modinfo->type = ETH_MODULE_SFF_8472; 3216 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3217 } 3218 3219 return 0; 3220 } 3221 3222 static int igb_get_module_eeprom(struct net_device *netdev, 3223 struct ethtool_eeprom *ee, u8 *data) 3224 { 3225 struct igb_adapter *adapter = netdev_priv(netdev); 3226 struct e1000_hw *hw = &adapter->hw; 3227 u32 status = 0; 3228 u16 *dataword; 3229 u16 first_word, last_word; 3230 int i = 0; 3231 3232 if (ee->len == 0) 3233 return -EINVAL; 3234 3235 first_word = ee->offset >> 1; 3236 last_word = (ee->offset + ee->len - 1) >> 1; 3237 3238 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16), 3239 GFP_KERNEL); 3240 if (!dataword) 3241 return -ENOMEM; 3242 3243 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 3244 for (i = 0; i < last_word - first_word + 1; i++) { 3245 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 3246 &dataword[i]); 3247 if (status) { 3248 /* Error occurred while reading module */ 3249 kfree(dataword); 3250 return -EIO; 3251 } 3252 3253 be16_to_cpus(&dataword[i]); 3254 } 3255 3256 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 3257 kfree(dataword); 3258 3259 return 0; 3260 } 3261 3262 static int igb_ethtool_begin(struct net_device *netdev) 3263 { 3264 struct igb_adapter *adapter = netdev_priv(netdev); 3265 pm_runtime_get_sync(&adapter->pdev->dev); 3266 return 0; 3267 } 3268 3269 static void igb_ethtool_complete(struct net_device *netdev) 3270 { 3271 struct igb_adapter *adapter = netdev_priv(netdev); 3272 pm_runtime_put(&adapter->pdev->dev); 3273 } 3274 3275 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 3276 { 3277 return IGB_RETA_SIZE; 3278 } 3279 3280 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3281 u8 *hfunc) 3282 { 3283 struct igb_adapter *adapter = netdev_priv(netdev); 3284 int i; 3285 3286 if (hfunc) 3287 *hfunc = ETH_RSS_HASH_TOP; 3288 if (!indir) 3289 return 0; 3290 for (i = 0; i < IGB_RETA_SIZE; i++) 3291 indir[i] = adapter->rss_indir_tbl[i]; 3292 3293 return 0; 3294 } 3295 3296 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 3297 { 3298 struct e1000_hw *hw = &adapter->hw; 3299 u32 reg = E1000_RETA(0); 3300 u32 shift = 0; 3301 int i = 0; 3302 3303 switch (hw->mac.type) { 3304 case e1000_82575: 3305 shift = 6; 3306 break; 3307 case e1000_82576: 3308 /* 82576 supports 2 RSS queues for SR-IOV */ 3309 if (adapter->vfs_allocated_count) 3310 shift = 3; 3311 break; 3312 default: 3313 break; 3314 } 3315 3316 while (i < IGB_RETA_SIZE) { 3317 u32 val = 0; 3318 int j; 3319 3320 for (j = 3; j >= 0; j--) { 3321 val <<= 8; 3322 val |= adapter->rss_indir_tbl[i + j]; 3323 } 3324 3325 wr32(reg, val << shift); 3326 reg += 4; 3327 i += 4; 3328 } 3329 } 3330 3331 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 3332 const u8 *key, const u8 hfunc) 3333 { 3334 struct igb_adapter *adapter = netdev_priv(netdev); 3335 struct e1000_hw *hw = &adapter->hw; 3336 int i; 3337 u32 num_queues; 3338 3339 /* We do not allow change in unsupported parameters */ 3340 if (key || 3341 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3342 return -EOPNOTSUPP; 3343 if (!indir) 3344 return 0; 3345 3346 num_queues = adapter->rss_queues; 3347 3348 switch (hw->mac.type) { 3349 case e1000_82576: 3350 /* 82576 supports 2 RSS queues for SR-IOV */ 3351 if (adapter->vfs_allocated_count) 3352 num_queues = 2; 3353 break; 3354 default: 3355 break; 3356 } 3357 3358 /* Verify user input. */ 3359 for (i = 0; i < IGB_RETA_SIZE; i++) 3360 if (indir[i] >= num_queues) 3361 return -EINVAL; 3362 3363 3364 for (i = 0; i < IGB_RETA_SIZE; i++) 3365 adapter->rss_indir_tbl[i] = indir[i]; 3366 3367 igb_write_rss_indir_tbl(adapter); 3368 3369 return 0; 3370 } 3371 3372 static unsigned int igb_max_channels(struct igb_adapter *adapter) 3373 { 3374 return igb_get_max_rss_queues(adapter); 3375 } 3376 3377 static void igb_get_channels(struct net_device *netdev, 3378 struct ethtool_channels *ch) 3379 { 3380 struct igb_adapter *adapter = netdev_priv(netdev); 3381 3382 /* Report maximum channels */ 3383 ch->max_combined = igb_max_channels(adapter); 3384 3385 /* Report info for other vector */ 3386 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3387 ch->max_other = NON_Q_VECTORS; 3388 ch->other_count = NON_Q_VECTORS; 3389 } 3390 3391 ch->combined_count = adapter->rss_queues; 3392 } 3393 3394 static int igb_set_channels(struct net_device *netdev, 3395 struct ethtool_channels *ch) 3396 { 3397 struct igb_adapter *adapter = netdev_priv(netdev); 3398 unsigned int count = ch->combined_count; 3399 unsigned int max_combined = 0; 3400 3401 /* Verify they are not requesting separate vectors */ 3402 if (!count || ch->rx_count || ch->tx_count) 3403 return -EINVAL; 3404 3405 /* Verify other_count is valid and has not been changed */ 3406 if (ch->other_count != NON_Q_VECTORS) 3407 return -EINVAL; 3408 3409 /* Verify the number of channels doesn't exceed hw limits */ 3410 max_combined = igb_max_channels(adapter); 3411 if (count > max_combined) 3412 return -EINVAL; 3413 3414 if (count != adapter->rss_queues) { 3415 adapter->rss_queues = count; 3416 igb_set_flag_queue_pairs(adapter, max_combined); 3417 3418 /* Hardware has to reinitialize queues and interrupts to 3419 * match the new configuration. 3420 */ 3421 return igb_reinit_queues(adapter); 3422 } 3423 3424 return 0; 3425 } 3426 3427 static u32 igb_get_priv_flags(struct net_device *netdev) 3428 { 3429 struct igb_adapter *adapter = netdev_priv(netdev); 3430 u32 priv_flags = 0; 3431 3432 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3433 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX; 3434 3435 return priv_flags; 3436 } 3437 3438 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3439 { 3440 struct igb_adapter *adapter = netdev_priv(netdev); 3441 unsigned int flags = adapter->flags; 3442 3443 flags &= ~IGB_FLAG_RX_LEGACY; 3444 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX) 3445 flags |= IGB_FLAG_RX_LEGACY; 3446 3447 if (flags != adapter->flags) { 3448 adapter->flags = flags; 3449 3450 /* reset interface to repopulate queues */ 3451 if (netif_running(netdev)) 3452 igb_reinit_locked(adapter); 3453 } 3454 3455 return 0; 3456 } 3457 3458 static const struct ethtool_ops igb_ethtool_ops = { 3459 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3460 .get_drvinfo = igb_get_drvinfo, 3461 .get_regs_len = igb_get_regs_len, 3462 .get_regs = igb_get_regs, 3463 .get_wol = igb_get_wol, 3464 .set_wol = igb_set_wol, 3465 .get_msglevel = igb_get_msglevel, 3466 .set_msglevel = igb_set_msglevel, 3467 .nway_reset = igb_nway_reset, 3468 .get_link = igb_get_link, 3469 .get_eeprom_len = igb_get_eeprom_len, 3470 .get_eeprom = igb_get_eeprom, 3471 .set_eeprom = igb_set_eeprom, 3472 .get_ringparam = igb_get_ringparam, 3473 .set_ringparam = igb_set_ringparam, 3474 .get_pauseparam = igb_get_pauseparam, 3475 .set_pauseparam = igb_set_pauseparam, 3476 .self_test = igb_diag_test, 3477 .get_strings = igb_get_strings, 3478 .set_phys_id = igb_set_phys_id, 3479 .get_sset_count = igb_get_sset_count, 3480 .get_ethtool_stats = igb_get_ethtool_stats, 3481 .get_coalesce = igb_get_coalesce, 3482 .set_coalesce = igb_set_coalesce, 3483 .get_ts_info = igb_get_ts_info, 3484 .get_rxnfc = igb_get_rxnfc, 3485 .set_rxnfc = igb_set_rxnfc, 3486 .get_eee = igb_get_eee, 3487 .set_eee = igb_set_eee, 3488 .get_module_info = igb_get_module_info, 3489 .get_module_eeprom = igb_get_module_eeprom, 3490 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3491 .get_rxfh = igb_get_rxfh, 3492 .set_rxfh = igb_set_rxfh, 3493 .get_channels = igb_get_channels, 3494 .set_channels = igb_set_channels, 3495 .get_priv_flags = igb_get_priv_flags, 3496 .set_priv_flags = igb_set_priv_flags, 3497 .begin = igb_ethtool_begin, 3498 .complete = igb_ethtool_complete, 3499 .get_link_ksettings = igb_get_link_ksettings, 3500 .set_link_ksettings = igb_set_link_ksettings, 3501 }; 3502 3503 void igb_set_ethtool_ops(struct net_device *netdev) 3504 { 3505 netdev->ethtool_ops = &igb_ethtool_ops; 3506 } 3507