1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #include <linux/if_ether.h> 5 #include <linux/delay.h> 6 7 #include "e1000_mac.h" 8 #include "e1000_phy.h" 9 10 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 12 u16 *phy_ctrl); 13 static s32 igb_wait_autoneg(struct e1000_hw *hw); 14 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 15 16 /* Cable length tables */ 17 static const u16 e1000_m88_cable_length_table[] = { 18 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 19 20 static const u16 e1000_igp_2_cable_length_table[] = { 21 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 22 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 23 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 24 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 25 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 26 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 27 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 28 104, 109, 114, 118, 121, 124}; 29 30 /** 31 * igb_check_reset_block - Check if PHY reset is blocked 32 * @hw: pointer to the HW structure 33 * 34 * Read the PHY management control register and check whether a PHY reset 35 * is blocked. If a reset is not blocked return 0, otherwise 36 * return E1000_BLK_PHY_RESET (12). 37 **/ 38 s32 igb_check_reset_block(struct e1000_hw *hw) 39 { 40 u32 manc; 41 42 manc = rd32(E1000_MANC); 43 44 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 45 } 46 47 /** 48 * igb_get_phy_id - Retrieve the PHY ID and revision 49 * @hw: pointer to the HW structure 50 * 51 * Reads the PHY registers and stores the PHY ID and possibly the PHY 52 * revision in the hardware structure. 53 **/ 54 s32 igb_get_phy_id(struct e1000_hw *hw) 55 { 56 struct e1000_phy_info *phy = &hw->phy; 57 s32 ret_val = 0; 58 u16 phy_id; 59 60 /* ensure PHY page selection to fix misconfigured i210 */ 61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); 63 64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 65 if (ret_val) 66 goto out; 67 68 phy->id = (u32)(phy_id << 16); 69 udelay(20); 70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 71 if (ret_val) 72 goto out; 73 74 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 75 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 76 77 out: 78 return ret_val; 79 } 80 81 /** 82 * igb_phy_reset_dsp - Reset PHY DSP 83 * @hw: pointer to the HW structure 84 * 85 * Reset the digital signal processor. 86 **/ 87 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 88 { 89 s32 ret_val = 0; 90 91 if (!(hw->phy.ops.write_reg)) 92 goto out; 93 94 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 95 if (ret_val) 96 goto out; 97 98 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 99 100 out: 101 return ret_val; 102 } 103 104 /** 105 * igb_read_phy_reg_mdic - Read MDI control register 106 * @hw: pointer to the HW structure 107 * @offset: register offset to be read 108 * @data: pointer to the read data 109 * 110 * Reads the MDI control register in the PHY at offset and stores the 111 * information read to data. 112 **/ 113 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 114 { 115 struct e1000_phy_info *phy = &hw->phy; 116 u32 i, mdic = 0; 117 s32 ret_val = 0; 118 119 if (offset > MAX_PHY_REG_ADDRESS) { 120 hw_dbg("PHY Address %d is out of range\n", offset); 121 ret_val = -E1000_ERR_PARAM; 122 goto out; 123 } 124 125 /* Set up Op-code, Phy Address, and register offset in the MDI 126 * Control register. The MAC will take care of interfacing with the 127 * PHY to retrieve the desired data. 128 */ 129 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 130 (phy->addr << E1000_MDIC_PHY_SHIFT) | 131 (E1000_MDIC_OP_READ)); 132 133 wr32(E1000_MDIC, mdic); 134 135 /* Poll the ready bit to see if the MDI read completed 136 * Increasing the time out as testing showed failures with 137 * the lower time out 138 */ 139 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 140 udelay(50); 141 mdic = rd32(E1000_MDIC); 142 if (mdic & E1000_MDIC_READY) 143 break; 144 } 145 if (!(mdic & E1000_MDIC_READY)) { 146 hw_dbg("MDI Read did not complete\n"); 147 ret_val = -E1000_ERR_PHY; 148 goto out; 149 } 150 if (mdic & E1000_MDIC_ERROR) { 151 hw_dbg("MDI Error\n"); 152 ret_val = -E1000_ERR_PHY; 153 goto out; 154 } 155 *data = (u16) mdic; 156 157 out: 158 return ret_val; 159 } 160 161 /** 162 * igb_write_phy_reg_mdic - Write MDI control register 163 * @hw: pointer to the HW structure 164 * @offset: register offset to write to 165 * @data: data to write to register at offset 166 * 167 * Writes data to MDI control register in the PHY at offset. 168 **/ 169 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 170 { 171 struct e1000_phy_info *phy = &hw->phy; 172 u32 i, mdic = 0; 173 s32 ret_val = 0; 174 175 if (offset > MAX_PHY_REG_ADDRESS) { 176 hw_dbg("PHY Address %d is out of range\n", offset); 177 ret_val = -E1000_ERR_PARAM; 178 goto out; 179 } 180 181 /* Set up Op-code, Phy Address, and register offset in the MDI 182 * Control register. The MAC will take care of interfacing with the 183 * PHY to retrieve the desired data. 184 */ 185 mdic = (((u32)data) | 186 (offset << E1000_MDIC_REG_SHIFT) | 187 (phy->addr << E1000_MDIC_PHY_SHIFT) | 188 (E1000_MDIC_OP_WRITE)); 189 190 wr32(E1000_MDIC, mdic); 191 192 /* Poll the ready bit to see if the MDI read completed 193 * Increasing the time out as testing showed failures with 194 * the lower time out 195 */ 196 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 197 udelay(50); 198 mdic = rd32(E1000_MDIC); 199 if (mdic & E1000_MDIC_READY) 200 break; 201 } 202 if (!(mdic & E1000_MDIC_READY)) { 203 hw_dbg("MDI Write did not complete\n"); 204 ret_val = -E1000_ERR_PHY; 205 goto out; 206 } 207 if (mdic & E1000_MDIC_ERROR) { 208 hw_dbg("MDI Error\n"); 209 ret_val = -E1000_ERR_PHY; 210 goto out; 211 } 212 213 out: 214 return ret_val; 215 } 216 217 /** 218 * igb_read_phy_reg_i2c - Read PHY register using i2c 219 * @hw: pointer to the HW structure 220 * @offset: register offset to be read 221 * @data: pointer to the read data 222 * 223 * Reads the PHY register at offset using the i2c interface and stores the 224 * retrieved information in data. 225 **/ 226 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 227 { 228 struct e1000_phy_info *phy = &hw->phy; 229 u32 i, i2ccmd = 0; 230 231 /* Set up Op-code, Phy Address, and register address in the I2CCMD 232 * register. The MAC will take care of interfacing with the 233 * PHY to retrieve the desired data. 234 */ 235 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 236 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 237 (E1000_I2CCMD_OPCODE_READ)); 238 239 wr32(E1000_I2CCMD, i2ccmd); 240 241 /* Poll the ready bit to see if the I2C read completed */ 242 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 243 udelay(50); 244 i2ccmd = rd32(E1000_I2CCMD); 245 if (i2ccmd & E1000_I2CCMD_READY) 246 break; 247 } 248 if (!(i2ccmd & E1000_I2CCMD_READY)) { 249 hw_dbg("I2CCMD Read did not complete\n"); 250 return -E1000_ERR_PHY; 251 } 252 if (i2ccmd & E1000_I2CCMD_ERROR) { 253 hw_dbg("I2CCMD Error bit set\n"); 254 return -E1000_ERR_PHY; 255 } 256 257 /* Need to byte-swap the 16-bit value. */ 258 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 259 260 return 0; 261 } 262 263 /** 264 * igb_write_phy_reg_i2c - Write PHY register using i2c 265 * @hw: pointer to the HW structure 266 * @offset: register offset to write to 267 * @data: data to write at register offset 268 * 269 * Writes the data to PHY register at the offset using the i2c interface. 270 **/ 271 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 272 { 273 struct e1000_phy_info *phy = &hw->phy; 274 u32 i, i2ccmd = 0; 275 u16 phy_data_swapped; 276 277 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/ 278 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 279 hw_dbg("PHY I2C Address %d is out of range.\n", 280 hw->phy.addr); 281 return -E1000_ERR_CONFIG; 282 } 283 284 /* Swap the data bytes for the I2C interface */ 285 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 286 287 /* Set up Op-code, Phy Address, and register address in the I2CCMD 288 * register. The MAC will take care of interfacing with the 289 * PHY to retrieve the desired data. 290 */ 291 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 292 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 293 E1000_I2CCMD_OPCODE_WRITE | 294 phy_data_swapped); 295 296 wr32(E1000_I2CCMD, i2ccmd); 297 298 /* Poll the ready bit to see if the I2C read completed */ 299 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 300 udelay(50); 301 i2ccmd = rd32(E1000_I2CCMD); 302 if (i2ccmd & E1000_I2CCMD_READY) 303 break; 304 } 305 if (!(i2ccmd & E1000_I2CCMD_READY)) { 306 hw_dbg("I2CCMD Write did not complete\n"); 307 return -E1000_ERR_PHY; 308 } 309 if (i2ccmd & E1000_I2CCMD_ERROR) { 310 hw_dbg("I2CCMD Error bit set\n"); 311 return -E1000_ERR_PHY; 312 } 313 314 return 0; 315 } 316 317 /** 318 * igb_read_sfp_data_byte - Reads SFP module data. 319 * @hw: pointer to the HW structure 320 * @offset: byte location offset to be read 321 * @data: read data buffer pointer 322 * 323 * Reads one byte from SFP module data stored 324 * in SFP resided EEPROM memory or SFP diagnostic area. 325 * Function should be called with 326 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 327 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 328 * access 329 **/ 330 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 331 { 332 u32 i = 0; 333 u32 i2ccmd = 0; 334 u32 data_local = 0; 335 336 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 337 hw_dbg("I2CCMD command address exceeds upper limit\n"); 338 return -E1000_ERR_PHY; 339 } 340 341 /* Set up Op-code, EEPROM Address,in the I2CCMD 342 * register. The MAC will take care of interfacing with the 343 * EEPROM to retrieve the desired data. 344 */ 345 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 346 E1000_I2CCMD_OPCODE_READ); 347 348 wr32(E1000_I2CCMD, i2ccmd); 349 350 /* Poll the ready bit to see if the I2C read completed */ 351 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 352 udelay(50); 353 data_local = rd32(E1000_I2CCMD); 354 if (data_local & E1000_I2CCMD_READY) 355 break; 356 } 357 if (!(data_local & E1000_I2CCMD_READY)) { 358 hw_dbg("I2CCMD Read did not complete\n"); 359 return -E1000_ERR_PHY; 360 } 361 if (data_local & E1000_I2CCMD_ERROR) { 362 hw_dbg("I2CCMD Error bit set\n"); 363 return -E1000_ERR_PHY; 364 } 365 *data = (u8) data_local & 0xFF; 366 367 return 0; 368 } 369 370 /** 371 * igb_read_phy_reg_igp - Read igp PHY register 372 * @hw: pointer to the HW structure 373 * @offset: register offset to be read 374 * @data: pointer to the read data 375 * 376 * Acquires semaphore, if necessary, then reads the PHY register at offset 377 * and storing the retrieved information in data. Release any acquired 378 * semaphores before exiting. 379 **/ 380 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 381 { 382 s32 ret_val = 0; 383 384 if (!(hw->phy.ops.acquire)) 385 goto out; 386 387 ret_val = hw->phy.ops.acquire(hw); 388 if (ret_val) 389 goto out; 390 391 if (offset > MAX_PHY_MULTI_PAGE_REG) { 392 ret_val = igb_write_phy_reg_mdic(hw, 393 IGP01E1000_PHY_PAGE_SELECT, 394 (u16)offset); 395 if (ret_val) { 396 hw->phy.ops.release(hw); 397 goto out; 398 } 399 } 400 401 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 402 data); 403 404 hw->phy.ops.release(hw); 405 406 out: 407 return ret_val; 408 } 409 410 /** 411 * igb_write_phy_reg_igp - Write igp PHY register 412 * @hw: pointer to the HW structure 413 * @offset: register offset to write to 414 * @data: data to write at register offset 415 * 416 * Acquires semaphore, if necessary, then writes the data to PHY register 417 * at the offset. Release any acquired semaphores before exiting. 418 **/ 419 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 420 { 421 s32 ret_val = 0; 422 423 if (!(hw->phy.ops.acquire)) 424 goto out; 425 426 ret_val = hw->phy.ops.acquire(hw); 427 if (ret_val) 428 goto out; 429 430 if (offset > MAX_PHY_MULTI_PAGE_REG) { 431 ret_val = igb_write_phy_reg_mdic(hw, 432 IGP01E1000_PHY_PAGE_SELECT, 433 (u16)offset); 434 if (ret_val) { 435 hw->phy.ops.release(hw); 436 goto out; 437 } 438 } 439 440 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 441 data); 442 443 hw->phy.ops.release(hw); 444 445 out: 446 return ret_val; 447 } 448 449 /** 450 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 451 * @hw: pointer to the HW structure 452 * 453 * Sets up Carrier-sense on Transmit and downshift values. 454 **/ 455 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 456 { 457 struct e1000_phy_info *phy = &hw->phy; 458 s32 ret_val; 459 u16 phy_data; 460 461 if (phy->reset_disable) { 462 ret_val = 0; 463 goto out; 464 } 465 466 if (phy->type == e1000_phy_82580) { 467 ret_val = hw->phy.ops.reset(hw); 468 if (ret_val) { 469 hw_dbg("Error resetting the PHY.\n"); 470 goto out; 471 } 472 } 473 474 /* Enable CRS on TX. This must be set for half-duplex operation. */ 475 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 476 if (ret_val) 477 goto out; 478 479 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 480 481 /* Enable downshift */ 482 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 483 484 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 485 if (ret_val) 486 goto out; 487 488 /* Set MDI/MDIX mode */ 489 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 490 if (ret_val) 491 goto out; 492 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 493 /* Options: 494 * 0 - Auto (default) 495 * 1 - MDI mode 496 * 2 - MDI-X mode 497 */ 498 switch (hw->phy.mdix) { 499 case 1: 500 break; 501 case 2: 502 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 503 break; 504 case 0: 505 default: 506 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 507 break; 508 } 509 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 510 511 out: 512 return ret_val; 513 } 514 515 /** 516 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 517 * @hw: pointer to the HW structure 518 * 519 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 520 * and downshift values are set also. 521 **/ 522 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 523 { 524 struct e1000_phy_info *phy = &hw->phy; 525 s32 ret_val; 526 u16 phy_data; 527 528 if (phy->reset_disable) { 529 ret_val = 0; 530 goto out; 531 } 532 533 /* Enable CRS on TX. This must be set for half-duplex operation. */ 534 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 535 if (ret_val) 536 goto out; 537 538 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 539 540 /* Options: 541 * MDI/MDI-X = 0 (default) 542 * 0 - Auto for all speeds 543 * 1 - MDI mode 544 * 2 - MDI-X mode 545 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 546 */ 547 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 548 549 switch (phy->mdix) { 550 case 1: 551 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 552 break; 553 case 2: 554 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 555 break; 556 case 3: 557 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 558 break; 559 case 0: 560 default: 561 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 562 break; 563 } 564 565 /* Options: 566 * disable_polarity_correction = 0 (default) 567 * Automatic Correction for Reversed Cable Polarity 568 * 0 - Disabled 569 * 1 - Enabled 570 */ 571 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 572 if (phy->disable_polarity_correction == 1) 573 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 574 575 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 576 if (ret_val) 577 goto out; 578 579 if (phy->revision < E1000_REVISION_4) { 580 /* Force TX_CLK in the Extended PHY Specific Control Register 581 * to 25MHz clock. 582 */ 583 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 584 &phy_data); 585 if (ret_val) 586 goto out; 587 588 phy_data |= M88E1000_EPSCR_TX_CLK_25; 589 590 if ((phy->revision == E1000_REVISION_2) && 591 (phy->id == M88E1111_I_PHY_ID)) { 592 /* 82573L PHY - set the downshift counter to 5x. */ 593 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 594 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 595 } else { 596 /* Configure Master and Slave downshift values */ 597 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 598 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 599 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 600 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 601 } 602 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 603 phy_data); 604 if (ret_val) 605 goto out; 606 } 607 608 /* Commit the changes. */ 609 ret_val = igb_phy_sw_reset(hw); 610 if (ret_val) { 611 hw_dbg("Error committing the PHY changes\n"); 612 goto out; 613 } 614 615 out: 616 return ret_val; 617 } 618 619 /** 620 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 621 * @hw: pointer to the HW structure 622 * 623 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 624 * Also enables and sets the downshift parameters. 625 **/ 626 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 627 { 628 struct e1000_phy_info *phy = &hw->phy; 629 s32 ret_val; 630 u16 phy_data; 631 632 if (phy->reset_disable) 633 return 0; 634 635 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 636 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 637 if (ret_val) 638 return ret_val; 639 640 /* Options: 641 * MDI/MDI-X = 0 (default) 642 * 0 - Auto for all speeds 643 * 1 - MDI mode 644 * 2 - MDI-X mode 645 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 646 */ 647 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 648 649 switch (phy->mdix) { 650 case 1: 651 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 652 break; 653 case 2: 654 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 655 break; 656 case 3: 657 /* M88E1112 does not support this mode) */ 658 if (phy->id != M88E1112_E_PHY_ID) { 659 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 660 break; 661 } 662 case 0: 663 default: 664 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 665 break; 666 } 667 668 /* Options: 669 * disable_polarity_correction = 0 (default) 670 * Automatic Correction for Reversed Cable Polarity 671 * 0 - Disabled 672 * 1 - Enabled 673 */ 674 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 675 if (phy->disable_polarity_correction == 1) 676 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 677 678 /* Enable downshift and setting it to X6 */ 679 if (phy->id == M88E1543_E_PHY_ID) { 680 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 681 ret_val = 682 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 683 if (ret_val) 684 return ret_val; 685 686 ret_val = igb_phy_sw_reset(hw); 687 if (ret_val) { 688 hw_dbg("Error committing the PHY changes\n"); 689 return ret_val; 690 } 691 } 692 693 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 694 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 695 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 696 697 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 698 if (ret_val) 699 return ret_val; 700 701 /* Commit the changes. */ 702 ret_val = igb_phy_sw_reset(hw); 703 if (ret_val) { 704 hw_dbg("Error committing the PHY changes\n"); 705 return ret_val; 706 } 707 ret_val = igb_set_master_slave_mode(hw); 708 if (ret_val) 709 return ret_val; 710 711 return 0; 712 } 713 714 /** 715 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 716 * @hw: pointer to the HW structure 717 * 718 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 719 * igp PHY's. 720 **/ 721 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 722 { 723 struct e1000_phy_info *phy = &hw->phy; 724 s32 ret_val; 725 u16 data; 726 727 if (phy->reset_disable) { 728 ret_val = 0; 729 goto out; 730 } 731 732 ret_val = phy->ops.reset(hw); 733 if (ret_val) { 734 hw_dbg("Error resetting the PHY.\n"); 735 goto out; 736 } 737 738 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 739 * timeout issues when LFS is enabled. 740 */ 741 msleep(100); 742 743 /* The NVM settings will configure LPLU in D3 for 744 * non-IGP1 PHYs. 745 */ 746 if (phy->type == e1000_phy_igp) { 747 /* disable lplu d3 during driver init */ 748 if (phy->ops.set_d3_lplu_state) 749 ret_val = phy->ops.set_d3_lplu_state(hw, false); 750 if (ret_val) { 751 hw_dbg("Error Disabling LPLU D3\n"); 752 goto out; 753 } 754 } 755 756 /* disable lplu d0 during driver init */ 757 ret_val = phy->ops.set_d0_lplu_state(hw, false); 758 if (ret_val) { 759 hw_dbg("Error Disabling LPLU D0\n"); 760 goto out; 761 } 762 /* Configure mdi-mdix settings */ 763 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 764 if (ret_val) 765 goto out; 766 767 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 768 769 switch (phy->mdix) { 770 case 1: 771 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 772 break; 773 case 2: 774 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 775 break; 776 case 0: 777 default: 778 data |= IGP01E1000_PSCR_AUTO_MDIX; 779 break; 780 } 781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 782 if (ret_val) 783 goto out; 784 785 /* set auto-master slave resolution settings */ 786 if (hw->mac.autoneg) { 787 /* when autonegotiation advertisement is only 1000Mbps then we 788 * should disable SmartSpeed and enable Auto MasterSlave 789 * resolution as hardware default. 790 */ 791 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 792 /* Disable SmartSpeed */ 793 ret_val = phy->ops.read_reg(hw, 794 IGP01E1000_PHY_PORT_CONFIG, 795 &data); 796 if (ret_val) 797 goto out; 798 799 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 800 ret_val = phy->ops.write_reg(hw, 801 IGP01E1000_PHY_PORT_CONFIG, 802 data); 803 if (ret_val) 804 goto out; 805 806 /* Set auto Master/Slave resolution process */ 807 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 808 if (ret_val) 809 goto out; 810 811 data &= ~CR_1000T_MS_ENABLE; 812 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 813 if (ret_val) 814 goto out; 815 } 816 817 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 818 if (ret_val) 819 goto out; 820 821 /* load defaults for future use */ 822 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 823 ((data & CR_1000T_MS_VALUE) ? 824 e1000_ms_force_master : 825 e1000_ms_force_slave) : 826 e1000_ms_auto; 827 828 switch (phy->ms_type) { 829 case e1000_ms_force_master: 830 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 831 break; 832 case e1000_ms_force_slave: 833 data |= CR_1000T_MS_ENABLE; 834 data &= ~(CR_1000T_MS_VALUE); 835 break; 836 case e1000_ms_auto: 837 data &= ~CR_1000T_MS_ENABLE; 838 default: 839 break; 840 } 841 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 842 if (ret_val) 843 goto out; 844 } 845 846 out: 847 return ret_val; 848 } 849 850 /** 851 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 852 * @hw: pointer to the HW structure 853 * 854 * Performs initial bounds checking on autoneg advertisement parameter, then 855 * configure to advertise the full capability. Setup the PHY to autoneg 856 * and restart the negotiation process between the link partner. If 857 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 858 **/ 859 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 860 { 861 struct e1000_phy_info *phy = &hw->phy; 862 s32 ret_val; 863 u16 phy_ctrl; 864 865 /* Perform some bounds checking on the autoneg advertisement 866 * parameter. 867 */ 868 phy->autoneg_advertised &= phy->autoneg_mask; 869 870 /* If autoneg_advertised is zero, we assume it was not defaulted 871 * by the calling code so we set to advertise full capability. 872 */ 873 if (phy->autoneg_advertised == 0) 874 phy->autoneg_advertised = phy->autoneg_mask; 875 876 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 877 ret_val = igb_phy_setup_autoneg(hw); 878 if (ret_val) { 879 hw_dbg("Error Setting up Auto-Negotiation\n"); 880 goto out; 881 } 882 hw_dbg("Restarting Auto-Neg\n"); 883 884 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 885 * the Auto Neg Restart bit in the PHY control register. 886 */ 887 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 888 if (ret_val) 889 goto out; 890 891 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 892 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 893 if (ret_val) 894 goto out; 895 896 /* Does the user want to wait for Auto-Neg to complete here, or 897 * check at a later time (for example, callback routine). 898 */ 899 if (phy->autoneg_wait_to_complete) { 900 ret_val = igb_wait_autoneg(hw); 901 if (ret_val) { 902 hw_dbg("Error while waiting for autoneg to complete\n"); 903 goto out; 904 } 905 } 906 907 hw->mac.get_link_status = true; 908 909 out: 910 return ret_val; 911 } 912 913 /** 914 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 915 * @hw: pointer to the HW structure 916 * 917 * Reads the MII auto-neg advertisement register and/or the 1000T control 918 * register and if the PHY is already setup for auto-negotiation, then 919 * return successful. Otherwise, setup advertisement and flow control to 920 * the appropriate values for the wanted auto-negotiation. 921 **/ 922 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 923 { 924 struct e1000_phy_info *phy = &hw->phy; 925 s32 ret_val; 926 u16 mii_autoneg_adv_reg; 927 u16 mii_1000t_ctrl_reg = 0; 928 929 phy->autoneg_advertised &= phy->autoneg_mask; 930 931 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 932 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 933 if (ret_val) 934 goto out; 935 936 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 937 /* Read the MII 1000Base-T Control Register (Address 9). */ 938 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 939 &mii_1000t_ctrl_reg); 940 if (ret_val) 941 goto out; 942 } 943 944 /* Need to parse both autoneg_advertised and fc and set up 945 * the appropriate PHY registers. First we will parse for 946 * autoneg_advertised software override. Since we can advertise 947 * a plethora of combinations, we need to check each bit 948 * individually. 949 */ 950 951 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 952 * Advertisement Register (Address 4) and the 1000 mb speed bits in 953 * the 1000Base-T Control Register (Address 9). 954 */ 955 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 956 NWAY_AR_100TX_HD_CAPS | 957 NWAY_AR_10T_FD_CAPS | 958 NWAY_AR_10T_HD_CAPS); 959 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 960 961 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 962 963 /* Do we want to advertise 10 Mb Half Duplex? */ 964 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 965 hw_dbg("Advertise 10mb Half duplex\n"); 966 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 967 } 968 969 /* Do we want to advertise 10 Mb Full Duplex? */ 970 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 971 hw_dbg("Advertise 10mb Full duplex\n"); 972 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 973 } 974 975 /* Do we want to advertise 100 Mb Half Duplex? */ 976 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 977 hw_dbg("Advertise 100mb Half duplex\n"); 978 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 979 } 980 981 /* Do we want to advertise 100 Mb Full Duplex? */ 982 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 983 hw_dbg("Advertise 100mb Full duplex\n"); 984 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 985 } 986 987 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 988 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 989 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 990 991 /* Do we want to advertise 1000 Mb Full Duplex? */ 992 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 993 hw_dbg("Advertise 1000mb Full duplex\n"); 994 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 995 } 996 997 /* Check for a software override of the flow control settings, and 998 * setup the PHY advertisement registers accordingly. If 999 * auto-negotiation is enabled, then software will have to set the 1000 * "PAUSE" bits to the correct value in the Auto-Negotiation 1001 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1002 * negotiation. 1003 * 1004 * The possible values of the "fc" parameter are: 1005 * 0: Flow control is completely disabled 1006 * 1: Rx flow control is enabled (we can receive pause frames 1007 * but not send pause frames). 1008 * 2: Tx flow control is enabled (we can send pause frames 1009 * but we do not support receiving pause frames). 1010 * 3: Both Rx and TX flow control (symmetric) are enabled. 1011 * other: No software override. The flow control configuration 1012 * in the EEPROM is used. 1013 */ 1014 switch (hw->fc.current_mode) { 1015 case e1000_fc_none: 1016 /* Flow control (RX & TX) is completely disabled by a 1017 * software over-ride. 1018 */ 1019 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1020 break; 1021 case e1000_fc_rx_pause: 1022 /* RX Flow control is enabled, and TX Flow control is 1023 * disabled, by a software over-ride. 1024 * 1025 * Since there really isn't a way to advertise that we are 1026 * capable of RX Pause ONLY, we will advertise that we 1027 * support both symmetric and asymmetric RX PAUSE. Later 1028 * (in e1000_config_fc_after_link_up) we will disable the 1029 * hw's ability to send PAUSE frames. 1030 */ 1031 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1032 break; 1033 case e1000_fc_tx_pause: 1034 /* TX Flow control is enabled, and RX Flow control is 1035 * disabled, by a software over-ride. 1036 */ 1037 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1038 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1039 break; 1040 case e1000_fc_full: 1041 /* Flow control (both RX and TX) is enabled by a software 1042 * over-ride. 1043 */ 1044 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1045 break; 1046 default: 1047 hw_dbg("Flow control param set incorrectly\n"); 1048 ret_val = -E1000_ERR_CONFIG; 1049 goto out; 1050 } 1051 1052 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1053 if (ret_val) 1054 goto out; 1055 1056 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1057 1058 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1059 ret_val = phy->ops.write_reg(hw, 1060 PHY_1000T_CTRL, 1061 mii_1000t_ctrl_reg); 1062 if (ret_val) 1063 goto out; 1064 } 1065 1066 out: 1067 return ret_val; 1068 } 1069 1070 /** 1071 * igb_setup_copper_link - Configure copper link settings 1072 * @hw: pointer to the HW structure 1073 * 1074 * Calls the appropriate function to configure the link for auto-neg or forced 1075 * speed and duplex. Then we check for link, once link is established calls 1076 * to configure collision distance and flow control are called. If link is 1077 * not established, we return -E1000_ERR_PHY (-2). 1078 **/ 1079 s32 igb_setup_copper_link(struct e1000_hw *hw) 1080 { 1081 s32 ret_val; 1082 bool link; 1083 1084 if (hw->mac.autoneg) { 1085 /* Setup autoneg and flow control advertisement and perform 1086 * autonegotiation. 1087 */ 1088 ret_val = igb_copper_link_autoneg(hw); 1089 if (ret_val) 1090 goto out; 1091 } else { 1092 /* PHY will be set to 10H, 10F, 100H or 100F 1093 * depending on user settings. 1094 */ 1095 hw_dbg("Forcing Speed and Duplex\n"); 1096 ret_val = hw->phy.ops.force_speed_duplex(hw); 1097 if (ret_val) { 1098 hw_dbg("Error Forcing Speed and Duplex\n"); 1099 goto out; 1100 } 1101 } 1102 1103 /* Check link status. Wait up to 100 microseconds for link to become 1104 * valid. 1105 */ 1106 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 1107 if (ret_val) 1108 goto out; 1109 1110 if (link) { 1111 hw_dbg("Valid link established!!!\n"); 1112 igb_config_collision_dist(hw); 1113 ret_val = igb_config_fc_after_link_up(hw); 1114 } else { 1115 hw_dbg("Unable to establish link!!!\n"); 1116 } 1117 1118 out: 1119 return ret_val; 1120 } 1121 1122 /** 1123 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1124 * @hw: pointer to the HW structure 1125 * 1126 * Calls the PHY setup function to force speed and duplex. Clears the 1127 * auto-crossover to force MDI manually. Waits for link and returns 1128 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1129 **/ 1130 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1131 { 1132 struct e1000_phy_info *phy = &hw->phy; 1133 s32 ret_val; 1134 u16 phy_data; 1135 bool link; 1136 1137 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1138 if (ret_val) 1139 goto out; 1140 1141 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1142 1143 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1144 if (ret_val) 1145 goto out; 1146 1147 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1148 * forced whenever speed and duplex are forced. 1149 */ 1150 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1151 if (ret_val) 1152 goto out; 1153 1154 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1155 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1156 1157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1158 if (ret_val) 1159 goto out; 1160 1161 hw_dbg("IGP PSCR: %X\n", phy_data); 1162 1163 udelay(1); 1164 1165 if (phy->autoneg_wait_to_complete) { 1166 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1167 1168 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1169 if (ret_val) 1170 goto out; 1171 1172 if (!link) 1173 hw_dbg("Link taking longer than expected.\n"); 1174 1175 /* Try once more */ 1176 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1177 if (ret_val) 1178 goto out; 1179 } 1180 1181 out: 1182 return ret_val; 1183 } 1184 1185 /** 1186 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1187 * @hw: pointer to the HW structure 1188 * 1189 * Calls the PHY setup function to force speed and duplex. Clears the 1190 * auto-crossover to force MDI manually. Resets the PHY to commit the 1191 * changes. If time expires while waiting for link up, we reset the DSP. 1192 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1193 * successful completion, else return corresponding error code. 1194 **/ 1195 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1196 { 1197 struct e1000_phy_info *phy = &hw->phy; 1198 s32 ret_val; 1199 u16 phy_data; 1200 bool link; 1201 1202 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1203 if (phy->type != e1000_phy_i210) { 1204 /* Clear Auto-Crossover to force MDI manually. M88E1000 1205 * requires MDI forced whenever speed and duplex are forced. 1206 */ 1207 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1208 &phy_data); 1209 if (ret_val) 1210 goto out; 1211 1212 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1213 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1214 phy_data); 1215 if (ret_val) 1216 goto out; 1217 1218 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1219 } 1220 1221 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1222 if (ret_val) 1223 goto out; 1224 1225 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1226 1227 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1228 if (ret_val) 1229 goto out; 1230 1231 /* Reset the phy to commit changes. */ 1232 ret_val = igb_phy_sw_reset(hw); 1233 if (ret_val) 1234 goto out; 1235 1236 if (phy->autoneg_wait_to_complete) { 1237 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1238 1239 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1240 if (ret_val) 1241 goto out; 1242 1243 if (!link) { 1244 bool reset_dsp = true; 1245 1246 switch (hw->phy.id) { 1247 case I347AT4_E_PHY_ID: 1248 case M88E1112_E_PHY_ID: 1249 case M88E1543_E_PHY_ID: 1250 case M88E1512_E_PHY_ID: 1251 case I210_I_PHY_ID: 1252 reset_dsp = false; 1253 break; 1254 default: 1255 if (hw->phy.type != e1000_phy_m88) 1256 reset_dsp = false; 1257 break; 1258 } 1259 if (!reset_dsp) { 1260 hw_dbg("Link taking longer than expected.\n"); 1261 } else { 1262 /* We didn't get link. 1263 * Reset the DSP and cross our fingers. 1264 */ 1265 ret_val = phy->ops.write_reg(hw, 1266 M88E1000_PHY_PAGE_SELECT, 1267 0x001d); 1268 if (ret_val) 1269 goto out; 1270 ret_val = igb_phy_reset_dsp(hw); 1271 if (ret_val) 1272 goto out; 1273 } 1274 } 1275 1276 /* Try once more */ 1277 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1278 100000, &link); 1279 if (ret_val) 1280 goto out; 1281 } 1282 1283 if (hw->phy.type != e1000_phy_m88 || 1284 hw->phy.id == I347AT4_E_PHY_ID || 1285 hw->phy.id == M88E1112_E_PHY_ID || 1286 hw->phy.id == M88E1543_E_PHY_ID || 1287 hw->phy.id == M88E1512_E_PHY_ID || 1288 hw->phy.id == I210_I_PHY_ID) 1289 goto out; 1290 1291 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1292 if (ret_val) 1293 goto out; 1294 1295 /* Resetting the phy means we need to re-force TX_CLK in the 1296 * Extended PHY Specific Control Register to 25MHz clock from 1297 * the reset value of 2.5MHz. 1298 */ 1299 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1300 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1301 if (ret_val) 1302 goto out; 1303 1304 /* In addition, we must re-enable CRS on Tx for both half and full 1305 * duplex. 1306 */ 1307 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1308 if (ret_val) 1309 goto out; 1310 1311 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1312 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1313 1314 out: 1315 return ret_val; 1316 } 1317 1318 /** 1319 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1320 * @hw: pointer to the HW structure 1321 * @phy_ctrl: pointer to current value of PHY_CONTROL 1322 * 1323 * Forces speed and duplex on the PHY by doing the following: disable flow 1324 * control, force speed/duplex on the MAC, disable auto speed detection, 1325 * disable auto-negotiation, configure duplex, configure speed, configure 1326 * the collision distance, write configuration to CTRL register. The 1327 * caller must write to the PHY_CONTROL register for these settings to 1328 * take affect. 1329 **/ 1330 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1331 u16 *phy_ctrl) 1332 { 1333 struct e1000_mac_info *mac = &hw->mac; 1334 u32 ctrl; 1335 1336 /* Turn off flow control when forcing speed/duplex */ 1337 hw->fc.current_mode = e1000_fc_none; 1338 1339 /* Force speed/duplex on the mac */ 1340 ctrl = rd32(E1000_CTRL); 1341 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1342 ctrl &= ~E1000_CTRL_SPD_SEL; 1343 1344 /* Disable Auto Speed Detection */ 1345 ctrl &= ~E1000_CTRL_ASDE; 1346 1347 /* Disable autoneg on the phy */ 1348 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1349 1350 /* Forcing Full or Half Duplex? */ 1351 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1352 ctrl &= ~E1000_CTRL_FD; 1353 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1354 hw_dbg("Half Duplex\n"); 1355 } else { 1356 ctrl |= E1000_CTRL_FD; 1357 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1358 hw_dbg("Full Duplex\n"); 1359 } 1360 1361 /* Forcing 10mb or 100mb? */ 1362 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1363 ctrl |= E1000_CTRL_SPD_100; 1364 *phy_ctrl |= MII_CR_SPEED_100; 1365 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1366 hw_dbg("Forcing 100mb\n"); 1367 } else { 1368 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1369 *phy_ctrl |= MII_CR_SPEED_10; 1370 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1371 hw_dbg("Forcing 10mb\n"); 1372 } 1373 1374 igb_config_collision_dist(hw); 1375 1376 wr32(E1000_CTRL, ctrl); 1377 } 1378 1379 /** 1380 * igb_set_d3_lplu_state - Sets low power link up state for D3 1381 * @hw: pointer to the HW structure 1382 * @active: boolean used to enable/disable lplu 1383 * 1384 * Success returns 0, Failure returns 1 1385 * 1386 * The low power link up (lplu) state is set to the power management level D3 1387 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1388 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1389 * is used during Dx states where the power conservation is most important. 1390 * During driver activity, SmartSpeed should be enabled so performance is 1391 * maintained. 1392 **/ 1393 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1394 { 1395 struct e1000_phy_info *phy = &hw->phy; 1396 s32 ret_val = 0; 1397 u16 data; 1398 1399 if (!(hw->phy.ops.read_reg)) 1400 goto out; 1401 1402 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1403 if (ret_val) 1404 goto out; 1405 1406 if (!active) { 1407 data &= ~IGP02E1000_PM_D3_LPLU; 1408 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1409 data); 1410 if (ret_val) 1411 goto out; 1412 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1413 * during Dx states where the power conservation is most 1414 * important. During driver activity we should enable 1415 * SmartSpeed, so performance is maintained. 1416 */ 1417 if (phy->smart_speed == e1000_smart_speed_on) { 1418 ret_val = phy->ops.read_reg(hw, 1419 IGP01E1000_PHY_PORT_CONFIG, 1420 &data); 1421 if (ret_val) 1422 goto out; 1423 1424 data |= IGP01E1000_PSCFR_SMART_SPEED; 1425 ret_val = phy->ops.write_reg(hw, 1426 IGP01E1000_PHY_PORT_CONFIG, 1427 data); 1428 if (ret_val) 1429 goto out; 1430 } else if (phy->smart_speed == e1000_smart_speed_off) { 1431 ret_val = phy->ops.read_reg(hw, 1432 IGP01E1000_PHY_PORT_CONFIG, 1433 &data); 1434 if (ret_val) 1435 goto out; 1436 1437 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1438 ret_val = phy->ops.write_reg(hw, 1439 IGP01E1000_PHY_PORT_CONFIG, 1440 data); 1441 if (ret_val) 1442 goto out; 1443 } 1444 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1445 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1446 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1447 data |= IGP02E1000_PM_D3_LPLU; 1448 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1449 data); 1450 if (ret_val) 1451 goto out; 1452 1453 /* When LPLU is enabled, we should disable SmartSpeed */ 1454 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1455 &data); 1456 if (ret_val) 1457 goto out; 1458 1459 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1460 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1461 data); 1462 } 1463 1464 out: 1465 return ret_val; 1466 } 1467 1468 /** 1469 * igb_check_downshift - Checks whether a downshift in speed occurred 1470 * @hw: pointer to the HW structure 1471 * 1472 * Success returns 0, Failure returns 1 1473 * 1474 * A downshift is detected by querying the PHY link health. 1475 **/ 1476 s32 igb_check_downshift(struct e1000_hw *hw) 1477 { 1478 struct e1000_phy_info *phy = &hw->phy; 1479 s32 ret_val; 1480 u16 phy_data, offset, mask; 1481 1482 switch (phy->type) { 1483 case e1000_phy_i210: 1484 case e1000_phy_m88: 1485 case e1000_phy_gg82563: 1486 offset = M88E1000_PHY_SPEC_STATUS; 1487 mask = M88E1000_PSSR_DOWNSHIFT; 1488 break; 1489 case e1000_phy_igp_2: 1490 case e1000_phy_igp: 1491 case e1000_phy_igp_3: 1492 offset = IGP01E1000_PHY_LINK_HEALTH; 1493 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1494 break; 1495 default: 1496 /* speed downshift not supported */ 1497 phy->speed_downgraded = false; 1498 ret_val = 0; 1499 goto out; 1500 } 1501 1502 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1503 1504 if (!ret_val) 1505 phy->speed_downgraded = (phy_data & mask) ? true : false; 1506 1507 out: 1508 return ret_val; 1509 } 1510 1511 /** 1512 * igb_check_polarity_m88 - Checks the polarity. 1513 * @hw: pointer to the HW structure 1514 * 1515 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1516 * 1517 * Polarity is determined based on the PHY specific status register. 1518 **/ 1519 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1520 { 1521 struct e1000_phy_info *phy = &hw->phy; 1522 s32 ret_val; 1523 u16 data; 1524 1525 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1526 1527 if (!ret_val) 1528 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1529 ? e1000_rev_polarity_reversed 1530 : e1000_rev_polarity_normal; 1531 1532 return ret_val; 1533 } 1534 1535 /** 1536 * igb_check_polarity_igp - Checks the polarity. 1537 * @hw: pointer to the HW structure 1538 * 1539 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1540 * 1541 * Polarity is determined based on the PHY port status register, and the 1542 * current speed (since there is no polarity at 100Mbps). 1543 **/ 1544 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1545 { 1546 struct e1000_phy_info *phy = &hw->phy; 1547 s32 ret_val; 1548 u16 data, offset, mask; 1549 1550 /* Polarity is determined based on the speed of 1551 * our connection. 1552 */ 1553 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1554 if (ret_val) 1555 goto out; 1556 1557 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1558 IGP01E1000_PSSR_SPEED_1000MBPS) { 1559 offset = IGP01E1000_PHY_PCS_INIT_REG; 1560 mask = IGP01E1000_PHY_POLARITY_MASK; 1561 } else { 1562 /* This really only applies to 10Mbps since 1563 * there is no polarity for 100Mbps (always 0). 1564 */ 1565 offset = IGP01E1000_PHY_PORT_STATUS; 1566 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1567 } 1568 1569 ret_val = phy->ops.read_reg(hw, offset, &data); 1570 1571 if (!ret_val) 1572 phy->cable_polarity = (data & mask) 1573 ? e1000_rev_polarity_reversed 1574 : e1000_rev_polarity_normal; 1575 1576 out: 1577 return ret_val; 1578 } 1579 1580 /** 1581 * igb_wait_autoneg - Wait for auto-neg completion 1582 * @hw: pointer to the HW structure 1583 * 1584 * Waits for auto-negotiation to complete or for the auto-negotiation time 1585 * limit to expire, which ever happens first. 1586 **/ 1587 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1588 { 1589 s32 ret_val = 0; 1590 u16 i, phy_status; 1591 1592 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1593 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1594 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1595 if (ret_val) 1596 break; 1597 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1598 if (ret_val) 1599 break; 1600 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1601 break; 1602 msleep(100); 1603 } 1604 1605 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1606 * has completed. 1607 */ 1608 return ret_val; 1609 } 1610 1611 /** 1612 * igb_phy_has_link - Polls PHY for link 1613 * @hw: pointer to the HW structure 1614 * @iterations: number of times to poll for link 1615 * @usec_interval: delay between polling attempts 1616 * @success: pointer to whether polling was successful or not 1617 * 1618 * Polls the PHY status register for link, 'iterations' number of times. 1619 **/ 1620 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1621 u32 usec_interval, bool *success) 1622 { 1623 s32 ret_val = 0; 1624 u16 i, phy_status; 1625 1626 for (i = 0; i < iterations; i++) { 1627 /* Some PHYs require the PHY_STATUS register to be read 1628 * twice due to the link bit being sticky. No harm doing 1629 * it across the board. 1630 */ 1631 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1632 if (ret_val && usec_interval > 0) { 1633 /* If the first read fails, another entity may have 1634 * ownership of the resources, wait and try again to 1635 * see if they have relinquished the resources yet. 1636 */ 1637 if (usec_interval >= 1000) 1638 mdelay(usec_interval/1000); 1639 else 1640 udelay(usec_interval); 1641 } 1642 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1643 if (ret_val) 1644 break; 1645 if (phy_status & MII_SR_LINK_STATUS) 1646 break; 1647 if (usec_interval >= 1000) 1648 mdelay(usec_interval/1000); 1649 else 1650 udelay(usec_interval); 1651 } 1652 1653 *success = (i < iterations) ? true : false; 1654 1655 return ret_val; 1656 } 1657 1658 /** 1659 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1660 * @hw: pointer to the HW structure 1661 * 1662 * Reads the PHY specific status register to retrieve the cable length 1663 * information. The cable length is determined by averaging the minimum and 1664 * maximum values to get the "average" cable length. The m88 PHY has four 1665 * possible cable length values, which are: 1666 * Register Value Cable Length 1667 * 0 < 50 meters 1668 * 1 50 - 80 meters 1669 * 2 80 - 110 meters 1670 * 3 110 - 140 meters 1671 * 4 > 140 meters 1672 **/ 1673 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1674 { 1675 struct e1000_phy_info *phy = &hw->phy; 1676 s32 ret_val; 1677 u16 phy_data, index; 1678 1679 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1680 if (ret_val) 1681 goto out; 1682 1683 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1684 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1685 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1686 ret_val = -E1000_ERR_PHY; 1687 goto out; 1688 } 1689 1690 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1691 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1692 1693 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1694 1695 out: 1696 return ret_val; 1697 } 1698 1699 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1700 { 1701 struct e1000_phy_info *phy = &hw->phy; 1702 s32 ret_val; 1703 u16 phy_data, phy_data2, index, default_page, is_cm; 1704 int len_tot = 0; 1705 u16 len_min; 1706 u16 len_max; 1707 1708 switch (hw->phy.id) { 1709 case M88E1543_E_PHY_ID: 1710 case M88E1512_E_PHY_ID: 1711 case I347AT4_E_PHY_ID: 1712 case I210_I_PHY_ID: 1713 /* Remember the original page select and set it to 7 */ 1714 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1715 &default_page); 1716 if (ret_val) 1717 goto out; 1718 1719 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1720 if (ret_val) 1721 goto out; 1722 1723 /* Check if the unit of cable length is meters or cm */ 1724 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1725 if (ret_val) 1726 goto out; 1727 1728 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1729 1730 /* Get cable length from Pair 0 length Regs */ 1731 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data); 1732 if (ret_val) 1733 goto out; 1734 1735 phy->pair_length[0] = phy_data / (is_cm ? 100 : 1); 1736 len_tot = phy->pair_length[0]; 1737 len_min = phy->pair_length[0]; 1738 len_max = phy->pair_length[0]; 1739 1740 /* Get cable length from Pair 1 length Regs */ 1741 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data); 1742 if (ret_val) 1743 goto out; 1744 1745 phy->pair_length[1] = phy_data / (is_cm ? 100 : 1); 1746 len_tot += phy->pair_length[1]; 1747 len_min = min(len_min, phy->pair_length[1]); 1748 len_max = max(len_max, phy->pair_length[1]); 1749 1750 /* Get cable length from Pair 2 length Regs */ 1751 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data); 1752 if (ret_val) 1753 goto out; 1754 1755 phy->pair_length[2] = phy_data / (is_cm ? 100 : 1); 1756 len_tot += phy->pair_length[2]; 1757 len_min = min(len_min, phy->pair_length[2]); 1758 len_max = max(len_max, phy->pair_length[2]); 1759 1760 /* Get cable length from Pair 3 length Regs */ 1761 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data); 1762 if (ret_val) 1763 goto out; 1764 1765 phy->pair_length[3] = phy_data / (is_cm ? 100 : 1); 1766 len_tot += phy->pair_length[3]; 1767 len_min = min(len_min, phy->pair_length[3]); 1768 len_max = max(len_max, phy->pair_length[3]); 1769 1770 /* Populate the phy structure with cable length in meters */ 1771 phy->min_cable_length = len_min; 1772 phy->max_cable_length = len_max; 1773 phy->cable_length = len_tot / 4; 1774 1775 /* Reset the page selec to its original value */ 1776 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1777 default_page); 1778 if (ret_val) 1779 goto out; 1780 break; 1781 case M88E1112_E_PHY_ID: 1782 /* Remember the original page select and set it to 5 */ 1783 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1784 &default_page); 1785 if (ret_val) 1786 goto out; 1787 1788 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1789 if (ret_val) 1790 goto out; 1791 1792 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1793 &phy_data); 1794 if (ret_val) 1795 goto out; 1796 1797 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1798 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1799 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1800 ret_val = -E1000_ERR_PHY; 1801 goto out; 1802 } 1803 1804 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1805 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1806 1807 phy->cable_length = (phy->min_cable_length + 1808 phy->max_cable_length) / 2; 1809 1810 /* Reset the page select to its original value */ 1811 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1812 default_page); 1813 if (ret_val) 1814 goto out; 1815 1816 break; 1817 default: 1818 ret_val = -E1000_ERR_PHY; 1819 goto out; 1820 } 1821 1822 out: 1823 return ret_val; 1824 } 1825 1826 /** 1827 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1828 * @hw: pointer to the HW structure 1829 * 1830 * The automatic gain control (agc) normalizes the amplitude of the 1831 * received signal, adjusting for the attenuation produced by the 1832 * cable. By reading the AGC registers, which represent the 1833 * combination of coarse and fine gain value, the value can be put 1834 * into a lookup table to obtain the approximate cable length 1835 * for each channel. 1836 **/ 1837 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1838 { 1839 struct e1000_phy_info *phy = &hw->phy; 1840 s32 ret_val = 0; 1841 u16 phy_data, i, agc_value = 0; 1842 u16 cur_agc_index, max_agc_index = 0; 1843 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1; 1844 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1845 IGP02E1000_PHY_AGC_A, 1846 IGP02E1000_PHY_AGC_B, 1847 IGP02E1000_PHY_AGC_C, 1848 IGP02E1000_PHY_AGC_D 1849 }; 1850 1851 /* Read the AGC registers for all channels */ 1852 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1853 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1854 if (ret_val) 1855 goto out; 1856 1857 /* Getting bits 15:9, which represent the combination of 1858 * coarse and fine gain values. The result is a number 1859 * that can be put into the lookup table to obtain the 1860 * approximate cable length. 1861 */ 1862 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1863 IGP02E1000_AGC_LENGTH_MASK; 1864 1865 /* Array index bound check. */ 1866 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) || 1867 (cur_agc_index == 0)) { 1868 ret_val = -E1000_ERR_PHY; 1869 goto out; 1870 } 1871 1872 /* Remove min & max AGC values from calculation. */ 1873 if (e1000_igp_2_cable_length_table[min_agc_index] > 1874 e1000_igp_2_cable_length_table[cur_agc_index]) 1875 min_agc_index = cur_agc_index; 1876 if (e1000_igp_2_cable_length_table[max_agc_index] < 1877 e1000_igp_2_cable_length_table[cur_agc_index]) 1878 max_agc_index = cur_agc_index; 1879 1880 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1881 } 1882 1883 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1884 e1000_igp_2_cable_length_table[max_agc_index]); 1885 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1886 1887 /* Calculate cable length with the error range of +/- 10 meters. */ 1888 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1889 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1890 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1891 1892 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1893 1894 out: 1895 return ret_val; 1896 } 1897 1898 /** 1899 * igb_get_phy_info_m88 - Retrieve PHY information 1900 * @hw: pointer to the HW structure 1901 * 1902 * Valid for only copper links. Read the PHY status register (sticky read) 1903 * to verify that link is up. Read the PHY special control register to 1904 * determine the polarity and 10base-T extended distance. Read the PHY 1905 * special status register to determine MDI/MDIx and current speed. If 1906 * speed is 1000, then determine cable length, local and remote receiver. 1907 **/ 1908 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1909 { 1910 struct e1000_phy_info *phy = &hw->phy; 1911 s32 ret_val; 1912 u16 phy_data; 1913 bool link; 1914 1915 if (phy->media_type != e1000_media_type_copper) { 1916 hw_dbg("Phy info is only valid for copper media\n"); 1917 ret_val = -E1000_ERR_CONFIG; 1918 goto out; 1919 } 1920 1921 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1922 if (ret_val) 1923 goto out; 1924 1925 if (!link) { 1926 hw_dbg("Phy info is only valid if link is up\n"); 1927 ret_val = -E1000_ERR_CONFIG; 1928 goto out; 1929 } 1930 1931 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1932 if (ret_val) 1933 goto out; 1934 1935 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1936 ? true : false; 1937 1938 ret_val = igb_check_polarity_m88(hw); 1939 if (ret_val) 1940 goto out; 1941 1942 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1943 if (ret_val) 1944 goto out; 1945 1946 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1947 1948 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1949 ret_val = phy->ops.get_cable_length(hw); 1950 if (ret_val) 1951 goto out; 1952 1953 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1954 if (ret_val) 1955 goto out; 1956 1957 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1958 ? e1000_1000t_rx_status_ok 1959 : e1000_1000t_rx_status_not_ok; 1960 1961 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1962 ? e1000_1000t_rx_status_ok 1963 : e1000_1000t_rx_status_not_ok; 1964 } else { 1965 /* Set values to "undefined" */ 1966 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1967 phy->local_rx = e1000_1000t_rx_status_undefined; 1968 phy->remote_rx = e1000_1000t_rx_status_undefined; 1969 } 1970 1971 out: 1972 return ret_val; 1973 } 1974 1975 /** 1976 * igb_get_phy_info_igp - Retrieve igp PHY information 1977 * @hw: pointer to the HW structure 1978 * 1979 * Read PHY status to determine if link is up. If link is up, then 1980 * set/determine 10base-T extended distance and polarity correction. Read 1981 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1982 * determine on the cable length, local and remote receiver. 1983 **/ 1984 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1985 { 1986 struct e1000_phy_info *phy = &hw->phy; 1987 s32 ret_val; 1988 u16 data; 1989 bool link; 1990 1991 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1992 if (ret_val) 1993 goto out; 1994 1995 if (!link) { 1996 hw_dbg("Phy info is only valid if link is up\n"); 1997 ret_val = -E1000_ERR_CONFIG; 1998 goto out; 1999 } 2000 2001 phy->polarity_correction = true; 2002 2003 ret_val = igb_check_polarity_igp(hw); 2004 if (ret_val) 2005 goto out; 2006 2007 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2008 if (ret_val) 2009 goto out; 2010 2011 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2012 2013 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2014 IGP01E1000_PSSR_SPEED_1000MBPS) { 2015 ret_val = phy->ops.get_cable_length(hw); 2016 if (ret_val) 2017 goto out; 2018 2019 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2020 if (ret_val) 2021 goto out; 2022 2023 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2024 ? e1000_1000t_rx_status_ok 2025 : e1000_1000t_rx_status_not_ok; 2026 2027 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2028 ? e1000_1000t_rx_status_ok 2029 : e1000_1000t_rx_status_not_ok; 2030 } else { 2031 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2032 phy->local_rx = e1000_1000t_rx_status_undefined; 2033 phy->remote_rx = e1000_1000t_rx_status_undefined; 2034 } 2035 2036 out: 2037 return ret_val; 2038 } 2039 2040 /** 2041 * igb_phy_sw_reset - PHY software reset 2042 * @hw: pointer to the HW structure 2043 * 2044 * Does a software reset of the PHY by reading the PHY control register and 2045 * setting/write the control register reset bit to the PHY. 2046 **/ 2047 s32 igb_phy_sw_reset(struct e1000_hw *hw) 2048 { 2049 s32 ret_val = 0; 2050 u16 phy_ctrl; 2051 2052 if (!(hw->phy.ops.read_reg)) 2053 goto out; 2054 2055 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2056 if (ret_val) 2057 goto out; 2058 2059 phy_ctrl |= MII_CR_RESET; 2060 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2061 if (ret_val) 2062 goto out; 2063 2064 udelay(1); 2065 2066 out: 2067 return ret_val; 2068 } 2069 2070 /** 2071 * igb_phy_hw_reset - PHY hardware reset 2072 * @hw: pointer to the HW structure 2073 * 2074 * Verify the reset block is not blocking us from resetting. Acquire 2075 * semaphore (if necessary) and read/set/write the device control reset 2076 * bit in the PHY. Wait the appropriate delay time for the device to 2077 * reset and release the semaphore (if necessary). 2078 **/ 2079 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2080 { 2081 struct e1000_phy_info *phy = &hw->phy; 2082 s32 ret_val; 2083 u32 ctrl; 2084 2085 ret_val = igb_check_reset_block(hw); 2086 if (ret_val) { 2087 ret_val = 0; 2088 goto out; 2089 } 2090 2091 ret_val = phy->ops.acquire(hw); 2092 if (ret_val) 2093 goto out; 2094 2095 ctrl = rd32(E1000_CTRL); 2096 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2097 wrfl(); 2098 2099 udelay(phy->reset_delay_us); 2100 2101 wr32(E1000_CTRL, ctrl); 2102 wrfl(); 2103 2104 udelay(150); 2105 2106 phy->ops.release(hw); 2107 2108 ret_val = phy->ops.get_cfg_done(hw); 2109 2110 out: 2111 return ret_val; 2112 } 2113 2114 /** 2115 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2116 * @hw: pointer to the HW structure 2117 * 2118 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2119 **/ 2120 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2121 { 2122 hw_dbg("Running IGP 3 PHY init script\n"); 2123 2124 /* PHY init IGP 3 */ 2125 /* Enable rise/fall, 10-mode work in class-A */ 2126 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2127 /* Remove all caps from Replica path filter */ 2128 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2129 /* Bias trimming for ADC, AFE and Driver (Default) */ 2130 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2131 /* Increase Hybrid poly bias */ 2132 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2133 /* Add 4% to TX amplitude in Giga mode */ 2134 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2135 /* Disable trimming (TTT) */ 2136 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2137 /* Poly DC correction to 94.6% + 2% for all channels */ 2138 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2139 /* ABS DC correction to 95.9% */ 2140 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2141 /* BG temp curve trim */ 2142 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2143 /* Increasing ADC OPAMP stage 1 currents to max */ 2144 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2145 /* Force 1000 ( required for enabling PHY regs configuration) */ 2146 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2147 /* Set upd_freq to 6 */ 2148 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2149 /* Disable NPDFE */ 2150 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2151 /* Disable adaptive fixed FFE (Default) */ 2152 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2153 /* Enable FFE hysteresis */ 2154 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2155 /* Fixed FFE for short cable lengths */ 2156 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2157 /* Fixed FFE for medium cable lengths */ 2158 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2159 /* Fixed FFE for long cable lengths */ 2160 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2161 /* Enable Adaptive Clip Threshold */ 2162 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2163 /* AHT reset limit to 1 */ 2164 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2165 /* Set AHT master delay to 127 msec */ 2166 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2167 /* Set scan bits for AHT */ 2168 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2169 /* Set AHT Preset bits */ 2170 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2171 /* Change integ_factor of channel A to 3 */ 2172 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2173 /* Change prop_factor of channels BCD to 8 */ 2174 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2175 /* Change cg_icount + enable integbp for channels BCD */ 2176 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2177 /* Change cg_icount + enable integbp + change prop_factor_master 2178 * to 8 for channel A 2179 */ 2180 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2181 /* Disable AHT in Slave mode on channel A */ 2182 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2183 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2184 * Enable SPD+B2B 2185 */ 2186 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2187 /* Enable restart AN on an1000_dis change */ 2188 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2189 /* Enable wh_fifo read clock in 10/100 modes */ 2190 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2191 /* Restart AN, Speed selection is 1000 */ 2192 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2193 2194 return 0; 2195 } 2196 2197 /** 2198 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY 2199 * @hw: pointer to the HW structure 2200 * 2201 * Initialize Marvel 1512 to work correctly with Avoton. 2202 **/ 2203 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw) 2204 { 2205 struct e1000_phy_info *phy = &hw->phy; 2206 s32 ret_val = 0; 2207 2208 /* Switch to PHY page 0xFF. */ 2209 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2210 if (ret_val) 2211 goto out; 2212 2213 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2214 if (ret_val) 2215 goto out; 2216 2217 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2218 if (ret_val) 2219 goto out; 2220 2221 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2222 if (ret_val) 2223 goto out; 2224 2225 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2226 if (ret_val) 2227 goto out; 2228 2229 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2230 if (ret_val) 2231 goto out; 2232 2233 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2234 if (ret_val) 2235 goto out; 2236 2237 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2238 if (ret_val) 2239 goto out; 2240 2241 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2242 if (ret_val) 2243 goto out; 2244 2245 /* Switch to PHY page 0xFB. */ 2246 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2247 if (ret_val) 2248 goto out; 2249 2250 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2251 if (ret_val) 2252 goto out; 2253 2254 /* Switch to PHY page 0x12. */ 2255 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2256 if (ret_val) 2257 goto out; 2258 2259 /* Change mode to SGMII-to-Copper */ 2260 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2261 if (ret_val) 2262 goto out; 2263 2264 /* Return the PHY to page 0. */ 2265 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2266 if (ret_val) 2267 goto out; 2268 2269 ret_val = igb_phy_sw_reset(hw); 2270 if (ret_val) { 2271 hw_dbg("Error committing the PHY changes\n"); 2272 return ret_val; 2273 } 2274 2275 /* msec_delay(1000); */ 2276 usleep_range(1000, 2000); 2277 out: 2278 return ret_val; 2279 } 2280 2281 /** 2282 * igb_initialize_M88E1543_phy - Initialize M88E1512 PHY 2283 * @hw: pointer to the HW structure 2284 * 2285 * Initialize Marvell 1543 to work correctly with Avoton. 2286 **/ 2287 s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw) 2288 { 2289 struct e1000_phy_info *phy = &hw->phy; 2290 s32 ret_val = 0; 2291 2292 /* Switch to PHY page 0xFF. */ 2293 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2294 if (ret_val) 2295 goto out; 2296 2297 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2298 if (ret_val) 2299 goto out; 2300 2301 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2302 if (ret_val) 2303 goto out; 2304 2305 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2306 if (ret_val) 2307 goto out; 2308 2309 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2310 if (ret_val) 2311 goto out; 2312 2313 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2314 if (ret_val) 2315 goto out; 2316 2317 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2318 if (ret_val) 2319 goto out; 2320 2321 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); 2322 if (ret_val) 2323 goto out; 2324 2325 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2326 if (ret_val) 2327 goto out; 2328 2329 /* Switch to PHY page 0xFB. */ 2330 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2331 if (ret_val) 2332 goto out; 2333 2334 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D); 2335 if (ret_val) 2336 goto out; 2337 2338 /* Switch to PHY page 0x12. */ 2339 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2340 if (ret_val) 2341 goto out; 2342 2343 /* Change mode to SGMII-to-Copper */ 2344 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2345 if (ret_val) 2346 goto out; 2347 2348 /* Switch to PHY page 1. */ 2349 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); 2350 if (ret_val) 2351 goto out; 2352 2353 /* Change mode to 1000BASE-X/SGMII and autoneg enable */ 2354 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); 2355 if (ret_val) 2356 goto out; 2357 2358 /* Return the PHY to page 0. */ 2359 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2360 if (ret_val) 2361 goto out; 2362 2363 ret_val = igb_phy_sw_reset(hw); 2364 if (ret_val) { 2365 hw_dbg("Error committing the PHY changes\n"); 2366 return ret_val; 2367 } 2368 2369 /* msec_delay(1000); */ 2370 usleep_range(1000, 2000); 2371 out: 2372 return ret_val; 2373 } 2374 2375 /** 2376 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2377 * @hw: pointer to the HW structure 2378 * 2379 * In the case of a PHY power down to save power, or to turn off link during a 2380 * driver unload, restore the link to previous settings. 2381 **/ 2382 void igb_power_up_phy_copper(struct e1000_hw *hw) 2383 { 2384 u16 mii_reg = 0; 2385 2386 /* The PHY will retain its settings across a power down/up cycle */ 2387 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2388 mii_reg &= ~MII_CR_POWER_DOWN; 2389 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2390 } 2391 2392 /** 2393 * igb_power_down_phy_copper - Power down copper PHY 2394 * @hw: pointer to the HW structure 2395 * 2396 * Power down PHY to save power when interface is down and wake on lan 2397 * is not enabled. 2398 **/ 2399 void igb_power_down_phy_copper(struct e1000_hw *hw) 2400 { 2401 u16 mii_reg = 0; 2402 2403 /* The PHY will retain its settings across a power down/up cycle */ 2404 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2405 mii_reg |= MII_CR_POWER_DOWN; 2406 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2407 usleep_range(1000, 2000); 2408 } 2409 2410 /** 2411 * igb_check_polarity_82580 - Checks the polarity. 2412 * @hw: pointer to the HW structure 2413 * 2414 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2415 * 2416 * Polarity is determined based on the PHY specific status register. 2417 **/ 2418 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2419 { 2420 struct e1000_phy_info *phy = &hw->phy; 2421 s32 ret_val; 2422 u16 data; 2423 2424 2425 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2426 2427 if (!ret_val) 2428 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2429 ? e1000_rev_polarity_reversed 2430 : e1000_rev_polarity_normal; 2431 2432 return ret_val; 2433 } 2434 2435 /** 2436 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2437 * @hw: pointer to the HW structure 2438 * 2439 * Calls the PHY setup function to force speed and duplex. Clears the 2440 * auto-crossover to force MDI manually. Waits for link and returns 2441 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2442 **/ 2443 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2444 { 2445 struct e1000_phy_info *phy = &hw->phy; 2446 s32 ret_val; 2447 u16 phy_data; 2448 bool link; 2449 2450 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2451 if (ret_val) 2452 goto out; 2453 2454 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2455 2456 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2457 if (ret_val) 2458 goto out; 2459 2460 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2461 * forced whenever speed and duplex are forced. 2462 */ 2463 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2464 if (ret_val) 2465 goto out; 2466 2467 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2468 2469 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2470 if (ret_val) 2471 goto out; 2472 2473 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2474 2475 udelay(1); 2476 2477 if (phy->autoneg_wait_to_complete) { 2478 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2479 2480 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2481 if (ret_val) 2482 goto out; 2483 2484 if (!link) 2485 hw_dbg("Link taking longer than expected.\n"); 2486 2487 /* Try once more */ 2488 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2489 if (ret_val) 2490 goto out; 2491 } 2492 2493 out: 2494 return ret_val; 2495 } 2496 2497 /** 2498 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2499 * @hw: pointer to the HW structure 2500 * 2501 * Read PHY status to determine if link is up. If link is up, then 2502 * set/determine 10base-T extended distance and polarity correction. Read 2503 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2504 * determine on the cable length, local and remote receiver. 2505 **/ 2506 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2507 { 2508 struct e1000_phy_info *phy = &hw->phy; 2509 s32 ret_val; 2510 u16 data; 2511 bool link; 2512 2513 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2514 if (ret_val) 2515 goto out; 2516 2517 if (!link) { 2518 hw_dbg("Phy info is only valid if link is up\n"); 2519 ret_val = -E1000_ERR_CONFIG; 2520 goto out; 2521 } 2522 2523 phy->polarity_correction = true; 2524 2525 ret_val = igb_check_polarity_82580(hw); 2526 if (ret_val) 2527 goto out; 2528 2529 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2530 if (ret_val) 2531 goto out; 2532 2533 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2534 2535 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2536 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2537 ret_val = hw->phy.ops.get_cable_length(hw); 2538 if (ret_val) 2539 goto out; 2540 2541 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2542 if (ret_val) 2543 goto out; 2544 2545 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2546 ? e1000_1000t_rx_status_ok 2547 : e1000_1000t_rx_status_not_ok; 2548 2549 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2550 ? e1000_1000t_rx_status_ok 2551 : e1000_1000t_rx_status_not_ok; 2552 } else { 2553 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2554 phy->local_rx = e1000_1000t_rx_status_undefined; 2555 phy->remote_rx = e1000_1000t_rx_status_undefined; 2556 } 2557 2558 out: 2559 return ret_val; 2560 } 2561 2562 /** 2563 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2564 * @hw: pointer to the HW structure 2565 * 2566 * Reads the diagnostic status register and verifies result is valid before 2567 * placing it in the phy_cable_length field. 2568 **/ 2569 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2570 { 2571 struct e1000_phy_info *phy = &hw->phy; 2572 s32 ret_val; 2573 u16 phy_data, length; 2574 2575 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2576 if (ret_val) 2577 goto out; 2578 2579 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2580 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2581 2582 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2583 ret_val = -E1000_ERR_PHY; 2584 2585 phy->cable_length = length; 2586 2587 out: 2588 return ret_val; 2589 } 2590 2591 /** 2592 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2593 * @hw: pointer to the HW structure 2594 * 2595 * Sets up Master/slave mode 2596 **/ 2597 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2598 { 2599 s32 ret_val; 2600 u16 phy_data; 2601 2602 /* Resolve Master/Slave mode */ 2603 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2604 if (ret_val) 2605 return ret_val; 2606 2607 /* load defaults for future use */ 2608 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2609 ((phy_data & CR_1000T_MS_VALUE) ? 2610 e1000_ms_force_master : 2611 e1000_ms_force_slave) : e1000_ms_auto; 2612 2613 switch (hw->phy.ms_type) { 2614 case e1000_ms_force_master: 2615 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2616 break; 2617 case e1000_ms_force_slave: 2618 phy_data |= CR_1000T_MS_ENABLE; 2619 phy_data &= ~(CR_1000T_MS_VALUE); 2620 break; 2621 case e1000_ms_auto: 2622 phy_data &= ~CR_1000T_MS_ENABLE; 2623 /* fall-through */ 2624 default: 2625 break; 2626 } 2627 2628 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2629 } 2630