1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/if_ether.h> 29 #include <linux/delay.h> 30 31 #include "e1000_mac.h" 32 #include "e1000_phy.h" 33 34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 36 u16 *phy_ctrl); 37 static s32 igb_wait_autoneg(struct e1000_hw *hw); 38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 39 40 /* Cable length tables */ 41 static const u16 e1000_m88_cable_length_table[] = 42 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof(e1000_m88_cable_length_table) / \ 45 sizeof(e1000_m88_cable_length_table[0])) 46 47 static const u16 e1000_igp_2_cable_length_table[] = 48 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57 (sizeof(e1000_igp_2_cable_length_table) / \ 58 sizeof(e1000_igp_2_cable_length_table[0])) 59 60 /** 61 * igb_check_reset_block - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 igb_check_reset_block(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = rd32(E1000_MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 75 E1000_BLK_PHY_RESET : 0; 76 } 77 78 /** 79 * igb_get_phy_id - Retrieve the PHY ID and revision 80 * @hw: pointer to the HW structure 81 * 82 * Reads the PHY registers and stores the PHY ID and possibly the PHY 83 * revision in the hardware structure. 84 **/ 85 s32 igb_get_phy_id(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = 0; 89 u16 phy_id; 90 91 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 92 if (ret_val) 93 goto out; 94 95 phy->id = (u32)(phy_id << 16); 96 udelay(20); 97 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 98 if (ret_val) 99 goto out; 100 101 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 102 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 103 104 out: 105 return ret_val; 106 } 107 108 /** 109 * igb_phy_reset_dsp - Reset PHY DSP 110 * @hw: pointer to the HW structure 111 * 112 * Reset the digital signal processor. 113 **/ 114 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 115 { 116 s32 ret_val = 0; 117 118 if (!(hw->phy.ops.write_reg)) 119 goto out; 120 121 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 122 if (ret_val) 123 goto out; 124 125 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 126 127 out: 128 return ret_val; 129 } 130 131 /** 132 * igb_read_phy_reg_mdic - Read MDI control register 133 * @hw: pointer to the HW structure 134 * @offset: register offset to be read 135 * @data: pointer to the read data 136 * 137 * Reads the MDI control regsiter in the PHY at offset and stores the 138 * information read to data. 139 **/ 140 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 141 { 142 struct e1000_phy_info *phy = &hw->phy; 143 u32 i, mdic = 0; 144 s32 ret_val = 0; 145 146 if (offset > MAX_PHY_REG_ADDRESS) { 147 hw_dbg("PHY Address %d is out of range\n", offset); 148 ret_val = -E1000_ERR_PARAM; 149 goto out; 150 } 151 152 /* 153 * Set up Op-code, Phy Address, and register offset in the MDI 154 * Control register. The MAC will take care of interfacing with the 155 * PHY to retrieve the desired data. 156 */ 157 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 158 (phy->addr << E1000_MDIC_PHY_SHIFT) | 159 (E1000_MDIC_OP_READ)); 160 161 wr32(E1000_MDIC, mdic); 162 163 /* 164 * Poll the ready bit to see if the MDI read completed 165 * Increasing the time out as testing showed failures with 166 * the lower time out 167 */ 168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 169 udelay(50); 170 mdic = rd32(E1000_MDIC); 171 if (mdic & E1000_MDIC_READY) 172 break; 173 } 174 if (!(mdic & E1000_MDIC_READY)) { 175 hw_dbg("MDI Read did not complete\n"); 176 ret_val = -E1000_ERR_PHY; 177 goto out; 178 } 179 if (mdic & E1000_MDIC_ERROR) { 180 hw_dbg("MDI Error\n"); 181 ret_val = -E1000_ERR_PHY; 182 goto out; 183 } 184 *data = (u16) mdic; 185 186 out: 187 return ret_val; 188 } 189 190 /** 191 * igb_write_phy_reg_mdic - Write MDI control register 192 * @hw: pointer to the HW structure 193 * @offset: register offset to write to 194 * @data: data to write to register at offset 195 * 196 * Writes data to MDI control register in the PHY at offset. 197 **/ 198 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 199 { 200 struct e1000_phy_info *phy = &hw->phy; 201 u32 i, mdic = 0; 202 s32 ret_val = 0; 203 204 if (offset > MAX_PHY_REG_ADDRESS) { 205 hw_dbg("PHY Address %d is out of range\n", offset); 206 ret_val = -E1000_ERR_PARAM; 207 goto out; 208 } 209 210 /* 211 * Set up Op-code, Phy Address, and register offset in the MDI 212 * Control register. The MAC will take care of interfacing with the 213 * PHY to retrieve the desired data. 214 */ 215 mdic = (((u32)data) | 216 (offset << E1000_MDIC_REG_SHIFT) | 217 (phy->addr << E1000_MDIC_PHY_SHIFT) | 218 (E1000_MDIC_OP_WRITE)); 219 220 wr32(E1000_MDIC, mdic); 221 222 /* 223 * Poll the ready bit to see if the MDI read completed 224 * Increasing the time out as testing showed failures with 225 * the lower time out 226 */ 227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 228 udelay(50); 229 mdic = rd32(E1000_MDIC); 230 if (mdic & E1000_MDIC_READY) 231 break; 232 } 233 if (!(mdic & E1000_MDIC_READY)) { 234 hw_dbg("MDI Write did not complete\n"); 235 ret_val = -E1000_ERR_PHY; 236 goto out; 237 } 238 if (mdic & E1000_MDIC_ERROR) { 239 hw_dbg("MDI Error\n"); 240 ret_val = -E1000_ERR_PHY; 241 goto out; 242 } 243 244 out: 245 return ret_val; 246 } 247 248 /** 249 * igb_read_phy_reg_i2c - Read PHY register using i2c 250 * @hw: pointer to the HW structure 251 * @offset: register offset to be read 252 * @data: pointer to the read data 253 * 254 * Reads the PHY register at offset using the i2c interface and stores the 255 * retrieved information in data. 256 **/ 257 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 258 { 259 struct e1000_phy_info *phy = &hw->phy; 260 u32 i, i2ccmd = 0; 261 262 263 /* 264 * Set up Op-code, Phy Address, and register address in the I2CCMD 265 * register. The MAC will take care of interfacing with the 266 * PHY to retrieve the desired data. 267 */ 268 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 269 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 270 (E1000_I2CCMD_OPCODE_READ)); 271 272 wr32(E1000_I2CCMD, i2ccmd); 273 274 /* Poll the ready bit to see if the I2C read completed */ 275 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 276 udelay(50); 277 i2ccmd = rd32(E1000_I2CCMD); 278 if (i2ccmd & E1000_I2CCMD_READY) 279 break; 280 } 281 if (!(i2ccmd & E1000_I2CCMD_READY)) { 282 hw_dbg("I2CCMD Read did not complete\n"); 283 return -E1000_ERR_PHY; 284 } 285 if (i2ccmd & E1000_I2CCMD_ERROR) { 286 hw_dbg("I2CCMD Error bit set\n"); 287 return -E1000_ERR_PHY; 288 } 289 290 /* Need to byte-swap the 16-bit value. */ 291 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 292 293 return 0; 294 } 295 296 /** 297 * igb_write_phy_reg_i2c - Write PHY register using i2c 298 * @hw: pointer to the HW structure 299 * @offset: register offset to write to 300 * @data: data to write at register offset 301 * 302 * Writes the data to PHY register at the offset using the i2c interface. 303 **/ 304 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 305 { 306 struct e1000_phy_info *phy = &hw->phy; 307 u32 i, i2ccmd = 0; 308 u16 phy_data_swapped; 309 310 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 311 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 312 hw_dbg("PHY I2C Address %d is out of range.\n", 313 hw->phy.addr); 314 return -E1000_ERR_CONFIG; 315 } 316 317 /* Swap the data bytes for the I2C interface */ 318 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 319 320 /* 321 * Set up Op-code, Phy Address, and register address in the I2CCMD 322 * register. The MAC will take care of interfacing with the 323 * PHY to retrieve the desired data. 324 */ 325 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 326 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 327 E1000_I2CCMD_OPCODE_WRITE | 328 phy_data_swapped); 329 330 wr32(E1000_I2CCMD, i2ccmd); 331 332 /* Poll the ready bit to see if the I2C read completed */ 333 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 334 udelay(50); 335 i2ccmd = rd32(E1000_I2CCMD); 336 if (i2ccmd & E1000_I2CCMD_READY) 337 break; 338 } 339 if (!(i2ccmd & E1000_I2CCMD_READY)) { 340 hw_dbg("I2CCMD Write did not complete\n"); 341 return -E1000_ERR_PHY; 342 } 343 if (i2ccmd & E1000_I2CCMD_ERROR) { 344 hw_dbg("I2CCMD Error bit set\n"); 345 return -E1000_ERR_PHY; 346 } 347 348 return 0; 349 } 350 351 /** 352 * igb_read_phy_reg_igp - Read igp PHY register 353 * @hw: pointer to the HW structure 354 * @offset: register offset to be read 355 * @data: pointer to the read data 356 * 357 * Acquires semaphore, if necessary, then reads the PHY register at offset 358 * and storing the retrieved information in data. Release any acquired 359 * semaphores before exiting. 360 **/ 361 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 362 { 363 s32 ret_val = 0; 364 365 if (!(hw->phy.ops.acquire)) 366 goto out; 367 368 ret_val = hw->phy.ops.acquire(hw); 369 if (ret_val) 370 goto out; 371 372 if (offset > MAX_PHY_MULTI_PAGE_REG) { 373 ret_val = igb_write_phy_reg_mdic(hw, 374 IGP01E1000_PHY_PAGE_SELECT, 375 (u16)offset); 376 if (ret_val) { 377 hw->phy.ops.release(hw); 378 goto out; 379 } 380 } 381 382 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 383 data); 384 385 hw->phy.ops.release(hw); 386 387 out: 388 return ret_val; 389 } 390 391 /** 392 * igb_write_phy_reg_igp - Write igp PHY register 393 * @hw: pointer to the HW structure 394 * @offset: register offset to write to 395 * @data: data to write at register offset 396 * 397 * Acquires semaphore, if necessary, then writes the data to PHY register 398 * at the offset. Release any acquired semaphores before exiting. 399 **/ 400 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 401 { 402 s32 ret_val = 0; 403 404 if (!(hw->phy.ops.acquire)) 405 goto out; 406 407 ret_val = hw->phy.ops.acquire(hw); 408 if (ret_val) 409 goto out; 410 411 if (offset > MAX_PHY_MULTI_PAGE_REG) { 412 ret_val = igb_write_phy_reg_mdic(hw, 413 IGP01E1000_PHY_PAGE_SELECT, 414 (u16)offset); 415 if (ret_val) { 416 hw->phy.ops.release(hw); 417 goto out; 418 } 419 } 420 421 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 422 data); 423 424 hw->phy.ops.release(hw); 425 426 out: 427 return ret_val; 428 } 429 430 /** 431 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 432 * @hw: pointer to the HW structure 433 * 434 * Sets up Carrier-sense on Transmit and downshift values. 435 **/ 436 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 437 { 438 struct e1000_phy_info *phy = &hw->phy; 439 s32 ret_val; 440 u16 phy_data; 441 442 443 if (phy->reset_disable) { 444 ret_val = 0; 445 goto out; 446 } 447 448 if (phy->type == e1000_phy_82580) { 449 ret_val = hw->phy.ops.reset(hw); 450 if (ret_val) { 451 hw_dbg("Error resetting the PHY.\n"); 452 goto out; 453 } 454 } 455 456 /* Enable CRS on TX. This must be set for half-duplex operation. */ 457 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 458 if (ret_val) 459 goto out; 460 461 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 462 463 /* Enable downshift */ 464 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 465 466 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 467 if (ret_val) 468 goto out; 469 470 /* Set MDI/MDIX mode */ 471 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 472 if (ret_val) 473 goto out; 474 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 475 /* 476 * Options: 477 * 0 - Auto (default) 478 * 1 - MDI mode 479 * 2 - MDI-X mode 480 */ 481 switch (hw->phy.mdix) { 482 case 1: 483 break; 484 case 2: 485 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 486 break; 487 case 0: 488 default: 489 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 490 break; 491 } 492 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 493 494 out: 495 return ret_val; 496 } 497 498 /** 499 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 500 * @hw: pointer to the HW structure 501 * 502 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 503 * and downshift values are set also. 504 **/ 505 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 506 { 507 struct e1000_phy_info *phy = &hw->phy; 508 s32 ret_val; 509 u16 phy_data; 510 511 if (phy->reset_disable) { 512 ret_val = 0; 513 goto out; 514 } 515 516 /* Enable CRS on TX. This must be set for half-duplex operation. */ 517 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 518 if (ret_val) 519 goto out; 520 521 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 522 523 /* 524 * Options: 525 * MDI/MDI-X = 0 (default) 526 * 0 - Auto for all speeds 527 * 1 - MDI mode 528 * 2 - MDI-X mode 529 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 530 */ 531 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 532 533 switch (phy->mdix) { 534 case 1: 535 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 536 break; 537 case 2: 538 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 539 break; 540 case 3: 541 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 542 break; 543 case 0: 544 default: 545 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 546 break; 547 } 548 549 /* 550 * Options: 551 * disable_polarity_correction = 0 (default) 552 * Automatic Correction for Reversed Cable Polarity 553 * 0 - Disabled 554 * 1 - Enabled 555 */ 556 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 557 if (phy->disable_polarity_correction == 1) 558 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 559 560 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 561 if (ret_val) 562 goto out; 563 564 if (phy->revision < E1000_REVISION_4) { 565 /* 566 * Force TX_CLK in the Extended PHY Specific Control Register 567 * to 25MHz clock. 568 */ 569 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 570 &phy_data); 571 if (ret_val) 572 goto out; 573 574 phy_data |= M88E1000_EPSCR_TX_CLK_25; 575 576 if ((phy->revision == E1000_REVISION_2) && 577 (phy->id == M88E1111_I_PHY_ID)) { 578 /* 82573L PHY - set the downshift counter to 5x. */ 579 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 580 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 581 } else { 582 /* Configure Master and Slave downshift values */ 583 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 584 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 585 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 586 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 587 } 588 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 589 phy_data); 590 if (ret_val) 591 goto out; 592 } 593 594 /* Commit the changes. */ 595 ret_val = igb_phy_sw_reset(hw); 596 if (ret_val) { 597 hw_dbg("Error committing the PHY changes\n"); 598 goto out; 599 } 600 if (phy->type == e1000_phy_i210) { 601 ret_val = igb_set_master_slave_mode(hw); 602 if (ret_val) 603 return ret_val; 604 } 605 606 out: 607 return ret_val; 608 } 609 610 /** 611 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 612 * @hw: pointer to the HW structure 613 * 614 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 615 * Also enables and sets the downshift parameters. 616 **/ 617 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 618 { 619 struct e1000_phy_info *phy = &hw->phy; 620 s32 ret_val; 621 u16 phy_data; 622 623 if (phy->reset_disable) { 624 ret_val = 0; 625 goto out; 626 } 627 628 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 629 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 630 if (ret_val) 631 goto out; 632 633 /* 634 * Options: 635 * MDI/MDI-X = 0 (default) 636 * 0 - Auto for all speeds 637 * 1 - MDI mode 638 * 2 - MDI-X mode 639 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 640 */ 641 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 642 643 switch (phy->mdix) { 644 case 1: 645 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 646 break; 647 case 2: 648 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 649 break; 650 case 3: 651 /* M88E1112 does not support this mode) */ 652 if (phy->id != M88E1112_E_PHY_ID) { 653 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 654 break; 655 } 656 case 0: 657 default: 658 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 659 break; 660 } 661 662 /* 663 * Options: 664 * disable_polarity_correction = 0 (default) 665 * Automatic Correction for Reversed Cable Polarity 666 * 0 - Disabled 667 * 1 - Enabled 668 */ 669 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 670 if (phy->disable_polarity_correction == 1) 671 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 672 673 /* Enable downshift and setting it to X6 */ 674 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 675 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 676 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 677 678 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 679 if (ret_val) 680 goto out; 681 682 /* Commit the changes. */ 683 ret_val = igb_phy_sw_reset(hw); 684 if (ret_val) { 685 hw_dbg("Error committing the PHY changes\n"); 686 goto out; 687 } 688 689 out: 690 return ret_val; 691 } 692 693 /** 694 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 695 * @hw: pointer to the HW structure 696 * 697 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 698 * igp PHY's. 699 **/ 700 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 701 { 702 struct e1000_phy_info *phy = &hw->phy; 703 s32 ret_val; 704 u16 data; 705 706 if (phy->reset_disable) { 707 ret_val = 0; 708 goto out; 709 } 710 711 ret_val = phy->ops.reset(hw); 712 if (ret_val) { 713 hw_dbg("Error resetting the PHY.\n"); 714 goto out; 715 } 716 717 /* 718 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 719 * timeout issues when LFS is enabled. 720 */ 721 msleep(100); 722 723 /* 724 * The NVM settings will configure LPLU in D3 for 725 * non-IGP1 PHYs. 726 */ 727 if (phy->type == e1000_phy_igp) { 728 /* disable lplu d3 during driver init */ 729 if (phy->ops.set_d3_lplu_state) 730 ret_val = phy->ops.set_d3_lplu_state(hw, false); 731 if (ret_val) { 732 hw_dbg("Error Disabling LPLU D3\n"); 733 goto out; 734 } 735 } 736 737 /* disable lplu d0 during driver init */ 738 ret_val = phy->ops.set_d0_lplu_state(hw, false); 739 if (ret_val) { 740 hw_dbg("Error Disabling LPLU D0\n"); 741 goto out; 742 } 743 /* Configure mdi-mdix settings */ 744 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 745 if (ret_val) 746 goto out; 747 748 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 749 750 switch (phy->mdix) { 751 case 1: 752 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 753 break; 754 case 2: 755 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 756 break; 757 case 0: 758 default: 759 data |= IGP01E1000_PSCR_AUTO_MDIX; 760 break; 761 } 762 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 763 if (ret_val) 764 goto out; 765 766 /* set auto-master slave resolution settings */ 767 if (hw->mac.autoneg) { 768 /* 769 * when autonegotiation advertisement is only 1000Mbps then we 770 * should disable SmartSpeed and enable Auto MasterSlave 771 * resolution as hardware default. 772 */ 773 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 774 /* Disable SmartSpeed */ 775 ret_val = phy->ops.read_reg(hw, 776 IGP01E1000_PHY_PORT_CONFIG, 777 &data); 778 if (ret_val) 779 goto out; 780 781 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 782 ret_val = phy->ops.write_reg(hw, 783 IGP01E1000_PHY_PORT_CONFIG, 784 data); 785 if (ret_val) 786 goto out; 787 788 /* Set auto Master/Slave resolution process */ 789 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 790 if (ret_val) 791 goto out; 792 793 data &= ~CR_1000T_MS_ENABLE; 794 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 795 if (ret_val) 796 goto out; 797 } 798 799 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 800 if (ret_val) 801 goto out; 802 803 /* load defaults for future use */ 804 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 805 ((data & CR_1000T_MS_VALUE) ? 806 e1000_ms_force_master : 807 e1000_ms_force_slave) : 808 e1000_ms_auto; 809 810 switch (phy->ms_type) { 811 case e1000_ms_force_master: 812 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 813 break; 814 case e1000_ms_force_slave: 815 data |= CR_1000T_MS_ENABLE; 816 data &= ~(CR_1000T_MS_VALUE); 817 break; 818 case e1000_ms_auto: 819 data &= ~CR_1000T_MS_ENABLE; 820 default: 821 break; 822 } 823 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 824 if (ret_val) 825 goto out; 826 } 827 828 out: 829 return ret_val; 830 } 831 832 /** 833 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 834 * @hw: pointer to the HW structure 835 * 836 * Performs initial bounds checking on autoneg advertisement parameter, then 837 * configure to advertise the full capability. Setup the PHY to autoneg 838 * and restart the negotiation process between the link partner. If 839 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 840 **/ 841 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 842 { 843 struct e1000_phy_info *phy = &hw->phy; 844 s32 ret_val; 845 u16 phy_ctrl; 846 847 /* 848 * Perform some bounds checking on the autoneg advertisement 849 * parameter. 850 */ 851 phy->autoneg_advertised &= phy->autoneg_mask; 852 853 /* 854 * If autoneg_advertised is zero, we assume it was not defaulted 855 * by the calling code so we set to advertise full capability. 856 */ 857 if (phy->autoneg_advertised == 0) 858 phy->autoneg_advertised = phy->autoneg_mask; 859 860 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 861 ret_val = igb_phy_setup_autoneg(hw); 862 if (ret_val) { 863 hw_dbg("Error Setting up Auto-Negotiation\n"); 864 goto out; 865 } 866 hw_dbg("Restarting Auto-Neg\n"); 867 868 /* 869 * Restart auto-negotiation by setting the Auto Neg Enable bit and 870 * the Auto Neg Restart bit in the PHY control register. 871 */ 872 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 873 if (ret_val) 874 goto out; 875 876 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 877 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 878 if (ret_val) 879 goto out; 880 881 /* 882 * Does the user want to wait for Auto-Neg to complete here, or 883 * check at a later time (for example, callback routine). 884 */ 885 if (phy->autoneg_wait_to_complete) { 886 ret_val = igb_wait_autoneg(hw); 887 if (ret_val) { 888 hw_dbg("Error while waiting for " 889 "autoneg to complete\n"); 890 goto out; 891 } 892 } 893 894 hw->mac.get_link_status = true; 895 896 out: 897 return ret_val; 898 } 899 900 /** 901 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 902 * @hw: pointer to the HW structure 903 * 904 * Reads the MII auto-neg advertisement register and/or the 1000T control 905 * register and if the PHY is already setup for auto-negotiation, then 906 * return successful. Otherwise, setup advertisement and flow control to 907 * the appropriate values for the wanted auto-negotiation. 908 **/ 909 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 910 { 911 struct e1000_phy_info *phy = &hw->phy; 912 s32 ret_val; 913 u16 mii_autoneg_adv_reg; 914 u16 mii_1000t_ctrl_reg = 0; 915 916 phy->autoneg_advertised &= phy->autoneg_mask; 917 918 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 919 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 920 if (ret_val) 921 goto out; 922 923 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 924 /* Read the MII 1000Base-T Control Register (Address 9). */ 925 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 926 &mii_1000t_ctrl_reg); 927 if (ret_val) 928 goto out; 929 } 930 931 /* 932 * Need to parse both autoneg_advertised and fc and set up 933 * the appropriate PHY registers. First we will parse for 934 * autoneg_advertised software override. Since we can advertise 935 * a plethora of combinations, we need to check each bit 936 * individually. 937 */ 938 939 /* 940 * First we clear all the 10/100 mb speed bits in the Auto-Neg 941 * Advertisement Register (Address 4) and the 1000 mb speed bits in 942 * the 1000Base-T Control Register (Address 9). 943 */ 944 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 945 NWAY_AR_100TX_HD_CAPS | 946 NWAY_AR_10T_FD_CAPS | 947 NWAY_AR_10T_HD_CAPS); 948 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 949 950 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 951 952 /* Do we want to advertise 10 Mb Half Duplex? */ 953 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 954 hw_dbg("Advertise 10mb Half duplex\n"); 955 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 956 } 957 958 /* Do we want to advertise 10 Mb Full Duplex? */ 959 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 960 hw_dbg("Advertise 10mb Full duplex\n"); 961 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 962 } 963 964 /* Do we want to advertise 100 Mb Half Duplex? */ 965 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 966 hw_dbg("Advertise 100mb Half duplex\n"); 967 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 968 } 969 970 /* Do we want to advertise 100 Mb Full Duplex? */ 971 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 972 hw_dbg("Advertise 100mb Full duplex\n"); 973 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 974 } 975 976 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 977 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 978 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 979 980 /* Do we want to advertise 1000 Mb Full Duplex? */ 981 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 982 hw_dbg("Advertise 1000mb Full duplex\n"); 983 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 984 } 985 986 /* 987 * Check for a software override of the flow control settings, and 988 * setup the PHY advertisement registers accordingly. If 989 * auto-negotiation is enabled, then software will have to set the 990 * "PAUSE" bits to the correct value in the Auto-Negotiation 991 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 992 * negotiation. 993 * 994 * The possible values of the "fc" parameter are: 995 * 0: Flow control is completely disabled 996 * 1: Rx flow control is enabled (we can receive pause frames 997 * but not send pause frames). 998 * 2: Tx flow control is enabled (we can send pause frames 999 * but we do not support receiving pause frames). 1000 * 3: Both Rx and TX flow control (symmetric) are enabled. 1001 * other: No software override. The flow control configuration 1002 * in the EEPROM is used. 1003 */ 1004 switch (hw->fc.current_mode) { 1005 case e1000_fc_none: 1006 /* 1007 * Flow control (RX & TX) is completely disabled by a 1008 * software over-ride. 1009 */ 1010 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1011 break; 1012 case e1000_fc_rx_pause: 1013 /* 1014 * RX Flow control is enabled, and TX Flow control is 1015 * disabled, by a software over-ride. 1016 * 1017 * Since there really isn't a way to advertise that we are 1018 * capable of RX Pause ONLY, we will advertise that we 1019 * support both symmetric and asymmetric RX PAUSE. Later 1020 * (in e1000_config_fc_after_link_up) we will disable the 1021 * hw's ability to send PAUSE frames. 1022 */ 1023 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1024 break; 1025 case e1000_fc_tx_pause: 1026 /* 1027 * TX Flow control is enabled, and RX Flow control is 1028 * disabled, by a software over-ride. 1029 */ 1030 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1031 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1032 break; 1033 case e1000_fc_full: 1034 /* 1035 * Flow control (both RX and TX) is enabled by a software 1036 * over-ride. 1037 */ 1038 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1039 break; 1040 default: 1041 hw_dbg("Flow control param set incorrectly\n"); 1042 ret_val = -E1000_ERR_CONFIG; 1043 goto out; 1044 } 1045 1046 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1047 if (ret_val) 1048 goto out; 1049 1050 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1051 1052 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1053 ret_val = phy->ops.write_reg(hw, 1054 PHY_1000T_CTRL, 1055 mii_1000t_ctrl_reg); 1056 if (ret_val) 1057 goto out; 1058 } 1059 1060 out: 1061 return ret_val; 1062 } 1063 1064 /** 1065 * igb_setup_copper_link - Configure copper link settings 1066 * @hw: pointer to the HW structure 1067 * 1068 * Calls the appropriate function to configure the link for auto-neg or forced 1069 * speed and duplex. Then we check for link, once link is established calls 1070 * to configure collision distance and flow control are called. If link is 1071 * not established, we return -E1000_ERR_PHY (-2). 1072 **/ 1073 s32 igb_setup_copper_link(struct e1000_hw *hw) 1074 { 1075 s32 ret_val; 1076 bool link; 1077 1078 1079 if (hw->mac.autoneg) { 1080 /* 1081 * Setup autoneg and flow control advertisement and perform 1082 * autonegotiation. 1083 */ 1084 ret_val = igb_copper_link_autoneg(hw); 1085 if (ret_val) 1086 goto out; 1087 } else { 1088 /* 1089 * PHY will be set to 10H, 10F, 100H or 100F 1090 * depending on user settings. 1091 */ 1092 hw_dbg("Forcing Speed and Duplex\n"); 1093 ret_val = hw->phy.ops.force_speed_duplex(hw); 1094 if (ret_val) { 1095 hw_dbg("Error Forcing Speed and Duplex\n"); 1096 goto out; 1097 } 1098 } 1099 1100 /* 1101 * Check link status. Wait up to 100 microseconds for link to become 1102 * valid. 1103 */ 1104 ret_val = igb_phy_has_link(hw, 1105 COPPER_LINK_UP_LIMIT, 1106 10, 1107 &link); 1108 if (ret_val) 1109 goto out; 1110 1111 if (link) { 1112 hw_dbg("Valid link established!!!\n"); 1113 igb_config_collision_dist(hw); 1114 ret_val = igb_config_fc_after_link_up(hw); 1115 } else { 1116 hw_dbg("Unable to establish link!!!\n"); 1117 } 1118 1119 out: 1120 return ret_val; 1121 } 1122 1123 /** 1124 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1125 * @hw: pointer to the HW structure 1126 * 1127 * Calls the PHY setup function to force speed and duplex. Clears the 1128 * auto-crossover to force MDI manually. Waits for link and returns 1129 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1130 **/ 1131 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1132 { 1133 struct e1000_phy_info *phy = &hw->phy; 1134 s32 ret_val; 1135 u16 phy_data; 1136 bool link; 1137 1138 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1139 if (ret_val) 1140 goto out; 1141 1142 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1143 1144 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1145 if (ret_val) 1146 goto out; 1147 1148 /* 1149 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1150 * forced whenever speed and duplex are forced. 1151 */ 1152 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1153 if (ret_val) 1154 goto out; 1155 1156 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1157 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1158 1159 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1160 if (ret_val) 1161 goto out; 1162 1163 hw_dbg("IGP PSCR: %X\n", phy_data); 1164 1165 udelay(1); 1166 1167 if (phy->autoneg_wait_to_complete) { 1168 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1169 1170 ret_val = igb_phy_has_link(hw, 1171 PHY_FORCE_LIMIT, 1172 100000, 1173 &link); 1174 if (ret_val) 1175 goto out; 1176 1177 if (!link) 1178 hw_dbg("Link taking longer than expected.\n"); 1179 1180 /* Try once more */ 1181 ret_val = igb_phy_has_link(hw, 1182 PHY_FORCE_LIMIT, 1183 100000, 1184 &link); 1185 if (ret_val) 1186 goto out; 1187 } 1188 1189 out: 1190 return ret_val; 1191 } 1192 1193 /** 1194 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1195 * @hw: pointer to the HW structure 1196 * 1197 * Calls the PHY setup function to force speed and duplex. Clears the 1198 * auto-crossover to force MDI manually. Resets the PHY to commit the 1199 * changes. If time expires while waiting for link up, we reset the DSP. 1200 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1201 * successful completion, else return corresponding error code. 1202 **/ 1203 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1204 { 1205 struct e1000_phy_info *phy = &hw->phy; 1206 s32 ret_val; 1207 u16 phy_data; 1208 bool link; 1209 1210 /* 1211 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1212 * forced whenever speed and duplex are forced. 1213 */ 1214 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1215 if (ret_val) 1216 goto out; 1217 1218 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1219 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1220 if (ret_val) 1221 goto out; 1222 1223 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1224 1225 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1226 if (ret_val) 1227 goto out; 1228 1229 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1230 1231 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1232 if (ret_val) 1233 goto out; 1234 1235 /* Reset the phy to commit changes. */ 1236 ret_val = igb_phy_sw_reset(hw); 1237 if (ret_val) 1238 goto out; 1239 1240 if (phy->autoneg_wait_to_complete) { 1241 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1242 1243 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1244 if (ret_val) 1245 goto out; 1246 1247 if (!link) { 1248 bool reset_dsp = true; 1249 1250 switch (hw->phy.id) { 1251 case I347AT4_E_PHY_ID: 1252 case M88E1112_E_PHY_ID: 1253 case I210_I_PHY_ID: 1254 reset_dsp = false; 1255 break; 1256 default: 1257 if (hw->phy.type != e1000_phy_m88) 1258 reset_dsp = false; 1259 break; 1260 } 1261 if (!reset_dsp) 1262 hw_dbg("Link taking longer than expected.\n"); 1263 else { 1264 /* 1265 * We didn't get link. 1266 * Reset the DSP and cross our fingers. 1267 */ 1268 ret_val = phy->ops.write_reg(hw, 1269 M88E1000_PHY_PAGE_SELECT, 1270 0x001d); 1271 if (ret_val) 1272 goto out; 1273 ret_val = igb_phy_reset_dsp(hw); 1274 if (ret_val) 1275 goto out; 1276 } 1277 } 1278 1279 /* Try once more */ 1280 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1281 100000, &link); 1282 if (ret_val) 1283 goto out; 1284 } 1285 1286 if (hw->phy.type != e1000_phy_m88 || 1287 hw->phy.id == I347AT4_E_PHY_ID || 1288 hw->phy.id == M88E1112_E_PHY_ID || 1289 hw->phy.id == I210_I_PHY_ID) 1290 goto out; 1291 1292 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1293 if (ret_val) 1294 goto out; 1295 1296 /* 1297 * Resetting the phy means we need to re-force TX_CLK in the 1298 * Extended PHY Specific Control Register to 25MHz clock from 1299 * the reset value of 2.5MHz. 1300 */ 1301 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1302 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1303 if (ret_val) 1304 goto out; 1305 1306 /* 1307 * In addition, we must re-enable CRS on Tx for both half and full 1308 * duplex. 1309 */ 1310 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1311 if (ret_val) 1312 goto out; 1313 1314 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1315 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1316 1317 out: 1318 return ret_val; 1319 } 1320 1321 /** 1322 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1323 * @hw: pointer to the HW structure 1324 * @phy_ctrl: pointer to current value of PHY_CONTROL 1325 * 1326 * Forces speed and duplex on the PHY by doing the following: disable flow 1327 * control, force speed/duplex on the MAC, disable auto speed detection, 1328 * disable auto-negotiation, configure duplex, configure speed, configure 1329 * the collision distance, write configuration to CTRL register. The 1330 * caller must write to the PHY_CONTROL register for these settings to 1331 * take affect. 1332 **/ 1333 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1334 u16 *phy_ctrl) 1335 { 1336 struct e1000_mac_info *mac = &hw->mac; 1337 u32 ctrl; 1338 1339 /* Turn off flow control when forcing speed/duplex */ 1340 hw->fc.current_mode = e1000_fc_none; 1341 1342 /* Force speed/duplex on the mac */ 1343 ctrl = rd32(E1000_CTRL); 1344 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1345 ctrl &= ~E1000_CTRL_SPD_SEL; 1346 1347 /* Disable Auto Speed Detection */ 1348 ctrl &= ~E1000_CTRL_ASDE; 1349 1350 /* Disable autoneg on the phy */ 1351 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1352 1353 /* Forcing Full or Half Duplex? */ 1354 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1355 ctrl &= ~E1000_CTRL_FD; 1356 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1357 hw_dbg("Half Duplex\n"); 1358 } else { 1359 ctrl |= E1000_CTRL_FD; 1360 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1361 hw_dbg("Full Duplex\n"); 1362 } 1363 1364 /* Forcing 10mb or 100mb? */ 1365 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1366 ctrl |= E1000_CTRL_SPD_100; 1367 *phy_ctrl |= MII_CR_SPEED_100; 1368 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1369 hw_dbg("Forcing 100mb\n"); 1370 } else { 1371 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1372 *phy_ctrl |= MII_CR_SPEED_10; 1373 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1374 hw_dbg("Forcing 10mb\n"); 1375 } 1376 1377 igb_config_collision_dist(hw); 1378 1379 wr32(E1000_CTRL, ctrl); 1380 } 1381 1382 /** 1383 * igb_set_d3_lplu_state - Sets low power link up state for D3 1384 * @hw: pointer to the HW structure 1385 * @active: boolean used to enable/disable lplu 1386 * 1387 * Success returns 0, Failure returns 1 1388 * 1389 * The low power link up (lplu) state is set to the power management level D3 1390 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1391 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1392 * is used during Dx states where the power conservation is most important. 1393 * During driver activity, SmartSpeed should be enabled so performance is 1394 * maintained. 1395 **/ 1396 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1397 { 1398 struct e1000_phy_info *phy = &hw->phy; 1399 s32 ret_val = 0; 1400 u16 data; 1401 1402 if (!(hw->phy.ops.read_reg)) 1403 goto out; 1404 1405 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1406 if (ret_val) 1407 goto out; 1408 1409 if (!active) { 1410 data &= ~IGP02E1000_PM_D3_LPLU; 1411 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1412 data); 1413 if (ret_val) 1414 goto out; 1415 /* 1416 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1417 * during Dx states where the power conservation is most 1418 * important. During driver activity we should enable 1419 * SmartSpeed, so performance is maintained. 1420 */ 1421 if (phy->smart_speed == e1000_smart_speed_on) { 1422 ret_val = phy->ops.read_reg(hw, 1423 IGP01E1000_PHY_PORT_CONFIG, 1424 &data); 1425 if (ret_val) 1426 goto out; 1427 1428 data |= IGP01E1000_PSCFR_SMART_SPEED; 1429 ret_val = phy->ops.write_reg(hw, 1430 IGP01E1000_PHY_PORT_CONFIG, 1431 data); 1432 if (ret_val) 1433 goto out; 1434 } else if (phy->smart_speed == e1000_smart_speed_off) { 1435 ret_val = phy->ops.read_reg(hw, 1436 IGP01E1000_PHY_PORT_CONFIG, 1437 &data); 1438 if (ret_val) 1439 goto out; 1440 1441 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1442 ret_val = phy->ops.write_reg(hw, 1443 IGP01E1000_PHY_PORT_CONFIG, 1444 data); 1445 if (ret_val) 1446 goto out; 1447 } 1448 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1449 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1450 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1451 data |= IGP02E1000_PM_D3_LPLU; 1452 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1453 data); 1454 if (ret_val) 1455 goto out; 1456 1457 /* When LPLU is enabled, we should disable SmartSpeed */ 1458 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1459 &data); 1460 if (ret_val) 1461 goto out; 1462 1463 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1464 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1465 data); 1466 } 1467 1468 out: 1469 return ret_val; 1470 } 1471 1472 /** 1473 * igb_check_downshift - Checks whether a downshift in speed occurred 1474 * @hw: pointer to the HW structure 1475 * 1476 * Success returns 0, Failure returns 1 1477 * 1478 * A downshift is detected by querying the PHY link health. 1479 **/ 1480 s32 igb_check_downshift(struct e1000_hw *hw) 1481 { 1482 struct e1000_phy_info *phy = &hw->phy; 1483 s32 ret_val; 1484 u16 phy_data, offset, mask; 1485 1486 switch (phy->type) { 1487 case e1000_phy_i210: 1488 case e1000_phy_m88: 1489 case e1000_phy_gg82563: 1490 offset = M88E1000_PHY_SPEC_STATUS; 1491 mask = M88E1000_PSSR_DOWNSHIFT; 1492 break; 1493 case e1000_phy_igp_2: 1494 case e1000_phy_igp: 1495 case e1000_phy_igp_3: 1496 offset = IGP01E1000_PHY_LINK_HEALTH; 1497 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1498 break; 1499 default: 1500 /* speed downshift not supported */ 1501 phy->speed_downgraded = false; 1502 ret_val = 0; 1503 goto out; 1504 } 1505 1506 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1507 1508 if (!ret_val) 1509 phy->speed_downgraded = (phy_data & mask) ? true : false; 1510 1511 out: 1512 return ret_val; 1513 } 1514 1515 /** 1516 * igb_check_polarity_m88 - Checks the polarity. 1517 * @hw: pointer to the HW structure 1518 * 1519 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1520 * 1521 * Polarity is determined based on the PHY specific status register. 1522 **/ 1523 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1524 { 1525 struct e1000_phy_info *phy = &hw->phy; 1526 s32 ret_val; 1527 u16 data; 1528 1529 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1530 1531 if (!ret_val) 1532 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1533 ? e1000_rev_polarity_reversed 1534 : e1000_rev_polarity_normal; 1535 1536 return ret_val; 1537 } 1538 1539 /** 1540 * igb_check_polarity_igp - Checks the polarity. 1541 * @hw: pointer to the HW structure 1542 * 1543 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1544 * 1545 * Polarity is determined based on the PHY port status register, and the 1546 * current speed (since there is no polarity at 100Mbps). 1547 **/ 1548 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1549 { 1550 struct e1000_phy_info *phy = &hw->phy; 1551 s32 ret_val; 1552 u16 data, offset, mask; 1553 1554 /* 1555 * Polarity is determined based on the speed of 1556 * our connection. 1557 */ 1558 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1559 if (ret_val) 1560 goto out; 1561 1562 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1563 IGP01E1000_PSSR_SPEED_1000MBPS) { 1564 offset = IGP01E1000_PHY_PCS_INIT_REG; 1565 mask = IGP01E1000_PHY_POLARITY_MASK; 1566 } else { 1567 /* 1568 * This really only applies to 10Mbps since 1569 * there is no polarity for 100Mbps (always 0). 1570 */ 1571 offset = IGP01E1000_PHY_PORT_STATUS; 1572 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1573 } 1574 1575 ret_val = phy->ops.read_reg(hw, offset, &data); 1576 1577 if (!ret_val) 1578 phy->cable_polarity = (data & mask) 1579 ? e1000_rev_polarity_reversed 1580 : e1000_rev_polarity_normal; 1581 1582 out: 1583 return ret_val; 1584 } 1585 1586 /** 1587 * igb_wait_autoneg - Wait for auto-neg compeletion 1588 * @hw: pointer to the HW structure 1589 * 1590 * Waits for auto-negotiation to complete or for the auto-negotiation time 1591 * limit to expire, which ever happens first. 1592 **/ 1593 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1594 { 1595 s32 ret_val = 0; 1596 u16 i, phy_status; 1597 1598 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1599 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1600 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1601 if (ret_val) 1602 break; 1603 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1604 if (ret_val) 1605 break; 1606 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1607 break; 1608 msleep(100); 1609 } 1610 1611 /* 1612 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1613 * has completed. 1614 */ 1615 return ret_val; 1616 } 1617 1618 /** 1619 * igb_phy_has_link - Polls PHY for link 1620 * @hw: pointer to the HW structure 1621 * @iterations: number of times to poll for link 1622 * @usec_interval: delay between polling attempts 1623 * @success: pointer to whether polling was successful or not 1624 * 1625 * Polls the PHY status register for link, 'iterations' number of times. 1626 **/ 1627 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1628 u32 usec_interval, bool *success) 1629 { 1630 s32 ret_val = 0; 1631 u16 i, phy_status; 1632 1633 for (i = 0; i < iterations; i++) { 1634 /* 1635 * Some PHYs require the PHY_STATUS register to be read 1636 * twice due to the link bit being sticky. No harm doing 1637 * it across the board. 1638 */ 1639 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1640 if (ret_val) { 1641 /* 1642 * If the first read fails, another entity may have 1643 * ownership of the resources, wait and try again to 1644 * see if they have relinquished the resources yet. 1645 */ 1646 udelay(usec_interval); 1647 } 1648 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1649 if (ret_val) 1650 break; 1651 if (phy_status & MII_SR_LINK_STATUS) 1652 break; 1653 if (usec_interval >= 1000) 1654 mdelay(usec_interval/1000); 1655 else 1656 udelay(usec_interval); 1657 } 1658 1659 *success = (i < iterations) ? true : false; 1660 1661 return ret_val; 1662 } 1663 1664 /** 1665 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1666 * @hw: pointer to the HW structure 1667 * 1668 * Reads the PHY specific status register to retrieve the cable length 1669 * information. The cable length is determined by averaging the minimum and 1670 * maximum values to get the "average" cable length. The m88 PHY has four 1671 * possible cable length values, which are: 1672 * Register Value Cable Length 1673 * 0 < 50 meters 1674 * 1 50 - 80 meters 1675 * 2 80 - 110 meters 1676 * 3 110 - 140 meters 1677 * 4 > 140 meters 1678 **/ 1679 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1680 { 1681 struct e1000_phy_info *phy = &hw->phy; 1682 s32 ret_val; 1683 u16 phy_data, index; 1684 1685 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1686 if (ret_val) 1687 goto out; 1688 1689 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1690 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1691 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1692 ret_val = -E1000_ERR_PHY; 1693 goto out; 1694 } 1695 1696 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1697 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1698 1699 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1700 1701 out: 1702 return ret_val; 1703 } 1704 1705 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1706 { 1707 struct e1000_phy_info *phy = &hw->phy; 1708 s32 ret_val; 1709 u16 phy_data, phy_data2, index, default_page, is_cm; 1710 1711 switch (hw->phy.id) { 1712 case I210_I_PHY_ID: 1713 case I347AT4_E_PHY_ID: 1714 /* Remember the original page select and set it to 7 */ 1715 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1716 &default_page); 1717 if (ret_val) 1718 goto out; 1719 1720 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1721 if (ret_val) 1722 goto out; 1723 1724 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1725 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1726 &phy_data); 1727 if (ret_val) 1728 goto out; 1729 1730 /* Check if the unit of cable length is meters or cm */ 1731 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1732 if (ret_val) 1733 goto out; 1734 1735 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1736 1737 /* Populate the phy structure with cable length in meters */ 1738 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1739 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1740 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1741 1742 /* Reset the page selec to its original value */ 1743 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1744 default_page); 1745 if (ret_val) 1746 goto out; 1747 break; 1748 case M88E1112_E_PHY_ID: 1749 /* Remember the original page select and set it to 5 */ 1750 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1751 &default_page); 1752 if (ret_val) 1753 goto out; 1754 1755 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1756 if (ret_val) 1757 goto out; 1758 1759 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1760 &phy_data); 1761 if (ret_val) 1762 goto out; 1763 1764 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1765 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1766 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1767 ret_val = -E1000_ERR_PHY; 1768 goto out; 1769 } 1770 1771 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1772 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1773 1774 phy->cable_length = (phy->min_cable_length + 1775 phy->max_cable_length) / 2; 1776 1777 /* Reset the page select to its original value */ 1778 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1779 default_page); 1780 if (ret_val) 1781 goto out; 1782 1783 break; 1784 default: 1785 ret_val = -E1000_ERR_PHY; 1786 goto out; 1787 } 1788 1789 out: 1790 return ret_val; 1791 } 1792 1793 /** 1794 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1795 * @hw: pointer to the HW structure 1796 * 1797 * The automatic gain control (agc) normalizes the amplitude of the 1798 * received signal, adjusting for the attenuation produced by the 1799 * cable. By reading the AGC registers, which represent the 1800 * combination of coarse and fine gain value, the value can be put 1801 * into a lookup table to obtain the approximate cable length 1802 * for each channel. 1803 **/ 1804 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1805 { 1806 struct e1000_phy_info *phy = &hw->phy; 1807 s32 ret_val = 0; 1808 u16 phy_data, i, agc_value = 0; 1809 u16 cur_agc_index, max_agc_index = 0; 1810 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1811 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1812 IGP02E1000_PHY_AGC_A, 1813 IGP02E1000_PHY_AGC_B, 1814 IGP02E1000_PHY_AGC_C, 1815 IGP02E1000_PHY_AGC_D 1816 }; 1817 1818 /* Read the AGC registers for all channels */ 1819 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1820 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1821 if (ret_val) 1822 goto out; 1823 1824 /* 1825 * Getting bits 15:9, which represent the combination of 1826 * coarse and fine gain values. The result is a number 1827 * that can be put into the lookup table to obtain the 1828 * approximate cable length. 1829 */ 1830 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1831 IGP02E1000_AGC_LENGTH_MASK; 1832 1833 /* Array index bound check. */ 1834 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1835 (cur_agc_index == 0)) { 1836 ret_val = -E1000_ERR_PHY; 1837 goto out; 1838 } 1839 1840 /* Remove min & max AGC values from calculation. */ 1841 if (e1000_igp_2_cable_length_table[min_agc_index] > 1842 e1000_igp_2_cable_length_table[cur_agc_index]) 1843 min_agc_index = cur_agc_index; 1844 if (e1000_igp_2_cable_length_table[max_agc_index] < 1845 e1000_igp_2_cable_length_table[cur_agc_index]) 1846 max_agc_index = cur_agc_index; 1847 1848 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1849 } 1850 1851 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1852 e1000_igp_2_cable_length_table[max_agc_index]); 1853 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1854 1855 /* Calculate cable length with the error range of +/- 10 meters. */ 1856 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1857 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1858 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1859 1860 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1861 1862 out: 1863 return ret_val; 1864 } 1865 1866 /** 1867 * igb_get_phy_info_m88 - Retrieve PHY information 1868 * @hw: pointer to the HW structure 1869 * 1870 * Valid for only copper links. Read the PHY status register (sticky read) 1871 * to verify that link is up. Read the PHY special control register to 1872 * determine the polarity and 10base-T extended distance. Read the PHY 1873 * special status register to determine MDI/MDIx and current speed. If 1874 * speed is 1000, then determine cable length, local and remote receiver. 1875 **/ 1876 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1877 { 1878 struct e1000_phy_info *phy = &hw->phy; 1879 s32 ret_val; 1880 u16 phy_data; 1881 bool link; 1882 1883 if (phy->media_type != e1000_media_type_copper) { 1884 hw_dbg("Phy info is only valid for copper media\n"); 1885 ret_val = -E1000_ERR_CONFIG; 1886 goto out; 1887 } 1888 1889 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1890 if (ret_val) 1891 goto out; 1892 1893 if (!link) { 1894 hw_dbg("Phy info is only valid if link is up\n"); 1895 ret_val = -E1000_ERR_CONFIG; 1896 goto out; 1897 } 1898 1899 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1900 if (ret_val) 1901 goto out; 1902 1903 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1904 ? true : false; 1905 1906 ret_val = igb_check_polarity_m88(hw); 1907 if (ret_val) 1908 goto out; 1909 1910 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1911 if (ret_val) 1912 goto out; 1913 1914 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1915 1916 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1917 ret_val = phy->ops.get_cable_length(hw); 1918 if (ret_val) 1919 goto out; 1920 1921 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1922 if (ret_val) 1923 goto out; 1924 1925 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1926 ? e1000_1000t_rx_status_ok 1927 : e1000_1000t_rx_status_not_ok; 1928 1929 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1930 ? e1000_1000t_rx_status_ok 1931 : e1000_1000t_rx_status_not_ok; 1932 } else { 1933 /* Set values to "undefined" */ 1934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1935 phy->local_rx = e1000_1000t_rx_status_undefined; 1936 phy->remote_rx = e1000_1000t_rx_status_undefined; 1937 } 1938 1939 out: 1940 return ret_val; 1941 } 1942 1943 /** 1944 * igb_get_phy_info_igp - Retrieve igp PHY information 1945 * @hw: pointer to the HW structure 1946 * 1947 * Read PHY status to determine if link is up. If link is up, then 1948 * set/determine 10base-T extended distance and polarity correction. Read 1949 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1950 * determine on the cable length, local and remote receiver. 1951 **/ 1952 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1953 { 1954 struct e1000_phy_info *phy = &hw->phy; 1955 s32 ret_val; 1956 u16 data; 1957 bool link; 1958 1959 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1960 if (ret_val) 1961 goto out; 1962 1963 if (!link) { 1964 hw_dbg("Phy info is only valid if link is up\n"); 1965 ret_val = -E1000_ERR_CONFIG; 1966 goto out; 1967 } 1968 1969 phy->polarity_correction = true; 1970 1971 ret_val = igb_check_polarity_igp(hw); 1972 if (ret_val) 1973 goto out; 1974 1975 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1976 if (ret_val) 1977 goto out; 1978 1979 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 1980 1981 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1982 IGP01E1000_PSSR_SPEED_1000MBPS) { 1983 ret_val = phy->ops.get_cable_length(hw); 1984 if (ret_val) 1985 goto out; 1986 1987 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 1988 if (ret_val) 1989 goto out; 1990 1991 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1992 ? e1000_1000t_rx_status_ok 1993 : e1000_1000t_rx_status_not_ok; 1994 1995 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1996 ? e1000_1000t_rx_status_ok 1997 : e1000_1000t_rx_status_not_ok; 1998 } else { 1999 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2000 phy->local_rx = e1000_1000t_rx_status_undefined; 2001 phy->remote_rx = e1000_1000t_rx_status_undefined; 2002 } 2003 2004 out: 2005 return ret_val; 2006 } 2007 2008 /** 2009 * igb_phy_sw_reset - PHY software reset 2010 * @hw: pointer to the HW structure 2011 * 2012 * Does a software reset of the PHY by reading the PHY control register and 2013 * setting/write the control register reset bit to the PHY. 2014 **/ 2015 s32 igb_phy_sw_reset(struct e1000_hw *hw) 2016 { 2017 s32 ret_val = 0; 2018 u16 phy_ctrl; 2019 2020 if (!(hw->phy.ops.read_reg)) 2021 goto out; 2022 2023 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2024 if (ret_val) 2025 goto out; 2026 2027 phy_ctrl |= MII_CR_RESET; 2028 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2029 if (ret_val) 2030 goto out; 2031 2032 udelay(1); 2033 2034 out: 2035 return ret_val; 2036 } 2037 2038 /** 2039 * igb_phy_hw_reset - PHY hardware reset 2040 * @hw: pointer to the HW structure 2041 * 2042 * Verify the reset block is not blocking us from resetting. Acquire 2043 * semaphore (if necessary) and read/set/write the device control reset 2044 * bit in the PHY. Wait the appropriate delay time for the device to 2045 * reset and relase the semaphore (if necessary). 2046 **/ 2047 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2048 { 2049 struct e1000_phy_info *phy = &hw->phy; 2050 s32 ret_val; 2051 u32 ctrl; 2052 2053 ret_val = igb_check_reset_block(hw); 2054 if (ret_val) { 2055 ret_val = 0; 2056 goto out; 2057 } 2058 2059 ret_val = phy->ops.acquire(hw); 2060 if (ret_val) 2061 goto out; 2062 2063 ctrl = rd32(E1000_CTRL); 2064 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2065 wrfl(); 2066 2067 udelay(phy->reset_delay_us); 2068 2069 wr32(E1000_CTRL, ctrl); 2070 wrfl(); 2071 2072 udelay(150); 2073 2074 phy->ops.release(hw); 2075 2076 ret_val = phy->ops.get_cfg_done(hw); 2077 2078 out: 2079 return ret_val; 2080 } 2081 2082 /** 2083 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2084 * @hw: pointer to the HW structure 2085 * 2086 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2087 **/ 2088 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2089 { 2090 hw_dbg("Running IGP 3 PHY init script\n"); 2091 2092 /* PHY init IGP 3 */ 2093 /* Enable rise/fall, 10-mode work in class-A */ 2094 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2095 /* Remove all caps from Replica path filter */ 2096 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2097 /* Bias trimming for ADC, AFE and Driver (Default) */ 2098 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2099 /* Increase Hybrid poly bias */ 2100 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2101 /* Add 4% to TX amplitude in Giga mode */ 2102 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2103 /* Disable trimming (TTT) */ 2104 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2105 /* Poly DC correction to 94.6% + 2% for all channels */ 2106 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2107 /* ABS DC correction to 95.9% */ 2108 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2109 /* BG temp curve trim */ 2110 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2111 /* Increasing ADC OPAMP stage 1 currents to max */ 2112 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2113 /* Force 1000 ( required for enabling PHY regs configuration) */ 2114 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2115 /* Set upd_freq to 6 */ 2116 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2117 /* Disable NPDFE */ 2118 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2119 /* Disable adaptive fixed FFE (Default) */ 2120 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2121 /* Enable FFE hysteresis */ 2122 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2123 /* Fixed FFE for short cable lengths */ 2124 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2125 /* Fixed FFE for medium cable lengths */ 2126 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2127 /* Fixed FFE for long cable lengths */ 2128 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2129 /* Enable Adaptive Clip Threshold */ 2130 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2131 /* AHT reset limit to 1 */ 2132 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2133 /* Set AHT master delay to 127 msec */ 2134 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2135 /* Set scan bits for AHT */ 2136 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2137 /* Set AHT Preset bits */ 2138 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2139 /* Change integ_factor of channel A to 3 */ 2140 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2141 /* Change prop_factor of channels BCD to 8 */ 2142 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2143 /* Change cg_icount + enable integbp for channels BCD */ 2144 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2145 /* 2146 * Change cg_icount + enable integbp + change prop_factor_master 2147 * to 8 for channel A 2148 */ 2149 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2150 /* Disable AHT in Slave mode on channel A */ 2151 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2152 /* 2153 * Enable LPLU and disable AN to 1000 in non-D0a states, 2154 * Enable SPD+B2B 2155 */ 2156 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2157 /* Enable restart AN on an1000_dis change */ 2158 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2159 /* Enable wh_fifo read clock in 10/100 modes */ 2160 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2161 /* Restart AN, Speed selection is 1000 */ 2162 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2163 2164 return 0; 2165 } 2166 2167 /** 2168 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2169 * @hw: pointer to the HW structure 2170 * 2171 * In the case of a PHY power down to save power, or to turn off link during a 2172 * driver unload, restore the link to previous settings. 2173 **/ 2174 void igb_power_up_phy_copper(struct e1000_hw *hw) 2175 { 2176 u16 mii_reg = 0; 2177 u16 power_reg = 0; 2178 2179 /* The PHY will retain its settings across a power down/up cycle */ 2180 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2181 mii_reg &= ~MII_CR_POWER_DOWN; 2182 if (hw->phy.type == e1000_phy_i210) { 2183 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2184 power_reg &= ~GS40G_CS_POWER_DOWN; 2185 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2186 } 2187 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2188 } 2189 2190 /** 2191 * igb_power_down_phy_copper - Power down copper PHY 2192 * @hw: pointer to the HW structure 2193 * 2194 * Power down PHY to save power when interface is down and wake on lan 2195 * is not enabled. 2196 **/ 2197 void igb_power_down_phy_copper(struct e1000_hw *hw) 2198 { 2199 u16 mii_reg = 0; 2200 u16 power_reg = 0; 2201 2202 /* The PHY will retain its settings across a power down/up cycle */ 2203 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2204 mii_reg |= MII_CR_POWER_DOWN; 2205 2206 /* i210 Phy requires an additional bit for power up/down */ 2207 if (hw->phy.type == e1000_phy_i210) { 2208 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2209 power_reg |= GS40G_CS_POWER_DOWN; 2210 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2211 } 2212 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2213 msleep(1); 2214 } 2215 2216 /** 2217 * igb_check_polarity_82580 - Checks the polarity. 2218 * @hw: pointer to the HW structure 2219 * 2220 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2221 * 2222 * Polarity is determined based on the PHY specific status register. 2223 **/ 2224 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2225 { 2226 struct e1000_phy_info *phy = &hw->phy; 2227 s32 ret_val; 2228 u16 data; 2229 2230 2231 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2232 2233 if (!ret_val) 2234 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2235 ? e1000_rev_polarity_reversed 2236 : e1000_rev_polarity_normal; 2237 2238 return ret_val; 2239 } 2240 2241 /** 2242 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2243 * @hw: pointer to the HW structure 2244 * 2245 * Calls the PHY setup function to force speed and duplex. Clears the 2246 * auto-crossover to force MDI manually. Waits for link and returns 2247 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2248 **/ 2249 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2250 { 2251 struct e1000_phy_info *phy = &hw->phy; 2252 s32 ret_val; 2253 u16 phy_data; 2254 bool link; 2255 2256 2257 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2258 if (ret_val) 2259 goto out; 2260 2261 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2262 2263 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2264 if (ret_val) 2265 goto out; 2266 2267 /* 2268 * Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2269 * forced whenever speed and duplex are forced. 2270 */ 2271 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2272 if (ret_val) 2273 goto out; 2274 2275 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2276 2277 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2278 if (ret_val) 2279 goto out; 2280 2281 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2282 2283 udelay(1); 2284 2285 if (phy->autoneg_wait_to_complete) { 2286 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2287 2288 ret_val = igb_phy_has_link(hw, 2289 PHY_FORCE_LIMIT, 2290 100000, 2291 &link); 2292 if (ret_val) 2293 goto out; 2294 2295 if (!link) 2296 hw_dbg("Link taking longer than expected.\n"); 2297 2298 /* Try once more */ 2299 ret_val = igb_phy_has_link(hw, 2300 PHY_FORCE_LIMIT, 2301 100000, 2302 &link); 2303 if (ret_val) 2304 goto out; 2305 } 2306 2307 out: 2308 return ret_val; 2309 } 2310 2311 /** 2312 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2313 * @hw: pointer to the HW structure 2314 * 2315 * Read PHY status to determine if link is up. If link is up, then 2316 * set/determine 10base-T extended distance and polarity correction. Read 2317 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2318 * determine on the cable length, local and remote receiver. 2319 **/ 2320 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2321 { 2322 struct e1000_phy_info *phy = &hw->phy; 2323 s32 ret_val; 2324 u16 data; 2325 bool link; 2326 2327 2328 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2329 if (ret_val) 2330 goto out; 2331 2332 if (!link) { 2333 hw_dbg("Phy info is only valid if link is up\n"); 2334 ret_val = -E1000_ERR_CONFIG; 2335 goto out; 2336 } 2337 2338 phy->polarity_correction = true; 2339 2340 ret_val = igb_check_polarity_82580(hw); 2341 if (ret_val) 2342 goto out; 2343 2344 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2345 if (ret_val) 2346 goto out; 2347 2348 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2349 2350 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2351 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2352 ret_val = hw->phy.ops.get_cable_length(hw); 2353 if (ret_val) 2354 goto out; 2355 2356 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2357 if (ret_val) 2358 goto out; 2359 2360 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2361 ? e1000_1000t_rx_status_ok 2362 : e1000_1000t_rx_status_not_ok; 2363 2364 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2365 ? e1000_1000t_rx_status_ok 2366 : e1000_1000t_rx_status_not_ok; 2367 } else { 2368 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2369 phy->local_rx = e1000_1000t_rx_status_undefined; 2370 phy->remote_rx = e1000_1000t_rx_status_undefined; 2371 } 2372 2373 out: 2374 return ret_val; 2375 } 2376 2377 /** 2378 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2379 * @hw: pointer to the HW structure 2380 * 2381 * Reads the diagnostic status register and verifies result is valid before 2382 * placing it in the phy_cable_length field. 2383 **/ 2384 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2385 { 2386 struct e1000_phy_info *phy = &hw->phy; 2387 s32 ret_val; 2388 u16 phy_data, length; 2389 2390 2391 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2392 if (ret_val) 2393 goto out; 2394 2395 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2396 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2397 2398 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2399 ret_val = -E1000_ERR_PHY; 2400 2401 phy->cable_length = length; 2402 2403 out: 2404 return ret_val; 2405 } 2406 2407 /** 2408 * igb_write_phy_reg_gs40g - Write GS40G PHY register 2409 * @hw: pointer to the HW structure 2410 * @offset: lower half is register offset to write to 2411 * upper half is page to use. 2412 * @data: data to write at register offset 2413 * 2414 * Acquires semaphore, if necessary, then writes the data to PHY register 2415 * at the offset. Release any acquired semaphores before exiting. 2416 **/ 2417 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 2418 { 2419 s32 ret_val; 2420 u16 page = offset >> GS40G_PAGE_SHIFT; 2421 2422 offset = offset & GS40G_OFFSET_MASK; 2423 ret_val = hw->phy.ops.acquire(hw); 2424 if (ret_val) 2425 return ret_val; 2426 2427 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2428 if (ret_val) 2429 goto release; 2430 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2431 2432 release: 2433 hw->phy.ops.release(hw); 2434 return ret_val; 2435 } 2436 2437 /** 2438 * igb_read_phy_reg_gs40g - Read GS40G PHY register 2439 * @hw: pointer to the HW structure 2440 * @offset: lower half is register offset to read to 2441 * upper half is page to use. 2442 * @data: data to read at register offset 2443 * 2444 * Acquires semaphore, if necessary, then reads the data in the PHY register 2445 * at the offset. Release any acquired semaphores before exiting. 2446 **/ 2447 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 2448 { 2449 s32 ret_val; 2450 u16 page = offset >> GS40G_PAGE_SHIFT; 2451 2452 offset = offset & GS40G_OFFSET_MASK; 2453 ret_val = hw->phy.ops.acquire(hw); 2454 if (ret_val) 2455 return ret_val; 2456 2457 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2458 if (ret_val) 2459 goto release; 2460 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2461 2462 release: 2463 hw->phy.ops.release(hw); 2464 return ret_val; 2465 } 2466 2467 /** 2468 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2469 * @hw: pointer to the HW structure 2470 * 2471 * Sets up Master/slave mode 2472 **/ 2473 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2474 { 2475 s32 ret_val; 2476 u16 phy_data; 2477 2478 /* Resolve Master/Slave mode */ 2479 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2480 if (ret_val) 2481 return ret_val; 2482 2483 /* load defaults for future use */ 2484 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2485 ((phy_data & CR_1000T_MS_VALUE) ? 2486 e1000_ms_force_master : 2487 e1000_ms_force_slave) : e1000_ms_auto; 2488 2489 switch (hw->phy.ms_type) { 2490 case e1000_ms_force_master: 2491 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2492 break; 2493 case e1000_ms_force_slave: 2494 phy_data |= CR_1000T_MS_ENABLE; 2495 phy_data &= ~(CR_1000T_MS_VALUE); 2496 break; 2497 case e1000_ms_auto: 2498 phy_data &= ~CR_1000T_MS_ENABLE; 2499 /* fall-through */ 2500 default: 2501 break; 2502 } 2503 2504 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2505 } 2506