1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #include "idpf.h" 5 #include "idpf_ptp.h" 6 #include "idpf_virtchnl.h" 7 #include "xdp.h" 8 9 #define idpf_tx_buf_next(buf) (*(u32 *)&(buf)->priv) 10 LIBETH_SQE_CHECK_PRIV(u32); 11 12 /** 13 * idpf_chk_linearize - Check if skb exceeds max descriptors per packet 14 * @skb: send buffer 15 * @max_bufs: maximum scatter gather buffers for single packet 16 * @count: number of buffers this packet needs 17 * 18 * Make sure we don't exceed maximum scatter gather buffers for a single 19 * packet. 20 * TSO case has been handled earlier from idpf_features_check(). 21 */ 22 static bool idpf_chk_linearize(const struct sk_buff *skb, 23 unsigned int max_bufs, 24 unsigned int count) 25 { 26 if (likely(count <= max_bufs)) 27 return false; 28 29 if (skb_is_gso(skb)) 30 return false; 31 32 return true; 33 } 34 35 /** 36 * idpf_tx_timeout - Respond to a Tx Hang 37 * @netdev: network interface device structure 38 * @txqueue: TX queue 39 */ 40 void idpf_tx_timeout(struct net_device *netdev, unsigned int txqueue) 41 { 42 struct idpf_adapter *adapter = idpf_netdev_to_adapter(netdev); 43 44 adapter->tx_timeout_count++; 45 46 netdev_err(netdev, "Detected Tx timeout: Count %d, Queue %d\n", 47 adapter->tx_timeout_count, txqueue); 48 if (!idpf_is_reset_in_prog(adapter)) { 49 set_bit(IDPF_HR_FUNC_RESET, adapter->flags); 50 queue_delayed_work(adapter->vc_event_wq, 51 &adapter->vc_event_task, 52 msecs_to_jiffies(10)); 53 } 54 } 55 56 /** 57 * idpf_tx_buf_rel_all - Free any empty Tx buffers 58 * @txq: queue to be cleaned 59 */ 60 static void idpf_tx_buf_rel_all(struct idpf_tx_queue *txq) 61 { 62 struct libeth_sq_napi_stats ss = { }; 63 struct xdp_frame_bulk bq; 64 struct libeth_cq_pp cp = { 65 .dev = txq->dev, 66 .bq = &bq, 67 .ss = &ss, 68 }; 69 u32 i; 70 71 /* Buffers already cleared, nothing to do */ 72 if (!txq->tx_buf) 73 return; 74 75 xdp_frame_bulk_init(&bq); 76 77 /* Free all the Tx buffer sk_buffs */ 78 for (i = 0; i < txq->buf_pool_size; i++) 79 libeth_tx_complete_any(&txq->tx_buf[i], &cp); 80 81 xdp_flush_frame_bulk(&bq); 82 83 kfree(txq->tx_buf); 84 txq->tx_buf = NULL; 85 } 86 87 /** 88 * idpf_tx_desc_rel - Free Tx resources per queue 89 * @txq: Tx descriptor ring for a specific queue 90 * 91 * Free all transmit software resources 92 */ 93 static void idpf_tx_desc_rel(struct idpf_tx_queue *txq) 94 { 95 bool xdp = idpf_queue_has(XDP, txq); 96 97 if (xdp) 98 libeth_xdpsq_deinit_timer(txq->timer); 99 100 idpf_tx_buf_rel_all(txq); 101 102 if (!xdp) 103 netdev_tx_reset_subqueue(txq->netdev, txq->idx); 104 105 if (!txq->desc_ring) 106 return; 107 108 if (!xdp && txq->refillq) 109 kfree(txq->refillq->ring); 110 111 dmam_free_coherent(txq->dev, txq->size, txq->desc_ring, txq->dma); 112 txq->desc_ring = NULL; 113 txq->next_to_use = 0; 114 txq->next_to_clean = 0; 115 } 116 117 /** 118 * idpf_compl_desc_rel - Free completion resources per queue 119 * @complq: completion queue 120 * 121 * Free all completion software resources. 122 */ 123 static void idpf_compl_desc_rel(struct idpf_compl_queue *complq) 124 { 125 if (!complq->comp) 126 return; 127 128 dma_free_coherent(complq->netdev->dev.parent, complq->size, 129 complq->desc_ring, complq->dma); 130 complq->desc_ring = NULL; 131 complq->next_to_use = 0; 132 complq->next_to_clean = 0; 133 } 134 135 /** 136 * idpf_tx_desc_rel_all - Free Tx Resources for All Queues 137 * @vport: virtual port structure 138 * 139 * Free all transmit software resources 140 */ 141 static void idpf_tx_desc_rel_all(struct idpf_vport *vport) 142 { 143 int i, j; 144 145 if (!vport->txq_grps) 146 return; 147 148 for (i = 0; i < vport->num_txq_grp; i++) { 149 struct idpf_txq_group *txq_grp = &vport->txq_grps[i]; 150 151 for (j = 0; j < txq_grp->num_txq; j++) 152 idpf_tx_desc_rel(txq_grp->txqs[j]); 153 154 if (idpf_is_queue_model_split(vport->txq_model)) 155 idpf_compl_desc_rel(txq_grp->complq); 156 } 157 } 158 159 /** 160 * idpf_tx_buf_alloc_all - Allocate memory for all buffer resources 161 * @tx_q: queue for which the buffers are allocated 162 * 163 * Returns 0 on success, negative on failure 164 */ 165 static int idpf_tx_buf_alloc_all(struct idpf_tx_queue *tx_q) 166 { 167 /* Allocate book keeping buffers only. Buffers to be supplied to HW 168 * are allocated by kernel network stack and received as part of skb 169 */ 170 if (idpf_queue_has(FLOW_SCH_EN, tx_q)) 171 tx_q->buf_pool_size = U16_MAX; 172 else 173 tx_q->buf_pool_size = tx_q->desc_count; 174 tx_q->tx_buf = kcalloc(tx_q->buf_pool_size, sizeof(*tx_q->tx_buf), 175 GFP_KERNEL); 176 if (!tx_q->tx_buf) 177 return -ENOMEM; 178 179 return 0; 180 } 181 182 /** 183 * idpf_tx_desc_alloc - Allocate the Tx descriptors 184 * @vport: vport to allocate resources for 185 * @tx_q: the tx ring to set up 186 * 187 * Returns 0 on success, negative on failure 188 */ 189 static int idpf_tx_desc_alloc(const struct idpf_vport *vport, 190 struct idpf_tx_queue *tx_q) 191 { 192 struct device *dev = tx_q->dev; 193 struct idpf_sw_queue *refillq; 194 int err; 195 196 err = idpf_tx_buf_alloc_all(tx_q); 197 if (err) 198 goto err_alloc; 199 200 tx_q->size = tx_q->desc_count * sizeof(*tx_q->base_tx); 201 202 /* Allocate descriptors also round up to nearest 4K */ 203 tx_q->size = ALIGN(tx_q->size, 4096); 204 tx_q->desc_ring = dmam_alloc_coherent(dev, tx_q->size, &tx_q->dma, 205 GFP_KERNEL); 206 if (!tx_q->desc_ring) { 207 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 208 tx_q->size); 209 err = -ENOMEM; 210 goto err_alloc; 211 } 212 213 tx_q->next_to_use = 0; 214 tx_q->next_to_clean = 0; 215 idpf_queue_set(GEN_CHK, tx_q); 216 217 if (!idpf_queue_has(FLOW_SCH_EN, tx_q)) 218 return 0; 219 220 refillq = tx_q->refillq; 221 refillq->desc_count = tx_q->buf_pool_size; 222 refillq->ring = kcalloc(refillq->desc_count, sizeof(u32), 223 GFP_KERNEL); 224 if (!refillq->ring) { 225 err = -ENOMEM; 226 goto err_alloc; 227 } 228 229 for (unsigned int i = 0; i < refillq->desc_count; i++) 230 refillq->ring[i] = 231 FIELD_PREP(IDPF_RFL_BI_BUFID_M, i) | 232 FIELD_PREP(IDPF_RFL_BI_GEN_M, 233 idpf_queue_has(GEN_CHK, refillq)); 234 235 /* Go ahead and flip the GEN bit since this counts as filling 236 * up the ring, i.e. we already ring wrapped. 237 */ 238 idpf_queue_change(GEN_CHK, refillq); 239 240 tx_q->last_re = tx_q->desc_count - IDPF_TX_SPLITQ_RE_MIN_GAP; 241 242 return 0; 243 244 err_alloc: 245 idpf_tx_desc_rel(tx_q); 246 247 return err; 248 } 249 250 /** 251 * idpf_compl_desc_alloc - allocate completion descriptors 252 * @vport: vport to allocate resources for 253 * @complq: completion queue to set up 254 * 255 * Return: 0 on success, -errno on failure. 256 */ 257 static int idpf_compl_desc_alloc(const struct idpf_vport *vport, 258 struct idpf_compl_queue *complq) 259 { 260 u32 desc_size; 261 262 desc_size = idpf_queue_has(FLOW_SCH_EN, complq) ? 263 sizeof(*complq->comp) : sizeof(*complq->comp_4b); 264 complq->size = array_size(complq->desc_count, desc_size); 265 266 complq->desc_ring = dma_alloc_coherent(complq->netdev->dev.parent, 267 complq->size, &complq->dma, 268 GFP_KERNEL); 269 if (!complq->desc_ring) 270 return -ENOMEM; 271 272 complq->next_to_use = 0; 273 complq->next_to_clean = 0; 274 idpf_queue_set(GEN_CHK, complq); 275 276 return 0; 277 } 278 279 /** 280 * idpf_tx_desc_alloc_all - allocate all queues Tx resources 281 * @vport: virtual port private structure 282 * 283 * Returns 0 on success, negative on failure 284 */ 285 static int idpf_tx_desc_alloc_all(struct idpf_vport *vport) 286 { 287 int err = 0; 288 int i, j; 289 290 /* Setup buffer queues. In single queue model buffer queues and 291 * completion queues will be same 292 */ 293 for (i = 0; i < vport->num_txq_grp; i++) { 294 for (j = 0; j < vport->txq_grps[i].num_txq; j++) { 295 struct idpf_tx_queue *txq = vport->txq_grps[i].txqs[j]; 296 297 err = idpf_tx_desc_alloc(vport, txq); 298 if (err) { 299 pci_err(vport->adapter->pdev, 300 "Allocation for Tx Queue %u failed\n", 301 i); 302 goto err_out; 303 } 304 } 305 306 if (!idpf_is_queue_model_split(vport->txq_model)) 307 continue; 308 309 /* Setup completion queues */ 310 err = idpf_compl_desc_alloc(vport, vport->txq_grps[i].complq); 311 if (err) { 312 pci_err(vport->adapter->pdev, 313 "Allocation for Tx Completion Queue %u failed\n", 314 i); 315 goto err_out; 316 } 317 } 318 319 err_out: 320 if (err) 321 idpf_tx_desc_rel_all(vport); 322 323 return err; 324 } 325 326 /** 327 * idpf_rx_page_rel - Release an rx buffer page 328 * @rx_buf: the buffer to free 329 */ 330 static void idpf_rx_page_rel(struct libeth_fqe *rx_buf) 331 { 332 if (unlikely(!rx_buf->netmem)) 333 return; 334 335 libeth_rx_recycle_slow(rx_buf->netmem); 336 337 rx_buf->netmem = 0; 338 rx_buf->offset = 0; 339 } 340 341 /** 342 * idpf_rx_hdr_buf_rel_all - Release header buffer memory 343 * @bufq: queue to use 344 */ 345 static void idpf_rx_hdr_buf_rel_all(struct idpf_buf_queue *bufq) 346 { 347 struct libeth_fq fq = { 348 .fqes = bufq->hdr_buf, 349 .pp = bufq->hdr_pp, 350 }; 351 352 for (u32 i = 0; i < bufq->desc_count; i++) 353 idpf_rx_page_rel(&bufq->hdr_buf[i]); 354 355 libeth_rx_fq_destroy(&fq); 356 bufq->hdr_buf = NULL; 357 bufq->hdr_pp = NULL; 358 } 359 360 /** 361 * idpf_rx_buf_rel_bufq - Free all Rx buffer resources for a buffer queue 362 * @bufq: queue to be cleaned 363 */ 364 static void idpf_rx_buf_rel_bufq(struct idpf_buf_queue *bufq) 365 { 366 struct libeth_fq fq = { 367 .fqes = bufq->buf, 368 .pp = bufq->pp, 369 }; 370 371 /* queue already cleared, nothing to do */ 372 if (!bufq->buf) 373 return; 374 375 /* Free all the bufs allocated and given to hw on Rx queue */ 376 for (u32 i = 0; i < bufq->desc_count; i++) 377 idpf_rx_page_rel(&bufq->buf[i]); 378 379 if (idpf_queue_has(HSPLIT_EN, bufq)) 380 idpf_rx_hdr_buf_rel_all(bufq); 381 382 libeth_rx_fq_destroy(&fq); 383 bufq->buf = NULL; 384 bufq->pp = NULL; 385 } 386 387 /** 388 * idpf_rx_buf_rel_all - Free all Rx buffer resources for a receive queue 389 * @rxq: queue to be cleaned 390 */ 391 static void idpf_rx_buf_rel_all(struct idpf_rx_queue *rxq) 392 { 393 struct libeth_fq fq = { 394 .fqes = rxq->rx_buf, 395 .pp = rxq->pp, 396 }; 397 398 if (!rxq->rx_buf) 399 return; 400 401 for (u32 i = 0; i < rxq->desc_count; i++) 402 idpf_rx_page_rel(&rxq->rx_buf[i]); 403 404 libeth_rx_fq_destroy(&fq); 405 rxq->rx_buf = NULL; 406 rxq->pp = NULL; 407 } 408 409 /** 410 * idpf_rx_desc_rel - Free a specific Rx q resources 411 * @rxq: queue to clean the resources from 412 * @dev: device to free DMA memory 413 * @model: single or split queue model 414 * 415 * Free a specific rx queue resources 416 */ 417 static void idpf_rx_desc_rel(struct idpf_rx_queue *rxq, struct device *dev, 418 u32 model) 419 { 420 if (!rxq) 421 return; 422 423 libeth_xdp_return_stash(&rxq->xdp); 424 425 if (!idpf_is_queue_model_split(model)) 426 idpf_rx_buf_rel_all(rxq); 427 428 rxq->next_to_alloc = 0; 429 rxq->next_to_clean = 0; 430 rxq->next_to_use = 0; 431 if (!rxq->desc_ring) 432 return; 433 434 dmam_free_coherent(dev, rxq->size, rxq->desc_ring, rxq->dma); 435 rxq->desc_ring = NULL; 436 } 437 438 /** 439 * idpf_rx_desc_rel_bufq - free buffer queue resources 440 * @bufq: buffer queue to clean the resources from 441 * @dev: device to free DMA memory 442 */ 443 static void idpf_rx_desc_rel_bufq(struct idpf_buf_queue *bufq, 444 struct device *dev) 445 { 446 if (!bufq) 447 return; 448 449 idpf_rx_buf_rel_bufq(bufq); 450 451 bufq->next_to_alloc = 0; 452 bufq->next_to_clean = 0; 453 bufq->next_to_use = 0; 454 455 if (!bufq->split_buf) 456 return; 457 458 dma_free_coherent(dev, bufq->size, bufq->split_buf, bufq->dma); 459 bufq->split_buf = NULL; 460 } 461 462 /** 463 * idpf_rx_desc_rel_all - Free Rx Resources for All Queues 464 * @vport: virtual port structure 465 * 466 * Free all rx queues resources 467 */ 468 static void idpf_rx_desc_rel_all(struct idpf_vport *vport) 469 { 470 struct device *dev = &vport->adapter->pdev->dev; 471 struct idpf_rxq_group *rx_qgrp; 472 u16 num_rxq; 473 int i, j; 474 475 if (!vport->rxq_grps) 476 return; 477 478 for (i = 0; i < vport->num_rxq_grp; i++) { 479 rx_qgrp = &vport->rxq_grps[i]; 480 481 if (!idpf_is_queue_model_split(vport->rxq_model)) { 482 for (j = 0; j < rx_qgrp->singleq.num_rxq; j++) 483 idpf_rx_desc_rel(rx_qgrp->singleq.rxqs[j], dev, 484 VIRTCHNL2_QUEUE_MODEL_SINGLE); 485 continue; 486 } 487 488 num_rxq = rx_qgrp->splitq.num_rxq_sets; 489 for (j = 0; j < num_rxq; j++) 490 idpf_rx_desc_rel(&rx_qgrp->splitq.rxq_sets[j]->rxq, 491 dev, VIRTCHNL2_QUEUE_MODEL_SPLIT); 492 493 if (!rx_qgrp->splitq.bufq_sets) 494 continue; 495 496 for (j = 0; j < vport->num_bufqs_per_qgrp; j++) { 497 struct idpf_bufq_set *bufq_set = 498 &rx_qgrp->splitq.bufq_sets[j]; 499 500 idpf_rx_desc_rel_bufq(&bufq_set->bufq, dev); 501 } 502 } 503 } 504 505 /** 506 * idpf_rx_buf_hw_update - Store the new tail and head values 507 * @bufq: queue to bump 508 * @val: new head index 509 */ 510 static void idpf_rx_buf_hw_update(struct idpf_buf_queue *bufq, u32 val) 511 { 512 bufq->next_to_use = val; 513 514 if (unlikely(!bufq->tail)) 515 return; 516 517 /* writel has an implicit memory barrier */ 518 writel(val, bufq->tail); 519 } 520 521 /** 522 * idpf_rx_hdr_buf_alloc_all - Allocate memory for header buffers 523 * @bufq: ring to use 524 * 525 * Returns 0 on success, negative on failure. 526 */ 527 static int idpf_rx_hdr_buf_alloc_all(struct idpf_buf_queue *bufq) 528 { 529 struct libeth_fq fq = { 530 .count = bufq->desc_count, 531 .type = LIBETH_FQE_HDR, 532 .xdp = idpf_xdp_enabled(bufq->q_vector->vport), 533 .nid = idpf_q_vector_to_mem(bufq->q_vector), 534 }; 535 int ret; 536 537 ret = libeth_rx_fq_create(&fq, &bufq->q_vector->napi); 538 if (ret) 539 return ret; 540 541 bufq->hdr_pp = fq.pp; 542 bufq->hdr_buf = fq.fqes; 543 bufq->hdr_truesize = fq.truesize; 544 bufq->rx_hbuf_size = fq.buf_len; 545 546 return 0; 547 } 548 549 /** 550 * idpf_post_buf_refill - Post buffer id to refill queue 551 * @refillq: refill queue to post to 552 * @buf_id: buffer id to post 553 */ 554 static void idpf_post_buf_refill(struct idpf_sw_queue *refillq, u16 buf_id) 555 { 556 u32 nta = refillq->next_to_use; 557 558 /* store the buffer ID and the SW maintained GEN bit to the refillq */ 559 refillq->ring[nta] = 560 FIELD_PREP(IDPF_RFL_BI_BUFID_M, buf_id) | 561 FIELD_PREP(IDPF_RFL_BI_GEN_M, 562 idpf_queue_has(GEN_CHK, refillq)); 563 564 if (unlikely(++nta == refillq->desc_count)) { 565 nta = 0; 566 idpf_queue_change(GEN_CHK, refillq); 567 } 568 569 refillq->next_to_use = nta; 570 } 571 572 /** 573 * idpf_rx_post_buf_desc - Post buffer to bufq descriptor ring 574 * @bufq: buffer queue to post to 575 * @buf_id: buffer id to post 576 * 577 * Returns false if buffer could not be allocated, true otherwise. 578 */ 579 static bool idpf_rx_post_buf_desc(struct idpf_buf_queue *bufq, u16 buf_id) 580 { 581 struct virtchnl2_splitq_rx_buf_desc *splitq_rx_desc = NULL; 582 struct libeth_fq_fp fq = { 583 .count = bufq->desc_count, 584 }; 585 u16 nta = bufq->next_to_alloc; 586 dma_addr_t addr; 587 588 splitq_rx_desc = &bufq->split_buf[nta]; 589 590 if (idpf_queue_has(HSPLIT_EN, bufq)) { 591 fq.pp = bufq->hdr_pp; 592 fq.fqes = bufq->hdr_buf; 593 fq.truesize = bufq->hdr_truesize; 594 595 addr = libeth_rx_alloc(&fq, buf_id); 596 if (addr == DMA_MAPPING_ERROR) 597 return false; 598 599 splitq_rx_desc->hdr_addr = cpu_to_le64(addr); 600 } 601 602 fq.pp = bufq->pp; 603 fq.fqes = bufq->buf; 604 fq.truesize = bufq->truesize; 605 606 addr = libeth_rx_alloc(&fq, buf_id); 607 if (addr == DMA_MAPPING_ERROR) 608 return false; 609 610 splitq_rx_desc->pkt_addr = cpu_to_le64(addr); 611 splitq_rx_desc->qword0.buf_id = cpu_to_le16(buf_id); 612 613 nta++; 614 if (unlikely(nta == bufq->desc_count)) 615 nta = 0; 616 bufq->next_to_alloc = nta; 617 618 return true; 619 } 620 621 /** 622 * idpf_rx_post_init_bufs - Post initial buffers to bufq 623 * @bufq: buffer queue to post working set to 624 * @working_set: number of buffers to put in working set 625 * 626 * Returns true if @working_set bufs were posted successfully, false otherwise. 627 */ 628 static bool idpf_rx_post_init_bufs(struct idpf_buf_queue *bufq, 629 u16 working_set) 630 { 631 int i; 632 633 for (i = 0; i < working_set; i++) { 634 if (!idpf_rx_post_buf_desc(bufq, i)) 635 return false; 636 } 637 638 idpf_rx_buf_hw_update(bufq, ALIGN_DOWN(bufq->next_to_alloc, 639 IDPF_RX_BUF_STRIDE)); 640 641 return true; 642 } 643 644 /** 645 * idpf_rx_buf_alloc_singleq - Allocate memory for all buffer resources 646 * @rxq: queue for which the buffers are allocated 647 * 648 * Return: 0 on success, -ENOMEM on failure. 649 */ 650 static int idpf_rx_buf_alloc_singleq(struct idpf_rx_queue *rxq) 651 { 652 if (idpf_rx_singleq_buf_hw_alloc_all(rxq, rxq->desc_count - 1)) 653 goto err; 654 655 return 0; 656 657 err: 658 idpf_rx_buf_rel_all(rxq); 659 660 return -ENOMEM; 661 } 662 663 /** 664 * idpf_rx_bufs_init_singleq - Initialize page pool and allocate Rx bufs 665 * @rxq: buffer queue to create page pool for 666 * 667 * Return: 0 on success, -errno on failure. 668 */ 669 static int idpf_rx_bufs_init_singleq(struct idpf_rx_queue *rxq) 670 { 671 struct libeth_fq fq = { 672 .count = rxq->desc_count, 673 .type = LIBETH_FQE_MTU, 674 .nid = idpf_q_vector_to_mem(rxq->q_vector), 675 }; 676 int ret; 677 678 ret = libeth_rx_fq_create(&fq, &rxq->q_vector->napi); 679 if (ret) 680 return ret; 681 682 rxq->pp = fq.pp; 683 rxq->rx_buf = fq.fqes; 684 rxq->truesize = fq.truesize; 685 rxq->rx_buf_size = fq.buf_len; 686 687 return idpf_rx_buf_alloc_singleq(rxq); 688 } 689 690 /** 691 * idpf_rx_buf_alloc_all - Allocate memory for all buffer resources 692 * @rxbufq: queue for which the buffers are allocated 693 * 694 * Returns 0 on success, negative on failure 695 */ 696 static int idpf_rx_buf_alloc_all(struct idpf_buf_queue *rxbufq) 697 { 698 int err = 0; 699 700 if (idpf_queue_has(HSPLIT_EN, rxbufq)) { 701 err = idpf_rx_hdr_buf_alloc_all(rxbufq); 702 if (err) 703 goto rx_buf_alloc_all_out; 704 } 705 706 /* Allocate buffers to be given to HW. */ 707 if (!idpf_rx_post_init_bufs(rxbufq, IDPF_RX_BUFQ_WORKING_SET(rxbufq))) 708 err = -ENOMEM; 709 710 rx_buf_alloc_all_out: 711 if (err) 712 idpf_rx_buf_rel_bufq(rxbufq); 713 714 return err; 715 } 716 717 /** 718 * idpf_rx_bufs_init - Initialize page pool, allocate rx bufs, and post to HW 719 * @bufq: buffer queue to create page pool for 720 * @type: type of Rx buffers to allocate 721 * 722 * Returns 0 on success, negative on failure 723 */ 724 static int idpf_rx_bufs_init(struct idpf_buf_queue *bufq, 725 enum libeth_fqe_type type) 726 { 727 struct libeth_fq fq = { 728 .truesize = bufq->truesize, 729 .count = bufq->desc_count, 730 .type = type, 731 .hsplit = idpf_queue_has(HSPLIT_EN, bufq), 732 .xdp = idpf_xdp_enabled(bufq->q_vector->vport), 733 .nid = idpf_q_vector_to_mem(bufq->q_vector), 734 }; 735 int ret; 736 737 ret = libeth_rx_fq_create(&fq, &bufq->q_vector->napi); 738 if (ret) 739 return ret; 740 741 bufq->pp = fq.pp; 742 bufq->buf = fq.fqes; 743 bufq->truesize = fq.truesize; 744 bufq->rx_buf_size = fq.buf_len; 745 746 return idpf_rx_buf_alloc_all(bufq); 747 } 748 749 /** 750 * idpf_rx_bufs_init_all - Initialize all RX bufs 751 * @vport: virtual port struct 752 * 753 * Returns 0 on success, negative on failure 754 */ 755 int idpf_rx_bufs_init_all(struct idpf_vport *vport) 756 { 757 bool split = idpf_is_queue_model_split(vport->rxq_model); 758 int i, j, err; 759 760 idpf_xdp_copy_prog_to_rqs(vport, vport->xdp_prog); 761 762 for (i = 0; i < vport->num_rxq_grp; i++) { 763 struct idpf_rxq_group *rx_qgrp = &vport->rxq_grps[i]; 764 u32 truesize = 0; 765 766 /* Allocate bufs for the rxq itself in singleq */ 767 if (!split) { 768 int num_rxq = rx_qgrp->singleq.num_rxq; 769 770 for (j = 0; j < num_rxq; j++) { 771 struct idpf_rx_queue *q; 772 773 q = rx_qgrp->singleq.rxqs[j]; 774 err = idpf_rx_bufs_init_singleq(q); 775 if (err) 776 return err; 777 } 778 779 continue; 780 } 781 782 /* Otherwise, allocate bufs for the buffer queues */ 783 for (j = 0; j < vport->num_bufqs_per_qgrp; j++) { 784 enum libeth_fqe_type type; 785 struct idpf_buf_queue *q; 786 787 q = &rx_qgrp->splitq.bufq_sets[j].bufq; 788 q->truesize = truesize; 789 790 type = truesize ? LIBETH_FQE_SHORT : LIBETH_FQE_MTU; 791 792 err = idpf_rx_bufs_init(q, type); 793 if (err) 794 return err; 795 796 truesize = q->truesize >> 1; 797 } 798 } 799 800 return 0; 801 } 802 803 /** 804 * idpf_rx_desc_alloc - Allocate queue Rx resources 805 * @vport: vport to allocate resources for 806 * @rxq: Rx queue for which the resources are setup 807 * 808 * Returns 0 on success, negative on failure 809 */ 810 static int idpf_rx_desc_alloc(const struct idpf_vport *vport, 811 struct idpf_rx_queue *rxq) 812 { 813 struct device *dev = &vport->adapter->pdev->dev; 814 815 rxq->size = rxq->desc_count * sizeof(union virtchnl2_rx_desc); 816 817 /* Allocate descriptors and also round up to nearest 4K */ 818 rxq->size = ALIGN(rxq->size, 4096); 819 rxq->desc_ring = dmam_alloc_coherent(dev, rxq->size, 820 &rxq->dma, GFP_KERNEL); 821 if (!rxq->desc_ring) { 822 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 823 rxq->size); 824 return -ENOMEM; 825 } 826 827 rxq->next_to_alloc = 0; 828 rxq->next_to_clean = 0; 829 rxq->next_to_use = 0; 830 idpf_queue_set(GEN_CHK, rxq); 831 832 return 0; 833 } 834 835 /** 836 * idpf_bufq_desc_alloc - Allocate buffer queue descriptor ring 837 * @vport: vport to allocate resources for 838 * @bufq: buffer queue for which the resources are set up 839 * 840 * Return: 0 on success, -ENOMEM on failure. 841 */ 842 static int idpf_bufq_desc_alloc(const struct idpf_vport *vport, 843 struct idpf_buf_queue *bufq) 844 { 845 struct device *dev = &vport->adapter->pdev->dev; 846 847 bufq->size = array_size(bufq->desc_count, sizeof(*bufq->split_buf)); 848 849 bufq->split_buf = dma_alloc_coherent(dev, bufq->size, &bufq->dma, 850 GFP_KERNEL); 851 if (!bufq->split_buf) 852 return -ENOMEM; 853 854 bufq->next_to_alloc = 0; 855 bufq->next_to_clean = 0; 856 bufq->next_to_use = 0; 857 858 idpf_queue_set(GEN_CHK, bufq); 859 860 return 0; 861 } 862 863 /** 864 * idpf_rx_desc_alloc_all - allocate all RX queues resources 865 * @vport: virtual port structure 866 * 867 * Returns 0 on success, negative on failure 868 */ 869 static int idpf_rx_desc_alloc_all(struct idpf_vport *vport) 870 { 871 struct idpf_rxq_group *rx_qgrp; 872 int i, j, err; 873 u16 num_rxq; 874 875 for (i = 0; i < vport->num_rxq_grp; i++) { 876 rx_qgrp = &vport->rxq_grps[i]; 877 if (idpf_is_queue_model_split(vport->rxq_model)) 878 num_rxq = rx_qgrp->splitq.num_rxq_sets; 879 else 880 num_rxq = rx_qgrp->singleq.num_rxq; 881 882 for (j = 0; j < num_rxq; j++) { 883 struct idpf_rx_queue *q; 884 885 if (idpf_is_queue_model_split(vport->rxq_model)) 886 q = &rx_qgrp->splitq.rxq_sets[j]->rxq; 887 else 888 q = rx_qgrp->singleq.rxqs[j]; 889 890 err = idpf_rx_desc_alloc(vport, q); 891 if (err) { 892 pci_err(vport->adapter->pdev, 893 "Memory allocation for Rx Queue %u failed\n", 894 i); 895 goto err_out; 896 } 897 } 898 899 if (!idpf_is_queue_model_split(vport->rxq_model)) 900 continue; 901 902 for (j = 0; j < vport->num_bufqs_per_qgrp; j++) { 903 struct idpf_buf_queue *q; 904 905 q = &rx_qgrp->splitq.bufq_sets[j].bufq; 906 907 err = idpf_bufq_desc_alloc(vport, q); 908 if (err) { 909 pci_err(vport->adapter->pdev, 910 "Memory allocation for Rx Buffer Queue %u failed\n", 911 i); 912 goto err_out; 913 } 914 } 915 } 916 917 return 0; 918 919 err_out: 920 idpf_rx_desc_rel_all(vport); 921 922 return err; 923 } 924 925 /** 926 * idpf_txq_group_rel - Release all resources for txq groups 927 * @vport: vport to release txq groups on 928 */ 929 static void idpf_txq_group_rel(struct idpf_vport *vport) 930 { 931 bool split, flow_sch_en; 932 int i, j; 933 934 if (!vport->txq_grps) 935 return; 936 937 split = idpf_is_queue_model_split(vport->txq_model); 938 flow_sch_en = !idpf_is_cap_ena(vport->adapter, IDPF_OTHER_CAPS, 939 VIRTCHNL2_CAP_SPLITQ_QSCHED); 940 941 for (i = 0; i < vport->num_txq_grp; i++) { 942 struct idpf_txq_group *txq_grp = &vport->txq_grps[i]; 943 944 for (j = 0; j < txq_grp->num_txq; j++) { 945 if (flow_sch_en) { 946 kfree(txq_grp->txqs[j]->refillq); 947 txq_grp->txqs[j]->refillq = NULL; 948 } 949 950 kfree(txq_grp->txqs[j]); 951 txq_grp->txqs[j] = NULL; 952 } 953 954 if (!split) 955 continue; 956 957 kfree(txq_grp->complq); 958 txq_grp->complq = NULL; 959 } 960 kfree(vport->txq_grps); 961 vport->txq_grps = NULL; 962 } 963 964 /** 965 * idpf_rxq_sw_queue_rel - Release software queue resources 966 * @rx_qgrp: rx queue group with software queues 967 */ 968 static void idpf_rxq_sw_queue_rel(struct idpf_rxq_group *rx_qgrp) 969 { 970 int i, j; 971 972 for (i = 0; i < rx_qgrp->vport->num_bufqs_per_qgrp; i++) { 973 struct idpf_bufq_set *bufq_set = &rx_qgrp->splitq.bufq_sets[i]; 974 975 for (j = 0; j < bufq_set->num_refillqs; j++) { 976 kfree(bufq_set->refillqs[j].ring); 977 bufq_set->refillqs[j].ring = NULL; 978 } 979 kfree(bufq_set->refillqs); 980 bufq_set->refillqs = NULL; 981 } 982 } 983 984 /** 985 * idpf_rxq_group_rel - Release all resources for rxq groups 986 * @vport: vport to release rxq groups on 987 */ 988 static void idpf_rxq_group_rel(struct idpf_vport *vport) 989 { 990 int i; 991 992 if (!vport->rxq_grps) 993 return; 994 995 for (i = 0; i < vport->num_rxq_grp; i++) { 996 struct idpf_rxq_group *rx_qgrp = &vport->rxq_grps[i]; 997 u16 num_rxq; 998 int j; 999 1000 if (idpf_is_queue_model_split(vport->rxq_model)) { 1001 num_rxq = rx_qgrp->splitq.num_rxq_sets; 1002 for (j = 0; j < num_rxq; j++) { 1003 kfree(rx_qgrp->splitq.rxq_sets[j]); 1004 rx_qgrp->splitq.rxq_sets[j] = NULL; 1005 } 1006 1007 idpf_rxq_sw_queue_rel(rx_qgrp); 1008 kfree(rx_qgrp->splitq.bufq_sets); 1009 rx_qgrp->splitq.bufq_sets = NULL; 1010 } else { 1011 num_rxq = rx_qgrp->singleq.num_rxq; 1012 for (j = 0; j < num_rxq; j++) { 1013 kfree(rx_qgrp->singleq.rxqs[j]); 1014 rx_qgrp->singleq.rxqs[j] = NULL; 1015 } 1016 } 1017 } 1018 kfree(vport->rxq_grps); 1019 vport->rxq_grps = NULL; 1020 } 1021 1022 /** 1023 * idpf_vport_queue_grp_rel_all - Release all queue groups 1024 * @vport: vport to release queue groups for 1025 */ 1026 static void idpf_vport_queue_grp_rel_all(struct idpf_vport *vport) 1027 { 1028 idpf_txq_group_rel(vport); 1029 idpf_rxq_group_rel(vport); 1030 } 1031 1032 /** 1033 * idpf_vport_queues_rel - Free memory for all queues 1034 * @vport: virtual port 1035 * 1036 * Free the memory allocated for queues associated to a vport 1037 */ 1038 void idpf_vport_queues_rel(struct idpf_vport *vport) 1039 { 1040 idpf_xdp_copy_prog_to_rqs(vport, NULL); 1041 1042 idpf_tx_desc_rel_all(vport); 1043 idpf_rx_desc_rel_all(vport); 1044 1045 idpf_xdpsqs_put(vport); 1046 idpf_vport_queue_grp_rel_all(vport); 1047 1048 kfree(vport->txqs); 1049 vport->txqs = NULL; 1050 } 1051 1052 /** 1053 * idpf_vport_init_fast_path_txqs - Initialize fast path txq array 1054 * @vport: vport to init txqs on 1055 * 1056 * We get a queue index from skb->queue_mapping and we need a fast way to 1057 * dereference the queue from queue groups. This allows us to quickly pull a 1058 * txq based on a queue index. 1059 * 1060 * Returns 0 on success, negative on failure 1061 */ 1062 static int idpf_vport_init_fast_path_txqs(struct idpf_vport *vport) 1063 { 1064 struct idpf_ptp_vport_tx_tstamp_caps *caps = vport->tx_tstamp_caps; 1065 struct work_struct *tstamp_task = &vport->tstamp_task; 1066 int i, j, k = 0; 1067 1068 vport->txqs = kcalloc(vport->num_txq, sizeof(*vport->txqs), 1069 GFP_KERNEL); 1070 1071 if (!vport->txqs) 1072 return -ENOMEM; 1073 1074 for (i = 0; i < vport->num_txq_grp; i++) { 1075 struct idpf_txq_group *tx_grp = &vport->txq_grps[i]; 1076 1077 for (j = 0; j < tx_grp->num_txq; j++, k++) { 1078 vport->txqs[k] = tx_grp->txqs[j]; 1079 vport->txqs[k]->idx = k; 1080 1081 if (!caps) 1082 continue; 1083 1084 vport->txqs[k]->cached_tstamp_caps = caps; 1085 vport->txqs[k]->tstamp_task = tstamp_task; 1086 } 1087 } 1088 1089 return 0; 1090 } 1091 1092 /** 1093 * idpf_vport_init_num_qs - Initialize number of queues 1094 * @vport: vport to initialize queues 1095 * @vport_msg: data to be filled into vport 1096 */ 1097 void idpf_vport_init_num_qs(struct idpf_vport *vport, 1098 struct virtchnl2_create_vport *vport_msg) 1099 { 1100 struct idpf_vport_user_config_data *config_data; 1101 u16 idx = vport->idx; 1102 1103 config_data = &vport->adapter->vport_config[idx]->user_config; 1104 vport->num_txq = le16_to_cpu(vport_msg->num_tx_q); 1105 vport->num_rxq = le16_to_cpu(vport_msg->num_rx_q); 1106 /* number of txqs and rxqs in config data will be zeros only in the 1107 * driver load path and we dont update them there after 1108 */ 1109 if (!config_data->num_req_tx_qs && !config_data->num_req_rx_qs) { 1110 config_data->num_req_tx_qs = le16_to_cpu(vport_msg->num_tx_q); 1111 config_data->num_req_rx_qs = le16_to_cpu(vport_msg->num_rx_q); 1112 } 1113 1114 if (idpf_is_queue_model_split(vport->txq_model)) 1115 vport->num_complq = le16_to_cpu(vport_msg->num_tx_complq); 1116 if (idpf_is_queue_model_split(vport->rxq_model)) 1117 vport->num_bufq = le16_to_cpu(vport_msg->num_rx_bufq); 1118 1119 vport->xdp_prog = config_data->xdp_prog; 1120 if (idpf_xdp_enabled(vport)) { 1121 vport->xdp_txq_offset = config_data->num_req_tx_qs; 1122 vport->num_xdp_txq = le16_to_cpu(vport_msg->num_tx_q) - 1123 vport->xdp_txq_offset; 1124 vport->xdpsq_share = libeth_xdpsq_shared(vport->num_xdp_txq); 1125 } else { 1126 vport->xdp_txq_offset = 0; 1127 vport->num_xdp_txq = 0; 1128 vport->xdpsq_share = false; 1129 } 1130 1131 /* Adjust number of buffer queues per Rx queue group. */ 1132 if (!idpf_is_queue_model_split(vport->rxq_model)) { 1133 vport->num_bufqs_per_qgrp = 0; 1134 1135 return; 1136 } 1137 1138 vport->num_bufqs_per_qgrp = IDPF_MAX_BUFQS_PER_RXQ_GRP; 1139 } 1140 1141 /** 1142 * idpf_vport_calc_num_q_desc - Calculate number of queue groups 1143 * @vport: vport to calculate q groups for 1144 */ 1145 void idpf_vport_calc_num_q_desc(struct idpf_vport *vport) 1146 { 1147 struct idpf_vport_user_config_data *config_data; 1148 int num_bufqs = vport->num_bufqs_per_qgrp; 1149 u32 num_req_txq_desc, num_req_rxq_desc; 1150 u16 idx = vport->idx; 1151 int i; 1152 1153 config_data = &vport->adapter->vport_config[idx]->user_config; 1154 num_req_txq_desc = config_data->num_req_txq_desc; 1155 num_req_rxq_desc = config_data->num_req_rxq_desc; 1156 1157 vport->complq_desc_count = 0; 1158 if (num_req_txq_desc) { 1159 vport->txq_desc_count = num_req_txq_desc; 1160 if (idpf_is_queue_model_split(vport->txq_model)) { 1161 vport->complq_desc_count = num_req_txq_desc; 1162 if (vport->complq_desc_count < IDPF_MIN_TXQ_COMPLQ_DESC) 1163 vport->complq_desc_count = 1164 IDPF_MIN_TXQ_COMPLQ_DESC; 1165 } 1166 } else { 1167 vport->txq_desc_count = IDPF_DFLT_TX_Q_DESC_COUNT; 1168 if (idpf_is_queue_model_split(vport->txq_model)) 1169 vport->complq_desc_count = 1170 IDPF_DFLT_TX_COMPLQ_DESC_COUNT; 1171 } 1172 1173 if (num_req_rxq_desc) 1174 vport->rxq_desc_count = num_req_rxq_desc; 1175 else 1176 vport->rxq_desc_count = IDPF_DFLT_RX_Q_DESC_COUNT; 1177 1178 for (i = 0; i < num_bufqs; i++) { 1179 if (!vport->bufq_desc_count[i]) 1180 vport->bufq_desc_count[i] = 1181 IDPF_RX_BUFQ_DESC_COUNT(vport->rxq_desc_count, 1182 num_bufqs); 1183 } 1184 } 1185 1186 /** 1187 * idpf_vport_calc_total_qs - Calculate total number of queues 1188 * @adapter: private data struct 1189 * @vport_idx: vport idx to retrieve vport pointer 1190 * @vport_msg: message to fill with data 1191 * @max_q: vport max queue info 1192 * 1193 * Return 0 on success, error value on failure. 1194 */ 1195 int idpf_vport_calc_total_qs(struct idpf_adapter *adapter, u16 vport_idx, 1196 struct virtchnl2_create_vport *vport_msg, 1197 struct idpf_vport_max_q *max_q) 1198 { 1199 int dflt_splitq_txq_grps = 0, dflt_singleq_txqs = 0; 1200 int dflt_splitq_rxq_grps = 0, dflt_singleq_rxqs = 0; 1201 u16 num_req_tx_qs = 0, num_req_rx_qs = 0; 1202 struct idpf_vport_user_config_data *user; 1203 struct idpf_vport_config *vport_config; 1204 u16 num_txq_grps, num_rxq_grps; 1205 u32 num_qs, num_xdpsq; 1206 1207 vport_config = adapter->vport_config[vport_idx]; 1208 if (vport_config) { 1209 num_req_tx_qs = vport_config->user_config.num_req_tx_qs; 1210 num_req_rx_qs = vport_config->user_config.num_req_rx_qs; 1211 } else { 1212 u32 num_cpus = netif_get_num_default_rss_queues(); 1213 1214 dflt_splitq_txq_grps = min_t(int, max_q->max_txq, num_cpus); 1215 dflt_singleq_txqs = min_t(int, max_q->max_txq, num_cpus); 1216 dflt_splitq_rxq_grps = min_t(int, max_q->max_rxq, num_cpus); 1217 dflt_singleq_rxqs = min_t(int, max_q->max_rxq, num_cpus); 1218 } 1219 1220 if (idpf_is_queue_model_split(le16_to_cpu(vport_msg->txq_model))) { 1221 num_txq_grps = num_req_tx_qs ? num_req_tx_qs : dflt_splitq_txq_grps; 1222 vport_msg->num_tx_complq = cpu_to_le16(num_txq_grps * 1223 IDPF_COMPLQ_PER_GROUP); 1224 vport_msg->num_tx_q = cpu_to_le16(num_txq_grps * 1225 IDPF_DFLT_SPLITQ_TXQ_PER_GROUP); 1226 } else { 1227 num_txq_grps = IDPF_DFLT_SINGLEQ_TX_Q_GROUPS; 1228 num_qs = num_txq_grps * (num_req_tx_qs ? num_req_tx_qs : 1229 dflt_singleq_txqs); 1230 vport_msg->num_tx_q = cpu_to_le16(num_qs); 1231 vport_msg->num_tx_complq = 0; 1232 } 1233 if (idpf_is_queue_model_split(le16_to_cpu(vport_msg->rxq_model))) { 1234 num_rxq_grps = num_req_rx_qs ? num_req_rx_qs : dflt_splitq_rxq_grps; 1235 vport_msg->num_rx_bufq = cpu_to_le16(num_rxq_grps * 1236 IDPF_MAX_BUFQS_PER_RXQ_GRP); 1237 vport_msg->num_rx_q = cpu_to_le16(num_rxq_grps * 1238 IDPF_DFLT_SPLITQ_RXQ_PER_GROUP); 1239 } else { 1240 num_rxq_grps = IDPF_DFLT_SINGLEQ_RX_Q_GROUPS; 1241 num_qs = num_rxq_grps * (num_req_rx_qs ? num_req_rx_qs : 1242 dflt_singleq_rxqs); 1243 vport_msg->num_rx_q = cpu_to_le16(num_qs); 1244 vport_msg->num_rx_bufq = 0; 1245 } 1246 1247 if (!vport_config) 1248 return 0; 1249 1250 user = &vport_config->user_config; 1251 user->num_req_rx_qs = le16_to_cpu(vport_msg->num_rx_q); 1252 user->num_req_tx_qs = le16_to_cpu(vport_msg->num_tx_q); 1253 1254 if (vport_config->user_config.xdp_prog) 1255 num_xdpsq = libeth_xdpsq_num(user->num_req_rx_qs, 1256 user->num_req_tx_qs, 1257 vport_config->max_q.max_txq); 1258 else 1259 num_xdpsq = 0; 1260 1261 vport_msg->num_tx_q = cpu_to_le16(user->num_req_tx_qs + num_xdpsq); 1262 if (idpf_is_queue_model_split(le16_to_cpu(vport_msg->txq_model))) 1263 vport_msg->num_tx_complq = vport_msg->num_tx_q; 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * idpf_vport_calc_num_q_groups - Calculate number of queue groups 1270 * @vport: vport to calculate q groups for 1271 */ 1272 void idpf_vport_calc_num_q_groups(struct idpf_vport *vport) 1273 { 1274 if (idpf_is_queue_model_split(vport->txq_model)) 1275 vport->num_txq_grp = vport->num_txq; 1276 else 1277 vport->num_txq_grp = IDPF_DFLT_SINGLEQ_TX_Q_GROUPS; 1278 1279 if (idpf_is_queue_model_split(vport->rxq_model)) 1280 vport->num_rxq_grp = vport->num_rxq; 1281 else 1282 vport->num_rxq_grp = IDPF_DFLT_SINGLEQ_RX_Q_GROUPS; 1283 } 1284 1285 /** 1286 * idpf_vport_calc_numq_per_grp - Calculate number of queues per group 1287 * @vport: vport to calculate queues for 1288 * @num_txq: return parameter for number of TX queues 1289 * @num_rxq: return parameter for number of RX queues 1290 */ 1291 static void idpf_vport_calc_numq_per_grp(struct idpf_vport *vport, 1292 u16 *num_txq, u16 *num_rxq) 1293 { 1294 if (idpf_is_queue_model_split(vport->txq_model)) 1295 *num_txq = IDPF_DFLT_SPLITQ_TXQ_PER_GROUP; 1296 else 1297 *num_txq = vport->num_txq; 1298 1299 if (idpf_is_queue_model_split(vport->rxq_model)) 1300 *num_rxq = IDPF_DFLT_SPLITQ_RXQ_PER_GROUP; 1301 else 1302 *num_rxq = vport->num_rxq; 1303 } 1304 1305 /** 1306 * idpf_rxq_set_descids - set the descids supported by this queue 1307 * @vport: virtual port data structure 1308 * @q: rx queue for which descids are set 1309 * 1310 */ 1311 static void idpf_rxq_set_descids(const struct idpf_vport *vport, 1312 struct idpf_rx_queue *q) 1313 { 1314 if (idpf_is_queue_model_split(vport->rxq_model)) 1315 return; 1316 1317 if (vport->base_rxd) 1318 q->rxdids = VIRTCHNL2_RXDID_1_32B_BASE_M; 1319 else 1320 q->rxdids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M; 1321 } 1322 1323 /** 1324 * idpf_txq_group_alloc - Allocate all txq group resources 1325 * @vport: vport to allocate txq groups for 1326 * @num_txq: number of txqs to allocate for each group 1327 * 1328 * Returns 0 on success, negative on failure 1329 */ 1330 static int idpf_txq_group_alloc(struct idpf_vport *vport, u16 num_txq) 1331 { 1332 bool split, flow_sch_en; 1333 int i; 1334 1335 vport->txq_grps = kcalloc(vport->num_txq_grp, 1336 sizeof(*vport->txq_grps), GFP_KERNEL); 1337 if (!vport->txq_grps) 1338 return -ENOMEM; 1339 1340 split = idpf_is_queue_model_split(vport->txq_model); 1341 flow_sch_en = !idpf_is_cap_ena(vport->adapter, IDPF_OTHER_CAPS, 1342 VIRTCHNL2_CAP_SPLITQ_QSCHED); 1343 1344 for (i = 0; i < vport->num_txq_grp; i++) { 1345 struct idpf_txq_group *tx_qgrp = &vport->txq_grps[i]; 1346 struct idpf_adapter *adapter = vport->adapter; 1347 int j; 1348 1349 tx_qgrp->vport = vport; 1350 tx_qgrp->num_txq = num_txq; 1351 1352 for (j = 0; j < tx_qgrp->num_txq; j++) { 1353 tx_qgrp->txqs[j] = kzalloc(sizeof(*tx_qgrp->txqs[j]), 1354 GFP_KERNEL); 1355 if (!tx_qgrp->txqs[j]) 1356 goto err_alloc; 1357 } 1358 1359 for (j = 0; j < tx_qgrp->num_txq; j++) { 1360 struct idpf_tx_queue *q = tx_qgrp->txqs[j]; 1361 1362 q->dev = &adapter->pdev->dev; 1363 q->desc_count = vport->txq_desc_count; 1364 q->tx_max_bufs = idpf_get_max_tx_bufs(adapter); 1365 q->tx_min_pkt_len = idpf_get_min_tx_pkt_len(adapter); 1366 q->netdev = vport->netdev; 1367 q->txq_grp = tx_qgrp; 1368 1369 if (!split) { 1370 q->clean_budget = vport->compln_clean_budget; 1371 idpf_queue_assign(CRC_EN, q, 1372 vport->crc_enable); 1373 } 1374 1375 if (!flow_sch_en) 1376 continue; 1377 1378 idpf_queue_set(FLOW_SCH_EN, q); 1379 1380 q->refillq = kzalloc(sizeof(*q->refillq), GFP_KERNEL); 1381 if (!q->refillq) 1382 goto err_alloc; 1383 1384 idpf_queue_set(GEN_CHK, q->refillq); 1385 idpf_queue_set(RFL_GEN_CHK, q->refillq); 1386 } 1387 1388 if (!split) 1389 continue; 1390 1391 tx_qgrp->complq = kcalloc(IDPF_COMPLQ_PER_GROUP, 1392 sizeof(*tx_qgrp->complq), 1393 GFP_KERNEL); 1394 if (!tx_qgrp->complq) 1395 goto err_alloc; 1396 1397 tx_qgrp->complq->desc_count = vport->complq_desc_count; 1398 tx_qgrp->complq->txq_grp = tx_qgrp; 1399 tx_qgrp->complq->netdev = vport->netdev; 1400 tx_qgrp->complq->clean_budget = vport->compln_clean_budget; 1401 1402 if (flow_sch_en) 1403 idpf_queue_set(FLOW_SCH_EN, tx_qgrp->complq); 1404 } 1405 1406 return 0; 1407 1408 err_alloc: 1409 idpf_txq_group_rel(vport); 1410 1411 return -ENOMEM; 1412 } 1413 1414 /** 1415 * idpf_rxq_group_alloc - Allocate all rxq group resources 1416 * @vport: vport to allocate rxq groups for 1417 * @num_rxq: number of rxqs to allocate for each group 1418 * 1419 * Returns 0 on success, negative on failure 1420 */ 1421 static int idpf_rxq_group_alloc(struct idpf_vport *vport, u16 num_rxq) 1422 { 1423 int i, k, err = 0; 1424 bool hs; 1425 1426 vport->rxq_grps = kcalloc(vport->num_rxq_grp, 1427 sizeof(struct idpf_rxq_group), GFP_KERNEL); 1428 if (!vport->rxq_grps) 1429 return -ENOMEM; 1430 1431 hs = idpf_vport_get_hsplit(vport) == ETHTOOL_TCP_DATA_SPLIT_ENABLED; 1432 1433 for (i = 0; i < vport->num_rxq_grp; i++) { 1434 struct idpf_rxq_group *rx_qgrp = &vport->rxq_grps[i]; 1435 int j; 1436 1437 rx_qgrp->vport = vport; 1438 if (!idpf_is_queue_model_split(vport->rxq_model)) { 1439 rx_qgrp->singleq.num_rxq = num_rxq; 1440 for (j = 0; j < num_rxq; j++) { 1441 rx_qgrp->singleq.rxqs[j] = 1442 kzalloc(sizeof(*rx_qgrp->singleq.rxqs[j]), 1443 GFP_KERNEL); 1444 if (!rx_qgrp->singleq.rxqs[j]) { 1445 err = -ENOMEM; 1446 goto err_alloc; 1447 } 1448 } 1449 goto skip_splitq_rx_init; 1450 } 1451 rx_qgrp->splitq.num_rxq_sets = num_rxq; 1452 1453 for (j = 0; j < num_rxq; j++) { 1454 rx_qgrp->splitq.rxq_sets[j] = 1455 kzalloc(sizeof(struct idpf_rxq_set), 1456 GFP_KERNEL); 1457 if (!rx_qgrp->splitq.rxq_sets[j]) { 1458 err = -ENOMEM; 1459 goto err_alloc; 1460 } 1461 } 1462 1463 rx_qgrp->splitq.bufq_sets = kcalloc(vport->num_bufqs_per_qgrp, 1464 sizeof(struct idpf_bufq_set), 1465 GFP_KERNEL); 1466 if (!rx_qgrp->splitq.bufq_sets) { 1467 err = -ENOMEM; 1468 goto err_alloc; 1469 } 1470 1471 for (j = 0; j < vport->num_bufqs_per_qgrp; j++) { 1472 struct idpf_bufq_set *bufq_set = 1473 &rx_qgrp->splitq.bufq_sets[j]; 1474 int swq_size = sizeof(struct idpf_sw_queue); 1475 struct idpf_buf_queue *q; 1476 1477 q = &rx_qgrp->splitq.bufq_sets[j].bufq; 1478 q->desc_count = vport->bufq_desc_count[j]; 1479 q->rx_buffer_low_watermark = IDPF_LOW_WATERMARK; 1480 1481 idpf_queue_assign(HSPLIT_EN, q, hs); 1482 1483 bufq_set->num_refillqs = num_rxq; 1484 bufq_set->refillqs = kcalloc(num_rxq, swq_size, 1485 GFP_KERNEL); 1486 if (!bufq_set->refillqs) { 1487 err = -ENOMEM; 1488 goto err_alloc; 1489 } 1490 for (k = 0; k < bufq_set->num_refillqs; k++) { 1491 struct idpf_sw_queue *refillq = 1492 &bufq_set->refillqs[k]; 1493 1494 refillq->desc_count = 1495 vport->bufq_desc_count[j]; 1496 idpf_queue_set(GEN_CHK, refillq); 1497 idpf_queue_set(RFL_GEN_CHK, refillq); 1498 refillq->ring = kcalloc(refillq->desc_count, 1499 sizeof(*refillq->ring), 1500 GFP_KERNEL); 1501 if (!refillq->ring) { 1502 err = -ENOMEM; 1503 goto err_alloc; 1504 } 1505 } 1506 } 1507 1508 skip_splitq_rx_init: 1509 for (j = 0; j < num_rxq; j++) { 1510 struct idpf_rx_queue *q; 1511 1512 if (!idpf_is_queue_model_split(vport->rxq_model)) { 1513 q = rx_qgrp->singleq.rxqs[j]; 1514 goto setup_rxq; 1515 } 1516 q = &rx_qgrp->splitq.rxq_sets[j]->rxq; 1517 rx_qgrp->splitq.rxq_sets[j]->refillq[0] = 1518 &rx_qgrp->splitq.bufq_sets[0].refillqs[j]; 1519 if (vport->num_bufqs_per_qgrp > IDPF_SINGLE_BUFQ_PER_RXQ_GRP) 1520 rx_qgrp->splitq.rxq_sets[j]->refillq[1] = 1521 &rx_qgrp->splitq.bufq_sets[1].refillqs[j]; 1522 1523 idpf_queue_assign(HSPLIT_EN, q, hs); 1524 1525 setup_rxq: 1526 q->desc_count = vport->rxq_desc_count; 1527 q->rx_ptype_lkup = vport->rx_ptype_lkup; 1528 q->bufq_sets = rx_qgrp->splitq.bufq_sets; 1529 q->idx = (i * num_rxq) + j; 1530 q->rx_buffer_low_watermark = IDPF_LOW_WATERMARK; 1531 q->rx_max_pkt_size = vport->netdev->mtu + 1532 LIBETH_RX_LL_LEN; 1533 idpf_rxq_set_descids(vport, q); 1534 } 1535 } 1536 1537 err_alloc: 1538 if (err) 1539 idpf_rxq_group_rel(vport); 1540 1541 return err; 1542 } 1543 1544 /** 1545 * idpf_vport_queue_grp_alloc_all - Allocate all queue groups/resources 1546 * @vport: vport with qgrps to allocate 1547 * 1548 * Returns 0 on success, negative on failure 1549 */ 1550 static int idpf_vport_queue_grp_alloc_all(struct idpf_vport *vport) 1551 { 1552 u16 num_txq, num_rxq; 1553 int err; 1554 1555 idpf_vport_calc_numq_per_grp(vport, &num_txq, &num_rxq); 1556 1557 err = idpf_txq_group_alloc(vport, num_txq); 1558 if (err) 1559 goto err_out; 1560 1561 err = idpf_rxq_group_alloc(vport, num_rxq); 1562 if (err) 1563 goto err_out; 1564 1565 return 0; 1566 1567 err_out: 1568 idpf_vport_queue_grp_rel_all(vport); 1569 1570 return err; 1571 } 1572 1573 /** 1574 * idpf_vport_queues_alloc - Allocate memory for all queues 1575 * @vport: virtual port 1576 * 1577 * Allocate memory for queues associated with a vport. Returns 0 on success, 1578 * negative on failure. 1579 */ 1580 int idpf_vport_queues_alloc(struct idpf_vport *vport) 1581 { 1582 int err; 1583 1584 err = idpf_vport_queue_grp_alloc_all(vport); 1585 if (err) 1586 goto err_out; 1587 1588 err = idpf_vport_init_fast_path_txqs(vport); 1589 if (err) 1590 goto err_out; 1591 1592 err = idpf_xdpsqs_get(vport); 1593 if (err) 1594 goto err_out; 1595 1596 err = idpf_tx_desc_alloc_all(vport); 1597 if (err) 1598 goto err_out; 1599 1600 err = idpf_rx_desc_alloc_all(vport); 1601 if (err) 1602 goto err_out; 1603 1604 return 0; 1605 1606 err_out: 1607 idpf_vport_queues_rel(vport); 1608 1609 return err; 1610 } 1611 1612 /** 1613 * idpf_tx_read_tstamp - schedule a work to read Tx timestamp value 1614 * @txq: queue to read the timestamp from 1615 * @skb: socket buffer to provide Tx timestamp value 1616 * 1617 * Schedule a work to read Tx timestamp value generated once the packet is 1618 * transmitted. 1619 */ 1620 static void idpf_tx_read_tstamp(struct idpf_tx_queue *txq, struct sk_buff *skb) 1621 { 1622 struct idpf_ptp_vport_tx_tstamp_caps *tx_tstamp_caps; 1623 struct idpf_ptp_tx_tstamp_status *tx_tstamp_status; 1624 1625 tx_tstamp_caps = txq->cached_tstamp_caps; 1626 spin_lock_bh(&tx_tstamp_caps->status_lock); 1627 1628 for (u32 i = 0; i < tx_tstamp_caps->num_entries; i++) { 1629 tx_tstamp_status = &tx_tstamp_caps->tx_tstamp_status[i]; 1630 if (tx_tstamp_status->state != IDPF_PTP_FREE) 1631 continue; 1632 1633 tx_tstamp_status->skb = skb; 1634 tx_tstamp_status->state = IDPF_PTP_REQUEST; 1635 1636 /* Fetch timestamp from completion descriptor through 1637 * virtchnl msg to report to stack. 1638 */ 1639 queue_work(system_unbound_wq, txq->tstamp_task); 1640 break; 1641 } 1642 1643 spin_unlock_bh(&tx_tstamp_caps->status_lock); 1644 } 1645 1646 #define idpf_tx_splitq_clean_bump_ntc(txq, ntc, desc, buf) \ 1647 do { \ 1648 if (unlikely(++(ntc) == (txq)->desc_count)) { \ 1649 ntc = 0; \ 1650 buf = (txq)->tx_buf; \ 1651 desc = &(txq)->flex_tx[0]; \ 1652 } else { \ 1653 (buf)++; \ 1654 (desc)++; \ 1655 } \ 1656 } while (0) 1657 1658 /** 1659 * idpf_tx_splitq_clean - Reclaim resources from buffer queue 1660 * @tx_q: Tx queue to clean 1661 * @end: queue index until which it should be cleaned 1662 * @napi_budget: Used to determine if we are in netpoll 1663 * @cleaned: pointer to stats struct to track cleaned packets/bytes 1664 * @descs_only: true if queue is using flow-based scheduling and should 1665 * not clean buffers at this time 1666 * 1667 * Cleans the queue descriptor ring. If the queue is using queue-based 1668 * scheduling, the buffers will be cleaned as well. If the queue is using 1669 * flow-based scheduling, only the descriptors are cleaned at this time. 1670 * Separate packet completion events will be reported on the completion queue, 1671 * and the buffers will be cleaned separately. The stats are not updated from 1672 * this function when using flow-based scheduling. 1673 */ 1674 static void idpf_tx_splitq_clean(struct idpf_tx_queue *tx_q, u16 end, 1675 int napi_budget, 1676 struct libeth_sq_napi_stats *cleaned, 1677 bool descs_only) 1678 { 1679 union idpf_tx_flex_desc *next_pending_desc = NULL; 1680 union idpf_tx_flex_desc *tx_desc; 1681 u32 ntc = tx_q->next_to_clean; 1682 struct libeth_cq_pp cp = { 1683 .dev = tx_q->dev, 1684 .ss = cleaned, 1685 .napi = napi_budget, 1686 }; 1687 struct idpf_tx_buf *tx_buf; 1688 1689 if (descs_only) { 1690 /* Bump ring index to mark as cleaned. */ 1691 tx_q->next_to_clean = end; 1692 return; 1693 } 1694 1695 tx_desc = &tx_q->flex_tx[ntc]; 1696 next_pending_desc = &tx_q->flex_tx[end]; 1697 tx_buf = &tx_q->tx_buf[ntc]; 1698 1699 while (tx_desc != next_pending_desc) { 1700 u32 eop_idx; 1701 1702 /* If this entry in the ring was used as a context descriptor, 1703 * it's corresponding entry in the buffer ring is reserved. We 1704 * can skip this descriptor since there is no buffer to clean. 1705 */ 1706 if (tx_buf->type <= LIBETH_SQE_CTX) 1707 goto fetch_next_txq_desc; 1708 1709 if (unlikely(tx_buf->type != LIBETH_SQE_SKB)) 1710 break; 1711 1712 eop_idx = tx_buf->rs_idx; 1713 libeth_tx_complete(tx_buf, &cp); 1714 1715 /* unmap remaining buffers */ 1716 while (ntc != eop_idx) { 1717 idpf_tx_splitq_clean_bump_ntc(tx_q, ntc, 1718 tx_desc, tx_buf); 1719 1720 /* unmap any remaining paged data */ 1721 libeth_tx_complete(tx_buf, &cp); 1722 } 1723 1724 fetch_next_txq_desc: 1725 idpf_tx_splitq_clean_bump_ntc(tx_q, ntc, tx_desc, tx_buf); 1726 } 1727 1728 tx_q->next_to_clean = ntc; 1729 } 1730 1731 /** 1732 * idpf_tx_clean_bufs - clean flow scheduling TX queue buffers 1733 * @txq: queue to clean 1734 * @buf_id: packet's starting buffer ID, from completion descriptor 1735 * @cleaned: pointer to stats struct to track cleaned packets/bytes 1736 * @budget: Used to determine if we are in netpoll 1737 * 1738 * Clean all buffers associated with the packet starting at buf_id. Returns the 1739 * byte/segment count for the cleaned packet. 1740 */ 1741 static void idpf_tx_clean_bufs(struct idpf_tx_queue *txq, u32 buf_id, 1742 struct libeth_sq_napi_stats *cleaned, 1743 int budget) 1744 { 1745 struct idpf_tx_buf *tx_buf = NULL; 1746 struct libeth_cq_pp cp = { 1747 .dev = txq->dev, 1748 .ss = cleaned, 1749 .napi = budget, 1750 }; 1751 1752 tx_buf = &txq->tx_buf[buf_id]; 1753 if (tx_buf->type == LIBETH_SQE_SKB) { 1754 if (skb_shinfo(tx_buf->skb)->tx_flags & SKBTX_IN_PROGRESS) 1755 idpf_tx_read_tstamp(txq, tx_buf->skb); 1756 1757 libeth_tx_complete(tx_buf, &cp); 1758 idpf_post_buf_refill(txq->refillq, buf_id); 1759 } 1760 1761 while (idpf_tx_buf_next(tx_buf) != IDPF_TXBUF_NULL) { 1762 buf_id = idpf_tx_buf_next(tx_buf); 1763 1764 tx_buf = &txq->tx_buf[buf_id]; 1765 libeth_tx_complete(tx_buf, &cp); 1766 idpf_post_buf_refill(txq->refillq, buf_id); 1767 } 1768 } 1769 1770 /** 1771 * idpf_tx_handle_rs_completion - clean a single packet and all of its buffers 1772 * whether on the buffer ring or in the hash table 1773 * @txq: Tx ring to clean 1774 * @desc: pointer to completion queue descriptor to extract completion 1775 * information from 1776 * @cleaned: pointer to stats struct to track cleaned packets/bytes 1777 * @budget: Used to determine if we are in netpoll 1778 * 1779 * Returns bytes/packets cleaned 1780 */ 1781 static void idpf_tx_handle_rs_completion(struct idpf_tx_queue *txq, 1782 struct idpf_splitq_tx_compl_desc *desc, 1783 struct libeth_sq_napi_stats *cleaned, 1784 int budget) 1785 { 1786 /* RS completion contains queue head for queue based scheduling or 1787 * completion tag for flow based scheduling. 1788 */ 1789 u16 rs_compl_val = le16_to_cpu(desc->common.q_head_compl_tag.q_head); 1790 1791 if (!idpf_queue_has(FLOW_SCH_EN, txq)) { 1792 idpf_tx_splitq_clean(txq, rs_compl_val, budget, cleaned, false); 1793 return; 1794 } 1795 1796 idpf_tx_clean_bufs(txq, rs_compl_val, cleaned, budget); 1797 } 1798 1799 /** 1800 * idpf_tx_clean_complq - Reclaim resources on completion queue 1801 * @complq: Tx ring to clean 1802 * @budget: Used to determine if we are in netpoll 1803 * @cleaned: returns number of packets cleaned 1804 * 1805 * Returns true if there's any budget left (e.g. the clean is finished) 1806 */ 1807 static bool idpf_tx_clean_complq(struct idpf_compl_queue *complq, int budget, 1808 int *cleaned) 1809 { 1810 struct idpf_splitq_tx_compl_desc *tx_desc; 1811 s16 ntc = complq->next_to_clean; 1812 struct idpf_netdev_priv *np; 1813 unsigned int complq_budget; 1814 bool complq_ok = true; 1815 int i; 1816 1817 complq_budget = complq->clean_budget; 1818 tx_desc = &complq->comp[ntc]; 1819 ntc -= complq->desc_count; 1820 1821 do { 1822 struct libeth_sq_napi_stats cleaned_stats = { }; 1823 struct idpf_tx_queue *tx_q; 1824 __le16 hw_head; 1825 int rel_tx_qid; 1826 u8 ctype; /* completion type */ 1827 u16 gen; 1828 1829 /* if the descriptor isn't done, no work yet to do */ 1830 gen = le16_get_bits(tx_desc->common.qid_comptype_gen, 1831 IDPF_TXD_COMPLQ_GEN_M); 1832 if (idpf_queue_has(GEN_CHK, complq) != gen) 1833 break; 1834 1835 /* Find necessary info of TX queue to clean buffers */ 1836 rel_tx_qid = le16_get_bits(tx_desc->common.qid_comptype_gen, 1837 IDPF_TXD_COMPLQ_QID_M); 1838 if (rel_tx_qid >= complq->txq_grp->num_txq || 1839 !complq->txq_grp->txqs[rel_tx_qid]) { 1840 netdev_err(complq->netdev, "TxQ not found\n"); 1841 goto fetch_next_desc; 1842 } 1843 tx_q = complq->txq_grp->txqs[rel_tx_qid]; 1844 1845 /* Determine completion type */ 1846 ctype = le16_get_bits(tx_desc->common.qid_comptype_gen, 1847 IDPF_TXD_COMPLQ_COMPL_TYPE_M); 1848 switch (ctype) { 1849 case IDPF_TXD_COMPLT_RE: 1850 hw_head = tx_desc->common.q_head_compl_tag.q_head; 1851 1852 idpf_tx_splitq_clean(tx_q, le16_to_cpu(hw_head), 1853 budget, &cleaned_stats, true); 1854 break; 1855 case IDPF_TXD_COMPLT_RS: 1856 idpf_tx_handle_rs_completion(tx_q, tx_desc, 1857 &cleaned_stats, budget); 1858 break; 1859 default: 1860 netdev_err(tx_q->netdev, 1861 "Unknown TX completion type: %d\n", ctype); 1862 goto fetch_next_desc; 1863 } 1864 1865 u64_stats_update_begin(&tx_q->stats_sync); 1866 u64_stats_add(&tx_q->q_stats.packets, cleaned_stats.packets); 1867 u64_stats_add(&tx_q->q_stats.bytes, cleaned_stats.bytes); 1868 tx_q->cleaned_pkts += cleaned_stats.packets; 1869 tx_q->cleaned_bytes += cleaned_stats.bytes; 1870 complq->num_completions++; 1871 u64_stats_update_end(&tx_q->stats_sync); 1872 1873 fetch_next_desc: 1874 tx_desc++; 1875 ntc++; 1876 if (unlikely(!ntc)) { 1877 ntc -= complq->desc_count; 1878 tx_desc = &complq->comp[0]; 1879 idpf_queue_change(GEN_CHK, complq); 1880 } 1881 1882 prefetch(tx_desc); 1883 1884 /* update budget accounting */ 1885 complq_budget--; 1886 } while (likely(complq_budget)); 1887 1888 /* Store the state of the complq to be used later in deciding if a 1889 * TXQ can be started again 1890 */ 1891 if (unlikely(IDPF_TX_COMPLQ_PENDING(complq->txq_grp) > 1892 IDPF_TX_COMPLQ_OVERFLOW_THRESH(complq))) 1893 complq_ok = false; 1894 1895 np = netdev_priv(complq->netdev); 1896 for (i = 0; i < complq->txq_grp->num_txq; ++i) { 1897 struct idpf_tx_queue *tx_q = complq->txq_grp->txqs[i]; 1898 struct netdev_queue *nq; 1899 bool dont_wake; 1900 1901 /* We didn't clean anything on this queue, move along */ 1902 if (!tx_q->cleaned_bytes) 1903 continue; 1904 1905 *cleaned += tx_q->cleaned_pkts; 1906 1907 /* Update BQL */ 1908 nq = netdev_get_tx_queue(tx_q->netdev, tx_q->idx); 1909 1910 dont_wake = !complq_ok || np->state != __IDPF_VPORT_UP || 1911 !netif_carrier_ok(tx_q->netdev); 1912 /* Check if the TXQ needs to and can be restarted */ 1913 __netif_txq_completed_wake(nq, tx_q->cleaned_pkts, tx_q->cleaned_bytes, 1914 IDPF_DESC_UNUSED(tx_q), IDPF_TX_WAKE_THRESH, 1915 dont_wake); 1916 1917 /* Reset cleaned stats for the next time this queue is 1918 * cleaned 1919 */ 1920 tx_q->cleaned_bytes = 0; 1921 tx_q->cleaned_pkts = 0; 1922 } 1923 1924 ntc += complq->desc_count; 1925 complq->next_to_clean = ntc; 1926 1927 return !!complq_budget; 1928 } 1929 1930 /** 1931 * idpf_wait_for_sw_marker_completion - wait for SW marker of disabled Tx queue 1932 * @txq: disabled Tx queue 1933 * 1934 * When Tx queue is requested for disabling, the CP sends a special completion 1935 * descriptor called "SW marker", meaning the queue is ready to be destroyed. 1936 * If, for some reason, the marker is not received within 500 ms, break the 1937 * polling to not hang the driver. 1938 */ 1939 void idpf_wait_for_sw_marker_completion(const struct idpf_tx_queue *txq) 1940 { 1941 struct idpf_compl_queue *complq; 1942 unsigned long timeout; 1943 bool flow, gen_flag; 1944 u32 ntc; 1945 1946 if (!idpf_queue_has(SW_MARKER, txq)) 1947 return; 1948 1949 complq = idpf_queue_has(XDP, txq) ? txq->complq : txq->txq_grp->complq; 1950 ntc = complq->next_to_clean; 1951 1952 flow = idpf_queue_has(FLOW_SCH_EN, complq); 1953 gen_flag = idpf_queue_has(GEN_CHK, complq); 1954 1955 timeout = jiffies + msecs_to_jiffies(IDPF_WAIT_FOR_MARKER_TIMEO); 1956 1957 do { 1958 struct idpf_splitq_4b_tx_compl_desc *tx_desc; 1959 struct idpf_tx_queue *target; 1960 u32 ctype_gen, id; 1961 1962 tx_desc = flow ? &complq->comp[ntc].common : 1963 &complq->comp_4b[ntc]; 1964 ctype_gen = le16_to_cpu(tx_desc->qid_comptype_gen); 1965 1966 if (!!(ctype_gen & IDPF_TXD_COMPLQ_GEN_M) != gen_flag) { 1967 usleep_range(500, 1000); 1968 continue; 1969 } 1970 1971 if (FIELD_GET(IDPF_TXD_COMPLQ_COMPL_TYPE_M, ctype_gen) != 1972 IDPF_TXD_COMPLT_SW_MARKER) 1973 goto next; 1974 1975 id = FIELD_GET(IDPF_TXD_COMPLQ_QID_M, ctype_gen); 1976 target = complq->txq_grp->txqs[id]; 1977 1978 idpf_queue_clear(SW_MARKER, target); 1979 if (target == txq) 1980 break; 1981 1982 next: 1983 if (unlikely(++ntc == complq->desc_count)) { 1984 ntc = 0; 1985 gen_flag = !gen_flag; 1986 } 1987 } while (time_before(jiffies, timeout)); 1988 1989 idpf_queue_assign(GEN_CHK, complq, gen_flag); 1990 complq->next_to_clean = ntc; 1991 } 1992 1993 /** 1994 * idpf_tx_splitq_build_ctb - populate command tag and size for queue 1995 * based scheduling descriptors 1996 * @desc: descriptor to populate 1997 * @params: pointer to tx params struct 1998 * @td_cmd: command to be filled in desc 1999 * @size: size of buffer 2000 */ 2001 void idpf_tx_splitq_build_ctb(union idpf_tx_flex_desc *desc, 2002 struct idpf_tx_splitq_params *params, 2003 u16 td_cmd, u16 size) 2004 { 2005 desc->q.qw1.cmd_dtype = 2006 le16_encode_bits(params->dtype, IDPF_FLEX_TXD_QW1_DTYPE_M); 2007 desc->q.qw1.cmd_dtype |= 2008 le16_encode_bits(td_cmd, IDPF_FLEX_TXD_QW1_CMD_M); 2009 desc->q.qw1.buf_size = cpu_to_le16(size); 2010 desc->q.qw1.l2tags.l2tag1 = cpu_to_le16(params->td_tag); 2011 } 2012 2013 /** 2014 * idpf_tx_splitq_build_flow_desc - populate command tag and size for flow 2015 * scheduling descriptors 2016 * @desc: descriptor to populate 2017 * @params: pointer to tx params struct 2018 * @td_cmd: command to be filled in desc 2019 * @size: size of buffer 2020 */ 2021 void idpf_tx_splitq_build_flow_desc(union idpf_tx_flex_desc *desc, 2022 struct idpf_tx_splitq_params *params, 2023 u16 td_cmd, u16 size) 2024 { 2025 *(u32 *)&desc->flow.qw1.cmd_dtype = (u8)(params->dtype | td_cmd); 2026 desc->flow.qw1.rxr_bufsize = cpu_to_le16((u16)size); 2027 desc->flow.qw1.compl_tag = cpu_to_le16(params->compl_tag); 2028 } 2029 2030 /** 2031 * idpf_tx_splitq_has_room - check if enough Tx splitq resources are available 2032 * @tx_q: the queue to be checked 2033 * @descs_needed: number of descriptors required for this packet 2034 * @bufs_needed: number of Tx buffers required for this packet 2035 * 2036 * Return: 0 if no room available, 1 otherwise 2037 */ 2038 static int idpf_txq_has_room(struct idpf_tx_queue *tx_q, u32 descs_needed, 2039 u32 bufs_needed) 2040 { 2041 if (IDPF_DESC_UNUSED(tx_q) < descs_needed || 2042 IDPF_TX_COMPLQ_PENDING(tx_q->txq_grp) > 2043 IDPF_TX_COMPLQ_OVERFLOW_THRESH(tx_q->txq_grp->complq) || 2044 idpf_tx_splitq_get_free_bufs(tx_q->refillq) < bufs_needed) 2045 return 0; 2046 return 1; 2047 } 2048 2049 /** 2050 * idpf_tx_maybe_stop_splitq - 1st level check for Tx splitq stop conditions 2051 * @tx_q: the queue to be checked 2052 * @descs_needed: number of descriptors required for this packet 2053 * @bufs_needed: number of buffers needed for this packet 2054 * 2055 * Return: 0 if stop is not needed 2056 */ 2057 static int idpf_tx_maybe_stop_splitq(struct idpf_tx_queue *tx_q, 2058 u32 descs_needed, 2059 u32 bufs_needed) 2060 { 2061 /* Since we have multiple resources to check for splitq, our 2062 * start,stop_thrs becomes a boolean check instead of a count 2063 * threshold. 2064 */ 2065 if (netif_subqueue_maybe_stop(tx_q->netdev, tx_q->idx, 2066 idpf_txq_has_room(tx_q, descs_needed, 2067 bufs_needed), 2068 1, 1)) 2069 return 0; 2070 2071 u64_stats_update_begin(&tx_q->stats_sync); 2072 u64_stats_inc(&tx_q->q_stats.q_busy); 2073 u64_stats_update_end(&tx_q->stats_sync); 2074 2075 return -EBUSY; 2076 } 2077 2078 /** 2079 * idpf_tx_buf_hw_update - Store the new tail value 2080 * @tx_q: queue to bump 2081 * @val: new tail index 2082 * @xmit_more: more skb's pending 2083 * 2084 * The naming here is special in that 'hw' signals that this function is about 2085 * to do a register write to update our queue status. We know this can only 2086 * mean tail here as HW should be owning head for TX. 2087 */ 2088 void idpf_tx_buf_hw_update(struct idpf_tx_queue *tx_q, u32 val, 2089 bool xmit_more) 2090 { 2091 struct netdev_queue *nq; 2092 2093 nq = netdev_get_tx_queue(tx_q->netdev, tx_q->idx); 2094 tx_q->next_to_use = val; 2095 2096 /* Force memory writes to complete before letting h/w 2097 * know there are new descriptors to fetch. (Only 2098 * applicable for weak-ordered memory model archs, 2099 * such as IA-64). 2100 */ 2101 wmb(); 2102 2103 /* notify HW of packet */ 2104 if (netif_xmit_stopped(nq) || !xmit_more) 2105 writel(val, tx_q->tail); 2106 } 2107 2108 /** 2109 * idpf_tx_res_count_required - get number of Tx resources needed for this pkt 2110 * @txq: queue to send buffer on 2111 * @skb: send buffer 2112 * @bufs_needed: (output) number of buffers needed for this skb. 2113 * 2114 * Return: number of data descriptors and buffers needed for this skb. 2115 */ 2116 unsigned int idpf_tx_res_count_required(struct idpf_tx_queue *txq, 2117 struct sk_buff *skb, 2118 u32 *bufs_needed) 2119 { 2120 const struct skb_shared_info *shinfo; 2121 unsigned int count = 0, i; 2122 2123 count += !!skb_headlen(skb); 2124 2125 if (!skb_is_nonlinear(skb)) 2126 return count; 2127 2128 shinfo = skb_shinfo(skb); 2129 *bufs_needed += shinfo->nr_frags; 2130 for (i = 0; i < shinfo->nr_frags; i++) { 2131 unsigned int size; 2132 2133 size = skb_frag_size(&shinfo->frags[i]); 2134 2135 /* We only need to use the idpf_size_to_txd_count check if the 2136 * fragment is going to span multiple descriptors, 2137 * i.e. size >= 16K. 2138 */ 2139 if (size >= SZ_16K) 2140 count += idpf_size_to_txd_count(size); 2141 else 2142 count++; 2143 } 2144 2145 if (idpf_chk_linearize(skb, txq->tx_max_bufs, count)) { 2146 if (__skb_linearize(skb)) 2147 return 0; 2148 2149 count = idpf_size_to_txd_count(skb->len); 2150 u64_stats_update_begin(&txq->stats_sync); 2151 u64_stats_inc(&txq->q_stats.linearize); 2152 u64_stats_update_end(&txq->stats_sync); 2153 } 2154 2155 return count; 2156 } 2157 2158 /** 2159 * idpf_tx_splitq_bump_ntu - adjust NTU and generation 2160 * @txq: the tx ring to wrap 2161 * @ntu: ring index to bump 2162 */ 2163 static unsigned int idpf_tx_splitq_bump_ntu(struct idpf_tx_queue *txq, u16 ntu) 2164 { 2165 ntu++; 2166 2167 if (ntu == txq->desc_count) 2168 ntu = 0; 2169 2170 return ntu; 2171 } 2172 2173 /** 2174 * idpf_tx_get_free_buf_id - get a free buffer ID from the refill queue 2175 * @refillq: refill queue to get buffer ID from 2176 * @buf_id: return buffer ID 2177 * 2178 * Return: true if a buffer ID was found, false if not 2179 */ 2180 static bool idpf_tx_get_free_buf_id(struct idpf_sw_queue *refillq, 2181 u32 *buf_id) 2182 { 2183 u32 ntc = refillq->next_to_clean; 2184 u32 refill_desc; 2185 2186 refill_desc = refillq->ring[ntc]; 2187 2188 if (unlikely(idpf_queue_has(RFL_GEN_CHK, refillq) != 2189 !!(refill_desc & IDPF_RFL_BI_GEN_M))) 2190 return false; 2191 2192 *buf_id = FIELD_GET(IDPF_RFL_BI_BUFID_M, refill_desc); 2193 2194 if (unlikely(++ntc == refillq->desc_count)) { 2195 idpf_queue_change(RFL_GEN_CHK, refillq); 2196 ntc = 0; 2197 } 2198 2199 refillq->next_to_clean = ntc; 2200 2201 return true; 2202 } 2203 2204 /** 2205 * idpf_tx_splitq_pkt_err_unmap - Unmap buffers and bump tail in case of error 2206 * @txq: Tx queue to unwind 2207 * @params: pointer to splitq params struct 2208 * @first: starting buffer for packet to unmap 2209 */ 2210 static void idpf_tx_splitq_pkt_err_unmap(struct idpf_tx_queue *txq, 2211 struct idpf_tx_splitq_params *params, 2212 struct idpf_tx_buf *first) 2213 { 2214 struct idpf_sw_queue *refillq = txq->refillq; 2215 struct libeth_sq_napi_stats ss = { }; 2216 struct idpf_tx_buf *tx_buf = first; 2217 struct libeth_cq_pp cp = { 2218 .dev = txq->dev, 2219 .ss = &ss, 2220 }; 2221 2222 u64_stats_update_begin(&txq->stats_sync); 2223 u64_stats_inc(&txq->q_stats.dma_map_errs); 2224 u64_stats_update_end(&txq->stats_sync); 2225 2226 libeth_tx_complete(tx_buf, &cp); 2227 while (idpf_tx_buf_next(tx_buf) != IDPF_TXBUF_NULL) { 2228 tx_buf = &txq->tx_buf[idpf_tx_buf_next(tx_buf)]; 2229 libeth_tx_complete(tx_buf, &cp); 2230 } 2231 2232 /* Update tail in case netdev_xmit_more was previously true. */ 2233 idpf_tx_buf_hw_update(txq, params->prev_ntu, false); 2234 2235 if (!refillq) 2236 return; 2237 2238 /* Restore refillq state to avoid leaking tags. */ 2239 if (params->prev_refill_gen != idpf_queue_has(RFL_GEN_CHK, refillq)) 2240 idpf_queue_change(RFL_GEN_CHK, refillq); 2241 refillq->next_to_clean = params->prev_refill_ntc; 2242 } 2243 2244 /** 2245 * idpf_tx_splitq_map - Build the Tx flex descriptor 2246 * @tx_q: queue to send buffer on 2247 * @params: pointer to splitq params struct 2248 * @first: first buffer info buffer to use 2249 * 2250 * This function loops over the skb data pointed to by *first 2251 * and gets a physical address for each memory location and programs 2252 * it and the length into the transmit flex descriptor. 2253 */ 2254 static void idpf_tx_splitq_map(struct idpf_tx_queue *tx_q, 2255 struct idpf_tx_splitq_params *params, 2256 struct idpf_tx_buf *first) 2257 { 2258 union idpf_tx_flex_desc *tx_desc; 2259 unsigned int data_len, size; 2260 struct idpf_tx_buf *tx_buf; 2261 u16 i = tx_q->next_to_use; 2262 struct netdev_queue *nq; 2263 struct sk_buff *skb; 2264 skb_frag_t *frag; 2265 u32 next_buf_id; 2266 u16 td_cmd = 0; 2267 dma_addr_t dma; 2268 2269 skb = first->skb; 2270 2271 td_cmd = params->offload.td_cmd; 2272 2273 data_len = skb->data_len; 2274 size = skb_headlen(skb); 2275 2276 tx_desc = &tx_q->flex_tx[i]; 2277 2278 dma = dma_map_single(tx_q->dev, skb->data, size, DMA_TO_DEVICE); 2279 2280 tx_buf = first; 2281 first->nr_frags = 0; 2282 2283 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2284 unsigned int max_data = IDPF_TX_MAX_DESC_DATA_ALIGNED; 2285 2286 if (unlikely(dma_mapping_error(tx_q->dev, dma))) { 2287 idpf_tx_buf_next(tx_buf) = IDPF_TXBUF_NULL; 2288 return idpf_tx_splitq_pkt_err_unmap(tx_q, params, 2289 first); 2290 } 2291 2292 first->nr_frags++; 2293 tx_buf->type = LIBETH_SQE_FRAG; 2294 2295 /* record length, and DMA address */ 2296 dma_unmap_len_set(tx_buf, len, size); 2297 dma_unmap_addr_set(tx_buf, dma, dma); 2298 2299 /* buf_addr is in same location for both desc types */ 2300 tx_desc->q.buf_addr = cpu_to_le64(dma); 2301 2302 /* The stack can send us fragments that are too large for a 2303 * single descriptor i.e. frag size > 16K-1. We will need to 2304 * split the fragment across multiple descriptors in this case. 2305 * To adhere to HW alignment restrictions, the fragment needs 2306 * to be split such that the first chunk ends on a 4K boundary 2307 * and all subsequent chunks start on a 4K boundary. We still 2308 * want to send as much data as possible though, so our 2309 * intermediate descriptor chunk size will be 12K. 2310 * 2311 * For example, consider a 32K fragment mapped to DMA addr 2600. 2312 * ------------------------------------------------------------ 2313 * | frag_size = 32K | 2314 * ------------------------------------------------------------ 2315 * |2600 |16384 |28672 2316 * 2317 * 3 descriptors will be used for this fragment. The HW expects 2318 * the descriptors to contain the following: 2319 * ------------------------------------------------------------ 2320 * | size = 13784 | size = 12K | size = 6696 | 2321 * | dma = 2600 | dma = 16384 | dma = 28672 | 2322 * ------------------------------------------------------------ 2323 * 2324 * We need to first adjust the max_data for the first chunk so 2325 * that it ends on a 4K boundary. By negating the value of the 2326 * DMA address and taking only the low order bits, we're 2327 * effectively calculating 2328 * 4K - (DMA addr lower order bits) = 2329 * bytes to next boundary. 2330 * 2331 * Add that to our base aligned max_data (12K) and we have 2332 * our first chunk size. In the example above, 2333 * 13784 = 12K + (4096-2600) 2334 * 2335 * After guaranteeing the first chunk ends on a 4K boundary, we 2336 * will give the intermediate descriptors 12K chunks and 2337 * whatever is left to the final descriptor. This ensures that 2338 * all descriptors used for the remaining chunks of the 2339 * fragment start on a 4K boundary and we use as few 2340 * descriptors as possible. 2341 */ 2342 max_data += -dma & (IDPF_TX_MAX_READ_REQ_SIZE - 1); 2343 while (unlikely(size > IDPF_TX_MAX_DESC_DATA)) { 2344 idpf_tx_splitq_build_desc(tx_desc, params, td_cmd, 2345 max_data); 2346 2347 if (unlikely(++i == tx_q->desc_count)) { 2348 tx_desc = &tx_q->flex_tx[0]; 2349 i = 0; 2350 } else { 2351 tx_desc++; 2352 } 2353 2354 /* Adjust the DMA offset and the remaining size of the 2355 * fragment. On the first iteration of this loop, 2356 * max_data will be >= 12K and <= 16K-1. On any 2357 * subsequent iteration of this loop, max_data will 2358 * always be 12K. 2359 */ 2360 dma += max_data; 2361 size -= max_data; 2362 2363 /* Reset max_data since remaining chunks will be 12K 2364 * at most 2365 */ 2366 max_data = IDPF_TX_MAX_DESC_DATA_ALIGNED; 2367 2368 /* buf_addr is in same location for both desc types */ 2369 tx_desc->q.buf_addr = cpu_to_le64(dma); 2370 } 2371 2372 if (!data_len) 2373 break; 2374 2375 idpf_tx_splitq_build_desc(tx_desc, params, td_cmd, size); 2376 2377 if (unlikely(++i == tx_q->desc_count)) { 2378 tx_desc = &tx_q->flex_tx[0]; 2379 i = 0; 2380 } else { 2381 tx_desc++; 2382 } 2383 2384 if (idpf_queue_has(FLOW_SCH_EN, tx_q)) { 2385 if (unlikely(!idpf_tx_get_free_buf_id(tx_q->refillq, 2386 &next_buf_id))) { 2387 idpf_tx_buf_next(tx_buf) = IDPF_TXBUF_NULL; 2388 return idpf_tx_splitq_pkt_err_unmap(tx_q, params, 2389 first); 2390 } 2391 } else { 2392 next_buf_id = i; 2393 } 2394 idpf_tx_buf_next(tx_buf) = next_buf_id; 2395 tx_buf = &tx_q->tx_buf[next_buf_id]; 2396 2397 size = skb_frag_size(frag); 2398 data_len -= size; 2399 2400 dma = skb_frag_dma_map(tx_q->dev, frag, 0, size, 2401 DMA_TO_DEVICE); 2402 } 2403 2404 /* record SW timestamp if HW timestamp is not available */ 2405 skb_tx_timestamp(skb); 2406 2407 first->type = LIBETH_SQE_SKB; 2408 2409 /* write last descriptor with RS and EOP bits */ 2410 first->rs_idx = i; 2411 idpf_tx_buf_next(tx_buf) = IDPF_TXBUF_NULL; 2412 td_cmd |= params->eop_cmd; 2413 idpf_tx_splitq_build_desc(tx_desc, params, td_cmd, size); 2414 i = idpf_tx_splitq_bump_ntu(tx_q, i); 2415 2416 tx_q->txq_grp->num_completions_pending++; 2417 2418 /* record bytecount for BQL */ 2419 nq = netdev_get_tx_queue(tx_q->netdev, tx_q->idx); 2420 netdev_tx_sent_queue(nq, first->bytes); 2421 2422 idpf_tx_buf_hw_update(tx_q, i, netdev_xmit_more()); 2423 } 2424 2425 /** 2426 * idpf_tso - computes mss and TSO length to prepare for TSO 2427 * @skb: pointer to skb 2428 * @off: pointer to struct that holds offload parameters 2429 * 2430 * Returns error (negative) if TSO was requested but cannot be applied to the 2431 * given skb, 0 if TSO does not apply to the given skb, or 1 otherwise. 2432 */ 2433 int idpf_tso(struct sk_buff *skb, struct idpf_tx_offload_params *off) 2434 { 2435 const struct skb_shared_info *shinfo; 2436 union { 2437 struct iphdr *v4; 2438 struct ipv6hdr *v6; 2439 unsigned char *hdr; 2440 } ip; 2441 union { 2442 struct tcphdr *tcp; 2443 struct udphdr *udp; 2444 unsigned char *hdr; 2445 } l4; 2446 u32 paylen, l4_start; 2447 int err; 2448 2449 if (!skb_is_gso(skb)) 2450 return 0; 2451 2452 err = skb_cow_head(skb, 0); 2453 if (err < 0) 2454 return err; 2455 2456 shinfo = skb_shinfo(skb); 2457 2458 ip.hdr = skb_network_header(skb); 2459 l4.hdr = skb_transport_header(skb); 2460 2461 /* initialize outer IP header fields */ 2462 if (ip.v4->version == 4) { 2463 ip.v4->tot_len = 0; 2464 ip.v4->check = 0; 2465 } else if (ip.v6->version == 6) { 2466 ip.v6->payload_len = 0; 2467 } 2468 2469 l4_start = skb_transport_offset(skb); 2470 2471 /* remove payload length from checksum */ 2472 paylen = skb->len - l4_start; 2473 2474 switch (shinfo->gso_type & ~SKB_GSO_DODGY) { 2475 case SKB_GSO_TCPV4: 2476 case SKB_GSO_TCPV6: 2477 csum_replace_by_diff(&l4.tcp->check, 2478 (__force __wsum)htonl(paylen)); 2479 off->tso_hdr_len = __tcp_hdrlen(l4.tcp) + l4_start; 2480 break; 2481 case SKB_GSO_UDP_L4: 2482 csum_replace_by_diff(&l4.udp->check, 2483 (__force __wsum)htonl(paylen)); 2484 /* compute length of segmentation header */ 2485 off->tso_hdr_len = sizeof(struct udphdr) + l4_start; 2486 l4.udp->len = htons(shinfo->gso_size + sizeof(struct udphdr)); 2487 break; 2488 default: 2489 return -EINVAL; 2490 } 2491 2492 off->tso_len = skb->len - off->tso_hdr_len; 2493 off->mss = shinfo->gso_size; 2494 off->tso_segs = shinfo->gso_segs; 2495 2496 off->tx_flags |= IDPF_TX_FLAGS_TSO; 2497 2498 return 1; 2499 } 2500 2501 2502 /** 2503 * idpf_tx_splitq_get_ctx_desc - grab next desc and update buffer ring 2504 * @txq: queue to put context descriptor on 2505 * 2506 * Since the TX buffer rings mimics the descriptor ring, update the tx buffer 2507 * ring entry to reflect that this index is a context descriptor 2508 */ 2509 static union idpf_flex_tx_ctx_desc * 2510 idpf_tx_splitq_get_ctx_desc(struct idpf_tx_queue *txq) 2511 { 2512 union idpf_flex_tx_ctx_desc *desc; 2513 int i = txq->next_to_use; 2514 2515 /* grab the next descriptor */ 2516 desc = &txq->flex_ctx[i]; 2517 txq->next_to_use = idpf_tx_splitq_bump_ntu(txq, i); 2518 2519 return desc; 2520 } 2521 2522 /** 2523 * idpf_tx_drop_skb - free the SKB and bump tail if necessary 2524 * @tx_q: queue to send buffer on 2525 * @skb: pointer to skb 2526 */ 2527 netdev_tx_t idpf_tx_drop_skb(struct idpf_tx_queue *tx_q, struct sk_buff *skb) 2528 { 2529 u64_stats_update_begin(&tx_q->stats_sync); 2530 u64_stats_inc(&tx_q->q_stats.skb_drops); 2531 u64_stats_update_end(&tx_q->stats_sync); 2532 2533 idpf_tx_buf_hw_update(tx_q, tx_q->next_to_use, false); 2534 2535 dev_kfree_skb(skb); 2536 2537 return NETDEV_TX_OK; 2538 } 2539 2540 #if (IS_ENABLED(CONFIG_PTP_1588_CLOCK)) 2541 /** 2542 * idpf_tx_tstamp - set up context descriptor for hardware timestamp 2543 * @tx_q: queue to send buffer on 2544 * @skb: pointer to the SKB we're sending 2545 * @off: pointer to the offload struct 2546 * 2547 * Return: Positive index number on success, negative otherwise. 2548 */ 2549 static int idpf_tx_tstamp(struct idpf_tx_queue *tx_q, struct sk_buff *skb, 2550 struct idpf_tx_offload_params *off) 2551 { 2552 int err, idx; 2553 2554 /* only timestamp the outbound packet if the user has requested it */ 2555 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2556 return -1; 2557 2558 if (!idpf_ptp_get_txq_tstamp_capability(tx_q)) 2559 return -1; 2560 2561 /* Tx timestamps cannot be sampled when doing TSO */ 2562 if (off->tx_flags & IDPF_TX_FLAGS_TSO) 2563 return -1; 2564 2565 /* Grab an open timestamp slot */ 2566 err = idpf_ptp_request_ts(tx_q, skb, &idx); 2567 if (err) { 2568 u64_stats_update_begin(&tx_q->stats_sync); 2569 u64_stats_inc(&tx_q->q_stats.tstamp_skipped); 2570 u64_stats_update_end(&tx_q->stats_sync); 2571 2572 return -1; 2573 } 2574 2575 off->tx_flags |= IDPF_TX_FLAGS_TSYN; 2576 2577 return idx; 2578 } 2579 2580 /** 2581 * idpf_tx_set_tstamp_desc - Set the Tx descriptor fields needed to generate 2582 * PHY Tx timestamp 2583 * @ctx_desc: Context descriptor 2584 * @idx: Index of the Tx timestamp latch 2585 */ 2586 static void idpf_tx_set_tstamp_desc(union idpf_flex_tx_ctx_desc *ctx_desc, 2587 u32 idx) 2588 { 2589 ctx_desc->tsyn.qw1 = le64_encode_bits(IDPF_TX_DESC_DTYPE_CTX, 2590 IDPF_TX_CTX_DTYPE_M) | 2591 le64_encode_bits(IDPF_TX_CTX_DESC_TSYN, 2592 IDPF_TX_CTX_CMD_M) | 2593 le64_encode_bits(idx, IDPF_TX_CTX_TSYN_REG_M); 2594 } 2595 #else /* CONFIG_PTP_1588_CLOCK */ 2596 static int idpf_tx_tstamp(struct idpf_tx_queue *tx_q, struct sk_buff *skb, 2597 struct idpf_tx_offload_params *off) 2598 { 2599 return -1; 2600 } 2601 2602 static void idpf_tx_set_tstamp_desc(union idpf_flex_tx_ctx_desc *ctx_desc, 2603 u32 idx) 2604 { } 2605 #endif /* CONFIG_PTP_1588_CLOCK */ 2606 2607 /** 2608 * idpf_tx_splitq_need_re - check whether RE bit needs to be set 2609 * @tx_q: pointer to Tx queue 2610 * 2611 * Return: true if RE bit needs to be set, false otherwise 2612 */ 2613 static bool idpf_tx_splitq_need_re(struct idpf_tx_queue *tx_q) 2614 { 2615 int gap = tx_q->next_to_use - tx_q->last_re; 2616 2617 gap += (gap < 0) ? tx_q->desc_count : 0; 2618 2619 return gap >= IDPF_TX_SPLITQ_RE_MIN_GAP; 2620 } 2621 2622 /** 2623 * idpf_tx_splitq_frame - Sends buffer on Tx ring using flex descriptors 2624 * @skb: send buffer 2625 * @tx_q: queue to send buffer on 2626 * 2627 * Returns NETDEV_TX_OK if sent, else an error code 2628 */ 2629 static netdev_tx_t idpf_tx_splitq_frame(struct sk_buff *skb, 2630 struct idpf_tx_queue *tx_q) 2631 { 2632 struct idpf_tx_splitq_params tx_params = { 2633 .prev_ntu = tx_q->next_to_use, 2634 }; 2635 union idpf_flex_tx_ctx_desc *ctx_desc; 2636 struct idpf_tx_buf *first; 2637 u32 count, buf_count = 1; 2638 int tso, idx; 2639 u32 buf_id; 2640 2641 count = idpf_tx_res_count_required(tx_q, skb, &buf_count); 2642 if (unlikely(!count)) 2643 return idpf_tx_drop_skb(tx_q, skb); 2644 2645 tso = idpf_tso(skb, &tx_params.offload); 2646 if (unlikely(tso < 0)) 2647 return idpf_tx_drop_skb(tx_q, skb); 2648 2649 /* Check for splitq specific TX resources */ 2650 count += (IDPF_TX_DESCS_PER_CACHE_LINE + tso); 2651 if (idpf_tx_maybe_stop_splitq(tx_q, count, buf_count)) { 2652 idpf_tx_buf_hw_update(tx_q, tx_q->next_to_use, false); 2653 2654 return NETDEV_TX_BUSY; 2655 } 2656 2657 if (tso) { 2658 /* If tso is needed, set up context desc */ 2659 ctx_desc = idpf_tx_splitq_get_ctx_desc(tx_q); 2660 2661 ctx_desc->tso.qw1.cmd_dtype = 2662 cpu_to_le16(IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX | 2663 IDPF_TX_FLEX_CTX_DESC_CMD_TSO); 2664 ctx_desc->tso.qw0.flex_tlen = 2665 cpu_to_le32(tx_params.offload.tso_len & 2666 IDPF_TXD_FLEX_CTX_TLEN_M); 2667 ctx_desc->tso.qw0.mss_rt = 2668 cpu_to_le16(tx_params.offload.mss & 2669 IDPF_TXD_FLEX_CTX_MSS_RT_M); 2670 ctx_desc->tso.qw0.hdr_len = tx_params.offload.tso_hdr_len; 2671 2672 u64_stats_update_begin(&tx_q->stats_sync); 2673 u64_stats_inc(&tx_q->q_stats.lso_pkts); 2674 u64_stats_update_end(&tx_q->stats_sync); 2675 } 2676 2677 idx = idpf_tx_tstamp(tx_q, skb, &tx_params.offload); 2678 if (idx != -1) { 2679 ctx_desc = idpf_tx_splitq_get_ctx_desc(tx_q); 2680 idpf_tx_set_tstamp_desc(ctx_desc, idx); 2681 } 2682 2683 if (idpf_queue_has(FLOW_SCH_EN, tx_q)) { 2684 struct idpf_sw_queue *refillq = tx_q->refillq; 2685 2686 /* Save refillq state in case of a packet rollback. Otherwise, 2687 * the tags will be leaked since they will be popped from the 2688 * refillq but never reposted during cleaning. 2689 */ 2690 tx_params.prev_refill_gen = 2691 idpf_queue_has(RFL_GEN_CHK, refillq); 2692 tx_params.prev_refill_ntc = refillq->next_to_clean; 2693 2694 if (unlikely(!idpf_tx_get_free_buf_id(tx_q->refillq, 2695 &buf_id))) { 2696 if (tx_params.prev_refill_gen != 2697 idpf_queue_has(RFL_GEN_CHK, refillq)) 2698 idpf_queue_change(RFL_GEN_CHK, refillq); 2699 refillq->next_to_clean = tx_params.prev_refill_ntc; 2700 2701 tx_q->next_to_use = tx_params.prev_ntu; 2702 return idpf_tx_drop_skb(tx_q, skb); 2703 } 2704 tx_params.compl_tag = buf_id; 2705 2706 tx_params.dtype = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE; 2707 tx_params.eop_cmd = IDPF_TXD_FLEX_FLOW_CMD_EOP; 2708 /* Set the RE bit to periodically "clean" the descriptor ring. 2709 * MIN_GAP is set to MIN_RING size to ensure it will be set at 2710 * least once each time around the ring. 2711 */ 2712 if (idpf_tx_splitq_need_re(tx_q)) { 2713 tx_params.eop_cmd |= IDPF_TXD_FLEX_FLOW_CMD_RE; 2714 tx_q->txq_grp->num_completions_pending++; 2715 tx_q->last_re = tx_q->next_to_use; 2716 } 2717 2718 if (skb->ip_summed == CHECKSUM_PARTIAL) 2719 tx_params.offload.td_cmd |= IDPF_TXD_FLEX_FLOW_CMD_CS_EN; 2720 2721 } else { 2722 buf_id = tx_q->next_to_use; 2723 2724 tx_params.dtype = IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2; 2725 tx_params.eop_cmd = IDPF_TXD_LAST_DESC_CMD; 2726 2727 if (skb->ip_summed == CHECKSUM_PARTIAL) 2728 tx_params.offload.td_cmd |= IDPF_TX_FLEX_DESC_CMD_CS_EN; 2729 } 2730 2731 first = &tx_q->tx_buf[buf_id]; 2732 first->skb = skb; 2733 2734 if (tso) { 2735 first->packets = tx_params.offload.tso_segs; 2736 first->bytes = skb->len + 2737 ((first->packets - 1) * tx_params.offload.tso_hdr_len); 2738 } else { 2739 first->packets = 1; 2740 first->bytes = max_t(unsigned int, skb->len, ETH_ZLEN); 2741 } 2742 2743 idpf_tx_splitq_map(tx_q, &tx_params, first); 2744 2745 return NETDEV_TX_OK; 2746 } 2747 2748 /** 2749 * idpf_tx_start - Selects the right Tx queue to send buffer 2750 * @skb: send buffer 2751 * @netdev: network interface device structure 2752 * 2753 * Returns NETDEV_TX_OK if sent, else an error code 2754 */ 2755 netdev_tx_t idpf_tx_start(struct sk_buff *skb, struct net_device *netdev) 2756 { 2757 const struct idpf_vport *vport = idpf_netdev_to_vport(netdev); 2758 struct idpf_tx_queue *tx_q; 2759 2760 if (unlikely(skb_get_queue_mapping(skb) >= 2761 vport->num_txq - vport->num_xdp_txq)) { 2762 dev_kfree_skb_any(skb); 2763 2764 return NETDEV_TX_OK; 2765 } 2766 2767 tx_q = vport->txqs[skb_get_queue_mapping(skb)]; 2768 2769 /* hardware can't handle really short frames, hardware padding works 2770 * beyond this point 2771 */ 2772 if (skb_put_padto(skb, tx_q->tx_min_pkt_len)) { 2773 idpf_tx_buf_hw_update(tx_q, tx_q->next_to_use, false); 2774 2775 return NETDEV_TX_OK; 2776 } 2777 2778 if (idpf_is_queue_model_split(vport->txq_model)) 2779 return idpf_tx_splitq_frame(skb, tx_q); 2780 else 2781 return idpf_tx_singleq_frame(skb, tx_q); 2782 } 2783 2784 /** 2785 * idpf_rx_hash - set the hash value in the skb 2786 * @rxq: Rx descriptor ring packet is being transacted on 2787 * @skb: pointer to current skb being populated 2788 * @rx_desc: Receive descriptor 2789 * @decoded: Decoded Rx packet type related fields 2790 */ 2791 static void 2792 idpf_rx_hash(const struct idpf_rx_queue *rxq, struct sk_buff *skb, 2793 const struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc, 2794 struct libeth_rx_pt decoded) 2795 { 2796 u32 hash; 2797 2798 if (!libeth_rx_pt_has_hash(rxq->xdp_rxq.dev, decoded)) 2799 return; 2800 2801 hash = le16_to_cpu(rx_desc->hash1) | 2802 (rx_desc->ff2_mirrid_hash2.hash2 << 16) | 2803 (rx_desc->hash3 << 24); 2804 2805 libeth_rx_pt_set_hash(skb, hash, decoded); 2806 } 2807 2808 /** 2809 * idpf_rx_csum - Indicate in skb if checksum is good 2810 * @rxq: Rx descriptor ring packet is being transacted on 2811 * @skb: pointer to current skb being populated 2812 * @csum_bits: checksum fields extracted from the descriptor 2813 * @decoded: Decoded Rx packet type related fields 2814 * 2815 * skb->protocol must be set before this function is called 2816 */ 2817 static void idpf_rx_csum(struct idpf_rx_queue *rxq, struct sk_buff *skb, 2818 struct libeth_rx_csum csum_bits, 2819 struct libeth_rx_pt decoded) 2820 { 2821 bool ipv4, ipv6; 2822 2823 /* check if Rx checksum is enabled */ 2824 if (!libeth_rx_pt_has_checksum(rxq->xdp_rxq.dev, decoded)) 2825 return; 2826 2827 /* check if HW has decoded the packet and checksum */ 2828 if (unlikely(!csum_bits.l3l4p)) 2829 return; 2830 2831 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4; 2832 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6; 2833 2834 if (unlikely(ipv4 && (csum_bits.ipe || csum_bits.eipe))) 2835 goto checksum_fail; 2836 2837 if (unlikely(ipv6 && csum_bits.ipv6exadd)) 2838 return; 2839 2840 /* check for L4 errors and handle packets that were not able to be 2841 * checksummed 2842 */ 2843 if (unlikely(csum_bits.l4e)) 2844 goto checksum_fail; 2845 2846 if (!csum_bits.raw_csum_valid || 2847 decoded.inner_prot == LIBETH_RX_PT_INNER_SCTP) { 2848 skb->ip_summed = CHECKSUM_UNNECESSARY; 2849 return; 2850 } 2851 2852 skb->csum = csum_unfold((__force __sum16)~swab16(csum_bits.raw_csum)); 2853 skb->ip_summed = CHECKSUM_COMPLETE; 2854 2855 return; 2856 2857 checksum_fail: 2858 u64_stats_update_begin(&rxq->stats_sync); 2859 u64_stats_inc(&rxq->q_stats.hw_csum_err); 2860 u64_stats_update_end(&rxq->stats_sync); 2861 } 2862 2863 /** 2864 * idpf_rx_splitq_extract_csum_bits - Extract checksum bits from descriptor 2865 * @rx_desc: receive descriptor 2866 * 2867 * Return: parsed checksum status. 2868 **/ 2869 static struct libeth_rx_csum 2870 idpf_rx_splitq_extract_csum_bits(const struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc) 2871 { 2872 struct libeth_rx_csum csum = { }; 2873 u8 qword0, qword1; 2874 2875 qword0 = rx_desc->status_err0_qw0; 2876 qword1 = rx_desc->status_err0_qw1; 2877 2878 csum.ipe = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_M, 2879 qword1); 2880 csum.eipe = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_M, 2881 qword1); 2882 csum.l4e = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_M, 2883 qword1); 2884 csum.l3l4p = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L3L4P_M, 2885 qword1); 2886 csum.ipv6exadd = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_M, 2887 qword0); 2888 csum.raw_csum_valid = 2889 !le16_get_bits(rx_desc->ptype_err_fflags0, 2890 VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M); 2891 csum.raw_csum = le16_to_cpu(rx_desc->misc.raw_cs); 2892 2893 return csum; 2894 } 2895 2896 /** 2897 * idpf_rx_rsc - Set the RSC fields in the skb 2898 * @rxq : Rx descriptor ring packet is being transacted on 2899 * @skb : pointer to current skb being populated 2900 * @rx_desc: Receive descriptor 2901 * @decoded: Decoded Rx packet type related fields 2902 * 2903 * Return 0 on success and error code on failure 2904 * 2905 * Populate the skb fields with the total number of RSC segments, RSC payload 2906 * length and packet type. 2907 */ 2908 static int idpf_rx_rsc(struct idpf_rx_queue *rxq, struct sk_buff *skb, 2909 const struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc, 2910 struct libeth_rx_pt decoded) 2911 { 2912 u16 rsc_segments, rsc_seg_len; 2913 bool ipv4, ipv6; 2914 int len; 2915 2916 if (unlikely(libeth_rx_pt_get_ip_ver(decoded) == 2917 LIBETH_RX_PT_OUTER_L2)) 2918 return -EINVAL; 2919 2920 rsc_seg_len = le16_to_cpu(rx_desc->misc.rscseglen); 2921 if (unlikely(!rsc_seg_len)) 2922 return -EINVAL; 2923 2924 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4; 2925 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6; 2926 2927 if (unlikely(!(ipv4 ^ ipv6))) 2928 return -EINVAL; 2929 2930 rsc_segments = DIV_ROUND_UP(skb->data_len, rsc_seg_len); 2931 2932 NAPI_GRO_CB(skb)->count = rsc_segments; 2933 skb_shinfo(skb)->gso_size = rsc_seg_len; 2934 2935 skb_reset_network_header(skb); 2936 2937 if (ipv4) { 2938 struct iphdr *ipv4h = ip_hdr(skb); 2939 2940 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2941 2942 /* Reset and set transport header offset in skb */ 2943 skb_set_transport_header(skb, sizeof(struct iphdr)); 2944 len = skb->len - skb_transport_offset(skb); 2945 2946 /* Compute the TCP pseudo header checksum*/ 2947 tcp_hdr(skb)->check = 2948 ~tcp_v4_check(len, ipv4h->saddr, ipv4h->daddr, 0); 2949 } else { 2950 struct ipv6hdr *ipv6h = ipv6_hdr(skb); 2951 2952 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2953 skb_set_transport_header(skb, sizeof(struct ipv6hdr)); 2954 len = skb->len - skb_transport_offset(skb); 2955 tcp_hdr(skb)->check = 2956 ~tcp_v6_check(len, &ipv6h->saddr, &ipv6h->daddr, 0); 2957 } 2958 2959 tcp_gro_complete(skb); 2960 2961 u64_stats_update_begin(&rxq->stats_sync); 2962 u64_stats_inc(&rxq->q_stats.rsc_pkts); 2963 u64_stats_update_end(&rxq->stats_sync); 2964 2965 return 0; 2966 } 2967 2968 /** 2969 * idpf_rx_hwtstamp - check for an RX timestamp and pass up the stack 2970 * @rxq: pointer to the rx queue that receives the timestamp 2971 * @rx_desc: pointer to rx descriptor containing timestamp 2972 * @skb: skb to put timestamp in 2973 */ 2974 static void 2975 idpf_rx_hwtstamp(const struct idpf_rx_queue *rxq, 2976 const struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc, 2977 struct sk_buff *skb) 2978 { 2979 u64 cached_time, ts_ns; 2980 u32 ts_high; 2981 2982 if (!(rx_desc->ts_low & VIRTCHNL2_RX_FLEX_TSTAMP_VALID)) 2983 return; 2984 2985 cached_time = READ_ONCE(rxq->cached_phc_time); 2986 2987 ts_high = le32_to_cpu(rx_desc->ts_high); 2988 ts_ns = idpf_ptp_tstamp_extend_32b_to_64b(cached_time, ts_high); 2989 2990 *skb_hwtstamps(skb) = (struct skb_shared_hwtstamps) { 2991 .hwtstamp = ns_to_ktime(ts_ns), 2992 }; 2993 } 2994 2995 /** 2996 * __idpf_rx_process_skb_fields - Populate skb header fields from Rx descriptor 2997 * @rxq: Rx descriptor ring packet is being transacted on 2998 * @skb: pointer to current skb being populated 2999 * @rx_desc: Receive descriptor 3000 * 3001 * This function checks the ring, descriptor, and packet information in 3002 * order to populate the hash, checksum, protocol, and 3003 * other fields within the skb. 3004 */ 3005 static int 3006 __idpf_rx_process_skb_fields(struct idpf_rx_queue *rxq, struct sk_buff *skb, 3007 const struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc) 3008 { 3009 struct libeth_rx_csum csum_bits; 3010 struct libeth_rx_pt decoded; 3011 u16 rx_ptype; 3012 3013 rx_ptype = le16_get_bits(rx_desc->ptype_err_fflags0, 3014 VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M); 3015 decoded = rxq->rx_ptype_lkup[rx_ptype]; 3016 3017 /* process RSS/hash */ 3018 idpf_rx_hash(rxq, skb, rx_desc, decoded); 3019 3020 if (idpf_queue_has(PTP, rxq)) 3021 idpf_rx_hwtstamp(rxq, rx_desc, skb); 3022 3023 if (le16_get_bits(rx_desc->hdrlen_flags, 3024 VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M)) 3025 return idpf_rx_rsc(rxq, skb, rx_desc, decoded); 3026 3027 csum_bits = idpf_rx_splitq_extract_csum_bits(rx_desc); 3028 idpf_rx_csum(rxq, skb, csum_bits, decoded); 3029 3030 return 0; 3031 } 3032 3033 static bool idpf_rx_process_skb_fields(struct sk_buff *skb, 3034 const struct libeth_xdp_buff *xdp, 3035 struct libeth_rq_napi_stats *rs) 3036 { 3037 struct idpf_rx_queue *rxq; 3038 3039 rxq = libeth_xdp_buff_to_rq(xdp, typeof(*rxq), xdp_rxq); 3040 3041 return !__idpf_rx_process_skb_fields(rxq, skb, xdp->desc); 3042 } 3043 3044 LIBETH_XDP_DEFINE_START(); 3045 LIBETH_XDP_DEFINE_RUN(static idpf_xdp_run_pass, idpf_xdp_run_prog, 3046 idpf_xdp_tx_flush_bulk, idpf_rx_process_skb_fields); 3047 LIBETH_XDP_DEFINE_FINALIZE(static idpf_xdp_finalize_rx, idpf_xdp_tx_flush_bulk, 3048 idpf_xdp_tx_finalize); 3049 LIBETH_XDP_DEFINE_END(); 3050 3051 /** 3052 * idpf_rx_hsplit_wa - handle header buffer overflows and split errors 3053 * @hdr: Rx buffer for the headers 3054 * @buf: Rx buffer for the payload 3055 * @data_len: number of bytes received to the payload buffer 3056 * 3057 * When a header buffer overflow occurs or the HW was unable do parse the 3058 * packet type to perform header split, the whole frame gets placed to the 3059 * payload buffer. We can't build a valid skb around a payload buffer when 3060 * the header split is active since it doesn't reserve any head- or tailroom. 3061 * In that case, copy either the whole frame when it's short or just the 3062 * Ethernet header to the header buffer to be able to build an skb and adjust 3063 * the data offset in the payload buffer, IOW emulate the header split. 3064 * 3065 * Return: number of bytes copied to the header buffer. 3066 */ 3067 static u32 idpf_rx_hsplit_wa(const struct libeth_fqe *hdr, 3068 struct libeth_fqe *buf, u32 data_len) 3069 { 3070 u32 copy = data_len <= L1_CACHE_BYTES ? data_len : ETH_HLEN; 3071 struct page *hdr_page, *buf_page; 3072 const void *src; 3073 void *dst; 3074 3075 if (unlikely(netmem_is_net_iov(buf->netmem)) || 3076 !libeth_rx_sync_for_cpu(buf, copy)) 3077 return 0; 3078 3079 hdr_page = __netmem_to_page(hdr->netmem); 3080 buf_page = __netmem_to_page(buf->netmem); 3081 dst = page_address(hdr_page) + hdr->offset + 3082 pp_page_to_nmdesc(hdr_page)->pp->p.offset; 3083 src = page_address(buf_page) + buf->offset + 3084 pp_page_to_nmdesc(buf_page)->pp->p.offset; 3085 3086 memcpy(dst, src, LARGEST_ALIGN(copy)); 3087 buf->offset += copy; 3088 3089 return copy; 3090 } 3091 3092 /** 3093 * idpf_rx_splitq_test_staterr - tests bits in Rx descriptor 3094 * status and error fields 3095 * @stat_err_field: field from descriptor to test bits in 3096 * @stat_err_bits: value to mask 3097 * 3098 */ 3099 static bool idpf_rx_splitq_test_staterr(const u8 stat_err_field, 3100 const u8 stat_err_bits) 3101 { 3102 return !!(stat_err_field & stat_err_bits); 3103 } 3104 3105 /** 3106 * idpf_rx_splitq_is_eop - process handling of EOP buffers 3107 * @rx_desc: Rx descriptor for current buffer 3108 * 3109 * If the buffer is an EOP buffer, this function exits returning true, 3110 * otherwise return false indicating that this is in fact a non-EOP buffer. 3111 */ 3112 static bool idpf_rx_splitq_is_eop(struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc) 3113 { 3114 /* if we are the last buffer then there is nothing else to do */ 3115 return likely(idpf_rx_splitq_test_staterr(rx_desc->status_err0_qw1, 3116 IDPF_RXD_EOF_SPLITQ)); 3117 } 3118 3119 /** 3120 * idpf_rx_splitq_clean - Clean completed descriptors from Rx queue 3121 * @rxq: Rx descriptor queue to retrieve receive buffer queue 3122 * @budget: Total limit on number of packets to process 3123 * 3124 * This function provides a "bounce buffer" approach to Rx interrupt 3125 * processing. The advantage to this is that on systems that have 3126 * expensive overhead for IOMMU access this provides a means of avoiding 3127 * it by maintaining the mapping of the page to the system. 3128 * 3129 * Returns amount of work completed 3130 */ 3131 static int idpf_rx_splitq_clean(struct idpf_rx_queue *rxq, int budget) 3132 { 3133 struct idpf_buf_queue *rx_bufq = NULL; 3134 struct libeth_rq_napi_stats rs = { }; 3135 u16 ntc = rxq->next_to_clean; 3136 LIBETH_XDP_ONSTACK_BUFF(xdp); 3137 LIBETH_XDP_ONSTACK_BULK(bq); 3138 3139 libeth_xdp_tx_init_bulk(&bq, rxq->xdp_prog, rxq->xdp_rxq.dev, 3140 rxq->xdpsqs, rxq->num_xdp_txq); 3141 libeth_xdp_init_buff(xdp, &rxq->xdp, &rxq->xdp_rxq); 3142 3143 /* Process Rx packets bounded by budget */ 3144 while (likely(rs.packets < budget)) { 3145 struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc; 3146 struct libeth_fqe *hdr, *rx_buf = NULL; 3147 struct idpf_sw_queue *refillq = NULL; 3148 struct idpf_rxq_set *rxq_set = NULL; 3149 unsigned int pkt_len = 0; 3150 unsigned int hdr_len = 0; 3151 u16 gen_id, buf_id = 0; 3152 int bufq_id; 3153 u8 rxdid; 3154 3155 /* get the Rx desc from Rx queue based on 'next_to_clean' */ 3156 rx_desc = &rxq->rx[ntc].flex_adv_nic_3_wb; 3157 3158 /* if the descriptor isn't done, no work yet to do */ 3159 gen_id = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3160 VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M); 3161 if (idpf_queue_has(GEN_CHK, rxq) != gen_id) 3162 break; 3163 3164 dma_rmb(); 3165 3166 rxdid = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M, 3167 rx_desc->rxdid_ucast); 3168 if (rxdid != VIRTCHNL2_RXDID_2_FLEX_SPLITQ) { 3169 IDPF_RX_BUMP_NTC(rxq, ntc); 3170 u64_stats_update_begin(&rxq->stats_sync); 3171 u64_stats_inc(&rxq->q_stats.bad_descs); 3172 u64_stats_update_end(&rxq->stats_sync); 3173 continue; 3174 } 3175 3176 pkt_len = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3177 VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M); 3178 3179 bufq_id = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3180 VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M); 3181 3182 rxq_set = container_of(rxq, struct idpf_rxq_set, rxq); 3183 refillq = rxq_set->refillq[bufq_id]; 3184 3185 /* retrieve buffer from the rxq */ 3186 rx_bufq = &rxq->bufq_sets[bufq_id].bufq; 3187 3188 buf_id = le16_to_cpu(rx_desc->buf_id); 3189 3190 rx_buf = &rx_bufq->buf[buf_id]; 3191 3192 if (!rx_bufq->hdr_pp) 3193 goto payload; 3194 3195 #define __HBO_BIT VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_HBO_M 3196 #define __HDR_LEN_MASK VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M 3197 if (likely(!(rx_desc->status_err0_qw1 & __HBO_BIT))) 3198 /* If a header buffer overflow, occurs, i.e. header is 3199 * too large to fit in the header split buffer, HW will 3200 * put the entire packet, including headers, in the 3201 * data/payload buffer. 3202 */ 3203 hdr_len = le16_get_bits(rx_desc->hdrlen_flags, 3204 __HDR_LEN_MASK); 3205 #undef __HDR_LEN_MASK 3206 #undef __HBO_BIT 3207 3208 hdr = &rx_bufq->hdr_buf[buf_id]; 3209 3210 if (unlikely(!hdr_len && !xdp->data)) { 3211 hdr_len = idpf_rx_hsplit_wa(hdr, rx_buf, pkt_len); 3212 /* If failed, drop both buffers by setting len to 0 */ 3213 pkt_len -= hdr_len ? : pkt_len; 3214 3215 u64_stats_update_begin(&rxq->stats_sync); 3216 u64_stats_inc(&rxq->q_stats.hsplit_buf_ovf); 3217 u64_stats_update_end(&rxq->stats_sync); 3218 } 3219 3220 if (libeth_xdp_process_buff(xdp, hdr, hdr_len)) 3221 rs.hsplit++; 3222 3223 hdr->netmem = 0; 3224 3225 payload: 3226 libeth_xdp_process_buff(xdp, rx_buf, pkt_len); 3227 rx_buf->netmem = 0; 3228 3229 idpf_post_buf_refill(refillq, buf_id); 3230 IDPF_RX_BUMP_NTC(rxq, ntc); 3231 3232 /* skip if it is non EOP desc */ 3233 if (!idpf_rx_splitq_is_eop(rx_desc) || unlikely(!xdp->data)) 3234 continue; 3235 3236 idpf_xdp_run_pass(xdp, &bq, rxq->napi, &rs, rx_desc); 3237 } 3238 3239 idpf_xdp_finalize_rx(&bq); 3240 3241 rxq->next_to_clean = ntc; 3242 libeth_xdp_save_buff(&rxq->xdp, xdp); 3243 3244 u64_stats_update_begin(&rxq->stats_sync); 3245 u64_stats_add(&rxq->q_stats.packets, rs.packets); 3246 u64_stats_add(&rxq->q_stats.bytes, rs.bytes); 3247 u64_stats_add(&rxq->q_stats.hsplit_pkts, rs.hsplit); 3248 u64_stats_update_end(&rxq->stats_sync); 3249 3250 return rs.packets; 3251 } 3252 3253 /** 3254 * idpf_rx_update_bufq_desc - Update buffer queue descriptor 3255 * @bufq: Pointer to the buffer queue 3256 * @buf_id: buffer ID 3257 * @buf_desc: Buffer queue descriptor 3258 * 3259 * Return 0 on success and negative on failure. 3260 */ 3261 static int idpf_rx_update_bufq_desc(struct idpf_buf_queue *bufq, u32 buf_id, 3262 struct virtchnl2_splitq_rx_buf_desc *buf_desc) 3263 { 3264 struct libeth_fq_fp fq = { 3265 .pp = bufq->pp, 3266 .fqes = bufq->buf, 3267 .truesize = bufq->truesize, 3268 .count = bufq->desc_count, 3269 }; 3270 dma_addr_t addr; 3271 3272 addr = libeth_rx_alloc(&fq, buf_id); 3273 if (addr == DMA_MAPPING_ERROR) 3274 return -ENOMEM; 3275 3276 buf_desc->pkt_addr = cpu_to_le64(addr); 3277 buf_desc->qword0.buf_id = cpu_to_le16(buf_id); 3278 3279 if (!idpf_queue_has(HSPLIT_EN, bufq)) 3280 return 0; 3281 3282 fq.pp = bufq->hdr_pp; 3283 fq.fqes = bufq->hdr_buf; 3284 fq.truesize = bufq->hdr_truesize; 3285 3286 addr = libeth_rx_alloc(&fq, buf_id); 3287 if (addr == DMA_MAPPING_ERROR) 3288 return -ENOMEM; 3289 3290 buf_desc->hdr_addr = cpu_to_le64(addr); 3291 3292 return 0; 3293 } 3294 3295 /** 3296 * idpf_rx_clean_refillq - Clean refill queue buffers 3297 * @bufq: buffer queue to post buffers back to 3298 * @refillq: refill queue to clean 3299 * 3300 * This function takes care of the buffer refill management 3301 */ 3302 static void idpf_rx_clean_refillq(struct idpf_buf_queue *bufq, 3303 struct idpf_sw_queue *refillq) 3304 { 3305 struct virtchnl2_splitq_rx_buf_desc *buf_desc; 3306 u16 bufq_nta = bufq->next_to_alloc; 3307 u16 ntc = refillq->next_to_clean; 3308 int cleaned = 0; 3309 3310 buf_desc = &bufq->split_buf[bufq_nta]; 3311 3312 /* make sure we stop at ring wrap in the unlikely case ring is full */ 3313 while (likely(cleaned < refillq->desc_count)) { 3314 u32 buf_id, refill_desc = refillq->ring[ntc]; 3315 bool failure; 3316 3317 if (idpf_queue_has(RFL_GEN_CHK, refillq) != 3318 !!(refill_desc & IDPF_RFL_BI_GEN_M)) 3319 break; 3320 3321 buf_id = FIELD_GET(IDPF_RFL_BI_BUFID_M, refill_desc); 3322 failure = idpf_rx_update_bufq_desc(bufq, buf_id, buf_desc); 3323 if (failure) 3324 break; 3325 3326 if (unlikely(++ntc == refillq->desc_count)) { 3327 idpf_queue_change(RFL_GEN_CHK, refillq); 3328 ntc = 0; 3329 } 3330 3331 if (unlikely(++bufq_nta == bufq->desc_count)) { 3332 buf_desc = &bufq->split_buf[0]; 3333 bufq_nta = 0; 3334 } else { 3335 buf_desc++; 3336 } 3337 3338 cleaned++; 3339 } 3340 3341 if (!cleaned) 3342 return; 3343 3344 /* We want to limit how many transactions on the bus we trigger with 3345 * tail writes so we only do it in strides. It's also important we 3346 * align the write to a multiple of 8 as required by HW. 3347 */ 3348 if (((bufq->next_to_use <= bufq_nta ? 0 : bufq->desc_count) + 3349 bufq_nta - bufq->next_to_use) >= IDPF_RX_BUF_POST_STRIDE) 3350 idpf_rx_buf_hw_update(bufq, ALIGN_DOWN(bufq_nta, 3351 IDPF_RX_BUF_POST_STRIDE)); 3352 3353 /* update next to alloc since we have filled the ring */ 3354 refillq->next_to_clean = ntc; 3355 bufq->next_to_alloc = bufq_nta; 3356 } 3357 3358 /** 3359 * idpf_rx_clean_refillq_all - Clean all refill queues 3360 * @bufq: buffer queue with refill queues 3361 * @nid: ID of the closest NUMA node with memory 3362 * 3363 * Iterates through all refill queues assigned to the buffer queue assigned to 3364 * this vector. Returns true if clean is complete within budget, false 3365 * otherwise. 3366 */ 3367 static void idpf_rx_clean_refillq_all(struct idpf_buf_queue *bufq, int nid) 3368 { 3369 struct idpf_bufq_set *bufq_set; 3370 int i; 3371 3372 page_pool_nid_changed(bufq->pp, nid); 3373 if (bufq->hdr_pp) 3374 page_pool_nid_changed(bufq->hdr_pp, nid); 3375 3376 bufq_set = container_of(bufq, struct idpf_bufq_set, bufq); 3377 for (i = 0; i < bufq_set->num_refillqs; i++) 3378 idpf_rx_clean_refillq(bufq, &bufq_set->refillqs[i]); 3379 } 3380 3381 /** 3382 * idpf_vport_intr_clean_queues - MSIX mode Interrupt Handler 3383 * @irq: interrupt number 3384 * @data: pointer to a q_vector 3385 * 3386 */ 3387 static irqreturn_t idpf_vport_intr_clean_queues(int __always_unused irq, 3388 void *data) 3389 { 3390 struct idpf_q_vector *q_vector = (struct idpf_q_vector *)data; 3391 3392 q_vector->total_events++; 3393 napi_schedule(&q_vector->napi); 3394 3395 return IRQ_HANDLED; 3396 } 3397 3398 /** 3399 * idpf_vport_intr_napi_del_all - Unregister napi for all q_vectors in vport 3400 * @vport: virtual port structure 3401 * 3402 */ 3403 static void idpf_vport_intr_napi_del_all(struct idpf_vport *vport) 3404 { 3405 u16 v_idx; 3406 3407 for (v_idx = 0; v_idx < vport->num_q_vectors; v_idx++) 3408 netif_napi_del(&vport->q_vectors[v_idx].napi); 3409 } 3410 3411 /** 3412 * idpf_vport_intr_napi_dis_all - Disable NAPI for all q_vectors in the vport 3413 * @vport: main vport structure 3414 */ 3415 static void idpf_vport_intr_napi_dis_all(struct idpf_vport *vport) 3416 { 3417 int v_idx; 3418 3419 for (v_idx = 0; v_idx < vport->num_q_vectors; v_idx++) 3420 napi_disable(&vport->q_vectors[v_idx].napi); 3421 } 3422 3423 /** 3424 * idpf_vport_intr_rel - Free memory allocated for interrupt vectors 3425 * @vport: virtual port 3426 * 3427 * Free the memory allocated for interrupt vectors associated to a vport 3428 */ 3429 void idpf_vport_intr_rel(struct idpf_vport *vport) 3430 { 3431 for (u32 v_idx = 0; v_idx < vport->num_q_vectors; v_idx++) { 3432 struct idpf_q_vector *q_vector = &vport->q_vectors[v_idx]; 3433 3434 kfree(q_vector->complq); 3435 q_vector->complq = NULL; 3436 kfree(q_vector->bufq); 3437 q_vector->bufq = NULL; 3438 kfree(q_vector->tx); 3439 q_vector->tx = NULL; 3440 kfree(q_vector->rx); 3441 q_vector->rx = NULL; 3442 } 3443 3444 kfree(vport->q_vectors); 3445 vport->q_vectors = NULL; 3446 } 3447 3448 static void idpf_q_vector_set_napi(struct idpf_q_vector *q_vector, bool link) 3449 { 3450 struct napi_struct *napi = link ? &q_vector->napi : NULL; 3451 struct net_device *dev = q_vector->vport->netdev; 3452 3453 for (u32 i = 0; i < q_vector->num_rxq; i++) 3454 netif_queue_set_napi(dev, q_vector->rx[i]->idx, 3455 NETDEV_QUEUE_TYPE_RX, napi); 3456 3457 for (u32 i = 0; i < q_vector->num_txq; i++) 3458 netif_queue_set_napi(dev, q_vector->tx[i]->idx, 3459 NETDEV_QUEUE_TYPE_TX, napi); 3460 } 3461 3462 /** 3463 * idpf_vport_intr_rel_irq - Free the IRQ association with the OS 3464 * @vport: main vport structure 3465 */ 3466 static void idpf_vport_intr_rel_irq(struct idpf_vport *vport) 3467 { 3468 struct idpf_adapter *adapter = vport->adapter; 3469 int vector; 3470 3471 for (vector = 0; vector < vport->num_q_vectors; vector++) { 3472 struct idpf_q_vector *q_vector = &vport->q_vectors[vector]; 3473 int irq_num, vidx; 3474 3475 /* free only the irqs that were actually requested */ 3476 if (!q_vector) 3477 continue; 3478 3479 vidx = vport->q_vector_idxs[vector]; 3480 irq_num = adapter->msix_entries[vidx].vector; 3481 3482 idpf_q_vector_set_napi(q_vector, false); 3483 kfree(free_irq(irq_num, q_vector)); 3484 } 3485 } 3486 3487 /** 3488 * idpf_vport_intr_dis_irq_all - Disable all interrupt 3489 * @vport: main vport structure 3490 */ 3491 static void idpf_vport_intr_dis_irq_all(struct idpf_vport *vport) 3492 { 3493 struct idpf_q_vector *q_vector = vport->q_vectors; 3494 int q_idx; 3495 3496 writel(0, vport->noirq_dyn_ctl); 3497 3498 for (q_idx = 0; q_idx < vport->num_q_vectors; q_idx++) 3499 writel(0, q_vector[q_idx].intr_reg.dyn_ctl); 3500 } 3501 3502 /** 3503 * idpf_vport_intr_buildreg_itr - Enable default interrupt generation settings 3504 * @q_vector: pointer to q_vector 3505 */ 3506 static u32 idpf_vport_intr_buildreg_itr(struct idpf_q_vector *q_vector) 3507 { 3508 u32 itr_val = q_vector->intr_reg.dyn_ctl_intena_m; 3509 int type = IDPF_NO_ITR_UPDATE_IDX; 3510 u16 itr = 0; 3511 3512 if (q_vector->wb_on_itr) { 3513 /* 3514 * Trigger a software interrupt when exiting wb_on_itr, to make 3515 * sure we catch any pending write backs that might have been 3516 * missed due to interrupt state transition. 3517 */ 3518 itr_val |= q_vector->intr_reg.dyn_ctl_swint_trig_m | 3519 q_vector->intr_reg.dyn_ctl_sw_itridx_ena_m; 3520 type = IDPF_SW_ITR_UPDATE_IDX; 3521 itr = IDPF_ITR_20K; 3522 } 3523 3524 itr &= IDPF_ITR_MASK; 3525 /* Don't clear PBA because that can cause lost interrupts that 3526 * came in while we were cleaning/polling 3527 */ 3528 itr_val |= (type << q_vector->intr_reg.dyn_ctl_itridx_s) | 3529 (itr << (q_vector->intr_reg.dyn_ctl_intrvl_s - 1)); 3530 3531 return itr_val; 3532 } 3533 3534 /** 3535 * idpf_update_dim_sample - Update dim sample with packets and bytes 3536 * @q_vector: the vector associated with the interrupt 3537 * @dim_sample: dim sample to update 3538 * @dim: dim instance structure 3539 * @packets: total packets 3540 * @bytes: total bytes 3541 * 3542 * Update the dim sample with the packets and bytes which are passed to this 3543 * function. Set the dim state appropriately if the dim settings gets stale. 3544 */ 3545 static void idpf_update_dim_sample(struct idpf_q_vector *q_vector, 3546 struct dim_sample *dim_sample, 3547 struct dim *dim, u64 packets, u64 bytes) 3548 { 3549 dim_update_sample(q_vector->total_events, packets, bytes, dim_sample); 3550 dim_sample->comp_ctr = 0; 3551 3552 /* if dim settings get stale, like when not updated for 1 second or 3553 * longer, force it to start again. This addresses the frequent case 3554 * of an idle queue being switched to by the scheduler. 3555 */ 3556 if (ktime_ms_delta(dim_sample->time, dim->start_sample.time) >= HZ) 3557 dim->state = DIM_START_MEASURE; 3558 } 3559 3560 /** 3561 * idpf_net_dim - Update net DIM algorithm 3562 * @q_vector: the vector associated with the interrupt 3563 * 3564 * Create a DIM sample and notify net_dim() so that it can possibly decide 3565 * a new ITR value based on incoming packets, bytes, and interrupts. 3566 * 3567 * This function is a no-op if the queue is not configured to dynamic ITR. 3568 */ 3569 static void idpf_net_dim(struct idpf_q_vector *q_vector) 3570 { 3571 struct dim_sample dim_sample = { }; 3572 u64 packets, bytes; 3573 u32 i; 3574 3575 if (!IDPF_ITR_IS_DYNAMIC(q_vector->tx_intr_mode)) 3576 goto check_rx_itr; 3577 3578 for (i = 0, packets = 0, bytes = 0; i < q_vector->num_txq; i++) { 3579 struct idpf_tx_queue *txq = q_vector->tx[i]; 3580 unsigned int start; 3581 3582 do { 3583 start = u64_stats_fetch_begin(&txq->stats_sync); 3584 packets += u64_stats_read(&txq->q_stats.packets); 3585 bytes += u64_stats_read(&txq->q_stats.bytes); 3586 } while (u64_stats_fetch_retry(&txq->stats_sync, start)); 3587 } 3588 3589 idpf_update_dim_sample(q_vector, &dim_sample, &q_vector->tx_dim, 3590 packets, bytes); 3591 net_dim(&q_vector->tx_dim, &dim_sample); 3592 3593 check_rx_itr: 3594 if (!IDPF_ITR_IS_DYNAMIC(q_vector->rx_intr_mode)) 3595 return; 3596 3597 for (i = 0, packets = 0, bytes = 0; i < q_vector->num_rxq; i++) { 3598 struct idpf_rx_queue *rxq = q_vector->rx[i]; 3599 unsigned int start; 3600 3601 do { 3602 start = u64_stats_fetch_begin(&rxq->stats_sync); 3603 packets += u64_stats_read(&rxq->q_stats.packets); 3604 bytes += u64_stats_read(&rxq->q_stats.bytes); 3605 } while (u64_stats_fetch_retry(&rxq->stats_sync, start)); 3606 } 3607 3608 idpf_update_dim_sample(q_vector, &dim_sample, &q_vector->rx_dim, 3609 packets, bytes); 3610 net_dim(&q_vector->rx_dim, &dim_sample); 3611 } 3612 3613 /** 3614 * idpf_vport_intr_update_itr_ena_irq - Update itr and re-enable MSIX interrupt 3615 * @q_vector: q_vector for which itr is being updated and interrupt enabled 3616 * 3617 * Update the net_dim() algorithm and re-enable the interrupt associated with 3618 * this vector. 3619 */ 3620 void idpf_vport_intr_update_itr_ena_irq(struct idpf_q_vector *q_vector) 3621 { 3622 u32 intval; 3623 3624 /* net_dim() updates ITR out-of-band using a work item */ 3625 idpf_net_dim(q_vector); 3626 3627 intval = idpf_vport_intr_buildreg_itr(q_vector); 3628 q_vector->wb_on_itr = false; 3629 3630 writel(intval, q_vector->intr_reg.dyn_ctl); 3631 } 3632 3633 /** 3634 * idpf_vport_intr_req_irq - get MSI-X vectors from the OS for the vport 3635 * @vport: main vport structure 3636 */ 3637 static int idpf_vport_intr_req_irq(struct idpf_vport *vport) 3638 { 3639 struct idpf_adapter *adapter = vport->adapter; 3640 const char *drv_name, *if_name, *vec_name; 3641 int vector, err, irq_num, vidx; 3642 3643 drv_name = dev_driver_string(&adapter->pdev->dev); 3644 if_name = netdev_name(vport->netdev); 3645 3646 for (vector = 0; vector < vport->num_q_vectors; vector++) { 3647 struct idpf_q_vector *q_vector = &vport->q_vectors[vector]; 3648 char *name; 3649 3650 vidx = vport->q_vector_idxs[vector]; 3651 irq_num = adapter->msix_entries[vidx].vector; 3652 3653 if (q_vector->num_rxq && q_vector->num_txq) 3654 vec_name = "TxRx"; 3655 else if (q_vector->num_rxq) 3656 vec_name = "Rx"; 3657 else if (q_vector->num_txq) 3658 vec_name = "Tx"; 3659 else 3660 continue; 3661 3662 name = kasprintf(GFP_KERNEL, "%s-%s-%s-%d", drv_name, if_name, 3663 vec_name, vidx); 3664 3665 err = request_irq(irq_num, idpf_vport_intr_clean_queues, 0, 3666 name, q_vector); 3667 if (err) { 3668 netdev_err(vport->netdev, 3669 "Request_irq failed, error: %d\n", err); 3670 goto free_q_irqs; 3671 } 3672 3673 idpf_q_vector_set_napi(q_vector, true); 3674 } 3675 3676 return 0; 3677 3678 free_q_irqs: 3679 while (--vector >= 0) { 3680 vidx = vport->q_vector_idxs[vector]; 3681 irq_num = adapter->msix_entries[vidx].vector; 3682 kfree(free_irq(irq_num, &vport->q_vectors[vector])); 3683 } 3684 3685 return err; 3686 } 3687 3688 /** 3689 * idpf_vport_intr_write_itr - Write ITR value to the ITR register 3690 * @q_vector: q_vector structure 3691 * @itr: Interrupt throttling rate 3692 * @tx: Tx or Rx ITR 3693 */ 3694 void idpf_vport_intr_write_itr(struct idpf_q_vector *q_vector, u16 itr, bool tx) 3695 { 3696 struct idpf_intr_reg *intr_reg; 3697 3698 if (tx && !q_vector->tx) 3699 return; 3700 else if (!tx && !q_vector->rx) 3701 return; 3702 3703 intr_reg = &q_vector->intr_reg; 3704 writel(ITR_REG_ALIGN(itr) >> IDPF_ITR_GRAN_S, 3705 tx ? intr_reg->tx_itr : intr_reg->rx_itr); 3706 } 3707 3708 /** 3709 * idpf_vport_intr_ena_irq_all - Enable IRQ for the given vport 3710 * @vport: main vport structure 3711 */ 3712 static void idpf_vport_intr_ena_irq_all(struct idpf_vport *vport) 3713 { 3714 bool dynamic; 3715 int q_idx; 3716 u16 itr; 3717 3718 for (q_idx = 0; q_idx < vport->num_q_vectors; q_idx++) { 3719 struct idpf_q_vector *qv = &vport->q_vectors[q_idx]; 3720 3721 /* Set the initial ITR values */ 3722 if (qv->num_txq) { 3723 dynamic = IDPF_ITR_IS_DYNAMIC(qv->tx_intr_mode); 3724 itr = vport->tx_itr_profile[qv->tx_dim.profile_ix]; 3725 idpf_vport_intr_write_itr(qv, dynamic ? 3726 itr : qv->tx_itr_value, 3727 true); 3728 } 3729 3730 if (qv->num_rxq) { 3731 dynamic = IDPF_ITR_IS_DYNAMIC(qv->rx_intr_mode); 3732 itr = vport->rx_itr_profile[qv->rx_dim.profile_ix]; 3733 idpf_vport_intr_write_itr(qv, dynamic ? 3734 itr : qv->rx_itr_value, 3735 false); 3736 } 3737 3738 if (qv->num_txq || qv->num_rxq) 3739 idpf_vport_intr_update_itr_ena_irq(qv); 3740 } 3741 3742 writel(vport->noirq_dyn_ctl_ena, vport->noirq_dyn_ctl); 3743 } 3744 3745 /** 3746 * idpf_vport_intr_deinit - Release all vector associations for the vport 3747 * @vport: main vport structure 3748 */ 3749 void idpf_vport_intr_deinit(struct idpf_vport *vport) 3750 { 3751 idpf_vport_intr_dis_irq_all(vport); 3752 idpf_vport_intr_napi_dis_all(vport); 3753 idpf_vport_intr_napi_del_all(vport); 3754 idpf_vport_intr_rel_irq(vport); 3755 } 3756 3757 /** 3758 * idpf_tx_dim_work - Call back from the stack 3759 * @work: work queue structure 3760 */ 3761 static void idpf_tx_dim_work(struct work_struct *work) 3762 { 3763 struct idpf_q_vector *q_vector; 3764 struct idpf_vport *vport; 3765 struct dim *dim; 3766 u16 itr; 3767 3768 dim = container_of(work, struct dim, work); 3769 q_vector = container_of(dim, struct idpf_q_vector, tx_dim); 3770 vport = q_vector->vport; 3771 3772 if (dim->profile_ix >= ARRAY_SIZE(vport->tx_itr_profile)) 3773 dim->profile_ix = ARRAY_SIZE(vport->tx_itr_profile) - 1; 3774 3775 /* look up the values in our local table */ 3776 itr = vport->tx_itr_profile[dim->profile_ix]; 3777 3778 idpf_vport_intr_write_itr(q_vector, itr, true); 3779 3780 dim->state = DIM_START_MEASURE; 3781 } 3782 3783 /** 3784 * idpf_rx_dim_work - Call back from the stack 3785 * @work: work queue structure 3786 */ 3787 static void idpf_rx_dim_work(struct work_struct *work) 3788 { 3789 struct idpf_q_vector *q_vector; 3790 struct idpf_vport *vport; 3791 struct dim *dim; 3792 u16 itr; 3793 3794 dim = container_of(work, struct dim, work); 3795 q_vector = container_of(dim, struct idpf_q_vector, rx_dim); 3796 vport = q_vector->vport; 3797 3798 if (dim->profile_ix >= ARRAY_SIZE(vport->rx_itr_profile)) 3799 dim->profile_ix = ARRAY_SIZE(vport->rx_itr_profile) - 1; 3800 3801 /* look up the values in our local table */ 3802 itr = vport->rx_itr_profile[dim->profile_ix]; 3803 3804 idpf_vport_intr_write_itr(q_vector, itr, false); 3805 3806 dim->state = DIM_START_MEASURE; 3807 } 3808 3809 /** 3810 * idpf_init_dim - Set up dynamic interrupt moderation 3811 * @qv: q_vector structure 3812 */ 3813 static void idpf_init_dim(struct idpf_q_vector *qv) 3814 { 3815 INIT_WORK(&qv->tx_dim.work, idpf_tx_dim_work); 3816 qv->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3817 qv->tx_dim.profile_ix = IDPF_DIM_DEFAULT_PROFILE_IX; 3818 3819 INIT_WORK(&qv->rx_dim.work, idpf_rx_dim_work); 3820 qv->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3821 qv->rx_dim.profile_ix = IDPF_DIM_DEFAULT_PROFILE_IX; 3822 } 3823 3824 /** 3825 * idpf_vport_intr_napi_ena_all - Enable NAPI for all q_vectors in the vport 3826 * @vport: main vport structure 3827 */ 3828 static void idpf_vport_intr_napi_ena_all(struct idpf_vport *vport) 3829 { 3830 int q_idx; 3831 3832 for (q_idx = 0; q_idx < vport->num_q_vectors; q_idx++) { 3833 struct idpf_q_vector *q_vector = &vport->q_vectors[q_idx]; 3834 3835 idpf_init_dim(q_vector); 3836 napi_enable(&q_vector->napi); 3837 } 3838 } 3839 3840 /** 3841 * idpf_tx_splitq_clean_all- Clean completion queues 3842 * @q_vec: queue vector 3843 * @budget: Used to determine if we are in netpoll 3844 * @cleaned: returns number of packets cleaned 3845 * 3846 * Returns false if clean is not complete else returns true 3847 */ 3848 static bool idpf_tx_splitq_clean_all(struct idpf_q_vector *q_vec, 3849 int budget, int *cleaned) 3850 { 3851 u16 num_complq = q_vec->num_complq; 3852 bool clean_complete = true; 3853 int i, budget_per_q; 3854 3855 if (unlikely(!num_complq)) 3856 return true; 3857 3858 budget_per_q = DIV_ROUND_UP(budget, num_complq); 3859 3860 for (i = 0; i < num_complq; i++) 3861 clean_complete &= idpf_tx_clean_complq(q_vec->complq[i], 3862 budget_per_q, cleaned); 3863 3864 return clean_complete; 3865 } 3866 3867 /** 3868 * idpf_rx_splitq_clean_all- Clean completion queues 3869 * @q_vec: queue vector 3870 * @budget: Used to determine if we are in netpoll 3871 * @cleaned: returns number of packets cleaned 3872 * 3873 * Returns false if clean is not complete else returns true 3874 */ 3875 static bool idpf_rx_splitq_clean_all(struct idpf_q_vector *q_vec, int budget, 3876 int *cleaned) 3877 { 3878 u16 num_rxq = q_vec->num_rxq; 3879 bool clean_complete = true; 3880 int pkts_cleaned = 0; 3881 int i, budget_per_q; 3882 int nid; 3883 3884 /* We attempt to distribute budget to each Rx queue fairly, but don't 3885 * allow the budget to go below 1 because that would exit polling early. 3886 */ 3887 budget_per_q = num_rxq ? max(budget / num_rxq, 1) : 0; 3888 for (i = 0; i < num_rxq; i++) { 3889 struct idpf_rx_queue *rxq = q_vec->rx[i]; 3890 int pkts_cleaned_per_q; 3891 3892 pkts_cleaned_per_q = idpf_rx_splitq_clean(rxq, budget_per_q); 3893 /* if we clean as many as budgeted, we must not be done */ 3894 if (pkts_cleaned_per_q >= budget_per_q) 3895 clean_complete = false; 3896 pkts_cleaned += pkts_cleaned_per_q; 3897 } 3898 *cleaned = pkts_cleaned; 3899 3900 nid = numa_mem_id(); 3901 3902 for (i = 0; i < q_vec->num_bufq; i++) 3903 idpf_rx_clean_refillq_all(q_vec->bufq[i], nid); 3904 3905 return clean_complete; 3906 } 3907 3908 /** 3909 * idpf_vport_splitq_napi_poll - NAPI handler 3910 * @napi: struct from which you get q_vector 3911 * @budget: budget provided by stack 3912 */ 3913 static int idpf_vport_splitq_napi_poll(struct napi_struct *napi, int budget) 3914 { 3915 struct idpf_q_vector *q_vector = 3916 container_of(napi, struct idpf_q_vector, napi); 3917 bool clean_complete; 3918 int work_done = 0; 3919 3920 /* Handle case where we are called by netpoll with a budget of 0 */ 3921 if (unlikely(!budget)) { 3922 idpf_tx_splitq_clean_all(q_vector, budget, &work_done); 3923 3924 return 0; 3925 } 3926 3927 clean_complete = idpf_rx_splitq_clean_all(q_vector, budget, &work_done); 3928 clean_complete &= idpf_tx_splitq_clean_all(q_vector, budget, &work_done); 3929 3930 /* If work not completed, return budget and polling will return */ 3931 if (!clean_complete) { 3932 idpf_vport_intr_set_wb_on_itr(q_vector); 3933 return budget; 3934 } 3935 3936 work_done = min_t(int, work_done, budget - 1); 3937 3938 /* Exit the polling mode, but don't re-enable interrupts if stack might 3939 * poll us due to busy-polling 3940 */ 3941 if (likely(napi_complete_done(napi, work_done))) 3942 idpf_vport_intr_update_itr_ena_irq(q_vector); 3943 else 3944 idpf_vport_intr_set_wb_on_itr(q_vector); 3945 3946 return work_done; 3947 } 3948 3949 /** 3950 * idpf_vport_intr_map_vector_to_qs - Map vectors to queues 3951 * @vport: virtual port 3952 * 3953 * Mapping for vectors to queues 3954 */ 3955 static void idpf_vport_intr_map_vector_to_qs(struct idpf_vport *vport) 3956 { 3957 u16 num_txq_grp = vport->num_txq_grp - vport->num_xdp_txq; 3958 bool split = idpf_is_queue_model_split(vport->rxq_model); 3959 struct idpf_rxq_group *rx_qgrp; 3960 struct idpf_txq_group *tx_qgrp; 3961 u32 i, qv_idx, q_index; 3962 3963 for (i = 0, qv_idx = 0; i < vport->num_rxq_grp; i++) { 3964 u16 num_rxq; 3965 3966 if (qv_idx >= vport->num_q_vectors) 3967 qv_idx = 0; 3968 3969 rx_qgrp = &vport->rxq_grps[i]; 3970 if (split) 3971 num_rxq = rx_qgrp->splitq.num_rxq_sets; 3972 else 3973 num_rxq = rx_qgrp->singleq.num_rxq; 3974 3975 for (u32 j = 0; j < num_rxq; j++) { 3976 struct idpf_rx_queue *q; 3977 3978 if (split) 3979 q = &rx_qgrp->splitq.rxq_sets[j]->rxq; 3980 else 3981 q = rx_qgrp->singleq.rxqs[j]; 3982 q->q_vector = &vport->q_vectors[qv_idx]; 3983 q_index = q->q_vector->num_rxq; 3984 q->q_vector->rx[q_index] = q; 3985 q->q_vector->num_rxq++; 3986 3987 if (split) 3988 q->napi = &q->q_vector->napi; 3989 } 3990 3991 if (split) { 3992 for (u32 j = 0; j < vport->num_bufqs_per_qgrp; j++) { 3993 struct idpf_buf_queue *bufq; 3994 3995 bufq = &rx_qgrp->splitq.bufq_sets[j].bufq; 3996 bufq->q_vector = &vport->q_vectors[qv_idx]; 3997 q_index = bufq->q_vector->num_bufq; 3998 bufq->q_vector->bufq[q_index] = bufq; 3999 bufq->q_vector->num_bufq++; 4000 } 4001 } 4002 4003 qv_idx++; 4004 } 4005 4006 split = idpf_is_queue_model_split(vport->txq_model); 4007 4008 for (i = 0, qv_idx = 0; i < num_txq_grp; i++) { 4009 u16 num_txq; 4010 4011 if (qv_idx >= vport->num_q_vectors) 4012 qv_idx = 0; 4013 4014 tx_qgrp = &vport->txq_grps[i]; 4015 num_txq = tx_qgrp->num_txq; 4016 4017 for (u32 j = 0; j < num_txq; j++) { 4018 struct idpf_tx_queue *q; 4019 4020 q = tx_qgrp->txqs[j]; 4021 q->q_vector = &vport->q_vectors[qv_idx]; 4022 q->q_vector->tx[q->q_vector->num_txq++] = q; 4023 } 4024 4025 if (split) { 4026 struct idpf_compl_queue *q = tx_qgrp->complq; 4027 4028 q->q_vector = &vport->q_vectors[qv_idx]; 4029 q->q_vector->complq[q->q_vector->num_complq++] = q; 4030 } 4031 4032 qv_idx++; 4033 } 4034 } 4035 4036 /** 4037 * idpf_vport_intr_init_vec_idx - Initialize the vector indexes 4038 * @vport: virtual port 4039 * 4040 * Initialize vector indexes with values returened over mailbox 4041 */ 4042 static int idpf_vport_intr_init_vec_idx(struct idpf_vport *vport) 4043 { 4044 struct idpf_adapter *adapter = vport->adapter; 4045 struct virtchnl2_alloc_vectors *ac; 4046 u16 *vecids, total_vecs; 4047 int i; 4048 4049 ac = adapter->req_vec_chunks; 4050 if (!ac) { 4051 for (i = 0; i < vport->num_q_vectors; i++) 4052 vport->q_vectors[i].v_idx = vport->q_vector_idxs[i]; 4053 4054 vport->noirq_v_idx = vport->q_vector_idxs[i]; 4055 4056 return 0; 4057 } 4058 4059 total_vecs = idpf_get_reserved_vecs(adapter); 4060 vecids = kcalloc(total_vecs, sizeof(u16), GFP_KERNEL); 4061 if (!vecids) 4062 return -ENOMEM; 4063 4064 idpf_get_vec_ids(adapter, vecids, total_vecs, &ac->vchunks); 4065 4066 for (i = 0; i < vport->num_q_vectors; i++) 4067 vport->q_vectors[i].v_idx = vecids[vport->q_vector_idxs[i]]; 4068 4069 vport->noirq_v_idx = vecids[vport->q_vector_idxs[i]]; 4070 4071 kfree(vecids); 4072 4073 return 0; 4074 } 4075 4076 /** 4077 * idpf_vport_intr_napi_add_all- Register napi handler for all qvectors 4078 * @vport: virtual port structure 4079 */ 4080 static void idpf_vport_intr_napi_add_all(struct idpf_vport *vport) 4081 { 4082 int (*napi_poll)(struct napi_struct *napi, int budget); 4083 u16 v_idx, qv_idx; 4084 int irq_num; 4085 4086 if (idpf_is_queue_model_split(vport->txq_model)) 4087 napi_poll = idpf_vport_splitq_napi_poll; 4088 else 4089 napi_poll = idpf_vport_singleq_napi_poll; 4090 4091 for (v_idx = 0; v_idx < vport->num_q_vectors; v_idx++) { 4092 struct idpf_q_vector *q_vector = &vport->q_vectors[v_idx]; 4093 qv_idx = vport->q_vector_idxs[v_idx]; 4094 irq_num = vport->adapter->msix_entries[qv_idx].vector; 4095 4096 netif_napi_add_config(vport->netdev, &q_vector->napi, 4097 napi_poll, v_idx); 4098 netif_napi_set_irq(&q_vector->napi, irq_num); 4099 } 4100 } 4101 4102 /** 4103 * idpf_vport_intr_alloc - Allocate memory for interrupt vectors 4104 * @vport: virtual port 4105 * 4106 * We allocate one q_vector per queue interrupt. If allocation fails we 4107 * return -ENOMEM. 4108 */ 4109 int idpf_vport_intr_alloc(struct idpf_vport *vport) 4110 { 4111 u16 txqs_per_vector, rxqs_per_vector, bufqs_per_vector; 4112 struct idpf_vport_user_config_data *user_config; 4113 struct idpf_q_vector *q_vector; 4114 struct idpf_q_coalesce *q_coal; 4115 u32 complqs_per_vector, v_idx; 4116 u16 idx = vport->idx; 4117 4118 user_config = &vport->adapter->vport_config[idx]->user_config; 4119 vport->q_vectors = kcalloc(vport->num_q_vectors, 4120 sizeof(struct idpf_q_vector), GFP_KERNEL); 4121 if (!vport->q_vectors) 4122 return -ENOMEM; 4123 4124 txqs_per_vector = DIV_ROUND_UP(vport->num_txq_grp, 4125 vport->num_q_vectors); 4126 rxqs_per_vector = DIV_ROUND_UP(vport->num_rxq_grp, 4127 vport->num_q_vectors); 4128 bufqs_per_vector = vport->num_bufqs_per_qgrp * 4129 DIV_ROUND_UP(vport->num_rxq_grp, 4130 vport->num_q_vectors); 4131 complqs_per_vector = DIV_ROUND_UP(vport->num_txq_grp, 4132 vport->num_q_vectors); 4133 4134 for (v_idx = 0; v_idx < vport->num_q_vectors; v_idx++) { 4135 q_vector = &vport->q_vectors[v_idx]; 4136 q_coal = &user_config->q_coalesce[v_idx]; 4137 q_vector->vport = vport; 4138 4139 q_vector->tx_itr_value = q_coal->tx_coalesce_usecs; 4140 q_vector->tx_intr_mode = q_coal->tx_intr_mode; 4141 q_vector->tx_itr_idx = VIRTCHNL2_ITR_IDX_1; 4142 4143 q_vector->rx_itr_value = q_coal->rx_coalesce_usecs; 4144 q_vector->rx_intr_mode = q_coal->rx_intr_mode; 4145 q_vector->rx_itr_idx = VIRTCHNL2_ITR_IDX_0; 4146 4147 q_vector->tx = kcalloc(txqs_per_vector, sizeof(*q_vector->tx), 4148 GFP_KERNEL); 4149 if (!q_vector->tx) 4150 goto error; 4151 4152 q_vector->rx = kcalloc(rxqs_per_vector, sizeof(*q_vector->rx), 4153 GFP_KERNEL); 4154 if (!q_vector->rx) 4155 goto error; 4156 4157 if (!idpf_is_queue_model_split(vport->rxq_model)) 4158 continue; 4159 4160 q_vector->bufq = kcalloc(bufqs_per_vector, 4161 sizeof(*q_vector->bufq), 4162 GFP_KERNEL); 4163 if (!q_vector->bufq) 4164 goto error; 4165 4166 q_vector->complq = kcalloc(complqs_per_vector, 4167 sizeof(*q_vector->complq), 4168 GFP_KERNEL); 4169 if (!q_vector->complq) 4170 goto error; 4171 } 4172 4173 return 0; 4174 4175 error: 4176 idpf_vport_intr_rel(vport); 4177 4178 return -ENOMEM; 4179 } 4180 4181 /** 4182 * idpf_vport_intr_init - Setup all vectors for the given vport 4183 * @vport: virtual port 4184 * 4185 * Returns 0 on success or negative on failure 4186 */ 4187 int idpf_vport_intr_init(struct idpf_vport *vport) 4188 { 4189 int err; 4190 4191 err = idpf_vport_intr_init_vec_idx(vport); 4192 if (err) 4193 return err; 4194 4195 idpf_vport_intr_map_vector_to_qs(vport); 4196 idpf_vport_intr_napi_add_all(vport); 4197 4198 err = vport->adapter->dev_ops.reg_ops.intr_reg_init(vport); 4199 if (err) 4200 goto unroll_vectors_alloc; 4201 4202 err = idpf_vport_intr_req_irq(vport); 4203 if (err) 4204 goto unroll_vectors_alloc; 4205 4206 return 0; 4207 4208 unroll_vectors_alloc: 4209 idpf_vport_intr_napi_del_all(vport); 4210 4211 return err; 4212 } 4213 4214 void idpf_vport_intr_ena(struct idpf_vport *vport) 4215 { 4216 idpf_vport_intr_napi_ena_all(vport); 4217 idpf_vport_intr_ena_irq_all(vport); 4218 } 4219 4220 /** 4221 * idpf_config_rss - Send virtchnl messages to configure RSS 4222 * @vport: virtual port 4223 * 4224 * Return 0 on success, negative on failure 4225 */ 4226 int idpf_config_rss(struct idpf_vport *vport) 4227 { 4228 int err; 4229 4230 err = idpf_send_get_set_rss_key_msg(vport, false); 4231 if (err) 4232 return err; 4233 4234 return idpf_send_get_set_rss_lut_msg(vport, false); 4235 } 4236 4237 /** 4238 * idpf_fill_dflt_rss_lut - Fill the indirection table with the default values 4239 * @vport: virtual port structure 4240 */ 4241 static void idpf_fill_dflt_rss_lut(struct idpf_vport *vport) 4242 { 4243 struct idpf_adapter *adapter = vport->adapter; 4244 u16 num_active_rxq = vport->num_rxq; 4245 struct idpf_rss_data *rss_data; 4246 int i; 4247 4248 rss_data = &adapter->vport_config[vport->idx]->user_config.rss_data; 4249 4250 for (i = 0; i < rss_data->rss_lut_size; i++) { 4251 rss_data->rss_lut[i] = i % num_active_rxq; 4252 rss_data->cached_lut[i] = rss_data->rss_lut[i]; 4253 } 4254 } 4255 4256 /** 4257 * idpf_init_rss - Allocate and initialize RSS resources 4258 * @vport: virtual port 4259 * 4260 * Return 0 on success, negative on failure 4261 */ 4262 int idpf_init_rss(struct idpf_vport *vport) 4263 { 4264 struct idpf_adapter *adapter = vport->adapter; 4265 struct idpf_rss_data *rss_data; 4266 u32 lut_size; 4267 4268 rss_data = &adapter->vport_config[vport->idx]->user_config.rss_data; 4269 4270 lut_size = rss_data->rss_lut_size * sizeof(u32); 4271 rss_data->rss_lut = kzalloc(lut_size, GFP_KERNEL); 4272 if (!rss_data->rss_lut) 4273 return -ENOMEM; 4274 4275 rss_data->cached_lut = kzalloc(lut_size, GFP_KERNEL); 4276 if (!rss_data->cached_lut) { 4277 kfree(rss_data->rss_lut); 4278 rss_data->rss_lut = NULL; 4279 4280 return -ENOMEM; 4281 } 4282 4283 /* Fill the default RSS lut values */ 4284 idpf_fill_dflt_rss_lut(vport); 4285 4286 return idpf_config_rss(vport); 4287 } 4288 4289 /** 4290 * idpf_deinit_rss - Release RSS resources 4291 * @vport: virtual port 4292 */ 4293 void idpf_deinit_rss(struct idpf_vport *vport) 4294 { 4295 struct idpf_adapter *adapter = vport->adapter; 4296 struct idpf_rss_data *rss_data; 4297 4298 rss_data = &adapter->vport_config[vport->idx]->user_config.rss_data; 4299 kfree(rss_data->cached_lut); 4300 rss_data->cached_lut = NULL; 4301 kfree(rss_data->rss_lut); 4302 rss_data->rss_lut = NULL; 4303 } 4304