1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #include "idpf.h" 5 #include "idpf_lan_pf_regs.h" 6 #include "idpf_virtchnl.h" 7 #include "idpf_ptp.h" 8 9 #define IDPF_PF_ITR_IDX_SPACING 0x4 10 11 /** 12 * idpf_ctlq_reg_init - initialize default mailbox registers 13 * @cq: pointer to the array of create control queues 14 */ 15 static void idpf_ctlq_reg_init(struct idpf_ctlq_create_info *cq) 16 { 17 int i; 18 19 for (i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) { 20 struct idpf_ctlq_create_info *ccq = cq + i; 21 22 switch (ccq->type) { 23 case IDPF_CTLQ_TYPE_MAILBOX_TX: 24 /* set head and tail registers in our local struct */ 25 ccq->reg.head = PF_FW_ATQH; 26 ccq->reg.tail = PF_FW_ATQT; 27 ccq->reg.len = PF_FW_ATQLEN; 28 ccq->reg.bah = PF_FW_ATQBAH; 29 ccq->reg.bal = PF_FW_ATQBAL; 30 ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M; 31 ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; 32 ccq->reg.head_mask = PF_FW_ATQH_ATQH_M; 33 break; 34 case IDPF_CTLQ_TYPE_MAILBOX_RX: 35 /* set head and tail registers in our local struct */ 36 ccq->reg.head = PF_FW_ARQH; 37 ccq->reg.tail = PF_FW_ARQT; 38 ccq->reg.len = PF_FW_ARQLEN; 39 ccq->reg.bah = PF_FW_ARQBAH; 40 ccq->reg.bal = PF_FW_ARQBAL; 41 ccq->reg.len_mask = PF_FW_ARQLEN_ARQLEN_M; 42 ccq->reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; 43 ccq->reg.head_mask = PF_FW_ARQH_ARQH_M; 44 break; 45 default: 46 break; 47 } 48 } 49 } 50 51 /** 52 * idpf_mb_intr_reg_init - Initialize mailbox interrupt register 53 * @adapter: adapter structure 54 */ 55 static void idpf_mb_intr_reg_init(struct idpf_adapter *adapter) 56 { 57 struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg; 58 u32 dyn_ctl = le32_to_cpu(adapter->caps.mailbox_dyn_ctl); 59 60 intr->dyn_ctl = idpf_get_reg_addr(adapter, dyn_ctl); 61 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 62 intr->dyn_ctl_itridx_m = PF_GLINT_DYN_CTL_ITR_INDX_M; 63 intr->icr_ena = idpf_get_reg_addr(adapter, PF_INT_DIR_OICR_ENA); 64 intr->icr_ena_ctlq_m = PF_INT_DIR_OICR_ENA_M; 65 } 66 67 /** 68 * idpf_intr_reg_init - Initialize interrupt registers 69 * @vport: virtual port structure 70 */ 71 static int idpf_intr_reg_init(struct idpf_vport *vport) 72 { 73 struct idpf_adapter *adapter = vport->adapter; 74 int num_vecs = vport->num_q_vectors; 75 struct idpf_vec_regs *reg_vals; 76 int num_regs, i, err = 0; 77 u32 rx_itr, tx_itr; 78 u16 total_vecs; 79 80 total_vecs = idpf_get_reserved_vecs(vport->adapter); 81 reg_vals = kcalloc(total_vecs, sizeof(struct idpf_vec_regs), 82 GFP_KERNEL); 83 if (!reg_vals) 84 return -ENOMEM; 85 86 num_regs = idpf_get_reg_intr_vecs(vport, reg_vals); 87 if (num_regs < num_vecs) { 88 err = -EINVAL; 89 goto free_reg_vals; 90 } 91 92 for (i = 0; i < num_vecs; i++) { 93 struct idpf_q_vector *q_vector = &vport->q_vectors[i]; 94 u16 vec_id = vport->q_vector_idxs[i] - IDPF_MBX_Q_VEC; 95 struct idpf_intr_reg *intr = &q_vector->intr_reg; 96 u32 spacing; 97 98 intr->dyn_ctl = idpf_get_reg_addr(adapter, 99 reg_vals[vec_id].dyn_ctl_reg); 100 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 101 intr->dyn_ctl_intena_msk_m = PF_GLINT_DYN_CTL_INTENA_MSK_M; 102 intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S; 103 intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S; 104 intr->dyn_ctl_wb_on_itr_m = PF_GLINT_DYN_CTL_WB_ON_ITR_M; 105 intr->dyn_ctl_swint_trig_m = PF_GLINT_DYN_CTL_SWINT_TRIG_M; 106 intr->dyn_ctl_sw_itridx_ena_m = 107 PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M; 108 109 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing, 110 IDPF_PF_ITR_IDX_SPACING); 111 rx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_0, 112 reg_vals[vec_id].itrn_reg, 113 spacing); 114 tx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_1, 115 reg_vals[vec_id].itrn_reg, 116 spacing); 117 intr->rx_itr = idpf_get_reg_addr(adapter, rx_itr); 118 intr->tx_itr = idpf_get_reg_addr(adapter, tx_itr); 119 } 120 121 free_reg_vals: 122 kfree(reg_vals); 123 124 return err; 125 } 126 127 /** 128 * idpf_reset_reg_init - Initialize reset registers 129 * @adapter: Driver specific private structure 130 */ 131 static void idpf_reset_reg_init(struct idpf_adapter *adapter) 132 { 133 adapter->reset_reg.rstat = idpf_get_reg_addr(adapter, PFGEN_RSTAT); 134 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M; 135 } 136 137 /** 138 * idpf_trigger_reset - trigger reset 139 * @adapter: Driver specific private structure 140 * @trig_cause: Reason to trigger a reset 141 */ 142 static void idpf_trigger_reset(struct idpf_adapter *adapter, 143 enum idpf_flags __always_unused trig_cause) 144 { 145 u32 reset_reg; 146 147 reset_reg = readl(idpf_get_reg_addr(adapter, PFGEN_CTRL)); 148 writel(reset_reg | PFGEN_CTRL_PFSWR, 149 idpf_get_reg_addr(adapter, PFGEN_CTRL)); 150 } 151 152 /** 153 * idpf_ptp_reg_init - Initialize required registers 154 * @adapter: Driver specific private structure 155 * 156 * Set the bits required for enabling shtime and cmd execution 157 */ 158 static void idpf_ptp_reg_init(const struct idpf_adapter *adapter) 159 { 160 adapter->ptp->cmd.shtime_enable_mask = PF_GLTSYN_CMD_SYNC_SHTIME_EN_M; 161 adapter->ptp->cmd.exec_cmd_mask = PF_GLTSYN_CMD_SYNC_EXEC_CMD_M; 162 } 163 164 /** 165 * idpf_reg_ops_init - Initialize register API function pointers 166 * @adapter: Driver specific private structure 167 */ 168 static void idpf_reg_ops_init(struct idpf_adapter *adapter) 169 { 170 adapter->dev_ops.reg_ops.ctlq_reg_init = idpf_ctlq_reg_init; 171 adapter->dev_ops.reg_ops.intr_reg_init = idpf_intr_reg_init; 172 adapter->dev_ops.reg_ops.mb_intr_reg_init = idpf_mb_intr_reg_init; 173 adapter->dev_ops.reg_ops.reset_reg_init = idpf_reset_reg_init; 174 adapter->dev_ops.reg_ops.trigger_reset = idpf_trigger_reset; 175 adapter->dev_ops.reg_ops.ptp_reg_init = idpf_ptp_reg_init; 176 } 177 178 /** 179 * idpf_dev_ops_init - Initialize device API function pointers 180 * @adapter: Driver specific private structure 181 */ 182 void idpf_dev_ops_init(struct idpf_adapter *adapter) 183 { 184 idpf_reg_ops_init(adapter); 185 } 186