1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #include "idpf.h" 5 #include "idpf_lan_pf_regs.h" 6 #include "idpf_virtchnl.h" 7 #include "idpf_ptp.h" 8 9 #define IDPF_PF_ITR_IDX_SPACING 0x4 10 11 /** 12 * idpf_ctlq_reg_init - initialize default mailbox registers 13 * @adapter: adapter structure 14 * @cq: pointer to the array of create control queues 15 */ 16 static void idpf_ctlq_reg_init(struct idpf_adapter *adapter, 17 struct idpf_ctlq_create_info *cq) 18 { 19 resource_size_t mbx_start = adapter->dev_ops.static_reg_info[0].start; 20 int i; 21 22 for (i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) { 23 struct idpf_ctlq_create_info *ccq = cq + i; 24 25 switch (ccq->type) { 26 case IDPF_CTLQ_TYPE_MAILBOX_TX: 27 /* set head and tail registers in our local struct */ 28 ccq->reg.head = PF_FW_ATQH - mbx_start; 29 ccq->reg.tail = PF_FW_ATQT - mbx_start; 30 ccq->reg.len = PF_FW_ATQLEN - mbx_start; 31 ccq->reg.bah = PF_FW_ATQBAH - mbx_start; 32 ccq->reg.bal = PF_FW_ATQBAL - mbx_start; 33 ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M; 34 ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; 35 ccq->reg.head_mask = PF_FW_ATQH_ATQH_M; 36 break; 37 case IDPF_CTLQ_TYPE_MAILBOX_RX: 38 /* set head and tail registers in our local struct */ 39 ccq->reg.head = PF_FW_ARQH - mbx_start; 40 ccq->reg.tail = PF_FW_ARQT - mbx_start; 41 ccq->reg.len = PF_FW_ARQLEN - mbx_start; 42 ccq->reg.bah = PF_FW_ARQBAH - mbx_start; 43 ccq->reg.bal = PF_FW_ARQBAL - mbx_start; 44 ccq->reg.len_mask = PF_FW_ARQLEN_ARQLEN_M; 45 ccq->reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; 46 ccq->reg.head_mask = PF_FW_ARQH_ARQH_M; 47 break; 48 default: 49 break; 50 } 51 } 52 } 53 54 /** 55 * idpf_mb_intr_reg_init - Initialize mailbox interrupt register 56 * @adapter: adapter structure 57 */ 58 static void idpf_mb_intr_reg_init(struct idpf_adapter *adapter) 59 { 60 struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg; 61 u32 dyn_ctl = le32_to_cpu(adapter->caps.mailbox_dyn_ctl); 62 63 intr->dyn_ctl = idpf_get_reg_addr(adapter, dyn_ctl); 64 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 65 intr->dyn_ctl_itridx_m = PF_GLINT_DYN_CTL_ITR_INDX_M; 66 intr->icr_ena = idpf_get_reg_addr(adapter, PF_INT_DIR_OICR_ENA); 67 intr->icr_ena_ctlq_m = PF_INT_DIR_OICR_ENA_M; 68 } 69 70 /** 71 * idpf_intr_reg_init - Initialize interrupt registers 72 * @vport: virtual port structure 73 * @rsrc: pointer to queue and vector resources 74 */ 75 static int idpf_intr_reg_init(struct idpf_vport *vport, 76 struct idpf_q_vec_rsrc *rsrc) 77 { 78 struct idpf_adapter *adapter = vport->adapter; 79 u16 num_vecs = rsrc->num_q_vectors; 80 struct idpf_vec_regs *reg_vals; 81 int num_regs, i, err = 0; 82 u32 rx_itr, tx_itr, val; 83 u16 total_vecs; 84 85 total_vecs = idpf_get_reserved_vecs(vport->adapter); 86 reg_vals = kcalloc(total_vecs, sizeof(struct idpf_vec_regs), 87 GFP_KERNEL); 88 if (!reg_vals) 89 return -ENOMEM; 90 91 num_regs = idpf_get_reg_intr_vecs(adapter, reg_vals); 92 if (num_regs < num_vecs) { 93 err = -EINVAL; 94 goto free_reg_vals; 95 } 96 97 for (i = 0; i < num_vecs; i++) { 98 struct idpf_q_vector *q_vector = &rsrc->q_vectors[i]; 99 u16 vec_id = rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC; 100 struct idpf_intr_reg *intr = &q_vector->intr_reg; 101 u32 spacing; 102 103 intr->dyn_ctl = idpf_get_reg_addr(adapter, 104 reg_vals[vec_id].dyn_ctl_reg); 105 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 106 intr->dyn_ctl_intena_msk_m = PF_GLINT_DYN_CTL_INTENA_MSK_M; 107 intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S; 108 intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S; 109 intr->dyn_ctl_wb_on_itr_m = PF_GLINT_DYN_CTL_WB_ON_ITR_M; 110 intr->dyn_ctl_swint_trig_m = PF_GLINT_DYN_CTL_SWINT_TRIG_M; 111 intr->dyn_ctl_sw_itridx_ena_m = 112 PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M; 113 114 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing, 115 IDPF_PF_ITR_IDX_SPACING); 116 rx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_0, 117 reg_vals[vec_id].itrn_reg, 118 spacing); 119 tx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_1, 120 reg_vals[vec_id].itrn_reg, 121 spacing); 122 intr->rx_itr = idpf_get_reg_addr(adapter, rx_itr); 123 intr->tx_itr = idpf_get_reg_addr(adapter, tx_itr); 124 } 125 126 /* Data vector for NOIRQ queues */ 127 128 val = reg_vals[rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC].dyn_ctl_reg; 129 rsrc->noirq_dyn_ctl = idpf_get_reg_addr(adapter, val); 130 131 val = PF_GLINT_DYN_CTL_WB_ON_ITR_M | PF_GLINT_DYN_CTL_INTENA_MSK_M | 132 FIELD_PREP(PF_GLINT_DYN_CTL_ITR_INDX_M, IDPF_NO_ITR_UPDATE_IDX); 133 rsrc->noirq_dyn_ctl_ena = val; 134 135 free_reg_vals: 136 kfree(reg_vals); 137 138 return err; 139 } 140 141 /** 142 * idpf_reset_reg_init - Initialize reset registers 143 * @adapter: Driver specific private structure 144 */ 145 static void idpf_reset_reg_init(struct idpf_adapter *adapter) 146 { 147 adapter->reset_reg.rstat = idpf_get_rstat_reg_addr(adapter, PFGEN_RSTAT); 148 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M; 149 } 150 151 /** 152 * idpf_trigger_reset - trigger reset 153 * @adapter: Driver specific private structure 154 * @trig_cause: Reason to trigger a reset 155 */ 156 static void idpf_trigger_reset(struct idpf_adapter *adapter, 157 enum idpf_flags __always_unused trig_cause) 158 { 159 u32 reset_reg; 160 161 reset_reg = readl(idpf_get_rstat_reg_addr(adapter, PFGEN_CTRL)); 162 writel(reset_reg | PFGEN_CTRL_PFSWR, 163 idpf_get_rstat_reg_addr(adapter, PFGEN_CTRL)); 164 } 165 166 /** 167 * idpf_ptp_reg_init - Initialize required registers 168 * @adapter: Driver specific private structure 169 * 170 * Set the bits required for enabling shtime and cmd execution 171 */ 172 static void idpf_ptp_reg_init(const struct idpf_adapter *adapter) 173 { 174 adapter->ptp->cmd.shtime_enable_mask = PF_GLTSYN_CMD_SYNC_SHTIME_EN_M; 175 adapter->ptp->cmd.exec_cmd_mask = PF_GLTSYN_CMD_SYNC_EXEC_CMD_M; 176 } 177 178 /** 179 * idpf_idc_register - register for IDC callbacks 180 * @adapter: Driver specific private structure 181 * 182 * Return: 0 on success or error code on failure. 183 */ 184 static int idpf_idc_register(struct idpf_adapter *adapter) 185 { 186 return idpf_idc_init_aux_core_dev(adapter, IIDC_FUNCTION_TYPE_PF); 187 } 188 189 /** 190 * idpf_reg_ops_init - Initialize register API function pointers 191 * @adapter: Driver specific private structure 192 */ 193 static void idpf_reg_ops_init(struct idpf_adapter *adapter) 194 { 195 adapter->dev_ops.reg_ops.ctlq_reg_init = idpf_ctlq_reg_init; 196 adapter->dev_ops.reg_ops.intr_reg_init = idpf_intr_reg_init; 197 adapter->dev_ops.reg_ops.mb_intr_reg_init = idpf_mb_intr_reg_init; 198 adapter->dev_ops.reg_ops.reset_reg_init = idpf_reset_reg_init; 199 adapter->dev_ops.reg_ops.trigger_reset = idpf_trigger_reset; 200 adapter->dev_ops.reg_ops.ptp_reg_init = idpf_ptp_reg_init; 201 } 202 203 /** 204 * idpf_dev_ops_init - Initialize device API function pointers 205 * @adapter: Driver specific private structure 206 */ 207 void idpf_dev_ops_init(struct idpf_adapter *adapter) 208 { 209 idpf_reg_ops_init(adapter); 210 211 adapter->dev_ops.idc_init = idpf_idc_register; 212 213 resource_set_range(&adapter->dev_ops.static_reg_info[0], 214 PF_FW_BASE, IDPF_PF_MBX_REGION_SZ); 215 resource_set_range(&adapter->dev_ops.static_reg_info[1], 216 PFGEN_RTRIG, IDPF_PF_RSTAT_REGION_SZ); 217 } 218