1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #include "idpf.h" 5 #include "idpf_lan_pf_regs.h" 6 #include "idpf_virtchnl.h" 7 #include "idpf_ptp.h" 8 9 #define IDPF_PF_ITR_IDX_SPACING 0x4 10 11 /** 12 * idpf_ctlq_reg_init - initialize default mailbox registers 13 * @mmio: struct that contains MMIO region info 14 * @cci: struct where the register offset pointer to be copied to 15 */ 16 static void idpf_ctlq_reg_init(struct libie_mmio_info *mmio, 17 struct libie_ctlq_create_info *cci) 18 { 19 struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg; 20 struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg; 21 22 tx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ATQH); 23 tx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ATQT); 24 tx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ATQLEN); 25 tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAH); 26 tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAL); 27 tx_reg->len_mask = PF_FW_ATQLEN_ATQLEN_M; 28 tx_reg->len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; 29 tx_reg->head_mask = PF_FW_ATQH_ATQH_M; 30 31 rx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ARQH); 32 rx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ARQT); 33 rx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ARQLEN); 34 rx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAH); 35 rx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAL); 36 rx_reg->len_mask = PF_FW_ARQLEN_ARQLEN_M; 37 rx_reg->len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; 38 rx_reg->head_mask = PF_FW_ARQH_ARQH_M; 39 } 40 41 /** 42 * idpf_mb_intr_reg_init - Initialize mailbox interrupt register 43 * @adapter: adapter structure 44 */ 45 static void idpf_mb_intr_reg_init(struct idpf_adapter *adapter) 46 { 47 struct libie_mmio_info *mmio = &adapter->ctlq_ctx.mmio_info; 48 struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg; 49 u32 dyn_ctl = le32_to_cpu(adapter->caps.mailbox_dyn_ctl); 50 51 intr->dyn_ctl = libie_pci_get_mmio_addr(mmio, dyn_ctl); 52 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 53 intr->dyn_ctl_itridx_m = PF_GLINT_DYN_CTL_ITR_INDX_M; 54 intr->icr_ena = libie_pci_get_mmio_addr(mmio, PF_INT_DIR_OICR_ENA); 55 intr->icr_ena_ctlq_m = PF_INT_DIR_OICR_ENA_M; 56 } 57 58 /** 59 * idpf_intr_reg_init - Initialize interrupt registers 60 * @vport: virtual port structure 61 * @rsrc: pointer to queue and vector resources 62 */ 63 static int idpf_intr_reg_init(struct idpf_vport *vport, 64 struct idpf_q_vec_rsrc *rsrc) 65 { 66 struct idpf_adapter *adapter = vport->adapter; 67 u16 num_vecs = rsrc->num_q_vectors; 68 struct idpf_vec_regs *reg_vals; 69 struct libie_mmio_info *mmio; 70 int num_regs, i, err = 0; 71 u32 rx_itr, tx_itr, val; 72 u16 total_vecs; 73 74 total_vecs = idpf_get_reserved_vecs(vport->adapter); 75 reg_vals = kzalloc_objs(struct idpf_vec_regs, total_vecs); 76 if (!reg_vals) 77 return -ENOMEM; 78 79 num_regs = idpf_get_reg_intr_vecs(adapter, reg_vals, total_vecs); 80 if (num_regs < num_vecs) { 81 err = -EINVAL; 82 goto free_reg_vals; 83 } 84 85 mmio = &adapter->ctlq_ctx.mmio_info; 86 87 for (i = 0; i < num_vecs; i++) { 88 struct idpf_q_vector *q_vector = &rsrc->q_vectors[i]; 89 u16 vec_id = rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC; 90 struct idpf_intr_reg *intr = &q_vector->intr_reg; 91 struct idpf_vec_regs *reg = ®_vals[vec_id]; 92 u32 spacing; 93 94 intr->dyn_ctl = libie_pci_get_mmio_addr(mmio, 95 reg->dyn_ctl_reg); 96 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 97 intr->dyn_ctl_intena_msk_m = PF_GLINT_DYN_CTL_INTENA_MSK_M; 98 intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S; 99 intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S; 100 intr->dyn_ctl_wb_on_itr_m = PF_GLINT_DYN_CTL_WB_ON_ITR_M; 101 intr->dyn_ctl_swint_trig_m = PF_GLINT_DYN_CTL_SWINT_TRIG_M; 102 intr->dyn_ctl_sw_itridx_ena_m = 103 PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M; 104 105 spacing = IDPF_ITR_IDX_SPACING(reg->itrn_index_spacing, 106 IDPF_PF_ITR_IDX_SPACING); 107 rx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_0, 108 reg->itrn_reg, spacing); 109 tx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_1, 110 reg->itrn_reg, spacing); 111 intr->rx_itr = libie_pci_get_mmio_addr(mmio, rx_itr); 112 intr->tx_itr = libie_pci_get_mmio_addr(mmio, tx_itr); 113 } 114 115 /* Data vector for NOIRQ queues */ 116 117 val = reg_vals[rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC].dyn_ctl_reg; 118 rsrc->noirq_dyn_ctl = 119 libie_pci_get_mmio_addr(&adapter->ctlq_ctx.mmio_info, val); 120 121 val = PF_GLINT_DYN_CTL_WB_ON_ITR_M | PF_GLINT_DYN_CTL_INTENA_MSK_M | 122 FIELD_PREP(PF_GLINT_DYN_CTL_ITR_INDX_M, IDPF_NO_ITR_UPDATE_IDX); 123 rsrc->noirq_dyn_ctl_ena = val; 124 125 free_reg_vals: 126 kfree(reg_vals); 127 128 return err; 129 } 130 131 /** 132 * idpf_reset_reg_init - Initialize reset registers 133 * @adapter: Driver specific private structure 134 */ 135 static void idpf_reset_reg_init(struct idpf_adapter *adapter) 136 { 137 adapter->reset_reg.rstat = 138 libie_pci_get_mmio_addr(&adapter->ctlq_ctx.mmio_info, 139 PFGEN_RSTAT); 140 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M; 141 } 142 143 /** 144 * idpf_trigger_reset - trigger reset 145 * @adapter: Driver specific private structure 146 * @trig_cause: Reason to trigger a reset 147 */ 148 static void idpf_trigger_reset(struct idpf_adapter *adapter, 149 enum idpf_flags __always_unused trig_cause) 150 { 151 void __iomem *addr; 152 153 addr = libie_pci_get_mmio_addr(&adapter->ctlq_ctx.mmio_info, 154 PFGEN_CTRL); 155 writel(readl(addr) | PFGEN_CTRL_PFSWR, addr); 156 } 157 158 /** 159 * idpf_ptp_reg_init - Initialize required registers 160 * @adapter: Driver specific private structure 161 * 162 * Set the bits required for enabling shtime and cmd execution 163 */ 164 static void idpf_ptp_reg_init(const struct idpf_adapter *adapter) 165 { 166 adapter->ptp->cmd.shtime_enable_mask = PF_GLTSYN_CMD_SYNC_SHTIME_EN_M; 167 adapter->ptp->cmd.exec_cmd_mask = PF_GLTSYN_CMD_SYNC_EXEC_CMD_M; 168 } 169 170 /** 171 * idpf_idc_register - register for IDC callbacks 172 * @adapter: Driver specific private structure 173 * 174 * Return: 0 on success or error code on failure. 175 */ 176 static int idpf_idc_register(struct idpf_adapter *adapter) 177 { 178 return idpf_idc_init_aux_core_dev(adapter, IIDC_FUNCTION_TYPE_PF); 179 } 180 181 /** 182 * idpf_reg_ops_init - Initialize register API function pointers 183 * @adapter: Driver specific private structure 184 */ 185 static void idpf_reg_ops_init(struct idpf_adapter *adapter) 186 { 187 adapter->dev_ops.reg_ops.ctlq_reg_init = idpf_ctlq_reg_init; 188 adapter->dev_ops.reg_ops.intr_reg_init = idpf_intr_reg_init; 189 adapter->dev_ops.reg_ops.mb_intr_reg_init = idpf_mb_intr_reg_init; 190 adapter->dev_ops.reg_ops.reset_reg_init = idpf_reset_reg_init; 191 adapter->dev_ops.reg_ops.trigger_reset = idpf_trigger_reset; 192 adapter->dev_ops.reg_ops.ptp_reg_init = idpf_ptp_reg_init; 193 } 194 195 /** 196 * idpf_dev_ops_init - Initialize device API function pointers 197 * @adapter: Driver specific private structure 198 */ 199 void idpf_dev_ops_init(struct idpf_adapter *adapter) 200 { 201 idpf_reg_ops_init(adapter); 202 203 adapter->dev_ops.idc_init = idpf_idc_register; 204 205 resource_set_range(&adapter->dev_ops.static_reg_info[0], 206 PF_FW_BASE, IDPF_PF_MBX_REGION_SZ); 207 resource_set_range(&adapter->dev_ops.static_reg_info[1], 208 PFGEN_RTRIG, IDPF_PF_RSTAT_REGION_SZ); 209 } 210