1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #include "idpf.h" 5 #include "idpf_lan_pf_regs.h" 6 7 #define IDPF_PF_ITR_IDX_SPACING 0x4 8 9 /** 10 * idpf_ctlq_reg_init - initialize default mailbox registers 11 * @cq: pointer to the array of create control queues 12 */ 13 static void idpf_ctlq_reg_init(struct idpf_ctlq_create_info *cq) 14 { 15 int i; 16 17 for (i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) { 18 struct idpf_ctlq_create_info *ccq = cq + i; 19 20 switch (ccq->type) { 21 case IDPF_CTLQ_TYPE_MAILBOX_TX: 22 /* set head and tail registers in our local struct */ 23 ccq->reg.head = PF_FW_ATQH; 24 ccq->reg.tail = PF_FW_ATQT; 25 ccq->reg.len = PF_FW_ATQLEN; 26 ccq->reg.bah = PF_FW_ATQBAH; 27 ccq->reg.bal = PF_FW_ATQBAL; 28 ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M; 29 ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; 30 ccq->reg.head_mask = PF_FW_ATQH_ATQH_M; 31 break; 32 case IDPF_CTLQ_TYPE_MAILBOX_RX: 33 /* set head and tail registers in our local struct */ 34 ccq->reg.head = PF_FW_ARQH; 35 ccq->reg.tail = PF_FW_ARQT; 36 ccq->reg.len = PF_FW_ARQLEN; 37 ccq->reg.bah = PF_FW_ARQBAH; 38 ccq->reg.bal = PF_FW_ARQBAL; 39 ccq->reg.len_mask = PF_FW_ARQLEN_ARQLEN_M; 40 ccq->reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; 41 ccq->reg.head_mask = PF_FW_ARQH_ARQH_M; 42 break; 43 default: 44 break; 45 } 46 } 47 } 48 49 /** 50 * idpf_mb_intr_reg_init - Initialize mailbox interrupt register 51 * @adapter: adapter structure 52 */ 53 static void idpf_mb_intr_reg_init(struct idpf_adapter *adapter) 54 { 55 struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg; 56 u32 dyn_ctl = le32_to_cpu(adapter->caps.mailbox_dyn_ctl); 57 58 intr->dyn_ctl = idpf_get_reg_addr(adapter, dyn_ctl); 59 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 60 intr->dyn_ctl_itridx_m = PF_GLINT_DYN_CTL_ITR_INDX_M; 61 intr->icr_ena = idpf_get_reg_addr(adapter, PF_INT_DIR_OICR_ENA); 62 intr->icr_ena_ctlq_m = PF_INT_DIR_OICR_ENA_M; 63 } 64 65 /** 66 * idpf_intr_reg_init - Initialize interrupt registers 67 * @vport: virtual port structure 68 */ 69 static int idpf_intr_reg_init(struct idpf_vport *vport) 70 { 71 struct idpf_adapter *adapter = vport->adapter; 72 int num_vecs = vport->num_q_vectors; 73 struct idpf_vec_regs *reg_vals; 74 int num_regs, i, err = 0; 75 u32 rx_itr, tx_itr; 76 u16 total_vecs; 77 78 total_vecs = idpf_get_reserved_vecs(vport->adapter); 79 reg_vals = kcalloc(total_vecs, sizeof(struct idpf_vec_regs), 80 GFP_KERNEL); 81 if (!reg_vals) 82 return -ENOMEM; 83 84 num_regs = idpf_get_reg_intr_vecs(vport, reg_vals); 85 if (num_regs < num_vecs) { 86 err = -EINVAL; 87 goto free_reg_vals; 88 } 89 90 for (i = 0; i < num_vecs; i++) { 91 struct idpf_q_vector *q_vector = &vport->q_vectors[i]; 92 u16 vec_id = vport->q_vector_idxs[i] - IDPF_MBX_Q_VEC; 93 struct idpf_intr_reg *intr = &q_vector->intr_reg; 94 u32 spacing; 95 96 intr->dyn_ctl = idpf_get_reg_addr(adapter, 97 reg_vals[vec_id].dyn_ctl_reg); 98 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M; 99 intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S; 100 intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S; 101 102 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing, 103 IDPF_PF_ITR_IDX_SPACING); 104 rx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_0, 105 reg_vals[vec_id].itrn_reg, 106 spacing); 107 tx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_1, 108 reg_vals[vec_id].itrn_reg, 109 spacing); 110 intr->rx_itr = idpf_get_reg_addr(adapter, rx_itr); 111 intr->tx_itr = idpf_get_reg_addr(adapter, tx_itr); 112 } 113 114 free_reg_vals: 115 kfree(reg_vals); 116 117 return err; 118 } 119 120 /** 121 * idpf_reset_reg_init - Initialize reset registers 122 * @adapter: Driver specific private structure 123 */ 124 static void idpf_reset_reg_init(struct idpf_adapter *adapter) 125 { 126 adapter->reset_reg.rstat = idpf_get_reg_addr(adapter, PFGEN_RSTAT); 127 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M; 128 } 129 130 /** 131 * idpf_trigger_reset - trigger reset 132 * @adapter: Driver specific private structure 133 * @trig_cause: Reason to trigger a reset 134 */ 135 static void idpf_trigger_reset(struct idpf_adapter *adapter, 136 enum idpf_flags __always_unused trig_cause) 137 { 138 u32 reset_reg; 139 140 reset_reg = readl(idpf_get_reg_addr(adapter, PFGEN_CTRL)); 141 writel(reset_reg | PFGEN_CTRL_PFSWR, 142 idpf_get_reg_addr(adapter, PFGEN_CTRL)); 143 } 144 145 /** 146 * idpf_reg_ops_init - Initialize register API function pointers 147 * @adapter: Driver specific private structure 148 */ 149 static void idpf_reg_ops_init(struct idpf_adapter *adapter) 150 { 151 adapter->dev_ops.reg_ops.ctlq_reg_init = idpf_ctlq_reg_init; 152 adapter->dev_ops.reg_ops.intr_reg_init = idpf_intr_reg_init; 153 adapter->dev_ops.reg_ops.mb_intr_reg_init = idpf_mb_intr_reg_init; 154 adapter->dev_ops.reg_ops.reset_reg_init = idpf_reset_reg_init; 155 adapter->dev_ops.reg_ops.trigger_reset = idpf_trigger_reset; 156 } 157 158 /** 159 * idpf_dev_ops_init - Initialize device API function pointers 160 * @adapter: Driver specific private structure 161 */ 162 void idpf_dev_ops_init(struct idpf_adapter *adapter) 163 { 164 idpf_reg_ops_init(adapter); 165 } 166