1*be7f0c1fSKarol Kolacinski /* SPDX-License-Identifier: GPL-2.0 */ 2*be7f0c1fSKarol Kolacinski /* Copyright (c) 2025, Intel Corporation. */ 3*be7f0c1fSKarol Kolacinski 4*be7f0c1fSKarol Kolacinski #ifndef _ICE_TSPLL_H_ 5*be7f0c1fSKarol Kolacinski #define _ICE_TSPLL_H_ 6*be7f0c1fSKarol Kolacinski 7*be7f0c1fSKarol Kolacinski /** 8*be7f0c1fSKarol Kolacinski * struct ice_cgu_pll_params_e82x - E82X CGU parameters 9*be7f0c1fSKarol Kolacinski * @refclk_pre_div: Reference clock pre-divisor 10*be7f0c1fSKarol Kolacinski * @feedback_div: Feedback divisor 11*be7f0c1fSKarol Kolacinski * @frac_n_div: Fractional divisor 12*be7f0c1fSKarol Kolacinski * @post_pll_div: Post PLL divisor 13*be7f0c1fSKarol Kolacinski * 14*be7f0c1fSKarol Kolacinski * Clock Generation Unit parameters used to program the PLL based on the 15*be7f0c1fSKarol Kolacinski * selected TIME_REF frequency. 16*be7f0c1fSKarol Kolacinski */ 17*be7f0c1fSKarol Kolacinski struct ice_cgu_pll_params_e82x { 18*be7f0c1fSKarol Kolacinski u32 refclk_pre_div; 19*be7f0c1fSKarol Kolacinski u32 feedback_div; 20*be7f0c1fSKarol Kolacinski u32 frac_n_div; 21*be7f0c1fSKarol Kolacinski u32 post_pll_div; 22*be7f0c1fSKarol Kolacinski }; 23*be7f0c1fSKarol Kolacinski 24*be7f0c1fSKarol Kolacinski /** 25*be7f0c1fSKarol Kolacinski * struct ice_cgu_pll_params_e825c - E825C CGU parameters 26*be7f0c1fSKarol Kolacinski * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection 27*be7f0c1fSKarol Kolacinski * @tspll_ndivratio: ndiv ratio that goes directly to the pll 28*be7f0c1fSKarol Kolacinski * @tspll_fbdiv_intgr: TS PLL integer feedback divide 29*be7f0c1fSKarol Kolacinski * @tspll_fbdiv_frac: TS PLL fractional feedback divide 30*be7f0c1fSKarol Kolacinski * @ref1588_ck_div: clock divider for tspll ref 31*be7f0c1fSKarol Kolacinski * 32*be7f0c1fSKarol Kolacinski * Clock Generation Unit parameters used to program the PLL based on the 33*be7f0c1fSKarol Kolacinski * selected TIME_REF/TCXO frequency. 34*be7f0c1fSKarol Kolacinski */ 35*be7f0c1fSKarol Kolacinski struct ice_cgu_pll_params_e825c { 36*be7f0c1fSKarol Kolacinski u32 tspll_ck_refclkfreq; 37*be7f0c1fSKarol Kolacinski u32 tspll_ndivratio; 38*be7f0c1fSKarol Kolacinski u32 tspll_fbdiv_intgr; 39*be7f0c1fSKarol Kolacinski u32 tspll_fbdiv_frac; 40*be7f0c1fSKarol Kolacinski u32 ref1588_ck_div; 41*be7f0c1fSKarol Kolacinski }; 42*be7f0c1fSKarol Kolacinski 43*be7f0c1fSKarol Kolacinski int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable); 44*be7f0c1fSKarol Kolacinski int ice_init_cgu_e82x(struct ice_hw *hw); 45*be7f0c1fSKarol Kolacinski 46*be7f0c1fSKarol Kolacinski #endif /* _ICE_TSPLL_H_ */ 47