1be7f0c1fSKarol Kolacinski /* SPDX-License-Identifier: GPL-2.0 */ 2be7f0c1fSKarol Kolacinski /* Copyright (c) 2025, Intel Corporation. */ 3be7f0c1fSKarol Kolacinski 4be7f0c1fSKarol Kolacinski #ifndef _ICE_TSPLL_H_ 5be7f0c1fSKarol Kolacinski #define _ICE_TSPLL_H_ 6be7f0c1fSKarol Kolacinski 7be7f0c1fSKarol Kolacinski /** 8*1ff7a6c5SKarol Kolacinski * struct ice_tspll_params_e82x - E82X TSPLL parameters 9be7f0c1fSKarol Kolacinski * @refclk_pre_div: Reference clock pre-divisor 10be7f0c1fSKarol Kolacinski * @feedback_div: Feedback divisor 11be7f0c1fSKarol Kolacinski * @frac_n_div: Fractional divisor 12be7f0c1fSKarol Kolacinski * @post_pll_div: Post PLL divisor 13be7f0c1fSKarol Kolacinski * 14be7f0c1fSKarol Kolacinski * Clock Generation Unit parameters used to program the PLL based on the 15*1ff7a6c5SKarol Kolacinski * selected TIME_REF/TCXO frequency. 16be7f0c1fSKarol Kolacinski */ 17*1ff7a6c5SKarol Kolacinski struct ice_tspll_params_e82x { 18be7f0c1fSKarol Kolacinski u32 refclk_pre_div; 19be7f0c1fSKarol Kolacinski u32 feedback_div; 20be7f0c1fSKarol Kolacinski u32 frac_n_div; 21be7f0c1fSKarol Kolacinski u32 post_pll_div; 22be7f0c1fSKarol Kolacinski }; 23be7f0c1fSKarol Kolacinski 24be7f0c1fSKarol Kolacinski /** 25*1ff7a6c5SKarol Kolacinski * struct ice_tspll_params_e825c - E825-C TSPLL parameters 26*1ff7a6c5SKarol Kolacinski * @ck_refclkfreq: ck_refclkfreq selection 27*1ff7a6c5SKarol Kolacinski * @ndivratio: ndiv ratio that goes directly to the PLL 28*1ff7a6c5SKarol Kolacinski * @fbdiv_intgr: TSPLL integer feedback divisor 29*1ff7a6c5SKarol Kolacinski * @fbdiv_frac: TSPLL fractional feedback divisor 30*1ff7a6c5SKarol Kolacinski * @ref1588_ck_div: clock divisor for tspll ref 31be7f0c1fSKarol Kolacinski * 32be7f0c1fSKarol Kolacinski * Clock Generation Unit parameters used to program the PLL based on the 33be7f0c1fSKarol Kolacinski * selected TIME_REF/TCXO frequency. 34be7f0c1fSKarol Kolacinski */ 35*1ff7a6c5SKarol Kolacinski struct ice_tspll_params_e825c { 36*1ff7a6c5SKarol Kolacinski u32 ck_refclkfreq; 37*1ff7a6c5SKarol Kolacinski u32 ndivratio; 38*1ff7a6c5SKarol Kolacinski u32 fbdiv_intgr; 39*1ff7a6c5SKarol Kolacinski u32 fbdiv_frac; 40be7f0c1fSKarol Kolacinski u32 ref1588_ck_div; 41be7f0c1fSKarol Kolacinski }; 42be7f0c1fSKarol Kolacinski 43*1ff7a6c5SKarol Kolacinski int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable); 44*1ff7a6c5SKarol Kolacinski int ice_tspll_init(struct ice_hw *hw); 45be7f0c1fSKarol Kolacinski 46be7f0c1fSKarol Kolacinski #endif /* _ICE_TSPLL_H_ */ 47