1be7f0c1fSKarol Kolacinski /* SPDX-License-Identifier: GPL-2.0 */ 2be7f0c1fSKarol Kolacinski /* Copyright (c) 2025, Intel Corporation. */ 3be7f0c1fSKarol Kolacinski 4be7f0c1fSKarol Kolacinski #ifndef _ICE_TSPLL_H_ 5be7f0c1fSKarol Kolacinski #define _ICE_TSPLL_H_ 6be7f0c1fSKarol Kolacinski 7be7f0c1fSKarol Kolacinski /** 81ff7a6c5SKarol Kolacinski * struct ice_tspll_params_e82x - E82X TSPLL parameters 9be7f0c1fSKarol Kolacinski * @refclk_pre_div: Reference clock pre-divisor 10*b3b26c98SKarol Kolacinski * @post_pll_div: Post PLL divisor 11be7f0c1fSKarol Kolacinski * @feedback_div: Feedback divisor 12be7f0c1fSKarol Kolacinski * @frac_n_div: Fractional divisor 13be7f0c1fSKarol Kolacinski * 14be7f0c1fSKarol Kolacinski * Clock Generation Unit parameters used to program the PLL based on the 151ff7a6c5SKarol Kolacinski * selected TIME_REF/TCXO frequency. 16be7f0c1fSKarol Kolacinski */ 171ff7a6c5SKarol Kolacinski struct ice_tspll_params_e82x { 18*b3b26c98SKarol Kolacinski u8 refclk_pre_div; 19*b3b26c98SKarol Kolacinski u8 post_pll_div; 20*b3b26c98SKarol Kolacinski u8 feedback_div; 21be7f0c1fSKarol Kolacinski u32 frac_n_div; 22be7f0c1fSKarol Kolacinski }; 23be7f0c1fSKarol Kolacinski 24b14b2d07SKarol Kolacinski #define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F 25b14b2d07SKarol Kolacinski #define ICE_TSPLL_NDIVRATIO_E825 5 26b14b2d07SKarol Kolacinski #define ICE_TSPLL_FBDIV_INTGR_E825 256 27be7f0c1fSKarol Kolacinski 281ff7a6c5SKarol Kolacinski int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable); 291ff7a6c5SKarol Kolacinski int ice_tspll_init(struct ice_hw *hw); 30be7f0c1fSKarol Kolacinski 31be7f0c1fSKarol Kolacinski #endif /* _ICE_TSPLL_H_ */ 32