1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_sched.h" 5 6 /** 7 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB 8 * @pi: port information structure 9 * @info: Scheduler element information from firmware 10 * 11 * This function inserts the root node of the scheduling tree topology 12 * to the SW DB. 13 */ 14 static enum ice_status 15 ice_sched_add_root_node(struct ice_port_info *pi, 16 struct ice_aqc_txsched_elem_data *info) 17 { 18 struct ice_sched_node *root; 19 struct ice_hw *hw; 20 21 if (!pi) 22 return ICE_ERR_PARAM; 23 24 hw = pi->hw; 25 26 root = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*root), GFP_KERNEL); 27 if (!root) 28 return ICE_ERR_NO_MEMORY; 29 30 /* coverity[suspicious_sizeof] */ 31 root->children = devm_kcalloc(ice_hw_to_dev(hw), hw->max_children[0], 32 sizeof(*root), GFP_KERNEL); 33 if (!root->children) { 34 devm_kfree(ice_hw_to_dev(hw), root); 35 return ICE_ERR_NO_MEMORY; 36 } 37 38 memcpy(&root->info, info, sizeof(*info)); 39 pi->root = root; 40 return 0; 41 } 42 43 /** 44 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB 45 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree 46 * @teid: node TEID to search 47 * 48 * This function searches for a node matching the TEID in the scheduling tree 49 * from the SW DB. The search is recursive and is restricted by the number of 50 * layers it has searched through; stopping at the max supported layer. 51 * 52 * This function needs to be called when holding the port_info->sched_lock 53 */ 54 struct ice_sched_node * 55 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid) 56 { 57 u16 i; 58 59 /* The TEID is same as that of the start_node */ 60 if (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid) 61 return start_node; 62 63 /* The node has no children or is at the max layer */ 64 if (!start_node->num_children || 65 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM || 66 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) 67 return NULL; 68 69 /* Check if TEID matches to any of the children nodes */ 70 for (i = 0; i < start_node->num_children; i++) 71 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid) 72 return start_node->children[i]; 73 74 /* Search within each child's sub-tree */ 75 for (i = 0; i < start_node->num_children; i++) { 76 struct ice_sched_node *tmp; 77 78 tmp = ice_sched_find_node_by_teid(start_node->children[i], 79 teid); 80 if (tmp) 81 return tmp; 82 } 83 84 return NULL; 85 } 86 87 /** 88 * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd 89 * @hw: pointer to the HW struct 90 * @cmd_opc: cmd opcode 91 * @elems_req: number of elements to request 92 * @buf: pointer to buffer 93 * @buf_size: buffer size in bytes 94 * @elems_resp: returns total number of elements response 95 * @cd: pointer to command details structure or NULL 96 * 97 * This function sends a scheduling elements cmd (cmd_opc) 98 */ 99 static enum ice_status 100 ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc, 101 u16 elems_req, void *buf, u16 buf_size, 102 u16 *elems_resp, struct ice_sq_cd *cd) 103 { 104 struct ice_aqc_sched_elem_cmd *cmd; 105 struct ice_aq_desc desc; 106 enum ice_status status; 107 108 cmd = &desc.params.sched_elem_cmd; 109 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc); 110 cmd->num_elem_req = cpu_to_le16(elems_req); 111 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 113 if (!status && elems_resp) 114 *elems_resp = le16_to_cpu(cmd->num_elem_resp); 115 116 return status; 117 } 118 119 /** 120 * ice_aq_query_sched_elems - query scheduler elements 121 * @hw: pointer to the HW struct 122 * @elems_req: number of elements to query 123 * @buf: pointer to buffer 124 * @buf_size: buffer size in bytes 125 * @elems_ret: returns total number of elements returned 126 * @cd: pointer to command details structure or NULL 127 * 128 * Query scheduling elements (0x0404) 129 */ 130 enum ice_status 131 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 132 struct ice_aqc_get_elem *buf, u16 buf_size, 133 u16 *elems_ret, struct ice_sq_cd *cd) 134 { 135 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems, 136 elems_req, (void *)buf, buf_size, 137 elems_ret, cd); 138 } 139 140 /** 141 * ice_sched_add_node - Insert the Tx scheduler node in SW DB 142 * @pi: port information structure 143 * @layer: Scheduler layer of the node 144 * @info: Scheduler element information from firmware 145 * 146 * This function inserts a scheduler node to the SW DB. 147 */ 148 enum ice_status 149 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 150 struct ice_aqc_txsched_elem_data *info) 151 { 152 struct ice_sched_node *parent; 153 struct ice_aqc_get_elem elem; 154 struct ice_sched_node *node; 155 enum ice_status status; 156 struct ice_hw *hw; 157 158 if (!pi) 159 return ICE_ERR_PARAM; 160 161 hw = pi->hw; 162 163 /* A valid parent node should be there */ 164 parent = ice_sched_find_node_by_teid(pi->root, 165 le32_to_cpu(info->parent_teid)); 166 if (!parent) { 167 ice_debug(hw, ICE_DBG_SCHED, 168 "Parent Node not found for parent_teid=0x%x\n", 169 le32_to_cpu(info->parent_teid)); 170 return ICE_ERR_PARAM; 171 } 172 173 /* query the current node information from FW before additing it 174 * to the SW DB 175 */ 176 status = ice_sched_query_elem(hw, le32_to_cpu(info->node_teid), &elem); 177 if (status) 178 return status; 179 180 node = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*node), GFP_KERNEL); 181 if (!node) 182 return ICE_ERR_NO_MEMORY; 183 if (hw->max_children[layer]) { 184 /* coverity[suspicious_sizeof] */ 185 node->children = devm_kcalloc(ice_hw_to_dev(hw), 186 hw->max_children[layer], 187 sizeof(*node), GFP_KERNEL); 188 if (!node->children) { 189 devm_kfree(ice_hw_to_dev(hw), node); 190 return ICE_ERR_NO_MEMORY; 191 } 192 } 193 194 node->in_use = true; 195 node->parent = parent; 196 node->tx_sched_layer = layer; 197 parent->children[parent->num_children++] = node; 198 memcpy(&node->info, &elem.generic[0], sizeof(node->info)); 199 return 0; 200 } 201 202 /** 203 * ice_aq_delete_sched_elems - delete scheduler elements 204 * @hw: pointer to the HW struct 205 * @grps_req: number of groups to delete 206 * @buf: pointer to buffer 207 * @buf_size: buffer size in bytes 208 * @grps_del: returns total number of elements deleted 209 * @cd: pointer to command details structure or NULL 210 * 211 * Delete scheduling elements (0x040F) 212 */ 213 static enum ice_status 214 ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req, 215 struct ice_aqc_delete_elem *buf, u16 buf_size, 216 u16 *grps_del, struct ice_sq_cd *cd) 217 { 218 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems, 219 grps_req, (void *)buf, buf_size, 220 grps_del, cd); 221 } 222 223 /** 224 * ice_sched_remove_elems - remove nodes from HW 225 * @hw: pointer to the HW struct 226 * @parent: pointer to the parent node 227 * @num_nodes: number of nodes 228 * @node_teids: array of node teids to be deleted 229 * 230 * This function remove nodes from HW 231 */ 232 static enum ice_status 233 ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent, 234 u16 num_nodes, u32 *node_teids) 235 { 236 struct ice_aqc_delete_elem *buf; 237 u16 i, num_groups_removed = 0; 238 enum ice_status status; 239 u16 buf_size; 240 241 buf_size = sizeof(*buf) + sizeof(u32) * (num_nodes - 1); 242 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL); 243 if (!buf) 244 return ICE_ERR_NO_MEMORY; 245 246 buf->hdr.parent_teid = parent->info.node_teid; 247 buf->hdr.num_elems = cpu_to_le16(num_nodes); 248 for (i = 0; i < num_nodes; i++) 249 buf->teid[i] = cpu_to_le32(node_teids[i]); 250 251 status = ice_aq_delete_sched_elems(hw, 1, buf, buf_size, 252 &num_groups_removed, NULL); 253 if (status || num_groups_removed != 1) 254 ice_debug(hw, ICE_DBG_SCHED, "remove node failed FW error %d\n", 255 hw->adminq.sq_last_status); 256 257 devm_kfree(ice_hw_to_dev(hw), buf); 258 return status; 259 } 260 261 /** 262 * ice_sched_get_first_node - get the first node of the given layer 263 * @pi: port information structure 264 * @parent: pointer the base node of the subtree 265 * @layer: layer number 266 * 267 * This function retrieves the first node of the given layer from the subtree 268 */ 269 static struct ice_sched_node * 270 ice_sched_get_first_node(struct ice_port_info *pi, 271 struct ice_sched_node *parent, u8 layer) 272 { 273 return pi->sib_head[parent->tc_num][layer]; 274 } 275 276 /** 277 * ice_sched_get_tc_node - get pointer to TC node 278 * @pi: port information structure 279 * @tc: TC number 280 * 281 * This function returns the TC node pointer 282 */ 283 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc) 284 { 285 u8 i; 286 287 if (!pi || !pi->root) 288 return NULL; 289 for (i = 0; i < pi->root->num_children; i++) 290 if (pi->root->children[i]->tc_num == tc) 291 return pi->root->children[i]; 292 return NULL; 293 } 294 295 /** 296 * ice_free_sched_node - Free a Tx scheduler node from SW DB 297 * @pi: port information structure 298 * @node: pointer to the ice_sched_node struct 299 * 300 * This function frees up a node from SW DB as well as from HW 301 * 302 * This function needs to be called with the port_info->sched_lock held 303 */ 304 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node) 305 { 306 struct ice_sched_node *parent; 307 struct ice_hw *hw = pi->hw; 308 u8 i, j; 309 310 /* Free the children before freeing up the parent node 311 * The parent array is updated below and that shifts the nodes 312 * in the array. So always pick the first child if num children > 0 313 */ 314 while (node->num_children) 315 ice_free_sched_node(pi, node->children[0]); 316 317 /* Leaf, TC and root nodes can't be deleted by SW */ 318 if (node->tx_sched_layer >= hw->sw_entry_point_layer && 319 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 320 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT && 321 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) { 322 u32 teid = le32_to_cpu(node->info.node_teid); 323 324 ice_sched_remove_elems(hw, node->parent, 1, &teid); 325 } 326 parent = node->parent; 327 /* root has no parent */ 328 if (parent) { 329 struct ice_sched_node *p; 330 331 /* update the parent */ 332 for (i = 0; i < parent->num_children; i++) 333 if (parent->children[i] == node) { 334 for (j = i + 1; j < parent->num_children; j++) 335 parent->children[j - 1] = 336 parent->children[j]; 337 parent->num_children--; 338 break; 339 } 340 341 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer); 342 while (p) { 343 if (p->sibling == node) { 344 p->sibling = node->sibling; 345 break; 346 } 347 p = p->sibling; 348 } 349 350 /* update the sibling head if head is getting removed */ 351 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node) 352 pi->sib_head[node->tc_num][node->tx_sched_layer] = 353 node->sibling; 354 } 355 356 /* leaf nodes have no children */ 357 if (node->children) 358 devm_kfree(ice_hw_to_dev(hw), node->children); 359 devm_kfree(ice_hw_to_dev(hw), node); 360 } 361 362 /** 363 * ice_aq_get_dflt_topo - gets default scheduler topology 364 * @hw: pointer to the HW struct 365 * @lport: logical port number 366 * @buf: pointer to buffer 367 * @buf_size: buffer size in bytes 368 * @num_branches: returns total number of queue to port branches 369 * @cd: pointer to command details structure or NULL 370 * 371 * Get default scheduler topology (0x400) 372 */ 373 static enum ice_status 374 ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport, 375 struct ice_aqc_get_topo_elem *buf, u16 buf_size, 376 u8 *num_branches, struct ice_sq_cd *cd) 377 { 378 struct ice_aqc_get_topo *cmd; 379 struct ice_aq_desc desc; 380 enum ice_status status; 381 382 cmd = &desc.params.get_topo; 383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo); 384 cmd->port_num = lport; 385 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 386 if (!status && num_branches) 387 *num_branches = cmd->num_branches; 388 389 return status; 390 } 391 392 /** 393 * ice_aq_add_sched_elems - adds scheduling element 394 * @hw: pointer to the HW struct 395 * @grps_req: the number of groups that are requested to be added 396 * @buf: pointer to buffer 397 * @buf_size: buffer size in bytes 398 * @grps_added: returns total number of groups added 399 * @cd: pointer to command details structure or NULL 400 * 401 * Add scheduling elements (0x0401) 402 */ 403 static enum ice_status 404 ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req, 405 struct ice_aqc_add_elem *buf, u16 buf_size, 406 u16 *grps_added, struct ice_sq_cd *cd) 407 { 408 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems, 409 grps_req, (void *)buf, buf_size, 410 grps_added, cd); 411 } 412 413 /** 414 * ice_aq_cfg_sched_elems - configures scheduler elements 415 * @hw: pointer to the HW struct 416 * @elems_req: number of elements to configure 417 * @buf: pointer to buffer 418 * @buf_size: buffer size in bytes 419 * @elems_cfgd: returns total number of elements configured 420 * @cd: pointer to command details structure or NULL 421 * 422 * Configure scheduling elements (0x0403) 423 */ 424 static enum ice_status 425 ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, 426 struct ice_aqc_conf_elem *buf, u16 buf_size, 427 u16 *elems_cfgd, struct ice_sq_cd *cd) 428 { 429 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems, 430 elems_req, (void *)buf, buf_size, 431 elems_cfgd, cd); 432 } 433 434 /** 435 * ice_aq_suspend_sched_elems - suspend scheduler elements 436 * @hw: pointer to the HW struct 437 * @elems_req: number of elements to suspend 438 * @buf: pointer to buffer 439 * @buf_size: buffer size in bytes 440 * @elems_ret: returns total number of elements suspended 441 * @cd: pointer to command details structure or NULL 442 * 443 * Suspend scheduling elements (0x0409) 444 */ 445 static enum ice_status 446 ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req, 447 struct ice_aqc_suspend_resume_elem *buf, 448 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 449 { 450 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems, 451 elems_req, (void *)buf, buf_size, 452 elems_ret, cd); 453 } 454 455 /** 456 * ice_aq_resume_sched_elems - resume scheduler elements 457 * @hw: pointer to the HW struct 458 * @elems_req: number of elements to resume 459 * @buf: pointer to buffer 460 * @buf_size: buffer size in bytes 461 * @elems_ret: returns total number of elements resumed 462 * @cd: pointer to command details structure or NULL 463 * 464 * resume scheduling elements (0x040A) 465 */ 466 static enum ice_status 467 ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req, 468 struct ice_aqc_suspend_resume_elem *buf, 469 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 470 { 471 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems, 472 elems_req, (void *)buf, buf_size, 473 elems_ret, cd); 474 } 475 476 /** 477 * ice_aq_query_sched_res - query scheduler resource 478 * @hw: pointer to the HW struct 479 * @buf_size: buffer size in bytes 480 * @buf: pointer to buffer 481 * @cd: pointer to command details structure or NULL 482 * 483 * Query scheduler resource allocation (0x0412) 484 */ 485 static enum ice_status 486 ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size, 487 struct ice_aqc_query_txsched_res_resp *buf, 488 struct ice_sq_cd *cd) 489 { 490 struct ice_aq_desc desc; 491 492 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res); 493 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 494 } 495 496 /** 497 * ice_sched_suspend_resume_elems - suspend or resume HW nodes 498 * @hw: pointer to the HW struct 499 * @num_nodes: number of nodes 500 * @node_teids: array of node teids to be suspended or resumed 501 * @suspend: true means suspend / false means resume 502 * 503 * This function suspends or resumes HW nodes 504 */ 505 static enum ice_status 506 ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, 507 bool suspend) 508 { 509 struct ice_aqc_suspend_resume_elem *buf; 510 u16 i, buf_size, num_elem_ret = 0; 511 enum ice_status status; 512 513 buf_size = sizeof(*buf) * num_nodes; 514 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL); 515 if (!buf) 516 return ICE_ERR_NO_MEMORY; 517 518 for (i = 0; i < num_nodes; i++) 519 buf->teid[i] = cpu_to_le32(node_teids[i]); 520 521 if (suspend) 522 status = ice_aq_suspend_sched_elems(hw, num_nodes, buf, 523 buf_size, &num_elem_ret, 524 NULL); 525 else 526 status = ice_aq_resume_sched_elems(hw, num_nodes, buf, 527 buf_size, &num_elem_ret, 528 NULL); 529 if (status || num_elem_ret != num_nodes) 530 ice_debug(hw, ICE_DBG_SCHED, "suspend/resume failed\n"); 531 532 devm_kfree(ice_hw_to_dev(hw), buf); 533 return status; 534 } 535 536 /** 537 * ice_alloc_lan_q_ctx - allocate LAN queue contexts for the given VSI and TC 538 * @hw: pointer to the HW struct 539 * @vsi_handle: VSI handle 540 * @tc: TC number 541 * @new_numqs: number of queues 542 */ 543 static enum ice_status 544 ice_alloc_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs) 545 { 546 struct ice_vsi_ctx *vsi_ctx; 547 struct ice_q_ctx *q_ctx; 548 549 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 550 if (!vsi_ctx) 551 return ICE_ERR_PARAM; 552 /* allocate LAN queue contexts */ 553 if (!vsi_ctx->lan_q_ctx[tc]) { 554 vsi_ctx->lan_q_ctx[tc] = devm_kcalloc(ice_hw_to_dev(hw), 555 new_numqs, 556 sizeof(*q_ctx), 557 GFP_KERNEL); 558 if (!vsi_ctx->lan_q_ctx[tc]) 559 return ICE_ERR_NO_MEMORY; 560 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 561 return 0; 562 } 563 /* num queues are increased, update the queue contexts */ 564 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) { 565 u16 prev_num = vsi_ctx->num_lan_q_entries[tc]; 566 567 q_ctx = devm_kcalloc(ice_hw_to_dev(hw), new_numqs, 568 sizeof(*q_ctx), GFP_KERNEL); 569 if (!q_ctx) 570 return ICE_ERR_NO_MEMORY; 571 memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc], 572 prev_num * sizeof(*q_ctx)); 573 devm_kfree(ice_hw_to_dev(hw), vsi_ctx->lan_q_ctx[tc]); 574 vsi_ctx->lan_q_ctx[tc] = q_ctx; 575 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 576 } 577 return 0; 578 } 579 580 /** 581 * ice_aq_rl_profile - performs a rate limiting task 582 * @hw: pointer to the HW struct 583 * @opcode:opcode for add, query, or remove profile(s) 584 * @num_profiles: the number of profiles 585 * @buf: pointer to buffer 586 * @buf_size: buffer size in bytes 587 * @num_processed: number of processed add or remove profile(s) to return 588 * @cd: pointer to command details structure 589 * 590 * RL profile function to add, query, or remove profile(s) 591 */ 592 static enum ice_status 593 ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode, 594 u16 num_profiles, struct ice_aqc_rl_profile_generic_elem *buf, 595 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd) 596 { 597 struct ice_aqc_rl_profile *cmd; 598 struct ice_aq_desc desc; 599 enum ice_status status; 600 601 cmd = &desc.params.rl_profile; 602 603 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 604 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 605 cmd->num_profiles = cpu_to_le16(num_profiles); 606 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 607 if (!status && num_processed) 608 *num_processed = le16_to_cpu(cmd->num_processed); 609 return status; 610 } 611 612 /** 613 * ice_aq_add_rl_profile - adds rate limiting profile(s) 614 * @hw: pointer to the HW struct 615 * @num_profiles: the number of profile(s) to be add 616 * @buf: pointer to buffer 617 * @buf_size: buffer size in bytes 618 * @num_profiles_added: total number of profiles added to return 619 * @cd: pointer to command details structure 620 * 621 * Add RL profile (0x0410) 622 */ 623 static enum ice_status 624 ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles, 625 struct ice_aqc_rl_profile_generic_elem *buf, 626 u16 buf_size, u16 *num_profiles_added, 627 struct ice_sq_cd *cd) 628 { 629 return ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles, 630 num_profiles, buf, 631 buf_size, num_profiles_added, cd); 632 } 633 634 /** 635 * ice_aq_remove_rl_profile - removes RL profile(s) 636 * @hw: pointer to the HW struct 637 * @num_profiles: the number of profile(s) to remove 638 * @buf: pointer to buffer 639 * @buf_size: buffer size in bytes 640 * @num_profiles_removed: total number of profiles removed to return 641 * @cd: pointer to command details structure or NULL 642 * 643 * Remove RL profile (0x0415) 644 */ 645 static enum ice_status 646 ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles, 647 struct ice_aqc_rl_profile_generic_elem *buf, 648 u16 buf_size, u16 *num_profiles_removed, 649 struct ice_sq_cd *cd) 650 { 651 return ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles, 652 num_profiles, buf, 653 buf_size, num_profiles_removed, cd); 654 } 655 656 /** 657 * ice_sched_del_rl_profile - remove RL profile 658 * @hw: pointer to the HW struct 659 * @rl_info: rate limit profile information 660 * 661 * If the profile ID is not referenced anymore, it removes profile ID with 662 * its associated parameters from HW DB,and locally. The caller needs to 663 * hold scheduler lock. 664 */ 665 static enum ice_status 666 ice_sched_del_rl_profile(struct ice_hw *hw, 667 struct ice_aqc_rl_profile_info *rl_info) 668 { 669 struct ice_aqc_rl_profile_generic_elem *buf; 670 u16 num_profiles_removed; 671 enum ice_status status; 672 u16 num_profiles = 1; 673 674 if (rl_info->prof_id_ref != 0) 675 return ICE_ERR_IN_USE; 676 677 /* Safe to remove profile ID */ 678 buf = (struct ice_aqc_rl_profile_generic_elem *) 679 &rl_info->profile; 680 status = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf), 681 &num_profiles_removed, NULL); 682 if (status || num_profiles_removed != num_profiles) 683 return ICE_ERR_CFG; 684 685 /* Delete stale entry now */ 686 list_del(&rl_info->list_entry); 687 devm_kfree(ice_hw_to_dev(hw), rl_info); 688 return status; 689 } 690 691 /** 692 * ice_sched_clear_rl_prof - clears RL prof entries 693 * @pi: port information structure 694 * 695 * This function removes all RL profile from HW as well as from SW DB. 696 */ 697 static void ice_sched_clear_rl_prof(struct ice_port_info *pi) 698 { 699 u16 ln; 700 701 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) { 702 struct ice_aqc_rl_profile_info *rl_prof_elem; 703 struct ice_aqc_rl_profile_info *rl_prof_tmp; 704 705 list_for_each_entry_safe(rl_prof_elem, rl_prof_tmp, 706 &pi->rl_prof_list[ln], list_entry) { 707 struct ice_hw *hw = pi->hw; 708 enum ice_status status; 709 710 rl_prof_elem->prof_id_ref = 0; 711 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 712 if (status) { 713 ice_debug(hw, ICE_DBG_SCHED, 714 "Remove rl profile failed\n"); 715 /* On error, free mem required */ 716 list_del(&rl_prof_elem->list_entry); 717 devm_kfree(ice_hw_to_dev(hw), rl_prof_elem); 718 } 719 } 720 } 721 } 722 723 /** 724 * ice_sched_clear_agg - clears the aggregator related information 725 * @hw: pointer to the hardware structure 726 * 727 * This function removes aggregator list and free up aggregator related memory 728 * previously allocated. 729 */ 730 void ice_sched_clear_agg(struct ice_hw *hw) 731 { 732 struct ice_sched_agg_info *agg_info; 733 struct ice_sched_agg_info *atmp; 734 735 list_for_each_entry_safe(agg_info, atmp, &hw->agg_list, list_entry) { 736 struct ice_sched_agg_vsi_info *agg_vsi_info; 737 struct ice_sched_agg_vsi_info *vtmp; 738 739 list_for_each_entry_safe(agg_vsi_info, vtmp, 740 &agg_info->agg_vsi_list, list_entry) { 741 list_del(&agg_vsi_info->list_entry); 742 devm_kfree(ice_hw_to_dev(hw), agg_vsi_info); 743 } 744 list_del(&agg_info->list_entry); 745 devm_kfree(ice_hw_to_dev(hw), agg_info); 746 } 747 } 748 749 /** 750 * ice_sched_clear_tx_topo - clears the scheduler tree nodes 751 * @pi: port information structure 752 * 753 * This function removes all the nodes from HW as well as from SW DB. 754 */ 755 static void ice_sched_clear_tx_topo(struct ice_port_info *pi) 756 { 757 if (!pi) 758 return; 759 /* remove RL profiles related lists */ 760 ice_sched_clear_rl_prof(pi); 761 if (pi->root) { 762 ice_free_sched_node(pi, pi->root); 763 pi->root = NULL; 764 } 765 } 766 767 /** 768 * ice_sched_clear_port - clear the scheduler elements from SW DB for a port 769 * @pi: port information structure 770 * 771 * Cleanup scheduling elements from SW DB 772 */ 773 void ice_sched_clear_port(struct ice_port_info *pi) 774 { 775 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 776 return; 777 778 pi->port_state = ICE_SCHED_PORT_STATE_INIT; 779 mutex_lock(&pi->sched_lock); 780 ice_sched_clear_tx_topo(pi); 781 mutex_unlock(&pi->sched_lock); 782 mutex_destroy(&pi->sched_lock); 783 } 784 785 /** 786 * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports 787 * @hw: pointer to the HW struct 788 * 789 * Cleanup scheduling elements from SW DB for all the ports 790 */ 791 void ice_sched_cleanup_all(struct ice_hw *hw) 792 { 793 if (!hw) 794 return; 795 796 if (hw->layer_info) { 797 devm_kfree(ice_hw_to_dev(hw), hw->layer_info); 798 hw->layer_info = NULL; 799 } 800 801 if (hw->port_info) 802 ice_sched_clear_port(hw->port_info); 803 804 hw->num_tx_sched_layers = 0; 805 hw->num_tx_sched_phys_layers = 0; 806 hw->flattened_layers = 0; 807 hw->max_cgds = 0; 808 } 809 810 /** 811 * ice_sched_add_elems - add nodes to HW and SW DB 812 * @pi: port information structure 813 * @tc_node: pointer to the branch node 814 * @parent: pointer to the parent node 815 * @layer: layer number to add nodes 816 * @num_nodes: number of nodes 817 * @num_nodes_added: pointer to num nodes added 818 * @first_node_teid: if new nodes are added then return the TEID of first node 819 * 820 * This function add nodes to HW as well as to SW DB for a given layer 821 */ 822 static enum ice_status 823 ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, 824 struct ice_sched_node *parent, u8 layer, u16 num_nodes, 825 u16 *num_nodes_added, u32 *first_node_teid) 826 { 827 struct ice_sched_node *prev, *new_node; 828 struct ice_aqc_add_elem *buf; 829 u16 i, num_groups_added = 0; 830 enum ice_status status = 0; 831 struct ice_hw *hw = pi->hw; 832 size_t buf_size; 833 u32 teid; 834 835 buf_size = struct_size(buf, generic, num_nodes - 1); 836 buf = devm_kzalloc(ice_hw_to_dev(hw), buf_size, GFP_KERNEL); 837 if (!buf) 838 return ICE_ERR_NO_MEMORY; 839 840 buf->hdr.parent_teid = parent->info.node_teid; 841 buf->hdr.num_elems = cpu_to_le16(num_nodes); 842 for (i = 0; i < num_nodes; i++) { 843 buf->generic[i].parent_teid = parent->info.node_teid; 844 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC; 845 buf->generic[i].data.valid_sections = 846 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 847 ICE_AQC_ELEM_VALID_EIR; 848 buf->generic[i].data.generic = 0; 849 buf->generic[i].data.cir_bw.bw_profile_idx = 850 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 851 buf->generic[i].data.cir_bw.bw_alloc = 852 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 853 buf->generic[i].data.eir_bw.bw_profile_idx = 854 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 855 buf->generic[i].data.eir_bw.bw_alloc = 856 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 857 } 858 859 status = ice_aq_add_sched_elems(hw, 1, buf, buf_size, 860 &num_groups_added, NULL); 861 if (status || num_groups_added != 1) { 862 ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n", 863 hw->adminq.sq_last_status); 864 devm_kfree(ice_hw_to_dev(hw), buf); 865 return ICE_ERR_CFG; 866 } 867 868 *num_nodes_added = num_nodes; 869 /* add nodes to the SW DB */ 870 for (i = 0; i < num_nodes; i++) { 871 status = ice_sched_add_node(pi, layer, &buf->generic[i]); 872 if (status) { 873 ice_debug(hw, ICE_DBG_SCHED, 874 "add nodes in SW DB failed status =%d\n", 875 status); 876 break; 877 } 878 879 teid = le32_to_cpu(buf->generic[i].node_teid); 880 new_node = ice_sched_find_node_by_teid(parent, teid); 881 if (!new_node) { 882 ice_debug(hw, ICE_DBG_SCHED, 883 "Node is missing for teid =%d\n", teid); 884 break; 885 } 886 887 new_node->sibling = NULL; 888 new_node->tc_num = tc_node->tc_num; 889 890 /* add it to previous node sibling pointer */ 891 /* Note: siblings are not linked across branches */ 892 prev = ice_sched_get_first_node(pi, tc_node, layer); 893 if (prev && prev != new_node) { 894 while (prev->sibling) 895 prev = prev->sibling; 896 prev->sibling = new_node; 897 } 898 899 /* initialize the sibling head */ 900 if (!pi->sib_head[tc_node->tc_num][layer]) 901 pi->sib_head[tc_node->tc_num][layer] = new_node; 902 903 if (i == 0) 904 *first_node_teid = teid; 905 } 906 907 devm_kfree(ice_hw_to_dev(hw), buf); 908 return status; 909 } 910 911 /** 912 * ice_sched_add_nodes_to_layer - Add nodes to a given layer 913 * @pi: port information structure 914 * @tc_node: pointer to TC node 915 * @parent: pointer to parent node 916 * @layer: layer number to add nodes 917 * @num_nodes: number of nodes to be added 918 * @first_node_teid: pointer to the first node TEID 919 * @num_nodes_added: pointer to number of nodes added 920 * 921 * This function add nodes to a given layer. 922 */ 923 static enum ice_status 924 ice_sched_add_nodes_to_layer(struct ice_port_info *pi, 925 struct ice_sched_node *tc_node, 926 struct ice_sched_node *parent, u8 layer, 927 u16 num_nodes, u32 *first_node_teid, 928 u16 *num_nodes_added) 929 { 930 u32 *first_teid_ptr = first_node_teid; 931 u16 new_num_nodes, max_child_nodes; 932 enum ice_status status = 0; 933 struct ice_hw *hw = pi->hw; 934 u16 num_added = 0; 935 u32 temp; 936 937 *num_nodes_added = 0; 938 939 if (!num_nodes) 940 return status; 941 942 if (!parent || layer < hw->sw_entry_point_layer) 943 return ICE_ERR_PARAM; 944 945 /* max children per node per layer */ 946 max_child_nodes = hw->max_children[parent->tx_sched_layer]; 947 948 /* current number of children + required nodes exceed max children ? */ 949 if ((parent->num_children + num_nodes) > max_child_nodes) { 950 /* Fail if the parent is a TC node */ 951 if (parent == tc_node) 952 return ICE_ERR_CFG; 953 954 /* utilize all the spaces if the parent is not full */ 955 if (parent->num_children < max_child_nodes) { 956 new_num_nodes = max_child_nodes - parent->num_children; 957 /* this recursion is intentional, and wouldn't 958 * go more than 2 calls 959 */ 960 status = ice_sched_add_nodes_to_layer(pi, tc_node, 961 parent, layer, 962 new_num_nodes, 963 first_node_teid, 964 &num_added); 965 if (status) 966 return status; 967 968 *num_nodes_added += num_added; 969 } 970 /* Don't modify the first node TEID memory if the first node was 971 * added already in the above call. Instead send some temp 972 * memory for all other recursive calls. 973 */ 974 if (num_added) 975 first_teid_ptr = &temp; 976 977 new_num_nodes = num_nodes - num_added; 978 979 /* This parent is full, try the next sibling */ 980 parent = parent->sibling; 981 982 /* this recursion is intentional, for 1024 queues 983 * per VSI, it goes max of 16 iterations. 984 * 1024 / 8 = 128 layer 8 nodes 985 * 128 /8 = 16 (add 8 nodes per iteration) 986 */ 987 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, 988 layer, new_num_nodes, 989 first_teid_ptr, 990 &num_added); 991 *num_nodes_added += num_added; 992 return status; 993 } 994 995 status = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, 996 num_nodes_added, first_node_teid); 997 return status; 998 } 999 1000 /** 1001 * ice_sched_get_qgrp_layer - get the current queue group layer number 1002 * @hw: pointer to the HW struct 1003 * 1004 * This function returns the current queue group layer number 1005 */ 1006 static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw) 1007 { 1008 /* It's always total layers - 1, the array is 0 relative so -2 */ 1009 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; 1010 } 1011 1012 /** 1013 * ice_sched_get_vsi_layer - get the current VSI layer number 1014 * @hw: pointer to the HW struct 1015 * 1016 * This function returns the current VSI layer number 1017 */ 1018 static u8 ice_sched_get_vsi_layer(struct ice_hw *hw) 1019 { 1020 /* Num Layers VSI layer 1021 * 9 6 1022 * 7 4 1023 * 5 or less sw_entry_point_layer 1024 */ 1025 /* calculate the VSI layer based on number of layers. */ 1026 if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) { 1027 u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; 1028 1029 if (layer > hw->sw_entry_point_layer) 1030 return layer; 1031 } 1032 return hw->sw_entry_point_layer; 1033 } 1034 1035 /** 1036 * ice_rm_dflt_leaf_node - remove the default leaf node in the tree 1037 * @pi: port information structure 1038 * 1039 * This function removes the leaf node that was created by the FW 1040 * during initialization 1041 */ 1042 static void ice_rm_dflt_leaf_node(struct ice_port_info *pi) 1043 { 1044 struct ice_sched_node *node; 1045 1046 node = pi->root; 1047 while (node) { 1048 if (!node->num_children) 1049 break; 1050 node = node->children[0]; 1051 } 1052 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) { 1053 u32 teid = le32_to_cpu(node->info.node_teid); 1054 enum ice_status status; 1055 1056 /* remove the default leaf node */ 1057 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid); 1058 if (!status) 1059 ice_free_sched_node(pi, node); 1060 } 1061 } 1062 1063 /** 1064 * ice_sched_rm_dflt_nodes - free the default nodes in the tree 1065 * @pi: port information structure 1066 * 1067 * This function frees all the nodes except root and TC that were created by 1068 * the FW during initialization 1069 */ 1070 static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi) 1071 { 1072 struct ice_sched_node *node; 1073 1074 ice_rm_dflt_leaf_node(pi); 1075 1076 /* remove the default nodes except TC and root nodes */ 1077 node = pi->root; 1078 while (node) { 1079 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer && 1080 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 1081 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) { 1082 ice_free_sched_node(pi, node); 1083 break; 1084 } 1085 1086 if (!node->num_children) 1087 break; 1088 node = node->children[0]; 1089 } 1090 } 1091 1092 /** 1093 * ice_sched_init_port - Initialize scheduler by querying information from FW 1094 * @pi: port info structure for the tree to cleanup 1095 * 1096 * This function is the initial call to find the total number of Tx scheduler 1097 * resources, default topology created by firmware and storing the information 1098 * in SW DB. 1099 */ 1100 enum ice_status ice_sched_init_port(struct ice_port_info *pi) 1101 { 1102 struct ice_aqc_get_topo_elem *buf; 1103 enum ice_status status; 1104 struct ice_hw *hw; 1105 u8 num_branches; 1106 u16 num_elems; 1107 u8 i, j; 1108 1109 if (!pi) 1110 return ICE_ERR_PARAM; 1111 hw = pi->hw; 1112 1113 /* Query the Default Topology from FW */ 1114 buf = devm_kzalloc(ice_hw_to_dev(hw), ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 1115 if (!buf) 1116 return ICE_ERR_NO_MEMORY; 1117 1118 /* Query default scheduling tree topology */ 1119 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN, 1120 &num_branches, NULL); 1121 if (status) 1122 goto err_init_port; 1123 1124 /* num_branches should be between 1-8 */ 1125 if (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) { 1126 ice_debug(hw, ICE_DBG_SCHED, "num_branches unexpected %d\n", 1127 num_branches); 1128 status = ICE_ERR_PARAM; 1129 goto err_init_port; 1130 } 1131 1132 /* get the number of elements on the default/first branch */ 1133 num_elems = le16_to_cpu(buf[0].hdr.num_elems); 1134 1135 /* num_elems should always be between 1-9 */ 1136 if (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) { 1137 ice_debug(hw, ICE_DBG_SCHED, "num_elems unexpected %d\n", 1138 num_elems); 1139 status = ICE_ERR_PARAM; 1140 goto err_init_port; 1141 } 1142 1143 /* If the last node is a leaf node then the index of the queue group 1144 * layer is two less than the number of elements. 1145 */ 1146 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type == 1147 ICE_AQC_ELEM_TYPE_LEAF) 1148 pi->last_node_teid = 1149 le32_to_cpu(buf[0].generic[num_elems - 2].node_teid); 1150 else 1151 pi->last_node_teid = 1152 le32_to_cpu(buf[0].generic[num_elems - 1].node_teid); 1153 1154 /* Insert the Tx Sched root node */ 1155 status = ice_sched_add_root_node(pi, &buf[0].generic[0]); 1156 if (status) 1157 goto err_init_port; 1158 1159 /* Parse the default tree and cache the information */ 1160 for (i = 0; i < num_branches; i++) { 1161 num_elems = le16_to_cpu(buf[i].hdr.num_elems); 1162 1163 /* Skip root element as already inserted */ 1164 for (j = 1; j < num_elems; j++) { 1165 /* update the sw entry point */ 1166 if (buf[0].generic[j].data.elem_type == 1167 ICE_AQC_ELEM_TYPE_ENTRY_POINT) 1168 hw->sw_entry_point_layer = j; 1169 1170 status = ice_sched_add_node(pi, j, &buf[i].generic[j]); 1171 if (status) 1172 goto err_init_port; 1173 } 1174 } 1175 1176 /* Remove the default nodes. */ 1177 if (pi->root) 1178 ice_sched_rm_dflt_nodes(pi); 1179 1180 /* initialize the port for handling the scheduler tree */ 1181 pi->port_state = ICE_SCHED_PORT_STATE_READY; 1182 mutex_init(&pi->sched_lock); 1183 for (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++) 1184 INIT_LIST_HEAD(&pi->rl_prof_list[i]); 1185 1186 err_init_port: 1187 if (status && pi->root) { 1188 ice_free_sched_node(pi, pi->root); 1189 pi->root = NULL; 1190 } 1191 1192 devm_kfree(ice_hw_to_dev(hw), buf); 1193 return status; 1194 } 1195 1196 /** 1197 * ice_sched_query_res_alloc - query the FW for num of logical sched layers 1198 * @hw: pointer to the HW struct 1199 * 1200 * query FW for allocated scheduler resources and store in HW struct 1201 */ 1202 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) 1203 { 1204 struct ice_aqc_query_txsched_res_resp *buf; 1205 enum ice_status status = 0; 1206 __le16 max_sibl; 1207 u16 i; 1208 1209 if (hw->layer_info) 1210 return status; 1211 1212 buf = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*buf), GFP_KERNEL); 1213 if (!buf) 1214 return ICE_ERR_NO_MEMORY; 1215 1216 status = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL); 1217 if (status) 1218 goto sched_query_out; 1219 1220 hw->num_tx_sched_layers = le16_to_cpu(buf->sched_props.logical_levels); 1221 hw->num_tx_sched_phys_layers = 1222 le16_to_cpu(buf->sched_props.phys_levels); 1223 hw->flattened_layers = buf->sched_props.flattening_bitmap; 1224 hw->max_cgds = buf->sched_props.max_pf_cgds; 1225 1226 /* max sibling group size of current layer refers to the max children 1227 * of the below layer node. 1228 * layer 1 node max children will be layer 2 max sibling group size 1229 * layer 2 node max children will be layer 3 max sibling group size 1230 * and so on. This array will be populated from root (index 0) to 1231 * qgroup layer 7. Leaf node has no children. 1232 */ 1233 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) { 1234 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz; 1235 hw->max_children[i] = le16_to_cpu(max_sibl); 1236 } 1237 1238 hw->layer_info = devm_kmemdup(ice_hw_to_dev(hw), buf->layer_props, 1239 (hw->num_tx_sched_layers * 1240 sizeof(*hw->layer_info)), 1241 GFP_KERNEL); 1242 if (!hw->layer_info) { 1243 status = ICE_ERR_NO_MEMORY; 1244 goto sched_query_out; 1245 } 1246 1247 sched_query_out: 1248 devm_kfree(ice_hw_to_dev(hw), buf); 1249 return status; 1250 } 1251 1252 /** 1253 * ice_sched_find_node_in_subtree - Find node in part of base node subtree 1254 * @hw: pointer to the HW struct 1255 * @base: pointer to the base node 1256 * @node: pointer to the node to search 1257 * 1258 * This function checks whether a given node is part of the base node 1259 * subtree or not 1260 */ 1261 static bool 1262 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 1263 struct ice_sched_node *node) 1264 { 1265 u8 i; 1266 1267 for (i = 0; i < base->num_children; i++) { 1268 struct ice_sched_node *child = base->children[i]; 1269 1270 if (node == child) 1271 return true; 1272 1273 if (child->tx_sched_layer > node->tx_sched_layer) 1274 return false; 1275 1276 /* this recursion is intentional, and wouldn't 1277 * go more than 8 calls 1278 */ 1279 if (ice_sched_find_node_in_subtree(hw, child, node)) 1280 return true; 1281 } 1282 return false; 1283 } 1284 1285 /** 1286 * ice_sched_get_free_qparent - Get a free LAN or RDMA queue group node 1287 * @pi: port information structure 1288 * @vsi_handle: software VSI handle 1289 * @tc: branch number 1290 * @owner: LAN or RDMA 1291 * 1292 * This function retrieves a free LAN or RDMA queue group node 1293 */ 1294 struct ice_sched_node * 1295 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 1296 u8 owner) 1297 { 1298 struct ice_sched_node *vsi_node, *qgrp_node = NULL; 1299 struct ice_vsi_ctx *vsi_ctx; 1300 u16 max_children; 1301 u8 qgrp_layer; 1302 1303 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw); 1304 max_children = pi->hw->max_children[qgrp_layer]; 1305 1306 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 1307 if (!vsi_ctx) 1308 return NULL; 1309 vsi_node = vsi_ctx->sched.vsi_node[tc]; 1310 /* validate invalid VSI ID */ 1311 if (!vsi_node) 1312 goto lan_q_exit; 1313 1314 /* get the first queue group node from VSI sub-tree */ 1315 qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer); 1316 while (qgrp_node) { 1317 /* make sure the qgroup node is part of the VSI subtree */ 1318 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1319 if (qgrp_node->num_children < max_children && 1320 qgrp_node->owner == owner) 1321 break; 1322 qgrp_node = qgrp_node->sibling; 1323 } 1324 1325 lan_q_exit: 1326 return qgrp_node; 1327 } 1328 1329 /** 1330 * ice_sched_get_vsi_node - Get a VSI node based on VSI ID 1331 * @hw: pointer to the HW struct 1332 * @tc_node: pointer to the TC node 1333 * @vsi_handle: software VSI handle 1334 * 1335 * This function retrieves a VSI node for a given VSI ID from a given 1336 * TC branch 1337 */ 1338 static struct ice_sched_node * 1339 ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node, 1340 u16 vsi_handle) 1341 { 1342 struct ice_sched_node *node; 1343 u8 vsi_layer; 1344 1345 vsi_layer = ice_sched_get_vsi_layer(hw); 1346 node = ice_sched_get_first_node(hw->port_info, tc_node, vsi_layer); 1347 1348 /* Check whether it already exists */ 1349 while (node) { 1350 if (node->vsi_handle == vsi_handle) 1351 return node; 1352 node = node->sibling; 1353 } 1354 1355 return node; 1356 } 1357 1358 /** 1359 * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes 1360 * @hw: pointer to the HW struct 1361 * @num_qs: number of queues 1362 * @num_nodes: num nodes array 1363 * 1364 * This function calculates the number of VSI child nodes based on the 1365 * number of queues. 1366 */ 1367 static void 1368 ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes) 1369 { 1370 u16 num = num_qs; 1371 u8 i, qgl, vsil; 1372 1373 qgl = ice_sched_get_qgrp_layer(hw); 1374 vsil = ice_sched_get_vsi_layer(hw); 1375 1376 /* calculate num nodes from queue group to VSI layer */ 1377 for (i = qgl; i > vsil; i--) { 1378 /* round to the next integer if there is a remainder */ 1379 num = DIV_ROUND_UP(num, hw->max_children[i]); 1380 1381 /* need at least one node */ 1382 num_nodes[i] = num ? num : 1; 1383 } 1384 } 1385 1386 /** 1387 * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree 1388 * @pi: port information structure 1389 * @vsi_handle: software VSI handle 1390 * @tc_node: pointer to the TC node 1391 * @num_nodes: pointer to the num nodes that needs to be added per layer 1392 * @owner: node owner (LAN or RDMA) 1393 * 1394 * This function adds the VSI child nodes to tree. It gets called for 1395 * LAN and RDMA separately. 1396 */ 1397 static enum ice_status 1398 ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1399 struct ice_sched_node *tc_node, u16 *num_nodes, 1400 u8 owner) 1401 { 1402 struct ice_sched_node *parent, *node; 1403 struct ice_hw *hw = pi->hw; 1404 enum ice_status status; 1405 u32 first_node_teid; 1406 u16 num_added = 0; 1407 u8 i, qgl, vsil; 1408 1409 qgl = ice_sched_get_qgrp_layer(hw); 1410 vsil = ice_sched_get_vsi_layer(hw); 1411 parent = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); 1412 for (i = vsil + 1; i <= qgl; i++) { 1413 if (!parent) 1414 return ICE_ERR_CFG; 1415 1416 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 1417 num_nodes[i], 1418 &first_node_teid, 1419 &num_added); 1420 if (status || num_nodes[i] != num_added) 1421 return ICE_ERR_CFG; 1422 1423 /* The newly added node can be a new parent for the next 1424 * layer nodes 1425 */ 1426 if (num_added) { 1427 parent = ice_sched_find_node_by_teid(tc_node, 1428 first_node_teid); 1429 node = parent; 1430 while (node) { 1431 node->owner = owner; 1432 node = node->sibling; 1433 } 1434 } else { 1435 parent = parent->children[0]; 1436 } 1437 } 1438 1439 return 0; 1440 } 1441 1442 /** 1443 * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes 1444 * @hw: pointer to the HW struct 1445 * @tc_node: pointer to TC node 1446 * @num_nodes: pointer to num nodes array 1447 * 1448 * This function calculates the number of supported nodes needed to add this 1449 * VSI into Tx tree including the VSI, parent and intermediate nodes in below 1450 * layers 1451 */ 1452 static void 1453 ice_sched_calc_vsi_support_nodes(struct ice_hw *hw, 1454 struct ice_sched_node *tc_node, u16 *num_nodes) 1455 { 1456 struct ice_sched_node *node; 1457 u8 vsil; 1458 int i; 1459 1460 vsil = ice_sched_get_vsi_layer(hw); 1461 for (i = vsil; i >= hw->sw_entry_point_layer; i--) 1462 /* Add intermediate nodes if TC has no children and 1463 * need at least one node for VSI 1464 */ 1465 if (!tc_node->num_children || i == vsil) { 1466 num_nodes[i]++; 1467 } else { 1468 /* If intermediate nodes are reached max children 1469 * then add a new one. 1470 */ 1471 node = ice_sched_get_first_node(hw->port_info, tc_node, 1472 (u8)i); 1473 /* scan all the siblings */ 1474 while (node) { 1475 if (node->num_children < hw->max_children[i]) 1476 break; 1477 node = node->sibling; 1478 } 1479 1480 /* tree has one intermediate node to add this new VSI. 1481 * So no need to calculate supported nodes for below 1482 * layers. 1483 */ 1484 if (node) 1485 break; 1486 /* all the nodes are full, allocate a new one */ 1487 num_nodes[i]++; 1488 } 1489 } 1490 1491 /** 1492 * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree 1493 * @pi: port information structure 1494 * @vsi_handle: software VSI handle 1495 * @tc_node: pointer to TC node 1496 * @num_nodes: pointer to num nodes array 1497 * 1498 * This function adds the VSI supported nodes into Tx tree including the 1499 * VSI, its parent and intermediate nodes in below layers 1500 */ 1501 static enum ice_status 1502 ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle, 1503 struct ice_sched_node *tc_node, u16 *num_nodes) 1504 { 1505 struct ice_sched_node *parent = tc_node; 1506 enum ice_status status; 1507 u32 first_node_teid; 1508 u16 num_added = 0; 1509 u8 i, vsil; 1510 1511 if (!pi) 1512 return ICE_ERR_PARAM; 1513 1514 vsil = ice_sched_get_vsi_layer(pi->hw); 1515 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) { 1516 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, 1517 i, num_nodes[i], 1518 &first_node_teid, 1519 &num_added); 1520 if (status || num_nodes[i] != num_added) 1521 return ICE_ERR_CFG; 1522 1523 /* The newly added node can be a new parent for the next 1524 * layer nodes 1525 */ 1526 if (num_added) 1527 parent = ice_sched_find_node_by_teid(tc_node, 1528 first_node_teid); 1529 else 1530 parent = parent->children[0]; 1531 1532 if (!parent) 1533 return ICE_ERR_CFG; 1534 1535 if (i == vsil) 1536 parent->vsi_handle = vsi_handle; 1537 } 1538 1539 return 0; 1540 } 1541 1542 /** 1543 * ice_sched_add_vsi_to_topo - add a new VSI into tree 1544 * @pi: port information structure 1545 * @vsi_handle: software VSI handle 1546 * @tc: TC number 1547 * 1548 * This function adds a new VSI into scheduler tree 1549 */ 1550 static enum ice_status 1551 ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc) 1552 { 1553 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1554 struct ice_sched_node *tc_node; 1555 struct ice_hw *hw = pi->hw; 1556 1557 tc_node = ice_sched_get_tc_node(pi, tc); 1558 if (!tc_node) 1559 return ICE_ERR_PARAM; 1560 1561 /* calculate number of supported nodes needed for this VSI */ 1562 ice_sched_calc_vsi_support_nodes(hw, tc_node, num_nodes); 1563 1564 /* add VSI supported nodes to TC subtree */ 1565 return ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node, 1566 num_nodes); 1567 } 1568 1569 /** 1570 * ice_sched_update_vsi_child_nodes - update VSI child nodes 1571 * @pi: port information structure 1572 * @vsi_handle: software VSI handle 1573 * @tc: TC number 1574 * @new_numqs: new number of max queues 1575 * @owner: owner of this subtree 1576 * 1577 * This function updates the VSI child nodes based on the number of queues 1578 */ 1579 static enum ice_status 1580 ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1581 u8 tc, u16 new_numqs, u8 owner) 1582 { 1583 u16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1584 struct ice_sched_node *vsi_node; 1585 struct ice_sched_node *tc_node; 1586 struct ice_vsi_ctx *vsi_ctx; 1587 enum ice_status status = 0; 1588 struct ice_hw *hw = pi->hw; 1589 u16 prev_numqs; 1590 1591 tc_node = ice_sched_get_tc_node(pi, tc); 1592 if (!tc_node) 1593 return ICE_ERR_CFG; 1594 1595 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); 1596 if (!vsi_node) 1597 return ICE_ERR_CFG; 1598 1599 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1600 if (!vsi_ctx) 1601 return ICE_ERR_PARAM; 1602 1603 prev_numqs = vsi_ctx->sched.max_lanq[tc]; 1604 /* num queues are not changed or less than the previous number */ 1605 if (new_numqs <= prev_numqs) 1606 return status; 1607 status = ice_alloc_lan_q_ctx(hw, vsi_handle, tc, new_numqs); 1608 if (status) 1609 return status; 1610 1611 if (new_numqs) 1612 ice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes); 1613 /* Keep the max number of queue configuration all the time. Update the 1614 * tree only if number of queues > previous number of queues. This may 1615 * leave some extra nodes in the tree if number of queues < previous 1616 * number but that wouldn't harm anything. Removing those extra nodes 1617 * may complicate the code if those nodes are part of SRL or 1618 * individually rate limited. 1619 */ 1620 status = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node, 1621 new_num_nodes, owner); 1622 if (status) 1623 return status; 1624 vsi_ctx->sched.max_lanq[tc] = new_numqs; 1625 1626 return 0; 1627 } 1628 1629 /** 1630 * ice_sched_cfg_vsi - configure the new/existing VSI 1631 * @pi: port information structure 1632 * @vsi_handle: software VSI handle 1633 * @tc: TC number 1634 * @maxqs: max number of queues 1635 * @owner: LAN or RDMA 1636 * @enable: TC enabled or disabled 1637 * 1638 * This function adds/updates VSI nodes based on the number of queues. If TC is 1639 * enabled and VSI is in suspended state then resume the VSI back. If TC is 1640 * disabled then suspend the VSI if it is not already. 1641 */ 1642 enum ice_status 1643 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 1644 u8 owner, bool enable) 1645 { 1646 struct ice_sched_node *vsi_node, *tc_node; 1647 struct ice_vsi_ctx *vsi_ctx; 1648 enum ice_status status = 0; 1649 struct ice_hw *hw = pi->hw; 1650 1651 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle); 1652 tc_node = ice_sched_get_tc_node(pi, tc); 1653 if (!tc_node) 1654 return ICE_ERR_PARAM; 1655 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1656 if (!vsi_ctx) 1657 return ICE_ERR_PARAM; 1658 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); 1659 1660 /* suspend the VSI if TC is not enabled */ 1661 if (!enable) { 1662 if (vsi_node && vsi_node->in_use) { 1663 u32 teid = le32_to_cpu(vsi_node->info.node_teid); 1664 1665 status = ice_sched_suspend_resume_elems(hw, 1, &teid, 1666 true); 1667 if (!status) 1668 vsi_node->in_use = false; 1669 } 1670 return status; 1671 } 1672 1673 /* TC is enabled, if it is a new VSI then add it to the tree */ 1674 if (!vsi_node) { 1675 status = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc); 1676 if (status) 1677 return status; 1678 1679 vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); 1680 if (!vsi_node) 1681 return ICE_ERR_CFG; 1682 1683 vsi_ctx->sched.vsi_node[tc] = vsi_node; 1684 vsi_node->in_use = true; 1685 /* invalidate the max queues whenever VSI gets added first time 1686 * into the scheduler tree (boot or after reset). We need to 1687 * recreate the child nodes all the time in these cases. 1688 */ 1689 vsi_ctx->sched.max_lanq[tc] = 0; 1690 } 1691 1692 /* update the VSI child nodes */ 1693 status = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs, 1694 owner); 1695 if (status) 1696 return status; 1697 1698 /* TC is enabled, resume the VSI if it is in the suspend state */ 1699 if (!vsi_node->in_use) { 1700 u32 teid = le32_to_cpu(vsi_node->info.node_teid); 1701 1702 status = ice_sched_suspend_resume_elems(hw, 1, &teid, false); 1703 if (!status) 1704 vsi_node->in_use = true; 1705 } 1706 1707 return status; 1708 } 1709 1710 /** 1711 * ice_sched_rm_agg_vsi_entry - remove aggregator related VSI info entry 1712 * @pi: port information structure 1713 * @vsi_handle: software VSI handle 1714 * 1715 * This function removes single aggregator VSI info entry from 1716 * aggregator list. 1717 */ 1718 static void 1719 ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle) 1720 { 1721 struct ice_sched_agg_info *agg_info; 1722 struct ice_sched_agg_info *atmp; 1723 1724 list_for_each_entry_safe(agg_info, atmp, &pi->hw->agg_list, 1725 list_entry) { 1726 struct ice_sched_agg_vsi_info *agg_vsi_info; 1727 struct ice_sched_agg_vsi_info *vtmp; 1728 1729 list_for_each_entry_safe(agg_vsi_info, vtmp, 1730 &agg_info->agg_vsi_list, list_entry) 1731 if (agg_vsi_info->vsi_handle == vsi_handle) { 1732 list_del(&agg_vsi_info->list_entry); 1733 devm_kfree(ice_hw_to_dev(pi->hw), 1734 agg_vsi_info); 1735 return; 1736 } 1737 } 1738 } 1739 1740 /** 1741 * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree 1742 * @node: pointer to the sub-tree node 1743 * 1744 * This function checks for a leaf node presence in a given sub-tree node. 1745 */ 1746 static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node) 1747 { 1748 u8 i; 1749 1750 for (i = 0; i < node->num_children; i++) 1751 if (ice_sched_is_leaf_node_present(node->children[i])) 1752 return true; 1753 /* check for a leaf node */ 1754 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF); 1755 } 1756 1757 /** 1758 * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes 1759 * @pi: port information structure 1760 * @vsi_handle: software VSI handle 1761 * @owner: LAN or RDMA 1762 * 1763 * This function removes the VSI and its LAN or RDMA children nodes from the 1764 * scheduler tree. 1765 */ 1766 static enum ice_status 1767 ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner) 1768 { 1769 enum ice_status status = ICE_ERR_PARAM; 1770 struct ice_vsi_ctx *vsi_ctx; 1771 u8 i; 1772 1773 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle); 1774 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 1775 return status; 1776 mutex_lock(&pi->sched_lock); 1777 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 1778 if (!vsi_ctx) 1779 goto exit_sched_rm_vsi_cfg; 1780 1781 ice_for_each_traffic_class(i) { 1782 struct ice_sched_node *vsi_node, *tc_node; 1783 u8 j = 0; 1784 1785 tc_node = ice_sched_get_tc_node(pi, i); 1786 if (!tc_node) 1787 continue; 1788 1789 vsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle); 1790 if (!vsi_node) 1791 continue; 1792 1793 if (ice_sched_is_leaf_node_present(vsi_node)) { 1794 ice_debug(pi->hw, ICE_DBG_SCHED, 1795 "VSI has leaf nodes in TC %d\n", i); 1796 status = ICE_ERR_IN_USE; 1797 goto exit_sched_rm_vsi_cfg; 1798 } 1799 while (j < vsi_node->num_children) { 1800 if (vsi_node->children[j]->owner == owner) { 1801 ice_free_sched_node(pi, vsi_node->children[j]); 1802 1803 /* reset the counter again since the num 1804 * children will be updated after node removal 1805 */ 1806 j = 0; 1807 } else { 1808 j++; 1809 } 1810 } 1811 /* remove the VSI if it has no children */ 1812 if (!vsi_node->num_children) { 1813 ice_free_sched_node(pi, vsi_node); 1814 vsi_ctx->sched.vsi_node[i] = NULL; 1815 1816 /* clean up aggregator related VSI info if any */ 1817 ice_sched_rm_agg_vsi_info(pi, vsi_handle); 1818 } 1819 if (owner == ICE_SCHED_NODE_OWNER_LAN) 1820 vsi_ctx->sched.max_lanq[i] = 0; 1821 } 1822 status = 0; 1823 1824 exit_sched_rm_vsi_cfg: 1825 mutex_unlock(&pi->sched_lock); 1826 return status; 1827 } 1828 1829 /** 1830 * ice_rm_vsi_lan_cfg - remove VSI and its LAN children nodes 1831 * @pi: port information structure 1832 * @vsi_handle: software VSI handle 1833 * 1834 * This function clears the VSI and its LAN children nodes from scheduler tree 1835 * for all TCs. 1836 */ 1837 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle) 1838 { 1839 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN); 1840 } 1841 1842 /** 1843 * ice_sched_rm_unused_rl_prof - remove unused RL profile 1844 * @pi: port information structure 1845 * 1846 * This function removes unused rate limit profiles from the HW and 1847 * SW DB. The caller needs to hold scheduler lock. 1848 */ 1849 static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi) 1850 { 1851 u16 ln; 1852 1853 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) { 1854 struct ice_aqc_rl_profile_info *rl_prof_elem; 1855 struct ice_aqc_rl_profile_info *rl_prof_tmp; 1856 1857 list_for_each_entry_safe(rl_prof_elem, rl_prof_tmp, 1858 &pi->rl_prof_list[ln], list_entry) { 1859 if (!ice_sched_del_rl_profile(pi->hw, rl_prof_elem)) 1860 ice_debug(pi->hw, ICE_DBG_SCHED, 1861 "Removed rl profile\n"); 1862 } 1863 } 1864 } 1865 1866 /** 1867 * ice_sched_update_elem - update element 1868 * @hw: pointer to the HW struct 1869 * @node: pointer to node 1870 * @info: node info to update 1871 * 1872 * It updates the HW DB, and local SW DB of node. It updates the scheduling 1873 * parameters of node from argument info data buffer (Info->data buf) and 1874 * returns success or error on config sched element failure. The caller 1875 * needs to hold scheduler lock. 1876 */ 1877 static enum ice_status 1878 ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node, 1879 struct ice_aqc_txsched_elem_data *info) 1880 { 1881 struct ice_aqc_conf_elem buf; 1882 enum ice_status status; 1883 u16 elem_cfgd = 0; 1884 u16 num_elems = 1; 1885 1886 buf.generic[0] = *info; 1887 /* Parent TEID is reserved field in this aq call */ 1888 buf.generic[0].parent_teid = 0; 1889 /* Element type is reserved field in this aq call */ 1890 buf.generic[0].data.elem_type = 0; 1891 /* Flags is reserved field in this aq call */ 1892 buf.generic[0].data.flags = 0; 1893 1894 /* Update HW DB */ 1895 /* Configure element node */ 1896 status = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf), 1897 &elem_cfgd, NULL); 1898 if (status || elem_cfgd != num_elems) { 1899 ice_debug(hw, ICE_DBG_SCHED, "Config sched elem error\n"); 1900 return ICE_ERR_CFG; 1901 } 1902 1903 /* Config success case */ 1904 /* Now update local SW DB */ 1905 /* Only copy the data portion of info buffer */ 1906 node->info.data = info->data; 1907 return status; 1908 } 1909 1910 /** 1911 * ice_sched_cfg_node_bw_alloc - configure node BW weight/alloc params 1912 * @hw: pointer to the HW struct 1913 * @node: sched node to configure 1914 * @rl_type: rate limit type CIR, EIR, or shared 1915 * @bw_alloc: BW weight/allocation 1916 * 1917 * This function configures node element's BW allocation. 1918 */ 1919 static enum ice_status 1920 ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node, 1921 enum ice_rl_type rl_type, u8 bw_alloc) 1922 { 1923 struct ice_aqc_txsched_elem_data buf; 1924 struct ice_aqc_txsched_elem *data; 1925 enum ice_status status; 1926 1927 buf = node->info; 1928 data = &buf.data; 1929 if (rl_type == ICE_MIN_BW) { 1930 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 1931 data->cir_bw.bw_alloc = cpu_to_le16(bw_alloc); 1932 } else if (rl_type == ICE_MAX_BW) { 1933 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 1934 data->eir_bw.bw_alloc = cpu_to_le16(bw_alloc); 1935 } else { 1936 return ICE_ERR_PARAM; 1937 } 1938 1939 /* Configure element */ 1940 status = ice_sched_update_elem(hw, node, &buf); 1941 return status; 1942 } 1943 1944 /** 1945 * ice_set_clear_cir_bw - set or clear CIR BW 1946 * @bw_t_info: bandwidth type information structure 1947 * @bw: bandwidth in Kbps - Kilo bits per sec 1948 * 1949 * Save or clear CIR bandwidth (BW) in the passed param bw_t_info. 1950 */ 1951 static void 1952 ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 1953 { 1954 if (bw == ICE_SCHED_DFLT_BW) { 1955 clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 1956 bw_t_info->cir_bw.bw = 0; 1957 } else { 1958 /* Save type of BW information */ 1959 set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 1960 bw_t_info->cir_bw.bw = bw; 1961 } 1962 } 1963 1964 /** 1965 * ice_set_clear_eir_bw - set or clear EIR BW 1966 * @bw_t_info: bandwidth type information structure 1967 * @bw: bandwidth in Kbps - Kilo bits per sec 1968 * 1969 * Save or clear EIR bandwidth (BW) in the passed param bw_t_info. 1970 */ 1971 static void 1972 ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 1973 { 1974 if (bw == ICE_SCHED_DFLT_BW) { 1975 clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 1976 bw_t_info->eir_bw.bw = 0; 1977 } else { 1978 /* EIR BW and Shared BW profiles are mutually exclusive and 1979 * hence only one of them may be set for any given element. 1980 * First clear earlier saved shared BW information. 1981 */ 1982 clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 1983 bw_t_info->shared_bw = 0; 1984 /* save EIR BW information */ 1985 set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 1986 bw_t_info->eir_bw.bw = bw; 1987 } 1988 } 1989 1990 /** 1991 * ice_set_clear_shared_bw - set or clear shared BW 1992 * @bw_t_info: bandwidth type information structure 1993 * @bw: bandwidth in Kbps - Kilo bits per sec 1994 * 1995 * Save or clear shared bandwidth (BW) in the passed param bw_t_info. 1996 */ 1997 static void 1998 ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 1999 { 2000 if (bw == ICE_SCHED_DFLT_BW) { 2001 clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 2002 bw_t_info->shared_bw = 0; 2003 } else { 2004 /* EIR BW and Shared BW profiles are mutually exclusive and 2005 * hence only one of them may be set for any given element. 2006 * First clear earlier saved EIR BW information. 2007 */ 2008 clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 2009 bw_t_info->eir_bw.bw = 0; 2010 /* save shared BW information */ 2011 set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 2012 bw_t_info->shared_bw = bw; 2013 } 2014 } 2015 2016 /** 2017 * ice_sched_calc_wakeup - calculate RL profile wakeup parameter 2018 * @bw: bandwidth in Kbps 2019 * 2020 * This function calculates the wakeup parameter of RL profile. 2021 */ 2022 static u16 ice_sched_calc_wakeup(s32 bw) 2023 { 2024 s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f; 2025 s32 wakeup_f_int; 2026 u16 wakeup = 0; 2027 2028 /* Get the wakeup integer value */ 2029 bytes_per_sec = div64_long(((s64)bw * 1000), BITS_PER_BYTE); 2030 wakeup_int = div64_long(ICE_RL_PROF_FREQUENCY, bytes_per_sec); 2031 if (wakeup_int > 63) { 2032 wakeup = (u16)((1 << 15) | wakeup_int); 2033 } else { 2034 /* Calculate fraction value up to 4 decimals 2035 * Convert Integer value to a constant multiplier 2036 */ 2037 wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int; 2038 wakeup_a = div64_long((s64)ICE_RL_PROF_MULTIPLIER * 2039 ICE_RL_PROF_FREQUENCY, 2040 bytes_per_sec); 2041 2042 /* Get Fraction value */ 2043 wakeup_f = wakeup_a - wakeup_b; 2044 2045 /* Round up the Fractional value via Ceil(Fractional value) */ 2046 if (wakeup_f > div64_long(ICE_RL_PROF_MULTIPLIER, 2)) 2047 wakeup_f += 1; 2048 2049 wakeup_f_int = (s32)div64_long(wakeup_f * ICE_RL_PROF_FRACTION, 2050 ICE_RL_PROF_MULTIPLIER); 2051 wakeup |= (u16)(wakeup_int << 9); 2052 wakeup |= (u16)(0x1ff & wakeup_f_int); 2053 } 2054 2055 return wakeup; 2056 } 2057 2058 /** 2059 * ice_sched_bw_to_rl_profile - convert BW to profile parameters 2060 * @bw: bandwidth in Kbps 2061 * @profile: profile parameters to return 2062 * 2063 * This function converts the BW to profile structure format. 2064 */ 2065 static enum ice_status 2066 ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile) 2067 { 2068 enum ice_status status = ICE_ERR_PARAM; 2069 s64 bytes_per_sec, ts_rate, mv_tmp; 2070 bool found = false; 2071 s32 encode = 0; 2072 s64 mv = 0; 2073 s32 i; 2074 2075 /* Bw settings range is from 0.5Mb/sec to 100Gb/sec */ 2076 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW) 2077 return status; 2078 2079 /* Bytes per second from Kbps */ 2080 bytes_per_sec = div64_long(((s64)bw * 1000), BITS_PER_BYTE); 2081 2082 /* encode is 6 bits but really useful are 5 bits */ 2083 for (i = 0; i < 64; i++) { 2084 u64 pow_result = BIT_ULL(i); 2085 2086 ts_rate = div64_long((s64)ICE_RL_PROF_FREQUENCY, 2087 pow_result * ICE_RL_PROF_TS_MULTIPLIER); 2088 if (ts_rate <= 0) 2089 continue; 2090 2091 /* Multiplier value */ 2092 mv_tmp = div64_long(bytes_per_sec * ICE_RL_PROF_MULTIPLIER, 2093 ts_rate); 2094 2095 /* Round to the nearest ICE_RL_PROF_MULTIPLIER */ 2096 mv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER); 2097 2098 /* First multiplier value greater than the given 2099 * accuracy bytes 2100 */ 2101 if (mv > ICE_RL_PROF_ACCURACY_BYTES) { 2102 encode = i; 2103 found = true; 2104 break; 2105 } 2106 } 2107 if (found) { 2108 u16 wm; 2109 2110 wm = ice_sched_calc_wakeup(bw); 2111 profile->rl_multiply = cpu_to_le16(mv); 2112 profile->wake_up_calc = cpu_to_le16(wm); 2113 profile->rl_encode = cpu_to_le16(encode); 2114 status = 0; 2115 } else { 2116 status = ICE_ERR_DOES_NOT_EXIST; 2117 } 2118 2119 return status; 2120 } 2121 2122 /** 2123 * ice_sched_add_rl_profile - add RL profile 2124 * @pi: port information structure 2125 * @rl_type: type of rate limit BW - min, max, or shared 2126 * @bw: bandwidth in Kbps - Kilo bits per sec 2127 * @layer_num: specifies in which layer to create profile 2128 * 2129 * This function first checks the existing list for corresponding BW 2130 * parameter. If it exists, it returns the associated profile otherwise 2131 * it creates a new rate limit profile for requested BW, and adds it to 2132 * the HW DB and local list. It returns the new profile or null on error. 2133 * The caller needs to hold the scheduler lock. 2134 */ 2135 static struct ice_aqc_rl_profile_info * 2136 ice_sched_add_rl_profile(struct ice_port_info *pi, 2137 enum ice_rl_type rl_type, u32 bw, u8 layer_num) 2138 { 2139 struct ice_aqc_rl_profile_generic_elem *buf; 2140 struct ice_aqc_rl_profile_info *rl_prof_elem; 2141 u16 profiles_added = 0, num_profiles = 1; 2142 enum ice_status status; 2143 struct ice_hw *hw; 2144 u8 profile_type; 2145 2146 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 2147 return NULL; 2148 switch (rl_type) { 2149 case ICE_MIN_BW: 2150 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 2151 break; 2152 case ICE_MAX_BW: 2153 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 2154 break; 2155 case ICE_SHARED_BW: 2156 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 2157 break; 2158 default: 2159 return NULL; 2160 } 2161 2162 if (!pi) 2163 return NULL; 2164 hw = pi->hw; 2165 list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num], 2166 list_entry) 2167 if (rl_prof_elem->profile.flags == profile_type && 2168 rl_prof_elem->bw == bw) 2169 /* Return existing profile ID info */ 2170 return rl_prof_elem; 2171 2172 /* Create new profile ID */ 2173 rl_prof_elem = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*rl_prof_elem), 2174 GFP_KERNEL); 2175 2176 if (!rl_prof_elem) 2177 return NULL; 2178 2179 status = ice_sched_bw_to_rl_profile(bw, &rl_prof_elem->profile); 2180 if (status) 2181 goto exit_add_rl_prof; 2182 2183 rl_prof_elem->bw = bw; 2184 /* layer_num is zero relative, and fw expects level from 1 to 9 */ 2185 rl_prof_elem->profile.level = layer_num + 1; 2186 rl_prof_elem->profile.flags = profile_type; 2187 rl_prof_elem->profile.max_burst_size = cpu_to_le16(hw->max_burst_size); 2188 2189 /* Create new entry in HW DB */ 2190 buf = (struct ice_aqc_rl_profile_generic_elem *) 2191 &rl_prof_elem->profile; 2192 status = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf), 2193 &profiles_added, NULL); 2194 if (status || profiles_added != num_profiles) 2195 goto exit_add_rl_prof; 2196 2197 /* Good entry - add in the list */ 2198 rl_prof_elem->prof_id_ref = 0; 2199 list_add(&rl_prof_elem->list_entry, &pi->rl_prof_list[layer_num]); 2200 return rl_prof_elem; 2201 2202 exit_add_rl_prof: 2203 devm_kfree(ice_hw_to_dev(hw), rl_prof_elem); 2204 return NULL; 2205 } 2206 2207 /** 2208 * ice_sched_cfg_node_bw_lmt - configure node sched params 2209 * @hw: pointer to the HW struct 2210 * @node: sched node to configure 2211 * @rl_type: rate limit type CIR, EIR, or shared 2212 * @rl_prof_id: rate limit profile ID 2213 * 2214 * This function configures node element's BW limit. 2215 */ 2216 static enum ice_status 2217 ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node, 2218 enum ice_rl_type rl_type, u16 rl_prof_id) 2219 { 2220 struct ice_aqc_txsched_elem_data buf; 2221 struct ice_aqc_txsched_elem *data; 2222 2223 buf = node->info; 2224 data = &buf.data; 2225 switch (rl_type) { 2226 case ICE_MIN_BW: 2227 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 2228 data->cir_bw.bw_profile_idx = cpu_to_le16(rl_prof_id); 2229 break; 2230 case ICE_MAX_BW: 2231 /* EIR BW and Shared BW profiles are mutually exclusive and 2232 * hence only one of them may be set for any given element 2233 */ 2234 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED) 2235 return ICE_ERR_CFG; 2236 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 2237 data->eir_bw.bw_profile_idx = cpu_to_le16(rl_prof_id); 2238 break; 2239 case ICE_SHARED_BW: 2240 /* Check for removing shared BW */ 2241 if (rl_prof_id == ICE_SCHED_NO_SHARED_RL_PROF_ID) { 2242 /* remove shared profile */ 2243 data->valid_sections &= ~ICE_AQC_ELEM_VALID_SHARED; 2244 data->srl_id = 0; /* clear SRL field */ 2245 2246 /* enable back EIR to default profile */ 2247 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 2248 data->eir_bw.bw_profile_idx = 2249 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 2250 break; 2251 } 2252 /* EIR BW and Shared BW profiles are mutually exclusive and 2253 * hence only one of them may be set for any given element 2254 */ 2255 if ((data->valid_sections & ICE_AQC_ELEM_VALID_EIR) && 2256 (le16_to_cpu(data->eir_bw.bw_profile_idx) != 2257 ICE_SCHED_DFLT_RL_PROF_ID)) 2258 return ICE_ERR_CFG; 2259 /* EIR BW is set to default, disable it */ 2260 data->valid_sections &= ~ICE_AQC_ELEM_VALID_EIR; 2261 /* Okay to enable shared BW now */ 2262 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED; 2263 data->srl_id = cpu_to_le16(rl_prof_id); 2264 break; 2265 default: 2266 /* Unknown rate limit type */ 2267 return ICE_ERR_PARAM; 2268 } 2269 2270 /* Configure element */ 2271 return ice_sched_update_elem(hw, node, &buf); 2272 } 2273 2274 /** 2275 * ice_sched_get_node_rl_prof_id - get node's rate limit profile ID 2276 * @node: sched node 2277 * @rl_type: rate limit type 2278 * 2279 * If existing profile matches, it returns the corresponding rate 2280 * limit profile ID, otherwise it returns an invalid ID as error. 2281 */ 2282 static u16 2283 ice_sched_get_node_rl_prof_id(struct ice_sched_node *node, 2284 enum ice_rl_type rl_type) 2285 { 2286 u16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID; 2287 struct ice_aqc_txsched_elem *data; 2288 2289 data = &node->info.data; 2290 switch (rl_type) { 2291 case ICE_MIN_BW: 2292 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR) 2293 rl_prof_id = le16_to_cpu(data->cir_bw.bw_profile_idx); 2294 break; 2295 case ICE_MAX_BW: 2296 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR) 2297 rl_prof_id = le16_to_cpu(data->eir_bw.bw_profile_idx); 2298 break; 2299 case ICE_SHARED_BW: 2300 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED) 2301 rl_prof_id = le16_to_cpu(data->srl_id); 2302 break; 2303 default: 2304 break; 2305 } 2306 2307 return rl_prof_id; 2308 } 2309 2310 /** 2311 * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer 2312 * @pi: port information structure 2313 * @rl_type: type of rate limit BW - min, max, or shared 2314 * @layer_index: layer index 2315 * 2316 * This function returns requested profile creation layer. 2317 */ 2318 static u8 2319 ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type, 2320 u8 layer_index) 2321 { 2322 struct ice_hw *hw = pi->hw; 2323 2324 if (layer_index >= hw->num_tx_sched_layers) 2325 return ICE_SCHED_INVAL_LAYER_NUM; 2326 switch (rl_type) { 2327 case ICE_MIN_BW: 2328 if (hw->layer_info[layer_index].max_cir_rl_profiles) 2329 return layer_index; 2330 break; 2331 case ICE_MAX_BW: 2332 if (hw->layer_info[layer_index].max_eir_rl_profiles) 2333 return layer_index; 2334 break; 2335 case ICE_SHARED_BW: 2336 /* if current layer doesn't support SRL profile creation 2337 * then try a layer up or down. 2338 */ 2339 if (hw->layer_info[layer_index].max_srl_profiles) 2340 return layer_index; 2341 else if (layer_index < hw->num_tx_sched_layers - 1 && 2342 hw->layer_info[layer_index + 1].max_srl_profiles) 2343 return layer_index + 1; 2344 else if (layer_index > 0 && 2345 hw->layer_info[layer_index - 1].max_srl_profiles) 2346 return layer_index - 1; 2347 break; 2348 default: 2349 break; 2350 } 2351 return ICE_SCHED_INVAL_LAYER_NUM; 2352 } 2353 2354 /** 2355 * ice_sched_get_srl_node - get shared rate limit node 2356 * @node: tree node 2357 * @srl_layer: shared rate limit layer 2358 * 2359 * This function returns SRL node to be used for shared rate limit purpose. 2360 * The caller needs to hold scheduler lock. 2361 */ 2362 static struct ice_sched_node * 2363 ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer) 2364 { 2365 if (srl_layer > node->tx_sched_layer) 2366 return node->children[0]; 2367 else if (srl_layer < node->tx_sched_layer) 2368 /* Node can't be created without a parent. It will always 2369 * have a valid parent except root node. 2370 */ 2371 return node->parent; 2372 else 2373 return node; 2374 } 2375 2376 /** 2377 * ice_sched_rm_rl_profile - remove RL profile ID 2378 * @pi: port information structure 2379 * @layer_num: layer number where profiles are saved 2380 * @profile_type: profile type like EIR, CIR, or SRL 2381 * @profile_id: profile ID to remove 2382 * 2383 * This function removes rate limit profile from layer 'layer_num' of type 2384 * 'profile_type' and profile ID as 'profile_id'. The caller needs to hold 2385 * scheduler lock. 2386 */ 2387 static enum ice_status 2388 ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type, 2389 u16 profile_id) 2390 { 2391 struct ice_aqc_rl_profile_info *rl_prof_elem; 2392 enum ice_status status = 0; 2393 2394 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 2395 return ICE_ERR_PARAM; 2396 /* Check the existing list for RL profile */ 2397 list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num], 2398 list_entry) 2399 if (rl_prof_elem->profile.flags == profile_type && 2400 le16_to_cpu(rl_prof_elem->profile.profile_id) == 2401 profile_id) { 2402 if (rl_prof_elem->prof_id_ref) 2403 rl_prof_elem->prof_id_ref--; 2404 2405 /* Remove old profile ID from database */ 2406 status = ice_sched_del_rl_profile(pi->hw, rl_prof_elem); 2407 if (status && status != ICE_ERR_IN_USE) 2408 ice_debug(pi->hw, ICE_DBG_SCHED, 2409 "Remove rl profile failed\n"); 2410 break; 2411 } 2412 if (status == ICE_ERR_IN_USE) 2413 status = 0; 2414 return status; 2415 } 2416 2417 /** 2418 * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default 2419 * @pi: port information structure 2420 * @node: pointer to node structure 2421 * @rl_type: rate limit type min, max, or shared 2422 * @layer_num: layer number where RL profiles are saved 2423 * 2424 * This function configures node element's BW rate limit profile ID of 2425 * type CIR, EIR, or SRL to default. This function needs to be called 2426 * with the scheduler lock held. 2427 */ 2428 static enum ice_status 2429 ice_sched_set_node_bw_dflt(struct ice_port_info *pi, 2430 struct ice_sched_node *node, 2431 enum ice_rl_type rl_type, u8 layer_num) 2432 { 2433 enum ice_status status; 2434 struct ice_hw *hw; 2435 u8 profile_type; 2436 u16 rl_prof_id; 2437 u16 old_id; 2438 2439 hw = pi->hw; 2440 switch (rl_type) { 2441 case ICE_MIN_BW: 2442 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 2443 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 2444 break; 2445 case ICE_MAX_BW: 2446 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 2447 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 2448 break; 2449 case ICE_SHARED_BW: 2450 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 2451 /* No SRL is configured for default case */ 2452 rl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID; 2453 break; 2454 default: 2455 return ICE_ERR_PARAM; 2456 } 2457 /* Save existing RL prof ID for later clean up */ 2458 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 2459 /* Configure BW scheduling parameters */ 2460 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 2461 if (status) 2462 return status; 2463 2464 /* Remove stale RL profile ID */ 2465 if (old_id == ICE_SCHED_DFLT_RL_PROF_ID || 2466 old_id == ICE_SCHED_INVAL_PROF_ID) 2467 return 0; 2468 2469 return ice_sched_rm_rl_profile(pi, layer_num, profile_type, old_id); 2470 } 2471 2472 /** 2473 * ice_sched_set_eir_srl_excl - set EIR/SRL exclusiveness 2474 * @pi: port information structure 2475 * @node: pointer to node structure 2476 * @layer_num: layer number where rate limit profiles are saved 2477 * @rl_type: rate limit type min, max, or shared 2478 * @bw: bandwidth value 2479 * 2480 * This function prepares node element's bandwidth to SRL or EIR exclusively. 2481 * EIR BW and Shared BW profiles are mutually exclusive and hence only one of 2482 * them may be set for any given element. This function needs to be called 2483 * with the scheduler lock held. 2484 */ 2485 static enum ice_status 2486 ice_sched_set_eir_srl_excl(struct ice_port_info *pi, 2487 struct ice_sched_node *node, 2488 u8 layer_num, enum ice_rl_type rl_type, u32 bw) 2489 { 2490 if (rl_type == ICE_SHARED_BW) { 2491 /* SRL node passed in this case, it may be different node */ 2492 if (bw == ICE_SCHED_DFLT_BW) 2493 /* SRL being removed, ice_sched_cfg_node_bw_lmt() 2494 * enables EIR to default. EIR is not set in this 2495 * case, so no additional action is required. 2496 */ 2497 return 0; 2498 2499 /* SRL being configured, set EIR to default here. 2500 * ice_sched_cfg_node_bw_lmt() disables EIR when it 2501 * configures SRL 2502 */ 2503 return ice_sched_set_node_bw_dflt(pi, node, ICE_MAX_BW, 2504 layer_num); 2505 } else if (rl_type == ICE_MAX_BW && 2506 node->info.data.valid_sections & ICE_AQC_ELEM_VALID_SHARED) { 2507 /* Remove Shared profile. Set default shared BW call 2508 * removes shared profile for a node. 2509 */ 2510 return ice_sched_set_node_bw_dflt(pi, node, 2511 ICE_SHARED_BW, 2512 layer_num); 2513 } 2514 return 0; 2515 } 2516 2517 /** 2518 * ice_sched_set_node_bw - set node's bandwidth 2519 * @pi: port information structure 2520 * @node: tree node 2521 * @rl_type: rate limit type min, max, or shared 2522 * @bw: bandwidth in Kbps - Kilo bits per sec 2523 * @layer_num: layer number 2524 * 2525 * This function adds new profile corresponding to requested BW, configures 2526 * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile 2527 * ID from local database. The caller needs to hold scheduler lock. 2528 */ 2529 static enum ice_status 2530 ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, 2531 enum ice_rl_type rl_type, u32 bw, u8 layer_num) 2532 { 2533 struct ice_aqc_rl_profile_info *rl_prof_info; 2534 enum ice_status status = ICE_ERR_PARAM; 2535 struct ice_hw *hw = pi->hw; 2536 u16 old_id, rl_prof_id; 2537 2538 rl_prof_info = ice_sched_add_rl_profile(pi, rl_type, bw, layer_num); 2539 if (!rl_prof_info) 2540 return status; 2541 2542 rl_prof_id = le16_to_cpu(rl_prof_info->profile.profile_id); 2543 2544 /* Save existing RL prof ID for later clean up */ 2545 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 2546 /* Configure BW scheduling parameters */ 2547 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 2548 if (status) 2549 return status; 2550 2551 /* New changes has been applied */ 2552 /* Increment the profile ID reference count */ 2553 rl_prof_info->prof_id_ref++; 2554 2555 /* Check for old ID removal */ 2556 if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) || 2557 old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id) 2558 return 0; 2559 2560 return ice_sched_rm_rl_profile(pi, layer_num, 2561 rl_prof_info->profile.flags, 2562 old_id); 2563 } 2564 2565 /** 2566 * ice_sched_set_node_bw_lmt - set node's BW limit 2567 * @pi: port information structure 2568 * @node: tree node 2569 * @rl_type: rate limit type min, max, or shared 2570 * @bw: bandwidth in Kbps - Kilo bits per sec 2571 * 2572 * It updates node's BW limit parameters like BW RL profile ID of type CIR, 2573 * EIR, or SRL. The caller needs to hold scheduler lock. 2574 */ 2575 static enum ice_status 2576 ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, 2577 enum ice_rl_type rl_type, u32 bw) 2578 { 2579 struct ice_sched_node *cfg_node = node; 2580 enum ice_status status; 2581 2582 struct ice_hw *hw; 2583 u8 layer_num; 2584 2585 if (!pi) 2586 return ICE_ERR_PARAM; 2587 hw = pi->hw; 2588 /* Remove unused RL profile IDs from HW and SW DB */ 2589 ice_sched_rm_unused_rl_prof(pi); 2590 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 2591 node->tx_sched_layer); 2592 if (layer_num >= hw->num_tx_sched_layers) 2593 return ICE_ERR_PARAM; 2594 2595 if (rl_type == ICE_SHARED_BW) { 2596 /* SRL node may be different */ 2597 cfg_node = ice_sched_get_srl_node(node, layer_num); 2598 if (!cfg_node) 2599 return ICE_ERR_CFG; 2600 } 2601 /* EIR BW and Shared BW profiles are mutually exclusive and 2602 * hence only one of them may be set for any given element 2603 */ 2604 status = ice_sched_set_eir_srl_excl(pi, cfg_node, layer_num, rl_type, 2605 bw); 2606 if (status) 2607 return status; 2608 if (bw == ICE_SCHED_DFLT_BW) 2609 return ice_sched_set_node_bw_dflt(pi, cfg_node, rl_type, 2610 layer_num); 2611 return ice_sched_set_node_bw(pi, cfg_node, rl_type, bw, layer_num); 2612 } 2613 2614 /** 2615 * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default 2616 * @pi: port information structure 2617 * @node: pointer to node structure 2618 * @rl_type: rate limit type min, max, or shared 2619 * 2620 * This function configures node element's BW rate limit profile ID of 2621 * type CIR, EIR, or SRL to default. This function needs to be called 2622 * with the scheduler lock held. 2623 */ 2624 static enum ice_status 2625 ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi, 2626 struct ice_sched_node *node, 2627 enum ice_rl_type rl_type) 2628 { 2629 return ice_sched_set_node_bw_lmt(pi, node, rl_type, 2630 ICE_SCHED_DFLT_BW); 2631 } 2632 2633 /** 2634 * ice_sched_validate_srl_node - Check node for SRL applicability 2635 * @node: sched node to configure 2636 * @sel_layer: selected SRL layer 2637 * 2638 * This function checks if the SRL can be applied to a selected layer node on 2639 * behalf of the requested node (first argument). This function needs to be 2640 * called with scheduler lock held. 2641 */ 2642 static enum ice_status 2643 ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer) 2644 { 2645 /* SRL profiles are not available on all layers. Check if the 2646 * SRL profile can be applied to a node above or below the 2647 * requested node. SRL configuration is possible only if the 2648 * selected layer's node has single child. 2649 */ 2650 if (sel_layer == node->tx_sched_layer || 2651 ((sel_layer == node->tx_sched_layer + 1) && 2652 node->num_children == 1) || 2653 ((sel_layer == node->tx_sched_layer - 1) && 2654 (node->parent && node->parent->num_children == 1))) 2655 return 0; 2656 2657 return ICE_ERR_CFG; 2658 } 2659 2660 /** 2661 * ice_sched_save_q_bw - save queue node's BW information 2662 * @q_ctx: queue context structure 2663 * @rl_type: rate limit type min, max, or shared 2664 * @bw: bandwidth in Kbps - Kilo bits per sec 2665 * 2666 * Save BW information of queue type node for post replay use. 2667 */ 2668 static enum ice_status 2669 ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw) 2670 { 2671 switch (rl_type) { 2672 case ICE_MIN_BW: 2673 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw); 2674 break; 2675 case ICE_MAX_BW: 2676 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw); 2677 break; 2678 case ICE_SHARED_BW: 2679 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw); 2680 break; 2681 default: 2682 return ICE_ERR_PARAM; 2683 } 2684 return 0; 2685 } 2686 2687 /** 2688 * ice_sched_set_q_bw_lmt - sets queue BW limit 2689 * @pi: port information structure 2690 * @vsi_handle: sw VSI handle 2691 * @tc: traffic class 2692 * @q_handle: software queue handle 2693 * @rl_type: min, max, or shared 2694 * @bw: bandwidth in Kbps 2695 * 2696 * This function sets BW limit of queue scheduling node. 2697 */ 2698 static enum ice_status 2699 ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 2700 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 2701 { 2702 enum ice_status status = ICE_ERR_PARAM; 2703 struct ice_sched_node *node; 2704 struct ice_q_ctx *q_ctx; 2705 2706 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2707 return ICE_ERR_PARAM; 2708 mutex_lock(&pi->sched_lock); 2709 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle); 2710 if (!q_ctx) 2711 goto exit_q_bw_lmt; 2712 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 2713 if (!node) { 2714 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n"); 2715 goto exit_q_bw_lmt; 2716 } 2717 2718 /* Return error if it is not a leaf node */ 2719 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) 2720 goto exit_q_bw_lmt; 2721 2722 /* SRL bandwidth layer selection */ 2723 if (rl_type == ICE_SHARED_BW) { 2724 u8 sel_layer; /* selected layer */ 2725 2726 sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type, 2727 node->tx_sched_layer); 2728 if (sel_layer >= pi->hw->num_tx_sched_layers) { 2729 status = ICE_ERR_PARAM; 2730 goto exit_q_bw_lmt; 2731 } 2732 status = ice_sched_validate_srl_node(node, sel_layer); 2733 if (status) 2734 goto exit_q_bw_lmt; 2735 } 2736 2737 if (bw == ICE_SCHED_DFLT_BW) 2738 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 2739 else 2740 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 2741 2742 if (!status) 2743 status = ice_sched_save_q_bw(q_ctx, rl_type, bw); 2744 2745 exit_q_bw_lmt: 2746 mutex_unlock(&pi->sched_lock); 2747 return status; 2748 } 2749 2750 /** 2751 * ice_cfg_q_bw_lmt - configure queue BW limit 2752 * @pi: port information structure 2753 * @vsi_handle: sw VSI handle 2754 * @tc: traffic class 2755 * @q_handle: software queue handle 2756 * @rl_type: min, max, or shared 2757 * @bw: bandwidth in Kbps 2758 * 2759 * This function configures BW limit of queue scheduling node. 2760 */ 2761 enum ice_status 2762 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 2763 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 2764 { 2765 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 2766 bw); 2767 } 2768 2769 /** 2770 * ice_cfg_q_bw_dflt_lmt - configure queue BW default limit 2771 * @pi: port information structure 2772 * @vsi_handle: sw VSI handle 2773 * @tc: traffic class 2774 * @q_handle: software queue handle 2775 * @rl_type: min, max, or shared 2776 * 2777 * This function configures BW default limit of queue scheduling node. 2778 */ 2779 enum ice_status 2780 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 2781 u16 q_handle, enum ice_rl_type rl_type) 2782 { 2783 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 2784 ICE_SCHED_DFLT_BW); 2785 } 2786 2787 /** 2788 * ice_cfg_rl_burst_size - Set burst size value 2789 * @hw: pointer to the HW struct 2790 * @bytes: burst size in bytes 2791 * 2792 * This function configures/set the burst size to requested new value. The new 2793 * burst size value is used for future rate limit calls. It doesn't change the 2794 * existing or previously created RL profiles. 2795 */ 2796 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes) 2797 { 2798 u16 burst_size_to_prog; 2799 2800 if (bytes < ICE_MIN_BURST_SIZE_ALLOWED || 2801 bytes > ICE_MAX_BURST_SIZE_ALLOWED) 2802 return ICE_ERR_PARAM; 2803 if (ice_round_to_num(bytes, 64) <= 2804 ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY) { 2805 /* 64 byte granularity case */ 2806 /* Disable MSB granularity bit */ 2807 burst_size_to_prog = ICE_64_BYTE_GRANULARITY; 2808 /* round number to nearest 64 byte granularity */ 2809 bytes = ice_round_to_num(bytes, 64); 2810 /* The value is in 64 byte chunks */ 2811 burst_size_to_prog |= (u16)(bytes / 64); 2812 } else { 2813 /* k bytes granularity case */ 2814 /* Enable MSB granularity bit */ 2815 burst_size_to_prog = ICE_KBYTE_GRANULARITY; 2816 /* round number to nearest 1024 granularity */ 2817 bytes = ice_round_to_num(bytes, 1024); 2818 /* check rounding doesn't go beyond allowed */ 2819 if (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY) 2820 bytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY; 2821 /* The value is in k bytes */ 2822 burst_size_to_prog |= (u16)(bytes / 1024); 2823 } 2824 hw->max_burst_size = burst_size_to_prog; 2825 return 0; 2826 } 2827 2828 /** 2829 * ice_sched_replay_node_prio - re-configure node priority 2830 * @hw: pointer to the HW struct 2831 * @node: sched node to configure 2832 * @priority: priority value 2833 * 2834 * This function configures node element's priority value. It 2835 * needs to be called with scheduler lock held. 2836 */ 2837 static enum ice_status 2838 ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node, 2839 u8 priority) 2840 { 2841 struct ice_aqc_txsched_elem_data buf; 2842 struct ice_aqc_txsched_elem *data; 2843 enum ice_status status; 2844 2845 buf = node->info; 2846 data = &buf.data; 2847 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 2848 data->generic = priority; 2849 2850 /* Configure element */ 2851 status = ice_sched_update_elem(hw, node, &buf); 2852 return status; 2853 } 2854 2855 /** 2856 * ice_sched_replay_node_bw - replay node(s) BW 2857 * @hw: pointer to the HW struct 2858 * @node: sched node to configure 2859 * @bw_t_info: BW type information 2860 * 2861 * This function restores node's BW from bw_t_info. The caller needs 2862 * to hold the scheduler lock. 2863 */ 2864 static enum ice_status 2865 ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node, 2866 struct ice_bw_type_info *bw_t_info) 2867 { 2868 struct ice_port_info *pi = hw->port_info; 2869 enum ice_status status = ICE_ERR_PARAM; 2870 u16 bw_alloc; 2871 2872 if (!node) 2873 return status; 2874 if (bitmap_empty(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT)) 2875 return 0; 2876 if (test_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap)) { 2877 status = ice_sched_replay_node_prio(hw, node, 2878 bw_t_info->generic); 2879 if (status) 2880 return status; 2881 } 2882 if (test_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap)) { 2883 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW, 2884 bw_t_info->cir_bw.bw); 2885 if (status) 2886 return status; 2887 } 2888 if (test_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap)) { 2889 bw_alloc = bw_t_info->cir_bw.bw_alloc; 2890 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW, 2891 bw_alloc); 2892 if (status) 2893 return status; 2894 } 2895 if (test_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap)) { 2896 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW, 2897 bw_t_info->eir_bw.bw); 2898 if (status) 2899 return status; 2900 } 2901 if (test_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap)) { 2902 bw_alloc = bw_t_info->eir_bw.bw_alloc; 2903 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW, 2904 bw_alloc); 2905 if (status) 2906 return status; 2907 } 2908 if (test_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap)) 2909 status = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW, 2910 bw_t_info->shared_bw); 2911 return status; 2912 } 2913 2914 /** 2915 * ice_sched_replay_q_bw - replay queue type node BW 2916 * @pi: port information structure 2917 * @q_ctx: queue context structure 2918 * 2919 * This function replays queue type node bandwidth. This function needs to be 2920 * called with scheduler lock held. 2921 */ 2922 enum ice_status 2923 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx) 2924 { 2925 struct ice_sched_node *q_node; 2926 2927 /* Following also checks the presence of node in tree */ 2928 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 2929 if (!q_node) 2930 return ICE_ERR_PARAM; 2931 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info); 2932 } 2933