xref: /linux/drivers/net/ethernet/intel/ice/ice_ptp_hw.h (revision ea518afc992032f7570c0a89ac9240b387dc0faf)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2021, Intel Corporation. */
3 
4 #ifndef _ICE_PTP_HW_H_
5 #define _ICE_PTP_HW_H_
6 #include <linux/dpll.h>
7 
8 enum ice_ptp_tmr_cmd {
9 	ICE_PTP_INIT_TIME,
10 	ICE_PTP_INIT_INCVAL,
11 	ICE_PTP_ADJ_TIME,
12 	ICE_PTP_ADJ_TIME_AT_TIME,
13 	ICE_PTP_READ_TIME,
14 	ICE_PTP_NOP,
15 };
16 
17 enum ice_ptp_serdes {
18 	ICE_PTP_SERDES_1G,
19 	ICE_PTP_SERDES_10G,
20 	ICE_PTP_SERDES_25G,
21 	ICE_PTP_SERDES_40G,
22 	ICE_PTP_SERDES_50G,
23 	ICE_PTP_SERDES_100G
24 };
25 
26 enum ice_ptp_link_spd {
27 	ICE_PTP_LNK_SPD_1G,
28 	ICE_PTP_LNK_SPD_10G,
29 	ICE_PTP_LNK_SPD_25G,
30 	ICE_PTP_LNK_SPD_25G_RS,
31 	ICE_PTP_LNK_SPD_40G,
32 	ICE_PTP_LNK_SPD_50G,
33 	ICE_PTP_LNK_SPD_50G_RS,
34 	ICE_PTP_LNK_SPD_100G_RS,
35 	NUM_ICE_PTP_LNK_SPD /* Must be last */
36 };
37 
38 enum ice_ptp_fec_mode {
39 	ICE_PTP_FEC_MODE_NONE,
40 	ICE_PTP_FEC_MODE_CLAUSE74,
41 	ICE_PTP_FEC_MODE_RS_FEC
42 };
43 
44 /**
45  * struct ice_time_ref_info_e82x
46  * @pll_freq: Frequency of PLL that drives timer ticks in Hz
47  * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
48  * @pps_delay: propagation delay of the PPS output signal
49  *
50  * Characteristic information for the various TIME_REF sources possible in the
51  * E822 devices
52  */
53 struct ice_time_ref_info_e82x {
54 	u64 pll_freq;
55 	u64 nominal_incval;
56 	u8 pps_delay;
57 };
58 
59 /**
60  * struct ice_vernier_info_e82x
61  * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
62  * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
63  * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
64  * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
65  * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
66  * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
67  * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
68  * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
69  * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
70  * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
71  * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
72  *
73  * Table of constants used during as part of the Vernier calibration of the Tx
74  * and Rx timestamps. This includes frequency values used to compute TUs per
75  * PAR/PCS clock cycle, and static delay values measured during hardware
76  * design.
77  *
78  * Note that some values are not used for all link speeds, and the
79  * P_REG_DESK_PAR* registers may represent different clock markers at
80  * different link speeds, either the deskew marker for multi-lane link speeds
81  * or the Reed Solomon gearbox marker for RS-FEC.
82  */
83 struct ice_vernier_info_e82x {
84 	u32 tx_par_clk;
85 	u32 rx_par_clk;
86 	u32 tx_pcs_clk;
87 	u32 rx_pcs_clk;
88 	u32 tx_desk_rsgb_par;
89 	u32 rx_desk_rsgb_par;
90 	u32 tx_desk_rsgb_pcs;
91 	u32 rx_desk_rsgb_pcs;
92 	u32 tx_fixed_delay;
93 	u32 pmd_adj_divisor;
94 	u32 rx_fixed_delay;
95 };
96 
97 /**
98  * struct ice_cgu_pll_params_e82x
99  * @refclk_pre_div: Reference clock pre-divisor
100  * @feedback_div: Feedback divisor
101  * @frac_n_div: Fractional divisor
102  * @post_pll_div: Post PLL divisor
103  *
104  * Clock Generation Unit parameters used to program the PLL based on the
105  * selected TIME_REF frequency.
106  */
107 struct ice_cgu_pll_params_e82x {
108 	u32 refclk_pre_div;
109 	u32 feedback_div;
110 	u32 frac_n_div;
111 	u32 post_pll_div;
112 };
113 
114 #define E810C_QSFP_C827_0_HANDLE	2
115 #define E810C_QSFP_C827_1_HANDLE	3
116 enum ice_e810_c827_idx {
117 	C827_0,
118 	C827_1
119 };
120 
121 enum ice_phy_rclk_pins {
122 	ICE_RCLKA_PIN = 0,		/* SCL pin */
123 	ICE_RCLKB_PIN,			/* SDA pin */
124 };
125 
126 #define ICE_E810_RCLK_PINS_NUM		(ICE_RCLKB_PIN + 1)
127 #define ICE_E82X_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)
128 #define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
129 					  (_pin) + ZL_REF1P)
130 
131 enum ice_zl_cgu_in_pins {
132 	ZL_REF0P = 0,
133 	ZL_REF0N,
134 	ZL_REF1P,
135 	ZL_REF1N,
136 	ZL_REF2P,
137 	ZL_REF2N,
138 	ZL_REF3P,
139 	ZL_REF3N,
140 	ZL_REF4P,
141 	ZL_REF4N,
142 	NUM_ZL_CGU_INPUT_PINS
143 };
144 
145 enum ice_zl_cgu_out_pins {
146 	ZL_OUT0 = 0,
147 	ZL_OUT1,
148 	ZL_OUT2,
149 	ZL_OUT3,
150 	ZL_OUT4,
151 	ZL_OUT5,
152 	ZL_OUT6,
153 	NUM_ZL_CGU_OUTPUT_PINS
154 };
155 
156 enum ice_si_cgu_in_pins {
157 	SI_REF0P = 0,
158 	SI_REF0N,
159 	SI_REF1P,
160 	SI_REF1N,
161 	SI_REF2P,
162 	SI_REF2N,
163 	SI_REF3,
164 	SI_REF4,
165 	NUM_SI_CGU_INPUT_PINS
166 };
167 
168 enum ice_si_cgu_out_pins {
169 	SI_OUT0 = 0,
170 	SI_OUT1,
171 	SI_OUT2,
172 	SI_OUT3,
173 	SI_OUT4,
174 	NUM_SI_CGU_OUTPUT_PINS
175 };
176 
177 struct ice_cgu_pin_desc {
178 	char *name;
179 	u8 index;
180 	enum dpll_pin_type type;
181 	u32 freq_supp_num;
182 	struct dpll_pin_frequency *freq_supp;
183 };
184 
185 extern const struct
186 ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
187 
188 #define E810C_QSFP_C827_0_HANDLE 2
189 #define E810C_QSFP_C827_1_HANDLE 3
190 
191 /* Table of constants related to possible TIME_REF sources */
192 extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];
193 
194 /* Table of constants for Vernier calibration on E822 */
195 extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
196 
197 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
198  * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
199  */
200 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
201 
202 /* Device agnostic functions */
203 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
204 bool ice_ptp_lock(struct ice_hw *hw);
205 void ice_ptp_unlock(struct ice_hw *hw);
206 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
207 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
208 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
209 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
210 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
211 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
212 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
213 void ice_ptp_reset_ts_memory(struct ice_hw *hw);
214 int ice_ptp_init_phc(struct ice_hw *hw);
215 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
216 
217 /* E822 family functions */
218 int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
219 int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
220 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
221 
222 /**
223  * ice_e82x_time_ref - Get the current TIME_REF from capabilities
224  * @hw: pointer to the HW structure
225  *
226  * Returns the current TIME_REF from the capabilities structure.
227  */
228 static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)
229 {
230 	return hw->func_caps.ts_func_info.time_ref;
231 }
232 
233 /**
234  * ice_set_e82x_time_ref - Set new TIME_REF
235  * @hw: pointer to the HW structure
236  * @time_ref: new TIME_REF to set
237  *
238  * Update the TIME_REF in the capabilities structure in response to some
239  * change, such as an update to the CGU registers.
240  */
241 static inline void
242 ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
243 {
244 	hw->func_caps.ts_func_info.time_ref = time_ref;
245 }
246 
247 static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
248 {
249 	return e822_time_ref[time_ref].pll_freq;
250 }
251 
252 static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
253 {
254 	return e822_time_ref[time_ref].nominal_incval;
255 }
256 
257 static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)
258 {
259 	return e822_time_ref[time_ref].pps_delay;
260 }
261 
262 /* E822 Vernier calibration functions */
263 int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
264 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
265 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
266 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
267 
268 /* E810 family functions */
269 int ice_ptp_init_phy_e810(struct ice_hw *hw);
270 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
271 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
272 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
273 bool ice_is_pca9575_present(struct ice_hw *hw);
274 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
275 struct dpll_pin_frequency *
276 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
277 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
278 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
279 		      enum dpll_lock_status last_dpll_state, u8 *pin,
280 		      u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
281 		      enum dpll_lock_status *dpll_state);
282 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
283 
284 void ice_ptp_init_phy_model(struct ice_hw *hw);
285 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
286 				      unsigned long *caps);
287 
288 #define PFTSYN_SEM_BYTES	4
289 
290 #define ICE_PTP_CLOCK_INDEX_0	0x00
291 #define ICE_PTP_CLOCK_INDEX_1	0x01
292 
293 /* PHY timer commands */
294 #define SEL_CPK_SRC	8
295 #define SEL_PHY_SRC	3
296 
297 /* Time Sync command Definitions */
298 #define GLTSYN_CMD_INIT_TIME		BIT(0)
299 #define GLTSYN_CMD_INIT_INCVAL		BIT(1)
300 #define GLTSYN_CMD_INIT_TIME_INCVAL	(BIT(0) | BIT(1))
301 #define GLTSYN_CMD_ADJ_TIME		BIT(2)
302 #define GLTSYN_CMD_ADJ_INIT_TIME	(BIT(2) | BIT(3))
303 #define GLTSYN_CMD_READ_TIME		BIT(7)
304 
305 /* PHY port Time Sync command definitions */
306 #define PHY_CMD_INIT_TIME		BIT(0)
307 #define PHY_CMD_INIT_INCVAL		BIT(1)
308 #define PHY_CMD_ADJ_TIME		(BIT(0) | BIT(1))
309 #define PHY_CMD_ADJ_TIME_AT_TIME	(BIT(0) | BIT(2))
310 #define PHY_CMD_READ_TIME		(BIT(0) | BIT(1) | BIT(2))
311 
312 #define TS_CMD_MASK_E810		0xFF
313 #define TS_CMD_MASK			0xF
314 #define SYNC_EXEC_CMD			0x3
315 
316 /* Macros to derive port low and high addresses on both quads */
317 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
318 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
319 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
320 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
321 
322 /* PHY QUAD register base addresses */
323 #define Q_0_BASE			0x94000
324 #define Q_1_BASE			0x114000
325 
326 /* Timestamp memory reset registers */
327 #define Q_REG_TS_CTRL			0x618
328 #define Q_REG_TS_CTRL_S			0
329 #define Q_REG_TS_CTRL_M			BIT(0)
330 
331 /* Timestamp availability status registers */
332 #define Q_REG_TX_MEMORY_STATUS_L	0xCF0
333 #define Q_REG_TX_MEMORY_STATUS_U	0xCF4
334 
335 /* Tx FIFO status registers */
336 #define Q_REG_FIFO23_STATUS		0xCF8
337 #define Q_REG_FIFO01_STATUS		0xCFC
338 #define Q_REG_FIFO02_S			0
339 #define Q_REG_FIFO02_M			ICE_M(0x3FF, 0)
340 #define Q_REG_FIFO13_S			10
341 #define Q_REG_FIFO13_M			ICE_M(0x3FF, 10)
342 
343 /* Interrupt control Config registers */
344 #define Q_REG_TX_MEM_GBL_CFG		0xC08
345 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S	0
346 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M	BIT(0)
347 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S	1
348 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M	ICE_M(0xFF, 1)
349 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S	9
350 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
351 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S	15
352 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M	BIT(15)
353 
354 /* Tx Timestamp data registers */
355 #define Q_REG_TX_MEMORY_BANK_START	0xA00
356 
357 /* PHY port register base addresses */
358 #define P_0_BASE			0x80000
359 #define P_4_BASE			0x106000
360 
361 /* Timestamp init registers */
362 #define P_REG_RX_TIMER_INC_PRE_L	0x46C
363 #define P_REG_RX_TIMER_INC_PRE_U	0x470
364 #define P_REG_TX_TIMER_INC_PRE_L	0x44C
365 #define P_REG_TX_TIMER_INC_PRE_U	0x450
366 
367 /* Timestamp match and adjust target registers */
368 #define P_REG_RX_TIMER_CNT_ADJ_L	0x474
369 #define P_REG_RX_TIMER_CNT_ADJ_U	0x478
370 #define P_REG_TX_TIMER_CNT_ADJ_L	0x454
371 #define P_REG_TX_TIMER_CNT_ADJ_U	0x458
372 
373 /* Timestamp capture registers */
374 #define P_REG_RX_CAPTURE_L		0x4D8
375 #define P_REG_RX_CAPTURE_U		0x4DC
376 #define P_REG_TX_CAPTURE_L		0x4B4
377 #define P_REG_TX_CAPTURE_U		0x4B8
378 
379 /* Timestamp PHY incval registers */
380 #define P_REG_TIMETUS_L			0x410
381 #define P_REG_TIMETUS_U			0x414
382 
383 #define P_REG_40B_LOW_M			0xFF
384 #define P_REG_40B_HIGH_S		8
385 
386 /* PHY window length registers */
387 #define P_REG_WL			0x40C
388 
389 #define PTP_VERNIER_WL			0x111ed
390 
391 /* PHY start registers */
392 #define P_REG_PS			0x408
393 #define P_REG_PS_START_S		0
394 #define P_REG_PS_START_M		BIT(0)
395 #define P_REG_PS_BYPASS_MODE_S		1
396 #define P_REG_PS_BYPASS_MODE_M		BIT(1)
397 #define P_REG_PS_ENA_CLK_S		2
398 #define P_REG_PS_ENA_CLK_M		BIT(2)
399 #define P_REG_PS_LOAD_OFFSET_S		3
400 #define P_REG_PS_LOAD_OFFSET_M		BIT(3)
401 #define P_REG_PS_SFT_RESET_S		11
402 #define P_REG_PS_SFT_RESET_M		BIT(11)
403 
404 /* PHY offset valid registers */
405 #define P_REG_TX_OV_STATUS		0x4D4
406 #define P_REG_TX_OV_STATUS_OV_S		0
407 #define P_REG_TX_OV_STATUS_OV_M		BIT(0)
408 #define P_REG_RX_OV_STATUS		0x4F8
409 #define P_REG_RX_OV_STATUS_OV_S		0
410 #define P_REG_RX_OV_STATUS_OV_M		BIT(0)
411 
412 /* PHY offset ready registers */
413 #define P_REG_TX_OR			0x45C
414 #define P_REG_RX_OR			0x47C
415 
416 /* PHY total offset registers */
417 #define P_REG_TOTAL_RX_OFFSET_L		0x460
418 #define P_REG_TOTAL_RX_OFFSET_U		0x464
419 #define P_REG_TOTAL_TX_OFFSET_L		0x440
420 #define P_REG_TOTAL_TX_OFFSET_U		0x444
421 
422 /* Timestamp PAR/PCS registers */
423 #define P_REG_UIX66_10G_40G_L		0x480
424 #define P_REG_UIX66_10G_40G_U		0x484
425 #define P_REG_UIX66_25G_100G_L		0x488
426 #define P_REG_UIX66_25G_100G_U		0x48C
427 #define P_REG_DESK_PAR_RX_TUS_L		0x490
428 #define P_REG_DESK_PAR_RX_TUS_U		0x494
429 #define P_REG_DESK_PAR_TX_TUS_L		0x498
430 #define P_REG_DESK_PAR_TX_TUS_U		0x49C
431 #define P_REG_DESK_PCS_RX_TUS_L		0x4A0
432 #define P_REG_DESK_PCS_RX_TUS_U		0x4A4
433 #define P_REG_DESK_PCS_TX_TUS_L		0x4A8
434 #define P_REG_DESK_PCS_TX_TUS_U		0x4AC
435 #define P_REG_PAR_RX_TUS_L		0x420
436 #define P_REG_PAR_RX_TUS_U		0x424
437 #define P_REG_PAR_TX_TUS_L		0x428
438 #define P_REG_PAR_TX_TUS_U		0x42C
439 #define P_REG_PCS_RX_TUS_L		0x430
440 #define P_REG_PCS_RX_TUS_U		0x434
441 #define P_REG_PCS_TX_TUS_L		0x438
442 #define P_REG_PCS_TX_TUS_U		0x43C
443 #define P_REG_PAR_RX_TIME_L		0x4F0
444 #define P_REG_PAR_RX_TIME_U		0x4F4
445 #define P_REG_PAR_TX_TIME_L		0x4CC
446 #define P_REG_PAR_TX_TIME_U		0x4D0
447 #define P_REG_PAR_PCS_RX_OFFSET_L	0x4E8
448 #define P_REG_PAR_PCS_RX_OFFSET_U	0x4EC
449 #define P_REG_PAR_PCS_TX_OFFSET_L	0x4C4
450 #define P_REG_PAR_PCS_TX_OFFSET_U	0x4C8
451 #define P_REG_LINK_SPEED		0x4FC
452 #define P_REG_LINK_SPEED_SERDES_S	0
453 #define P_REG_LINK_SPEED_SERDES_M	ICE_M(0x7, 0)
454 #define P_REG_LINK_SPEED_FEC_MODE_S	3
455 #define P_REG_LINK_SPEED_FEC_MODE_M	ICE_M(0x3, 3)
456 #define P_REG_LINK_SPEED_FEC_MODE(reg)			\
457 	(((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >>	\
458 	 P_REG_LINK_SPEED_FEC_MODE_S)
459 
460 /* PHY timestamp related registers */
461 #define P_REG_PMD_ALIGNMENT		0x0FC
462 #define P_REG_RX_80_TO_160_CNT		0x6FC
463 #define P_REG_RX_80_TO_160_CNT_RXCYC_S	0
464 #define P_REG_RX_80_TO_160_CNT_RXCYC_M	BIT(0)
465 #define P_REG_RX_40_TO_160_CNT		0x8FC
466 #define P_REG_RX_40_TO_160_CNT_RXCYC_S	0
467 #define P_REG_RX_40_TO_160_CNT_RXCYC_M	ICE_M(0x3, 0)
468 
469 /* Rx FIFO status registers */
470 #define P_REG_RX_OV_FS			0x4F8
471 #define P_REG_RX_OV_FS_FIFO_STATUS_S	2
472 #define P_REG_RX_OV_FS_FIFO_STATUS_M	ICE_M(0x3FF, 2)
473 
474 /* Timestamp command registers */
475 #define P_REG_TX_TMR_CMD		0x448
476 #define P_REG_RX_TMR_CMD		0x468
477 
478 /* E810 timesync enable register */
479 #define ETH_GLTSYN_ENA(_i)		(0x03000348 + ((_i) * 4))
480 
481 /* E810 shadow init time registers */
482 #define ETH_GLTSYN_SHTIME_0(i)		(0x03000368 + ((i) * 32))
483 #define ETH_GLTSYN_SHTIME_L(i)		(0x0300036C + ((i) * 32))
484 
485 /* E810 shadow time adjust registers */
486 #define ETH_GLTSYN_SHADJ_L(_i)		(0x03000378 + ((_i) * 32))
487 #define ETH_GLTSYN_SHADJ_H(_i)		(0x0300037C + ((_i) * 32))
488 
489 /* E810 timer command register */
490 #define ETH_GLTSYN_CMD			0x03000344
491 
492 /* Source timer incval macros */
493 #define INCVAL_HIGH_M			0xFF
494 
495 /* Timestamp block macros */
496 #define TS_VALID			BIT(0)
497 #define TS_LOW_M			0xFFFFFFFF
498 #define TS_HIGH_M			0xFF
499 #define TS_HIGH_S			32
500 
501 #define TS_PHY_LOW_M			0xFF
502 #define TS_PHY_HIGH_M			0xFFFFFFFF
503 #define TS_PHY_HIGH_S			8
504 
505 #define BYTES_PER_IDX_ADDR_L_U		8
506 #define BYTES_PER_IDX_ADDR_L		4
507 
508 /* Tx timestamp low latency read definitions */
509 #define TS_LL_READ_RETRIES		200
510 #define TS_LL_READ_TS_HIGH		GENMASK(23, 16)
511 #define TS_LL_READ_TS_IDX		GENMASK(29, 24)
512 #define TS_LL_READ_TS_INTR		BIT(30)
513 #define TS_LL_READ_TS			BIT(31)
514 
515 /* Internal PHY timestamp address */
516 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
517 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U +		\
518 			     BYTES_PER_IDX_ADDR_L))
519 
520 /* External PHY timestamp address */
521 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) +			\
522 				 ((idx) * BYTES_PER_IDX_ADDR_L_U))
523 
524 #define LOW_TX_MEMORY_BANK_START	0x03090000
525 #define HIGH_TX_MEMORY_BANK_START	0x03090004
526 
527 /* E810T SMA controller pin control */
528 #define ICE_SMA1_DIR_EN_E810T		BIT(4)
529 #define ICE_SMA1_TX_EN_E810T		BIT(5)
530 #define ICE_SMA2_UFL2_RX_DIS_E810T	BIT(3)
531 #define ICE_SMA2_DIR_EN_E810T		BIT(6)
532 #define ICE_SMA2_TX_EN_E810T		BIT(7)
533 
534 #define ICE_SMA1_MASK_E810T	(ICE_SMA1_DIR_EN_E810T | \
535 				 ICE_SMA1_TX_EN_E810T)
536 #define ICE_SMA2_MASK_E810T	(ICE_SMA2_UFL2_RX_DIS_E810T | \
537 				 ICE_SMA2_DIR_EN_E810T | \
538 				 ICE_SMA2_TX_EN_E810T)
539 #define ICE_ALL_SMA_MASK_E810T	(ICE_SMA1_MASK_E810T | \
540 				 ICE_SMA2_MASK_E810T)
541 
542 #define ICE_SMA_MIN_BIT_E810T	3
543 #define ICE_SMA_MAX_BIT_E810T	7
544 #define ICE_PCA9575_P1_OFFSET	8
545 
546 /* E810T PCA9575 IO controller registers */
547 #define ICE_PCA9575_P0_IN	0x0
548 
549 /* E810T PCA9575 IO controller pin control */
550 #define ICE_E810T_P0_GNSS_PRSNT_N	BIT(4)
551 
552 #endif /* _ICE_PTP_HW_H_ */
553