1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_LAN_TX_RX_H_ 5 #define _ICE_LAN_TX_RX_H_ 6 7 union ice_32byte_rx_desc { 8 struct { 9 __le64 pkt_addr; /* Packet buffer address */ 10 __le64 hdr_addr; /* Header buffer address */ 11 /* bit 0 of hdr_addr is DD bit */ 12 __le64 rsvd1; 13 __le64 rsvd2; 14 } read; 15 struct { 16 struct { 17 struct { 18 __le16 mirroring_status; 19 __le16 l2tag1; 20 } lo_dword; 21 union { 22 __le32 rss; /* RSS Hash */ 23 __le32 fd_id; /* Flow Director filter ID */ 24 } hi_dword; 25 } qword0; 26 struct { 27 /* status/error/PTYPE/length */ 28 __le64 status_error_len; 29 } qword1; 30 struct { 31 __le16 ext_status; /* extended status */ 32 __le16 rsvd; 33 __le16 l2tag2_1; 34 __le16 l2tag2_2; 35 } qword2; 36 struct { 37 __le32 reserved; 38 __le32 fd_id; 39 } qword3; 40 } wb; /* writeback */ 41 }; 42 43 struct ice_fltr_desc { 44 __le64 qidx_compq_space_stat; 45 __le64 dtype_cmd_vsi_fdid; 46 }; 47 48 #define ICE_FXD_FLTR_QW0_QINDEX_S 0 49 #define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S) 50 #define ICE_FXD_FLTR_QW0_COMP_Q_S 11 51 #define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S) 52 #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL 53 54 #define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12 55 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M \ 56 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S) 57 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL 58 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW 0x2ULL 59 60 #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14 61 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S) 62 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL 63 64 #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16 65 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \ 66 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S) 67 #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29 68 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S) 69 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL 70 71 #define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31 72 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S) 73 #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL 74 #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL 75 76 #define ICE_FXD_FLTR_QW0_TO_Q_S 32 77 #define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S) 78 #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL 79 80 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35 81 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) 82 #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL 83 84 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38 85 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \ 86 (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) 87 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL 88 89 #define ICE_FXD_FLTR_QW0_DROP_S 40 90 #define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S) 91 #define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL 92 #define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL 93 94 #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41 95 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S) 96 #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL 97 98 #define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44 99 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S) 100 #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL 101 102 #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48 103 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \ 104 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S) 105 #define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL 106 107 #define ICE_FXD_FLTR_QW1_DTYPE_S 0 108 #define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S) 109 #define ICE_FXD_FLTR_QW1_PCMD_S 4 110 #define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S) 111 #define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL 112 #define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL 113 114 #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5 115 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S) 116 #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL 117 118 #define ICE_FXD_FLTR_QW1_PROF_S 8 119 #define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S) 120 #define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL 121 122 #define ICE_FXD_FLTR_QW1_FD_VSI_S 14 123 #define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S) 124 #define ICE_FXD_FLTR_QW1_SWAP_S 24 125 #define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S) 126 #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL 127 #define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL 128 129 #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 130 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) 131 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL 132 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL 133 134 #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 135 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) 136 #define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL 137 138 #define ICE_FXD_FLTR_QW1_FDID_S 32 139 #define ICE_FXD_FLTR_QW1_FDID_M \ 140 (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) 141 #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL 142 143 /* definition for FD filter programming status descriptor WB format */ 144 #define ICE_FXD_FLTR_WB_QW1_DD_S 0 145 #define ICE_FXD_FLTR_WB_QW1_DD_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S) 146 #define ICE_FXD_FLTR_WB_QW1_DD_YES 0x1ULL 147 148 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_S 1 149 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_M \ 150 (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S) 151 #define ICE_FXD_FLTR_WB_QW1_PROG_ADD 0x0ULL 152 #define ICE_FXD_FLTR_WB_QW1_PROG_DEL 0x1ULL 153 154 #define ICE_FXD_FLTR_WB_QW1_FAIL_S 4 155 #define ICE_FXD_FLTR_WB_QW1_FAIL_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S) 156 #define ICE_FXD_FLTR_WB_QW1_FAIL_YES 0x1ULL 157 158 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5 159 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ 160 (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) 161 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL 162 163 struct ice_rx_ptype_decoded { 164 u32 known:1; 165 u32 outer_ip:1; 166 u32 outer_ip_ver:2; 167 u32 outer_frag:1; 168 u32 tunnel_type:3; 169 u32 tunnel_end_prot:2; 170 u32 tunnel_end_frag:1; 171 u32 inner_prot:4; 172 u32 payload_layer:3; 173 }; 174 175 enum ice_rx_ptype_outer_ip { 176 ICE_RX_PTYPE_OUTER_L2 = 0, 177 ICE_RX_PTYPE_OUTER_IP = 1, 178 }; 179 180 enum ice_rx_ptype_outer_ip_ver { 181 ICE_RX_PTYPE_OUTER_NONE = 0, 182 ICE_RX_PTYPE_OUTER_IPV4 = 1, 183 ICE_RX_PTYPE_OUTER_IPV6 = 2, 184 }; 185 186 enum ice_rx_ptype_outer_fragmented { 187 ICE_RX_PTYPE_NOT_FRAG = 0, 188 ICE_RX_PTYPE_FRAG = 1, 189 }; 190 191 enum ice_rx_ptype_tunnel_type { 192 ICE_RX_PTYPE_TUNNEL_NONE = 0, 193 ICE_RX_PTYPE_TUNNEL_IP_IP = 1, 194 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 195 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 196 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 197 }; 198 199 enum ice_rx_ptype_tunnel_end_prot { 200 ICE_RX_PTYPE_TUNNEL_END_NONE = 0, 201 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, 202 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, 203 }; 204 205 enum ice_rx_ptype_inner_prot { 206 ICE_RX_PTYPE_INNER_PROT_NONE = 0, 207 ICE_RX_PTYPE_INNER_PROT_UDP = 1, 208 ICE_RX_PTYPE_INNER_PROT_TCP = 2, 209 ICE_RX_PTYPE_INNER_PROT_SCTP = 3, 210 ICE_RX_PTYPE_INNER_PROT_ICMP = 4, 211 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, 212 }; 213 214 enum ice_rx_ptype_payload_layer { 215 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 216 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 217 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 218 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 219 }; 220 221 /* Rx Flex Descriptor 222 * This descriptor is used instead of the legacy version descriptor when 223 * ice_rlan_ctx.adv_desc is set 224 */ 225 union ice_32b_rx_flex_desc { 226 struct { 227 __le64 pkt_addr; /* Packet buffer address */ 228 __le64 hdr_addr; /* Header buffer address */ 229 /* bit 0 of hdr_addr is DD bit */ 230 __le64 rsvd1; 231 __le64 rsvd2; 232 } read; 233 struct { 234 /* Qword 0 */ 235 u8 rxdid; /* descriptor builder profile ID */ 236 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 237 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 238 __le16 pkt_len; /* [15:14] are reserved */ 239 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 240 /* sph=[11:11] */ 241 /* ff1/ext=[15:12] */ 242 243 /* Qword 1 */ 244 __le16 status_error0; 245 __le16 l2tag1; 246 __le16 flex_meta0; 247 __le16 flex_meta1; 248 249 /* Qword 2 */ 250 __le16 status_error1; 251 u8 flex_flags2; 252 u8 time_stamp_low; 253 __le16 l2tag2_1st; 254 __le16 l2tag2_2nd; 255 256 /* Qword 3 */ 257 __le16 flex_meta2; 258 __le16 flex_meta3; 259 union { 260 struct { 261 __le16 flex_meta4; 262 __le16 flex_meta5; 263 } flex; 264 __le32 ts_high; 265 } flex_ts; 266 } wb; /* writeback */ 267 }; 268 269 /* Rx Flex Descriptor NIC Profile 270 * This descriptor corresponds to RxDID 2 which contains 271 * metadata fields for RSS, flow ID and timestamp info 272 */ 273 struct ice_32b_rx_flex_desc_nic { 274 /* Qword 0 */ 275 u8 rxdid; 276 u8 mir_id_umb_cast; 277 __le16 ptype_flexi_flags0; 278 __le16 pkt_len; 279 __le16 hdr_len_sph_flex_flags1; 280 281 /* Qword 1 */ 282 __le16 status_error0; 283 __le16 l2tag1; 284 __le32 rss_hash; 285 286 /* Qword 2 */ 287 __le16 status_error1; 288 u8 flexi_flags2; 289 u8 ts_low; 290 __le16 l2tag2_1st; 291 __le16 l2tag2_2nd; 292 293 /* Qword 3 */ 294 __le32 flow_id; 295 union { 296 struct { 297 __le16 vlan_id; 298 __le16 flow_id_ipv6; 299 } flex; 300 __le32 ts_high; 301 } flex_ts; 302 }; 303 304 /* Rx Flex Descriptor NIC Profile 305 * RxDID Profile ID 6 306 * Flex-field 0: RSS hash lower 16-bits 307 * Flex-field 1: RSS hash upper 16-bits 308 * Flex-field 2: Flow ID lower 16-bits 309 * Flex-field 3: Source VSI 310 * Flex-field 4: reserved, VLAN ID taken from L2Tag 311 */ 312 struct ice_32b_rx_flex_desc_nic_2 { 313 /* Qword 0 */ 314 u8 rxdid; 315 u8 mir_id_umb_cast; 316 __le16 ptype_flexi_flags0; 317 __le16 pkt_len; 318 __le16 hdr_len_sph_flex_flags1; 319 320 /* Qword 1 */ 321 __le16 status_error0; 322 __le16 l2tag1; 323 __le32 rss_hash; 324 325 /* Qword 2 */ 326 __le16 status_error1; 327 u8 flexi_flags2; 328 u8 ts_low; 329 __le16 l2tag2_1st; 330 __le16 l2tag2_2nd; 331 332 /* Qword 3 */ 333 __le16 flow_id; 334 __le16 src_vsi; 335 union { 336 struct { 337 __le16 rsvd; 338 __le16 flow_id_ipv6; 339 } flex; 340 __le32 ts_high; 341 } flex_ts; 342 }; 343 344 /* Receive Flex Descriptor profile IDs: There are a total 345 * of 64 profiles where profile IDs 0/1 are for legacy; and 346 * profiles 2-63 are flex profiles that can be programmed 347 * with a specific metadata (profile 7 reserved for HW) 348 */ 349 enum ice_rxdid { 350 ICE_RXDID_LEGACY_0 = 0, 351 ICE_RXDID_LEGACY_1 = 1, 352 ICE_RXDID_FLEX_NIC = 2, 353 ICE_RXDID_FLEX_NIC_2 = 6, 354 ICE_RXDID_HW = 7, 355 ICE_RXDID_LAST = 63, 356 }; 357 358 /* Receive Flex Descriptor Rx opcode values */ 359 #define ICE_RX_OPC_MDID 0x01 360 361 /* Receive Descriptor MDID values that access packet flags */ 362 enum ice_flex_mdid_pkt_flags { 363 ICE_RX_MDID_PKT_FLAGS_15_0 = 20, 364 ICE_RX_MDID_PKT_FLAGS_31_16, 365 ICE_RX_MDID_PKT_FLAGS_47_32, 366 ICE_RX_MDID_PKT_FLAGS_63_48, 367 }; 368 369 /* Receive Descriptor MDID values */ 370 enum ice_flex_rx_mdid { 371 ICE_RX_MDID_FLOW_ID_LOWER = 5, 372 ICE_RX_MDID_FLOW_ID_HIGH, 373 ICE_RX_MDID_SRC_VSI = 19, 374 ICE_RX_MDID_HASH_LOW = 56, 375 ICE_RX_MDID_HASH_HIGH, 376 }; 377 378 /* Rx/Tx Flag64 packet flag bits */ 379 enum ice_flg64_bits { 380 ICE_FLG_PKT_DSI = 0, 381 ICE_FLG_EVLAN_x8100 = 14, 382 ICE_FLG_EVLAN_x9100, 383 ICE_FLG_VLAN_x8100, 384 ICE_FLG_TNL_MAC = 22, 385 ICE_FLG_TNL_VLAN, 386 ICE_FLG_PKT_FRG, 387 ICE_FLG_FIN = 32, 388 ICE_FLG_SYN, 389 ICE_FLG_RST, 390 ICE_FLG_TNL0 = 38, 391 ICE_FLG_TNL1, 392 ICE_FLG_TNL2, 393 ICE_FLG_UDP_GRE, 394 ICE_FLG_RSVD = 63 395 }; 396 397 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ 398 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ 399 400 /* for ice_32byte_rx_flex_desc.pkt_length member */ 401 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ 402 403 enum ice_rx_flex_desc_status_error_0_bits { 404 /* Note: These are predefined bit offsets */ 405 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, 406 ICE_RX_FLEX_DESC_STATUS0_EOF_S, 407 ICE_RX_FLEX_DESC_STATUS0_HBO_S, 408 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, 409 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 410 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 411 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 412 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 413 ICE_RX_FLEX_DESC_STATUS0_LPBK_S, 414 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 415 ICE_RX_FLEX_DESC_STATUS0_RXE_S, 416 ICE_RX_FLEX_DESC_STATUS0_CRCP_S, 417 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 418 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 419 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 420 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 421 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 422 }; 423 424 enum ice_rx_flex_desc_status_error_1_bits { 425 /* Note: These are predefined bit offsets */ 426 ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4, 427 /* [10:5] reserved */ 428 ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11, 429 ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */ 430 }; 431 432 #define ICE_RXQ_CTX_SIZE_DWORDS 8 433 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 434 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 435 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 436 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) 437 438 /* RLAN Rx queue context data 439 * 440 * The sizes of the variables may be larger than needed due to crossing byte 441 * boundaries. If we do not have the width of the variable set to the correct 442 * size then we could end up shifting bits off the top of the variable when the 443 * variable is at the top of a byte and crosses over into the next byte. 444 */ 445 struct ice_rlan_ctx { 446 u16 head; 447 u16 cpuid; /* bigger than needed, see above for reason */ 448 #define ICE_RLAN_BASE_S 7 449 u64 base; 450 u16 qlen; 451 #define ICE_RLAN_CTX_DBUF_S 7 452 u16 dbuf; /* bigger than needed, see above for reason */ 453 #define ICE_RLAN_CTX_HBUF_S 6 454 u16 hbuf; /* bigger than needed, see above for reason */ 455 u8 dtype; 456 u8 dsize; 457 u8 crcstrip; 458 u8 l2tsel; 459 u8 hsplit_0; 460 u8 hsplit_1; 461 u8 showiv; 462 u32 rxmax; /* bigger than needed, see above for reason */ 463 u8 tphrdesc_ena; 464 u8 tphwdesc_ena; 465 u8 tphdata_ena; 466 u8 tphhead_ena; 467 u16 lrxqthresh; /* bigger than needed, see above for reason */ 468 u8 prefena; /* NOTE: normally must be set to 1 at init */ 469 }; 470 471 struct ice_ctx_ele { 472 u16 offset; 473 u16 size_of; 474 u16 width; 475 u16 lsb; 476 }; 477 478 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ 479 .offset = offsetof(struct _struct, _ele), \ 480 .size_of = sizeof_field(struct _struct, _ele), \ 481 .width = _width, \ 482 .lsb = _lsb, \ 483 } 484 485 /* for hsplit_0 field of Rx RLAN context */ 486 enum ice_rlan_ctx_rx_hsplit_0 { 487 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, 488 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, 489 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, 490 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 491 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, 492 }; 493 494 /* for hsplit_1 field of Rx RLAN context */ 495 enum ice_rlan_ctx_rx_hsplit_1 { 496 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, 497 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, 498 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, 499 }; 500 501 /* Tx Descriptor */ 502 struct ice_tx_desc { 503 __le64 buf_addr; /* Address of descriptor's data buf */ 504 __le64 cmd_type_offset_bsz; 505 }; 506 507 enum ice_tx_desc_dtype_value { 508 ICE_TX_DESC_DTYPE_DATA = 0x0, 509 ICE_TX_DESC_DTYPE_CTX = 0x1, 510 ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8, 511 /* DESC_DONE - HW has completed write-back of descriptor */ 512 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, 513 }; 514 515 #define ICE_TXD_QW1_CMD_S 4 516 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) 517 518 enum ice_tx_desc_cmd_bits { 519 ICE_TX_DESC_CMD_EOP = 0x0001, 520 ICE_TX_DESC_CMD_RS = 0x0002, 521 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, 522 ICE_TX_DESC_CMD_DUMMY = 0x0010, 523 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, 524 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, 525 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, 526 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, 527 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, 528 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, 529 ICE_TX_DESC_CMD_RE = 0x0400, 530 }; 531 532 #define ICE_TXD_QW1_OFFSET_S 16 533 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) 534 535 enum ice_tx_desc_len_fields { 536 /* Note: These are predefined bit offsets */ 537 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 538 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 539 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 540 }; 541 542 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) 543 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) 544 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) 545 546 /* Tx descriptor field limits in bytes */ 547 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ 548 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) 549 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ 550 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) 551 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ 552 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) 553 554 #define ICE_TXD_QW1_TX_BUF_SZ_S 34 555 #define ICE_TXD_QW1_L2TAG1_S 48 556 557 /* Context descriptors */ 558 struct ice_tx_ctx_desc { 559 __le32 tunneling_params; 560 __le16 l2tag2; 561 __le16 rsvd; 562 __le64 qw1; 563 }; 564 565 #define ICE_TXD_CTX_QW1_CMD_S 4 566 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) 567 568 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 569 #define ICE_TXD_CTX_QW1_TSO_LEN_M \ 570 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) 571 572 #define ICE_TXD_CTX_QW1_MSS_S 50 573 #define ICE_TXD_CTX_MIN_MSS 64 574 575 #define ICE_TXD_CTX_QW1_VSI_S 50 576 #define ICE_TXD_CTX_QW1_VSI_M (0x3FFULL << ICE_TXD_CTX_QW1_VSI_S) 577 578 enum ice_tx_ctx_desc_cmd_bits { 579 ICE_TX_CTX_DESC_TSO = 0x01, 580 ICE_TX_CTX_DESC_TSYN = 0x02, 581 ICE_TX_CTX_DESC_IL2TAG2 = 0x04, 582 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 583 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 584 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 585 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 586 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, 587 ICE_TX_CTX_DESC_RESERVED = 0x40 588 }; 589 590 enum ice_tx_ctx_desc_eipt_offload { 591 ICE_TX_CTX_EIPT_NONE = 0x0, 592 ICE_TX_CTX_EIPT_IPV6 = 0x1, 593 ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2, 594 ICE_TX_CTX_EIPT_IPV4 = 0x3 595 }; 596 597 #define ICE_TXD_CTX_QW0_EIPLEN_S 2 598 599 #define ICE_TXD_CTX_QW0_L4TUNT_S 9 600 601 #define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S) 602 #define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S) 603 604 #define ICE_TXD_CTX_QW0_NATLEN_S 12 605 606 #define ICE_TXD_CTX_QW0_L4T_CS_S 23 607 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) 608 609 #define ICE_LAN_TXQ_MAX_QGRPS 127 610 #define ICE_LAN_TXQ_MAX_QDIS 1023 611 612 /* Tx queue context data 613 * 614 * The sizes of the variables may be larger than needed due to crossing byte 615 * boundaries. If we do not have the width of the variable set to the correct 616 * size then we could end up shifting bits off the top of the variable when the 617 * variable is at the top of a byte and crosses over into the next byte. 618 */ 619 struct ice_tlan_ctx { 620 #define ICE_TLAN_CTX_BASE_S 7 621 u64 base; /* base is defined in 128-byte units */ 622 u8 port_num; 623 u16 cgd_num; /* bigger than needed, see above for reason */ 624 u8 pf_num; 625 u16 vmvf_num; 626 u8 vmvf_type; 627 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0 628 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 629 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 630 u16 src_vsi; 631 u8 tsyn_ena; 632 u8 internal_usage_flag; 633 u8 alt_vlan; 634 u16 cpuid; /* bigger than needed, see above for reason */ 635 u8 wb_mode; 636 u8 tphrd_desc; 637 u8 tphrd; 638 u8 tphwr_desc; 639 u16 cmpq_id; 640 u16 qnum_in_func; 641 u8 itr_notification_mode; 642 u8 adjust_prof_id; 643 u32 qlen; /* bigger than needed, see above for reason */ 644 u8 quanta_prof_idx; 645 u8 tso_ena; 646 u16 tso_qnum; 647 u8 legacy_int; 648 u8 drop_ena; 649 u8 cache_prof_idx; 650 u8 pkt_shaper_prof_idx; 651 u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ 652 }; 653 654 /* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the 655 * hardware to a bit-field that can be used by SW to more easily determine the 656 * packet type. 657 * 658 * Macros are used to shorten the table lines and make this table human 659 * readable. 660 * 661 * We store the PTYPE in the top byte of the bit field - this is just so that 662 * we can check that the table doesn't have a row missing, as the index into 663 * the table should be the PTYPE. 664 * 665 * Typical work flow: 666 * 667 * IF NOT ice_ptype_lkup[ptype].known 668 * THEN 669 * Packet is unknown 670 * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP 671 * Use the rest of the fields to look at the tunnels, inner protocols, etc 672 * ELSE 673 * Use the enum ice_rx_l2_ptype to decode the packet type 674 * ENDIF 675 */ 676 #define ICE_PTYPES \ 677 /* L2 Packet types */ \ 678 ICE_PTT_UNUSED_ENTRY(0), \ 679 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), \ 680 ICE_PTT_UNUSED_ENTRY(2), \ 681 ICE_PTT_UNUSED_ENTRY(3), \ 682 ICE_PTT_UNUSED_ENTRY(4), \ 683 ICE_PTT_UNUSED_ENTRY(5), \ 684 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), \ 685 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), \ 686 ICE_PTT_UNUSED_ENTRY(8), \ 687 ICE_PTT_UNUSED_ENTRY(9), \ 688 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), \ 689 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), \ 690 ICE_PTT_UNUSED_ENTRY(12), \ 691 ICE_PTT_UNUSED_ENTRY(13), \ 692 ICE_PTT_UNUSED_ENTRY(14), \ 693 ICE_PTT_UNUSED_ENTRY(15), \ 694 ICE_PTT_UNUSED_ENTRY(16), \ 695 ICE_PTT_UNUSED_ENTRY(17), \ 696 ICE_PTT_UNUSED_ENTRY(18), \ 697 ICE_PTT_UNUSED_ENTRY(19), \ 698 ICE_PTT_UNUSED_ENTRY(20), \ 699 ICE_PTT_UNUSED_ENTRY(21), \ 700 \ 701 /* Non Tunneled IPv4 */ \ 702 ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), \ 703 ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), \ 704 ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), \ 705 ICE_PTT_UNUSED_ENTRY(25), \ 706 ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), \ 707 ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), \ 708 ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), \ 709 \ 710 /* IPv4 --> IPv4 */ \ 711 ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), \ 712 ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), \ 713 ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), \ 714 ICE_PTT_UNUSED_ENTRY(32), \ 715 ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), \ 716 ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), \ 717 ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), \ 718 \ 719 /* IPv4 --> IPv6 */ \ 720 ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), \ 721 ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), \ 722 ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), \ 723 ICE_PTT_UNUSED_ENTRY(39), \ 724 ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), \ 725 ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), \ 726 ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), \ 727 \ 728 /* IPv4 --> GRE/NAT */ \ 729 ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), \ 730 \ 731 /* IPv4 --> GRE/NAT --> IPv4 */ \ 732 ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), \ 733 ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), \ 734 ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), \ 735 ICE_PTT_UNUSED_ENTRY(47), \ 736 ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), \ 737 ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), \ 738 ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), \ 739 \ 740 /* IPv4 --> GRE/NAT --> IPv6 */ \ 741 ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), \ 742 ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), \ 743 ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), \ 744 ICE_PTT_UNUSED_ENTRY(54), \ 745 ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), \ 746 ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), \ 747 ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), \ 748 \ 749 /* IPv4 --> GRE/NAT --> MAC */ \ 750 ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), \ 751 \ 752 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ \ 753 ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), \ 754 ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), \ 755 ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), \ 756 ICE_PTT_UNUSED_ENTRY(62), \ 757 ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), \ 758 ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), \ 759 ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), \ 760 \ 761 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ \ 762 ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), \ 763 ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), \ 764 ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), \ 765 ICE_PTT_UNUSED_ENTRY(69), \ 766 ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), \ 767 ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), \ 768 ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), \ 769 \ 770 /* IPv4 --> GRE/NAT --> MAC/VLAN */ \ 771 ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), \ 772 \ 773 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ \ 774 ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), \ 775 ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), \ 776 ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), \ 777 ICE_PTT_UNUSED_ENTRY(77), \ 778 ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), \ 779 ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), \ 780 ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), \ 781 \ 782 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ \ 783 ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), \ 784 ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), \ 785 ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), \ 786 ICE_PTT_UNUSED_ENTRY(84), \ 787 ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), \ 788 ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), \ 789 ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), \ 790 \ 791 /* Non Tunneled IPv6 */ \ 792 ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), \ 793 ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), \ 794 ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), \ 795 ICE_PTT_UNUSED_ENTRY(91), \ 796 ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), \ 797 ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), \ 798 ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), \ 799 \ 800 /* IPv6 --> IPv4 */ \ 801 ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), \ 802 ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), \ 803 ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), \ 804 ICE_PTT_UNUSED_ENTRY(98), \ 805 ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), \ 806 ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), \ 807 ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), \ 808 \ 809 /* IPv6 --> IPv6 */ \ 810 ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), \ 811 ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), \ 812 ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), \ 813 ICE_PTT_UNUSED_ENTRY(105), \ 814 ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), \ 815 ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), \ 816 ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), \ 817 \ 818 /* IPv6 --> GRE/NAT */ \ 819 ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), \ 820 \ 821 /* IPv6 --> GRE/NAT -> IPv4 */ \ 822 ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), \ 823 ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), \ 824 ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), \ 825 ICE_PTT_UNUSED_ENTRY(113), \ 826 ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), \ 827 ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), \ 828 ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), \ 829 \ 830 /* IPv6 --> GRE/NAT -> IPv6 */ \ 831 ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), \ 832 ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), \ 833 ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), \ 834 ICE_PTT_UNUSED_ENTRY(120), \ 835 ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), \ 836 ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), \ 837 ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), \ 838 \ 839 /* IPv6 --> GRE/NAT -> MAC */ \ 840 ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), \ 841 \ 842 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ \ 843 ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), \ 844 ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), \ 845 ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), \ 846 ICE_PTT_UNUSED_ENTRY(128), \ 847 ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), \ 848 ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), \ 849 ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), \ 850 \ 851 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ \ 852 ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), \ 853 ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), \ 854 ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), \ 855 ICE_PTT_UNUSED_ENTRY(135), \ 856 ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), \ 857 ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), \ 858 ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), \ 859 \ 860 /* IPv6 --> GRE/NAT -> MAC/VLAN */ \ 861 ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), \ 862 \ 863 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ \ 864 ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), \ 865 ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), \ 866 ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), \ 867 ICE_PTT_UNUSED_ENTRY(143), \ 868 ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), \ 869 ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), \ 870 ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), \ 871 \ 872 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ \ 873 ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), \ 874 ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), \ 875 ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), \ 876 ICE_PTT_UNUSED_ENTRY(150), \ 877 ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), \ 878 ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), \ 879 ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 880 881 #define ICE_NUM_DEFINED_PTYPES 154 882 883 /* macro to make the table lines short, use explicit indexing with [PTYPE] */ 884 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 885 [PTYPE] = { \ 886 1, \ 887 ICE_RX_PTYPE_OUTER_##OUTER_IP, \ 888 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 889 ICE_RX_PTYPE_##OUTER_FRAG, \ 890 ICE_RX_PTYPE_TUNNEL_##T, \ 891 ICE_RX_PTYPE_TUNNEL_END_##TE, \ 892 ICE_RX_PTYPE_##TEF, \ 893 ICE_RX_PTYPE_INNER_PROT_##I, \ 894 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } 895 896 #define ICE_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 897 898 /* shorter macros makes the table fit but are terse */ 899 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG 900 #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG 901 902 /* Lookup table mapping in the 10-bit HW PTYPE to the bit field for decoding */ 903 static const struct ice_rx_ptype_decoded ice_ptype_lkup[BIT(10)] = { 904 ICE_PTYPES 905 906 /* unused entries */ 907 [ICE_NUM_DEFINED_PTYPES ... 1023] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 908 }; 909 910 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) 911 { 912 return ice_ptype_lkup[ptype]; 913 } 914 915 916 #endif /* _ICE_LAN_TX_RX_H_ */ 917