1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 /* Machine-generated file */ 5 6 #ifndef _ICE_HW_AUTOGEN_H_ 7 #define _ICE_HW_AUTOGEN_H_ 8 9 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) 10 #define GLCOMM_QUANTA_PROF_MAX_INDEX 15 11 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S 0 12 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M ICE_M(0x3FFF, 0) 13 #define GLCOMM_QUANTA_PROF_MAX_CMD_S 16 14 #define GLCOMM_QUANTA_PROF_MAX_CMD_M ICE_M(0xFF, 16) 15 #define GLCOMM_QUANTA_PROF_MAX_DESC_S 24 16 #define GLCOMM_QUANTA_PROF_MAX_DESC_M ICE_M(0x3F, 24) 17 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) 18 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) 19 #define QTX_COMM_HEAD_HEAD_S 0 20 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0) 21 #define PF_FW_ARQBAH 0x00080180 22 #define PF_FW_ARQBAL 0x00080080 23 #define PF_FW_ARQH 0x00080380 24 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0) 25 #define PF_FW_ARQLEN 0x00080280 26 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 27 #define PF_FW_ARQLEN_ARQVFE_M BIT(28) 28 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29) 29 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30) 30 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31) 31 #define PF_FW_ARQT 0x00080480 32 #define PF_FW_ATQBAH 0x00080100 33 #define PF_FW_ATQBAL 0x00080000 34 #define PF_FW_ATQH 0x00080300 35 #define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0) 36 #define PF_FW_ATQLEN 0x00080200 37 #define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 38 #define PF_FW_ATQLEN_ATQVFE_M BIT(28) 39 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29) 40 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30) 41 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) 42 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) 43 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31) 44 #define PF_FW_ATQT 0x00080400 45 #define PF_MBX_ARQBAH 0x0022E400 46 #define PF_MBX_ARQBAL 0x0022E380 47 #define PF_MBX_ARQH 0x0022E500 48 #define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0) 49 #define PF_MBX_ARQLEN 0x0022E480 50 #define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 51 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30) 52 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) 53 #define PF_MBX_ARQT 0x0022E580 54 #define PF_MBX_ATQBAH 0x0022E180 55 #define PF_MBX_ATQBAL 0x0022E100 56 #define PF_MBX_ATQH 0x0022E280 57 #define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0) 58 #define PF_MBX_ATQLEN 0x0022E200 59 #define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 60 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30) 61 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) 62 #define PF_MBX_ATQT 0x0022E300 63 #define PF_SB_ARQBAH 0x0022FF00 64 #define PF_SB_ARQBAH_ARQBAH_S 0 65 #define PF_SB_ARQBAH_ARQBAH_M ICE_M(0xFFFFFFFF, 0) 66 #define PF_SB_ARQBAL 0x0022FE80 67 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0 68 #define PF_SB_ARQBAL_ARQBAL_LSB_M ICE_M(0x3F, 0) 69 #define PF_SB_ARQBAL_ARQBAL_S 6 70 #define PF_SB_ARQBAL_ARQBAL_M ICE_M(0x3FFFFFF, 6) 71 #define PF_SB_ARQH 0x00230000 72 #define PF_SB_ARQH_ARQH_S 0 73 #define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0) 74 #define PF_SB_ARQLEN 0x0022FF80 75 #define PF_SB_ARQLEN_ARQLEN_S 0 76 #define PF_SB_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 77 #define PF_SB_ARQLEN_ARQVFE_S 28 78 #define PF_SB_ARQLEN_ARQVFE_M BIT(28) 79 #define PF_SB_ARQLEN_ARQOVFL_S 29 80 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29) 81 #define PF_SB_ARQLEN_ARQCRIT_S 30 82 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30) 83 #define PF_SB_ARQLEN_ARQENABLE_S 31 84 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31) 85 #define PF_SB_ARQT 0x00230080 86 #define PF_SB_ARQT_ARQT_S 0 87 #define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0) 88 #define PF_SB_ATQBAH 0x0022FC80 89 #define PF_SB_ATQBAH_ATQBAH_S 0 90 #define PF_SB_ATQBAH_ATQBAH_M ICE_M(0xFFFFFFFF, 0) 91 #define PF_SB_ATQBAL 0x0022FC00 92 #define PF_SB_ATQBAL_ATQBAL_S 6 93 #define PF_SB_ATQBAL_ATQBAL_M ICE_M(0x3FFFFFF, 6) 94 #define PF_SB_ATQH 0x0022FD80 95 #define PF_SB_ATQH_ATQH_S 0 96 #define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0) 97 #define PF_SB_ATQLEN 0x0022FD00 98 #define PF_SB_ATQLEN_ATQLEN_S 0 99 #define PF_SB_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 100 #define PF_SB_ATQLEN_ATQVFE_S 28 101 #define PF_SB_ATQLEN_ATQVFE_M BIT(28) 102 #define PF_SB_ATQLEN_ATQOVFL_S 29 103 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29) 104 #define PF_SB_ATQLEN_ATQCRIT_S 30 105 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30) 106 #define PF_SB_ATQLEN_ATQENABLE_S 31 107 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31) 108 #define PF_SB_ATQT 0x0022FE00 109 #define PF_SB_ATQT_ATQT_S 0 110 #define PF_SB_ATQT_ATQT_M ICE_M(0x3FF, 0) 111 #define PF_SB_REM_DEV_CTL 0x002300F0 112 #define PRTDCB_GENC 0x00083000 113 #define PRTDCB_GENC_PFCLDA_S 16 114 #define PRTDCB_GENC_PFCLDA_M ICE_M(0xFFFF, 16) 115 #define PRTDCB_GENS 0x00083020 116 #define PRTDCB_GENS_DCBX_STATUS_S 0 117 #define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0) 118 #define PRTDCB_TUP2TC 0x001D26C0 119 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) 120 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) 121 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) 122 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0 123 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, 0) 124 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4)) 125 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0 126 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0) 127 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30 128 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30) 129 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4)) 130 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0 131 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0) 132 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30 133 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30) 134 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4)) 135 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0 136 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0) 137 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30 138 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30) 139 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4)) 140 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0 141 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0) 142 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30 143 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30) 144 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) 145 #define QRXFLXP_CNTXT_RXDID_IDX_S 0 146 #define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0) 147 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8 148 #define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8) 149 #define QRXFLXP_CNTXT_TS_M BIT(11) 150 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4 151 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M ICE_M(0x3, 4) 152 #define GLGEN_CLKSTAT_SRC 0x000B826C 153 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) 154 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4) 155 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8 156 #define GLGEN_GPIO_CTL_PIN_FUNC_M ICE_M(0xF, 8) 157 #define GLGEN_RSTAT 0x000B8188 158 #define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0) 159 #define GLGEN_RSTCTL 0x000B8180 160 #define GLGEN_RSTCTL_GRSTDEL_S 0 161 #define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S) 162 #define GLGEN_RSTAT_RESET_TYPE_S 2 163 #define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2) 164 #define GLGEN_RTRIG 0x000B8190 165 #define GLGEN_RTRIG_CORER_M BIT(0) 166 #define GLGEN_RTRIG_GLOBR_M BIT(1) 167 #define GLGEN_STAT 0x000B612C 168 #define GLGEN_SWITCH_MODE_CONFIG 0x000B81E0 169 #define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M BIT(2) 170 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) 171 #define PFGEN_CTRL 0x00091000 172 #define PFGEN_CTRL_PFSWR_M BIT(0) 173 #define PFGEN_STATE 0x00088000 174 #define PRTGEN_STATUS 0x000B8100 175 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) 176 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) 177 #define VPGEN_VFRSTAT_VFRD_M BIT(0) 178 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) 179 #define VPGEN_VFRTRIG_VFSWR_M BIT(0) 180 #define GLINT_CTL 0x0016CC54 181 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0) 182 #define GLINT_CTL_ITR_GRAN_200_S 16 183 #define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16) 184 #define GLINT_CTL_ITR_GRAN_100_S 20 185 #define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20) 186 #define GLINT_CTL_ITR_GRAN_50_S 24 187 #define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24) 188 #define GLINT_CTL_ITR_GRAN_25_S 28 189 #define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28) 190 #define GLGEN_MAC_LINK_TOPO 0x000B81DC 191 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M GENMASK(1, 0) 192 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) 193 #define GLINT_DYN_CTL_INTENA_M BIT(0) 194 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1) 195 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) 196 #define GLINT_DYN_CTL_ITR_INDX_S 3 197 #define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3) 198 #define GLINT_DYN_CTL_INTERVAL_S 5 199 #define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5) 200 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) 201 #define GLINT_DYN_CTL_SW_ITR_INDX_S 25 202 #define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25) 203 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) 204 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) 205 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) 206 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) 207 #define GLINT_RATE_INTRL_ENA_M BIT(6) 208 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) 209 #define GLINT_VECT2FUNC_VF_NUM_S 0 210 #define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0) 211 #define GLINT_VECT2FUNC_PF_NUM_S 12 212 #define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12) 213 #define GLINT_VECT2FUNC_IS_PF_S 16 214 #define GLINT_VECT2FUNC_IS_PF_M BIT(16) 215 #define PFINT_ALLOC 0x001D2600 216 #define PFINT_ALLOC_FIRST ICE_M(0x7FF, 0) 217 #define PFINT_FW_CTL 0x0016C800 218 #define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 219 #define PFINT_FW_CTL_ITR_INDX_S 11 220 #define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11) 221 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) 222 #define PFINT_MBX_CTL 0x0016B280 223 #define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 224 #define PFINT_MBX_CTL_ITR_INDX_S 11 225 #define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11) 226 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) 227 #define PFINT_OICR 0x0016CA00 228 #define PFINT_OICR_TSYN_TX_M BIT(11) 229 #define PFINT_OICR_TSYN_EVNT_M BIT(12) 230 #define PFINT_OICR_ECC_ERR_M BIT(16) 231 #define PFINT_OICR_MAL_DETECT_M BIT(19) 232 #define PFINT_OICR_GRST_M BIT(20) 233 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21) 234 #define PFINT_OICR_HMC_ERR_M BIT(26) 235 #define PFINT_OICR_PE_PUSH_M BIT(27) 236 #define PFINT_OICR_PE_CRITERR_M BIT(28) 237 #define PFINT_OICR_VFLR_M BIT(29) 238 #define PFINT_OICR_SWINT_M BIT(31) 239 #define PFINT_OICR_CTL 0x0016CA80 240 #define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 241 #define PFINT_OICR_CTL_ITR_INDX_S 11 242 #define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11) 243 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) 244 #define PFINT_OICR_ENA 0x0016C900 245 #define PFINT_SB_CTL 0x0016B600 246 #define PFINT_SB_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 247 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30) 248 #define PFINT_TSYN_MSK 0x0016C980 249 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) 250 #define QINT_RQCTL_MSIX_INDX_S 0 251 #define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 252 #define QINT_RQCTL_ITR_INDX_S 11 253 #define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11) 254 #define QINT_RQCTL_CAUSE_ENA_M BIT(30) 255 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) 256 #define QINT_TQCTL_MSIX_INDX_S 0 257 #define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 258 #define QINT_TQCTL_ITR_INDX_S 11 259 #define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11) 260 #define QINT_TQCTL_CAUSE_ENA_M BIT(30) 261 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) 262 #define VPINT_ALLOC_FIRST_S 0 263 #define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0) 264 #define VPINT_ALLOC_LAST_S 12 265 #define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12) 266 #define VPINT_ALLOC_VALID_M BIT(31) 267 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) 268 #define VPINT_ALLOC_PCI_FIRST_S 0 269 #define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0) 270 #define VPINT_ALLOC_PCI_LAST_S 12 271 #define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12) 272 #define VPINT_ALLOC_PCI_VALID_M BIT(31) 273 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) 274 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) 275 #define GLLAN_RCTL_0 0x002941F8 276 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) 277 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) 278 #define QRX_CTRL_MAX_INDEX 2047 279 #define QRX_CTRL_QENA_REQ_S 0 280 #define QRX_CTRL_QENA_REQ_M BIT(0) 281 #define QRX_CTRL_QENA_STAT_S 2 282 #define QRX_CTRL_QENA_STAT_M BIT(2) 283 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) 284 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) 285 #define QRX_TAIL_MAX_INDEX 2047 286 #define QRX_TAIL_TAIL_S 0 287 #define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0) 288 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) 289 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0 290 #define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0) 291 #define VPLAN_RX_QBASE_VFNUMQ_S 16 292 #define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 293 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) 294 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) 295 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) 296 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0 297 #define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0) 298 #define VPLAN_TX_QBASE_VFNUMQ_S 16 299 #define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 300 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) 301 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) 302 #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT(_i) (0x001E36E0 + ((_i) * 32)) 303 #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 8 304 #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M GENMASK(15, 0) 305 #define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR(_i) (0x001E3800 + ((_i) * 32)) 306 #define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M GENMASK(15, 0) 307 #define GL_MDCK_TX_TDPU 0x00049348 308 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1) 309 #define GL_MDET_RX 0x00294C00 310 #define GL_MDET_RX_QNUM_S 0 311 #define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0) 312 #define GL_MDET_RX_VF_NUM_S 15 313 #define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15) 314 #define GL_MDET_RX_PF_NUM_S 23 315 #define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23) 316 #define GL_MDET_RX_MAL_TYPE_S 26 317 #define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26) 318 #define GL_MDET_RX_VALID_M BIT(31) 319 #define GL_MDET_TX_PQM 0x002D2E00 320 #define GL_MDET_TX_PQM_PF_NUM_S 0 321 #define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0) 322 #define GL_MDET_TX_PQM_VF_NUM_S 4 323 #define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4) 324 #define GL_MDET_TX_PQM_QNUM_S 12 325 #define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12) 326 #define GL_MDET_TX_PQM_MAL_TYPE_S 26 327 #define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26) 328 #define GL_MDET_TX_PQM_VALID_M BIT(31) 329 #define GL_MDET_TX_TCLAN_BY_MAC(hw) \ 330 ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \ 331 E800_GL_MDET_TX_TCLAN) 332 #define E800_GL_MDET_TX_TCLAN 0x000FC068 333 #define E830_GL_MDET_TX_TCLAN 0x000FCCC0 334 #define GL_MDET_TX_TCLAN_QNUM_S 0 335 #define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0) 336 #define GL_MDET_TX_TCLAN_VF_NUM_S 15 337 #define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15) 338 #define GL_MDET_TX_TCLAN_PF_NUM_S 23 339 #define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23) 340 #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26 341 #define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26) 342 #define GL_MDET_TX_TCLAN_VALID_M BIT(31) 343 #define PF_MDET_RX 0x00294280 344 #define PF_MDET_RX_VALID_M BIT(0) 345 #define PF_MDET_TX_PQM 0x002D2C80 346 #define PF_MDET_TX_PQM_VALID_M BIT(0) 347 #define PF_MDET_TX_TCLAN_BY_MAC(hw) \ 348 ((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \ 349 E800_PF_MDET_TX_TCLAN) 350 #define E800_PF_MDET_TX_TCLAN 0x000FC000 351 #define E830_PF_MDET_TX_TCLAN 0x000FCC00 352 #define PF_MDET_TX_TCLAN_VALID_M BIT(0) 353 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) 354 #define VP_MDET_RX_VALID_M BIT(0) 355 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) 356 #define VP_MDET_TX_PQM_VALID_M BIT(0) 357 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) 358 #define VP_MDET_TX_TCLAN_VALID_M BIT(0) 359 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) 360 #define VP_MDET_TX_TDPU_VALID_M BIT(0) 361 #define E800_GL_MNG_FWSM_FW_MODES_M GENMASK(2, 0) 362 #define E830_GL_MNG_FWSM_FW_MODES_M GENMASK(1, 0) 363 #define GL_MNG_FWSM 0x000B6134 364 #define GL_MNG_FWSM_FW_LOADING_M BIT(30) 365 #define GLNVM_FLA 0x000B6108 366 #define GLNVM_FLA_LOCKED_M BIT(6) 367 #define GLNVM_GENS 0x000B6100 368 #define GLNVM_GENS_SR_SIZE_S 5 369 #define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5) 370 #define GLNVM_ULD 0x000B6008 371 #define GLNVM_ULD_PCIER_DONE_M BIT(0) 372 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1) 373 #define GLNVM_ULD_CORER_DONE_M BIT(3) 374 #define GLNVM_ULD_GLOBR_DONE_M BIT(4) 375 #define GLNVM_ULD_POR_DONE_M BIT(5) 376 #define GLNVM_ULD_POR_DONE_1_M BIT(8) 377 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9) 378 #define GLNVM_ULD_PE_DONE_M BIT(10) 379 #define GLPCI_CNF2 0x000BE004 380 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) 381 #define PF_FUNC_RID 0x0009E880 382 #define PF_FUNC_RID_FUNC_NUM_S 0 383 #define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0) 384 #define PF_PCI_CIAA 0x0009E580 385 #define PF_PCI_CIAA_VF_NUM_S 12 386 #define PF_PCI_CIAD 0x0009E500 387 #define GL_PWR_MODE_CTL 0x000B820C 388 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30 389 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30) 390 #define GLQF_FD_CNT 0x00460018 391 #define E800_GLQF_FD_CNT_FD_GCNT_M GENMASK(14, 0) 392 #define E830_GLQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) 393 #define GLQF_FD_CNT_FD_BCNT_S 16 394 #define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16) 395 #define E830_GLQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) 396 #define GLQF_FD_SIZE 0x00460010 397 #define GLQF_FD_SIZE_FD_GSIZE_S 0 398 #define E800_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(14, 0) 399 #define E830_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(15, 0) 400 #define GLQF_FD_SIZE_FD_BSIZE_S 16 401 #define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16) 402 #define E830_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(31, 16) 403 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) 404 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) 405 #define GLQF_FDMASK_MAX_INDEX 31 406 #define GLQF_FDMASK_MSK_INDEX_S 0 407 #define GLQF_FDMASK_MSK_INDEX_M ICE_M(0x1F, 0) 408 #define GLQF_FDMASK_MASK_S 16 409 #define GLQF_FDMASK_MASK_M ICE_M(0xFFFF, 16) 410 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) 411 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) 412 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) 413 #define GLQF_HMASK_MAX_INDEX 31 414 #define GLQF_HMASK_MSK_INDEX_S 0 415 #define GLQF_HMASK_MSK_INDEX_M ICE_M(0x1F, 0) 416 #define GLQF_HMASK_MASK_S 16 417 #define GLQF_HMASK_MASK_M ICE_M(0xFFFF, 16) 418 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) 419 #define GLQF_HMASK_SEL_MAX_INDEX 127 420 #define GLQF_HMASK_SEL_MASK_SEL_S 0 421 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512)) 422 #define GLQF_HSYMM_REG_SIZE 4 423 #define GLQF_HSYMM_REG_PER_PROF 6 424 #define GLQF_HSYMM_ENABLE_BIT BIT(7) 425 #define E800_PFQF_FD_CNT_FD_GCNT_M GENMASK(14, 0) 426 #define E830_PFQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) 427 #define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16) 428 #define E830_PFQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) 429 #define PFQF_FD_ENA 0x0043A000 430 #define PFQF_FD_ENA_FD_ENA_M BIT(0) 431 #define PFQF_FD_SIZE 0x00460100 432 #define GLDCB_RTCTQ_RXQNUM_S 0 433 #define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0) 434 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) 435 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) 436 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) 437 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) 438 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) 439 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) 440 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) 441 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) 442 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) 443 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) 444 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) 445 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) 446 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) 447 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) 448 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) 449 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) 450 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) 451 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) 452 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) 453 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) 454 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) 455 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) 456 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) 457 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) 458 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) 459 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) 460 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) 461 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) 462 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) 463 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) 464 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) 465 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) 466 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) 467 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) 468 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) 469 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) 470 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) 471 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) 472 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) 473 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) 474 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) 475 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) 476 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) 477 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) 478 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) 479 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) 480 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) 481 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) 482 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) 483 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) 484 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) 485 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) 486 #define PRTRPB_RDPC 0x000AC260 487 #define GLHH_ART_CTL 0x000A41D4 488 #define GLHH_ART_CTL_ACTIVE_M BIT(0) 489 #define GLHH_ART_TIME_H 0x000A41D8 490 #define GLHH_ART_TIME_L 0x000A41DC 491 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) 492 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4) 493 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) 494 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0) 495 #define GLTSYN_AUX_OUT_0_OUTMOD_M ICE_M(0x3, 1) 496 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) 497 #define GLTSYN_CMD 0x00088810 498 #define GLTSYN_CMD_SYNC 0x00088814 499 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) 500 #define GLTSYN_ENA_TSYN_ENA_M BIT(0) 501 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) 502 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) 503 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) 504 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) 505 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) 506 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) 507 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) 508 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) 509 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) 510 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) 511 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) 512 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) 513 #define GLTSYN_STAT_EVENT0_M BIT(0) 514 #define GLTSYN_STAT_EVENT1_M BIT(1) 515 #define GLTSYN_STAT_EVENT2_M BIT(2) 516 #define GLTSYN_SYNC_DLAY 0x00088818 517 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) 518 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) 519 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) 520 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) 521 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) 522 #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */ 523 #define PFHH_SEM_BUSY_M BIT(0) 524 #define PFTSYN_SEM 0x00088880 525 #define PFTSYN_SEM_BUSY_M BIT(0) 526 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) 527 #define VSIQF_FD_CNT_FD_GCNT_S 0 528 #define E800_VSIQF_FD_CNT_FD_GCNT_M GENMASK(13, 0) 529 #define E830_VSIQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) 530 #define VSIQF_FD_CNT_FD_BCNT_S 16 531 #define E800_VSIQF_FD_CNT_FD_BCNT_M GENMASK(29, 16) 532 #define E830_VSIQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) 533 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) 534 #define VSIQF_HKEY_MAX_INDEX 12 535 #define PFPM_APM 0x000B8080 536 #define PFPM_APM_APME_M BIT(0) 537 #define PFPM_WUFC 0x0009DC00 538 #define PFPM_WUFC_MAG_M BIT(1) 539 #define PFPM_WUS 0x0009DB80 540 #define PFPM_WUS_LNKC_M BIT(0) 541 #define PFPM_WUS_MAG_M BIT(1) 542 #define PFPM_WUS_MNG_M BIT(3) 543 #define PFPM_WUS_FW_RST_WK_M BIT(31) 544 #define E830_PRTMAC_CL01_PS_QNT 0x001E32A0 545 #define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0) 546 #define E830_PRTMAC_CL01_QNT_THR 0x001E3320 547 #define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0) 548 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) 549 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) 550 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000 551 #define E830_MBX_VF_DEC_TRIG(_VF) (0x00233800 + (_VF) * 4) 552 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + (_VF) * 4) 553 554 #endif /* _ICE_HW_AUTOGEN_H_ */ 555