1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #ifndef _ICE_ETHTOOL_H_ 5 #define _ICE_ETHTOOL_H_ 6 7 struct ice_phy_type_to_ethtool { 8 u64 aq_link_speed; 9 u8 link_mode; 10 }; 11 12 struct ice_serdes_equalization_to_ethtool { 13 int rx_equ_pre2; 14 int rx_equ_pre1; 15 int rx_equ_post1; 16 int rx_equ_bflf; 17 int rx_equ_bfhf; 18 int rx_equ_drate; 19 int rx_equ_ctle_gainhf; 20 int rx_equ_ctle_gainlf; 21 int rx_equ_ctle_gaindc; 22 int rx_equ_ctle_bw; 23 int rx_equ_dfe_gain; 24 int rx_equ_dfe_gain_2; 25 int rx_equ_dfe_2; 26 int rx_equ_dfe_3; 27 int rx_equ_dfe_4; 28 int rx_equ_dfe_5; 29 int rx_equ_dfe_6; 30 int rx_equ_dfe_7; 31 int rx_equ_dfe_8; 32 int rx_equ_dfe_9; 33 int rx_equ_dfe_10; 34 int rx_equ_dfe_11; 35 int rx_equ_dfe_12; 36 int tx_equ_pre1; 37 int tx_equ_pre3; 38 int tx_equ_atten; 39 int tx_equ_post1; 40 int tx_equ_pre2; 41 }; 42 43 struct ice_regdump_to_ethtool { 44 /* A multilane port can have max 4 serdes */ 45 struct ice_serdes_equalization_to_ethtool equalization[4]; 46 }; 47 48 /* Port topology from lport i.e. 49 * serdes mapping, pcsquad, macport, cage etc... 50 */ 51 struct ice_port_topology { 52 u16 pcs_port; 53 u16 primary_serdes_lane; 54 u16 serdes_lane_count; 55 u16 pcs_quad_select; 56 }; 57 58 /* Macro to make PHY type to Ethtool link mode table entry. 59 * The index is the PHY type. 60 */ 61 #define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\ 62 .aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \ 63 .link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \ 64 } 65 66 /* Lookup table mapping PHY type low to link speed and Ethtool link modes. 67 * Array index corresponds to HW PHY type bit, see 68 * ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*. 69 */ 70 static const struct ice_phy_type_to_ethtool 71 phy_type_low_lkup[] = { 72 [0] = ICE_PHY_TYPE(100MB, 100baseT_Full), 73 [1] = ICE_PHY_TYPE(100MB, 100baseT_Full), 74 [2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full), 75 [3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full), 76 [4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full), 77 [5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full), 78 [6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full), 79 [7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full), 80 [8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full), 81 [9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full), 82 [10] = ICE_PHY_TYPE(5GB, 5000baseT_Full), 83 [11] = ICE_PHY_TYPE(5GB, 5000baseT_Full), 84 [12] = ICE_PHY_TYPE(10GB, 10000baseT_Full), 85 [13] = ICE_PHY_TYPE(10GB, 10000baseCR_Full), 86 [14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full), 87 [15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full), 88 [16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full), 89 [17] = ICE_PHY_TYPE(10GB, 10000baseCR_Full), 90 [18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full), 91 [19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 92 [20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 93 [21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 94 [22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 95 [23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 96 [24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 97 [25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 98 [26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 99 [27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 100 [28] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 101 [29] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 102 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full), 103 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full), 104 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full), 105 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full), 106 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full), 107 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full), 108 [36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 109 [37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 110 [38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 111 [39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full), 112 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 113 [41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 114 [42] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 115 [43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 116 [44] = ICE_PHY_TYPE(50GB, 50000baseCR_Full), 117 [45] = ICE_PHY_TYPE(50GB, 50000baseSR_Full), 118 [46] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full), 119 [47] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full), 120 [48] = ICE_PHY_TYPE(50GB, 50000baseKR_Full), 121 [49] = ICE_PHY_TYPE(50GB, 50000baseSR_Full), 122 [50] = ICE_PHY_TYPE(50GB, 50000baseCR_Full), 123 [51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 124 [52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full), 125 [53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full), 126 [54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full), 127 [55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 128 [56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 129 [57] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full), 130 [58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 131 [59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 132 [60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full), 133 [61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 134 [62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 135 [63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full), 136 }; 137 138 /* Lookup table mapping PHY type high to link speed and Ethtool link modes. 139 * Array index corresponds to HW PHY type bit, see 140 * ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_* 141 */ 142 static const struct ice_phy_type_to_ethtool 143 phy_type_high_lkup[] = { 144 [0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full), 145 [1] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 146 [2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 147 [3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 148 [4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 149 [5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full), 150 [6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full), 151 [7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full), 152 [8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full), 153 [9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full), 154 [10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full), 155 [11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full), 156 [12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full), 157 }; 158 159 #endif /* !_ICE_ETHTOOL_H_ */ 160