1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2022, Intel Corporation. */ 3 4 #ifndef _ICE_DPLL_H_ 5 #define _ICE_DPLL_H_ 6 7 #include "ice.h" 8 9 #define ICE_DPLL_PRIO_MAX 0xF 10 #define ICE_DPLL_RCLK_NUM_MAX 4 11 12 /** ice_dpll_pin - store info about pins 13 * @pin: dpll pin structure 14 * @pf: pointer to pf, which has registered the dpll_pin 15 * @idx: ice pin private idx 16 * @num_parents: hols number of parent pins 17 * @parent_idx: hold indexes of parent pins 18 * @flags: pin flags returned from HW 19 * @state: state of a pin 20 * @prop: pin properties 21 * @freq: current frequency of a pin 22 */ 23 struct ice_dpll_pin { 24 struct dpll_pin *pin; 25 struct ice_pf *pf; 26 u8 idx; 27 u8 num_parents; 28 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; 29 u8 flags[ICE_DPLL_RCLK_NUM_MAX]; 30 u8 state[ICE_DPLL_RCLK_NUM_MAX]; 31 struct dpll_pin_properties prop; 32 u32 freq; 33 }; 34 35 /** ice_dpll - store info required for DPLL control 36 * @dpll: pointer to dpll dev 37 * @pf: pointer to pf, which has registered the dpll_device 38 * @dpll_idx: index of dpll on the NIC 39 * @input_idx: currently selected input index 40 * @prev_input_idx: previously selected input index 41 * @ref_state: state of dpll reference signals 42 * @eec_mode: eec_mode dpll is configured for 43 * @phase_shift: phase shift delay of a dpll 44 * @input_prio: priorities of each input 45 * @dpll_state: current dpll sync state 46 * @prev_dpll_state: last dpll sync state 47 * @active_input: pointer to active input pin 48 * @prev_input: pointer to previous active input pin 49 */ 50 struct ice_dpll { 51 struct dpll_device *dpll; 52 struct ice_pf *pf; 53 u8 dpll_idx; 54 u8 input_idx; 55 u8 prev_input_idx; 56 u8 ref_state; 57 u8 eec_mode; 58 s64 phase_shift; 59 u8 *input_prio; 60 enum dpll_lock_status dpll_state; 61 enum dpll_lock_status prev_dpll_state; 62 enum dpll_mode mode; 63 struct dpll_pin *active_input; 64 struct dpll_pin *prev_input; 65 }; 66 67 /** ice_dplls - store info required for CCU (clock controlling unit) 68 * @kworker: periodic worker 69 * @work: periodic work 70 * @lock: locks access to configuration of a dpll 71 * @eec: pointer to EEC dpll dev 72 * @pps: pointer to PPS dpll dev 73 * @inputs: input pins pointer 74 * @outputs: output pins pointer 75 * @rclk: recovered pins pointer 76 * @num_inputs: number of input pins available on dpll 77 * @num_outputs: number of output pins available on dpll 78 * @cgu_state_acq_err_num: number of errors returned during periodic work 79 * @base_rclk_idx: idx of first pin used for clock revocery pins 80 * @clock_id: clock_id of dplls 81 */ 82 struct ice_dplls { 83 struct kthread_worker *kworker; 84 struct kthread_delayed_work work; 85 struct mutex lock; 86 struct ice_dpll eec; 87 struct ice_dpll pps; 88 struct ice_dpll_pin *inputs; 89 struct ice_dpll_pin *outputs; 90 struct ice_dpll_pin rclk; 91 u8 num_inputs; 92 u8 num_outputs; 93 int cgu_state_acq_err_num; 94 u8 base_rclk_idx; 95 u64 clock_id; 96 s32 input_phase_adj_max; 97 s32 output_phase_adj_max; 98 }; 99 100 void ice_dpll_init(struct ice_pf *pf); 101 102 void ice_dpll_deinit(struct ice_pf *pf); 103 104 #endif 105