1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2022, Intel Corporation. */ 3 4 #ifndef _ICE_DPLL_H_ 5 #define _ICE_DPLL_H_ 6 7 #include "ice.h" 8 9 #define ICE_DPLL_RCLK_NUM_MAX 4 10 11 /** ice_dpll_pin - store info about pins 12 * @pin: dpll pin structure 13 * @pf: pointer to pf, which has registered the dpll_pin 14 * @idx: ice pin private idx 15 * @num_parents: hols number of parent pins 16 * @parent_idx: hold indexes of parent pins 17 * @flags: pin flags returned from HW 18 * @state: state of a pin 19 * @prop: pin properties 20 * @freq: current frequency of a pin 21 * @phase_adjust: current phase adjust value 22 */ 23 struct ice_dpll_pin { 24 struct dpll_pin *pin; 25 struct ice_pf *pf; 26 u8 idx; 27 u8 num_parents; 28 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; 29 u8 flags[ICE_DPLL_RCLK_NUM_MAX]; 30 u8 state[ICE_DPLL_RCLK_NUM_MAX]; 31 struct dpll_pin_properties prop; 32 u32 freq; 33 s32 phase_adjust; 34 }; 35 36 /** ice_dpll - store info required for DPLL control 37 * @dpll: pointer to dpll dev 38 * @pf: pointer to pf, which has registered the dpll_device 39 * @dpll_idx: index of dpll on the NIC 40 * @input_idx: currently selected input index 41 * @prev_input_idx: previously selected input index 42 * @ref_state: state of dpll reference signals 43 * @eec_mode: eec_mode dpll is configured for 44 * @phase_offset: phase offset of active pin vs dpll signal 45 * @prev_phase_offset: previous phase offset of active pin vs dpll signal 46 * @input_prio: priorities of each input 47 * @dpll_state: current dpll sync state 48 * @prev_dpll_state: last dpll sync state 49 * @active_input: pointer to active input pin 50 * @prev_input: pointer to previous active input pin 51 */ 52 struct ice_dpll { 53 struct dpll_device *dpll; 54 struct ice_pf *pf; 55 u8 dpll_idx; 56 u8 input_idx; 57 u8 prev_input_idx; 58 u8 ref_state; 59 u8 eec_mode; 60 s64 phase_offset; 61 s64 prev_phase_offset; 62 u8 *input_prio; 63 enum dpll_lock_status dpll_state; 64 enum dpll_lock_status prev_dpll_state; 65 enum dpll_mode mode; 66 struct dpll_pin *active_input; 67 struct dpll_pin *prev_input; 68 }; 69 70 /** ice_dplls - store info required for CCU (clock controlling unit) 71 * @kworker: periodic worker 72 * @work: periodic work 73 * @lock: locks access to configuration of a dpll 74 * @eec: pointer to EEC dpll dev 75 * @pps: pointer to PPS dpll dev 76 * @inputs: input pins pointer 77 * @outputs: output pins pointer 78 * @rclk: recovered pins pointer 79 * @num_inputs: number of input pins available on dpll 80 * @num_outputs: number of output pins available on dpll 81 * @cgu_state_acq_err_num: number of errors returned during periodic work 82 * @base_rclk_idx: idx of first pin used for clock revocery pins 83 * @clock_id: clock_id of dplls 84 * @input_phase_adj_max: max phase adjust value for an input pins 85 * @output_phase_adj_max: max phase adjust value for an output pins 86 */ 87 struct ice_dplls { 88 struct kthread_worker *kworker; 89 struct kthread_delayed_work work; 90 struct mutex lock; 91 struct ice_dpll eec; 92 struct ice_dpll pps; 93 struct ice_dpll_pin *inputs; 94 struct ice_dpll_pin *outputs; 95 struct ice_dpll_pin rclk; 96 u8 num_inputs; 97 u8 num_outputs; 98 int cgu_state_acq_err_num; 99 u8 base_rclk_idx; 100 u64 clock_id; 101 s32 input_phase_adj_max; 102 s32 output_phase_adj_max; 103 }; 104 105 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) 106 void ice_dpll_init(struct ice_pf *pf); 107 void ice_dpll_deinit(struct ice_pf *pf); 108 #else 109 static inline void ice_dpll_init(struct ice_pf *pf) { } 110 static inline void ice_dpll_deinit(struct ice_pf *pf) { } 111 #endif 112 113 #endif 114