1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2022, Intel Corporation. */ 3 4 #ifndef _ICE_DPLL_H_ 5 #define _ICE_DPLL_H_ 6 7 #include "ice.h" 8 9 #define ICE_DPLL_RCLK_NUM_MAX 4 10 11 /** 12 * enum ice_dpll_pin_sw - enumerate ice software pin indices: 13 * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin 14 * @ICE_DPLL_PIN_SW_2_IDX: index of second SW pin 15 * @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair 16 */ 17 enum ice_dpll_pin_sw { 18 ICE_DPLL_PIN_SW_1_IDX, 19 ICE_DPLL_PIN_SW_2_IDX, 20 ICE_DPLL_PIN_SW_NUM 21 }; 22 23 struct ice_dpll_pin_work { 24 struct work_struct work; 25 unsigned long action; 26 struct ice_dpll_pin *pin; 27 }; 28 29 /** ice_dpll_pin - store info about pins 30 * @pin: dpll pin structure 31 * @pf: pointer to pf, which has registered the dpll_pin 32 * @tracker: reference count tracker 33 * @idx: ice pin private idx 34 * @num_parents: hols number of parent pins 35 * @parent_idx: hold indexes of parent pins 36 * @flags: pin flags returned from HW 37 * @state: state of a pin 38 * @prop: pin properties 39 * @freq: current frequency of a pin 40 * @phase_adjust: current phase adjust value 41 * @phase_offset: monitored phase offset value 42 * @ref_sync: store id of reference sync pin 43 */ 44 struct ice_dpll_pin { 45 struct dpll_pin *pin; 46 struct ice_pf *pf; 47 dpll_tracker tracker; 48 struct fwnode_handle *fwnode; 49 struct notifier_block nb; 50 u8 idx; 51 u8 num_parents; 52 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; 53 u8 flags[ICE_DPLL_RCLK_NUM_MAX]; 54 u8 state[ICE_DPLL_RCLK_NUM_MAX]; 55 struct dpll_pin_properties prop; 56 u32 freq; 57 s32 phase_adjust; 58 struct ice_dpll_pin *input; 59 struct ice_dpll_pin *output; 60 enum dpll_pin_direction direction; 61 s64 phase_offset; 62 u8 status; 63 u8 ref_sync; 64 bool active; 65 bool hidden; 66 }; 67 68 /** ice_dpll - store info required for DPLL control 69 * @dpll: pointer to dpll dev 70 * @pf: pointer to pf, which has registered the dpll_device 71 * @tracker: reference count tracker 72 * @dpll_idx: index of dpll on the NIC 73 * @input_idx: currently selected input index 74 * @prev_input_idx: previously selected input index 75 * @ref_state: state of dpll reference signals 76 * @eec_mode: eec_mode dpll is configured for 77 * @phase_offset: phase offset of active pin vs dpll signal 78 * @prev_phase_offset: previous phase offset of active pin vs dpll signal 79 * @input_prio: priorities of each input 80 * @dpll_state: current dpll sync state 81 * @prev_dpll_state: last dpll sync state 82 * @phase_offset_monitor_period: period for phase offset monitor read frequency 83 * @active_input: pointer to active input pin 84 * @prev_input: pointer to previous active input pin 85 * @ops: holds the registered ops 86 */ 87 struct ice_dpll { 88 struct dpll_device *dpll; 89 struct ice_pf *pf; 90 dpll_tracker tracker; 91 u8 dpll_idx; 92 u8 input_idx; 93 u8 prev_input_idx; 94 u8 ref_state; 95 u8 eec_mode; 96 s64 phase_offset; 97 s64 prev_phase_offset; 98 u8 *input_prio; 99 enum dpll_lock_status dpll_state; 100 enum dpll_lock_status prev_dpll_state; 101 enum dpll_mode mode; 102 u32 phase_offset_monitor_period; 103 struct dpll_pin *active_input; 104 struct dpll_pin *prev_input; 105 const struct dpll_device_ops *ops; 106 }; 107 108 /** ice_dplls - store info required for CCU (clock controlling unit) 109 * @kworker: periodic worker 110 * @work: periodic work 111 * @lock: locks access to configuration of a dpll 112 * @eec: pointer to EEC dpll dev 113 * @pps: pointer to PPS dpll dev 114 * @inputs: input pins pointer 115 * @outputs: output pins pointer 116 * @rclk: recovered pins pointer 117 * @num_inputs: number of input pins available on dpll 118 * @num_outputs: number of output pins available on dpll 119 * @cgu_state_acq_err_num: number of errors returned during periodic work 120 * @base_rclk_idx: idx of first pin used for clock revocery pins 121 * @clock_id: clock_id of dplls 122 * @input_phase_adj_max: max phase adjust value for an input pins 123 * @output_phase_adj_max: max phase adjust value for an output pins 124 * @periodic_counter: counter of periodic work executions 125 */ 126 struct ice_dplls { 127 struct kthread_worker *kworker; 128 struct kthread_delayed_work work; 129 struct workqueue_struct *wq; 130 struct mutex lock; 131 struct completion dpll_init; 132 struct ice_dpll eec; 133 struct ice_dpll pps; 134 struct ice_dpll_pin *inputs; 135 struct ice_dpll_pin *outputs; 136 struct ice_dpll_pin sma[ICE_DPLL_PIN_SW_NUM]; 137 struct ice_dpll_pin ufl[ICE_DPLL_PIN_SW_NUM]; 138 struct ice_dpll_pin rclk; 139 u8 num_inputs; 140 u8 num_outputs; 141 u8 sma_data; 142 u8 base_rclk_idx; 143 int cgu_state_acq_err_num; 144 u64 clock_id; 145 s32 input_phase_adj_max; 146 s32 output_phase_adj_max; 147 u32 periodic_counter; 148 bool generic; 149 }; 150 151 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) 152 void ice_dpll_init(struct ice_pf *pf); 153 void ice_dpll_deinit(struct ice_pf *pf); 154 #else 155 static inline void ice_dpll_init(struct ice_pf *pf) { } 156 static inline void ice_dpll_deinit(struct ice_pf *pf) { } 157 #endif 158 159 #endif 160 161 #define ICE_CGU_R10 0x28 162 #define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5) 163 #define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9) 164 #define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14) 165 #define ICE_CGU_R10_SYNCE_DCK_RST BIT(15) 166 #define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16) 167 #define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19) 168 #define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24) 169 #define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25) 170 #define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27) 171 172 #define ICE_CGU_R11 0x2C 173 #define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1) 174 175 #define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 176