17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_CONTROLQ_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_CONTROLQ_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 87ec59eeaSAnirudh Venkataramanan 9f31e4b6fSAnirudh Venkataramanan /* Maximum buffer lengths for all control queue types */ 10f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_MAX_BUF_LEN 4096 11f31e4b6fSAnirudh Venkataramanan 127ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC(R, i) \ 137ec59eeaSAnirudh Venkataramanan (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 147ec59eeaSAnirudh Venkataramanan 157ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC_UNUSED(R) \ 167ec59eeaSAnirudh Venkataramanan (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 177ec59eeaSAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 187ec59eeaSAnirudh Venkataramanan 197ec59eeaSAnirudh Venkataramanan /* Defines that help manage the driver vs FW API checks. 207ec59eeaSAnirudh Venkataramanan * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 217ec59eeaSAnirudh Venkataramanan * 227ec59eeaSAnirudh Venkataramanan */ 237ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_BRANCH 0x00 247ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_MAJOR 0x00 257ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_MINOR 0x01 267ec59eeaSAnirudh Venkataramanan 277ec59eeaSAnirudh Venkataramanan /* Different control queue types: These are mainly for SW consumption. */ 287ec59eeaSAnirudh Venkataramanan enum ice_ctl_q { 297ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_UNKNOWN = 0, 307ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_ADMIN, 317ec59eeaSAnirudh Venkataramanan }; 327ec59eeaSAnirudh Venkataramanan 337ec59eeaSAnirudh Venkataramanan /* Control Queue default settings */ 347ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */ 357ec59eeaSAnirudh Venkataramanan 367ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring { 377ec59eeaSAnirudh Venkataramanan void *dma_head; /* Virtual address to dma head */ 387ec59eeaSAnirudh Venkataramanan struct ice_dma_mem desc_buf; /* descriptor ring memory */ 397ec59eeaSAnirudh Venkataramanan void *cmd_buf; /* command buffer memory */ 407ec59eeaSAnirudh Venkataramanan 417ec59eeaSAnirudh Venkataramanan union { 427ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *sq_bi; 437ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *rq_bi; 447ec59eeaSAnirudh Venkataramanan } r; 457ec59eeaSAnirudh Venkataramanan 467ec59eeaSAnirudh Venkataramanan u16 count; /* Number of descriptors */ 477ec59eeaSAnirudh Venkataramanan 487ec59eeaSAnirudh Venkataramanan /* used for interrupt processing */ 497ec59eeaSAnirudh Venkataramanan u16 next_to_use; 507ec59eeaSAnirudh Venkataramanan u16 next_to_clean; 517ec59eeaSAnirudh Venkataramanan 527ec59eeaSAnirudh Venkataramanan /* used for queue tracking */ 537ec59eeaSAnirudh Venkataramanan u32 head; 547ec59eeaSAnirudh Venkataramanan u32 tail; 557ec59eeaSAnirudh Venkataramanan u32 len; 567ec59eeaSAnirudh Venkataramanan u32 bah; 577ec59eeaSAnirudh Venkataramanan u32 bal; 587ec59eeaSAnirudh Venkataramanan u32 len_mask; 597ec59eeaSAnirudh Venkataramanan u32 len_ena_mask; 607ec59eeaSAnirudh Venkataramanan u32 head_mask; 617ec59eeaSAnirudh Venkataramanan }; 627ec59eeaSAnirudh Venkataramanan 637ec59eeaSAnirudh Venkataramanan /* sq transaction details */ 647ec59eeaSAnirudh Venkataramanan struct ice_sq_cd { 657ec59eeaSAnirudh Venkataramanan struct ice_aq_desc *wb_desc; 667ec59eeaSAnirudh Venkataramanan }; 677ec59eeaSAnirudh Venkataramanan 687ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 697ec59eeaSAnirudh Venkataramanan 70*940b61afSAnirudh Venkataramanan /* rq event information */ 71*940b61afSAnirudh Venkataramanan struct ice_rq_event_info { 72*940b61afSAnirudh Venkataramanan struct ice_aq_desc desc; 73*940b61afSAnirudh Venkataramanan u16 msg_len; 74*940b61afSAnirudh Venkataramanan u16 buf_len; 75*940b61afSAnirudh Venkataramanan u8 *msg_buf; 76*940b61afSAnirudh Venkataramanan }; 77*940b61afSAnirudh Venkataramanan 787ec59eeaSAnirudh Venkataramanan /* Control Queue information */ 797ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info { 807ec59eeaSAnirudh Venkataramanan enum ice_ctl_q qtype; 817ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring rq; /* receive queue */ 827ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring sq; /* send queue */ 837ec59eeaSAnirudh Venkataramanan u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 847ec59eeaSAnirudh Venkataramanan u16 num_rq_entries; /* receive queue depth */ 857ec59eeaSAnirudh Venkataramanan u16 num_sq_entries; /* send queue depth */ 867ec59eeaSAnirudh Venkataramanan u16 rq_buf_size; /* receive queue buffer size */ 877ec59eeaSAnirudh Venkataramanan u16 sq_buf_size; /* send queue buffer size */ 887ec59eeaSAnirudh Venkataramanan struct mutex sq_lock; /* Send queue lock */ 897ec59eeaSAnirudh Venkataramanan struct mutex rq_lock; /* Receive queue lock */ 907ec59eeaSAnirudh Venkataramanan enum ice_aq_err sq_last_status; /* last status on send queue */ 917ec59eeaSAnirudh Venkataramanan enum ice_aq_err rq_last_status; /* last status on receive queue */ 927ec59eeaSAnirudh Venkataramanan }; 937ec59eeaSAnirudh Venkataramanan 947ec59eeaSAnirudh Venkataramanan #endif /* _ICE_CONTROLQ_H_ */ 95