1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_COMMON_H_ 5 #define _ICE_COMMON_H_ 6 7 #include <linux/bitfield.h> 8 9 #include "ice.h" 10 #include "ice_type.h" 11 #include "ice_nvm.h" 12 #include "ice_flex_pipe.h" 13 #include "ice_parser.h" 14 #include <linux/avf/virtchnl.h> 15 #include "ice_switch.h" 16 #include "ice_fdir.h" 17 18 #define ICE_SQ_SEND_DELAY_TIME_MS 10 19 #define ICE_SQ_SEND_MAX_EXECUTE 3 20 21 #define FEC_REG_SHIFT 2 22 #define FEC_RECV_ID_SHIFT 4 23 #define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT) 24 #define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT) 25 #define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT) 26 #define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT) 27 #define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT) 28 #define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT) 29 #define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT) 30 #define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT) 31 #define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT) 32 #define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT) 33 #define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT) 34 #define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT) 35 #define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT) 36 #define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT) 37 #define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT) 38 #define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT) 39 #define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT) 40 #define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT) 41 42 #define ICE_CGU_R9 0x24 43 union ice_cgu_r9 { 44 struct { 45 u32 time_ref_freq_sel : 3; 46 u32 clk_eref1_en : 1; 47 u32 clk_eref0_en : 1; 48 u32 time_ref_en : 1; 49 u32 time_sync_en : 1; 50 u32 one_pps_out_en : 1; 51 u32 clk_ref_synce_en : 1; 52 u32 clk_synce1_en : 1; 53 u32 clk_synce0_en : 1; 54 u32 net_clk_ref1_en : 1; 55 u32 net_clk_ref0_en : 1; 56 u32 clk_synce1_amp : 2; 57 u32 misc6 : 1; 58 u32 clk_synce0_amp : 2; 59 u32 one_pps_out_amp : 2; 60 u32 misc24 : 12; 61 }; 62 u32 val; 63 }; 64 65 #define ICE_CGU_R16 0x40 66 union ice_cgu_r16 { 67 struct { 68 u32 synce_remndr : 6; 69 u32 synce_phlmt_en : 1; 70 u32 misc13 : 17; 71 u32 ck_refclkfreq : 8; 72 }; 73 u32 val; 74 }; 75 76 #define ICE_CGU_R19 0x4c 77 union ice_cgu_r19_e82x { 78 struct { 79 u32 fbdiv_intgr : 8; 80 u32 fdpll_ulck_thr : 5; 81 u32 misc15 : 3; 82 u32 ndivratio : 4; 83 u32 tspll_iref_ndivratio : 3; 84 u32 misc19 : 1; 85 u32 japll_ndivratio : 4; 86 u32 japll_iref_ndivratio : 3; 87 u32 misc27 : 1; 88 }; 89 u32 val; 90 }; 91 92 union ice_cgu_r19_e825 { 93 struct { 94 u32 tspll_fbdiv_intgr : 10; 95 u32 fdpll_ulck_thr : 5; 96 u32 misc15 : 1; 97 u32 tspll_ndivratio : 4; 98 u32 tspll_iref_ndivratio : 3; 99 u32 misc19 : 1; 100 u32 japll_ndivratio : 4; 101 u32 japll_postdiv_pdivratio : 3; 102 u32 misc27 : 1; 103 }; 104 u32 val; 105 }; 106 107 #define ICE_CGU_R22 0x58 108 union ice_cgu_r22 { 109 struct { 110 u32 fdpll_frac_div_out_nc : 2; 111 u32 fdpll_lock_int_for : 1; 112 u32 synce_hdov_int_for : 1; 113 u32 synce_lock_int_for : 1; 114 u32 fdpll_phlead_slip_nc : 1; 115 u32 fdpll_acc1_ovfl_nc : 1; 116 u32 fdpll_acc2_ovfl_nc : 1; 117 u32 synce_status_nc : 6; 118 u32 fdpll_acc1f_ovfl : 1; 119 u32 misc18 : 1; 120 u32 fdpllclk_div : 4; 121 u32 time1588clk_div : 4; 122 u32 synceclk_div : 4; 123 u32 synceclk_sel_div2 : 1; 124 u32 fdpllclk_sel_div2 : 1; 125 u32 time1588clk_sel_div2 : 1; 126 u32 misc3 : 1; 127 }; 128 u32 val; 129 }; 130 131 #define ICE_CGU_R23 0x5C 132 union ice_cgu_r23 { 133 struct { 134 u32 cgupll_fbdiv_intgr : 10; 135 u32 ux56pll_fbdiv_intgr : 10; 136 u32 misc20 : 4; 137 u32 ts_pll_enable : 1; 138 u32 time_sync_tspll_align_sel : 1; 139 u32 ext_synce_sel : 1; 140 u32 ref1588_ck_div : 4; 141 u32 time_ref_sel : 1; 142 143 }; 144 u32 val; 145 }; 146 147 #define ICE_CGU_R24 0x60 148 union ice_cgu_r24 { 149 struct { 150 u32 fbdiv_frac : 22; 151 u32 misc20 : 2; 152 u32 ts_pll_enable : 1; 153 u32 time_sync_tspll_align_sel : 1; 154 u32 ext_synce_sel : 1; 155 u32 ref1588_ck_div : 4; 156 u32 time_ref_sel : 1; 157 }; 158 u32 val; 159 }; 160 161 #define TSPLL_CNTR_BIST_SETTINGS 0x344 162 union tspll_cntr_bist_settings { 163 struct { 164 u32 i_irefgen_settling_time_cntr_7_0 : 8; 165 u32 i_irefgen_settling_time_ro_standby_1_0 : 2; 166 u32 reserved195 : 5; 167 u32 i_plllock_sel_0 : 1; 168 u32 i_plllock_sel_1 : 1; 169 u32 i_plllock_cnt_6_0 : 7; 170 u32 i_plllock_cnt_10_7 : 4; 171 u32 reserved200 : 4; 172 }; 173 u32 val; 174 }; 175 176 #define TSPLL_RO_BWM_LF 0x370 177 union tspll_ro_bwm_lf { 178 struct { 179 u32 bw_freqov_high_cri_7_0 : 8; 180 u32 bw_freqov_high_cri_9_8 : 2; 181 u32 biascaldone_cri : 1; 182 u32 plllock_gain_tran_cri : 1; 183 u32 plllock_true_lock_cri : 1; 184 u32 pllunlock_flag_cri : 1; 185 u32 afcerr_cri : 1; 186 u32 afcdone_cri : 1; 187 u32 feedfwrdgain_cal_cri_7_0 : 8; 188 u32 m2fbdivmod_cri_7_0 : 8; 189 }; 190 u32 val; 191 }; 192 193 #define TSPLL_RO_LOCK_E825C 0x3f0 194 union tspll_ro_lock_e825c { 195 struct { 196 u32 bw_freqov_high_cri_7_0 : 8; 197 u32 bw_freqov_high_cri_9_8 : 2; 198 u32 reserved455 : 1; 199 u32 plllock_gain_tran_cri : 1; 200 u32 plllock_true_lock_cri : 1; 201 u32 pllunlock_flag_cri : 1; 202 u32 afcerr_cri : 1; 203 u32 afcdone_cri : 1; 204 u32 feedfwrdgain_cal_cri_7_0 : 8; 205 u32 reserved462 : 8; 206 }; 207 u32 val; 208 }; 209 210 #define TSPLL_BW_TDC_E825C 0x31c 211 union tspll_bw_tdc_e825c { 212 struct { 213 u32 i_tdc_offset_lock_1_0 : 2; 214 u32 i_bbthresh1_2_0 : 3; 215 u32 i_bbthresh2_2_0 : 3; 216 u32 i_tdcsel_1_0 : 2; 217 u32 i_tdcovccorr_en_h : 1; 218 u32 i_divretimeren : 1; 219 u32 i_bw_ampmeas_window : 1; 220 u32 i_bw_lowerbound_2_0 : 3; 221 u32 i_bw_upperbound_2_0 : 3; 222 u32 i_bw_mode_1_0 : 2; 223 u32 i_ft_mode_sel_2_0 : 3; 224 u32 i_bwphase_4_0 : 5; 225 u32 i_plllock_sel_1_0 : 2; 226 u32 i_afc_divratio : 1; 227 }; 228 u32 val; 229 }; 230 231 int ice_init_hw(struct ice_hw *hw); 232 void ice_deinit_hw(struct ice_hw *hw); 233 int ice_check_reset(struct ice_hw *hw); 234 int ice_reset(struct ice_hw *hw, enum ice_reset_req req); 235 int ice_create_all_ctrlq(struct ice_hw *hw); 236 int ice_init_all_ctrlq(struct ice_hw *hw); 237 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 238 void ice_destroy_all_ctrlq(struct ice_hw *hw); 239 int 240 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 241 struct ice_rq_event_info *e, u16 *pending); 242 int 243 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 244 int ice_update_link_info(struct ice_port_info *pi); 245 int 246 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 247 enum ice_aq_res_access_type access, u32 timeout); 248 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 249 int 250 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 251 int 252 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 253 int ice_aq_alloc_free_res(struct ice_hw *hw, 254 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 255 enum ice_adminq_opc opc); 256 bool ice_is_sbq_supported(struct ice_hw *hw); 257 struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw); 258 int 259 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 260 struct ice_aq_desc *desc, void *buf, u16 buf_size, 261 struct ice_sq_cd *cd); 262 void ice_clear_pxe_mode(struct ice_hw *hw); 263 int ice_get_caps(struct ice_hw *hw); 264 265 void ice_set_safe_mode_caps(struct ice_hw *hw); 266 267 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 268 u32 rxq_index); 269 270 int 271 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 272 int 273 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 274 int 275 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 276 struct ice_aqc_get_set_rss_keys *keys); 277 int 278 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 279 struct ice_aqc_get_set_rss_keys *keys); 280 281 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 282 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 283 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 284 285 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf); 286 287 extern struct mutex ice_global_cfg_lock_sw; 288 289 int 290 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 291 void *buf, u16 buf_size, struct ice_sq_cd *cd); 292 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 293 294 int 295 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 296 struct ice_sq_cd *cd); 297 int 298 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 299 struct ice_sq_cd *cd); 300 int 301 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 302 struct ice_aqc_get_phy_caps_data *caps, 303 struct ice_sq_cd *cd); 304 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw); 305 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw); 306 bool ice_is_cgu_in_netlist(struct ice_hw *hw); 307 bool ice_is_gps_in_netlist(struct ice_hw *hw); 308 int 309 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 310 u8 *node_part_number, u16 *node_handle); 311 int 312 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 313 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 314 int 315 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps); 316 void 317 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 318 u16 link_speeds_bitmap); 319 int 320 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 321 struct ice_sq_cd *cd); 322 bool ice_is_generic_mac(struct ice_hw *hw); 323 int ice_clear_pf_cfg(struct ice_hw *hw); 324 int 325 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 326 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 327 bool ice_fw_supports_link_override(struct ice_hw *hw); 328 int 329 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 330 struct ice_port_info *pi); 331 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 332 bool ice_is_fw_health_report_supported(struct ice_hw *hw); 333 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source); 334 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 335 u8 serdes_num, int *output); 336 int 337 ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 338 enum ice_fec_stats_types fec_type, u32 *output); 339 340 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 341 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 342 int 343 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 344 bool ena_auto_link_update); 345 int 346 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 347 enum ice_fc_mode req_mode); 348 bool 349 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 350 struct ice_aqc_set_phy_cfg_data *cfg); 351 void 352 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 353 struct ice_aqc_get_phy_caps_data *caps, 354 struct ice_aqc_set_phy_cfg_data *cfg); 355 int 356 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 357 enum ice_fec_mode fec); 358 int 359 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 360 struct ice_sq_cd *cd); 361 int 362 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 363 int 364 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 365 struct ice_link_status *link, struct ice_sq_cd *cd); 366 int 367 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 368 struct ice_sq_cd *cd); 369 int 370 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 371 372 int 373 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 374 struct ice_sq_cd *cd); 375 int 376 ice_aq_get_port_options(struct ice_hw *hw, 377 struct ice_aqc_get_port_options_elem *options, 378 u8 *option_count, u8 lport, bool lport_valid, 379 u8 *active_option_idx, bool *active_option_valid, 380 u8 *pending_option_idx, bool *pending_option_valid); 381 int 382 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 383 u8 new_option); 384 int ice_get_phy_lane_number(struct ice_hw *hw); 385 int 386 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 387 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 388 bool write, struct ice_sq_cd *cd); 389 u32 ice_get_link_speed(u16 index); 390 391 int 392 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 393 u16 *max_rdmaqs); 394 int 395 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 396 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 397 int 398 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 399 u16 *q_id); 400 int 401 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 402 u16 *q_handle, u16 *q_ids, u32 *q_teids, 403 enum ice_disq_rst_src rst_src, u16 vmvf_num, 404 struct ice_sq_cd *cd); 405 int 406 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 407 u16 *max_lanqs); 408 int 409 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 410 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 411 struct ice_sq_cd *cd); 412 int 413 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 414 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 415 struct ice_sq_cd *cd); 416 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 417 void ice_replay_post(struct ice_hw *hw); 418 struct ice_q_ctx * 419 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 420 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag); 421 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 422 struct ice_cgu_input_measure *meas, 423 u16 meas_num); 424 int 425 ice_aq_get_cgu_abilities(struct ice_hw *hw, 426 struct ice_aqc_get_cgu_abilities *abilities); 427 int 428 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 429 u32 freq, s32 phase_delay); 430 int 431 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 432 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay); 433 int 434 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 435 u8 src_sel, u32 freq, s32 phase_delay); 436 int 437 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 438 u8 *src_sel, u32 *freq, u32 *src_freq); 439 int 440 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 441 u8 *dpll_state, u8 *config, s64 *phase_offset, 442 u8 *eec_mode); 443 int 444 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 445 u8 config, u8 eec_mode); 446 int 447 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 448 u8 ref_priority); 449 int 450 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 451 u8 *ref_prio); 452 int 453 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 454 u32 *cgu_fw_ver); 455 456 int 457 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 458 u32 *freq); 459 int 460 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 461 u8 *flags, u16 *node_handle); 462 int ice_aq_get_sensor_reading(struct ice_hw *hw, 463 struct ice_aqc_get_sensor_reading_resp *data); 464 void 465 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 466 u64 *prev_stat, u64 *cur_stat); 467 void 468 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 469 u64 *prev_stat, u64 *cur_stat); 470 int 471 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 472 struct ice_aqc_txsched_elem_data *buf); 473 int 474 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 475 struct ice_sq_cd *cd); 476 int 477 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 478 bool *value, struct ice_sq_cd *cd); 479 bool ice_is_100m_speed_supported(struct ice_hw *hw); 480 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high); 481 int 482 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 483 struct ice_sq_cd *cd); 484 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 485 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add); 486 int ice_lldp_execute_pending_mib(struct ice_hw *hw); 487 int 488 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 489 u16 bus_addr, __le16 addr, u8 params, u8 *data, 490 struct ice_sq_cd *cd); 491 int 492 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 493 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 494 struct ice_sq_cd *cd); 495 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle); 496 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data); 497 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 498 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val); 499 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val); 500 #endif /* _ICE_COMMON_H_ */ 501