1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_COMMON_H_ 5 #define _ICE_COMMON_H_ 6 7 #include <linux/bitfield.h> 8 9 #include "ice.h" 10 #include "ice_type.h" 11 #include "ice_nvm.h" 12 #include "ice_flex_pipe.h" 13 #include "ice_parser.h" 14 #include <linux/avf/virtchnl.h> 15 #include "ice_switch.h" 16 #include "ice_fdir.h" 17 18 #define ICE_SQ_SEND_DELAY_TIME_MS 10 19 #define ICE_SQ_SEND_MAX_EXECUTE 3 20 21 #define FEC_REG_SHIFT 2 22 #define FEC_RECV_ID_SHIFT 4 23 #define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT) 24 #define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT) 25 #define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT) 26 #define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT) 27 #define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT) 28 #define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT) 29 #define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT) 30 #define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT) 31 #define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT) 32 #define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT) 33 #define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT) 34 #define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT) 35 #define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT) 36 #define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT) 37 #define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT) 38 #define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT) 39 #define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT) 40 #define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT) 41 42 #define ICE_CGU_R9 0x24 43 #define ICE_CGU_R9_TIME_REF_FREQ_SEL GENMASK(2, 0) 44 #define ICE_CGU_R9_CLK_EREF0_EN BIT(4) 45 #define ICE_CGU_R9_TIME_REF_EN BIT(5) 46 #define ICE_CGU_R9_TIME_SYNC_EN BIT(6) 47 #define ICE_CGU_R9_ONE_PPS_OUT_EN BIT(7) 48 #define ICE_CGU_R9_ONE_PPS_OUT_AMP GENMASK(19, 18) 49 50 #define ICE_CGU_R16 0x40 51 #define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ GENMASK(31, 24) 52 53 #define ICE_CGU_R19 0x4C 54 #define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X GENMASK(7, 0) 55 #define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 GENMASK(9, 0) 56 #define ICE_CGU_R19_TSPLL_NDIVRATIO GENMASK(19, 16) 57 58 #define ICE_CGU_R22 0x58 59 #define ICE_CGU_R22_TIME1588CLK_DIV GENMASK(23, 20) 60 #define ICE_CGU_R22_TIME1588CLK_DIV2 BIT(30) 61 62 #define ICE_CGU_R23 0x5C 63 #define ICE_CGU_R24 0x60 64 #define ICE_CGU_R24_FBDIV_FRAC GENMASK(21, 0) 65 #define ICE_CGU_R23_R24_TSPLL_ENABLE BIT(24) 66 #define ICE_CGU_R23_R24_REF1588_CK_DIV GENMASK(30, 27) 67 #define ICE_CGU_R23_R24_TIME_REF_SEL BIT(31) 68 69 #define ICE_CGU_BW_TDC 0x31C 70 #define ICE_CGU_BW_TDC_PLLLOCK_SEL GENMASK(30, 29) 71 72 #define ICE_CGU_RO_LOCK 0x3F0 73 #define ICE_CGU_RO_LOCK_TRUE_LOCK BIT(12) 74 #define ICE_CGU_RO_LOCK_UNLOCK BIT(13) 75 76 #define ICE_CGU_CNTR_BIST 0x344 77 #define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0 BIT(15) 78 #define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1 BIT(16) 79 80 #define ICE_CGU_RO_BWM_LF 0x370 81 #define ICE_CGU_RO_BWM_LF_TRUE_LOCK BIT(12) 82 83 int ice_init_hw(struct ice_hw *hw); 84 void ice_deinit_hw(struct ice_hw *hw); 85 int ice_check_reset(struct ice_hw *hw); 86 int ice_reset(struct ice_hw *hw, enum ice_reset_req req); 87 int ice_create_all_ctrlq(struct ice_hw *hw); 88 int ice_init_all_ctrlq(struct ice_hw *hw); 89 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 90 void ice_destroy_all_ctrlq(struct ice_hw *hw); 91 int 92 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 93 struct ice_rq_event_info *e, u16 *pending); 94 int 95 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 96 int ice_update_link_info(struct ice_port_info *pi); 97 int 98 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 99 enum ice_aq_res_access_type access, u32 timeout); 100 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 101 int 102 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 103 int 104 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 105 int ice_aq_alloc_free_res(struct ice_hw *hw, 106 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 107 enum ice_adminq_opc opc); 108 bool ice_is_sbq_supported(struct ice_hw *hw); 109 struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw); 110 int 111 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 112 struct ice_aq_desc *desc, void *buf, u16 buf_size, 113 struct ice_sq_cd *cd); 114 void ice_clear_pxe_mode(struct ice_hw *hw); 115 int ice_get_caps(struct ice_hw *hw); 116 117 void ice_set_safe_mode_caps(struct ice_hw *hw); 118 119 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 120 u32 rxq_index); 121 122 int 123 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 124 int 125 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 126 int 127 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 128 struct ice_aqc_get_set_rss_keys *keys); 129 int 130 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 131 struct ice_aqc_get_set_rss_keys *keys); 132 133 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 134 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 135 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 136 137 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf); 138 139 extern struct mutex ice_global_cfg_lock_sw; 140 141 int 142 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 143 void *buf, u16 buf_size, struct ice_sq_cd *cd); 144 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 145 146 int 147 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 148 struct ice_sq_cd *cd); 149 int 150 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 151 struct ice_sq_cd *cd); 152 int 153 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 154 struct ice_aqc_get_phy_caps_data *caps, 155 struct ice_sq_cd *cd); 156 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw); 157 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw); 158 bool ice_is_cgu_in_netlist(struct ice_hw *hw); 159 bool ice_is_gps_in_netlist(struct ice_hw *hw); 160 int 161 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 162 u8 *node_part_number, u16 *node_handle); 163 int 164 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 165 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 166 int 167 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps); 168 void 169 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 170 u16 link_speeds_bitmap); 171 int 172 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 173 struct ice_sq_cd *cd); 174 bool ice_is_generic_mac(struct ice_hw *hw); 175 int ice_clear_pf_cfg(struct ice_hw *hw); 176 int 177 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 178 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 179 bool ice_fw_supports_link_override(struct ice_hw *hw); 180 int 181 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 182 struct ice_port_info *pi); 183 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 184 bool ice_is_fw_health_report_supported(struct ice_hw *hw); 185 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source); 186 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 187 u8 serdes_num, int *output); 188 int 189 ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 190 enum ice_fec_stats_types fec_type, u32 *output); 191 192 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 193 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 194 int 195 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 196 bool ena_auto_link_update); 197 int 198 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 199 enum ice_fc_mode req_mode); 200 bool 201 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 202 struct ice_aqc_set_phy_cfg_data *cfg); 203 void 204 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 205 struct ice_aqc_get_phy_caps_data *caps, 206 struct ice_aqc_set_phy_cfg_data *cfg); 207 int 208 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 209 enum ice_fec_mode fec); 210 int 211 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 212 struct ice_sq_cd *cd); 213 int 214 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 215 int 216 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 217 struct ice_link_status *link, struct ice_sq_cd *cd); 218 int 219 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 220 struct ice_sq_cd *cd); 221 int 222 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 223 224 int 225 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 226 struct ice_sq_cd *cd); 227 int 228 ice_aq_get_port_options(struct ice_hw *hw, 229 struct ice_aqc_get_port_options_elem *options, 230 u8 *option_count, u8 lport, bool lport_valid, 231 u8 *active_option_idx, bool *active_option_valid, 232 u8 *pending_option_idx, bool *pending_option_valid); 233 int 234 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 235 u8 new_option); 236 int ice_get_phy_lane_number(struct ice_hw *hw); 237 int 238 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 239 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 240 bool write, struct ice_sq_cd *cd); 241 u32 ice_get_link_speed(u16 index); 242 243 int 244 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 245 u16 *max_rdmaqs); 246 int 247 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 248 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 249 int 250 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 251 u16 *q_id); 252 int 253 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 254 u16 *q_handle, u16 *q_ids, u32 *q_teids, 255 enum ice_disq_rst_src rst_src, u16 vmvf_num, 256 struct ice_sq_cd *cd); 257 int 258 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 259 u16 *max_lanqs); 260 int 261 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 262 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 263 struct ice_sq_cd *cd); 264 int 265 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 266 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 267 struct ice_sq_cd *cd); 268 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 269 void ice_replay_post(struct ice_hw *hw); 270 struct ice_q_ctx * 271 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 272 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag); 273 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 274 struct ice_cgu_input_measure *meas, 275 u16 meas_num); 276 int 277 ice_aq_get_cgu_abilities(struct ice_hw *hw, 278 struct ice_aqc_get_cgu_abilities *abilities); 279 int 280 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 281 u32 freq, s32 phase_delay); 282 int 283 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 284 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay); 285 int 286 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 287 u8 src_sel, u32 freq, s32 phase_delay); 288 int 289 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 290 u8 *src_sel, u32 *freq, u32 *src_freq); 291 int 292 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 293 u8 *dpll_state, u8 *config, s64 *phase_offset, 294 u8 *eec_mode); 295 int 296 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 297 u8 config, u8 eec_mode); 298 int 299 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 300 u8 ref_priority); 301 int 302 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 303 u8 *ref_prio); 304 int 305 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 306 u32 *cgu_fw_ver); 307 308 int 309 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 310 u32 *freq); 311 int 312 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 313 u8 *flags, u16 *node_handle); 314 int ice_aq_get_sensor_reading(struct ice_hw *hw, 315 struct ice_aqc_get_sensor_reading_resp *data); 316 void 317 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 318 u64 *prev_stat, u64 *cur_stat); 319 void 320 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 321 u64 *prev_stat, u64 *cur_stat); 322 int 323 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 324 struct ice_aqc_txsched_elem_data *buf); 325 int 326 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 327 struct ice_sq_cd *cd); 328 int 329 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 330 bool *value, struct ice_sq_cd *cd); 331 bool ice_is_100m_speed_supported(struct ice_hw *hw); 332 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high); 333 int 334 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 335 struct ice_sq_cd *cd); 336 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 337 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add); 338 int ice_lldp_execute_pending_mib(struct ice_hw *hw); 339 int 340 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 341 u16 bus_addr, __le16 addr, u8 params, u8 *data, 342 struct ice_sq_cd *cd); 343 int 344 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 345 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 346 struct ice_sq_cd *cd); 347 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle); 348 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data); 349 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 350 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val); 351 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val); 352 #endif /* _ICE_COMMON_H_ */ 353