1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 10 #define ICE_PF_RESET_WAIT_COUNT 300 11 #define ICE_MAX_NETLIST_SIZE 10 12 13 static const char * const ice_link_mode_str_low[] = { 14 [0] = "100BASE_TX", 15 [1] = "100M_SGMII", 16 [2] = "1000BASE_T", 17 [3] = "1000BASE_SX", 18 [4] = "1000BASE_LX", 19 [5] = "1000BASE_KX", 20 [6] = "1G_SGMII", 21 [7] = "2500BASE_T", 22 [8] = "2500BASE_X", 23 [9] = "2500BASE_KX", 24 [10] = "5GBASE_T", 25 [11] = "5GBASE_KR", 26 [12] = "10GBASE_T", 27 [13] = "10G_SFI_DA", 28 [14] = "10GBASE_SR", 29 [15] = "10GBASE_LR", 30 [16] = "10GBASE_KR_CR1", 31 [17] = "10G_SFI_AOC_ACC", 32 [18] = "10G_SFI_C2C", 33 [19] = "25GBASE_T", 34 [20] = "25GBASE_CR", 35 [21] = "25GBASE_CR_S", 36 [22] = "25GBASE_CR1", 37 [23] = "25GBASE_SR", 38 [24] = "25GBASE_LR", 39 [25] = "25GBASE_KR", 40 [26] = "25GBASE_KR_S", 41 [27] = "25GBASE_KR1", 42 [28] = "25G_AUI_AOC_ACC", 43 [29] = "25G_AUI_C2C", 44 [30] = "40GBASE_CR4", 45 [31] = "40GBASE_SR4", 46 [32] = "40GBASE_LR4", 47 [33] = "40GBASE_KR4", 48 [34] = "40G_XLAUI_AOC_ACC", 49 [35] = "40G_XLAUI", 50 [36] = "50GBASE_CR2", 51 [37] = "50GBASE_SR2", 52 [38] = "50GBASE_LR2", 53 [39] = "50GBASE_KR2", 54 [40] = "50G_LAUI2_AOC_ACC", 55 [41] = "50G_LAUI2", 56 [42] = "50G_AUI2_AOC_ACC", 57 [43] = "50G_AUI2", 58 [44] = "50GBASE_CP", 59 [45] = "50GBASE_SR", 60 [46] = "50GBASE_FR", 61 [47] = "50GBASE_LR", 62 [48] = "50GBASE_KR_PAM4", 63 [49] = "50G_AUI1_AOC_ACC", 64 [50] = "50G_AUI1", 65 [51] = "100GBASE_CR4", 66 [52] = "100GBASE_SR4", 67 [53] = "100GBASE_LR4", 68 [54] = "100GBASE_KR4", 69 [55] = "100G_CAUI4_AOC_ACC", 70 [56] = "100G_CAUI4", 71 [57] = "100G_AUI4_AOC_ACC", 72 [58] = "100G_AUI4", 73 [59] = "100GBASE_CR_PAM4", 74 [60] = "100GBASE_KR_PAM4", 75 [61] = "100GBASE_CP2", 76 [62] = "100GBASE_SR2", 77 [63] = "100GBASE_DR", 78 }; 79 80 static const char * const ice_link_mode_str_high[] = { 81 [0] = "100GBASE_KR2_PAM4", 82 [1] = "100G_CAUI2_AOC_ACC", 83 [2] = "100G_CAUI2", 84 [3] = "100G_AUI2_AOC_ACC", 85 [4] = "100G_AUI2", 86 }; 87 88 /** 89 * ice_dump_phy_type - helper function to dump phy_type 90 * @hw: pointer to the HW structure 91 * @low: 64 bit value for phy_type_low 92 * @high: 64 bit value for phy_type_high 93 * @prefix: prefix string to differentiate multiple dumps 94 */ 95 static void 96 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 97 { 98 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 99 100 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 101 if (low & BIT_ULL(i)) 102 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 103 prefix, i, ice_link_mode_str_low[i]); 104 } 105 106 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 107 108 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 109 if (high & BIT_ULL(i)) 110 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 111 prefix, i, ice_link_mode_str_high[i]); 112 } 113 } 114 115 /** 116 * ice_set_mac_type - Sets MAC type 117 * @hw: pointer to the HW structure 118 * 119 * This function sets the MAC type of the adapter based on the 120 * vendor ID and device ID stored in the HW structure. 121 */ 122 static int ice_set_mac_type(struct ice_hw *hw) 123 { 124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 125 return -ENODEV; 126 127 switch (hw->device_id) { 128 case ICE_DEV_ID_E810C_BACKPLANE: 129 case ICE_DEV_ID_E810C_QSFP: 130 case ICE_DEV_ID_E810C_SFP: 131 case ICE_DEV_ID_E810_XXV_BACKPLANE: 132 case ICE_DEV_ID_E810_XXV_QSFP: 133 case ICE_DEV_ID_E810_XXV_SFP: 134 hw->mac_type = ICE_MAC_E810; 135 break; 136 case ICE_DEV_ID_E823C_10G_BASE_T: 137 case ICE_DEV_ID_E823C_BACKPLANE: 138 case ICE_DEV_ID_E823C_QSFP: 139 case ICE_DEV_ID_E823C_SFP: 140 case ICE_DEV_ID_E823C_SGMII: 141 case ICE_DEV_ID_E822C_10G_BASE_T: 142 case ICE_DEV_ID_E822C_BACKPLANE: 143 case ICE_DEV_ID_E822C_QSFP: 144 case ICE_DEV_ID_E822C_SFP: 145 case ICE_DEV_ID_E822C_SGMII: 146 case ICE_DEV_ID_E822L_10G_BASE_T: 147 case ICE_DEV_ID_E822L_BACKPLANE: 148 case ICE_DEV_ID_E822L_SFP: 149 case ICE_DEV_ID_E822L_SGMII: 150 case ICE_DEV_ID_E823L_10G_BASE_T: 151 case ICE_DEV_ID_E823L_1GBE: 152 case ICE_DEV_ID_E823L_BACKPLANE: 153 case ICE_DEV_ID_E823L_QSFP: 154 case ICE_DEV_ID_E823L_SFP: 155 hw->mac_type = ICE_MAC_GENERIC; 156 break; 157 default: 158 hw->mac_type = ICE_MAC_UNKNOWN; 159 break; 160 } 161 162 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 163 return 0; 164 } 165 166 /** 167 * ice_is_e810 168 * @hw: pointer to the hardware structure 169 * 170 * returns true if the device is E810 based, false if not. 171 */ 172 bool ice_is_e810(struct ice_hw *hw) 173 { 174 return hw->mac_type == ICE_MAC_E810; 175 } 176 177 /** 178 * ice_is_e810t 179 * @hw: pointer to the hardware structure 180 * 181 * returns true if the device is E810T based, false if not. 182 */ 183 bool ice_is_e810t(struct ice_hw *hw) 184 { 185 switch (hw->device_id) { 186 case ICE_DEV_ID_E810C_SFP: 187 switch (hw->subsystem_device_id) { 188 case ICE_SUBDEV_ID_E810T: 189 case ICE_SUBDEV_ID_E810T2: 190 case ICE_SUBDEV_ID_E810T3: 191 case ICE_SUBDEV_ID_E810T4: 192 case ICE_SUBDEV_ID_E810T6: 193 case ICE_SUBDEV_ID_E810T7: 194 return true; 195 } 196 break; 197 case ICE_DEV_ID_E810C_QSFP: 198 switch (hw->subsystem_device_id) { 199 case ICE_SUBDEV_ID_E810T2: 200 case ICE_SUBDEV_ID_E810T3: 201 case ICE_SUBDEV_ID_E810T5: 202 return true; 203 } 204 break; 205 default: 206 break; 207 } 208 209 return false; 210 } 211 212 /** 213 * ice_is_e823 214 * @hw: pointer to the hardware structure 215 * 216 * returns true if the device is E823-L or E823-C based, false if not. 217 */ 218 bool ice_is_e823(struct ice_hw *hw) 219 { 220 switch (hw->device_id) { 221 case ICE_DEV_ID_E823L_BACKPLANE: 222 case ICE_DEV_ID_E823L_SFP: 223 case ICE_DEV_ID_E823L_10G_BASE_T: 224 case ICE_DEV_ID_E823L_1GBE: 225 case ICE_DEV_ID_E823L_QSFP: 226 case ICE_DEV_ID_E823C_BACKPLANE: 227 case ICE_DEV_ID_E823C_QSFP: 228 case ICE_DEV_ID_E823C_SFP: 229 case ICE_DEV_ID_E823C_10G_BASE_T: 230 case ICE_DEV_ID_E823C_SGMII: 231 return true; 232 default: 233 return false; 234 } 235 } 236 237 /** 238 * ice_clear_pf_cfg - Clear PF configuration 239 * @hw: pointer to the hardware structure 240 * 241 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 242 * configuration, flow director filters, etc.). 243 */ 244 int ice_clear_pf_cfg(struct ice_hw *hw) 245 { 246 struct ice_aq_desc desc; 247 248 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 249 250 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 251 } 252 253 /** 254 * ice_aq_manage_mac_read - manage MAC address read command 255 * @hw: pointer to the HW struct 256 * @buf: a virtual buffer to hold the manage MAC read response 257 * @buf_size: Size of the virtual buffer 258 * @cd: pointer to command details structure or NULL 259 * 260 * This function is used to return per PF station MAC address (0x0107). 261 * NOTE: Upon successful completion of this command, MAC address information 262 * is returned in user specified buffer. Please interpret user specified 263 * buffer as "manage_mac_read" response. 264 * Response such as various MAC addresses are stored in HW struct (port.mac) 265 * ice_discover_dev_caps is expected to be called before this function is 266 * called. 267 */ 268 static int 269 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 270 struct ice_sq_cd *cd) 271 { 272 struct ice_aqc_manage_mac_read_resp *resp; 273 struct ice_aqc_manage_mac_read *cmd; 274 struct ice_aq_desc desc; 275 int status; 276 u16 flags; 277 u8 i; 278 279 cmd = &desc.params.mac_read; 280 281 if (buf_size < sizeof(*resp)) 282 return -EINVAL; 283 284 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 285 286 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 287 if (status) 288 return status; 289 290 resp = buf; 291 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 292 293 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 294 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 295 return -EIO; 296 } 297 298 /* A single port can report up to two (LAN and WoL) addresses */ 299 for (i = 0; i < cmd->num_addr; i++) 300 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 301 ether_addr_copy(hw->port_info->mac.lan_addr, 302 resp[i].mac_addr); 303 ether_addr_copy(hw->port_info->mac.perm_addr, 304 resp[i].mac_addr); 305 break; 306 } 307 308 return 0; 309 } 310 311 /** 312 * ice_aq_get_phy_caps - returns PHY capabilities 313 * @pi: port information structure 314 * @qual_mods: report qualified modules 315 * @report_mode: report mode capabilities 316 * @pcaps: structure for PHY capabilities to be filled 317 * @cd: pointer to command details structure or NULL 318 * 319 * Returns the various PHY capabilities supported on the Port (0x0600) 320 */ 321 int 322 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 323 struct ice_aqc_get_phy_caps_data *pcaps, 324 struct ice_sq_cd *cd) 325 { 326 struct ice_aqc_get_phy_caps *cmd; 327 u16 pcaps_size = sizeof(*pcaps); 328 struct ice_aq_desc desc; 329 const char *prefix; 330 struct ice_hw *hw; 331 int status; 332 333 cmd = &desc.params.get_phy; 334 335 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 336 return -EINVAL; 337 hw = pi->hw; 338 339 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 340 !ice_fw_supports_report_dflt_cfg(hw)) 341 return -EINVAL; 342 343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 344 345 if (qual_mods) 346 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 347 348 cmd->param0 |= cpu_to_le16(report_mode); 349 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 350 351 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 352 353 switch (report_mode) { 354 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 355 prefix = "phy_caps_media"; 356 break; 357 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 358 prefix = "phy_caps_no_media"; 359 break; 360 case ICE_AQC_REPORT_ACTIVE_CFG: 361 prefix = "phy_caps_active"; 362 break; 363 case ICE_AQC_REPORT_DFLT_CFG: 364 prefix = "phy_caps_default"; 365 break; 366 default: 367 prefix = "phy_caps_invalid"; 368 } 369 370 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 371 le64_to_cpu(pcaps->phy_type_high), prefix); 372 373 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 374 prefix, report_mode); 375 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 376 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 377 pcaps->low_power_ctrl_an); 378 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 379 pcaps->eee_cap); 380 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 381 pcaps->eeer_value); 382 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 383 pcaps->link_fec_options); 384 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 385 prefix, pcaps->module_compliance_enforcement); 386 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 387 prefix, pcaps->extended_compliance_code); 388 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 389 pcaps->module_type[0]); 390 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 391 pcaps->module_type[1]); 392 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 393 pcaps->module_type[2]); 394 395 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 396 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 397 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 398 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 399 sizeof(pi->phy.link_info.module_type)); 400 } 401 402 return status; 403 } 404 405 /** 406 * ice_aq_get_link_topo_handle - get link topology node return status 407 * @pi: port information structure 408 * @node_type: requested node type 409 * @cd: pointer to command details structure or NULL 410 * 411 * Get link topology node return status for specified node type (0x06E0) 412 * 413 * Node type cage can be used to determine if cage is present. If AQC 414 * returns error (ENOENT), then no cage present. If no cage present, then 415 * connection type is backplane or BASE-T. 416 */ 417 static int 418 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 419 struct ice_sq_cd *cd) 420 { 421 struct ice_aqc_get_link_topo *cmd; 422 struct ice_aq_desc desc; 423 424 cmd = &desc.params.get_link_topo; 425 426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 427 428 cmd->addr.topo_params.node_type_ctx = 429 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 430 ICE_AQC_LINK_TOPO_NODE_CTX_S); 431 432 /* set node type */ 433 cmd->addr.topo_params.node_type_ctx |= 434 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 435 436 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 437 } 438 439 /** 440 * ice_aq_get_netlist_node 441 * @hw: pointer to the hw struct 442 * @cmd: get_link_topo AQ structure 443 * @node_part_number: output node part number if node found 444 * @node_handle: output node handle parameter if node found 445 * 446 * Get netlist node handle. 447 */ 448 int 449 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 450 u8 *node_part_number, u16 *node_handle) 451 { 452 struct ice_aq_desc desc; 453 454 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 455 desc.params.get_link_topo = *cmd; 456 457 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 458 return -EINTR; 459 460 if (node_handle) 461 *node_handle = 462 le16_to_cpu(desc.params.get_link_topo.addr.handle); 463 if (node_part_number) 464 *node_part_number = desc.params.get_link_topo.node_part_num; 465 466 return 0; 467 } 468 469 /** 470 * ice_find_netlist_node 471 * @hw: pointer to the hw struct 472 * @node_type_ctx: type of netlist node to look for 473 * @node_part_number: node part number to look for 474 * @node_handle: output parameter if node found - optional 475 * 476 * Find and return the node handle for a given node type and part number in the 477 * netlist. When found ICE_SUCCESS is returned, ICE_ERR_DOES_NOT_EXIST 478 * otherwise. If node_handle provided, it would be set to found node handle. 479 */ 480 int 481 ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, 482 u16 *node_handle) 483 { 484 struct ice_aqc_get_link_topo cmd; 485 u8 rec_node_part_number; 486 u16 rec_node_handle; 487 u8 idx; 488 489 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 490 int status; 491 492 memset(&cmd, 0, sizeof(cmd)); 493 494 cmd.addr.topo_params.node_type_ctx = 495 (node_type_ctx << ICE_AQC_LINK_TOPO_NODE_TYPE_S); 496 cmd.addr.topo_params.index = idx; 497 498 status = ice_aq_get_netlist_node(hw, &cmd, 499 &rec_node_part_number, 500 &rec_node_handle); 501 if (status) 502 return status; 503 504 if (rec_node_part_number == node_part_number) { 505 if (node_handle) 506 *node_handle = rec_node_handle; 507 return 0; 508 } 509 } 510 511 return -ENOTBLK; 512 } 513 514 /** 515 * ice_is_media_cage_present 516 * @pi: port information structure 517 * 518 * Returns true if media cage is present, else false. If no cage, then 519 * media type is backplane or BASE-T. 520 */ 521 static bool ice_is_media_cage_present(struct ice_port_info *pi) 522 { 523 /* Node type cage can be used to determine if cage is present. If AQC 524 * returns error (ENOENT), then no cage present. If no cage present then 525 * connection type is backplane or BASE-T. 526 */ 527 return !ice_aq_get_link_topo_handle(pi, 528 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 529 NULL); 530 } 531 532 /** 533 * ice_get_media_type - Gets media type 534 * @pi: port information structure 535 */ 536 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 537 { 538 struct ice_link_status *hw_link_info; 539 540 if (!pi) 541 return ICE_MEDIA_UNKNOWN; 542 543 hw_link_info = &pi->phy.link_info; 544 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 545 /* If more than one media type is selected, report unknown */ 546 return ICE_MEDIA_UNKNOWN; 547 548 if (hw_link_info->phy_type_low) { 549 /* 1G SGMII is a special case where some DA cable PHYs 550 * may show this as an option when it really shouldn't 551 * be since SGMII is meant to be between a MAC and a PHY 552 * in a backplane. Try to detect this case and handle it 553 */ 554 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 555 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 556 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 557 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 558 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 559 return ICE_MEDIA_DA; 560 561 switch (hw_link_info->phy_type_low) { 562 case ICE_PHY_TYPE_LOW_1000BASE_SX: 563 case ICE_PHY_TYPE_LOW_1000BASE_LX: 564 case ICE_PHY_TYPE_LOW_10GBASE_SR: 565 case ICE_PHY_TYPE_LOW_10GBASE_LR: 566 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 567 case ICE_PHY_TYPE_LOW_25GBASE_SR: 568 case ICE_PHY_TYPE_LOW_25GBASE_LR: 569 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 570 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 571 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 572 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 573 case ICE_PHY_TYPE_LOW_50GBASE_SR: 574 case ICE_PHY_TYPE_LOW_50GBASE_FR: 575 case ICE_PHY_TYPE_LOW_50GBASE_LR: 576 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 577 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 578 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 579 case ICE_PHY_TYPE_LOW_100GBASE_DR: 580 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 581 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 582 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 583 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 584 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 585 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 586 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 587 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 588 return ICE_MEDIA_FIBER; 589 case ICE_PHY_TYPE_LOW_100BASE_TX: 590 case ICE_PHY_TYPE_LOW_1000BASE_T: 591 case ICE_PHY_TYPE_LOW_2500BASE_T: 592 case ICE_PHY_TYPE_LOW_5GBASE_T: 593 case ICE_PHY_TYPE_LOW_10GBASE_T: 594 case ICE_PHY_TYPE_LOW_25GBASE_T: 595 return ICE_MEDIA_BASET; 596 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 597 case ICE_PHY_TYPE_LOW_25GBASE_CR: 598 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 599 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 600 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 601 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 602 case ICE_PHY_TYPE_LOW_50GBASE_CP: 603 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 604 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 605 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 606 return ICE_MEDIA_DA; 607 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 608 case ICE_PHY_TYPE_LOW_40G_XLAUI: 609 case ICE_PHY_TYPE_LOW_50G_LAUI2: 610 case ICE_PHY_TYPE_LOW_50G_AUI2: 611 case ICE_PHY_TYPE_LOW_50G_AUI1: 612 case ICE_PHY_TYPE_LOW_100G_AUI4: 613 case ICE_PHY_TYPE_LOW_100G_CAUI4: 614 if (ice_is_media_cage_present(pi)) 615 return ICE_MEDIA_DA; 616 fallthrough; 617 case ICE_PHY_TYPE_LOW_1000BASE_KX: 618 case ICE_PHY_TYPE_LOW_2500BASE_KX: 619 case ICE_PHY_TYPE_LOW_2500BASE_X: 620 case ICE_PHY_TYPE_LOW_5GBASE_KR: 621 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 622 case ICE_PHY_TYPE_LOW_25GBASE_KR: 623 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 624 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 625 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 626 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 627 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 628 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 629 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 630 return ICE_MEDIA_BACKPLANE; 631 } 632 } else { 633 switch (hw_link_info->phy_type_high) { 634 case ICE_PHY_TYPE_HIGH_100G_AUI2: 635 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 636 if (ice_is_media_cage_present(pi)) 637 return ICE_MEDIA_DA; 638 fallthrough; 639 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 640 return ICE_MEDIA_BACKPLANE; 641 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 642 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 643 return ICE_MEDIA_FIBER; 644 } 645 } 646 return ICE_MEDIA_UNKNOWN; 647 } 648 649 /** 650 * ice_aq_get_link_info 651 * @pi: port information structure 652 * @ena_lse: enable/disable LinkStatusEvent reporting 653 * @link: pointer to link status structure - optional 654 * @cd: pointer to command details structure or NULL 655 * 656 * Get Link Status (0x607). Returns the link status of the adapter. 657 */ 658 int 659 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 660 struct ice_link_status *link, struct ice_sq_cd *cd) 661 { 662 struct ice_aqc_get_link_status_data link_data = { 0 }; 663 struct ice_aqc_get_link_status *resp; 664 struct ice_link_status *li_old, *li; 665 enum ice_media_type *hw_media_type; 666 struct ice_fc_info *hw_fc_info; 667 bool tx_pause, rx_pause; 668 struct ice_aq_desc desc; 669 struct ice_hw *hw; 670 u16 cmd_flags; 671 int status; 672 673 if (!pi) 674 return -EINVAL; 675 hw = pi->hw; 676 li_old = &pi->phy.link_info_old; 677 hw_media_type = &pi->phy.media_type; 678 li = &pi->phy.link_info; 679 hw_fc_info = &pi->fc; 680 681 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 682 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 683 resp = &desc.params.get_link_status; 684 resp->cmd_flags = cpu_to_le16(cmd_flags); 685 resp->lport_num = pi->lport; 686 687 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 688 689 if (status) 690 return status; 691 692 /* save off old link status information */ 693 *li_old = *li; 694 695 /* update current link status information */ 696 li->link_speed = le16_to_cpu(link_data.link_speed); 697 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 698 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 699 *hw_media_type = ice_get_media_type(pi); 700 li->link_info = link_data.link_info; 701 li->link_cfg_err = link_data.link_cfg_err; 702 li->an_info = link_data.an_info; 703 li->ext_info = link_data.ext_info; 704 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 705 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 706 li->topo_media_conflict = link_data.topo_media_conflict; 707 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 708 ICE_AQ_CFG_PACING_TYPE_M); 709 710 /* update fc info */ 711 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 712 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 713 if (tx_pause && rx_pause) 714 hw_fc_info->current_mode = ICE_FC_FULL; 715 else if (tx_pause) 716 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 717 else if (rx_pause) 718 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 719 else 720 hw_fc_info->current_mode = ICE_FC_NONE; 721 722 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 723 724 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 725 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 726 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 727 (unsigned long long)li->phy_type_low); 728 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 729 (unsigned long long)li->phy_type_high); 730 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 731 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 732 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 733 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 734 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 735 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 736 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 737 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 738 li->max_frame_size); 739 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 740 741 /* save link status information */ 742 if (link) 743 *link = *li; 744 745 /* flag cleared so calling functions don't call AQ again */ 746 pi->phy.get_link_info = false; 747 748 return 0; 749 } 750 751 /** 752 * ice_fill_tx_timer_and_fc_thresh 753 * @hw: pointer to the HW struct 754 * @cmd: pointer to MAC cfg structure 755 * 756 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 757 * descriptor 758 */ 759 static void 760 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 761 struct ice_aqc_set_mac_cfg *cmd) 762 { 763 u16 fc_thres_val, tx_timer_val; 764 u32 val; 765 766 /* We read back the transmit timer and FC threshold value of 767 * LFC. Thus, we will use index = 768 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 769 * 770 * Also, because we are operating on transmit timer and FC 771 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 772 */ 773 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 774 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 777 tx_timer_val = val & 778 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 779 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 780 781 /* Retrieve the FC threshold */ 782 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 783 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 784 785 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 786 } 787 788 /** 789 * ice_aq_set_mac_cfg 790 * @hw: pointer to the HW struct 791 * @max_frame_size: Maximum Frame Size to be supported 792 * @cd: pointer to command details structure or NULL 793 * 794 * Set MAC configuration (0x0603) 795 */ 796 int 797 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 798 { 799 struct ice_aqc_set_mac_cfg *cmd; 800 struct ice_aq_desc desc; 801 802 cmd = &desc.params.set_mac_cfg; 803 804 if (max_frame_size == 0) 805 return -EINVAL; 806 807 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 808 809 cmd->max_frame_size = cpu_to_le16(max_frame_size); 810 811 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 812 813 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 814 } 815 816 /** 817 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 818 * @hw: pointer to the HW struct 819 */ 820 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 821 { 822 struct ice_switch_info *sw; 823 int status; 824 825 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 826 sizeof(*hw->switch_info), GFP_KERNEL); 827 sw = hw->switch_info; 828 829 if (!sw) 830 return -ENOMEM; 831 832 INIT_LIST_HEAD(&sw->vsi_list_map_head); 833 sw->prof_res_bm_init = 0; 834 835 status = ice_init_def_sw_recp(hw); 836 if (status) { 837 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 838 return status; 839 } 840 return 0; 841 } 842 843 /** 844 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 845 * @hw: pointer to the HW struct 846 */ 847 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 848 { 849 struct ice_switch_info *sw = hw->switch_info; 850 struct ice_vsi_list_map_info *v_pos_map; 851 struct ice_vsi_list_map_info *v_tmp_map; 852 struct ice_sw_recipe *recps; 853 u8 i; 854 855 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 856 list_entry) { 857 list_del(&v_pos_map->list_entry); 858 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 859 } 860 recps = sw->recp_list; 861 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 862 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 863 864 recps[i].root_rid = i; 865 list_for_each_entry_safe(rg_entry, tmprg_entry, 866 &recps[i].rg_list, l_entry) { 867 list_del(&rg_entry->l_entry); 868 devm_kfree(ice_hw_to_dev(hw), rg_entry); 869 } 870 871 if (recps[i].adv_rule) { 872 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 873 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 874 875 mutex_destroy(&recps[i].filt_rule_lock); 876 list_for_each_entry_safe(lst_itr, tmp_entry, 877 &recps[i].filt_rules, 878 list_entry) { 879 list_del(&lst_itr->list_entry); 880 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 881 devm_kfree(ice_hw_to_dev(hw), lst_itr); 882 } 883 } else { 884 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 885 886 mutex_destroy(&recps[i].filt_rule_lock); 887 list_for_each_entry_safe(lst_itr, tmp_entry, 888 &recps[i].filt_rules, 889 list_entry) { 890 list_del(&lst_itr->list_entry); 891 devm_kfree(ice_hw_to_dev(hw), lst_itr); 892 } 893 } 894 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 895 } 896 ice_rm_all_sw_replay_rule_info(hw); 897 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 898 devm_kfree(ice_hw_to_dev(hw), sw); 899 } 900 901 /** 902 * ice_get_fw_log_cfg - get FW logging configuration 903 * @hw: pointer to the HW struct 904 */ 905 static int ice_get_fw_log_cfg(struct ice_hw *hw) 906 { 907 struct ice_aq_desc desc; 908 __le16 *config; 909 int status; 910 u16 size; 911 912 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 913 config = kzalloc(size, GFP_KERNEL); 914 if (!config) 915 return -ENOMEM; 916 917 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 918 919 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 920 if (!status) { 921 u16 i; 922 923 /* Save FW logging information into the HW structure */ 924 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 925 u16 v, m, flgs; 926 927 v = le16_to_cpu(config[i]); 928 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 929 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 930 931 if (m < ICE_AQC_FW_LOG_ID_MAX) 932 hw->fw_log.evnts[m].cur = flgs; 933 } 934 } 935 936 kfree(config); 937 938 return status; 939 } 940 941 /** 942 * ice_cfg_fw_log - configure FW logging 943 * @hw: pointer to the HW struct 944 * @enable: enable certain FW logging events if true, disable all if false 945 * 946 * This function enables/disables the FW logging via Rx CQ events and a UART 947 * port based on predetermined configurations. FW logging via the Rx CQ can be 948 * enabled/disabled for individual PF's. However, FW logging via the UART can 949 * only be enabled/disabled for all PFs on the same device. 950 * 951 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 952 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 953 * before initializing the device. 954 * 955 * When re/configuring FW logging, callers need to update the "cfg" elements of 956 * the hw->fw_log.evnts array with the desired logging event configurations for 957 * modules of interest. When disabling FW logging completely, the callers can 958 * just pass false in the "enable" parameter. On completion, the function will 959 * update the "cur" element of the hw->fw_log.evnts array with the resulting 960 * logging event configurations of the modules that are being re/configured. FW 961 * logging modules that are not part of a reconfiguration operation retain their 962 * previous states. 963 * 964 * Before resetting the device, it is recommended that the driver disables FW 965 * logging before shutting down the control queue. When disabling FW logging 966 * ("enable" = false), the latest configurations of FW logging events stored in 967 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 968 * a device reset. 969 * 970 * When enabling FW logging to emit log messages via the Rx CQ during the 971 * device's initialization phase, a mechanism alternative to interrupt handlers 972 * needs to be used to extract FW log messages from the Rx CQ periodically and 973 * to prevent the Rx CQ from being full and stalling other types of control 974 * messages from FW to SW. Interrupts are typically disabled during the device's 975 * initialization phase. 976 */ 977 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 978 { 979 struct ice_aqc_fw_logging *cmd; 980 u16 i, chgs = 0, len = 0; 981 struct ice_aq_desc desc; 982 __le16 *data = NULL; 983 u8 actv_evnts = 0; 984 void *buf = NULL; 985 int status = 0; 986 987 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 988 return 0; 989 990 /* Disable FW logging only when the control queue is still responsive */ 991 if (!enable && 992 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 993 return 0; 994 995 /* Get current FW log settings */ 996 status = ice_get_fw_log_cfg(hw); 997 if (status) 998 return status; 999 1000 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 1001 cmd = &desc.params.fw_logging; 1002 1003 /* Indicate which controls are valid */ 1004 if (hw->fw_log.cq_en) 1005 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 1006 1007 if (hw->fw_log.uart_en) 1008 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 1009 1010 if (enable) { 1011 /* Fill in an array of entries with FW logging modules and 1012 * logging events being reconfigured. 1013 */ 1014 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 1015 u16 val; 1016 1017 /* Keep track of enabled event types */ 1018 actv_evnts |= hw->fw_log.evnts[i].cfg; 1019 1020 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 1021 continue; 1022 1023 if (!data) { 1024 data = devm_kcalloc(ice_hw_to_dev(hw), 1025 ICE_AQC_FW_LOG_ID_MAX, 1026 sizeof(*data), 1027 GFP_KERNEL); 1028 if (!data) 1029 return -ENOMEM; 1030 } 1031 1032 val = i << ICE_AQC_FW_LOG_ID_S; 1033 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 1034 data[chgs++] = cpu_to_le16(val); 1035 } 1036 1037 /* Only enable FW logging if at least one module is specified. 1038 * If FW logging is currently enabled but all modules are not 1039 * enabled to emit log messages, disable FW logging altogether. 1040 */ 1041 if (actv_evnts) { 1042 /* Leave if there is effectively no change */ 1043 if (!chgs) 1044 goto out; 1045 1046 if (hw->fw_log.cq_en) 1047 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 1048 1049 if (hw->fw_log.uart_en) 1050 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 1051 1052 buf = data; 1053 len = sizeof(*data) * chgs; 1054 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1055 } 1056 } 1057 1058 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 1059 if (!status) { 1060 /* Update the current configuration to reflect events enabled. 1061 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 1062 * logging mode is enabled for the device. They do not reflect 1063 * actual modules being enabled to emit log messages. So, their 1064 * values remain unchanged even when all modules are disabled. 1065 */ 1066 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 1067 1068 hw->fw_log.actv_evnts = actv_evnts; 1069 for (i = 0; i < cnt; i++) { 1070 u16 v, m; 1071 1072 if (!enable) { 1073 /* When disabling all FW logging events as part 1074 * of device's de-initialization, the original 1075 * configurations are retained, and can be used 1076 * to reconfigure FW logging later if the device 1077 * is re-initialized. 1078 */ 1079 hw->fw_log.evnts[i].cur = 0; 1080 continue; 1081 } 1082 1083 v = le16_to_cpu(data[i]); 1084 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 1085 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 1086 } 1087 } 1088 1089 out: 1090 devm_kfree(ice_hw_to_dev(hw), data); 1091 1092 return status; 1093 } 1094 1095 /** 1096 * ice_output_fw_log 1097 * @hw: pointer to the HW struct 1098 * @desc: pointer to the AQ message descriptor 1099 * @buf: pointer to the buffer accompanying the AQ message 1100 * 1101 * Formats a FW Log message and outputs it via the standard driver logs. 1102 */ 1103 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 1104 { 1105 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 1106 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 1107 le16_to_cpu(desc->datalen)); 1108 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 1109 } 1110 1111 /** 1112 * ice_get_itr_intrl_gran 1113 * @hw: pointer to the HW struct 1114 * 1115 * Determines the ITR/INTRL granularities based on the maximum aggregate 1116 * bandwidth according to the device's configuration during power-on. 1117 */ 1118 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1119 { 1120 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 1121 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 1122 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 1123 1124 switch (max_agg_bw) { 1125 case ICE_MAX_AGG_BW_200G: 1126 case ICE_MAX_AGG_BW_100G: 1127 case ICE_MAX_AGG_BW_50G: 1128 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1129 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1130 break; 1131 case ICE_MAX_AGG_BW_25G: 1132 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1133 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1134 break; 1135 } 1136 } 1137 1138 /** 1139 * ice_init_hw - main hardware initialization routine 1140 * @hw: pointer to the hardware structure 1141 */ 1142 int ice_init_hw(struct ice_hw *hw) 1143 { 1144 struct ice_aqc_get_phy_caps_data *pcaps; 1145 u16 mac_buf_len; 1146 void *mac_buf; 1147 int status; 1148 1149 /* Set MAC type based on DeviceID */ 1150 status = ice_set_mac_type(hw); 1151 if (status) 1152 return status; 1153 1154 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 1155 PF_FUNC_RID_FUNC_NUM_M) >> 1156 PF_FUNC_RID_FUNC_NUM_S; 1157 1158 status = ice_reset(hw, ICE_RESET_PFR); 1159 if (status) 1160 return status; 1161 1162 ice_get_itr_intrl_gran(hw); 1163 1164 status = ice_create_all_ctrlq(hw); 1165 if (status) 1166 goto err_unroll_cqinit; 1167 1168 /* Enable FW logging. Not fatal if this fails. */ 1169 status = ice_cfg_fw_log(hw, true); 1170 if (status) 1171 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 1172 1173 status = ice_clear_pf_cfg(hw); 1174 if (status) 1175 goto err_unroll_cqinit; 1176 1177 /* Set bit to enable Flow Director filters */ 1178 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1179 INIT_LIST_HEAD(&hw->fdir_list_head); 1180 1181 ice_clear_pxe_mode(hw); 1182 1183 status = ice_init_nvm(hw); 1184 if (status) 1185 goto err_unroll_cqinit; 1186 1187 status = ice_get_caps(hw); 1188 if (status) 1189 goto err_unroll_cqinit; 1190 1191 if (!hw->port_info) 1192 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1193 sizeof(*hw->port_info), 1194 GFP_KERNEL); 1195 if (!hw->port_info) { 1196 status = -ENOMEM; 1197 goto err_unroll_cqinit; 1198 } 1199 1200 /* set the back pointer to HW */ 1201 hw->port_info->hw = hw; 1202 1203 /* Initialize port_info struct with switch configuration data */ 1204 status = ice_get_initial_sw_cfg(hw); 1205 if (status) 1206 goto err_unroll_alloc; 1207 1208 hw->evb_veb = true; 1209 1210 /* init xarray for identifying scheduling nodes uniquely */ 1211 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1212 1213 /* Query the allocated resources for Tx scheduler */ 1214 status = ice_sched_query_res_alloc(hw); 1215 if (status) { 1216 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1217 goto err_unroll_alloc; 1218 } 1219 ice_sched_get_psm_clk_freq(hw); 1220 1221 /* Initialize port_info struct with scheduler data */ 1222 status = ice_sched_init_port(hw->port_info); 1223 if (status) 1224 goto err_unroll_sched; 1225 1226 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1227 if (!pcaps) { 1228 status = -ENOMEM; 1229 goto err_unroll_sched; 1230 } 1231 1232 /* Initialize port_info struct with PHY capabilities */ 1233 status = ice_aq_get_phy_caps(hw->port_info, false, 1234 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1235 NULL); 1236 devm_kfree(ice_hw_to_dev(hw), pcaps); 1237 if (status) 1238 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1239 status); 1240 1241 /* Initialize port_info struct with link information */ 1242 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1243 if (status) 1244 goto err_unroll_sched; 1245 1246 /* need a valid SW entry point to build a Tx tree */ 1247 if (!hw->sw_entry_point_layer) { 1248 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1249 status = -EIO; 1250 goto err_unroll_sched; 1251 } 1252 INIT_LIST_HEAD(&hw->agg_list); 1253 /* Initialize max burst size */ 1254 if (!hw->max_burst_size) 1255 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1256 1257 status = ice_init_fltr_mgmt_struct(hw); 1258 if (status) 1259 goto err_unroll_sched; 1260 1261 /* Get MAC information */ 1262 /* A single port can report up to two (LAN and WoL) addresses */ 1263 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1264 sizeof(struct ice_aqc_manage_mac_read_resp), 1265 GFP_KERNEL); 1266 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1267 1268 if (!mac_buf) { 1269 status = -ENOMEM; 1270 goto err_unroll_fltr_mgmt_struct; 1271 } 1272 1273 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1274 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1275 1276 if (status) 1277 goto err_unroll_fltr_mgmt_struct; 1278 /* enable jumbo frame support at MAC level */ 1279 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1280 if (status) 1281 goto err_unroll_fltr_mgmt_struct; 1282 /* Obtain counter base index which would be used by flow director */ 1283 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1284 if (status) 1285 goto err_unroll_fltr_mgmt_struct; 1286 status = ice_init_hw_tbls(hw); 1287 if (status) 1288 goto err_unroll_fltr_mgmt_struct; 1289 mutex_init(&hw->tnl_lock); 1290 return 0; 1291 1292 err_unroll_fltr_mgmt_struct: 1293 ice_cleanup_fltr_mgmt_struct(hw); 1294 err_unroll_sched: 1295 ice_sched_cleanup_all(hw); 1296 err_unroll_alloc: 1297 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1298 err_unroll_cqinit: 1299 ice_destroy_all_ctrlq(hw); 1300 return status; 1301 } 1302 1303 /** 1304 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1305 * @hw: pointer to the hardware structure 1306 * 1307 * This should be called only during nominal operation, not as a result of 1308 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1309 * applicable initializations if it fails for any reason. 1310 */ 1311 void ice_deinit_hw(struct ice_hw *hw) 1312 { 1313 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1314 ice_cleanup_fltr_mgmt_struct(hw); 1315 1316 ice_sched_cleanup_all(hw); 1317 ice_sched_clear_agg(hw); 1318 ice_free_seg(hw); 1319 ice_free_hw_tbls(hw); 1320 mutex_destroy(&hw->tnl_lock); 1321 1322 /* Attempt to disable FW logging before shutting down control queues */ 1323 ice_cfg_fw_log(hw, false); 1324 ice_destroy_all_ctrlq(hw); 1325 1326 /* Clear VSI contexts if not already cleared */ 1327 ice_clear_all_vsi_ctx(hw); 1328 } 1329 1330 /** 1331 * ice_check_reset - Check to see if a global reset is complete 1332 * @hw: pointer to the hardware structure 1333 */ 1334 int ice_check_reset(struct ice_hw *hw) 1335 { 1336 u32 cnt, reg = 0, grst_timeout, uld_mask; 1337 1338 /* Poll for Device Active state in case a recent CORER, GLOBR, 1339 * or EMPR has occurred. The grst delay value is in 100ms units. 1340 * Add 1sec for outstanding AQ commands that can take a long time. 1341 */ 1342 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1343 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1344 1345 for (cnt = 0; cnt < grst_timeout; cnt++) { 1346 mdelay(100); 1347 reg = rd32(hw, GLGEN_RSTAT); 1348 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1349 break; 1350 } 1351 1352 if (cnt == grst_timeout) { 1353 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1354 return -EIO; 1355 } 1356 1357 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1358 GLNVM_ULD_PCIER_DONE_1_M |\ 1359 GLNVM_ULD_CORER_DONE_M |\ 1360 GLNVM_ULD_GLOBR_DONE_M |\ 1361 GLNVM_ULD_POR_DONE_M |\ 1362 GLNVM_ULD_POR_DONE_1_M |\ 1363 GLNVM_ULD_PCIER_DONE_2_M) 1364 1365 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1366 GLNVM_ULD_PE_DONE_M : 0); 1367 1368 /* Device is Active; check Global Reset processes are done */ 1369 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1370 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1371 if (reg == uld_mask) { 1372 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1373 break; 1374 } 1375 mdelay(10); 1376 } 1377 1378 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1379 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1380 reg); 1381 return -EIO; 1382 } 1383 1384 return 0; 1385 } 1386 1387 /** 1388 * ice_pf_reset - Reset the PF 1389 * @hw: pointer to the hardware structure 1390 * 1391 * If a global reset has been triggered, this function checks 1392 * for its completion and then issues the PF reset 1393 */ 1394 static int ice_pf_reset(struct ice_hw *hw) 1395 { 1396 u32 cnt, reg; 1397 1398 /* If at function entry a global reset was already in progress, i.e. 1399 * state is not 'device active' or any of the reset done bits are not 1400 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1401 * global reset is done. 1402 */ 1403 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1404 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1405 /* poll on global reset currently in progress until done */ 1406 if (ice_check_reset(hw)) 1407 return -EIO; 1408 1409 return 0; 1410 } 1411 1412 /* Reset the PF */ 1413 reg = rd32(hw, PFGEN_CTRL); 1414 1415 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1416 1417 /* Wait for the PFR to complete. The wait time is the global config lock 1418 * timeout plus the PFR timeout which will account for a possible reset 1419 * that is occurring during a download package operation. 1420 */ 1421 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1422 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1423 reg = rd32(hw, PFGEN_CTRL); 1424 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1425 break; 1426 1427 mdelay(1); 1428 } 1429 1430 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1431 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1432 return -EIO; 1433 } 1434 1435 return 0; 1436 } 1437 1438 /** 1439 * ice_reset - Perform different types of reset 1440 * @hw: pointer to the hardware structure 1441 * @req: reset request 1442 * 1443 * This function triggers a reset as specified by the req parameter. 1444 * 1445 * Note: 1446 * If anything other than a PF reset is triggered, PXE mode is restored. 1447 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1448 * interface has been restored in the rebuild flow. 1449 */ 1450 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1451 { 1452 u32 val = 0; 1453 1454 switch (req) { 1455 case ICE_RESET_PFR: 1456 return ice_pf_reset(hw); 1457 case ICE_RESET_CORER: 1458 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1459 val = GLGEN_RTRIG_CORER_M; 1460 break; 1461 case ICE_RESET_GLOBR: 1462 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1463 val = GLGEN_RTRIG_GLOBR_M; 1464 break; 1465 default: 1466 return -EINVAL; 1467 } 1468 1469 val |= rd32(hw, GLGEN_RTRIG); 1470 wr32(hw, GLGEN_RTRIG, val); 1471 ice_flush(hw); 1472 1473 /* wait for the FW to be ready */ 1474 return ice_check_reset(hw); 1475 } 1476 1477 /** 1478 * ice_copy_rxq_ctx_to_hw 1479 * @hw: pointer to the hardware structure 1480 * @ice_rxq_ctx: pointer to the rxq context 1481 * @rxq_index: the index of the Rx queue 1482 * 1483 * Copies rxq context from dense structure to HW register space 1484 */ 1485 static int 1486 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1487 { 1488 u8 i; 1489 1490 if (!ice_rxq_ctx) 1491 return -EINVAL; 1492 1493 if (rxq_index > QRX_CTRL_MAX_INDEX) 1494 return -EINVAL; 1495 1496 /* Copy each dword separately to HW */ 1497 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1498 wr32(hw, QRX_CONTEXT(i, rxq_index), 1499 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1500 1501 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1502 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1503 } 1504 1505 return 0; 1506 } 1507 1508 /* LAN Rx Queue Context */ 1509 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1510 /* Field Width LSB */ 1511 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1512 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1513 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1514 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1515 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1516 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1517 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1518 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1519 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1520 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1521 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1522 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1523 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1524 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1525 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1526 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1527 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1528 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1529 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1530 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1531 { 0 } 1532 }; 1533 1534 /** 1535 * ice_write_rxq_ctx 1536 * @hw: pointer to the hardware structure 1537 * @rlan_ctx: pointer to the rxq context 1538 * @rxq_index: the index of the Rx queue 1539 * 1540 * Converts rxq context from sparse to dense structure and then writes 1541 * it to HW register space and enables the hardware to prefetch descriptors 1542 * instead of only fetching them on demand 1543 */ 1544 int 1545 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1546 u32 rxq_index) 1547 { 1548 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1549 1550 if (!rlan_ctx) 1551 return -EINVAL; 1552 1553 rlan_ctx->prefena = 1; 1554 1555 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1556 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1557 } 1558 1559 /* LAN Tx Queue Context */ 1560 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1561 /* Field Width LSB */ 1562 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1563 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1564 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1565 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1566 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1567 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1568 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1569 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1570 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1571 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1572 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1573 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1574 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1575 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1576 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1577 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1578 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1579 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1580 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1581 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1582 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1583 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1584 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1585 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1586 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1587 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1588 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1589 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1590 { 0 } 1591 }; 1592 1593 /* Sideband Queue command wrappers */ 1594 1595 /** 1596 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1597 * @hw: pointer to the HW struct 1598 * @desc: descriptor describing the command 1599 * @buf: buffer to use for indirect commands (NULL for direct commands) 1600 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1601 * @cd: pointer to command details structure 1602 */ 1603 static int 1604 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1605 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1606 { 1607 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1608 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1609 } 1610 1611 /** 1612 * ice_sbq_rw_reg - Fill Sideband Queue command 1613 * @hw: pointer to the HW struct 1614 * @in: message info to be filled in descriptor 1615 */ 1616 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1617 { 1618 struct ice_sbq_cmd_desc desc = {0}; 1619 struct ice_sbq_msg_req msg = {0}; 1620 u16 msg_len; 1621 int status; 1622 1623 msg_len = sizeof(msg); 1624 1625 msg.dest_dev = in->dest_dev; 1626 msg.opcode = in->opcode; 1627 msg.flags = ICE_SBQ_MSG_FLAGS; 1628 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1629 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1630 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1631 1632 if (in->opcode) 1633 msg.data = cpu_to_le32(in->data); 1634 else 1635 /* data read comes back in completion, so shorten the struct by 1636 * sizeof(msg.data) 1637 */ 1638 msg_len -= sizeof(msg.data); 1639 1640 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1641 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1642 desc.param0.cmd_len = cpu_to_le16(msg_len); 1643 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1644 if (!status && !in->opcode) 1645 in->data = le32_to_cpu 1646 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1647 return status; 1648 } 1649 1650 /* FW Admin Queue command wrappers */ 1651 1652 /* Software lock/mutex that is meant to be held while the Global Config Lock 1653 * in firmware is acquired by the software to prevent most (but not all) types 1654 * of AQ commands from being sent to FW 1655 */ 1656 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1657 1658 /** 1659 * ice_should_retry_sq_send_cmd 1660 * @opcode: AQ opcode 1661 * 1662 * Decide if we should retry the send command routine for the ATQ, depending 1663 * on the opcode. 1664 */ 1665 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1666 { 1667 switch (opcode) { 1668 case ice_aqc_opc_get_link_topo: 1669 case ice_aqc_opc_lldp_stop: 1670 case ice_aqc_opc_lldp_start: 1671 case ice_aqc_opc_lldp_filter_ctrl: 1672 return true; 1673 } 1674 1675 return false; 1676 } 1677 1678 /** 1679 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1680 * @hw: pointer to the HW struct 1681 * @cq: pointer to the specific Control queue 1682 * @desc: prefilled descriptor describing the command 1683 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1684 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1685 * @cd: pointer to command details structure 1686 * 1687 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1688 * Queue if the EBUSY AQ error is returned. 1689 */ 1690 static int 1691 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1692 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1693 struct ice_sq_cd *cd) 1694 { 1695 struct ice_aq_desc desc_cpy; 1696 bool is_cmd_for_retry; 1697 u8 idx = 0; 1698 u16 opcode; 1699 int status; 1700 1701 opcode = le16_to_cpu(desc->opcode); 1702 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1703 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1704 1705 if (is_cmd_for_retry) { 1706 /* All retryable cmds are direct, without buf. */ 1707 WARN_ON(buf); 1708 1709 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1710 } 1711 1712 do { 1713 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1714 1715 if (!is_cmd_for_retry || !status || 1716 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1717 break; 1718 1719 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1720 1721 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1722 1723 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1724 1725 return status; 1726 } 1727 1728 /** 1729 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1730 * @hw: pointer to the HW struct 1731 * @desc: descriptor describing the command 1732 * @buf: buffer to use for indirect commands (NULL for direct commands) 1733 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1734 * @cd: pointer to command details structure 1735 * 1736 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1737 */ 1738 int 1739 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1740 u16 buf_size, struct ice_sq_cd *cd) 1741 { 1742 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1743 bool lock_acquired = false; 1744 int status; 1745 1746 /* When a package download is in process (i.e. when the firmware's 1747 * Global Configuration Lock resource is held), only the Download 1748 * Package, Get Version, Get Package Info List, Upload Section, 1749 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1750 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1751 * Recipes to Profile Association, and Release Resource (with resource 1752 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1753 * must block until the package download completes and the Global Config 1754 * Lock is released. See also ice_acquire_global_cfg_lock(). 1755 */ 1756 switch (le16_to_cpu(desc->opcode)) { 1757 case ice_aqc_opc_download_pkg: 1758 case ice_aqc_opc_get_pkg_info_list: 1759 case ice_aqc_opc_get_ver: 1760 case ice_aqc_opc_upload_section: 1761 case ice_aqc_opc_update_pkg: 1762 case ice_aqc_opc_set_port_params: 1763 case ice_aqc_opc_get_vlan_mode_parameters: 1764 case ice_aqc_opc_set_vlan_mode_parameters: 1765 case ice_aqc_opc_add_recipe: 1766 case ice_aqc_opc_recipe_to_profile: 1767 case ice_aqc_opc_get_recipe: 1768 case ice_aqc_opc_get_recipe_to_profile: 1769 break; 1770 case ice_aqc_opc_release_res: 1771 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1772 break; 1773 fallthrough; 1774 default: 1775 mutex_lock(&ice_global_cfg_lock_sw); 1776 lock_acquired = true; 1777 break; 1778 } 1779 1780 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1781 if (lock_acquired) 1782 mutex_unlock(&ice_global_cfg_lock_sw); 1783 1784 return status; 1785 } 1786 1787 /** 1788 * ice_aq_get_fw_ver 1789 * @hw: pointer to the HW struct 1790 * @cd: pointer to command details structure or NULL 1791 * 1792 * Get the firmware version (0x0001) from the admin queue commands 1793 */ 1794 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1795 { 1796 struct ice_aqc_get_ver *resp; 1797 struct ice_aq_desc desc; 1798 int status; 1799 1800 resp = &desc.params.get_ver; 1801 1802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1803 1804 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1805 1806 if (!status) { 1807 hw->fw_branch = resp->fw_branch; 1808 hw->fw_maj_ver = resp->fw_major; 1809 hw->fw_min_ver = resp->fw_minor; 1810 hw->fw_patch = resp->fw_patch; 1811 hw->fw_build = le32_to_cpu(resp->fw_build); 1812 hw->api_branch = resp->api_branch; 1813 hw->api_maj_ver = resp->api_major; 1814 hw->api_min_ver = resp->api_minor; 1815 hw->api_patch = resp->api_patch; 1816 } 1817 1818 return status; 1819 } 1820 1821 /** 1822 * ice_aq_send_driver_ver 1823 * @hw: pointer to the HW struct 1824 * @dv: driver's major, minor version 1825 * @cd: pointer to command details structure or NULL 1826 * 1827 * Send the driver version (0x0002) to the firmware 1828 */ 1829 int 1830 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1831 struct ice_sq_cd *cd) 1832 { 1833 struct ice_aqc_driver_ver *cmd; 1834 struct ice_aq_desc desc; 1835 u16 len; 1836 1837 cmd = &desc.params.driver_ver; 1838 1839 if (!dv) 1840 return -EINVAL; 1841 1842 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1843 1844 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1845 cmd->major_ver = dv->major_ver; 1846 cmd->minor_ver = dv->minor_ver; 1847 cmd->build_ver = dv->build_ver; 1848 cmd->subbuild_ver = dv->subbuild_ver; 1849 1850 len = 0; 1851 while (len < sizeof(dv->driver_string) && 1852 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1853 len++; 1854 1855 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1856 } 1857 1858 /** 1859 * ice_aq_q_shutdown 1860 * @hw: pointer to the HW struct 1861 * @unloading: is the driver unloading itself 1862 * 1863 * Tell the Firmware that we're shutting down the AdminQ and whether 1864 * or not the driver is unloading as well (0x0003). 1865 */ 1866 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1867 { 1868 struct ice_aqc_q_shutdown *cmd; 1869 struct ice_aq_desc desc; 1870 1871 cmd = &desc.params.q_shutdown; 1872 1873 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1874 1875 if (unloading) 1876 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1877 1878 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1879 } 1880 1881 /** 1882 * ice_aq_req_res 1883 * @hw: pointer to the HW struct 1884 * @res: resource ID 1885 * @access: access type 1886 * @sdp_number: resource number 1887 * @timeout: the maximum time in ms that the driver may hold the resource 1888 * @cd: pointer to command details structure or NULL 1889 * 1890 * Requests common resource using the admin queue commands (0x0008). 1891 * When attempting to acquire the Global Config Lock, the driver can 1892 * learn of three states: 1893 * 1) 0 - acquired lock, and can perform download package 1894 * 2) -EIO - did not get lock, driver should fail to load 1895 * 3) -EALREADY - did not get lock, but another driver has 1896 * successfully downloaded the package; the driver does 1897 * not have to download the package and can continue 1898 * loading 1899 * 1900 * Note that if the caller is in an acquire lock, perform action, release lock 1901 * phase of operation, it is possible that the FW may detect a timeout and issue 1902 * a CORER. In this case, the driver will receive a CORER interrupt and will 1903 * have to determine its cause. The calling thread that is handling this flow 1904 * will likely get an error propagated back to it indicating the Download 1905 * Package, Update Package or the Release Resource AQ commands timed out. 1906 */ 1907 static int 1908 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1909 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1910 struct ice_sq_cd *cd) 1911 { 1912 struct ice_aqc_req_res *cmd_resp; 1913 struct ice_aq_desc desc; 1914 int status; 1915 1916 cmd_resp = &desc.params.res_owner; 1917 1918 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1919 1920 cmd_resp->res_id = cpu_to_le16(res); 1921 cmd_resp->access_type = cpu_to_le16(access); 1922 cmd_resp->res_number = cpu_to_le32(sdp_number); 1923 cmd_resp->timeout = cpu_to_le32(*timeout); 1924 *timeout = 0; 1925 1926 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1927 1928 /* The completion specifies the maximum time in ms that the driver 1929 * may hold the resource in the Timeout field. 1930 */ 1931 1932 /* Global config lock response utilizes an additional status field. 1933 * 1934 * If the Global config lock resource is held by some other driver, the 1935 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1936 * and the timeout field indicates the maximum time the current owner 1937 * of the resource has to free it. 1938 */ 1939 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1940 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1941 *timeout = le32_to_cpu(cmd_resp->timeout); 1942 return 0; 1943 } else if (le16_to_cpu(cmd_resp->status) == 1944 ICE_AQ_RES_GLBL_IN_PROG) { 1945 *timeout = le32_to_cpu(cmd_resp->timeout); 1946 return -EIO; 1947 } else if (le16_to_cpu(cmd_resp->status) == 1948 ICE_AQ_RES_GLBL_DONE) { 1949 return -EALREADY; 1950 } 1951 1952 /* invalid FW response, force a timeout immediately */ 1953 *timeout = 0; 1954 return -EIO; 1955 } 1956 1957 /* If the resource is held by some other driver, the command completes 1958 * with a busy return value and the timeout field indicates the maximum 1959 * time the current owner of the resource has to free it. 1960 */ 1961 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1962 *timeout = le32_to_cpu(cmd_resp->timeout); 1963 1964 return status; 1965 } 1966 1967 /** 1968 * ice_aq_release_res 1969 * @hw: pointer to the HW struct 1970 * @res: resource ID 1971 * @sdp_number: resource number 1972 * @cd: pointer to command details structure or NULL 1973 * 1974 * release common resource using the admin queue commands (0x0009) 1975 */ 1976 static int 1977 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1978 struct ice_sq_cd *cd) 1979 { 1980 struct ice_aqc_req_res *cmd; 1981 struct ice_aq_desc desc; 1982 1983 cmd = &desc.params.res_owner; 1984 1985 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1986 1987 cmd->res_id = cpu_to_le16(res); 1988 cmd->res_number = cpu_to_le32(sdp_number); 1989 1990 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1991 } 1992 1993 /** 1994 * ice_acquire_res 1995 * @hw: pointer to the HW structure 1996 * @res: resource ID 1997 * @access: access type (read or write) 1998 * @timeout: timeout in milliseconds 1999 * 2000 * This function will attempt to acquire the ownership of a resource. 2001 */ 2002 int 2003 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2004 enum ice_aq_res_access_type access, u32 timeout) 2005 { 2006 #define ICE_RES_POLLING_DELAY_MS 10 2007 u32 delay = ICE_RES_POLLING_DELAY_MS; 2008 u32 time_left = timeout; 2009 int status; 2010 2011 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2012 2013 /* A return code of -EALREADY means that another driver has 2014 * previously acquired the resource and performed any necessary updates; 2015 * in this case the caller does not obtain the resource and has no 2016 * further work to do. 2017 */ 2018 if (status == -EALREADY) 2019 goto ice_acquire_res_exit; 2020 2021 if (status) 2022 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2023 2024 /* If necessary, poll until the current lock owner timeouts */ 2025 timeout = time_left; 2026 while (status && timeout && time_left) { 2027 mdelay(delay); 2028 timeout = (timeout > delay) ? timeout - delay : 0; 2029 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2030 2031 if (status == -EALREADY) 2032 /* lock free, but no work to do */ 2033 break; 2034 2035 if (!status) 2036 /* lock acquired */ 2037 break; 2038 } 2039 if (status && status != -EALREADY) 2040 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2041 2042 ice_acquire_res_exit: 2043 if (status == -EALREADY) { 2044 if (access == ICE_RES_WRITE) 2045 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2046 else 2047 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2048 } 2049 return status; 2050 } 2051 2052 /** 2053 * ice_release_res 2054 * @hw: pointer to the HW structure 2055 * @res: resource ID 2056 * 2057 * This function will release a resource using the proper Admin Command. 2058 */ 2059 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2060 { 2061 unsigned long timeout; 2062 int status; 2063 2064 /* there are some rare cases when trying to release the resource 2065 * results in an admin queue timeout, so handle them correctly 2066 */ 2067 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2068 do { 2069 status = ice_aq_release_res(hw, res, 0, NULL); 2070 if (status != -EIO) 2071 break; 2072 usleep_range(1000, 2000); 2073 } while (time_before(jiffies, timeout)); 2074 } 2075 2076 /** 2077 * ice_aq_alloc_free_res - command to allocate/free resources 2078 * @hw: pointer to the HW struct 2079 * @buf: Indirect buffer to hold data parameters and response 2080 * @buf_size: size of buffer for indirect commands 2081 * @opc: pass in the command opcode 2082 * 2083 * Helper function to allocate/free resources using the admin queue commands 2084 */ 2085 int ice_aq_alloc_free_res(struct ice_hw *hw, 2086 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2087 enum ice_adminq_opc opc) 2088 { 2089 struct ice_aqc_alloc_free_res_cmd *cmd; 2090 struct ice_aq_desc desc; 2091 2092 cmd = &desc.params.sw_res_ctrl; 2093 2094 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2095 return -EINVAL; 2096 2097 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2098 2099 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2100 2101 cmd->num_entries = cpu_to_le16(1); 2102 2103 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2104 } 2105 2106 /** 2107 * ice_alloc_hw_res - allocate resource 2108 * @hw: pointer to the HW struct 2109 * @type: type of resource 2110 * @num: number of resources to allocate 2111 * @btm: allocate from bottom 2112 * @res: pointer to array that will receive the resources 2113 */ 2114 int 2115 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2116 { 2117 struct ice_aqc_alloc_free_res_elem *buf; 2118 u16 buf_len; 2119 int status; 2120 2121 buf_len = struct_size(buf, elem, num); 2122 buf = kzalloc(buf_len, GFP_KERNEL); 2123 if (!buf) 2124 return -ENOMEM; 2125 2126 /* Prepare buffer to allocate resource. */ 2127 buf->num_elems = cpu_to_le16(num); 2128 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2129 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2130 if (btm) 2131 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2132 2133 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2134 if (status) 2135 goto ice_alloc_res_exit; 2136 2137 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2138 2139 ice_alloc_res_exit: 2140 kfree(buf); 2141 return status; 2142 } 2143 2144 /** 2145 * ice_free_hw_res - free allocated HW resource 2146 * @hw: pointer to the HW struct 2147 * @type: type of resource to free 2148 * @num: number of resources 2149 * @res: pointer to array that contains the resources to free 2150 */ 2151 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2152 { 2153 struct ice_aqc_alloc_free_res_elem *buf; 2154 u16 buf_len; 2155 int status; 2156 2157 buf_len = struct_size(buf, elem, num); 2158 buf = kzalloc(buf_len, GFP_KERNEL); 2159 if (!buf) 2160 return -ENOMEM; 2161 2162 /* Prepare buffer to free resource. */ 2163 buf->num_elems = cpu_to_le16(num); 2164 buf->res_type = cpu_to_le16(type); 2165 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2166 2167 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2168 if (status) 2169 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2170 2171 kfree(buf); 2172 return status; 2173 } 2174 2175 /** 2176 * ice_get_num_per_func - determine number of resources per PF 2177 * @hw: pointer to the HW structure 2178 * @max: value to be evenly split between each PF 2179 * 2180 * Determine the number of valid functions by going through the bitmap returned 2181 * from parsing capabilities and use this to calculate the number of resources 2182 * per PF based on the max value passed in. 2183 */ 2184 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2185 { 2186 u8 funcs; 2187 2188 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2189 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2190 ICE_CAPS_VALID_FUNCS_M); 2191 2192 if (!funcs) 2193 return 0; 2194 2195 return max / funcs; 2196 } 2197 2198 /** 2199 * ice_parse_common_caps - parse common device/function capabilities 2200 * @hw: pointer to the HW struct 2201 * @caps: pointer to common capabilities structure 2202 * @elem: the capability element to parse 2203 * @prefix: message prefix for tracing capabilities 2204 * 2205 * Given a capability element, extract relevant details into the common 2206 * capability structure. 2207 * 2208 * Returns: true if the capability matches one of the common capability ids, 2209 * false otherwise. 2210 */ 2211 static bool 2212 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2213 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2214 { 2215 u32 logical_id = le32_to_cpu(elem->logical_id); 2216 u32 phys_id = le32_to_cpu(elem->phys_id); 2217 u32 number = le32_to_cpu(elem->number); 2218 u16 cap = le16_to_cpu(elem->cap); 2219 bool found = true; 2220 2221 switch (cap) { 2222 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2223 caps->valid_functions = number; 2224 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2225 caps->valid_functions); 2226 break; 2227 case ICE_AQC_CAPS_SRIOV: 2228 caps->sr_iov_1_1 = (number == 1); 2229 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2230 caps->sr_iov_1_1); 2231 break; 2232 case ICE_AQC_CAPS_DCB: 2233 caps->dcb = (number == 1); 2234 caps->active_tc_bitmap = logical_id; 2235 caps->maxtc = phys_id; 2236 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2237 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2238 caps->active_tc_bitmap); 2239 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2240 break; 2241 case ICE_AQC_CAPS_RSS: 2242 caps->rss_table_size = number; 2243 caps->rss_table_entry_width = logical_id; 2244 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2245 caps->rss_table_size); 2246 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2247 caps->rss_table_entry_width); 2248 break; 2249 case ICE_AQC_CAPS_RXQS: 2250 caps->num_rxq = number; 2251 caps->rxq_first_id = phys_id; 2252 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2253 caps->num_rxq); 2254 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2255 caps->rxq_first_id); 2256 break; 2257 case ICE_AQC_CAPS_TXQS: 2258 caps->num_txq = number; 2259 caps->txq_first_id = phys_id; 2260 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2261 caps->num_txq); 2262 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2263 caps->txq_first_id); 2264 break; 2265 case ICE_AQC_CAPS_MSIX: 2266 caps->num_msix_vectors = number; 2267 caps->msix_vector_first_id = phys_id; 2268 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2269 caps->num_msix_vectors); 2270 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2271 caps->msix_vector_first_id); 2272 break; 2273 case ICE_AQC_CAPS_PENDING_NVM_VER: 2274 caps->nvm_update_pending_nvm = true; 2275 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2276 break; 2277 case ICE_AQC_CAPS_PENDING_OROM_VER: 2278 caps->nvm_update_pending_orom = true; 2279 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2280 break; 2281 case ICE_AQC_CAPS_PENDING_NET_VER: 2282 caps->nvm_update_pending_netlist = true; 2283 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2284 break; 2285 case ICE_AQC_CAPS_NVM_MGMT: 2286 caps->nvm_unified_update = 2287 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2288 true : false; 2289 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2290 caps->nvm_unified_update); 2291 break; 2292 case ICE_AQC_CAPS_RDMA: 2293 caps->rdma = (number == 1); 2294 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2295 break; 2296 case ICE_AQC_CAPS_MAX_MTU: 2297 caps->max_mtu = number; 2298 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2299 prefix, caps->max_mtu); 2300 break; 2301 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2302 caps->pcie_reset_avoidance = (number > 0); 2303 ice_debug(hw, ICE_DBG_INIT, 2304 "%s: pcie_reset_avoidance = %d\n", prefix, 2305 caps->pcie_reset_avoidance); 2306 break; 2307 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2308 caps->reset_restrict_support = (number == 1); 2309 ice_debug(hw, ICE_DBG_INIT, 2310 "%s: reset_restrict_support = %d\n", prefix, 2311 caps->reset_restrict_support); 2312 break; 2313 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2314 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2315 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2316 prefix, caps->roce_lag); 2317 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2318 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2319 prefix, caps->sriov_lag); 2320 break; 2321 default: 2322 /* Not one of the recognized common capabilities */ 2323 found = false; 2324 } 2325 2326 return found; 2327 } 2328 2329 /** 2330 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2331 * @hw: pointer to the HW structure 2332 * @caps: pointer to capabilities structure to fix 2333 * 2334 * Re-calculate the capabilities that are dependent on the number of physical 2335 * ports; i.e. some features are not supported or function differently on 2336 * devices with more than 4 ports. 2337 */ 2338 static void 2339 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2340 { 2341 /* This assumes device capabilities are always scanned before function 2342 * capabilities during the initialization flow. 2343 */ 2344 if (hw->dev_caps.num_funcs > 4) { 2345 /* Max 4 TCs per port */ 2346 caps->maxtc = 4; 2347 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2348 caps->maxtc); 2349 if (caps->rdma) { 2350 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2351 caps->rdma = 0; 2352 } 2353 2354 /* print message only when processing device capabilities 2355 * during initialization. 2356 */ 2357 if (caps == &hw->dev_caps.common_cap) 2358 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2359 } 2360 } 2361 2362 /** 2363 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2364 * @hw: pointer to the HW struct 2365 * @func_p: pointer to function capabilities structure 2366 * @cap: pointer to the capability element to parse 2367 * 2368 * Extract function capabilities for ICE_AQC_CAPS_VF. 2369 */ 2370 static void 2371 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2372 struct ice_aqc_list_caps_elem *cap) 2373 { 2374 u32 logical_id = le32_to_cpu(cap->logical_id); 2375 u32 number = le32_to_cpu(cap->number); 2376 2377 func_p->num_allocd_vfs = number; 2378 func_p->vf_base_id = logical_id; 2379 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2380 func_p->num_allocd_vfs); 2381 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2382 func_p->vf_base_id); 2383 } 2384 2385 /** 2386 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2387 * @hw: pointer to the HW struct 2388 * @func_p: pointer to function capabilities structure 2389 * @cap: pointer to the capability element to parse 2390 * 2391 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2392 */ 2393 static void 2394 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2395 struct ice_aqc_list_caps_elem *cap) 2396 { 2397 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2398 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2399 le32_to_cpu(cap->number)); 2400 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2401 func_p->guar_num_vsi); 2402 } 2403 2404 /** 2405 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2406 * @hw: pointer to the HW struct 2407 * @func_p: pointer to function capabilities structure 2408 * @cap: pointer to the capability element to parse 2409 * 2410 * Extract function capabilities for ICE_AQC_CAPS_1588. 2411 */ 2412 static void 2413 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2414 struct ice_aqc_list_caps_elem *cap) 2415 { 2416 struct ice_ts_func_info *info = &func_p->ts_func_info; 2417 u32 number = le32_to_cpu(cap->number); 2418 2419 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2420 func_p->common_cap.ieee_1588 = info->ena; 2421 2422 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2423 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2424 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2425 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2426 2427 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2428 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2429 2430 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2431 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2432 } else { 2433 /* Unknown clock frequency, so assume a (probably incorrect) 2434 * default to avoid out-of-bounds look ups of frequency 2435 * related information. 2436 */ 2437 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2438 info->clk_freq); 2439 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2440 } 2441 2442 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2443 func_p->common_cap.ieee_1588); 2444 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2445 info->src_tmr_owned); 2446 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2447 info->tmr_ena); 2448 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2449 info->tmr_index_owned); 2450 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2451 info->tmr_index_assoc); 2452 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2453 info->clk_freq); 2454 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2455 info->clk_src); 2456 } 2457 2458 /** 2459 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2460 * @hw: pointer to the HW struct 2461 * @func_p: pointer to function capabilities structure 2462 * 2463 * Extract function capabilities for ICE_AQC_CAPS_FD. 2464 */ 2465 static void 2466 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2467 { 2468 u32 reg_val, val; 2469 2470 reg_val = rd32(hw, GLQF_FD_SIZE); 2471 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2472 GLQF_FD_SIZE_FD_GSIZE_S; 2473 func_p->fd_fltr_guar = 2474 ice_get_num_per_func(hw, val); 2475 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2476 GLQF_FD_SIZE_FD_BSIZE_S; 2477 func_p->fd_fltr_best_effort = val; 2478 2479 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2480 func_p->fd_fltr_guar); 2481 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2482 func_p->fd_fltr_best_effort); 2483 } 2484 2485 /** 2486 * ice_parse_func_caps - Parse function capabilities 2487 * @hw: pointer to the HW struct 2488 * @func_p: pointer to function capabilities structure 2489 * @buf: buffer containing the function capability records 2490 * @cap_count: the number of capabilities 2491 * 2492 * Helper function to parse function (0x000A) capabilities list. For 2493 * capabilities shared between device and function, this relies on 2494 * ice_parse_common_caps. 2495 * 2496 * Loop through the list of provided capabilities and extract the relevant 2497 * data into the function capabilities structured. 2498 */ 2499 static void 2500 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2501 void *buf, u32 cap_count) 2502 { 2503 struct ice_aqc_list_caps_elem *cap_resp; 2504 u32 i; 2505 2506 cap_resp = buf; 2507 2508 memset(func_p, 0, sizeof(*func_p)); 2509 2510 for (i = 0; i < cap_count; i++) { 2511 u16 cap = le16_to_cpu(cap_resp[i].cap); 2512 bool found; 2513 2514 found = ice_parse_common_caps(hw, &func_p->common_cap, 2515 &cap_resp[i], "func caps"); 2516 2517 switch (cap) { 2518 case ICE_AQC_CAPS_VF: 2519 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2520 break; 2521 case ICE_AQC_CAPS_VSI: 2522 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2523 break; 2524 case ICE_AQC_CAPS_1588: 2525 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2526 break; 2527 case ICE_AQC_CAPS_FD: 2528 ice_parse_fdir_func_caps(hw, func_p); 2529 break; 2530 default: 2531 /* Don't list common capabilities as unknown */ 2532 if (!found) 2533 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2534 i, cap); 2535 break; 2536 } 2537 } 2538 2539 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2540 } 2541 2542 /** 2543 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2544 * @hw: pointer to the HW struct 2545 * @dev_p: pointer to device capabilities structure 2546 * @cap: capability element to parse 2547 * 2548 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2549 */ 2550 static void 2551 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2552 struct ice_aqc_list_caps_elem *cap) 2553 { 2554 u32 number = le32_to_cpu(cap->number); 2555 2556 dev_p->num_funcs = hweight32(number); 2557 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2558 dev_p->num_funcs); 2559 } 2560 2561 /** 2562 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2563 * @hw: pointer to the HW struct 2564 * @dev_p: pointer to device capabilities structure 2565 * @cap: capability element to parse 2566 * 2567 * Parse ICE_AQC_CAPS_VF for device capabilities. 2568 */ 2569 static void 2570 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2571 struct ice_aqc_list_caps_elem *cap) 2572 { 2573 u32 number = le32_to_cpu(cap->number); 2574 2575 dev_p->num_vfs_exposed = number; 2576 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2577 dev_p->num_vfs_exposed); 2578 } 2579 2580 /** 2581 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2582 * @hw: pointer to the HW struct 2583 * @dev_p: pointer to device capabilities structure 2584 * @cap: capability element to parse 2585 * 2586 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2587 */ 2588 static void 2589 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2590 struct ice_aqc_list_caps_elem *cap) 2591 { 2592 u32 number = le32_to_cpu(cap->number); 2593 2594 dev_p->num_vsi_allocd_to_host = number; 2595 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2596 dev_p->num_vsi_allocd_to_host); 2597 } 2598 2599 /** 2600 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2601 * @hw: pointer to the HW struct 2602 * @dev_p: pointer to device capabilities structure 2603 * @cap: capability element to parse 2604 * 2605 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2606 */ 2607 static void 2608 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2609 struct ice_aqc_list_caps_elem *cap) 2610 { 2611 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2612 u32 logical_id = le32_to_cpu(cap->logical_id); 2613 u32 phys_id = le32_to_cpu(cap->phys_id); 2614 u32 number = le32_to_cpu(cap->number); 2615 2616 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2617 dev_p->common_cap.ieee_1588 = info->ena; 2618 2619 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2620 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2621 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2622 2623 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2624 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2625 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2626 2627 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2628 2629 info->ena_ports = logical_id; 2630 info->tmr_own_map = phys_id; 2631 2632 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2633 dev_p->common_cap.ieee_1588); 2634 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2635 info->tmr0_owner); 2636 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2637 info->tmr0_owned); 2638 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2639 info->tmr0_ena); 2640 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2641 info->tmr1_owner); 2642 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2643 info->tmr1_owned); 2644 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2645 info->tmr1_ena); 2646 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2647 info->ts_ll_read); 2648 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2649 info->ena_ports); 2650 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2651 info->tmr_own_map); 2652 } 2653 2654 /** 2655 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2656 * @hw: pointer to the HW struct 2657 * @dev_p: pointer to device capabilities structure 2658 * @cap: capability element to parse 2659 * 2660 * Parse ICE_AQC_CAPS_FD for device capabilities. 2661 */ 2662 static void 2663 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2664 struct ice_aqc_list_caps_elem *cap) 2665 { 2666 u32 number = le32_to_cpu(cap->number); 2667 2668 dev_p->num_flow_director_fltr = number; 2669 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2670 dev_p->num_flow_director_fltr); 2671 } 2672 2673 /** 2674 * ice_parse_dev_caps - Parse device capabilities 2675 * @hw: pointer to the HW struct 2676 * @dev_p: pointer to device capabilities structure 2677 * @buf: buffer containing the device capability records 2678 * @cap_count: the number of capabilities 2679 * 2680 * Helper device to parse device (0x000B) capabilities list. For 2681 * capabilities shared between device and function, this relies on 2682 * ice_parse_common_caps. 2683 * 2684 * Loop through the list of provided capabilities and extract the relevant 2685 * data into the device capabilities structured. 2686 */ 2687 static void 2688 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2689 void *buf, u32 cap_count) 2690 { 2691 struct ice_aqc_list_caps_elem *cap_resp; 2692 u32 i; 2693 2694 cap_resp = buf; 2695 2696 memset(dev_p, 0, sizeof(*dev_p)); 2697 2698 for (i = 0; i < cap_count; i++) { 2699 u16 cap = le16_to_cpu(cap_resp[i].cap); 2700 bool found; 2701 2702 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2703 &cap_resp[i], "dev caps"); 2704 2705 switch (cap) { 2706 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2707 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2708 break; 2709 case ICE_AQC_CAPS_VF: 2710 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2711 break; 2712 case ICE_AQC_CAPS_VSI: 2713 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2714 break; 2715 case ICE_AQC_CAPS_1588: 2716 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2717 break; 2718 case ICE_AQC_CAPS_FD: 2719 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2720 break; 2721 default: 2722 /* Don't list common capabilities as unknown */ 2723 if (!found) 2724 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2725 i, cap); 2726 break; 2727 } 2728 } 2729 2730 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2731 } 2732 2733 /** 2734 * ice_is_pf_c827 - check if pf contains c827 phy 2735 * @hw: pointer to the hw struct 2736 */ 2737 bool ice_is_pf_c827(struct ice_hw *hw) 2738 { 2739 struct ice_aqc_get_link_topo cmd = {}; 2740 u8 node_part_number; 2741 u16 node_handle; 2742 int status; 2743 2744 if (hw->mac_type != ICE_MAC_E810) 2745 return false; 2746 2747 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 2748 return true; 2749 2750 cmd.addr.topo_params.node_type_ctx = 2751 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 2752 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 2753 cmd.addr.topo_params.index = 0; 2754 2755 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 2756 &node_handle); 2757 2758 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 2759 return false; 2760 2761 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 2762 return true; 2763 2764 return false; 2765 } 2766 2767 /** 2768 * ice_is_gps_in_netlist 2769 * @hw: pointer to the hw struct 2770 * 2771 * Check if the GPS generic device is present in the netlist 2772 */ 2773 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2774 { 2775 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2776 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 2777 return false; 2778 2779 return true; 2780 } 2781 2782 /** 2783 * ice_aq_list_caps - query function/device capabilities 2784 * @hw: pointer to the HW struct 2785 * @buf: a buffer to hold the capabilities 2786 * @buf_size: size of the buffer 2787 * @cap_count: if not NULL, set to the number of capabilities reported 2788 * @opc: capabilities type to discover, device or function 2789 * @cd: pointer to command details structure or NULL 2790 * 2791 * Get the function (0x000A) or device (0x000B) capabilities description from 2792 * firmware and store it in the buffer. 2793 * 2794 * If the cap_count pointer is not NULL, then it is set to the number of 2795 * capabilities firmware will report. Note that if the buffer size is too 2796 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2797 * cap_count will still be updated in this case. It is recommended that the 2798 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2799 * firmware could return) to avoid this. 2800 */ 2801 int 2802 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2803 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2804 { 2805 struct ice_aqc_list_caps *cmd; 2806 struct ice_aq_desc desc; 2807 int status; 2808 2809 cmd = &desc.params.get_cap; 2810 2811 if (opc != ice_aqc_opc_list_func_caps && 2812 opc != ice_aqc_opc_list_dev_caps) 2813 return -EINVAL; 2814 2815 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2816 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2817 2818 if (cap_count) 2819 *cap_count = le32_to_cpu(cmd->count); 2820 2821 return status; 2822 } 2823 2824 /** 2825 * ice_discover_dev_caps - Read and extract device capabilities 2826 * @hw: pointer to the hardware structure 2827 * @dev_caps: pointer to device capabilities structure 2828 * 2829 * Read the device capabilities and extract them into the dev_caps structure 2830 * for later use. 2831 */ 2832 int 2833 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2834 { 2835 u32 cap_count = 0; 2836 void *cbuf; 2837 int status; 2838 2839 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2840 if (!cbuf) 2841 return -ENOMEM; 2842 2843 /* Although the driver doesn't know the number of capabilities the 2844 * device will return, we can simply send a 4KB buffer, the maximum 2845 * possible size that firmware can return. 2846 */ 2847 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2848 2849 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2850 ice_aqc_opc_list_dev_caps, NULL); 2851 if (!status) 2852 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2853 kfree(cbuf); 2854 2855 return status; 2856 } 2857 2858 /** 2859 * ice_discover_func_caps - Read and extract function capabilities 2860 * @hw: pointer to the hardware structure 2861 * @func_caps: pointer to function capabilities structure 2862 * 2863 * Read the function capabilities and extract them into the func_caps structure 2864 * for later use. 2865 */ 2866 static int 2867 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2868 { 2869 u32 cap_count = 0; 2870 void *cbuf; 2871 int status; 2872 2873 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2874 if (!cbuf) 2875 return -ENOMEM; 2876 2877 /* Although the driver doesn't know the number of capabilities the 2878 * device will return, we can simply send a 4KB buffer, the maximum 2879 * possible size that firmware can return. 2880 */ 2881 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2882 2883 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2884 ice_aqc_opc_list_func_caps, NULL); 2885 if (!status) 2886 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2887 kfree(cbuf); 2888 2889 return status; 2890 } 2891 2892 /** 2893 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2894 * @hw: pointer to the hardware structure 2895 */ 2896 void ice_set_safe_mode_caps(struct ice_hw *hw) 2897 { 2898 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2899 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2900 struct ice_hw_common_caps cached_caps; 2901 u32 num_funcs; 2902 2903 /* cache some func_caps values that should be restored after memset */ 2904 cached_caps = func_caps->common_cap; 2905 2906 /* unset func capabilities */ 2907 memset(func_caps, 0, sizeof(*func_caps)); 2908 2909 #define ICE_RESTORE_FUNC_CAP(name) \ 2910 func_caps->common_cap.name = cached_caps.name 2911 2912 /* restore cached values */ 2913 ICE_RESTORE_FUNC_CAP(valid_functions); 2914 ICE_RESTORE_FUNC_CAP(txq_first_id); 2915 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2916 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2917 ICE_RESTORE_FUNC_CAP(max_mtu); 2918 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2919 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2920 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2921 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2922 2923 /* one Tx and one Rx queue in safe mode */ 2924 func_caps->common_cap.num_rxq = 1; 2925 func_caps->common_cap.num_txq = 1; 2926 2927 /* two MSIX vectors, one for traffic and one for misc causes */ 2928 func_caps->common_cap.num_msix_vectors = 2; 2929 func_caps->guar_num_vsi = 1; 2930 2931 /* cache some dev_caps values that should be restored after memset */ 2932 cached_caps = dev_caps->common_cap; 2933 num_funcs = dev_caps->num_funcs; 2934 2935 /* unset dev capabilities */ 2936 memset(dev_caps, 0, sizeof(*dev_caps)); 2937 2938 #define ICE_RESTORE_DEV_CAP(name) \ 2939 dev_caps->common_cap.name = cached_caps.name 2940 2941 /* restore cached values */ 2942 ICE_RESTORE_DEV_CAP(valid_functions); 2943 ICE_RESTORE_DEV_CAP(txq_first_id); 2944 ICE_RESTORE_DEV_CAP(rxq_first_id); 2945 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2946 ICE_RESTORE_DEV_CAP(max_mtu); 2947 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2948 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2949 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2950 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2951 dev_caps->num_funcs = num_funcs; 2952 2953 /* one Tx and one Rx queue per function in safe mode */ 2954 dev_caps->common_cap.num_rxq = num_funcs; 2955 dev_caps->common_cap.num_txq = num_funcs; 2956 2957 /* two MSIX vectors per function */ 2958 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2959 } 2960 2961 /** 2962 * ice_get_caps - get info about the HW 2963 * @hw: pointer to the hardware structure 2964 */ 2965 int ice_get_caps(struct ice_hw *hw) 2966 { 2967 int status; 2968 2969 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2970 if (status) 2971 return status; 2972 2973 return ice_discover_func_caps(hw, &hw->func_caps); 2974 } 2975 2976 /** 2977 * ice_aq_manage_mac_write - manage MAC address write command 2978 * @hw: pointer to the HW struct 2979 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2980 * @flags: flags to control write behavior 2981 * @cd: pointer to command details structure or NULL 2982 * 2983 * This function is used to write MAC address to the NVM (0x0108). 2984 */ 2985 int 2986 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2987 struct ice_sq_cd *cd) 2988 { 2989 struct ice_aqc_manage_mac_write *cmd; 2990 struct ice_aq_desc desc; 2991 2992 cmd = &desc.params.mac_write; 2993 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2994 2995 cmd->flags = flags; 2996 ether_addr_copy(cmd->mac_addr, mac_addr); 2997 2998 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2999 } 3000 3001 /** 3002 * ice_aq_clear_pxe_mode 3003 * @hw: pointer to the HW struct 3004 * 3005 * Tell the firmware that the driver is taking over from PXE (0x0110). 3006 */ 3007 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3008 { 3009 struct ice_aq_desc desc; 3010 3011 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3012 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3013 3014 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3015 } 3016 3017 /** 3018 * ice_clear_pxe_mode - clear pxe operations mode 3019 * @hw: pointer to the HW struct 3020 * 3021 * Make sure all PXE mode settings are cleared, including things 3022 * like descriptor fetch/write-back mode. 3023 */ 3024 void ice_clear_pxe_mode(struct ice_hw *hw) 3025 { 3026 if (ice_check_sq_alive(hw, &hw->adminq)) 3027 ice_aq_clear_pxe_mode(hw); 3028 } 3029 3030 /** 3031 * ice_aq_set_port_params - set physical port parameters. 3032 * @pi: pointer to the port info struct 3033 * @double_vlan: if set double VLAN is enabled 3034 * @cd: pointer to command details structure or NULL 3035 * 3036 * Set Physical port parameters (0x0203) 3037 */ 3038 int 3039 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3040 struct ice_sq_cd *cd) 3041 3042 { 3043 struct ice_aqc_set_port_params *cmd; 3044 struct ice_hw *hw = pi->hw; 3045 struct ice_aq_desc desc; 3046 u16 cmd_flags = 0; 3047 3048 cmd = &desc.params.set_port_params; 3049 3050 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3051 if (double_vlan) 3052 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3053 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3054 3055 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3056 } 3057 3058 /** 3059 * ice_is_100m_speed_supported 3060 * @hw: pointer to the HW struct 3061 * 3062 * returns true if 100M speeds are supported by the device, 3063 * false otherwise. 3064 */ 3065 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3066 { 3067 switch (hw->device_id) { 3068 case ICE_DEV_ID_E822C_SGMII: 3069 case ICE_DEV_ID_E822L_SGMII: 3070 case ICE_DEV_ID_E823L_1GBE: 3071 case ICE_DEV_ID_E823C_SGMII: 3072 return true; 3073 default: 3074 return false; 3075 } 3076 } 3077 3078 /** 3079 * ice_get_link_speed_based_on_phy_type - returns link speed 3080 * @phy_type_low: lower part of phy_type 3081 * @phy_type_high: higher part of phy_type 3082 * 3083 * This helper function will convert an entry in PHY type structure 3084 * [phy_type_low, phy_type_high] to its corresponding link speed. 3085 * Note: In the structure of [phy_type_low, phy_type_high], there should 3086 * be one bit set, as this function will convert one PHY type to its 3087 * speed. 3088 * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3089 * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3090 */ 3091 static u16 3092 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3093 { 3094 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3095 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3096 3097 switch (phy_type_low) { 3098 case ICE_PHY_TYPE_LOW_100BASE_TX: 3099 case ICE_PHY_TYPE_LOW_100M_SGMII: 3100 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3101 break; 3102 case ICE_PHY_TYPE_LOW_1000BASE_T: 3103 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3104 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3105 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3106 case ICE_PHY_TYPE_LOW_1G_SGMII: 3107 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3108 break; 3109 case ICE_PHY_TYPE_LOW_2500BASE_T: 3110 case ICE_PHY_TYPE_LOW_2500BASE_X: 3111 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3112 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3113 break; 3114 case ICE_PHY_TYPE_LOW_5GBASE_T: 3115 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3116 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3117 break; 3118 case ICE_PHY_TYPE_LOW_10GBASE_T: 3119 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3120 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3121 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3122 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3123 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3124 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3125 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3126 break; 3127 case ICE_PHY_TYPE_LOW_25GBASE_T: 3128 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3129 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3130 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3131 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3132 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3133 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3134 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3135 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3136 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3137 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3138 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3139 break; 3140 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3141 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3142 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3143 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3144 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3145 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3146 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3147 break; 3148 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3149 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3150 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3151 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3152 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3153 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3154 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3155 case ICE_PHY_TYPE_LOW_50G_AUI2: 3156 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3157 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3158 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3159 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3160 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3161 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3162 case ICE_PHY_TYPE_LOW_50G_AUI1: 3163 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3164 break; 3165 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3166 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3167 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3168 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3169 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3170 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3171 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3172 case ICE_PHY_TYPE_LOW_100G_AUI4: 3173 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3174 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3175 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3176 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3177 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3178 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3179 break; 3180 default: 3181 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3182 break; 3183 } 3184 3185 switch (phy_type_high) { 3186 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3187 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3188 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3189 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3190 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3191 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3192 break; 3193 default: 3194 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3195 break; 3196 } 3197 3198 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3199 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3200 return ICE_AQ_LINK_SPEED_UNKNOWN; 3201 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3202 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3203 return ICE_AQ_LINK_SPEED_UNKNOWN; 3204 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3205 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3206 return speed_phy_type_low; 3207 else 3208 return speed_phy_type_high; 3209 } 3210 3211 /** 3212 * ice_update_phy_type 3213 * @phy_type_low: pointer to the lower part of phy_type 3214 * @phy_type_high: pointer to the higher part of phy_type 3215 * @link_speeds_bitmap: targeted link speeds bitmap 3216 * 3217 * Note: For the link_speeds_bitmap structure, you can check it at 3218 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3219 * link_speeds_bitmap include multiple speeds. 3220 * 3221 * Each entry in this [phy_type_low, phy_type_high] structure will 3222 * present a certain link speed. This helper function will turn on bits 3223 * in [phy_type_low, phy_type_high] structure based on the value of 3224 * link_speeds_bitmap input parameter. 3225 */ 3226 void 3227 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3228 u16 link_speeds_bitmap) 3229 { 3230 u64 pt_high; 3231 u64 pt_low; 3232 int index; 3233 u16 speed; 3234 3235 /* We first check with low part of phy_type */ 3236 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3237 pt_low = BIT_ULL(index); 3238 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3239 3240 if (link_speeds_bitmap & speed) 3241 *phy_type_low |= BIT_ULL(index); 3242 } 3243 3244 /* We then check with high part of phy_type */ 3245 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3246 pt_high = BIT_ULL(index); 3247 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3248 3249 if (link_speeds_bitmap & speed) 3250 *phy_type_high |= BIT_ULL(index); 3251 } 3252 } 3253 3254 /** 3255 * ice_aq_set_phy_cfg 3256 * @hw: pointer to the HW struct 3257 * @pi: port info structure of the interested logical port 3258 * @cfg: structure with PHY configuration data to be set 3259 * @cd: pointer to command details structure or NULL 3260 * 3261 * Set the various PHY configuration parameters supported on the Port. 3262 * One or more of the Set PHY config parameters may be ignored in an MFP 3263 * mode as the PF may not have the privilege to set some of the PHY Config 3264 * parameters. This status will be indicated by the command response (0x0601). 3265 */ 3266 int 3267 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3268 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3269 { 3270 struct ice_aq_desc desc; 3271 int status; 3272 3273 if (!cfg) 3274 return -EINVAL; 3275 3276 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3277 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3278 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3279 cfg->caps); 3280 3281 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3282 } 3283 3284 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3285 desc.params.set_phy.lport_num = pi->lport; 3286 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3287 3288 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3289 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3290 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3291 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3292 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3293 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3294 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3295 cfg->low_power_ctrl_an); 3296 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3297 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3298 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3299 cfg->link_fec_opt); 3300 3301 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3302 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3303 status = 0; 3304 3305 if (!status) 3306 pi->phy.curr_user_phy_cfg = *cfg; 3307 3308 return status; 3309 } 3310 3311 /** 3312 * ice_update_link_info - update status of the HW network link 3313 * @pi: port info structure of the interested logical port 3314 */ 3315 int ice_update_link_info(struct ice_port_info *pi) 3316 { 3317 struct ice_link_status *li; 3318 int status; 3319 3320 if (!pi) 3321 return -EINVAL; 3322 3323 li = &pi->phy.link_info; 3324 3325 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3326 if (status) 3327 return status; 3328 3329 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3330 struct ice_aqc_get_phy_caps_data *pcaps; 3331 struct ice_hw *hw; 3332 3333 hw = pi->hw; 3334 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3335 GFP_KERNEL); 3336 if (!pcaps) 3337 return -ENOMEM; 3338 3339 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3340 pcaps, NULL); 3341 3342 devm_kfree(ice_hw_to_dev(hw), pcaps); 3343 } 3344 3345 return status; 3346 } 3347 3348 /** 3349 * ice_cache_phy_user_req 3350 * @pi: port information structure 3351 * @cache_data: PHY logging data 3352 * @cache_mode: PHY logging mode 3353 * 3354 * Log the user request on (FC, FEC, SPEED) for later use. 3355 */ 3356 static void 3357 ice_cache_phy_user_req(struct ice_port_info *pi, 3358 struct ice_phy_cache_mode_data cache_data, 3359 enum ice_phy_cache_mode cache_mode) 3360 { 3361 if (!pi) 3362 return; 3363 3364 switch (cache_mode) { 3365 case ICE_FC_MODE: 3366 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3367 break; 3368 case ICE_SPEED_MODE: 3369 pi->phy.curr_user_speed_req = 3370 cache_data.data.curr_user_speed_req; 3371 break; 3372 case ICE_FEC_MODE: 3373 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3374 break; 3375 default: 3376 break; 3377 } 3378 } 3379 3380 /** 3381 * ice_caps_to_fc_mode 3382 * @caps: PHY capabilities 3383 * 3384 * Convert PHY FC capabilities to ice FC mode 3385 */ 3386 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3387 { 3388 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3389 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3390 return ICE_FC_FULL; 3391 3392 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3393 return ICE_FC_TX_PAUSE; 3394 3395 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3396 return ICE_FC_RX_PAUSE; 3397 3398 return ICE_FC_NONE; 3399 } 3400 3401 /** 3402 * ice_caps_to_fec_mode 3403 * @caps: PHY capabilities 3404 * @fec_options: Link FEC options 3405 * 3406 * Convert PHY FEC capabilities to ice FEC mode 3407 */ 3408 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3409 { 3410 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3411 return ICE_FEC_AUTO; 3412 3413 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3414 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3415 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3416 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3417 return ICE_FEC_BASER; 3418 3419 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3420 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3421 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3422 return ICE_FEC_RS; 3423 3424 return ICE_FEC_NONE; 3425 } 3426 3427 /** 3428 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3429 * @pi: port information structure 3430 * @cfg: PHY configuration data to set FC mode 3431 * @req_mode: FC mode to configure 3432 */ 3433 int 3434 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3435 enum ice_fc_mode req_mode) 3436 { 3437 struct ice_phy_cache_mode_data cache_data; 3438 u8 pause_mask = 0x0; 3439 3440 if (!pi || !cfg) 3441 return -EINVAL; 3442 3443 switch (req_mode) { 3444 case ICE_FC_FULL: 3445 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3446 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3447 break; 3448 case ICE_FC_RX_PAUSE: 3449 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3450 break; 3451 case ICE_FC_TX_PAUSE: 3452 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3453 break; 3454 default: 3455 break; 3456 } 3457 3458 /* clear the old pause settings */ 3459 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3460 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3461 3462 /* set the new capabilities */ 3463 cfg->caps |= pause_mask; 3464 3465 /* Cache user FC request */ 3466 cache_data.data.curr_user_fc_req = req_mode; 3467 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3468 3469 return 0; 3470 } 3471 3472 /** 3473 * ice_set_fc 3474 * @pi: port information structure 3475 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3476 * @ena_auto_link_update: enable automatic link update 3477 * 3478 * Set the requested flow control mode. 3479 */ 3480 int 3481 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3482 { 3483 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3484 struct ice_aqc_get_phy_caps_data *pcaps; 3485 struct ice_hw *hw; 3486 int status; 3487 3488 if (!pi || !aq_failures) 3489 return -EINVAL; 3490 3491 *aq_failures = 0; 3492 hw = pi->hw; 3493 3494 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3495 if (!pcaps) 3496 return -ENOMEM; 3497 3498 /* Get the current PHY config */ 3499 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3500 pcaps, NULL); 3501 if (status) { 3502 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3503 goto out; 3504 } 3505 3506 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3507 3508 /* Configure the set PHY data */ 3509 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3510 if (status) 3511 goto out; 3512 3513 /* If the capabilities have changed, then set the new config */ 3514 if (cfg.caps != pcaps->caps) { 3515 int retry_count, retry_max = 10; 3516 3517 /* Auto restart link so settings take effect */ 3518 if (ena_auto_link_update) 3519 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3520 3521 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3522 if (status) { 3523 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3524 goto out; 3525 } 3526 3527 /* Update the link info 3528 * It sometimes takes a really long time for link to 3529 * come back from the atomic reset. Thus, we wait a 3530 * little bit. 3531 */ 3532 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3533 status = ice_update_link_info(pi); 3534 3535 if (!status) 3536 break; 3537 3538 mdelay(100); 3539 } 3540 3541 if (status) 3542 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3543 } 3544 3545 out: 3546 devm_kfree(ice_hw_to_dev(hw), pcaps); 3547 return status; 3548 } 3549 3550 /** 3551 * ice_phy_caps_equals_cfg 3552 * @phy_caps: PHY capabilities 3553 * @phy_cfg: PHY configuration 3554 * 3555 * Helper function to determine if PHY capabilities matches PHY 3556 * configuration 3557 */ 3558 bool 3559 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3560 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3561 { 3562 u8 caps_mask, cfg_mask; 3563 3564 if (!phy_caps || !phy_cfg) 3565 return false; 3566 3567 /* These bits are not common between capabilities and configuration. 3568 * Do not use them to determine equality. 3569 */ 3570 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3571 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3572 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3573 3574 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3575 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3576 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3577 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3578 phy_caps->eee_cap != phy_cfg->eee_cap || 3579 phy_caps->eeer_value != phy_cfg->eeer_value || 3580 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3581 return false; 3582 3583 return true; 3584 } 3585 3586 /** 3587 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3588 * @pi: port information structure 3589 * @caps: PHY ability structure to copy date from 3590 * @cfg: PHY configuration structure to copy data to 3591 * 3592 * Helper function to copy AQC PHY get ability data to PHY set configuration 3593 * data structure 3594 */ 3595 void 3596 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3597 struct ice_aqc_get_phy_caps_data *caps, 3598 struct ice_aqc_set_phy_cfg_data *cfg) 3599 { 3600 if (!pi || !caps || !cfg) 3601 return; 3602 3603 memset(cfg, 0, sizeof(*cfg)); 3604 cfg->phy_type_low = caps->phy_type_low; 3605 cfg->phy_type_high = caps->phy_type_high; 3606 cfg->caps = caps->caps; 3607 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3608 cfg->eee_cap = caps->eee_cap; 3609 cfg->eeer_value = caps->eeer_value; 3610 cfg->link_fec_opt = caps->link_fec_options; 3611 cfg->module_compliance_enforcement = 3612 caps->module_compliance_enforcement; 3613 } 3614 3615 /** 3616 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3617 * @pi: port information structure 3618 * @cfg: PHY configuration data to set FEC mode 3619 * @fec: FEC mode to configure 3620 */ 3621 int 3622 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3623 enum ice_fec_mode fec) 3624 { 3625 struct ice_aqc_get_phy_caps_data *pcaps; 3626 struct ice_hw *hw; 3627 int status; 3628 3629 if (!pi || !cfg) 3630 return -EINVAL; 3631 3632 hw = pi->hw; 3633 3634 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3635 if (!pcaps) 3636 return -ENOMEM; 3637 3638 status = ice_aq_get_phy_caps(pi, false, 3639 (ice_fw_supports_report_dflt_cfg(hw) ? 3640 ICE_AQC_REPORT_DFLT_CFG : 3641 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3642 if (status) 3643 goto out; 3644 3645 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3646 cfg->link_fec_opt = pcaps->link_fec_options; 3647 3648 switch (fec) { 3649 case ICE_FEC_BASER: 3650 /* Clear RS bits, and AND BASE-R ability 3651 * bits and OR request bits. 3652 */ 3653 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3654 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3655 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3656 ICE_AQC_PHY_FEC_25G_KR_REQ; 3657 break; 3658 case ICE_FEC_RS: 3659 /* Clear BASE-R bits, and AND RS ability 3660 * bits and OR request bits. 3661 */ 3662 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3663 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3664 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3665 break; 3666 case ICE_FEC_NONE: 3667 /* Clear all FEC option bits. */ 3668 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3669 break; 3670 case ICE_FEC_AUTO: 3671 /* AND auto FEC bit, and all caps bits. */ 3672 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3673 cfg->link_fec_opt |= pcaps->link_fec_options; 3674 break; 3675 default: 3676 status = -EINVAL; 3677 break; 3678 } 3679 3680 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3681 !ice_fw_supports_report_dflt_cfg(hw)) { 3682 struct ice_link_default_override_tlv tlv = { 0 }; 3683 3684 status = ice_get_link_default_override(&tlv, pi); 3685 if (status) 3686 goto out; 3687 3688 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3689 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3690 cfg->link_fec_opt = tlv.fec_options; 3691 } 3692 3693 out: 3694 kfree(pcaps); 3695 3696 return status; 3697 } 3698 3699 /** 3700 * ice_get_link_status - get status of the HW network link 3701 * @pi: port information structure 3702 * @link_up: pointer to bool (true/false = linkup/linkdown) 3703 * 3704 * Variable link_up is true if link is up, false if link is down. 3705 * The variable link_up is invalid if status is non zero. As a 3706 * result of this call, link status reporting becomes enabled 3707 */ 3708 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3709 { 3710 struct ice_phy_info *phy_info; 3711 int status = 0; 3712 3713 if (!pi || !link_up) 3714 return -EINVAL; 3715 3716 phy_info = &pi->phy; 3717 3718 if (phy_info->get_link_info) { 3719 status = ice_update_link_info(pi); 3720 3721 if (status) 3722 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3723 status); 3724 } 3725 3726 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3727 3728 return status; 3729 } 3730 3731 /** 3732 * ice_aq_set_link_restart_an 3733 * @pi: pointer to the port information structure 3734 * @ena_link: if true: enable link, if false: disable link 3735 * @cd: pointer to command details structure or NULL 3736 * 3737 * Sets up the link and restarts the Auto-Negotiation over the link. 3738 */ 3739 int 3740 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3741 struct ice_sq_cd *cd) 3742 { 3743 struct ice_aqc_restart_an *cmd; 3744 struct ice_aq_desc desc; 3745 3746 cmd = &desc.params.restart_an; 3747 3748 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3749 3750 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3751 cmd->lport_num = pi->lport; 3752 if (ena_link) 3753 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3754 else 3755 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3756 3757 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3758 } 3759 3760 /** 3761 * ice_aq_set_event_mask 3762 * @hw: pointer to the HW struct 3763 * @port_num: port number of the physical function 3764 * @mask: event mask to be set 3765 * @cd: pointer to command details structure or NULL 3766 * 3767 * Set event mask (0x0613) 3768 */ 3769 int 3770 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3771 struct ice_sq_cd *cd) 3772 { 3773 struct ice_aqc_set_event_mask *cmd; 3774 struct ice_aq_desc desc; 3775 3776 cmd = &desc.params.set_event_mask; 3777 3778 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3779 3780 cmd->lport_num = port_num; 3781 3782 cmd->event_mask = cpu_to_le16(mask); 3783 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3784 } 3785 3786 /** 3787 * ice_aq_set_mac_loopback 3788 * @hw: pointer to the HW struct 3789 * @ena_lpbk: Enable or Disable loopback 3790 * @cd: pointer to command details structure or NULL 3791 * 3792 * Enable/disable loopback on a given port 3793 */ 3794 int 3795 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3796 { 3797 struct ice_aqc_set_mac_lb *cmd; 3798 struct ice_aq_desc desc; 3799 3800 cmd = &desc.params.set_mac_lb; 3801 3802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3803 if (ena_lpbk) 3804 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3805 3806 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3807 } 3808 3809 /** 3810 * ice_aq_set_port_id_led 3811 * @pi: pointer to the port information 3812 * @is_orig_mode: is this LED set to original mode (by the net-list) 3813 * @cd: pointer to command details structure or NULL 3814 * 3815 * Set LED value for the given port (0x06e9) 3816 */ 3817 int 3818 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3819 struct ice_sq_cd *cd) 3820 { 3821 struct ice_aqc_set_port_id_led *cmd; 3822 struct ice_hw *hw = pi->hw; 3823 struct ice_aq_desc desc; 3824 3825 cmd = &desc.params.set_port_id_led; 3826 3827 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3828 3829 if (is_orig_mode) 3830 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3831 else 3832 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3833 3834 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3835 } 3836 3837 /** 3838 * ice_aq_get_port_options 3839 * @hw: pointer to the HW struct 3840 * @options: buffer for the resultant port options 3841 * @option_count: input - size of the buffer in port options structures, 3842 * output - number of returned port options 3843 * @lport: logical port to call the command with (optional) 3844 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3845 * when PF owns more than 1 port it must be true 3846 * @active_option_idx: index of active port option in returned buffer 3847 * @active_option_valid: active option in returned buffer is valid 3848 * @pending_option_idx: index of pending port option in returned buffer 3849 * @pending_option_valid: pending option in returned buffer is valid 3850 * 3851 * Calls Get Port Options AQC (0x06ea) and verifies result. 3852 */ 3853 int 3854 ice_aq_get_port_options(struct ice_hw *hw, 3855 struct ice_aqc_get_port_options_elem *options, 3856 u8 *option_count, u8 lport, bool lport_valid, 3857 u8 *active_option_idx, bool *active_option_valid, 3858 u8 *pending_option_idx, bool *pending_option_valid) 3859 { 3860 struct ice_aqc_get_port_options *cmd; 3861 struct ice_aq_desc desc; 3862 int status; 3863 u8 i; 3864 3865 /* options buffer shall be able to hold max returned options */ 3866 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3867 return -EINVAL; 3868 3869 cmd = &desc.params.get_port_options; 3870 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3871 3872 if (lport_valid) 3873 cmd->lport_num = lport; 3874 cmd->lport_num_valid = lport_valid; 3875 3876 status = ice_aq_send_cmd(hw, &desc, options, 3877 *option_count * sizeof(*options), NULL); 3878 if (status) 3879 return status; 3880 3881 /* verify direct FW response & set output parameters */ 3882 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3883 cmd->port_options_count); 3884 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3885 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3886 cmd->port_options); 3887 if (*active_option_valid) { 3888 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3889 cmd->port_options); 3890 if (*active_option_idx > (*option_count - 1)) 3891 return -EIO; 3892 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3893 *active_option_idx); 3894 } 3895 3896 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3897 cmd->pending_port_option_status); 3898 if (*pending_option_valid) { 3899 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3900 cmd->pending_port_option_status); 3901 if (*pending_option_idx > (*option_count - 1)) 3902 return -EIO; 3903 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3904 *pending_option_idx); 3905 } 3906 3907 /* mask output options fields */ 3908 for (i = 0; i < *option_count; i++) { 3909 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3910 options[i].pmd); 3911 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3912 options[i].max_lane_speed); 3913 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3914 options[i].pmd, options[i].max_lane_speed); 3915 } 3916 3917 return 0; 3918 } 3919 3920 /** 3921 * ice_aq_set_port_option 3922 * @hw: pointer to the HW struct 3923 * @lport: logical port to call the command with 3924 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3925 * when PF owns more than 1 port it must be true 3926 * @new_option: new port option to be written 3927 * 3928 * Calls Set Port Options AQC (0x06eb). 3929 */ 3930 int 3931 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3932 u8 new_option) 3933 { 3934 struct ice_aqc_set_port_option *cmd; 3935 struct ice_aq_desc desc; 3936 3937 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3938 return -EINVAL; 3939 3940 cmd = &desc.params.set_port_option; 3941 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3942 3943 if (lport_valid) 3944 cmd->lport_num = lport; 3945 3946 cmd->lport_num_valid = lport_valid; 3947 cmd->selected_port_option = new_option; 3948 3949 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3950 } 3951 3952 /** 3953 * ice_aq_sff_eeprom 3954 * @hw: pointer to the HW struct 3955 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3956 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3957 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3958 * @page: QSFP page 3959 * @set_page: set or ignore the page 3960 * @data: pointer to data buffer to be read/written to the I2C device. 3961 * @length: 1-16 for read, 1 for write. 3962 * @write: 0 read, 1 for write. 3963 * @cd: pointer to command details structure or NULL 3964 * 3965 * Read/Write SFF EEPROM (0x06EE) 3966 */ 3967 int 3968 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3969 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3970 bool write, struct ice_sq_cd *cd) 3971 { 3972 struct ice_aqc_sff_eeprom *cmd; 3973 struct ice_aq_desc desc; 3974 int status; 3975 3976 if (!data || (mem_addr & 0xff00)) 3977 return -EINVAL; 3978 3979 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3980 cmd = &desc.params.read_write_sff_param; 3981 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3982 cmd->lport_num = (u8)(lport & 0xff); 3983 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3984 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3985 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3986 ((set_page << 3987 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3988 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3989 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3990 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3991 if (write) 3992 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3993 3994 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3995 return status; 3996 } 3997 3998 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 3999 { 4000 switch (type) { 4001 case ICE_LUT_VSI: 4002 return ICE_LUT_VSI_SIZE; 4003 case ICE_LUT_GLOBAL: 4004 return ICE_LUT_GLOBAL_SIZE; 4005 case ICE_LUT_PF: 4006 return ICE_LUT_PF_SIZE; 4007 } 4008 WARN_ONCE(1, "incorrect type passed"); 4009 return ICE_LUT_VSI_SIZE; 4010 } 4011 4012 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4013 { 4014 switch (size) { 4015 case ICE_LUT_VSI_SIZE: 4016 return ICE_AQC_LUT_SIZE_SMALL; 4017 case ICE_LUT_GLOBAL_SIZE: 4018 return ICE_AQC_LUT_SIZE_512; 4019 case ICE_LUT_PF_SIZE: 4020 return ICE_AQC_LUT_SIZE_2K; 4021 } 4022 WARN_ONCE(1, "incorrect size passed"); 4023 return 0; 4024 } 4025 4026 /** 4027 * __ice_aq_get_set_rss_lut 4028 * @hw: pointer to the hardware structure 4029 * @params: RSS LUT parameters 4030 * @set: set true to set the table, false to get the table 4031 * 4032 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4033 */ 4034 static int 4035 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4036 struct ice_aq_get_set_rss_lut_params *params, bool set) 4037 { 4038 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4039 enum ice_lut_type lut_type = params->lut_type; 4040 struct ice_aqc_get_set_rss_lut *desc_params; 4041 enum ice_aqc_lut_flags flags; 4042 enum ice_lut_size lut_size; 4043 struct ice_aq_desc desc; 4044 u8 *lut = params->lut; 4045 4046 4047 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4048 return -EINVAL; 4049 4050 lut_size = ice_lut_type_to_size(lut_type); 4051 if (lut_size > params->lut_size) 4052 return -EINVAL; 4053 else if (set && lut_size != params->lut_size) 4054 return -EINVAL; 4055 4056 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4057 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4058 if (set) 4059 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4060 4061 desc_params = &desc.params.get_set_rss_lut; 4062 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4063 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4064 4065 if (lut_type == ICE_LUT_GLOBAL) 4066 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4067 params->global_lut_id); 4068 4069 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4070 desc_params->flags = cpu_to_le16(flags); 4071 4072 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4073 } 4074 4075 /** 4076 * ice_aq_get_rss_lut 4077 * @hw: pointer to the hardware structure 4078 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4079 * 4080 * get the RSS lookup table, PF or VSI type 4081 */ 4082 int 4083 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4084 { 4085 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4086 } 4087 4088 /** 4089 * ice_aq_set_rss_lut 4090 * @hw: pointer to the hardware structure 4091 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4092 * 4093 * set the RSS lookup table, PF or VSI type 4094 */ 4095 int 4096 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4097 { 4098 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4099 } 4100 4101 /** 4102 * __ice_aq_get_set_rss_key 4103 * @hw: pointer to the HW struct 4104 * @vsi_id: VSI FW index 4105 * @key: pointer to key info struct 4106 * @set: set true to set the key, false to get the key 4107 * 4108 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4109 */ 4110 static int 4111 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4112 struct ice_aqc_get_set_rss_keys *key, bool set) 4113 { 4114 struct ice_aqc_get_set_rss_key *desc_params; 4115 u16 key_size = sizeof(*key); 4116 struct ice_aq_desc desc; 4117 4118 if (set) { 4119 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4120 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4121 } else { 4122 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4123 } 4124 4125 desc_params = &desc.params.get_set_rss_key; 4126 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4127 4128 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4129 } 4130 4131 /** 4132 * ice_aq_get_rss_key 4133 * @hw: pointer to the HW struct 4134 * @vsi_handle: software VSI handle 4135 * @key: pointer to key info struct 4136 * 4137 * get the RSS key per VSI 4138 */ 4139 int 4140 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4141 struct ice_aqc_get_set_rss_keys *key) 4142 { 4143 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4144 return -EINVAL; 4145 4146 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4147 key, false); 4148 } 4149 4150 /** 4151 * ice_aq_set_rss_key 4152 * @hw: pointer to the HW struct 4153 * @vsi_handle: software VSI handle 4154 * @keys: pointer to key info struct 4155 * 4156 * set the RSS key per VSI 4157 */ 4158 int 4159 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4160 struct ice_aqc_get_set_rss_keys *keys) 4161 { 4162 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4163 return -EINVAL; 4164 4165 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4166 keys, true); 4167 } 4168 4169 /** 4170 * ice_aq_add_lan_txq 4171 * @hw: pointer to the hardware structure 4172 * @num_qgrps: Number of added queue groups 4173 * @qg_list: list of queue groups to be added 4174 * @buf_size: size of buffer for indirect command 4175 * @cd: pointer to command details structure or NULL 4176 * 4177 * Add Tx LAN queue (0x0C30) 4178 * 4179 * NOTE: 4180 * Prior to calling add Tx LAN queue: 4181 * Initialize the following as part of the Tx queue context: 4182 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4183 * Cache profile and Packet shaper profile. 4184 * 4185 * After add Tx LAN queue AQ command is completed: 4186 * Interrupts should be associated with specific queues, 4187 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4188 * flow. 4189 */ 4190 static int 4191 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4192 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4193 struct ice_sq_cd *cd) 4194 { 4195 struct ice_aqc_add_tx_qgrp *list; 4196 struct ice_aqc_add_txqs *cmd; 4197 struct ice_aq_desc desc; 4198 u16 i, sum_size = 0; 4199 4200 cmd = &desc.params.add_txqs; 4201 4202 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4203 4204 if (!qg_list) 4205 return -EINVAL; 4206 4207 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4208 return -EINVAL; 4209 4210 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4211 sum_size += struct_size(list, txqs, list->num_txqs); 4212 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4213 list->num_txqs); 4214 } 4215 4216 if (buf_size != sum_size) 4217 return -EINVAL; 4218 4219 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4220 4221 cmd->num_qgrps = num_qgrps; 4222 4223 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4224 } 4225 4226 /** 4227 * ice_aq_dis_lan_txq 4228 * @hw: pointer to the hardware structure 4229 * @num_qgrps: number of groups in the list 4230 * @qg_list: the list of groups to disable 4231 * @buf_size: the total size of the qg_list buffer in bytes 4232 * @rst_src: if called due to reset, specifies the reset source 4233 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4234 * @cd: pointer to command details structure or NULL 4235 * 4236 * Disable LAN Tx queue (0x0C31) 4237 */ 4238 static int 4239 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4240 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4241 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4242 struct ice_sq_cd *cd) 4243 { 4244 struct ice_aqc_dis_txq_item *item; 4245 struct ice_aqc_dis_txqs *cmd; 4246 struct ice_aq_desc desc; 4247 u16 i, sz = 0; 4248 int status; 4249 4250 cmd = &desc.params.dis_txqs; 4251 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4252 4253 /* qg_list can be NULL only in VM/VF reset flow */ 4254 if (!qg_list && !rst_src) 4255 return -EINVAL; 4256 4257 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4258 return -EINVAL; 4259 4260 cmd->num_entries = num_qgrps; 4261 4262 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4263 ICE_AQC_Q_DIS_TIMEOUT_M); 4264 4265 switch (rst_src) { 4266 case ICE_VM_RESET: 4267 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4268 cmd->vmvf_and_timeout |= 4269 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4270 break; 4271 case ICE_VF_RESET: 4272 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4273 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4274 cmd->vmvf_and_timeout |= 4275 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4276 ICE_AQC_Q_DIS_VMVF_NUM_M); 4277 break; 4278 case ICE_NO_RESET: 4279 default: 4280 break; 4281 } 4282 4283 /* flush pipe on time out */ 4284 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4285 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4286 if (!qg_list) 4287 goto do_aq; 4288 4289 /* set RD bit to indicate that command buffer is provided by the driver 4290 * and it needs to be read by the firmware 4291 */ 4292 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4293 4294 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4295 u16 item_size = struct_size(item, q_id, item->num_qs); 4296 4297 /* If the num of queues is even, add 2 bytes of padding */ 4298 if ((item->num_qs % 2) == 0) 4299 item_size += 2; 4300 4301 sz += item_size; 4302 4303 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4304 } 4305 4306 if (buf_size != sz) 4307 return -EINVAL; 4308 4309 do_aq: 4310 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4311 if (status) { 4312 if (!qg_list) 4313 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4314 vmvf_num, hw->adminq.sq_last_status); 4315 else 4316 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4317 le16_to_cpu(qg_list[0].q_id[0]), 4318 hw->adminq.sq_last_status); 4319 } 4320 return status; 4321 } 4322 4323 /** 4324 * ice_aq_cfg_lan_txq 4325 * @hw: pointer to the hardware structure 4326 * @buf: buffer for command 4327 * @buf_size: size of buffer in bytes 4328 * @num_qs: number of queues being configured 4329 * @oldport: origination lport 4330 * @newport: destination lport 4331 * @cd: pointer to command details structure or NULL 4332 * 4333 * Move/Configure LAN Tx queue (0x0C32) 4334 * 4335 * There is a better AQ command to use for moving nodes, so only coding 4336 * this one for configuring the node. 4337 */ 4338 int 4339 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4340 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4341 struct ice_sq_cd *cd) 4342 { 4343 struct ice_aqc_cfg_txqs *cmd; 4344 struct ice_aq_desc desc; 4345 int status; 4346 4347 cmd = &desc.params.cfg_txqs; 4348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4349 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4350 4351 if (!buf) 4352 return -EINVAL; 4353 4354 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4355 cmd->num_qs = num_qs; 4356 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4357 cmd->port_num_chng |= (newport << ICE_AQC_Q_CFG_DST_PRT_S) & 4358 ICE_AQC_Q_CFG_DST_PRT_M; 4359 cmd->time_out = (5 << ICE_AQC_Q_CFG_TIMEOUT_S) & 4360 ICE_AQC_Q_CFG_TIMEOUT_M; 4361 cmd->blocked_cgds = 0; 4362 4363 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4364 if (status) 4365 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4366 hw->adminq.sq_last_status); 4367 return status; 4368 } 4369 4370 /** 4371 * ice_aq_add_rdma_qsets 4372 * @hw: pointer to the hardware structure 4373 * @num_qset_grps: Number of RDMA Qset groups 4374 * @qset_list: list of Qset groups to be added 4375 * @buf_size: size of buffer for indirect command 4376 * @cd: pointer to command details structure or NULL 4377 * 4378 * Add Tx RDMA Qsets (0x0C33) 4379 */ 4380 static int 4381 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4382 struct ice_aqc_add_rdma_qset_data *qset_list, 4383 u16 buf_size, struct ice_sq_cd *cd) 4384 { 4385 struct ice_aqc_add_rdma_qset_data *list; 4386 struct ice_aqc_add_rdma_qset *cmd; 4387 struct ice_aq_desc desc; 4388 u16 i, sum_size = 0; 4389 4390 cmd = &desc.params.add_rdma_qset; 4391 4392 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4393 4394 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4395 return -EINVAL; 4396 4397 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4398 u16 num_qsets = le16_to_cpu(list->num_qsets); 4399 4400 sum_size += struct_size(list, rdma_qsets, num_qsets); 4401 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4402 num_qsets); 4403 } 4404 4405 if (buf_size != sum_size) 4406 return -EINVAL; 4407 4408 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4409 4410 cmd->num_qset_grps = num_qset_grps; 4411 4412 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4413 } 4414 4415 /* End of FW Admin Queue command wrappers */ 4416 4417 /** 4418 * ice_write_byte - write a byte to a packed context structure 4419 * @src_ctx: the context structure to read from 4420 * @dest_ctx: the context to be written to 4421 * @ce_info: a description of the struct to be filled 4422 */ 4423 static void 4424 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4425 { 4426 u8 src_byte, dest_byte, mask; 4427 u8 *from, *dest; 4428 u16 shift_width; 4429 4430 /* copy from the next struct field */ 4431 from = src_ctx + ce_info->offset; 4432 4433 /* prepare the bits and mask */ 4434 shift_width = ce_info->lsb % 8; 4435 mask = (u8)(BIT(ce_info->width) - 1); 4436 4437 src_byte = *from; 4438 src_byte &= mask; 4439 4440 /* shift to correct alignment */ 4441 mask <<= shift_width; 4442 src_byte <<= shift_width; 4443 4444 /* get the current bits from the target bit string */ 4445 dest = dest_ctx + (ce_info->lsb / 8); 4446 4447 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4448 4449 dest_byte &= ~mask; /* get the bits not changing */ 4450 dest_byte |= src_byte; /* add in the new bits */ 4451 4452 /* put it all back */ 4453 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4454 } 4455 4456 /** 4457 * ice_write_word - write a word to a packed context structure 4458 * @src_ctx: the context structure to read from 4459 * @dest_ctx: the context to be written to 4460 * @ce_info: a description of the struct to be filled 4461 */ 4462 static void 4463 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4464 { 4465 u16 src_word, mask; 4466 __le16 dest_word; 4467 u8 *from, *dest; 4468 u16 shift_width; 4469 4470 /* copy from the next struct field */ 4471 from = src_ctx + ce_info->offset; 4472 4473 /* prepare the bits and mask */ 4474 shift_width = ce_info->lsb % 8; 4475 mask = BIT(ce_info->width) - 1; 4476 4477 /* don't swizzle the bits until after the mask because the mask bits 4478 * will be in a different bit position on big endian machines 4479 */ 4480 src_word = *(u16 *)from; 4481 src_word &= mask; 4482 4483 /* shift to correct alignment */ 4484 mask <<= shift_width; 4485 src_word <<= shift_width; 4486 4487 /* get the current bits from the target bit string */ 4488 dest = dest_ctx + (ce_info->lsb / 8); 4489 4490 memcpy(&dest_word, dest, sizeof(dest_word)); 4491 4492 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4493 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4494 4495 /* put it all back */ 4496 memcpy(dest, &dest_word, sizeof(dest_word)); 4497 } 4498 4499 /** 4500 * ice_write_dword - write a dword to a packed context structure 4501 * @src_ctx: the context structure to read from 4502 * @dest_ctx: the context to be written to 4503 * @ce_info: a description of the struct to be filled 4504 */ 4505 static void 4506 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4507 { 4508 u32 src_dword, mask; 4509 __le32 dest_dword; 4510 u8 *from, *dest; 4511 u16 shift_width; 4512 4513 /* copy from the next struct field */ 4514 from = src_ctx + ce_info->offset; 4515 4516 /* prepare the bits and mask */ 4517 shift_width = ce_info->lsb % 8; 4518 4519 /* if the field width is exactly 32 on an x86 machine, then the shift 4520 * operation will not work because the SHL instructions count is masked 4521 * to 5 bits so the shift will do nothing 4522 */ 4523 if (ce_info->width < 32) 4524 mask = BIT(ce_info->width) - 1; 4525 else 4526 mask = (u32)~0; 4527 4528 /* don't swizzle the bits until after the mask because the mask bits 4529 * will be in a different bit position on big endian machines 4530 */ 4531 src_dword = *(u32 *)from; 4532 src_dword &= mask; 4533 4534 /* shift to correct alignment */ 4535 mask <<= shift_width; 4536 src_dword <<= shift_width; 4537 4538 /* get the current bits from the target bit string */ 4539 dest = dest_ctx + (ce_info->lsb / 8); 4540 4541 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4542 4543 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4544 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4545 4546 /* put it all back */ 4547 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4548 } 4549 4550 /** 4551 * ice_write_qword - write a qword to a packed context structure 4552 * @src_ctx: the context structure to read from 4553 * @dest_ctx: the context to be written to 4554 * @ce_info: a description of the struct to be filled 4555 */ 4556 static void 4557 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4558 { 4559 u64 src_qword, mask; 4560 __le64 dest_qword; 4561 u8 *from, *dest; 4562 u16 shift_width; 4563 4564 /* copy from the next struct field */ 4565 from = src_ctx + ce_info->offset; 4566 4567 /* prepare the bits and mask */ 4568 shift_width = ce_info->lsb % 8; 4569 4570 /* if the field width is exactly 64 on an x86 machine, then the shift 4571 * operation will not work because the SHL instructions count is masked 4572 * to 6 bits so the shift will do nothing 4573 */ 4574 if (ce_info->width < 64) 4575 mask = BIT_ULL(ce_info->width) - 1; 4576 else 4577 mask = (u64)~0; 4578 4579 /* don't swizzle the bits until after the mask because the mask bits 4580 * will be in a different bit position on big endian machines 4581 */ 4582 src_qword = *(u64 *)from; 4583 src_qword &= mask; 4584 4585 /* shift to correct alignment */ 4586 mask <<= shift_width; 4587 src_qword <<= shift_width; 4588 4589 /* get the current bits from the target bit string */ 4590 dest = dest_ctx + (ce_info->lsb / 8); 4591 4592 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4593 4594 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4595 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4596 4597 /* put it all back */ 4598 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4599 } 4600 4601 /** 4602 * ice_set_ctx - set context bits in packed structure 4603 * @hw: pointer to the hardware structure 4604 * @src_ctx: pointer to a generic non-packed context structure 4605 * @dest_ctx: pointer to memory for the packed structure 4606 * @ce_info: a description of the structure to be transformed 4607 */ 4608 int 4609 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4610 const struct ice_ctx_ele *ce_info) 4611 { 4612 int f; 4613 4614 for (f = 0; ce_info[f].width; f++) { 4615 /* We have to deal with each element of the FW response 4616 * using the correct size so that we are correct regardless 4617 * of the endianness of the machine. 4618 */ 4619 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4620 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4621 f, ce_info[f].width, ce_info[f].size_of); 4622 continue; 4623 } 4624 switch (ce_info[f].size_of) { 4625 case sizeof(u8): 4626 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4627 break; 4628 case sizeof(u16): 4629 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4630 break; 4631 case sizeof(u32): 4632 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4633 break; 4634 case sizeof(u64): 4635 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4636 break; 4637 default: 4638 return -EINVAL; 4639 } 4640 } 4641 4642 return 0; 4643 } 4644 4645 /** 4646 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4647 * @hw: pointer to the HW struct 4648 * @vsi_handle: software VSI handle 4649 * @tc: TC number 4650 * @q_handle: software queue handle 4651 */ 4652 struct ice_q_ctx * 4653 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4654 { 4655 struct ice_vsi_ctx *vsi; 4656 struct ice_q_ctx *q_ctx; 4657 4658 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4659 if (!vsi) 4660 return NULL; 4661 if (q_handle >= vsi->num_lan_q_entries[tc]) 4662 return NULL; 4663 if (!vsi->lan_q_ctx[tc]) 4664 return NULL; 4665 q_ctx = vsi->lan_q_ctx[tc]; 4666 return &q_ctx[q_handle]; 4667 } 4668 4669 /** 4670 * ice_ena_vsi_txq 4671 * @pi: port information structure 4672 * @vsi_handle: software VSI handle 4673 * @tc: TC number 4674 * @q_handle: software queue handle 4675 * @num_qgrps: Number of added queue groups 4676 * @buf: list of queue groups to be added 4677 * @buf_size: size of buffer for indirect command 4678 * @cd: pointer to command details structure or NULL 4679 * 4680 * This function adds one LAN queue 4681 */ 4682 int 4683 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4684 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4685 struct ice_sq_cd *cd) 4686 { 4687 struct ice_aqc_txsched_elem_data node = { 0 }; 4688 struct ice_sched_node *parent; 4689 struct ice_q_ctx *q_ctx; 4690 struct ice_hw *hw; 4691 int status; 4692 4693 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4694 return -EIO; 4695 4696 if (num_qgrps > 1 || buf->num_txqs > 1) 4697 return -ENOSPC; 4698 4699 hw = pi->hw; 4700 4701 if (!ice_is_vsi_valid(hw, vsi_handle)) 4702 return -EINVAL; 4703 4704 mutex_lock(&pi->sched_lock); 4705 4706 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4707 if (!q_ctx) { 4708 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4709 q_handle); 4710 status = -EINVAL; 4711 goto ena_txq_exit; 4712 } 4713 4714 /* find a parent node */ 4715 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4716 ICE_SCHED_NODE_OWNER_LAN); 4717 if (!parent) { 4718 status = -EINVAL; 4719 goto ena_txq_exit; 4720 } 4721 4722 buf->parent_teid = parent->info.node_teid; 4723 node.parent_teid = parent->info.node_teid; 4724 /* Mark that the values in the "generic" section as valid. The default 4725 * value in the "generic" section is zero. This means that : 4726 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4727 * - 0 priority among siblings, indicated by Bit 1-3. 4728 * - WFQ, indicated by Bit 4. 4729 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4730 * Bit 5-6. 4731 * - Bit 7 is reserved. 4732 * Without setting the generic section as valid in valid_sections, the 4733 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4734 */ 4735 buf->txqs[0].info.valid_sections = 4736 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4737 ICE_AQC_ELEM_VALID_EIR; 4738 buf->txqs[0].info.generic = 0; 4739 buf->txqs[0].info.cir_bw.bw_profile_idx = 4740 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4741 buf->txqs[0].info.cir_bw.bw_alloc = 4742 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4743 buf->txqs[0].info.eir_bw.bw_profile_idx = 4744 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4745 buf->txqs[0].info.eir_bw.bw_alloc = 4746 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4747 4748 /* add the LAN queue */ 4749 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4750 if (status) { 4751 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4752 le16_to_cpu(buf->txqs[0].txq_id), 4753 hw->adminq.sq_last_status); 4754 goto ena_txq_exit; 4755 } 4756 4757 node.node_teid = buf->txqs[0].q_teid; 4758 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4759 q_ctx->q_handle = q_handle; 4760 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4761 4762 /* add a leaf node into scheduler tree queue layer */ 4763 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4764 if (!status) 4765 status = ice_sched_replay_q_bw(pi, q_ctx); 4766 4767 ena_txq_exit: 4768 mutex_unlock(&pi->sched_lock); 4769 return status; 4770 } 4771 4772 /** 4773 * ice_dis_vsi_txq 4774 * @pi: port information structure 4775 * @vsi_handle: software VSI handle 4776 * @tc: TC number 4777 * @num_queues: number of queues 4778 * @q_handles: pointer to software queue handle array 4779 * @q_ids: pointer to the q_id array 4780 * @q_teids: pointer to queue node teids 4781 * @rst_src: if called due to reset, specifies the reset source 4782 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4783 * @cd: pointer to command details structure or NULL 4784 * 4785 * This function removes queues and their corresponding nodes in SW DB 4786 */ 4787 int 4788 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4789 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4790 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4791 struct ice_sq_cd *cd) 4792 { 4793 struct ice_aqc_dis_txq_item *qg_list; 4794 struct ice_q_ctx *q_ctx; 4795 int status = -ENOENT; 4796 struct ice_hw *hw; 4797 u16 i, buf_size; 4798 4799 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4800 return -EIO; 4801 4802 hw = pi->hw; 4803 4804 if (!num_queues) { 4805 /* if queue is disabled already yet the disable queue command 4806 * has to be sent to complete the VF reset, then call 4807 * ice_aq_dis_lan_txq without any queue information 4808 */ 4809 if (rst_src) 4810 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4811 vmvf_num, NULL); 4812 return -EIO; 4813 } 4814 4815 buf_size = struct_size(qg_list, q_id, 1); 4816 qg_list = kzalloc(buf_size, GFP_KERNEL); 4817 if (!qg_list) 4818 return -ENOMEM; 4819 4820 mutex_lock(&pi->sched_lock); 4821 4822 for (i = 0; i < num_queues; i++) { 4823 struct ice_sched_node *node; 4824 4825 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4826 if (!node) 4827 continue; 4828 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4829 if (!q_ctx) { 4830 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4831 q_handles[i]); 4832 continue; 4833 } 4834 if (q_ctx->q_handle != q_handles[i]) { 4835 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4836 q_ctx->q_handle, q_handles[i]); 4837 continue; 4838 } 4839 qg_list->parent_teid = node->info.parent_teid; 4840 qg_list->num_qs = 1; 4841 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4842 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4843 vmvf_num, cd); 4844 4845 if (status) 4846 break; 4847 ice_free_sched_node(pi, node); 4848 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4849 q_ctx->q_teid = ICE_INVAL_TEID; 4850 } 4851 mutex_unlock(&pi->sched_lock); 4852 kfree(qg_list); 4853 return status; 4854 } 4855 4856 /** 4857 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4858 * @pi: port information structure 4859 * @vsi_handle: software VSI handle 4860 * @tc_bitmap: TC bitmap 4861 * @maxqs: max queues array per TC 4862 * @owner: LAN or RDMA 4863 * 4864 * This function adds/updates the VSI queues per TC. 4865 */ 4866 static int 4867 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4868 u16 *maxqs, u8 owner) 4869 { 4870 int status = 0; 4871 u8 i; 4872 4873 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4874 return -EIO; 4875 4876 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4877 return -EINVAL; 4878 4879 mutex_lock(&pi->sched_lock); 4880 4881 ice_for_each_traffic_class(i) { 4882 /* configuration is possible only if TC node is present */ 4883 if (!ice_sched_get_tc_node(pi, i)) 4884 continue; 4885 4886 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4887 ice_is_tc_ena(tc_bitmap, i)); 4888 if (status) 4889 break; 4890 } 4891 4892 mutex_unlock(&pi->sched_lock); 4893 return status; 4894 } 4895 4896 /** 4897 * ice_cfg_vsi_lan - configure VSI LAN queues 4898 * @pi: port information structure 4899 * @vsi_handle: software VSI handle 4900 * @tc_bitmap: TC bitmap 4901 * @max_lanqs: max LAN queues array per TC 4902 * 4903 * This function adds/updates the VSI LAN queues per TC. 4904 */ 4905 int 4906 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4907 u16 *max_lanqs) 4908 { 4909 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4910 ICE_SCHED_NODE_OWNER_LAN); 4911 } 4912 4913 /** 4914 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4915 * @pi: port information structure 4916 * @vsi_handle: software VSI handle 4917 * @tc_bitmap: TC bitmap 4918 * @max_rdmaqs: max RDMA queues array per TC 4919 * 4920 * This function adds/updates the VSI RDMA queues per TC. 4921 */ 4922 int 4923 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4924 u16 *max_rdmaqs) 4925 { 4926 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4927 ICE_SCHED_NODE_OWNER_RDMA); 4928 } 4929 4930 /** 4931 * ice_ena_vsi_rdma_qset 4932 * @pi: port information structure 4933 * @vsi_handle: software VSI handle 4934 * @tc: TC number 4935 * @rdma_qset: pointer to RDMA Qset 4936 * @num_qsets: number of RDMA Qsets 4937 * @qset_teid: pointer to Qset node TEIDs 4938 * 4939 * This function adds RDMA Qset 4940 */ 4941 int 4942 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4943 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4944 { 4945 struct ice_aqc_txsched_elem_data node = { 0 }; 4946 struct ice_aqc_add_rdma_qset_data *buf; 4947 struct ice_sched_node *parent; 4948 struct ice_hw *hw; 4949 u16 i, buf_size; 4950 int ret; 4951 4952 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4953 return -EIO; 4954 hw = pi->hw; 4955 4956 if (!ice_is_vsi_valid(hw, vsi_handle)) 4957 return -EINVAL; 4958 4959 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4960 buf = kzalloc(buf_size, GFP_KERNEL); 4961 if (!buf) 4962 return -ENOMEM; 4963 mutex_lock(&pi->sched_lock); 4964 4965 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4966 ICE_SCHED_NODE_OWNER_RDMA); 4967 if (!parent) { 4968 ret = -EINVAL; 4969 goto rdma_error_exit; 4970 } 4971 buf->parent_teid = parent->info.node_teid; 4972 node.parent_teid = parent->info.node_teid; 4973 4974 buf->num_qsets = cpu_to_le16(num_qsets); 4975 for (i = 0; i < num_qsets; i++) { 4976 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4977 buf->rdma_qsets[i].info.valid_sections = 4978 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4979 ICE_AQC_ELEM_VALID_EIR; 4980 buf->rdma_qsets[i].info.generic = 0; 4981 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4982 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4983 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4984 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4985 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4986 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4987 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4988 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4989 } 4990 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4991 if (ret) { 4992 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4993 goto rdma_error_exit; 4994 } 4995 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4996 for (i = 0; i < num_qsets; i++) { 4997 node.node_teid = buf->rdma_qsets[i].qset_teid; 4998 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4999 &node, NULL); 5000 if (ret) 5001 break; 5002 qset_teid[i] = le32_to_cpu(node.node_teid); 5003 } 5004 rdma_error_exit: 5005 mutex_unlock(&pi->sched_lock); 5006 kfree(buf); 5007 return ret; 5008 } 5009 5010 /** 5011 * ice_dis_vsi_rdma_qset - free RDMA resources 5012 * @pi: port_info struct 5013 * @count: number of RDMA Qsets to free 5014 * @qset_teid: TEID of Qset node 5015 * @q_id: list of queue IDs being disabled 5016 */ 5017 int 5018 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5019 u16 *q_id) 5020 { 5021 struct ice_aqc_dis_txq_item *qg_list; 5022 struct ice_hw *hw; 5023 int status = 0; 5024 u16 qg_size; 5025 int i; 5026 5027 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5028 return -EIO; 5029 5030 hw = pi->hw; 5031 5032 qg_size = struct_size(qg_list, q_id, 1); 5033 qg_list = kzalloc(qg_size, GFP_KERNEL); 5034 if (!qg_list) 5035 return -ENOMEM; 5036 5037 mutex_lock(&pi->sched_lock); 5038 5039 for (i = 0; i < count; i++) { 5040 struct ice_sched_node *node; 5041 5042 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5043 if (!node) 5044 continue; 5045 5046 qg_list->parent_teid = node->info.parent_teid; 5047 qg_list->num_qs = 1; 5048 qg_list->q_id[0] = 5049 cpu_to_le16(q_id[i] | 5050 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5051 5052 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5053 ICE_NO_RESET, 0, NULL); 5054 if (status) 5055 break; 5056 5057 ice_free_sched_node(pi, node); 5058 } 5059 5060 mutex_unlock(&pi->sched_lock); 5061 kfree(qg_list); 5062 return status; 5063 } 5064 5065 /** 5066 * ice_aq_get_cgu_abilities - get cgu abilities 5067 * @hw: pointer to the HW struct 5068 * @abilities: CGU abilities 5069 * 5070 * Get CGU abilities (0x0C61) 5071 * Return: 0 on success or negative value on failure. 5072 */ 5073 int 5074 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5075 struct ice_aqc_get_cgu_abilities *abilities) 5076 { 5077 struct ice_aq_desc desc; 5078 5079 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5080 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5081 } 5082 5083 /** 5084 * ice_aq_set_input_pin_cfg - set input pin config 5085 * @hw: pointer to the HW struct 5086 * @input_idx: Input index 5087 * @flags1: Input flags 5088 * @flags2: Input flags 5089 * @freq: Frequency in Hz 5090 * @phase_delay: Delay in ps 5091 * 5092 * Set CGU input config (0x0C62) 5093 * Return: 0 on success or negative value on failure. 5094 */ 5095 int 5096 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5097 u32 freq, s32 phase_delay) 5098 { 5099 struct ice_aqc_set_cgu_input_config *cmd; 5100 struct ice_aq_desc desc; 5101 5102 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5103 cmd = &desc.params.set_cgu_input_config; 5104 cmd->input_idx = input_idx; 5105 cmd->flags1 = flags1; 5106 cmd->flags2 = flags2; 5107 cmd->freq = cpu_to_le32(freq); 5108 cmd->phase_delay = cpu_to_le32(phase_delay); 5109 5110 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5111 } 5112 5113 /** 5114 * ice_aq_get_input_pin_cfg - get input pin config 5115 * @hw: pointer to the HW struct 5116 * @input_idx: Input index 5117 * @status: Pin status 5118 * @type: Pin type 5119 * @flags1: Input flags 5120 * @flags2: Input flags 5121 * @freq: Frequency in Hz 5122 * @phase_delay: Delay in ps 5123 * 5124 * Get CGU input config (0x0C63) 5125 * Return: 0 on success or negative value on failure. 5126 */ 5127 int 5128 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5129 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5130 { 5131 struct ice_aqc_get_cgu_input_config *cmd; 5132 struct ice_aq_desc desc; 5133 int ret; 5134 5135 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5136 cmd = &desc.params.get_cgu_input_config; 5137 cmd->input_idx = input_idx; 5138 5139 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5140 if (!ret) { 5141 if (status) 5142 *status = cmd->status; 5143 if (type) 5144 *type = cmd->type; 5145 if (flags1) 5146 *flags1 = cmd->flags1; 5147 if (flags2) 5148 *flags2 = cmd->flags2; 5149 if (freq) 5150 *freq = le32_to_cpu(cmd->freq); 5151 if (phase_delay) 5152 *phase_delay = le32_to_cpu(cmd->phase_delay); 5153 } 5154 5155 return ret; 5156 } 5157 5158 /** 5159 * ice_aq_set_output_pin_cfg - set output pin config 5160 * @hw: pointer to the HW struct 5161 * @output_idx: Output index 5162 * @flags: Output flags 5163 * @src_sel: Index of DPLL block 5164 * @freq: Output frequency 5165 * @phase_delay: Output phase compensation 5166 * 5167 * Set CGU output config (0x0C64) 5168 * Return: 0 on success or negative value on failure. 5169 */ 5170 int 5171 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5172 u8 src_sel, u32 freq, s32 phase_delay) 5173 { 5174 struct ice_aqc_set_cgu_output_config *cmd; 5175 struct ice_aq_desc desc; 5176 5177 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5178 cmd = &desc.params.set_cgu_output_config; 5179 cmd->output_idx = output_idx; 5180 cmd->flags = flags; 5181 cmd->src_sel = src_sel; 5182 cmd->freq = cpu_to_le32(freq); 5183 cmd->phase_delay = cpu_to_le32(phase_delay); 5184 5185 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5186 } 5187 5188 /** 5189 * ice_aq_get_output_pin_cfg - get output pin config 5190 * @hw: pointer to the HW struct 5191 * @output_idx: Output index 5192 * @flags: Output flags 5193 * @src_sel: Internal DPLL source 5194 * @freq: Output frequency 5195 * @src_freq: Source frequency 5196 * 5197 * Get CGU output config (0x0C65) 5198 * Return: 0 on success or negative value on failure. 5199 */ 5200 int 5201 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5202 u8 *src_sel, u32 *freq, u32 *src_freq) 5203 { 5204 struct ice_aqc_get_cgu_output_config *cmd; 5205 struct ice_aq_desc desc; 5206 int ret; 5207 5208 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5209 cmd = &desc.params.get_cgu_output_config; 5210 cmd->output_idx = output_idx; 5211 5212 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5213 if (!ret) { 5214 if (flags) 5215 *flags = cmd->flags; 5216 if (src_sel) 5217 *src_sel = cmd->src_sel; 5218 if (freq) 5219 *freq = le32_to_cpu(cmd->freq); 5220 if (src_freq) 5221 *src_freq = le32_to_cpu(cmd->src_freq); 5222 } 5223 5224 return ret; 5225 } 5226 5227 /** 5228 * ice_aq_get_cgu_dpll_status - get dpll status 5229 * @hw: pointer to the HW struct 5230 * @dpll_num: DPLL index 5231 * @ref_state: Reference clock state 5232 * @config: current DPLL config 5233 * @dpll_state: current DPLL state 5234 * @phase_offset: Phase offset in ns 5235 * @eec_mode: EEC_mode 5236 * 5237 * Get CGU DPLL status (0x0C66) 5238 * Return: 0 on success or negative value on failure. 5239 */ 5240 int 5241 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5242 u8 *dpll_state, u8 *config, s64 *phase_offset, 5243 u8 *eec_mode) 5244 { 5245 struct ice_aqc_get_cgu_dpll_status *cmd; 5246 const s64 nsec_per_psec = 1000LL; 5247 struct ice_aq_desc desc; 5248 int status; 5249 5250 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5251 cmd = &desc.params.get_cgu_dpll_status; 5252 cmd->dpll_num = dpll_num; 5253 5254 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5255 if (!status) { 5256 *ref_state = cmd->ref_state; 5257 *dpll_state = cmd->dpll_state; 5258 *config = cmd->config; 5259 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5260 *phase_offset <<= 32; 5261 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5262 *phase_offset = div64_s64(sign_extend64(*phase_offset, 47), 5263 nsec_per_psec); 5264 *eec_mode = cmd->eec_mode; 5265 } 5266 5267 return status; 5268 } 5269 5270 /** 5271 * ice_aq_set_cgu_dpll_config - set dpll config 5272 * @hw: pointer to the HW struct 5273 * @dpll_num: DPLL index 5274 * @ref_state: Reference clock state 5275 * @config: DPLL config 5276 * @eec_mode: EEC mode 5277 * 5278 * Set CGU DPLL config (0x0C67) 5279 * Return: 0 on success or negative value on failure. 5280 */ 5281 int 5282 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5283 u8 config, u8 eec_mode) 5284 { 5285 struct ice_aqc_set_cgu_dpll_config *cmd; 5286 struct ice_aq_desc desc; 5287 5288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5289 cmd = &desc.params.set_cgu_dpll_config; 5290 cmd->dpll_num = dpll_num; 5291 cmd->ref_state = ref_state; 5292 cmd->config = config; 5293 cmd->eec_mode = eec_mode; 5294 5295 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5296 } 5297 5298 /** 5299 * ice_aq_set_cgu_ref_prio - set input reference priority 5300 * @hw: pointer to the HW struct 5301 * @dpll_num: DPLL index 5302 * @ref_idx: Reference pin index 5303 * @ref_priority: Reference input priority 5304 * 5305 * Set CGU reference priority (0x0C68) 5306 * Return: 0 on success or negative value on failure. 5307 */ 5308 int 5309 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5310 u8 ref_priority) 5311 { 5312 struct ice_aqc_set_cgu_ref_prio *cmd; 5313 struct ice_aq_desc desc; 5314 5315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5316 cmd = &desc.params.set_cgu_ref_prio; 5317 cmd->dpll_num = dpll_num; 5318 cmd->ref_idx = ref_idx; 5319 cmd->ref_priority = ref_priority; 5320 5321 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5322 } 5323 5324 /** 5325 * ice_aq_get_cgu_ref_prio - get input reference priority 5326 * @hw: pointer to the HW struct 5327 * @dpll_num: DPLL index 5328 * @ref_idx: Reference pin index 5329 * @ref_prio: Reference input priority 5330 * 5331 * Get CGU reference priority (0x0C69) 5332 * Return: 0 on success or negative value on failure. 5333 */ 5334 int 5335 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5336 u8 *ref_prio) 5337 { 5338 struct ice_aqc_get_cgu_ref_prio *cmd; 5339 struct ice_aq_desc desc; 5340 int status; 5341 5342 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5343 cmd = &desc.params.get_cgu_ref_prio; 5344 cmd->dpll_num = dpll_num; 5345 cmd->ref_idx = ref_idx; 5346 5347 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5348 if (!status) 5349 *ref_prio = cmd->ref_priority; 5350 5351 return status; 5352 } 5353 5354 /** 5355 * ice_aq_get_cgu_info - get cgu info 5356 * @hw: pointer to the HW struct 5357 * @cgu_id: CGU ID 5358 * @cgu_cfg_ver: CGU config version 5359 * @cgu_fw_ver: CGU firmware version 5360 * 5361 * Get CGU info (0x0C6A) 5362 * Return: 0 on success or negative value on failure. 5363 */ 5364 int 5365 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5366 u32 *cgu_fw_ver) 5367 { 5368 struct ice_aqc_get_cgu_info *cmd; 5369 struct ice_aq_desc desc; 5370 int status; 5371 5372 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5373 cmd = &desc.params.get_cgu_info; 5374 5375 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5376 if (!status) { 5377 *cgu_id = le32_to_cpu(cmd->cgu_id); 5378 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5379 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5380 } 5381 5382 return status; 5383 } 5384 5385 /** 5386 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5387 * @hw: pointer to the HW struct 5388 * @phy_output: PHY reference clock output pin 5389 * @enable: GPIO state to be applied 5390 * @freq: PHY output frequency 5391 * 5392 * Set phy recovered clock as reference (0x0630) 5393 * Return: 0 on success or negative value on failure. 5394 */ 5395 int 5396 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5397 u32 *freq) 5398 { 5399 struct ice_aqc_set_phy_rec_clk_out *cmd; 5400 struct ice_aq_desc desc; 5401 int status; 5402 5403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5404 cmd = &desc.params.set_phy_rec_clk_out; 5405 cmd->phy_output = phy_output; 5406 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5407 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5408 cmd->freq = cpu_to_le32(*freq); 5409 5410 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5411 if (!status) 5412 *freq = le32_to_cpu(cmd->freq); 5413 5414 return status; 5415 } 5416 5417 /** 5418 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5419 * @hw: pointer to the HW struct 5420 * @phy_output: PHY reference clock output pin 5421 * @port_num: Port number 5422 * @flags: PHY flags 5423 * @node_handle: PHY output frequency 5424 * 5425 * Get PHY recovered clock output info (0x0631) 5426 * Return: 0 on success or negative value on failure. 5427 */ 5428 int 5429 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5430 u8 *flags, u16 *node_handle) 5431 { 5432 struct ice_aqc_get_phy_rec_clk_out *cmd; 5433 struct ice_aq_desc desc; 5434 int status; 5435 5436 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5437 cmd = &desc.params.get_phy_rec_clk_out; 5438 cmd->phy_output = *phy_output; 5439 5440 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5441 if (!status) { 5442 *phy_output = cmd->phy_output; 5443 if (port_num) 5444 *port_num = cmd->port_num; 5445 if (flags) 5446 *flags = cmd->flags; 5447 if (node_handle) 5448 *node_handle = le16_to_cpu(cmd->node_handle); 5449 } 5450 5451 return status; 5452 } 5453 5454 /** 5455 * ice_replay_pre_init - replay pre initialization 5456 * @hw: pointer to the HW struct 5457 * 5458 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5459 */ 5460 static int ice_replay_pre_init(struct ice_hw *hw) 5461 { 5462 struct ice_switch_info *sw = hw->switch_info; 5463 u8 i; 5464 5465 /* Delete old entries from replay filter list head if there is any */ 5466 ice_rm_all_sw_replay_rule_info(hw); 5467 /* In start of replay, move entries into replay_rules list, it 5468 * will allow adding rules entries back to filt_rules list, 5469 * which is operational list. 5470 */ 5471 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5472 list_replace_init(&sw->recp_list[i].filt_rules, 5473 &sw->recp_list[i].filt_replay_rules); 5474 ice_sched_replay_agg_vsi_preinit(hw); 5475 5476 return 0; 5477 } 5478 5479 /** 5480 * ice_replay_vsi - replay VSI configuration 5481 * @hw: pointer to the HW struct 5482 * @vsi_handle: driver VSI handle 5483 * 5484 * Restore all VSI configuration after reset. It is required to call this 5485 * function with main VSI first. 5486 */ 5487 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5488 { 5489 int status; 5490 5491 if (!ice_is_vsi_valid(hw, vsi_handle)) 5492 return -EINVAL; 5493 5494 /* Replay pre-initialization if there is any */ 5495 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5496 status = ice_replay_pre_init(hw); 5497 if (status) 5498 return status; 5499 } 5500 /* Replay per VSI all RSS configurations */ 5501 status = ice_replay_rss_cfg(hw, vsi_handle); 5502 if (status) 5503 return status; 5504 /* Replay per VSI all filters */ 5505 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5506 if (!status) 5507 status = ice_replay_vsi_agg(hw, vsi_handle); 5508 return status; 5509 } 5510 5511 /** 5512 * ice_replay_post - post replay configuration cleanup 5513 * @hw: pointer to the HW struct 5514 * 5515 * Post replay cleanup. 5516 */ 5517 void ice_replay_post(struct ice_hw *hw) 5518 { 5519 /* Delete old entries from replay filter list head */ 5520 ice_rm_all_sw_replay_rule_info(hw); 5521 ice_sched_replay_agg(hw); 5522 } 5523 5524 /** 5525 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5526 * @hw: ptr to the hardware info 5527 * @reg: offset of 64 bit HW register to read from 5528 * @prev_stat_loaded: bool to specify if previous stats are loaded 5529 * @prev_stat: ptr to previous loaded stat value 5530 * @cur_stat: ptr to current stat value 5531 */ 5532 void 5533 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5534 u64 *prev_stat, u64 *cur_stat) 5535 { 5536 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5537 5538 /* device stats are not reset at PFR, they likely will not be zeroed 5539 * when the driver starts. Thus, save the value from the first read 5540 * without adding to the statistic value so that we report stats which 5541 * count up from zero. 5542 */ 5543 if (!prev_stat_loaded) { 5544 *prev_stat = new_data; 5545 return; 5546 } 5547 5548 /* Calculate the difference between the new and old values, and then 5549 * add it to the software stat value. 5550 */ 5551 if (new_data >= *prev_stat) 5552 *cur_stat += new_data - *prev_stat; 5553 else 5554 /* to manage the potential roll-over */ 5555 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5556 5557 /* Update the previously stored value to prepare for next read */ 5558 *prev_stat = new_data; 5559 } 5560 5561 /** 5562 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5563 * @hw: ptr to the hardware info 5564 * @reg: offset of HW register to read from 5565 * @prev_stat_loaded: bool to specify if previous stats are loaded 5566 * @prev_stat: ptr to previous loaded stat value 5567 * @cur_stat: ptr to current stat value 5568 */ 5569 void 5570 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5571 u64 *prev_stat, u64 *cur_stat) 5572 { 5573 u32 new_data; 5574 5575 new_data = rd32(hw, reg); 5576 5577 /* device stats are not reset at PFR, they likely will not be zeroed 5578 * when the driver starts. Thus, save the value from the first read 5579 * without adding to the statistic value so that we report stats which 5580 * count up from zero. 5581 */ 5582 if (!prev_stat_loaded) { 5583 *prev_stat = new_data; 5584 return; 5585 } 5586 5587 /* Calculate the difference between the new and old values, and then 5588 * add it to the software stat value. 5589 */ 5590 if (new_data >= *prev_stat) 5591 *cur_stat += new_data - *prev_stat; 5592 else 5593 /* to manage the potential roll-over */ 5594 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5595 5596 /* Update the previously stored value to prepare for next read */ 5597 *prev_stat = new_data; 5598 } 5599 5600 /** 5601 * ice_sched_query_elem - query element information from HW 5602 * @hw: pointer to the HW struct 5603 * @node_teid: node TEID to be queried 5604 * @buf: buffer to element information 5605 * 5606 * This function queries HW element information 5607 */ 5608 int 5609 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5610 struct ice_aqc_txsched_elem_data *buf) 5611 { 5612 u16 buf_size, num_elem_ret = 0; 5613 int status; 5614 5615 buf_size = sizeof(*buf); 5616 memset(buf, 0, buf_size); 5617 buf->node_teid = cpu_to_le32(node_teid); 5618 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5619 NULL); 5620 if (status || num_elem_ret != 1) 5621 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5622 return status; 5623 } 5624 5625 /** 5626 * ice_aq_read_i2c 5627 * @hw: pointer to the hw struct 5628 * @topo_addr: topology address for a device to communicate with 5629 * @bus_addr: 7-bit I2C bus address 5630 * @addr: I2C memory address (I2C offset) with up to 16 bits 5631 * @params: I2C parameters: bit [7] - Repeated start, 5632 * bits [6:5] data offset size, 5633 * bit [4] - I2C address type, 5634 * bits [3:0] - data size to read (0-16 bytes) 5635 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5636 * @cd: pointer to command details structure or NULL 5637 * 5638 * Read I2C (0x06E2) 5639 */ 5640 int 5641 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5642 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5643 struct ice_sq_cd *cd) 5644 { 5645 struct ice_aq_desc desc = { 0 }; 5646 struct ice_aqc_i2c *cmd; 5647 u8 data_size; 5648 int status; 5649 5650 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5651 cmd = &desc.params.read_write_i2c; 5652 5653 if (!data) 5654 return -EINVAL; 5655 5656 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5657 5658 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5659 cmd->topo_addr = topo_addr; 5660 cmd->i2c_params = params; 5661 cmd->i2c_addr = addr; 5662 5663 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5664 if (!status) { 5665 struct ice_aqc_read_i2c_resp *resp; 5666 u8 i; 5667 5668 resp = &desc.params.read_i2c_resp; 5669 for (i = 0; i < data_size; i++) { 5670 *data = resp->i2c_data[i]; 5671 data++; 5672 } 5673 } 5674 5675 return status; 5676 } 5677 5678 /** 5679 * ice_aq_write_i2c 5680 * @hw: pointer to the hw struct 5681 * @topo_addr: topology address for a device to communicate with 5682 * @bus_addr: 7-bit I2C bus address 5683 * @addr: I2C memory address (I2C offset) with up to 16 bits 5684 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5685 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5686 * @cd: pointer to command details structure or NULL 5687 * 5688 * Write I2C (0x06E3) 5689 * 5690 * * Return: 5691 * * 0 - Successful write to the i2c device 5692 * * -EINVAL - Data size greater than 4 bytes 5693 * * -EIO - FW error 5694 */ 5695 int 5696 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5697 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5698 struct ice_sq_cd *cd) 5699 { 5700 struct ice_aq_desc desc = { 0 }; 5701 struct ice_aqc_i2c *cmd; 5702 u8 data_size; 5703 5704 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5705 cmd = &desc.params.read_write_i2c; 5706 5707 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5708 5709 /* data_size limited to 4 */ 5710 if (data_size > 4) 5711 return -EINVAL; 5712 5713 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5714 cmd->topo_addr = topo_addr; 5715 cmd->i2c_params = params; 5716 cmd->i2c_addr = addr; 5717 5718 memcpy(cmd->i2c_data, data, data_size); 5719 5720 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5721 } 5722 5723 /** 5724 * ice_aq_set_gpio 5725 * @hw: pointer to the hw struct 5726 * @gpio_ctrl_handle: GPIO controller node handle 5727 * @pin_idx: IO Number of the GPIO that needs to be set 5728 * @value: SW provide IO value to set in the LSB 5729 * @cd: pointer to command details structure or NULL 5730 * 5731 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5732 */ 5733 int 5734 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5735 struct ice_sq_cd *cd) 5736 { 5737 struct ice_aqc_gpio *cmd; 5738 struct ice_aq_desc desc; 5739 5740 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5741 cmd = &desc.params.read_write_gpio; 5742 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5743 cmd->gpio_num = pin_idx; 5744 cmd->gpio_val = value ? 1 : 0; 5745 5746 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5747 } 5748 5749 /** 5750 * ice_aq_get_gpio 5751 * @hw: pointer to the hw struct 5752 * @gpio_ctrl_handle: GPIO controller node handle 5753 * @pin_idx: IO Number of the GPIO that needs to be set 5754 * @value: IO value read 5755 * @cd: pointer to command details structure or NULL 5756 * 5757 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5758 * the topology 5759 */ 5760 int 5761 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5762 bool *value, struct ice_sq_cd *cd) 5763 { 5764 struct ice_aqc_gpio *cmd; 5765 struct ice_aq_desc desc; 5766 int status; 5767 5768 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5769 cmd = &desc.params.read_write_gpio; 5770 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5771 cmd->gpio_num = pin_idx; 5772 5773 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5774 if (status) 5775 return status; 5776 5777 *value = !!cmd->gpio_val; 5778 return 0; 5779 } 5780 5781 /** 5782 * ice_is_fw_api_min_ver 5783 * @hw: pointer to the hardware structure 5784 * @maj: major version 5785 * @min: minor version 5786 * @patch: patch version 5787 * 5788 * Checks if the firmware API is minimum version 5789 */ 5790 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5791 { 5792 if (hw->api_maj_ver == maj) { 5793 if (hw->api_min_ver > min) 5794 return true; 5795 if (hw->api_min_ver == min && hw->api_patch >= patch) 5796 return true; 5797 } else if (hw->api_maj_ver > maj) { 5798 return true; 5799 } 5800 5801 return false; 5802 } 5803 5804 /** 5805 * ice_fw_supports_link_override 5806 * @hw: pointer to the hardware structure 5807 * 5808 * Checks if the firmware supports link override 5809 */ 5810 bool ice_fw_supports_link_override(struct ice_hw *hw) 5811 { 5812 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5813 ICE_FW_API_LINK_OVERRIDE_MIN, 5814 ICE_FW_API_LINK_OVERRIDE_PATCH); 5815 } 5816 5817 /** 5818 * ice_get_link_default_override 5819 * @ldo: pointer to the link default override struct 5820 * @pi: pointer to the port info struct 5821 * 5822 * Gets the link default override for a port 5823 */ 5824 int 5825 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5826 struct ice_port_info *pi) 5827 { 5828 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5829 struct ice_hw *hw = pi->hw; 5830 int status; 5831 5832 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5833 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5834 if (status) { 5835 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5836 return status; 5837 } 5838 5839 /* Each port has its own config; calculate for our port */ 5840 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5841 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5842 5843 /* link options first */ 5844 status = ice_read_sr_word(hw, tlv_start, &buf); 5845 if (status) { 5846 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5847 return status; 5848 } 5849 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5850 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5851 ICE_LINK_OVERRIDE_PHY_CFG_S; 5852 5853 /* link PHY config */ 5854 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5855 status = ice_read_sr_word(hw, offset, &buf); 5856 if (status) { 5857 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5858 return status; 5859 } 5860 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5861 5862 /* PHY types low */ 5863 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5864 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5865 status = ice_read_sr_word(hw, (offset + i), &buf); 5866 if (status) { 5867 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5868 return status; 5869 } 5870 /* shift 16 bits at a time to fill 64 bits */ 5871 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5872 } 5873 5874 /* PHY types high */ 5875 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5876 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5877 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5878 status = ice_read_sr_word(hw, (offset + i), &buf); 5879 if (status) { 5880 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5881 return status; 5882 } 5883 /* shift 16 bits at a time to fill 64 bits */ 5884 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5885 } 5886 5887 return status; 5888 } 5889 5890 /** 5891 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5892 * @caps: get PHY capability data 5893 */ 5894 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5895 { 5896 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5897 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5898 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5899 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5900 return true; 5901 5902 return false; 5903 } 5904 5905 /** 5906 * ice_aq_set_lldp_mib - Set the LLDP MIB 5907 * @hw: pointer to the HW struct 5908 * @mib_type: Local, Remote or both Local and Remote MIBs 5909 * @buf: pointer to the caller-supplied buffer to store the MIB block 5910 * @buf_size: size of the buffer (in bytes) 5911 * @cd: pointer to command details structure or NULL 5912 * 5913 * Set the LLDP MIB. (0x0A08) 5914 */ 5915 int 5916 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5917 struct ice_sq_cd *cd) 5918 { 5919 struct ice_aqc_lldp_set_local_mib *cmd; 5920 struct ice_aq_desc desc; 5921 5922 cmd = &desc.params.lldp_set_mib; 5923 5924 if (buf_size == 0 || !buf) 5925 return -EINVAL; 5926 5927 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5928 5929 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5930 desc.datalen = cpu_to_le16(buf_size); 5931 5932 cmd->type = mib_type; 5933 cmd->length = cpu_to_le16(buf_size); 5934 5935 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5936 } 5937 5938 /** 5939 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5940 * @hw: pointer to HW struct 5941 */ 5942 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5943 { 5944 if (hw->mac_type != ICE_MAC_E810) 5945 return false; 5946 5947 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5948 ICE_FW_API_LLDP_FLTR_MIN, 5949 ICE_FW_API_LLDP_FLTR_PATCH); 5950 } 5951 5952 /** 5953 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5954 * @hw: pointer to HW struct 5955 * @vsi_num: absolute HW index for VSI 5956 * @add: boolean for if adding or removing a filter 5957 */ 5958 int 5959 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5960 { 5961 struct ice_aqc_lldp_filter_ctrl *cmd; 5962 struct ice_aq_desc desc; 5963 5964 cmd = &desc.params.lldp_filter_ctrl; 5965 5966 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5967 5968 if (add) 5969 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5970 else 5971 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5972 5973 cmd->vsi_num = cpu_to_le16(vsi_num); 5974 5975 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5976 } 5977 5978 /** 5979 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 5980 * @hw: pointer to HW struct 5981 */ 5982 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 5983 { 5984 struct ice_aq_desc desc; 5985 5986 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 5987 5988 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5989 } 5990 5991 /** 5992 * ice_fw_supports_report_dflt_cfg 5993 * @hw: pointer to the hardware structure 5994 * 5995 * Checks if the firmware supports report default configuration 5996 */ 5997 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5998 { 5999 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6000 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6001 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6002 } 6003 6004 /* each of the indexes into the following array match the speed of a return 6005 * value from the list of AQ returned speeds like the range: 6006 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6007 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6008 * array. The array is defined as 15 elements long because the link_speed 6009 * returned by the firmware is a 16 bit * value, but is indexed 6010 * by [fls(speed) - 1] 6011 */ 6012 static const u32 ice_aq_to_link_speed[] = { 6013 SPEED_10, /* BIT(0) */ 6014 SPEED_100, 6015 SPEED_1000, 6016 SPEED_2500, 6017 SPEED_5000, 6018 SPEED_10000, 6019 SPEED_20000, 6020 SPEED_25000, 6021 SPEED_40000, 6022 SPEED_50000, 6023 SPEED_100000, /* BIT(10) */ 6024 }; 6025 6026 /** 6027 * ice_get_link_speed - get integer speed from table 6028 * @index: array index from fls(aq speed) - 1 6029 * 6030 * Returns: u32 value containing integer speed 6031 */ 6032 u32 ice_get_link_speed(u16 index) 6033 { 6034 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6035 return 0; 6036 6037 return ice_aq_to_link_speed[index]; 6038 } 6039