1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 8 #define ICE_PF_RESET_WAIT_COUNT 200 9 10 #define ICE_NIC_FLX_ENTRY(hw, mdid, idx) \ 11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(ICE_RXDID_FLEX_NIC), \ 12 ((ICE_RX_OPC_MDID << \ 13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 17 18 #define ICE_NIC_FLX_FLG_ENTRY(hw, flg_0, flg_1, flg_2, flg_3, idx) \ 19 wr32((hw), GLFLXP_RXDID_FLAGS(ICE_RXDID_FLEX_NIC, idx), \ 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 28 29 /** 30 * ice_set_mac_type - Sets MAC type 31 * @hw: pointer to the HW structure 32 * 33 * This function sets the MAC type of the adapter based on the 34 * vendor ID and device ID stored in the hw structure. 35 */ 36 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 37 { 38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 39 return ICE_ERR_DEVICE_NOT_SUPPORTED; 40 41 hw->mac_type = ICE_MAC_GENERIC; 42 return 0; 43 } 44 45 /** 46 * ice_clear_pf_cfg - Clear PF configuration 47 * @hw: pointer to the hardware structure 48 * 49 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 50 * configuration, flow director filters, etc.). 51 */ 52 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 53 { 54 struct ice_aq_desc desc; 55 56 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 57 58 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 59 } 60 61 /** 62 * ice_aq_manage_mac_read - manage MAC address read command 63 * @hw: pointer to the hw struct 64 * @buf: a virtual buffer to hold the manage MAC read response 65 * @buf_size: Size of the virtual buffer 66 * @cd: pointer to command details structure or NULL 67 * 68 * This function is used to return per PF station MAC address (0x0107). 69 * NOTE: Upon successful completion of this command, MAC address information 70 * is returned in user specified buffer. Please interpret user specified 71 * buffer as "manage_mac_read" response. 72 * Response such as various MAC addresses are stored in HW struct (port.mac) 73 * ice_aq_discover_caps is expected to be called before this function is called. 74 */ 75 static enum ice_status 76 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 77 struct ice_sq_cd *cd) 78 { 79 struct ice_aqc_manage_mac_read_resp *resp; 80 struct ice_aqc_manage_mac_read *cmd; 81 struct ice_aq_desc desc; 82 enum ice_status status; 83 u16 flags; 84 u8 i; 85 86 cmd = &desc.params.mac_read; 87 88 if (buf_size < sizeof(*resp)) 89 return ICE_ERR_BUF_TOO_SHORT; 90 91 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 92 93 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 94 if (status) 95 return status; 96 97 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 98 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 99 100 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 101 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 102 return ICE_ERR_CFG; 103 } 104 105 /* A single port can report up to two (LAN and WoL) addresses */ 106 for (i = 0; i < cmd->num_addr; i++) 107 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 108 ether_addr_copy(hw->port_info->mac.lan_addr, 109 resp[i].mac_addr); 110 ether_addr_copy(hw->port_info->mac.perm_addr, 111 resp[i].mac_addr); 112 break; 113 } 114 115 return 0; 116 } 117 118 /** 119 * ice_aq_get_phy_caps - returns PHY capabilities 120 * @pi: port information structure 121 * @qual_mods: report qualified modules 122 * @report_mode: report mode capabilities 123 * @pcaps: structure for PHY capabilities to be filled 124 * @cd: pointer to command details structure or NULL 125 * 126 * Returns the various PHY capabilities supported on the Port (0x0600) 127 */ 128 static enum ice_status 129 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 130 struct ice_aqc_get_phy_caps_data *pcaps, 131 struct ice_sq_cd *cd) 132 { 133 struct ice_aqc_get_phy_caps *cmd; 134 u16 pcaps_size = sizeof(*pcaps); 135 struct ice_aq_desc desc; 136 enum ice_status status; 137 138 cmd = &desc.params.get_phy; 139 140 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 141 return ICE_ERR_PARAM; 142 143 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 144 145 if (qual_mods) 146 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 147 148 cmd->param0 |= cpu_to_le16(report_mode); 149 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 150 151 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) 152 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 153 154 return status; 155 } 156 157 /** 158 * ice_get_media_type - Gets media type 159 * @pi: port information structure 160 */ 161 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 162 { 163 struct ice_link_status *hw_link_info; 164 165 if (!pi) 166 return ICE_MEDIA_UNKNOWN; 167 168 hw_link_info = &pi->phy.link_info; 169 170 if (hw_link_info->phy_type_low) { 171 switch (hw_link_info->phy_type_low) { 172 case ICE_PHY_TYPE_LOW_1000BASE_SX: 173 case ICE_PHY_TYPE_LOW_1000BASE_LX: 174 case ICE_PHY_TYPE_LOW_10GBASE_SR: 175 case ICE_PHY_TYPE_LOW_10GBASE_LR: 176 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 177 case ICE_PHY_TYPE_LOW_25GBASE_SR: 178 case ICE_PHY_TYPE_LOW_25GBASE_LR: 179 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 180 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 181 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 182 return ICE_MEDIA_FIBER; 183 case ICE_PHY_TYPE_LOW_100BASE_TX: 184 case ICE_PHY_TYPE_LOW_1000BASE_T: 185 case ICE_PHY_TYPE_LOW_2500BASE_T: 186 case ICE_PHY_TYPE_LOW_5GBASE_T: 187 case ICE_PHY_TYPE_LOW_10GBASE_T: 188 case ICE_PHY_TYPE_LOW_25GBASE_T: 189 return ICE_MEDIA_BASET; 190 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 191 case ICE_PHY_TYPE_LOW_25GBASE_CR: 192 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 193 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 194 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 195 return ICE_MEDIA_DA; 196 case ICE_PHY_TYPE_LOW_1000BASE_KX: 197 case ICE_PHY_TYPE_LOW_2500BASE_KX: 198 case ICE_PHY_TYPE_LOW_2500BASE_X: 199 case ICE_PHY_TYPE_LOW_5GBASE_KR: 200 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 201 case ICE_PHY_TYPE_LOW_25GBASE_KR: 202 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 203 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 204 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 205 return ICE_MEDIA_BACKPLANE; 206 } 207 } 208 209 return ICE_MEDIA_UNKNOWN; 210 } 211 212 /** 213 * ice_aq_get_link_info 214 * @pi: port information structure 215 * @ena_lse: enable/disable LinkStatusEvent reporting 216 * @link: pointer to link status structure - optional 217 * @cd: pointer to command details structure or NULL 218 * 219 * Get Link Status (0x607). Returns the link status of the adapter. 220 */ 221 enum ice_status 222 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 223 struct ice_link_status *link, struct ice_sq_cd *cd) 224 { 225 struct ice_link_status *hw_link_info_old, *hw_link_info; 226 struct ice_aqc_get_link_status_data link_data = { 0 }; 227 struct ice_aqc_get_link_status *resp; 228 enum ice_media_type *hw_media_type; 229 struct ice_fc_info *hw_fc_info; 230 bool tx_pause, rx_pause; 231 struct ice_aq_desc desc; 232 enum ice_status status; 233 u16 cmd_flags; 234 235 if (!pi) 236 return ICE_ERR_PARAM; 237 hw_link_info_old = &pi->phy.link_info_old; 238 hw_media_type = &pi->phy.media_type; 239 hw_link_info = &pi->phy.link_info; 240 hw_fc_info = &pi->fc; 241 242 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 243 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 244 resp = &desc.params.get_link_status; 245 resp->cmd_flags = cpu_to_le16(cmd_flags); 246 resp->lport_num = pi->lport; 247 248 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), 249 cd); 250 251 if (status) 252 return status; 253 254 /* save off old link status information */ 255 *hw_link_info_old = *hw_link_info; 256 257 /* update current link status information */ 258 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); 259 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); 260 *hw_media_type = ice_get_media_type(pi); 261 hw_link_info->link_info = link_data.link_info; 262 hw_link_info->an_info = link_data.an_info; 263 hw_link_info->ext_info = link_data.ext_info; 264 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); 265 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; 266 267 /* update fc info */ 268 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 269 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 270 if (tx_pause && rx_pause) 271 hw_fc_info->current_mode = ICE_FC_FULL; 272 else if (tx_pause) 273 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 274 else if (rx_pause) 275 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 276 else 277 hw_fc_info->current_mode = ICE_FC_NONE; 278 279 hw_link_info->lse_ena = 280 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 281 282 /* save link status information */ 283 if (link) 284 *link = *hw_link_info; 285 286 /* flag cleared so calling functions don't call AQ again */ 287 pi->phy.get_link_info = false; 288 289 return status; 290 } 291 292 /** 293 * ice_init_flex_parser - initialize rx flex parser 294 * @hw: pointer to the hardware structure 295 * 296 * Function to initialize flex descriptors 297 */ 298 static void ice_init_flex_parser(struct ice_hw *hw) 299 { 300 u8 idx = 0; 301 302 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_LOW, 0); 303 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_HIGH, 1); 304 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_LOWER, 2); 305 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_HIGH, 3); 306 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_FRG, ICE_RXFLG_UDP_GRE, 307 ICE_RXFLG_PKT_DSI, ICE_RXFLG_FIN, idx++); 308 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_SYN, ICE_RXFLG_RST, 309 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++); 310 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, 311 ICE_RXFLG_EVLAN_x8100, ICE_RXFLG_EVLAN_x9100, 312 idx++); 313 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_VLAN_x8100, ICE_RXFLG_TNL_VLAN, 314 ICE_RXFLG_TNL_MAC, ICE_RXFLG_TNL0, idx++); 315 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2, 316 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx); 317 } 318 319 /** 320 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 321 * @hw: pointer to the hw struct 322 */ 323 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 324 { 325 struct ice_switch_info *sw; 326 327 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 328 sizeof(*hw->switch_info), GFP_KERNEL); 329 sw = hw->switch_info; 330 331 if (!sw) 332 return ICE_ERR_NO_MEMORY; 333 334 INIT_LIST_HEAD(&sw->vsi_list_map_head); 335 336 mutex_init(&sw->mac_list_lock); 337 INIT_LIST_HEAD(&sw->mac_list_head); 338 339 mutex_init(&sw->vlan_list_lock); 340 INIT_LIST_HEAD(&sw->vlan_list_head); 341 342 mutex_init(&sw->eth_m_list_lock); 343 INIT_LIST_HEAD(&sw->eth_m_list_head); 344 345 mutex_init(&sw->promisc_list_lock); 346 INIT_LIST_HEAD(&sw->promisc_list_head); 347 348 mutex_init(&sw->mac_vlan_list_lock); 349 INIT_LIST_HEAD(&sw->mac_vlan_list_head); 350 351 return 0; 352 } 353 354 /** 355 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 356 * @hw: pointer to the hw struct 357 */ 358 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 359 { 360 struct ice_switch_info *sw = hw->switch_info; 361 struct ice_vsi_list_map_info *v_pos_map; 362 struct ice_vsi_list_map_info *v_tmp_map; 363 364 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 365 list_entry) { 366 list_del(&v_pos_map->list_entry); 367 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 368 } 369 370 mutex_destroy(&sw->mac_list_lock); 371 mutex_destroy(&sw->vlan_list_lock); 372 mutex_destroy(&sw->eth_m_list_lock); 373 mutex_destroy(&sw->promisc_list_lock); 374 mutex_destroy(&sw->mac_vlan_list_lock); 375 376 devm_kfree(ice_hw_to_dev(hw), sw); 377 } 378 379 /** 380 * ice_init_hw - main hardware initialization routine 381 * @hw: pointer to the hardware structure 382 */ 383 enum ice_status ice_init_hw(struct ice_hw *hw) 384 { 385 struct ice_aqc_get_phy_caps_data *pcaps; 386 enum ice_status status; 387 u16 mac_buf_len; 388 void *mac_buf; 389 390 /* Set MAC type based on DeviceID */ 391 status = ice_set_mac_type(hw); 392 if (status) 393 return status; 394 395 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 396 PF_FUNC_RID_FUNC_NUM_M) >> 397 PF_FUNC_RID_FUNC_NUM_S; 398 399 status = ice_reset(hw, ICE_RESET_PFR); 400 if (status) 401 return status; 402 403 /* set these values to minimum allowed */ 404 hw->itr_gran_200 = ICE_ITR_GRAN_MIN_200; 405 hw->itr_gran_100 = ICE_ITR_GRAN_MIN_100; 406 hw->itr_gran_50 = ICE_ITR_GRAN_MIN_50; 407 hw->itr_gran_25 = ICE_ITR_GRAN_MIN_25; 408 409 status = ice_init_all_ctrlq(hw); 410 if (status) 411 goto err_unroll_cqinit; 412 413 status = ice_clear_pf_cfg(hw); 414 if (status) 415 goto err_unroll_cqinit; 416 417 ice_clear_pxe_mode(hw); 418 419 status = ice_init_nvm(hw); 420 if (status) 421 goto err_unroll_cqinit; 422 423 status = ice_get_caps(hw); 424 if (status) 425 goto err_unroll_cqinit; 426 427 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 428 sizeof(*hw->port_info), GFP_KERNEL); 429 if (!hw->port_info) { 430 status = ICE_ERR_NO_MEMORY; 431 goto err_unroll_cqinit; 432 } 433 434 /* set the back pointer to hw */ 435 hw->port_info->hw = hw; 436 437 /* Initialize port_info struct with switch configuration data */ 438 status = ice_get_initial_sw_cfg(hw); 439 if (status) 440 goto err_unroll_alloc; 441 442 hw->evb_veb = true; 443 444 /* Query the allocated resources for tx scheduler */ 445 status = ice_sched_query_res_alloc(hw); 446 if (status) { 447 ice_debug(hw, ICE_DBG_SCHED, 448 "Failed to get scheduler allocated resources\n"); 449 goto err_unroll_alloc; 450 } 451 452 /* Initialize port_info struct with scheduler data */ 453 status = ice_sched_init_port(hw->port_info); 454 if (status) 455 goto err_unroll_sched; 456 457 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 458 if (!pcaps) { 459 status = ICE_ERR_NO_MEMORY; 460 goto err_unroll_sched; 461 } 462 463 /* Initialize port_info struct with PHY capabilities */ 464 status = ice_aq_get_phy_caps(hw->port_info, false, 465 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 466 devm_kfree(ice_hw_to_dev(hw), pcaps); 467 if (status) 468 goto err_unroll_sched; 469 470 /* Initialize port_info struct with link information */ 471 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 472 if (status) 473 goto err_unroll_sched; 474 475 status = ice_init_fltr_mgmt_struct(hw); 476 if (status) 477 goto err_unroll_sched; 478 479 /* Get MAC information */ 480 /* A single port can report up to two (LAN and WoL) addresses */ 481 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 482 sizeof(struct ice_aqc_manage_mac_read_resp), 483 GFP_KERNEL); 484 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 485 486 if (!mac_buf) { 487 status = ICE_ERR_NO_MEMORY; 488 goto err_unroll_fltr_mgmt_struct; 489 } 490 491 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 492 devm_kfree(ice_hw_to_dev(hw), mac_buf); 493 494 if (status) 495 goto err_unroll_fltr_mgmt_struct; 496 497 ice_init_flex_parser(hw); 498 499 return 0; 500 501 err_unroll_fltr_mgmt_struct: 502 ice_cleanup_fltr_mgmt_struct(hw); 503 err_unroll_sched: 504 ice_sched_cleanup_all(hw); 505 err_unroll_alloc: 506 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 507 err_unroll_cqinit: 508 ice_shutdown_all_ctrlq(hw); 509 return status; 510 } 511 512 /** 513 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 514 * @hw: pointer to the hardware structure 515 */ 516 void ice_deinit_hw(struct ice_hw *hw) 517 { 518 ice_sched_cleanup_all(hw); 519 ice_shutdown_all_ctrlq(hw); 520 521 if (hw->port_info) { 522 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 523 hw->port_info = NULL; 524 } 525 526 ice_cleanup_fltr_mgmt_struct(hw); 527 } 528 529 /** 530 * ice_check_reset - Check to see if a global reset is complete 531 * @hw: pointer to the hardware structure 532 */ 533 enum ice_status ice_check_reset(struct ice_hw *hw) 534 { 535 u32 cnt, reg = 0, grst_delay; 536 537 /* Poll for Device Active state in case a recent CORER, GLOBR, 538 * or EMPR has occurred. The grst delay value is in 100ms units. 539 * Add 1sec for outstanding AQ commands that can take a long time. 540 */ 541 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 542 GLGEN_RSTCTL_GRSTDEL_S) + 10; 543 544 for (cnt = 0; cnt < grst_delay; cnt++) { 545 mdelay(100); 546 reg = rd32(hw, GLGEN_RSTAT); 547 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 548 break; 549 } 550 551 if (cnt == grst_delay) { 552 ice_debug(hw, ICE_DBG_INIT, 553 "Global reset polling failed to complete.\n"); 554 return ICE_ERR_RESET_FAILED; 555 } 556 557 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 558 GLNVM_ULD_GLOBR_DONE_M) 559 560 /* Device is Active; check Global Reset processes are done */ 561 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 562 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 563 if (reg == ICE_RESET_DONE_MASK) { 564 ice_debug(hw, ICE_DBG_INIT, 565 "Global reset processes done. %d\n", cnt); 566 break; 567 } 568 mdelay(10); 569 } 570 571 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 572 ice_debug(hw, ICE_DBG_INIT, 573 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 574 reg); 575 return ICE_ERR_RESET_FAILED; 576 } 577 578 return 0; 579 } 580 581 /** 582 * ice_pf_reset - Reset the PF 583 * @hw: pointer to the hardware structure 584 * 585 * If a global reset has been triggered, this function checks 586 * for its completion and then issues the PF reset 587 */ 588 static enum ice_status ice_pf_reset(struct ice_hw *hw) 589 { 590 u32 cnt, reg; 591 592 /* If at function entry a global reset was already in progress, i.e. 593 * state is not 'device active' or any of the reset done bits are not 594 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 595 * global reset is done. 596 */ 597 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 598 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 599 /* poll on global reset currently in progress until done */ 600 if (ice_check_reset(hw)) 601 return ICE_ERR_RESET_FAILED; 602 603 return 0; 604 } 605 606 /* Reset the PF */ 607 reg = rd32(hw, PFGEN_CTRL); 608 609 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 610 611 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 612 reg = rd32(hw, PFGEN_CTRL); 613 if (!(reg & PFGEN_CTRL_PFSWR_M)) 614 break; 615 616 mdelay(1); 617 } 618 619 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 620 ice_debug(hw, ICE_DBG_INIT, 621 "PF reset polling failed to complete.\n"); 622 return ICE_ERR_RESET_FAILED; 623 } 624 625 return 0; 626 } 627 628 /** 629 * ice_reset - Perform different types of reset 630 * @hw: pointer to the hardware structure 631 * @req: reset request 632 * 633 * This function triggers a reset as specified by the req parameter. 634 * 635 * Note: 636 * If anything other than a PF reset is triggered, PXE mode is restored. 637 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 638 * interface has been restored in the rebuild flow. 639 */ 640 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 641 { 642 u32 val = 0; 643 644 switch (req) { 645 case ICE_RESET_PFR: 646 return ice_pf_reset(hw); 647 case ICE_RESET_CORER: 648 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 649 val = GLGEN_RTRIG_CORER_M; 650 break; 651 case ICE_RESET_GLOBR: 652 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 653 val = GLGEN_RTRIG_GLOBR_M; 654 break; 655 } 656 657 val |= rd32(hw, GLGEN_RTRIG); 658 wr32(hw, GLGEN_RTRIG, val); 659 ice_flush(hw); 660 661 /* wait for the FW to be ready */ 662 return ice_check_reset(hw); 663 } 664 665 /** 666 * ice_copy_rxq_ctx_to_hw 667 * @hw: pointer to the hardware structure 668 * @ice_rxq_ctx: pointer to the rxq context 669 * @rxq_index: the index of the rx queue 670 * 671 * Copies rxq context from dense structure to hw register space 672 */ 673 static enum ice_status 674 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 675 { 676 u8 i; 677 678 if (!ice_rxq_ctx) 679 return ICE_ERR_BAD_PTR; 680 681 if (rxq_index > QRX_CTRL_MAX_INDEX) 682 return ICE_ERR_PARAM; 683 684 /* Copy each dword separately to hw */ 685 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 686 wr32(hw, QRX_CONTEXT(i, rxq_index), 687 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 688 689 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 690 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 691 } 692 693 return 0; 694 } 695 696 /* LAN Rx Queue Context */ 697 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 698 /* Field Width LSB */ 699 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 700 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 701 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 702 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 703 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 704 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 705 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 706 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 707 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 708 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 709 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 710 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 711 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 712 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 713 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 714 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 715 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 716 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 717 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 718 { 0 } 719 }; 720 721 /** 722 * ice_write_rxq_ctx 723 * @hw: pointer to the hardware structure 724 * @rlan_ctx: pointer to the rxq context 725 * @rxq_index: the index of the rx queue 726 * 727 * Converts rxq context from sparse to dense structure and then writes 728 * it to hw register space 729 */ 730 enum ice_status 731 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 732 u32 rxq_index) 733 { 734 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 735 736 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 737 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 738 } 739 740 /* LAN Tx Queue Context */ 741 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 742 /* Field Width LSB */ 743 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 744 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 745 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 746 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 747 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 748 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 749 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 750 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 751 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 752 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 753 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 754 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 755 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 756 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 757 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 758 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 759 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 760 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 761 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 762 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 763 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 764 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 765 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 766 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 767 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 768 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 769 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), 770 { 0 } 771 }; 772 773 /** 774 * ice_debug_cq 775 * @hw: pointer to the hardware structure 776 * @mask: debug mask 777 * @desc: pointer to control queue descriptor 778 * @buf: pointer to command buffer 779 * @buf_len: max length of buf 780 * 781 * Dumps debug log about control command with descriptor contents. 782 */ 783 void ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, 784 void *buf, u16 buf_len) 785 { 786 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; 787 u16 len; 788 789 #ifndef CONFIG_DYNAMIC_DEBUG 790 if (!(mask & hw->debug_mask)) 791 return; 792 #endif 793 794 if (!desc) 795 return; 796 797 len = le16_to_cpu(cq_desc->datalen); 798 799 ice_debug(hw, mask, 800 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 801 le16_to_cpu(cq_desc->opcode), 802 le16_to_cpu(cq_desc->flags), 803 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); 804 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 805 le32_to_cpu(cq_desc->cookie_high), 806 le32_to_cpu(cq_desc->cookie_low)); 807 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 808 le32_to_cpu(cq_desc->params.generic.param0), 809 le32_to_cpu(cq_desc->params.generic.param1)); 810 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 811 le32_to_cpu(cq_desc->params.generic.addr_high), 812 le32_to_cpu(cq_desc->params.generic.addr_low)); 813 if (buf && cq_desc->datalen != 0) { 814 ice_debug(hw, mask, "Buffer:\n"); 815 if (buf_len < len) 816 len = buf_len; 817 818 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); 819 } 820 } 821 822 /* FW Admin Queue command wrappers */ 823 824 /** 825 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 826 * @hw: pointer to the hw struct 827 * @desc: descriptor describing the command 828 * @buf: buffer to use for indirect commands (NULL for direct commands) 829 * @buf_size: size of buffer for indirect commands (0 for direct commands) 830 * @cd: pointer to command details structure 831 * 832 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 833 */ 834 enum ice_status 835 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 836 u16 buf_size, struct ice_sq_cd *cd) 837 { 838 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 839 } 840 841 /** 842 * ice_aq_get_fw_ver 843 * @hw: pointer to the hw struct 844 * @cd: pointer to command details structure or NULL 845 * 846 * Get the firmware version (0x0001) from the admin queue commands 847 */ 848 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 849 { 850 struct ice_aqc_get_ver *resp; 851 struct ice_aq_desc desc; 852 enum ice_status status; 853 854 resp = &desc.params.get_ver; 855 856 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 857 858 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 859 860 if (!status) { 861 hw->fw_branch = resp->fw_branch; 862 hw->fw_maj_ver = resp->fw_major; 863 hw->fw_min_ver = resp->fw_minor; 864 hw->fw_patch = resp->fw_patch; 865 hw->fw_build = le32_to_cpu(resp->fw_build); 866 hw->api_branch = resp->api_branch; 867 hw->api_maj_ver = resp->api_major; 868 hw->api_min_ver = resp->api_minor; 869 hw->api_patch = resp->api_patch; 870 } 871 872 return status; 873 } 874 875 /** 876 * ice_aq_q_shutdown 877 * @hw: pointer to the hw struct 878 * @unloading: is the driver unloading itself 879 * 880 * Tell the Firmware that we're shutting down the AdminQ and whether 881 * or not the driver is unloading as well (0x0003). 882 */ 883 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 884 { 885 struct ice_aqc_q_shutdown *cmd; 886 struct ice_aq_desc desc; 887 888 cmd = &desc.params.q_shutdown; 889 890 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 891 892 if (unloading) 893 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); 894 895 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 896 } 897 898 /** 899 * ice_aq_req_res 900 * @hw: pointer to the hw struct 901 * @res: resource id 902 * @access: access type 903 * @sdp_number: resource number 904 * @timeout: the maximum time in ms that the driver may hold the resource 905 * @cd: pointer to command details structure or NULL 906 * 907 * requests common resource using the admin queue commands (0x0008) 908 */ 909 static enum ice_status 910 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 911 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 912 struct ice_sq_cd *cd) 913 { 914 struct ice_aqc_req_res *cmd_resp; 915 struct ice_aq_desc desc; 916 enum ice_status status; 917 918 cmd_resp = &desc.params.res_owner; 919 920 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 921 922 cmd_resp->res_id = cpu_to_le16(res); 923 cmd_resp->access_type = cpu_to_le16(access); 924 cmd_resp->res_number = cpu_to_le32(sdp_number); 925 926 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 927 /* The completion specifies the maximum time in ms that the driver 928 * may hold the resource in the Timeout field. 929 * If the resource is held by someone else, the command completes with 930 * busy return value and the timeout field indicates the maximum time 931 * the current owner of the resource has to free it. 932 */ 933 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 934 *timeout = le32_to_cpu(cmd_resp->timeout); 935 936 return status; 937 } 938 939 /** 940 * ice_aq_release_res 941 * @hw: pointer to the hw struct 942 * @res: resource id 943 * @sdp_number: resource number 944 * @cd: pointer to command details structure or NULL 945 * 946 * release common resource using the admin queue commands (0x0009) 947 */ 948 static enum ice_status 949 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 950 struct ice_sq_cd *cd) 951 { 952 struct ice_aqc_req_res *cmd; 953 struct ice_aq_desc desc; 954 955 cmd = &desc.params.res_owner; 956 957 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 958 959 cmd->res_id = cpu_to_le16(res); 960 cmd->res_number = cpu_to_le32(sdp_number); 961 962 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 963 } 964 965 /** 966 * ice_acquire_res 967 * @hw: pointer to the HW structure 968 * @res: resource id 969 * @access: access type (read or write) 970 * 971 * This function will attempt to acquire the ownership of a resource. 972 */ 973 enum ice_status 974 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 975 enum ice_aq_res_access_type access) 976 { 977 #define ICE_RES_POLLING_DELAY_MS 10 978 u32 delay = ICE_RES_POLLING_DELAY_MS; 979 enum ice_status status; 980 u32 time_left = 0; 981 u32 timeout; 982 983 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 984 985 /* An admin queue return code of ICE_AQ_RC_EEXIST means that another 986 * driver has previously acquired the resource and performed any 987 * necessary updates; in this case the caller does not obtain the 988 * resource and has no further work to do. 989 */ 990 if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { 991 status = ICE_ERR_AQ_NO_WORK; 992 goto ice_acquire_res_exit; 993 } 994 995 if (status) 996 ice_debug(hw, ICE_DBG_RES, 997 "resource %d acquire type %d failed.\n", res, access); 998 999 /* If necessary, poll until the current lock owner timeouts */ 1000 timeout = time_left; 1001 while (status && timeout && time_left) { 1002 mdelay(delay); 1003 timeout = (timeout > delay) ? timeout - delay : 0; 1004 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1005 1006 if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { 1007 /* lock free, but no work to do */ 1008 status = ICE_ERR_AQ_NO_WORK; 1009 break; 1010 } 1011 1012 if (!status) 1013 /* lock acquired */ 1014 break; 1015 } 1016 if (status && status != ICE_ERR_AQ_NO_WORK) 1017 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1018 1019 ice_acquire_res_exit: 1020 if (status == ICE_ERR_AQ_NO_WORK) { 1021 if (access == ICE_RES_WRITE) 1022 ice_debug(hw, ICE_DBG_RES, 1023 "resource indicates no work to do.\n"); 1024 else 1025 ice_debug(hw, ICE_DBG_RES, 1026 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1027 } 1028 return status; 1029 } 1030 1031 /** 1032 * ice_release_res 1033 * @hw: pointer to the HW structure 1034 * @res: resource id 1035 * 1036 * This function will release a resource using the proper Admin Command. 1037 */ 1038 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1039 { 1040 enum ice_status status; 1041 u32 total_delay = 0; 1042 1043 status = ice_aq_release_res(hw, res, 0, NULL); 1044 1045 /* there are some rare cases when trying to release the resource 1046 * results in an admin Q timeout, so handle them correctly 1047 */ 1048 while ((status == ICE_ERR_AQ_TIMEOUT) && 1049 (total_delay < hw->adminq.sq_cmd_timeout)) { 1050 mdelay(1); 1051 status = ice_aq_release_res(hw, res, 0, NULL); 1052 total_delay++; 1053 } 1054 } 1055 1056 /** 1057 * ice_parse_caps - parse function/device capabilities 1058 * @hw: pointer to the hw struct 1059 * @buf: pointer to a buffer containing function/device capability records 1060 * @cap_count: number of capability records in the list 1061 * @opc: type of capabilities list to parse 1062 * 1063 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1064 */ 1065 static void 1066 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1067 enum ice_adminq_opc opc) 1068 { 1069 struct ice_aqc_list_caps_elem *cap_resp; 1070 struct ice_hw_func_caps *func_p = NULL; 1071 struct ice_hw_dev_caps *dev_p = NULL; 1072 struct ice_hw_common_caps *caps; 1073 u32 i; 1074 1075 if (!buf) 1076 return; 1077 1078 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1079 1080 if (opc == ice_aqc_opc_list_dev_caps) { 1081 dev_p = &hw->dev_caps; 1082 caps = &dev_p->common_cap; 1083 } else if (opc == ice_aqc_opc_list_func_caps) { 1084 func_p = &hw->func_caps; 1085 caps = &func_p->common_cap; 1086 } else { 1087 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1088 return; 1089 } 1090 1091 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1092 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1093 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1094 u32 number = le32_to_cpu(cap_resp->number); 1095 u16 cap = le16_to_cpu(cap_resp->cap); 1096 1097 switch (cap) { 1098 case ICE_AQC_CAPS_VSI: 1099 if (dev_p) { 1100 dev_p->num_vsi_allocd_to_host = number; 1101 ice_debug(hw, ICE_DBG_INIT, 1102 "HW caps: Dev.VSI cnt = %d\n", 1103 dev_p->num_vsi_allocd_to_host); 1104 } else if (func_p) { 1105 func_p->guaranteed_num_vsi = number; 1106 ice_debug(hw, ICE_DBG_INIT, 1107 "HW caps: Func.VSI cnt = %d\n", 1108 func_p->guaranteed_num_vsi); 1109 } 1110 break; 1111 case ICE_AQC_CAPS_RSS: 1112 caps->rss_table_size = number; 1113 caps->rss_table_entry_width = logical_id; 1114 ice_debug(hw, ICE_DBG_INIT, 1115 "HW caps: RSS table size = %d\n", 1116 caps->rss_table_size); 1117 ice_debug(hw, ICE_DBG_INIT, 1118 "HW caps: RSS table width = %d\n", 1119 caps->rss_table_entry_width); 1120 break; 1121 case ICE_AQC_CAPS_RXQS: 1122 caps->num_rxq = number; 1123 caps->rxq_first_id = phys_id; 1124 ice_debug(hw, ICE_DBG_INIT, 1125 "HW caps: Num Rx Qs = %d\n", caps->num_rxq); 1126 ice_debug(hw, ICE_DBG_INIT, 1127 "HW caps: Rx first queue ID = %d\n", 1128 caps->rxq_first_id); 1129 break; 1130 case ICE_AQC_CAPS_TXQS: 1131 caps->num_txq = number; 1132 caps->txq_first_id = phys_id; 1133 ice_debug(hw, ICE_DBG_INIT, 1134 "HW caps: Num Tx Qs = %d\n", caps->num_txq); 1135 ice_debug(hw, ICE_DBG_INIT, 1136 "HW caps: Tx first queue ID = %d\n", 1137 caps->txq_first_id); 1138 break; 1139 case ICE_AQC_CAPS_MSIX: 1140 caps->num_msix_vectors = number; 1141 caps->msix_vector_first_id = phys_id; 1142 ice_debug(hw, ICE_DBG_INIT, 1143 "HW caps: MSIX vector count = %d\n", 1144 caps->num_msix_vectors); 1145 ice_debug(hw, ICE_DBG_INIT, 1146 "HW caps: MSIX first vector index = %d\n", 1147 caps->msix_vector_first_id); 1148 break; 1149 case ICE_AQC_CAPS_MAX_MTU: 1150 caps->max_mtu = number; 1151 if (dev_p) 1152 ice_debug(hw, ICE_DBG_INIT, 1153 "HW caps: Dev.MaxMTU = %d\n", 1154 caps->max_mtu); 1155 else if (func_p) 1156 ice_debug(hw, ICE_DBG_INIT, 1157 "HW caps: func.MaxMTU = %d\n", 1158 caps->max_mtu); 1159 break; 1160 default: 1161 ice_debug(hw, ICE_DBG_INIT, 1162 "HW caps: Unknown capability[%d]: 0x%x\n", i, 1163 cap); 1164 break; 1165 } 1166 } 1167 } 1168 1169 /** 1170 * ice_aq_discover_caps - query function/device capabilities 1171 * @hw: pointer to the hw struct 1172 * @buf: a virtual buffer to hold the capabilities 1173 * @buf_size: Size of the virtual buffer 1174 * @data_size: Size of the returned data, or buf size needed if AQ err==ENOMEM 1175 * @opc: capabilities type to discover - pass in the command opcode 1176 * @cd: pointer to command details structure or NULL 1177 * 1178 * Get the function(0x000a)/device(0x000b) capabilities description from 1179 * the firmware. 1180 */ 1181 static enum ice_status 1182 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u16 *data_size, 1183 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1184 { 1185 struct ice_aqc_list_caps *cmd; 1186 struct ice_aq_desc desc; 1187 enum ice_status status; 1188 1189 cmd = &desc.params.get_cap; 1190 1191 if (opc != ice_aqc_opc_list_func_caps && 1192 opc != ice_aqc_opc_list_dev_caps) 1193 return ICE_ERR_PARAM; 1194 1195 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1196 1197 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1198 if (!status) 1199 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1200 *data_size = le16_to_cpu(desc.datalen); 1201 1202 return status; 1203 } 1204 1205 /** 1206 * ice_get_caps - get info about the HW 1207 * @hw: pointer to the hardware structure 1208 */ 1209 enum ice_status ice_get_caps(struct ice_hw *hw) 1210 { 1211 enum ice_status status; 1212 u16 data_size = 0; 1213 u16 cbuf_len; 1214 u8 retries; 1215 1216 /* The driver doesn't know how many capabilities the device will return 1217 * so the buffer size required isn't known ahead of time. The driver 1218 * starts with cbuf_len and if this turns out to be insufficient, the 1219 * device returns ICE_AQ_RC_ENOMEM and also the buffer size it needs. 1220 * The driver then allocates the buffer of this size and retries the 1221 * operation. So it follows that the retry count is 2. 1222 */ 1223 #define ICE_GET_CAP_BUF_COUNT 40 1224 #define ICE_GET_CAP_RETRY_COUNT 2 1225 1226 cbuf_len = ICE_GET_CAP_BUF_COUNT * 1227 sizeof(struct ice_aqc_list_caps_elem); 1228 1229 retries = ICE_GET_CAP_RETRY_COUNT; 1230 1231 do { 1232 void *cbuf; 1233 1234 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1235 if (!cbuf) 1236 return ICE_ERR_NO_MEMORY; 1237 1238 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &data_size, 1239 ice_aqc_opc_list_func_caps, NULL); 1240 devm_kfree(ice_hw_to_dev(hw), cbuf); 1241 1242 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1243 break; 1244 1245 /* If ENOMEM is returned, try again with bigger buffer */ 1246 cbuf_len = data_size; 1247 } while (--retries); 1248 1249 return status; 1250 } 1251 1252 /** 1253 * ice_aq_manage_mac_write - manage MAC address write command 1254 * @hw: pointer to the hw struct 1255 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1256 * @flags: flags to control write behavior 1257 * @cd: pointer to command details structure or NULL 1258 * 1259 * This function is used to write MAC address to the NVM (0x0108). 1260 */ 1261 enum ice_status 1262 ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags, 1263 struct ice_sq_cd *cd) 1264 { 1265 struct ice_aqc_manage_mac_write *cmd; 1266 struct ice_aq_desc desc; 1267 1268 cmd = &desc.params.mac_write; 1269 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 1270 1271 cmd->flags = flags; 1272 1273 /* Prep values for flags, sah, sal */ 1274 cmd->sah = htons(*((u16 *)mac_addr)); 1275 cmd->sal = htonl(*((u32 *)(mac_addr + 2))); 1276 1277 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1278 } 1279 1280 /** 1281 * ice_aq_clear_pxe_mode 1282 * @hw: pointer to the hw struct 1283 * 1284 * Tell the firmware that the driver is taking over from PXE (0x0110). 1285 */ 1286 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 1287 { 1288 struct ice_aq_desc desc; 1289 1290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 1291 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 1292 1293 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1294 } 1295 1296 /** 1297 * ice_clear_pxe_mode - clear pxe operations mode 1298 * @hw: pointer to the hw struct 1299 * 1300 * Make sure all PXE mode settings are cleared, including things 1301 * like descriptor fetch/write-back mode. 1302 */ 1303 void ice_clear_pxe_mode(struct ice_hw *hw) 1304 { 1305 if (ice_check_sq_alive(hw, &hw->adminq)) 1306 ice_aq_clear_pxe_mode(hw); 1307 } 1308 1309 /** 1310 * ice_aq_set_phy_cfg 1311 * @hw: pointer to the hw struct 1312 * @lport: logical port number 1313 * @cfg: structure with PHY configuration data to be set 1314 * @cd: pointer to command details structure or NULL 1315 * 1316 * Set the various PHY configuration parameters supported on the Port. 1317 * One or more of the Set PHY config parameters may be ignored in an MFP 1318 * mode as the PF may not have the privilege to set some of the PHY Config 1319 * parameters. This status will be indicated by the command response (0x0601). 1320 */ 1321 static enum ice_status 1322 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 1323 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 1324 { 1325 struct ice_aqc_set_phy_cfg *cmd; 1326 struct ice_aq_desc desc; 1327 1328 if (!cfg) 1329 return ICE_ERR_PARAM; 1330 1331 cmd = &desc.params.set_phy; 1332 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 1333 cmd->lport_num = lport; 1334 1335 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 1336 } 1337 1338 /** 1339 * ice_update_link_info - update status of the HW network link 1340 * @pi: port info structure of the interested logical port 1341 */ 1342 static enum ice_status 1343 ice_update_link_info(struct ice_port_info *pi) 1344 { 1345 struct ice_aqc_get_phy_caps_data *pcaps; 1346 struct ice_phy_info *phy_info; 1347 enum ice_status status; 1348 struct ice_hw *hw; 1349 1350 if (!pi) 1351 return ICE_ERR_PARAM; 1352 1353 hw = pi->hw; 1354 1355 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1356 if (!pcaps) 1357 return ICE_ERR_NO_MEMORY; 1358 1359 phy_info = &pi->phy; 1360 status = ice_aq_get_link_info(pi, true, NULL, NULL); 1361 if (status) 1362 goto out; 1363 1364 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { 1365 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, 1366 pcaps, NULL); 1367 if (status) 1368 goto out; 1369 1370 memcpy(phy_info->link_info.module_type, &pcaps->module_type, 1371 sizeof(phy_info->link_info.module_type)); 1372 } 1373 out: 1374 devm_kfree(ice_hw_to_dev(hw), pcaps); 1375 return status; 1376 } 1377 1378 /** 1379 * ice_set_fc 1380 * @pi: port information structure 1381 * @aq_failures: pointer to status code, specific to ice_set_fc routine 1382 * @atomic_restart: enable automatic link update 1383 * 1384 * Set the requested flow control mode. 1385 */ 1386 enum ice_status 1387 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool atomic_restart) 1388 { 1389 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 1390 struct ice_aqc_get_phy_caps_data *pcaps; 1391 enum ice_status status; 1392 u8 pause_mask = 0x0; 1393 struct ice_hw *hw; 1394 1395 if (!pi) 1396 return ICE_ERR_PARAM; 1397 hw = pi->hw; 1398 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 1399 1400 switch (pi->fc.req_mode) { 1401 case ICE_FC_FULL: 1402 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 1403 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 1404 break; 1405 case ICE_FC_RX_PAUSE: 1406 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 1407 break; 1408 case ICE_FC_TX_PAUSE: 1409 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1416 if (!pcaps) 1417 return ICE_ERR_NO_MEMORY; 1418 1419 /* Get the current phy config */ 1420 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 1421 NULL); 1422 if (status) { 1423 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 1424 goto out; 1425 } 1426 1427 /* clear the old pause settings */ 1428 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 1429 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 1430 /* set the new capabilities */ 1431 cfg.caps |= pause_mask; 1432 /* If the capabilities have changed, then set the new config */ 1433 if (cfg.caps != pcaps->caps) { 1434 int retry_count, retry_max = 10; 1435 1436 /* Auto restart link so settings take effect */ 1437 if (atomic_restart) 1438 cfg.caps |= ICE_AQ_PHY_ENA_ATOMIC_LINK; 1439 /* Copy over all the old settings */ 1440 cfg.phy_type_low = pcaps->phy_type_low; 1441 cfg.low_power_ctrl = pcaps->low_power_ctrl; 1442 cfg.eee_cap = pcaps->eee_cap; 1443 cfg.eeer_value = pcaps->eeer_value; 1444 cfg.link_fec_opt = pcaps->link_fec_options; 1445 1446 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 1447 if (status) { 1448 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 1449 goto out; 1450 } 1451 1452 /* Update the link info 1453 * It sometimes takes a really long time for link to 1454 * come back from the atomic reset. Thus, we wait a 1455 * little bit. 1456 */ 1457 for (retry_count = 0; retry_count < retry_max; retry_count++) { 1458 status = ice_update_link_info(pi); 1459 1460 if (!status) 1461 break; 1462 1463 mdelay(100); 1464 } 1465 1466 if (status) 1467 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 1468 } 1469 1470 out: 1471 devm_kfree(ice_hw_to_dev(hw), pcaps); 1472 return status; 1473 } 1474 1475 /** 1476 * ice_get_link_status - get status of the HW network link 1477 * @pi: port information structure 1478 * @link_up: pointer to bool (true/false = linkup/linkdown) 1479 * 1480 * Variable link_up is true if link is up, false if link is down. 1481 * The variable link_up is invalid if status is non zero. As a 1482 * result of this call, link status reporting becomes enabled 1483 */ 1484 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 1485 { 1486 struct ice_phy_info *phy_info; 1487 enum ice_status status = 0; 1488 1489 if (!pi || !link_up) 1490 return ICE_ERR_PARAM; 1491 1492 phy_info = &pi->phy; 1493 1494 if (phy_info->get_link_info) { 1495 status = ice_update_link_info(pi); 1496 1497 if (status) 1498 ice_debug(pi->hw, ICE_DBG_LINK, 1499 "get link status error, status = %d\n", 1500 status); 1501 } 1502 1503 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 1504 1505 return status; 1506 } 1507 1508 /** 1509 * ice_aq_set_link_restart_an 1510 * @pi: pointer to the port information structure 1511 * @ena_link: if true: enable link, if false: disable link 1512 * @cd: pointer to command details structure or NULL 1513 * 1514 * Sets up the link and restarts the Auto-Negotiation over the link. 1515 */ 1516 enum ice_status 1517 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 1518 struct ice_sq_cd *cd) 1519 { 1520 struct ice_aqc_restart_an *cmd; 1521 struct ice_aq_desc desc; 1522 1523 cmd = &desc.params.restart_an; 1524 1525 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 1526 1527 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 1528 cmd->lport_num = pi->lport; 1529 if (ena_link) 1530 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 1531 else 1532 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 1533 1534 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 1535 } 1536 1537 /** 1538 * ice_aq_set_event_mask 1539 * @hw: pointer to the hw struct 1540 * @port_num: port number of the physical function 1541 * @mask: event mask to be set 1542 * @cd: pointer to command details structure or NULL 1543 * 1544 * Set event mask (0x0613) 1545 */ 1546 enum ice_status 1547 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 1548 struct ice_sq_cd *cd) 1549 { 1550 struct ice_aqc_set_event_mask *cmd; 1551 struct ice_aq_desc desc; 1552 1553 cmd = &desc.params.set_event_mask; 1554 1555 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 1556 1557 cmd->lport_num = port_num; 1558 1559 cmd->event_mask = cpu_to_le16(mask); 1560 1561 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1562 } 1563 1564 /** 1565 * __ice_aq_get_set_rss_lut 1566 * @hw: pointer to the hardware structure 1567 * @vsi_id: VSI FW index 1568 * @lut_type: LUT table type 1569 * @lut: pointer to the LUT buffer provided by the caller 1570 * @lut_size: size of the LUT buffer 1571 * @glob_lut_idx: global LUT index 1572 * @set: set true to set the table, false to get the table 1573 * 1574 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 1575 */ 1576 static enum ice_status 1577 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1578 u16 lut_size, u8 glob_lut_idx, bool set) 1579 { 1580 struct ice_aqc_get_set_rss_lut *cmd_resp; 1581 struct ice_aq_desc desc; 1582 enum ice_status status; 1583 u16 flags = 0; 1584 1585 cmd_resp = &desc.params.get_set_rss_lut; 1586 1587 if (set) { 1588 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 1589 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1590 } else { 1591 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 1592 } 1593 1594 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 1595 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 1596 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 1597 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 1598 1599 switch (lut_type) { 1600 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 1601 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 1602 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 1603 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 1604 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 1605 break; 1606 default: 1607 status = ICE_ERR_PARAM; 1608 goto ice_aq_get_set_rss_lut_exit; 1609 } 1610 1611 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 1612 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 1613 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 1614 1615 if (!set) 1616 goto ice_aq_get_set_rss_lut_send; 1617 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 1618 if (!set) 1619 goto ice_aq_get_set_rss_lut_send; 1620 } else { 1621 goto ice_aq_get_set_rss_lut_send; 1622 } 1623 1624 /* LUT size is only valid for Global and PF table types */ 1625 switch (lut_size) { 1626 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 1627 break; 1628 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 1629 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 1630 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 1631 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 1632 break; 1633 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 1634 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 1635 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 1636 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 1637 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 1638 break; 1639 } 1640 /* fall-through */ 1641 default: 1642 status = ICE_ERR_PARAM; 1643 goto ice_aq_get_set_rss_lut_exit; 1644 } 1645 1646 ice_aq_get_set_rss_lut_send: 1647 cmd_resp->flags = cpu_to_le16(flags); 1648 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 1649 1650 ice_aq_get_set_rss_lut_exit: 1651 return status; 1652 } 1653 1654 /** 1655 * ice_aq_get_rss_lut 1656 * @hw: pointer to the hardware structure 1657 * @vsi_id: VSI FW index 1658 * @lut_type: LUT table type 1659 * @lut: pointer to the LUT buffer provided by the caller 1660 * @lut_size: size of the LUT buffer 1661 * 1662 * get the RSS lookup table, PF or VSI type 1663 */ 1664 enum ice_status 1665 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1666 u16 lut_size) 1667 { 1668 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, 1669 false); 1670 } 1671 1672 /** 1673 * ice_aq_set_rss_lut 1674 * @hw: pointer to the hardware structure 1675 * @vsi_id: VSI FW index 1676 * @lut_type: LUT table type 1677 * @lut: pointer to the LUT buffer provided by the caller 1678 * @lut_size: size of the LUT buffer 1679 * 1680 * set the RSS lookup table, PF or VSI type 1681 */ 1682 enum ice_status 1683 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1684 u16 lut_size) 1685 { 1686 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, 1687 true); 1688 } 1689 1690 /** 1691 * __ice_aq_get_set_rss_key 1692 * @hw: pointer to the hw struct 1693 * @vsi_id: VSI FW index 1694 * @key: pointer to key info struct 1695 * @set: set true to set the key, false to get the key 1696 * 1697 * get (0x0B04) or set (0x0B02) the RSS key per VSI 1698 */ 1699 static enum 1700 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 1701 struct ice_aqc_get_set_rss_keys *key, 1702 bool set) 1703 { 1704 struct ice_aqc_get_set_rss_key *cmd_resp; 1705 u16 key_size = sizeof(*key); 1706 struct ice_aq_desc desc; 1707 1708 cmd_resp = &desc.params.get_set_rss_key; 1709 1710 if (set) { 1711 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 1712 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1713 } else { 1714 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 1715 } 1716 1717 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 1718 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 1719 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 1720 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 1721 1722 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 1723 } 1724 1725 /** 1726 * ice_aq_get_rss_key 1727 * @hw: pointer to the hw struct 1728 * @vsi_id: VSI FW index 1729 * @key: pointer to key info struct 1730 * 1731 * get the RSS key per VSI 1732 */ 1733 enum ice_status 1734 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_id, 1735 struct ice_aqc_get_set_rss_keys *key) 1736 { 1737 return __ice_aq_get_set_rss_key(hw, vsi_id, key, false); 1738 } 1739 1740 /** 1741 * ice_aq_set_rss_key 1742 * @hw: pointer to the hw struct 1743 * @vsi_id: VSI FW index 1744 * @keys: pointer to key info struct 1745 * 1746 * set the RSS key per VSI 1747 */ 1748 enum ice_status 1749 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_id, 1750 struct ice_aqc_get_set_rss_keys *keys) 1751 { 1752 return __ice_aq_get_set_rss_key(hw, vsi_id, keys, true); 1753 } 1754 1755 /** 1756 * ice_aq_add_lan_txq 1757 * @hw: pointer to the hardware structure 1758 * @num_qgrps: Number of added queue groups 1759 * @qg_list: list of queue groups to be added 1760 * @buf_size: size of buffer for indirect command 1761 * @cd: pointer to command details structure or NULL 1762 * 1763 * Add Tx LAN queue (0x0C30) 1764 * 1765 * NOTE: 1766 * Prior to calling add Tx LAN queue: 1767 * Initialize the following as part of the Tx queue context: 1768 * Completion queue ID if the queue uses Completion queue, Quanta profile, 1769 * Cache profile and Packet shaper profile. 1770 * 1771 * After add Tx LAN queue AQ command is completed: 1772 * Interrupts should be associated with specific queues, 1773 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 1774 * flow. 1775 */ 1776 static enum ice_status 1777 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 1778 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 1779 struct ice_sq_cd *cd) 1780 { 1781 u16 i, sum_header_size, sum_q_size = 0; 1782 struct ice_aqc_add_tx_qgrp *list; 1783 struct ice_aqc_add_txqs *cmd; 1784 struct ice_aq_desc desc; 1785 1786 cmd = &desc.params.add_txqs; 1787 1788 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 1789 1790 if (!qg_list) 1791 return ICE_ERR_PARAM; 1792 1793 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 1794 return ICE_ERR_PARAM; 1795 1796 sum_header_size = num_qgrps * 1797 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 1798 1799 list = qg_list; 1800 for (i = 0; i < num_qgrps; i++) { 1801 struct ice_aqc_add_txqs_perq *q = list->txqs; 1802 1803 sum_q_size += list->num_txqs * sizeof(*q); 1804 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 1805 } 1806 1807 if (buf_size != (sum_header_size + sum_q_size)) 1808 return ICE_ERR_PARAM; 1809 1810 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1811 1812 cmd->num_qgrps = num_qgrps; 1813 1814 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 1815 } 1816 1817 /** 1818 * ice_aq_dis_lan_txq 1819 * @hw: pointer to the hardware structure 1820 * @num_qgrps: number of groups in the list 1821 * @qg_list: the list of groups to disable 1822 * @buf_size: the total size of the qg_list buffer in bytes 1823 * @cd: pointer to command details structure or NULL 1824 * 1825 * Disable LAN Tx queue (0x0C31) 1826 */ 1827 static enum ice_status 1828 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 1829 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 1830 struct ice_sq_cd *cd) 1831 { 1832 struct ice_aqc_dis_txqs *cmd; 1833 struct ice_aq_desc desc; 1834 u16 i, sz = 0; 1835 1836 cmd = &desc.params.dis_txqs; 1837 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 1838 1839 if (!qg_list) 1840 return ICE_ERR_PARAM; 1841 1842 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 1843 return ICE_ERR_PARAM; 1844 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1845 cmd->num_entries = num_qgrps; 1846 1847 for (i = 0; i < num_qgrps; ++i) { 1848 /* Calculate the size taken up by the queue IDs in this group */ 1849 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 1850 1851 /* Add the size of the group header */ 1852 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 1853 1854 /* If the num of queues is even, add 2 bytes of padding */ 1855 if ((qg_list[i].num_qs % 2) == 0) 1856 sz += 2; 1857 } 1858 1859 if (buf_size != sz) 1860 return ICE_ERR_PARAM; 1861 1862 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 1863 } 1864 1865 /* End of FW Admin Queue command wrappers */ 1866 1867 /** 1868 * ice_write_byte - write a byte to a packed context structure 1869 * @src_ctx: the context structure to read from 1870 * @dest_ctx: the context to be written to 1871 * @ce_info: a description of the struct to be filled 1872 */ 1873 static void ice_write_byte(u8 *src_ctx, u8 *dest_ctx, 1874 const struct ice_ctx_ele *ce_info) 1875 { 1876 u8 src_byte, dest_byte, mask; 1877 u8 *from, *dest; 1878 u16 shift_width; 1879 1880 /* copy from the next struct field */ 1881 from = src_ctx + ce_info->offset; 1882 1883 /* prepare the bits and mask */ 1884 shift_width = ce_info->lsb % 8; 1885 mask = (u8)(BIT(ce_info->width) - 1); 1886 1887 src_byte = *from; 1888 src_byte &= mask; 1889 1890 /* shift to correct alignment */ 1891 mask <<= shift_width; 1892 src_byte <<= shift_width; 1893 1894 /* get the current bits from the target bit string */ 1895 dest = dest_ctx + (ce_info->lsb / 8); 1896 1897 memcpy(&dest_byte, dest, sizeof(dest_byte)); 1898 1899 dest_byte &= ~mask; /* get the bits not changing */ 1900 dest_byte |= src_byte; /* add in the new bits */ 1901 1902 /* put it all back */ 1903 memcpy(dest, &dest_byte, sizeof(dest_byte)); 1904 } 1905 1906 /** 1907 * ice_write_word - write a word to a packed context structure 1908 * @src_ctx: the context structure to read from 1909 * @dest_ctx: the context to be written to 1910 * @ce_info: a description of the struct to be filled 1911 */ 1912 static void ice_write_word(u8 *src_ctx, u8 *dest_ctx, 1913 const struct ice_ctx_ele *ce_info) 1914 { 1915 u16 src_word, mask; 1916 __le16 dest_word; 1917 u8 *from, *dest; 1918 u16 shift_width; 1919 1920 /* copy from the next struct field */ 1921 from = src_ctx + ce_info->offset; 1922 1923 /* prepare the bits and mask */ 1924 shift_width = ce_info->lsb % 8; 1925 mask = BIT(ce_info->width) - 1; 1926 1927 /* don't swizzle the bits until after the mask because the mask bits 1928 * will be in a different bit position on big endian machines 1929 */ 1930 src_word = *(u16 *)from; 1931 src_word &= mask; 1932 1933 /* shift to correct alignment */ 1934 mask <<= shift_width; 1935 src_word <<= shift_width; 1936 1937 /* get the current bits from the target bit string */ 1938 dest = dest_ctx + (ce_info->lsb / 8); 1939 1940 memcpy(&dest_word, dest, sizeof(dest_word)); 1941 1942 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 1943 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 1944 1945 /* put it all back */ 1946 memcpy(dest, &dest_word, sizeof(dest_word)); 1947 } 1948 1949 /** 1950 * ice_write_dword - write a dword to a packed context structure 1951 * @src_ctx: the context structure to read from 1952 * @dest_ctx: the context to be written to 1953 * @ce_info: a description of the struct to be filled 1954 */ 1955 static void ice_write_dword(u8 *src_ctx, u8 *dest_ctx, 1956 const struct ice_ctx_ele *ce_info) 1957 { 1958 u32 src_dword, mask; 1959 __le32 dest_dword; 1960 u8 *from, *dest; 1961 u16 shift_width; 1962 1963 /* copy from the next struct field */ 1964 from = src_ctx + ce_info->offset; 1965 1966 /* prepare the bits and mask */ 1967 shift_width = ce_info->lsb % 8; 1968 1969 /* if the field width is exactly 32 on an x86 machine, then the shift 1970 * operation will not work because the SHL instructions count is masked 1971 * to 5 bits so the shift will do nothing 1972 */ 1973 if (ce_info->width < 32) 1974 mask = BIT(ce_info->width) - 1; 1975 else 1976 mask = (u32)~0; 1977 1978 /* don't swizzle the bits until after the mask because the mask bits 1979 * will be in a different bit position on big endian machines 1980 */ 1981 src_dword = *(u32 *)from; 1982 src_dword &= mask; 1983 1984 /* shift to correct alignment */ 1985 mask <<= shift_width; 1986 src_dword <<= shift_width; 1987 1988 /* get the current bits from the target bit string */ 1989 dest = dest_ctx + (ce_info->lsb / 8); 1990 1991 memcpy(&dest_dword, dest, sizeof(dest_dword)); 1992 1993 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 1994 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 1995 1996 /* put it all back */ 1997 memcpy(dest, &dest_dword, sizeof(dest_dword)); 1998 } 1999 2000 /** 2001 * ice_write_qword - write a qword to a packed context structure 2002 * @src_ctx: the context structure to read from 2003 * @dest_ctx: the context to be written to 2004 * @ce_info: a description of the struct to be filled 2005 */ 2006 static void ice_write_qword(u8 *src_ctx, u8 *dest_ctx, 2007 const struct ice_ctx_ele *ce_info) 2008 { 2009 u64 src_qword, mask; 2010 __le64 dest_qword; 2011 u8 *from, *dest; 2012 u16 shift_width; 2013 2014 /* copy from the next struct field */ 2015 from = src_ctx + ce_info->offset; 2016 2017 /* prepare the bits and mask */ 2018 shift_width = ce_info->lsb % 8; 2019 2020 /* if the field width is exactly 64 on an x86 machine, then the shift 2021 * operation will not work because the SHL instructions count is masked 2022 * to 6 bits so the shift will do nothing 2023 */ 2024 if (ce_info->width < 64) 2025 mask = BIT_ULL(ce_info->width) - 1; 2026 else 2027 mask = (u64)~0; 2028 2029 /* don't swizzle the bits until after the mask because the mask bits 2030 * will be in a different bit position on big endian machines 2031 */ 2032 src_qword = *(u64 *)from; 2033 src_qword &= mask; 2034 2035 /* shift to correct alignment */ 2036 mask <<= shift_width; 2037 src_qword <<= shift_width; 2038 2039 /* get the current bits from the target bit string */ 2040 dest = dest_ctx + (ce_info->lsb / 8); 2041 2042 memcpy(&dest_qword, dest, sizeof(dest_qword)); 2043 2044 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 2045 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 2046 2047 /* put it all back */ 2048 memcpy(dest, &dest_qword, sizeof(dest_qword)); 2049 } 2050 2051 /** 2052 * ice_set_ctx - set context bits in packed structure 2053 * @src_ctx: pointer to a generic non-packed context structure 2054 * @dest_ctx: pointer to memory for the packed structure 2055 * @ce_info: a description of the structure to be transformed 2056 */ 2057 enum ice_status 2058 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2059 { 2060 int f; 2061 2062 for (f = 0; ce_info[f].width; f++) { 2063 /* We have to deal with each element of the FW response 2064 * using the correct size so that we are correct regardless 2065 * of the endianness of the machine. 2066 */ 2067 switch (ce_info[f].size_of) { 2068 case sizeof(u8): 2069 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 2070 break; 2071 case sizeof(u16): 2072 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 2073 break; 2074 case sizeof(u32): 2075 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 2076 break; 2077 case sizeof(u64): 2078 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 2079 break; 2080 default: 2081 return ICE_ERR_INVAL_SIZE; 2082 } 2083 } 2084 2085 return 0; 2086 } 2087 2088 /** 2089 * ice_ena_vsi_txq 2090 * @pi: port information structure 2091 * @vsi_id: VSI id 2092 * @tc: tc number 2093 * @num_qgrps: Number of added queue groups 2094 * @buf: list of queue groups to be added 2095 * @buf_size: size of buffer for indirect command 2096 * @cd: pointer to command details structure or NULL 2097 * 2098 * This function adds one lan q 2099 */ 2100 enum ice_status 2101 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_id, u8 tc, u8 num_qgrps, 2102 struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 2103 struct ice_sq_cd *cd) 2104 { 2105 struct ice_aqc_txsched_elem_data node = { 0 }; 2106 struct ice_sched_node *parent; 2107 enum ice_status status; 2108 struct ice_hw *hw; 2109 2110 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2111 return ICE_ERR_CFG; 2112 2113 if (num_qgrps > 1 || buf->num_txqs > 1) 2114 return ICE_ERR_MAX_LIMIT; 2115 2116 hw = pi->hw; 2117 2118 mutex_lock(&pi->sched_lock); 2119 2120 /* find a parent node */ 2121 parent = ice_sched_get_free_qparent(pi, vsi_id, tc, 2122 ICE_SCHED_NODE_OWNER_LAN); 2123 if (!parent) { 2124 status = ICE_ERR_PARAM; 2125 goto ena_txq_exit; 2126 } 2127 buf->parent_teid = parent->info.node_teid; 2128 node.parent_teid = parent->info.node_teid; 2129 /* Mark that the values in the "generic" section as valid. The default 2130 * value in the "generic" section is zero. This means that : 2131 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 2132 * - 0 priority among siblings, indicated by Bit 1-3. 2133 * - WFQ, indicated by Bit 4. 2134 * - 0 Adjustment value is used in PSM credit update flow, indicated by 2135 * Bit 5-6. 2136 * - Bit 7 is reserved. 2137 * Without setting the generic section as valid in valid_sections, the 2138 * Admin Q command will fail with error code ICE_AQ_RC_EINVAL. 2139 */ 2140 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 2141 2142 /* add the lan q */ 2143 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 2144 if (status) 2145 goto ena_txq_exit; 2146 2147 node.node_teid = buf->txqs[0].q_teid; 2148 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 2149 2150 /* add a leaf node into schduler tree q layer */ 2151 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 2152 2153 ena_txq_exit: 2154 mutex_unlock(&pi->sched_lock); 2155 return status; 2156 } 2157 2158 /** 2159 * ice_dis_vsi_txq 2160 * @pi: port information structure 2161 * @num_queues: number of queues 2162 * @q_ids: pointer to the q_id array 2163 * @q_teids: pointer to queue node teids 2164 * @cd: pointer to command details structure or NULL 2165 * 2166 * This function removes queues and their corresponding nodes in SW DB 2167 */ 2168 enum ice_status 2169 ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids, 2170 u32 *q_teids, struct ice_sq_cd *cd) 2171 { 2172 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 2173 struct ice_aqc_dis_txq_item qg_list; 2174 u16 i; 2175 2176 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2177 return ICE_ERR_CFG; 2178 2179 mutex_lock(&pi->sched_lock); 2180 2181 for (i = 0; i < num_queues; i++) { 2182 struct ice_sched_node *node; 2183 2184 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 2185 if (!node) 2186 continue; 2187 qg_list.parent_teid = node->info.parent_teid; 2188 qg_list.num_qs = 1; 2189 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 2190 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 2191 sizeof(qg_list), cd); 2192 2193 if (status) 2194 break; 2195 ice_free_sched_node(pi, node); 2196 } 2197 mutex_unlock(&pi->sched_lock); 2198 return status; 2199 } 2200 2201 /** 2202 * ice_cfg_vsi_qs - configure the new/exisiting VSI queues 2203 * @pi: port information structure 2204 * @vsi_id: VSI Id 2205 * @tc_bitmap: TC bitmap 2206 * @maxqs: max queues array per TC 2207 * @owner: lan or rdma 2208 * 2209 * This function adds/updates the VSI queues per TC. 2210 */ 2211 static enum ice_status 2212 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, 2213 u16 *maxqs, u8 owner) 2214 { 2215 enum ice_status status = 0; 2216 u8 i; 2217 2218 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2219 return ICE_ERR_CFG; 2220 2221 mutex_lock(&pi->sched_lock); 2222 2223 for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) { 2224 /* configuration is possible only if TC node is present */ 2225 if (!ice_sched_get_tc_node(pi, i)) 2226 continue; 2227 2228 status = ice_sched_cfg_vsi(pi, vsi_id, i, maxqs[i], owner, 2229 ice_is_tc_ena(tc_bitmap, i)); 2230 if (status) 2231 break; 2232 } 2233 2234 mutex_unlock(&pi->sched_lock); 2235 return status; 2236 } 2237 2238 /** 2239 * ice_cfg_vsi_lan - configure VSI lan queues 2240 * @pi: port information structure 2241 * @vsi_id: VSI Id 2242 * @tc_bitmap: TC bitmap 2243 * @max_lanqs: max lan queues array per TC 2244 * 2245 * This function adds/updates the VSI lan queues per TC. 2246 */ 2247 enum ice_status 2248 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, 2249 u16 *max_lanqs) 2250 { 2251 return ice_cfg_vsi_qs(pi, vsi_id, tc_bitmap, max_lanqs, 2252 ICE_SCHED_NODE_OWNER_LAN); 2253 } 2254