1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473 } 474 475 /** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496 { 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520 } 521 522 /** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529 static bool ice_is_media_cage_present(struct ice_port_info *pi) 530 { 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538 } 539 540 /** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545 { 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655 } 656 657 /** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665 { 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673 } 674 675 /** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684 int 685 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687 { 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775 } 776 777 /** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785 static void 786 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788 { 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824 } 825 826 /** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834 int 835 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 { 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852 } 853 854 /** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859 { 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882 } 883 884 /** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889 { 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932 } 933 934 /** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942 { 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958 } 959 960 /** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968 { 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985 } 986 987 /** 988 * ice_init_hw - main hardware initialization routine 989 * @hw: pointer to the hardware structure 990 */ 991 int ice_init_hw(struct ice_hw *hw) 992 { 993 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 994 void *mac_buf __free(kfree) = NULL; 995 u16 mac_buf_len; 996 int status; 997 998 /* Set MAC type based on DeviceID */ 999 status = ice_set_mac_type(hw); 1000 if (status) 1001 return status; 1002 1003 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1004 1005 status = ice_reset(hw, ICE_RESET_PFR); 1006 if (status) 1007 return status; 1008 1009 ice_get_itr_intrl_gran(hw); 1010 1011 status = ice_create_all_ctrlq(hw); 1012 if (status) 1013 goto err_unroll_cqinit; 1014 1015 status = ice_fwlog_init(hw); 1016 if (status) 1017 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1018 status); 1019 1020 status = ice_clear_pf_cfg(hw); 1021 if (status) 1022 goto err_unroll_cqinit; 1023 1024 /* Set bit to enable Flow Director filters */ 1025 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1026 INIT_LIST_HEAD(&hw->fdir_list_head); 1027 1028 ice_clear_pxe_mode(hw); 1029 1030 status = ice_init_nvm(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 status = ice_get_caps(hw); 1035 if (status) 1036 goto err_unroll_cqinit; 1037 1038 if (!hw->port_info) 1039 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1040 sizeof(*hw->port_info), 1041 GFP_KERNEL); 1042 if (!hw->port_info) { 1043 status = -ENOMEM; 1044 goto err_unroll_cqinit; 1045 } 1046 1047 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1048 /* set the back pointer to HW */ 1049 hw->port_info->hw = hw; 1050 1051 /* Initialize port_info struct with switch configuration data */ 1052 status = ice_get_initial_sw_cfg(hw); 1053 if (status) 1054 goto err_unroll_alloc; 1055 1056 hw->evb_veb = true; 1057 1058 /* init xarray for identifying scheduling nodes uniquely */ 1059 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1060 1061 /* Query the allocated resources for Tx scheduler */ 1062 status = ice_sched_query_res_alloc(hw); 1063 if (status) { 1064 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1065 goto err_unroll_alloc; 1066 } 1067 ice_sched_get_psm_clk_freq(hw); 1068 1069 /* Initialize port_info struct with scheduler data */ 1070 status = ice_sched_init_port(hw->port_info); 1071 if (status) 1072 goto err_unroll_sched; 1073 1074 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1075 if (!pcaps) { 1076 status = -ENOMEM; 1077 goto err_unroll_sched; 1078 } 1079 1080 /* Initialize port_info struct with PHY capabilities */ 1081 status = ice_aq_get_phy_caps(hw->port_info, false, 1082 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1083 NULL); 1084 if (status) 1085 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1086 status); 1087 1088 /* Initialize port_info struct with link information */ 1089 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1090 if (status) 1091 goto err_unroll_sched; 1092 1093 /* need a valid SW entry point to build a Tx tree */ 1094 if (!hw->sw_entry_point_layer) { 1095 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1096 status = -EIO; 1097 goto err_unroll_sched; 1098 } 1099 INIT_LIST_HEAD(&hw->agg_list); 1100 /* Initialize max burst size */ 1101 if (!hw->max_burst_size) 1102 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1103 1104 status = ice_init_fltr_mgmt_struct(hw); 1105 if (status) 1106 goto err_unroll_sched; 1107 1108 /* Get MAC information */ 1109 /* A single port can report up to two (LAN and WoL) addresses */ 1110 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1111 GFP_KERNEL); 1112 if (!mac_buf) { 1113 status = -ENOMEM; 1114 goto err_unroll_fltr_mgmt_struct; 1115 } 1116 1117 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1118 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1119 1120 if (status) 1121 goto err_unroll_fltr_mgmt_struct; 1122 /* enable jumbo frame support at MAC level */ 1123 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1124 if (status) 1125 goto err_unroll_fltr_mgmt_struct; 1126 /* Obtain counter base index which would be used by flow director */ 1127 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1128 if (status) 1129 goto err_unroll_fltr_mgmt_struct; 1130 status = ice_init_hw_tbls(hw); 1131 if (status) 1132 goto err_unroll_fltr_mgmt_struct; 1133 mutex_init(&hw->tnl_lock); 1134 ice_init_chk_recipe_reuse_support(hw); 1135 1136 /* Some cards require longer initialization times 1137 * due to necessity of loading FW from an external source. 1138 * This can take even half a minute. 1139 */ 1140 if (ice_is_pf_c827(hw)) { 1141 status = ice_wait_for_fw(hw, 30000); 1142 if (status) { 1143 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1144 goto err_unroll_fltr_mgmt_struct; 1145 } 1146 } 1147 1148 hw->lane_num = ice_get_phy_lane_number(hw); 1149 1150 return 0; 1151 err_unroll_fltr_mgmt_struct: 1152 ice_cleanup_fltr_mgmt_struct(hw); 1153 err_unroll_sched: 1154 ice_sched_cleanup_all(hw); 1155 err_unroll_alloc: 1156 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1157 err_unroll_cqinit: 1158 ice_destroy_all_ctrlq(hw); 1159 return status; 1160 } 1161 1162 /** 1163 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1164 * @hw: pointer to the hardware structure 1165 * 1166 * This should be called only during nominal operation, not as a result of 1167 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1168 * applicable initializations if it fails for any reason. 1169 */ 1170 void ice_deinit_hw(struct ice_hw *hw) 1171 { 1172 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1173 ice_cleanup_fltr_mgmt_struct(hw); 1174 1175 ice_sched_cleanup_all(hw); 1176 ice_sched_clear_agg(hw); 1177 ice_free_seg(hw); 1178 ice_free_hw_tbls(hw); 1179 mutex_destroy(&hw->tnl_lock); 1180 1181 ice_fwlog_deinit(hw); 1182 ice_destroy_all_ctrlq(hw); 1183 1184 /* Clear VSI contexts if not already cleared */ 1185 ice_clear_all_vsi_ctx(hw); 1186 } 1187 1188 /** 1189 * ice_check_reset - Check to see if a global reset is complete 1190 * @hw: pointer to the hardware structure 1191 */ 1192 int ice_check_reset(struct ice_hw *hw) 1193 { 1194 u32 cnt, reg = 0, grst_timeout, uld_mask; 1195 1196 /* Poll for Device Active state in case a recent CORER, GLOBR, 1197 * or EMPR has occurred. The grst delay value is in 100ms units. 1198 * Add 1sec for outstanding AQ commands that can take a long time. 1199 */ 1200 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1201 rd32(hw, GLGEN_RSTCTL)) + 10; 1202 1203 for (cnt = 0; cnt < grst_timeout; cnt++) { 1204 mdelay(100); 1205 reg = rd32(hw, GLGEN_RSTAT); 1206 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1207 break; 1208 } 1209 1210 if (cnt == grst_timeout) { 1211 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1212 return -EIO; 1213 } 1214 1215 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1216 GLNVM_ULD_PCIER_DONE_1_M |\ 1217 GLNVM_ULD_CORER_DONE_M |\ 1218 GLNVM_ULD_GLOBR_DONE_M |\ 1219 GLNVM_ULD_POR_DONE_M |\ 1220 GLNVM_ULD_POR_DONE_1_M |\ 1221 GLNVM_ULD_PCIER_DONE_2_M) 1222 1223 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1224 GLNVM_ULD_PE_DONE_M : 0); 1225 1226 /* Device is Active; check Global Reset processes are done */ 1227 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1228 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1229 if (reg == uld_mask) { 1230 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1231 break; 1232 } 1233 mdelay(10); 1234 } 1235 1236 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1237 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1238 reg); 1239 return -EIO; 1240 } 1241 1242 return 0; 1243 } 1244 1245 /** 1246 * ice_pf_reset - Reset the PF 1247 * @hw: pointer to the hardware structure 1248 * 1249 * If a global reset has been triggered, this function checks 1250 * for its completion and then issues the PF reset 1251 */ 1252 static int ice_pf_reset(struct ice_hw *hw) 1253 { 1254 u32 cnt, reg; 1255 1256 /* If at function entry a global reset was already in progress, i.e. 1257 * state is not 'device active' or any of the reset done bits are not 1258 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1259 * global reset is done. 1260 */ 1261 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1262 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1263 /* poll on global reset currently in progress until done */ 1264 if (ice_check_reset(hw)) 1265 return -EIO; 1266 1267 return 0; 1268 } 1269 1270 /* Reset the PF */ 1271 reg = rd32(hw, PFGEN_CTRL); 1272 1273 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1274 1275 /* Wait for the PFR to complete. The wait time is the global config lock 1276 * timeout plus the PFR timeout which will account for a possible reset 1277 * that is occurring during a download package operation. 1278 */ 1279 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1280 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1281 reg = rd32(hw, PFGEN_CTRL); 1282 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1283 break; 1284 1285 mdelay(1); 1286 } 1287 1288 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1289 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1290 return -EIO; 1291 } 1292 1293 return 0; 1294 } 1295 1296 /** 1297 * ice_reset - Perform different types of reset 1298 * @hw: pointer to the hardware structure 1299 * @req: reset request 1300 * 1301 * This function triggers a reset as specified by the req parameter. 1302 * 1303 * Note: 1304 * If anything other than a PF reset is triggered, PXE mode is restored. 1305 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1306 * interface has been restored in the rebuild flow. 1307 */ 1308 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1309 { 1310 u32 val = 0; 1311 1312 switch (req) { 1313 case ICE_RESET_PFR: 1314 return ice_pf_reset(hw); 1315 case ICE_RESET_CORER: 1316 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1317 val = GLGEN_RTRIG_CORER_M; 1318 break; 1319 case ICE_RESET_GLOBR: 1320 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1321 val = GLGEN_RTRIG_GLOBR_M; 1322 break; 1323 default: 1324 return -EINVAL; 1325 } 1326 1327 val |= rd32(hw, GLGEN_RTRIG); 1328 wr32(hw, GLGEN_RTRIG, val); 1329 ice_flush(hw); 1330 1331 /* wait for the FW to be ready */ 1332 return ice_check_reset(hw); 1333 } 1334 1335 /** 1336 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1337 * @hw: pointer to the hardware structure 1338 * @rxq_ctx: pointer to the packed Rx queue context 1339 * @rxq_index: the index of the Rx queue 1340 */ 1341 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1342 const ice_rxq_ctx_buf_t *rxq_ctx, 1343 u32 rxq_index) 1344 { 1345 /* Copy each dword separately to HW */ 1346 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1347 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1348 1349 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1350 1351 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1352 } 1353 } 1354 1355 /** 1356 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1357 * @hw: pointer to the hardware structure 1358 * @rxq_ctx: pointer to the packed Rx queue context 1359 * @rxq_index: the index of the Rx queue 1360 */ 1361 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1362 ice_rxq_ctx_buf_t *rxq_ctx, 1363 u32 rxq_index) 1364 { 1365 u32 *ctx = (u32 *)rxq_ctx; 1366 1367 /* Copy each dword separately from HW */ 1368 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1369 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1370 1371 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1372 } 1373 } 1374 1375 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1376 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1377 1378 /* LAN Rx Queue Context */ 1379 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1380 /* Field Width LSB */ 1381 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1382 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1383 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1384 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1385 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1386 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1387 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1388 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1389 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1390 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1391 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1392 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1393 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1394 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1395 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1396 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1397 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1398 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1399 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1400 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1401 }; 1402 1403 /** 1404 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1405 * @ctx: the Rx queue context to pack 1406 * @buf: the HW buffer to pack into 1407 * 1408 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1409 * bit-packed HW layout. 1410 */ 1411 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1412 ice_rxq_ctx_buf_t *buf) 1413 { 1414 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1415 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1416 } 1417 1418 /** 1419 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1420 * @buf: the HW buffer to unpack from 1421 * @ctx: the Rx queue context to unpack 1422 * 1423 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1424 * structure. 1425 */ 1426 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1427 struct ice_rlan_ctx *ctx) 1428 { 1429 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1430 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1431 } 1432 1433 /** 1434 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1435 * @hw: pointer to the hardware structure 1436 * @rlan_ctx: pointer to the unpacked Rx queue context 1437 * @rxq_index: the index of the Rx queue 1438 * 1439 * Pack the sparse Rx Queue context into dense hardware format and write it 1440 * into the HW register space. 1441 * 1442 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1443 */ 1444 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1445 u32 rxq_index) 1446 { 1447 ice_rxq_ctx_buf_t buf = {}; 1448 1449 if (rxq_index > QRX_CTRL_MAX_INDEX) 1450 return -EINVAL; 1451 1452 ice_pack_rxq_ctx(rlan_ctx, &buf); 1453 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1454 1455 return 0; 1456 } 1457 1458 /** 1459 * ice_read_rxq_ctx - Read Rx queue context from HW 1460 * @hw: pointer to the hardware structure 1461 * @rlan_ctx: pointer to the Rx queue context 1462 * @rxq_index: the index of the Rx queue 1463 * 1464 * Read the Rx queue context from the hardware registers, and unpack it into 1465 * the sparse Rx queue context structure. 1466 * 1467 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1468 */ 1469 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1470 u32 rxq_index) 1471 { 1472 ice_rxq_ctx_buf_t buf = {}; 1473 1474 if (rxq_index > QRX_CTRL_MAX_INDEX) 1475 return -EINVAL; 1476 1477 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1478 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1479 1480 return 0; 1481 } 1482 1483 /* LAN Tx Queue Context */ 1484 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1485 /* Field Width LSB */ 1486 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1487 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1488 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1489 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1490 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1491 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1492 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1493 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1494 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1495 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1496 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1497 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1498 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1499 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1500 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1501 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1502 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1503 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1504 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1505 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1506 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1507 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1508 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1509 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1510 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1511 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1512 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1513 }; 1514 1515 /** 1516 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1517 * @ctx: the Tx queue context to pack 1518 * @buf: the Admin Queue HW buffer to pack into 1519 * 1520 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1521 * bit-packed Admin Queue layout. 1522 */ 1523 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1524 { 1525 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1526 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1527 } 1528 1529 /** 1530 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1531 * @ctx: the Tx queue context to pack 1532 * @buf: the HW buffer to pack into 1533 * 1534 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1535 * bit-packed HW layout, including the internal data portion. 1536 */ 1537 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1538 ice_txq_ctx_buf_full_t *buf) 1539 { 1540 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1541 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1542 } 1543 1544 /** 1545 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1546 * @buf: the HW buffer to unpack from 1547 * @ctx: the Tx queue context to unpack 1548 * 1549 * Unpack the Tx queue context from the HW buffer (including the full internal 1550 * state) into the CPU-friendly structure. 1551 */ 1552 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1553 struct ice_tlan_ctx *ctx) 1554 { 1555 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1556 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1557 } 1558 1559 /** 1560 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1561 * @hw: pointer to the hardware structure 1562 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1563 * @txq_index: the index of the Tx queue 1564 * 1565 * Copy Tx Queue context from HW register space to dense structure 1566 */ 1567 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1568 ice_txq_ctx_buf_full_t *txq_ctx, 1569 u32 txq_index) 1570 { 1571 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1572 u32 *ctx = (u32 *)txq_ctx; 1573 u32 txq_base, reg; 1574 1575 /* Get Tx queue base within card space */ 1576 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1577 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1578 1579 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1580 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1581 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1582 txq_base + txq_index) | 1583 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1584 1585 /* Prevent other PFs on the same adapter from accessing the Tx queue 1586 * context interface concurrently. 1587 */ 1588 spin_lock(&pf->adapter->txq_ctx_lock); 1589 1590 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1591 ice_flush(hw); 1592 1593 /* Copy each dword separately from HW */ 1594 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1595 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1596 1597 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1598 } 1599 1600 spin_unlock(&pf->adapter->txq_ctx_lock); 1601 } 1602 1603 /** 1604 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1605 * @hw: pointer to the hardware structure 1606 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1607 * @txq_index: the index of the Tx queue 1608 */ 1609 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1610 const ice_txq_ctx_buf_full_t *txq_ctx, 1611 u32 txq_index) 1612 { 1613 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1614 u32 txq_base, reg; 1615 1616 /* Get Tx queue base within card space */ 1617 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1618 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1619 1620 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1621 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1622 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1623 txq_base + txq_index) | 1624 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1625 1626 /* Prevent other PFs on the same adapter from accessing the Tx queue 1627 * context interface concurrently. 1628 */ 1629 spin_lock(&pf->adapter->txq_ctx_lock); 1630 1631 /* Copy each dword separately to HW */ 1632 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1633 u32 ctx = ((const u32 *)txq_ctx)[i]; 1634 1635 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1636 1637 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1638 } 1639 1640 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1641 ice_flush(hw); 1642 1643 spin_unlock(&pf->adapter->txq_ctx_lock); 1644 } 1645 1646 /** 1647 * ice_read_txq_ctx - Read Tx queue context from HW 1648 * @hw: pointer to the hardware structure 1649 * @tlan_ctx: pointer to the Tx queue context 1650 * @txq_index: the index of the Tx queue 1651 * 1652 * Read the Tx queue context from the HW registers, then unpack it into the 1653 * ice_tlan_ctx structure for use. 1654 * 1655 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1656 */ 1657 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1658 u32 txq_index) 1659 { 1660 ice_txq_ctx_buf_full_t buf = {}; 1661 1662 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1663 return -EINVAL; 1664 1665 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1666 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1667 1668 return 0; 1669 } 1670 1671 /** 1672 * ice_write_txq_ctx - Write Tx queue context to HW 1673 * @hw: pointer to the hardware structure 1674 * @tlan_ctx: pointer to the Tx queue context 1675 * @txq_index: the index of the Tx queue 1676 * 1677 * Pack the Tx queue context into the dense HW layout, then write it into the 1678 * HW registers. 1679 * 1680 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1681 */ 1682 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1683 u32 txq_index) 1684 { 1685 ice_txq_ctx_buf_full_t buf = {}; 1686 1687 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1688 return -EINVAL; 1689 1690 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1691 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1692 1693 return 0; 1694 } 1695 1696 /* Sideband Queue command wrappers */ 1697 1698 /** 1699 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1700 * @hw: pointer to the HW struct 1701 * @desc: descriptor describing the command 1702 * @buf: buffer to use for indirect commands (NULL for direct commands) 1703 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1704 * @cd: pointer to command details structure 1705 */ 1706 static int 1707 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1708 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1709 { 1710 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1711 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1712 } 1713 1714 /** 1715 * ice_sbq_rw_reg - Fill Sideband Queue command 1716 * @hw: pointer to the HW struct 1717 * @in: message info to be filled in descriptor 1718 * @flags: control queue descriptor flags 1719 */ 1720 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1721 { 1722 struct ice_sbq_cmd_desc desc = {0}; 1723 struct ice_sbq_msg_req msg = {0}; 1724 u16 msg_len; 1725 int status; 1726 1727 msg_len = sizeof(msg); 1728 1729 msg.dest_dev = in->dest_dev; 1730 msg.opcode = in->opcode; 1731 msg.flags = ICE_SBQ_MSG_FLAGS; 1732 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1733 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1734 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1735 1736 if (in->opcode) 1737 msg.data = cpu_to_le32(in->data); 1738 else 1739 /* data read comes back in completion, so shorten the struct by 1740 * sizeof(msg.data) 1741 */ 1742 msg_len -= sizeof(msg.data); 1743 1744 desc.flags = cpu_to_le16(flags); 1745 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1746 desc.param0.cmd_len = cpu_to_le16(msg_len); 1747 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1748 if (!status && !in->opcode) 1749 in->data = le32_to_cpu 1750 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1751 return status; 1752 } 1753 1754 /* FW Admin Queue command wrappers */ 1755 1756 /* Software lock/mutex that is meant to be held while the Global Config Lock 1757 * in firmware is acquired by the software to prevent most (but not all) types 1758 * of AQ commands from being sent to FW 1759 */ 1760 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1761 1762 /** 1763 * ice_should_retry_sq_send_cmd 1764 * @opcode: AQ opcode 1765 * 1766 * Decide if we should retry the send command routine for the ATQ, depending 1767 * on the opcode. 1768 */ 1769 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1770 { 1771 switch (opcode) { 1772 case ice_aqc_opc_get_link_topo: 1773 case ice_aqc_opc_lldp_stop: 1774 case ice_aqc_opc_lldp_start: 1775 case ice_aqc_opc_lldp_filter_ctrl: 1776 return true; 1777 } 1778 1779 return false; 1780 } 1781 1782 /** 1783 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1784 * @hw: pointer to the HW struct 1785 * @cq: pointer to the specific Control queue 1786 * @desc: prefilled descriptor describing the command 1787 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1788 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1789 * @cd: pointer to command details structure 1790 * 1791 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1792 * Queue if the EBUSY AQ error is returned. 1793 */ 1794 static int 1795 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1796 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1797 struct ice_sq_cd *cd) 1798 { 1799 struct libie_aq_desc desc_cpy; 1800 bool is_cmd_for_retry; 1801 u8 idx = 0; 1802 u16 opcode; 1803 int status; 1804 1805 opcode = le16_to_cpu(desc->opcode); 1806 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1807 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1808 1809 if (is_cmd_for_retry) { 1810 /* All retryable cmds are direct, without buf. */ 1811 WARN_ON(buf); 1812 1813 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1814 } 1815 1816 do { 1817 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1818 1819 if (!is_cmd_for_retry || !status || 1820 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1821 break; 1822 1823 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1824 1825 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1826 1827 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1828 1829 return status; 1830 } 1831 1832 /** 1833 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1834 * @hw: pointer to the HW struct 1835 * @desc: descriptor describing the command 1836 * @buf: buffer to use for indirect commands (NULL for direct commands) 1837 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1838 * @cd: pointer to command details structure 1839 * 1840 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1841 */ 1842 int 1843 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1844 u16 buf_size, struct ice_sq_cd *cd) 1845 { 1846 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1847 bool lock_acquired = false; 1848 int status; 1849 1850 /* When a package download is in process (i.e. when the firmware's 1851 * Global Configuration Lock resource is held), only the Download 1852 * Package, Get Version, Get Package Info List, Upload Section, 1853 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1854 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1855 * Recipes to Profile Association, and Release Resource (with resource 1856 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1857 * must block until the package download completes and the Global Config 1858 * Lock is released. See also ice_acquire_global_cfg_lock(). 1859 */ 1860 switch (le16_to_cpu(desc->opcode)) { 1861 case ice_aqc_opc_download_pkg: 1862 case ice_aqc_opc_get_pkg_info_list: 1863 case ice_aqc_opc_get_ver: 1864 case ice_aqc_opc_upload_section: 1865 case ice_aqc_opc_update_pkg: 1866 case ice_aqc_opc_set_port_params: 1867 case ice_aqc_opc_get_vlan_mode_parameters: 1868 case ice_aqc_opc_set_vlan_mode_parameters: 1869 case ice_aqc_opc_set_tx_topo: 1870 case ice_aqc_opc_get_tx_topo: 1871 case ice_aqc_opc_add_recipe: 1872 case ice_aqc_opc_recipe_to_profile: 1873 case ice_aqc_opc_get_recipe: 1874 case ice_aqc_opc_get_recipe_to_profile: 1875 break; 1876 case ice_aqc_opc_release_res: 1877 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1878 break; 1879 fallthrough; 1880 default: 1881 mutex_lock(&ice_global_cfg_lock_sw); 1882 lock_acquired = true; 1883 break; 1884 } 1885 1886 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1887 if (lock_acquired) 1888 mutex_unlock(&ice_global_cfg_lock_sw); 1889 1890 return status; 1891 } 1892 1893 /** 1894 * ice_aq_get_fw_ver 1895 * @hw: pointer to the HW struct 1896 * @cd: pointer to command details structure or NULL 1897 * 1898 * Get the firmware version (0x0001) from the admin queue commands 1899 */ 1900 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1901 { 1902 struct libie_aqc_get_ver *resp; 1903 struct libie_aq_desc desc; 1904 int status; 1905 1906 resp = &desc.params.get_ver; 1907 1908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1909 1910 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1911 1912 if (!status) { 1913 hw->fw_branch = resp->fw_branch; 1914 hw->fw_maj_ver = resp->fw_major; 1915 hw->fw_min_ver = resp->fw_minor; 1916 hw->fw_patch = resp->fw_patch; 1917 hw->fw_build = le32_to_cpu(resp->fw_build); 1918 hw->api_branch = resp->api_branch; 1919 hw->api_maj_ver = resp->api_major; 1920 hw->api_min_ver = resp->api_minor; 1921 hw->api_patch = resp->api_patch; 1922 } 1923 1924 return status; 1925 } 1926 1927 /** 1928 * ice_aq_send_driver_ver 1929 * @hw: pointer to the HW struct 1930 * @dv: driver's major, minor version 1931 * @cd: pointer to command details structure or NULL 1932 * 1933 * Send the driver version (0x0002) to the firmware 1934 */ 1935 int 1936 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1937 struct ice_sq_cd *cd) 1938 { 1939 struct libie_aqc_driver_ver *cmd; 1940 struct libie_aq_desc desc; 1941 u16 len; 1942 1943 cmd = &desc.params.driver_ver; 1944 1945 if (!dv) 1946 return -EINVAL; 1947 1948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1949 1950 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1951 cmd->major_ver = dv->major_ver; 1952 cmd->minor_ver = dv->minor_ver; 1953 cmd->build_ver = dv->build_ver; 1954 cmd->subbuild_ver = dv->subbuild_ver; 1955 1956 len = 0; 1957 while (len < sizeof(dv->driver_string) && 1958 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1959 len++; 1960 1961 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1962 } 1963 1964 /** 1965 * ice_aq_q_shutdown 1966 * @hw: pointer to the HW struct 1967 * @unloading: is the driver unloading itself 1968 * 1969 * Tell the Firmware that we're shutting down the AdminQ and whether 1970 * or not the driver is unloading as well (0x0003). 1971 */ 1972 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1973 { 1974 struct ice_aqc_q_shutdown *cmd; 1975 struct libie_aq_desc desc; 1976 1977 cmd = libie_aq_raw(&desc); 1978 1979 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1980 1981 if (unloading) 1982 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1983 1984 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1985 } 1986 1987 /** 1988 * ice_aq_req_res 1989 * @hw: pointer to the HW struct 1990 * @res: resource ID 1991 * @access: access type 1992 * @sdp_number: resource number 1993 * @timeout: the maximum time in ms that the driver may hold the resource 1994 * @cd: pointer to command details structure or NULL 1995 * 1996 * Requests common resource using the admin queue commands (0x0008). 1997 * When attempting to acquire the Global Config Lock, the driver can 1998 * learn of three states: 1999 * 1) 0 - acquired lock, and can perform download package 2000 * 2) -EIO - did not get lock, driver should fail to load 2001 * 3) -EALREADY - did not get lock, but another driver has 2002 * successfully downloaded the package; the driver does 2003 * not have to download the package and can continue 2004 * loading 2005 * 2006 * Note that if the caller is in an acquire lock, perform action, release lock 2007 * phase of operation, it is possible that the FW may detect a timeout and issue 2008 * a CORER. In this case, the driver will receive a CORER interrupt and will 2009 * have to determine its cause. The calling thread that is handling this flow 2010 * will likely get an error propagated back to it indicating the Download 2011 * Package, Update Package or the Release Resource AQ commands timed out. 2012 */ 2013 static int 2014 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2015 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2016 struct ice_sq_cd *cd) 2017 { 2018 struct libie_aqc_req_res *cmd_resp; 2019 struct libie_aq_desc desc; 2020 int status; 2021 2022 cmd_resp = &desc.params.res_owner; 2023 2024 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2025 2026 cmd_resp->res_id = cpu_to_le16(res); 2027 cmd_resp->access_type = cpu_to_le16(access); 2028 cmd_resp->res_number = cpu_to_le32(sdp_number); 2029 cmd_resp->timeout = cpu_to_le32(*timeout); 2030 *timeout = 0; 2031 2032 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2033 2034 /* The completion specifies the maximum time in ms that the driver 2035 * may hold the resource in the Timeout field. 2036 */ 2037 2038 /* Global config lock response utilizes an additional status field. 2039 * 2040 * If the Global config lock resource is held by some other driver, the 2041 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2042 * and the timeout field indicates the maximum time the current owner 2043 * of the resource has to free it. 2044 */ 2045 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2046 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2047 *timeout = le32_to_cpu(cmd_resp->timeout); 2048 return 0; 2049 } else if (le16_to_cpu(cmd_resp->status) == 2050 LIBIE_AQ_RES_GLBL_IN_PROG) { 2051 *timeout = le32_to_cpu(cmd_resp->timeout); 2052 return -EIO; 2053 } else if (le16_to_cpu(cmd_resp->status) == 2054 LIBIE_AQ_RES_GLBL_DONE) { 2055 return -EALREADY; 2056 } 2057 2058 /* invalid FW response, force a timeout immediately */ 2059 *timeout = 0; 2060 return -EIO; 2061 } 2062 2063 /* If the resource is held by some other driver, the command completes 2064 * with a busy return value and the timeout field indicates the maximum 2065 * time the current owner of the resource has to free it. 2066 */ 2067 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2068 *timeout = le32_to_cpu(cmd_resp->timeout); 2069 2070 return status; 2071 } 2072 2073 /** 2074 * ice_aq_release_res 2075 * @hw: pointer to the HW struct 2076 * @res: resource ID 2077 * @sdp_number: resource number 2078 * @cd: pointer to command details structure or NULL 2079 * 2080 * release common resource using the admin queue commands (0x0009) 2081 */ 2082 static int 2083 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2084 struct ice_sq_cd *cd) 2085 { 2086 struct libie_aqc_req_res *cmd; 2087 struct libie_aq_desc desc; 2088 2089 cmd = &desc.params.res_owner; 2090 2091 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2092 2093 cmd->res_id = cpu_to_le16(res); 2094 cmd->res_number = cpu_to_le32(sdp_number); 2095 2096 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2097 } 2098 2099 /** 2100 * ice_acquire_res 2101 * @hw: pointer to the HW structure 2102 * @res: resource ID 2103 * @access: access type (read or write) 2104 * @timeout: timeout in milliseconds 2105 * 2106 * This function will attempt to acquire the ownership of a resource. 2107 */ 2108 int 2109 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2110 enum ice_aq_res_access_type access, u32 timeout) 2111 { 2112 #define ICE_RES_POLLING_DELAY_MS 10 2113 u32 delay = ICE_RES_POLLING_DELAY_MS; 2114 u32 time_left = timeout; 2115 int status; 2116 2117 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2118 2119 /* A return code of -EALREADY means that another driver has 2120 * previously acquired the resource and performed any necessary updates; 2121 * in this case the caller does not obtain the resource and has no 2122 * further work to do. 2123 */ 2124 if (status == -EALREADY) 2125 goto ice_acquire_res_exit; 2126 2127 if (status) 2128 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2129 2130 /* If necessary, poll until the current lock owner timeouts */ 2131 timeout = time_left; 2132 while (status && timeout && time_left) { 2133 mdelay(delay); 2134 timeout = (timeout > delay) ? timeout - delay : 0; 2135 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2136 2137 if (status == -EALREADY) 2138 /* lock free, but no work to do */ 2139 break; 2140 2141 if (!status) 2142 /* lock acquired */ 2143 break; 2144 } 2145 if (status && status != -EALREADY) 2146 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2147 2148 ice_acquire_res_exit: 2149 if (status == -EALREADY) { 2150 if (access == ICE_RES_WRITE) 2151 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2152 else 2153 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2154 } 2155 return status; 2156 } 2157 2158 /** 2159 * ice_release_res 2160 * @hw: pointer to the HW structure 2161 * @res: resource ID 2162 * 2163 * This function will release a resource using the proper Admin Command. 2164 */ 2165 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2166 { 2167 unsigned long timeout; 2168 int status; 2169 2170 /* there are some rare cases when trying to release the resource 2171 * results in an admin queue timeout, so handle them correctly 2172 */ 2173 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2174 do { 2175 status = ice_aq_release_res(hw, res, 0, NULL); 2176 if (status != -EIO) 2177 break; 2178 usleep_range(1000, 2000); 2179 } while (time_before(jiffies, timeout)); 2180 } 2181 2182 /** 2183 * ice_aq_alloc_free_res - command to allocate/free resources 2184 * @hw: pointer to the HW struct 2185 * @buf: Indirect buffer to hold data parameters and response 2186 * @buf_size: size of buffer for indirect commands 2187 * @opc: pass in the command opcode 2188 * 2189 * Helper function to allocate/free resources using the admin queue commands 2190 */ 2191 int ice_aq_alloc_free_res(struct ice_hw *hw, 2192 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2193 enum ice_adminq_opc opc) 2194 { 2195 struct ice_aqc_alloc_free_res_cmd *cmd; 2196 struct libie_aq_desc desc; 2197 2198 cmd = libie_aq_raw(&desc); 2199 2200 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2201 return -EINVAL; 2202 2203 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2204 2205 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2206 2207 cmd->num_entries = cpu_to_le16(1); 2208 2209 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2210 } 2211 2212 /** 2213 * ice_alloc_hw_res - allocate resource 2214 * @hw: pointer to the HW struct 2215 * @type: type of resource 2216 * @num: number of resources to allocate 2217 * @btm: allocate from bottom 2218 * @res: pointer to array that will receive the resources 2219 */ 2220 int 2221 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2222 { 2223 struct ice_aqc_alloc_free_res_elem *buf; 2224 u16 buf_len; 2225 int status; 2226 2227 buf_len = struct_size(buf, elem, num); 2228 buf = kzalloc(buf_len, GFP_KERNEL); 2229 if (!buf) 2230 return -ENOMEM; 2231 2232 /* Prepare buffer to allocate resource. */ 2233 buf->num_elems = cpu_to_le16(num); 2234 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2235 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2236 if (btm) 2237 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2238 2239 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2240 if (status) 2241 goto ice_alloc_res_exit; 2242 2243 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2244 2245 ice_alloc_res_exit: 2246 kfree(buf); 2247 return status; 2248 } 2249 2250 /** 2251 * ice_free_hw_res - free allocated HW resource 2252 * @hw: pointer to the HW struct 2253 * @type: type of resource to free 2254 * @num: number of resources 2255 * @res: pointer to array that contains the resources to free 2256 */ 2257 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2258 { 2259 struct ice_aqc_alloc_free_res_elem *buf; 2260 u16 buf_len; 2261 int status; 2262 2263 buf_len = struct_size(buf, elem, num); 2264 buf = kzalloc(buf_len, GFP_KERNEL); 2265 if (!buf) 2266 return -ENOMEM; 2267 2268 /* Prepare buffer to free resource. */ 2269 buf->num_elems = cpu_to_le16(num); 2270 buf->res_type = cpu_to_le16(type); 2271 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2272 2273 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2274 if (status) 2275 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2276 2277 kfree(buf); 2278 return status; 2279 } 2280 2281 /** 2282 * ice_get_num_per_func - determine number of resources per PF 2283 * @hw: pointer to the HW structure 2284 * @max: value to be evenly split between each PF 2285 * 2286 * Determine the number of valid functions by going through the bitmap returned 2287 * from parsing capabilities and use this to calculate the number of resources 2288 * per PF based on the max value passed in. 2289 */ 2290 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2291 { 2292 u8 funcs; 2293 2294 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2295 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2296 ICE_CAPS_VALID_FUNCS_M); 2297 2298 if (!funcs) 2299 return 0; 2300 2301 return max / funcs; 2302 } 2303 2304 /** 2305 * ice_parse_common_caps - parse common device/function capabilities 2306 * @hw: pointer to the HW struct 2307 * @caps: pointer to common capabilities structure 2308 * @elem: the capability element to parse 2309 * @prefix: message prefix for tracing capabilities 2310 * 2311 * Given a capability element, extract relevant details into the common 2312 * capability structure. 2313 * 2314 * Returns: true if the capability matches one of the common capability ids, 2315 * false otherwise. 2316 */ 2317 static bool 2318 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2319 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2320 { 2321 u32 logical_id = le32_to_cpu(elem->logical_id); 2322 u32 phys_id = le32_to_cpu(elem->phys_id); 2323 u32 number = le32_to_cpu(elem->number); 2324 u16 cap = le16_to_cpu(elem->cap); 2325 bool found = true; 2326 2327 switch (cap) { 2328 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2329 caps->valid_functions = number; 2330 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2331 caps->valid_functions); 2332 break; 2333 case LIBIE_AQC_CAPS_SRIOV: 2334 caps->sr_iov_1_1 = (number == 1); 2335 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2336 caps->sr_iov_1_1); 2337 break; 2338 case LIBIE_AQC_CAPS_DCB: 2339 caps->dcb = (number == 1); 2340 caps->active_tc_bitmap = logical_id; 2341 caps->maxtc = phys_id; 2342 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2343 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2344 caps->active_tc_bitmap); 2345 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2346 break; 2347 case LIBIE_AQC_CAPS_RSS: 2348 caps->rss_table_size = number; 2349 caps->rss_table_entry_width = logical_id; 2350 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2351 caps->rss_table_size); 2352 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2353 caps->rss_table_entry_width); 2354 break; 2355 case LIBIE_AQC_CAPS_RXQS: 2356 caps->num_rxq = number; 2357 caps->rxq_first_id = phys_id; 2358 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2359 caps->num_rxq); 2360 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2361 caps->rxq_first_id); 2362 break; 2363 case LIBIE_AQC_CAPS_TXQS: 2364 caps->num_txq = number; 2365 caps->txq_first_id = phys_id; 2366 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2367 caps->num_txq); 2368 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2369 caps->txq_first_id); 2370 break; 2371 case LIBIE_AQC_CAPS_MSIX: 2372 caps->num_msix_vectors = number; 2373 caps->msix_vector_first_id = phys_id; 2374 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2375 caps->num_msix_vectors); 2376 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2377 caps->msix_vector_first_id); 2378 break; 2379 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2380 caps->nvm_update_pending_nvm = true; 2381 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2382 break; 2383 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2384 caps->nvm_update_pending_orom = true; 2385 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2386 break; 2387 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2388 caps->nvm_update_pending_netlist = true; 2389 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2390 break; 2391 case LIBIE_AQC_CAPS_NVM_MGMT: 2392 caps->nvm_unified_update = 2393 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2394 true : false; 2395 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2396 caps->nvm_unified_update); 2397 break; 2398 case LIBIE_AQC_CAPS_RDMA: 2399 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2400 caps->rdma = (number == 1); 2401 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2402 break; 2403 case LIBIE_AQC_CAPS_MAX_MTU: 2404 caps->max_mtu = number; 2405 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2406 prefix, caps->max_mtu); 2407 break; 2408 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2409 caps->pcie_reset_avoidance = (number > 0); 2410 ice_debug(hw, ICE_DBG_INIT, 2411 "%s: pcie_reset_avoidance = %d\n", prefix, 2412 caps->pcie_reset_avoidance); 2413 break; 2414 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2415 caps->reset_restrict_support = (number == 1); 2416 ice_debug(hw, ICE_DBG_INIT, 2417 "%s: reset_restrict_support = %d\n", prefix, 2418 caps->reset_restrict_support); 2419 break; 2420 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2421 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2422 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2423 prefix, caps->roce_lag); 2424 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2425 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2426 prefix, caps->sriov_lag); 2427 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2428 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2429 prefix, caps->sriov_aa_lag); 2430 break; 2431 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2432 caps->tx_sched_topo_comp_mode_en = (number == 1); 2433 break; 2434 default: 2435 /* Not one of the recognized common capabilities */ 2436 found = false; 2437 } 2438 2439 return found; 2440 } 2441 2442 /** 2443 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2444 * @hw: pointer to the HW structure 2445 * @caps: pointer to capabilities structure to fix 2446 * 2447 * Re-calculate the capabilities that are dependent on the number of physical 2448 * ports; i.e. some features are not supported or function differently on 2449 * devices with more than 4 ports. 2450 */ 2451 static void 2452 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2453 { 2454 /* This assumes device capabilities are always scanned before function 2455 * capabilities during the initialization flow. 2456 */ 2457 if (hw->dev_caps.num_funcs > 4) { 2458 /* Max 4 TCs per port */ 2459 caps->maxtc = 4; 2460 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2461 caps->maxtc); 2462 if (caps->rdma) { 2463 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2464 caps->rdma = 0; 2465 } 2466 2467 /* print message only when processing device capabilities 2468 * during initialization. 2469 */ 2470 if (caps == &hw->dev_caps.common_cap) 2471 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2472 } 2473 } 2474 2475 /** 2476 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2477 * @hw: pointer to the HW struct 2478 * @func_p: pointer to function capabilities structure 2479 * @cap: pointer to the capability element to parse 2480 * 2481 * Extract function capabilities for ICE_AQC_CAPS_VF. 2482 */ 2483 static void 2484 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2485 struct libie_aqc_list_caps_elem *cap) 2486 { 2487 u32 logical_id = le32_to_cpu(cap->logical_id); 2488 u32 number = le32_to_cpu(cap->number); 2489 2490 func_p->num_allocd_vfs = number; 2491 func_p->vf_base_id = logical_id; 2492 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2493 func_p->num_allocd_vfs); 2494 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2495 func_p->vf_base_id); 2496 } 2497 2498 /** 2499 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2500 * @hw: pointer to the HW struct 2501 * @func_p: pointer to function capabilities structure 2502 * @cap: pointer to the capability element to parse 2503 * 2504 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2505 */ 2506 static void 2507 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2508 struct libie_aqc_list_caps_elem *cap) 2509 { 2510 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2511 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2512 le32_to_cpu(cap->number)); 2513 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2514 func_p->guar_num_vsi); 2515 } 2516 2517 /** 2518 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2519 * @hw: pointer to the HW struct 2520 * @func_p: pointer to function capabilities structure 2521 * @cap: pointer to the capability element to parse 2522 * 2523 * Extract function capabilities for ICE_AQC_CAPS_1588. 2524 */ 2525 static void 2526 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2527 struct libie_aqc_list_caps_elem *cap) 2528 { 2529 struct ice_ts_func_info *info = &func_p->ts_func_info; 2530 u32 number = le32_to_cpu(cap->number); 2531 2532 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2533 func_p->common_cap.ieee_1588 = info->ena; 2534 2535 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2536 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2537 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2538 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2539 2540 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2541 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2542 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2543 } else { 2544 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2545 info->clk_src = ICE_CLK_SRC_TIME_REF; 2546 } 2547 2548 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2549 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2550 } else { 2551 /* Unknown clock frequency, so assume a (probably incorrect) 2552 * default to avoid out-of-bounds look ups of frequency 2553 * related information. 2554 */ 2555 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2556 info->clk_freq); 2557 info->time_ref = ICE_TSPLL_FREQ_25_000; 2558 } 2559 2560 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2561 func_p->common_cap.ieee_1588); 2562 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2563 info->src_tmr_owned); 2564 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2565 info->tmr_ena); 2566 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2567 info->tmr_index_owned); 2568 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2569 info->tmr_index_assoc); 2570 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2571 info->clk_freq); 2572 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2573 info->clk_src); 2574 } 2575 2576 /** 2577 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2578 * @hw: pointer to the HW struct 2579 * @func_p: pointer to function capabilities structure 2580 * 2581 * Extract function capabilities for ICE_AQC_CAPS_FD. 2582 */ 2583 static void 2584 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2585 { 2586 u32 reg_val, gsize, bsize; 2587 2588 reg_val = rd32(hw, GLQF_FD_SIZE); 2589 switch (hw->mac_type) { 2590 case ICE_MAC_E830: 2591 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2592 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2593 break; 2594 case ICE_MAC_E810: 2595 default: 2596 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2597 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2598 } 2599 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2600 func_p->fd_fltr_best_effort = bsize; 2601 2602 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2603 func_p->fd_fltr_guar); 2604 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2605 func_p->fd_fltr_best_effort); 2606 } 2607 2608 /** 2609 * ice_parse_func_caps - Parse function capabilities 2610 * @hw: pointer to the HW struct 2611 * @func_p: pointer to function capabilities structure 2612 * @buf: buffer containing the function capability records 2613 * @cap_count: the number of capabilities 2614 * 2615 * Helper function to parse function (0x000A) capabilities list. For 2616 * capabilities shared between device and function, this relies on 2617 * ice_parse_common_caps. 2618 * 2619 * Loop through the list of provided capabilities and extract the relevant 2620 * data into the function capabilities structured. 2621 */ 2622 static void 2623 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2624 void *buf, u32 cap_count) 2625 { 2626 struct libie_aqc_list_caps_elem *cap_resp; 2627 u32 i; 2628 2629 cap_resp = buf; 2630 2631 memset(func_p, 0, sizeof(*func_p)); 2632 2633 for (i = 0; i < cap_count; i++) { 2634 u16 cap = le16_to_cpu(cap_resp[i].cap); 2635 bool found; 2636 2637 found = ice_parse_common_caps(hw, &func_p->common_cap, 2638 &cap_resp[i], "func caps"); 2639 2640 switch (cap) { 2641 case LIBIE_AQC_CAPS_VF: 2642 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2643 break; 2644 case LIBIE_AQC_CAPS_VSI: 2645 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2646 break; 2647 case LIBIE_AQC_CAPS_1588: 2648 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2649 break; 2650 case LIBIE_AQC_CAPS_FD: 2651 ice_parse_fdir_func_caps(hw, func_p); 2652 break; 2653 default: 2654 /* Don't list common capabilities as unknown */ 2655 if (!found) 2656 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2657 i, cap); 2658 break; 2659 } 2660 } 2661 2662 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2663 } 2664 2665 /** 2666 * ice_func_id_to_logical_id - map from function id to logical pf id 2667 * @active_function_bitmap: active function bitmap 2668 * @pf_id: function number of device 2669 * 2670 * Return: logical PF ID. 2671 */ 2672 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2673 { 2674 u8 logical_id = 0; 2675 u8 i; 2676 2677 for (i = 0; i < pf_id; i++) 2678 if (active_function_bitmap & BIT(i)) 2679 logical_id++; 2680 2681 return logical_id; 2682 } 2683 2684 /** 2685 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2686 * @hw: pointer to the HW struct 2687 * @dev_p: pointer to device capabilities structure 2688 * @cap: capability element to parse 2689 * 2690 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2691 */ 2692 static void 2693 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2694 struct libie_aqc_list_caps_elem *cap) 2695 { 2696 u32 number = le32_to_cpu(cap->number); 2697 2698 dev_p->num_funcs = hweight32(number); 2699 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2700 dev_p->num_funcs); 2701 2702 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2703 } 2704 2705 /** 2706 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2707 * @hw: pointer to the HW struct 2708 * @dev_p: pointer to device capabilities structure 2709 * @cap: capability element to parse 2710 * 2711 * Parse ICE_AQC_CAPS_VF for device capabilities. 2712 */ 2713 static void 2714 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2715 struct libie_aqc_list_caps_elem *cap) 2716 { 2717 u32 number = le32_to_cpu(cap->number); 2718 2719 dev_p->num_vfs_exposed = number; 2720 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2721 dev_p->num_vfs_exposed); 2722 } 2723 2724 /** 2725 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2726 * @hw: pointer to the HW struct 2727 * @dev_p: pointer to device capabilities structure 2728 * @cap: capability element to parse 2729 * 2730 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2731 */ 2732 static void 2733 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2734 struct libie_aqc_list_caps_elem *cap) 2735 { 2736 u32 number = le32_to_cpu(cap->number); 2737 2738 dev_p->num_vsi_allocd_to_host = number; 2739 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2740 dev_p->num_vsi_allocd_to_host); 2741 } 2742 2743 /** 2744 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2745 * @hw: pointer to the HW struct 2746 * @dev_p: pointer to device capabilities structure 2747 * @cap: capability element to parse 2748 * 2749 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2750 */ 2751 static void 2752 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2753 struct libie_aqc_list_caps_elem *cap) 2754 { 2755 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2756 u32 logical_id = le32_to_cpu(cap->logical_id); 2757 u32 phys_id = le32_to_cpu(cap->phys_id); 2758 u32 number = le32_to_cpu(cap->number); 2759 2760 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2761 dev_p->common_cap.ieee_1588 = info->ena; 2762 2763 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2764 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2765 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2766 2767 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2768 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2769 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2770 2771 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2772 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2773 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2774 2775 info->ena_ports = logical_id; 2776 info->tmr_own_map = phys_id; 2777 2778 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2779 dev_p->common_cap.ieee_1588); 2780 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2781 info->tmr0_owner); 2782 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2783 info->tmr0_owned); 2784 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2785 info->tmr0_ena); 2786 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2787 info->tmr1_owner); 2788 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2789 info->tmr1_owned); 2790 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2791 info->tmr1_ena); 2792 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2793 info->ts_ll_read); 2794 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2795 info->ts_ll_int_read); 2796 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2797 info->ll_phy_tmr_update); 2798 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2799 info->ena_ports); 2800 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2801 info->tmr_own_map); 2802 } 2803 2804 /** 2805 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2806 * @hw: pointer to the HW struct 2807 * @dev_p: pointer to device capabilities structure 2808 * @cap: capability element to parse 2809 * 2810 * Parse ICE_AQC_CAPS_FD for device capabilities. 2811 */ 2812 static void 2813 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2814 struct libie_aqc_list_caps_elem *cap) 2815 { 2816 u32 number = le32_to_cpu(cap->number); 2817 2818 dev_p->num_flow_director_fltr = number; 2819 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2820 dev_p->num_flow_director_fltr); 2821 } 2822 2823 /** 2824 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2825 * @hw: pointer to the HW struct 2826 * @dev_p: pointer to device capabilities structure 2827 * @cap: capability element to parse 2828 * 2829 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2830 * enabled sensors. 2831 */ 2832 static void 2833 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2834 struct libie_aqc_list_caps_elem *cap) 2835 { 2836 dev_p->supported_sensors = le32_to_cpu(cap->number); 2837 2838 ice_debug(hw, ICE_DBG_INIT, 2839 "dev caps: supported sensors (bitmap) = 0x%x\n", 2840 dev_p->supported_sensors); 2841 } 2842 2843 /** 2844 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2845 * @hw: pointer to the HW struct 2846 * @dev_p: pointer to device capabilities structure 2847 * @cap: capability element to parse 2848 * 2849 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2850 */ 2851 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2852 struct ice_hw_dev_caps *dev_p, 2853 struct libie_aqc_list_caps_elem *cap) 2854 { 2855 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2856 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2857 2858 dev_info(ice_hw_to_dev(hw), 2859 "PF is configured in %s mode with IP instance ID %d\n", 2860 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2861 "primary" : "secondary", dev_p->nac_topo.id); 2862 2863 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2864 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2865 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2866 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2867 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2868 dev_p->nac_topo.id); 2869 } 2870 2871 /** 2872 * ice_parse_dev_caps - Parse device capabilities 2873 * @hw: pointer to the HW struct 2874 * @dev_p: pointer to device capabilities structure 2875 * @buf: buffer containing the device capability records 2876 * @cap_count: the number of capabilities 2877 * 2878 * Helper device to parse device (0x000B) capabilities list. For 2879 * capabilities shared between device and function, this relies on 2880 * ice_parse_common_caps. 2881 * 2882 * Loop through the list of provided capabilities and extract the relevant 2883 * data into the device capabilities structured. 2884 */ 2885 static void 2886 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2887 void *buf, u32 cap_count) 2888 { 2889 struct libie_aqc_list_caps_elem *cap_resp; 2890 u32 i; 2891 2892 cap_resp = buf; 2893 2894 memset(dev_p, 0, sizeof(*dev_p)); 2895 2896 for (i = 0; i < cap_count; i++) { 2897 u16 cap = le16_to_cpu(cap_resp[i].cap); 2898 bool found; 2899 2900 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2901 &cap_resp[i], "dev caps"); 2902 2903 switch (cap) { 2904 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2905 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2906 break; 2907 case LIBIE_AQC_CAPS_VF: 2908 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2909 break; 2910 case LIBIE_AQC_CAPS_VSI: 2911 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2912 break; 2913 case LIBIE_AQC_CAPS_1588: 2914 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2915 break; 2916 case LIBIE_AQC_CAPS_FD: 2917 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2918 break; 2919 case LIBIE_AQC_CAPS_SENSOR_READING: 2920 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2921 break; 2922 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2923 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2924 break; 2925 default: 2926 /* Don't list common capabilities as unknown */ 2927 if (!found) 2928 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2929 i, cap); 2930 break; 2931 } 2932 } 2933 2934 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2935 } 2936 2937 /** 2938 * ice_is_phy_rclk_in_netlist 2939 * @hw: pointer to the hw struct 2940 * 2941 * Check if the PHY Recovered Clock device is present in the netlist 2942 */ 2943 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2944 { 2945 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2946 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2947 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2948 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2949 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2950 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2951 return false; 2952 2953 return true; 2954 } 2955 2956 /** 2957 * ice_is_clock_mux_in_netlist 2958 * @hw: pointer to the hw struct 2959 * 2960 * Check if the Clock Multiplexer device is present in the netlist 2961 */ 2962 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2963 { 2964 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2965 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2966 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2967 NULL)) 2968 return false; 2969 2970 return true; 2971 } 2972 2973 /** 2974 * ice_is_cgu_in_netlist - check for CGU presence 2975 * @hw: pointer to the hw struct 2976 * 2977 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2978 * Save the CGU part number in the hw structure for later use. 2979 * Return: 2980 * * true - cgu is present 2981 * * false - cgu is not present 2982 */ 2983 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2984 { 2985 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2986 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2987 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2988 NULL)) { 2989 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2990 return true; 2991 } else if (!ice_find_netlist_node(hw, 2992 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2993 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2994 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2995 NULL)) { 2996 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2997 return true; 2998 } 2999 3000 return false; 3001 } 3002 3003 /** 3004 * ice_is_gps_in_netlist 3005 * @hw: pointer to the hw struct 3006 * 3007 * Check if the GPS generic device is present in the netlist 3008 */ 3009 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3010 { 3011 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3012 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3013 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3014 return false; 3015 3016 return true; 3017 } 3018 3019 /** 3020 * ice_aq_list_caps - query function/device capabilities 3021 * @hw: pointer to the HW struct 3022 * @buf: a buffer to hold the capabilities 3023 * @buf_size: size of the buffer 3024 * @cap_count: if not NULL, set to the number of capabilities reported 3025 * @opc: capabilities type to discover, device or function 3026 * @cd: pointer to command details structure or NULL 3027 * 3028 * Get the function (0x000A) or device (0x000B) capabilities description from 3029 * firmware and store it in the buffer. 3030 * 3031 * If the cap_count pointer is not NULL, then it is set to the number of 3032 * capabilities firmware will report. Note that if the buffer size is too 3033 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3034 * cap_count will still be updated in this case. It is recommended that the 3035 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3036 * firmware could return) to avoid this. 3037 */ 3038 int 3039 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3040 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3041 { 3042 struct libie_aqc_list_caps *cmd; 3043 struct libie_aq_desc desc; 3044 int status; 3045 3046 cmd = &desc.params.get_cap; 3047 3048 if (opc != ice_aqc_opc_list_func_caps && 3049 opc != ice_aqc_opc_list_dev_caps) 3050 return -EINVAL; 3051 3052 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3053 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3054 3055 if (cap_count) 3056 *cap_count = le32_to_cpu(cmd->count); 3057 3058 return status; 3059 } 3060 3061 /** 3062 * ice_discover_dev_caps - Read and extract device capabilities 3063 * @hw: pointer to the hardware structure 3064 * @dev_caps: pointer to device capabilities structure 3065 * 3066 * Read the device capabilities and extract them into the dev_caps structure 3067 * for later use. 3068 */ 3069 int 3070 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3071 { 3072 u32 cap_count = 0; 3073 void *cbuf; 3074 int status; 3075 3076 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3077 if (!cbuf) 3078 return -ENOMEM; 3079 3080 /* Although the driver doesn't know the number of capabilities the 3081 * device will return, we can simply send a 4KB buffer, the maximum 3082 * possible size that firmware can return. 3083 */ 3084 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3085 3086 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3087 ice_aqc_opc_list_dev_caps, NULL); 3088 if (!status) 3089 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3090 kfree(cbuf); 3091 3092 return status; 3093 } 3094 3095 /** 3096 * ice_discover_func_caps - Read and extract function capabilities 3097 * @hw: pointer to the hardware structure 3098 * @func_caps: pointer to function capabilities structure 3099 * 3100 * Read the function capabilities and extract them into the func_caps structure 3101 * for later use. 3102 */ 3103 static int 3104 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3105 { 3106 u32 cap_count = 0; 3107 void *cbuf; 3108 int status; 3109 3110 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3111 if (!cbuf) 3112 return -ENOMEM; 3113 3114 /* Although the driver doesn't know the number of capabilities the 3115 * device will return, we can simply send a 4KB buffer, the maximum 3116 * possible size that firmware can return. 3117 */ 3118 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3119 3120 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3121 ice_aqc_opc_list_func_caps, NULL); 3122 if (!status) 3123 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3124 kfree(cbuf); 3125 3126 return status; 3127 } 3128 3129 /** 3130 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3131 * @hw: pointer to the hardware structure 3132 */ 3133 void ice_set_safe_mode_caps(struct ice_hw *hw) 3134 { 3135 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3136 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3137 struct ice_hw_common_caps cached_caps; 3138 u32 num_funcs; 3139 3140 /* cache some func_caps values that should be restored after memset */ 3141 cached_caps = func_caps->common_cap; 3142 3143 /* unset func capabilities */ 3144 memset(func_caps, 0, sizeof(*func_caps)); 3145 3146 #define ICE_RESTORE_FUNC_CAP(name) \ 3147 func_caps->common_cap.name = cached_caps.name 3148 3149 /* restore cached values */ 3150 ICE_RESTORE_FUNC_CAP(valid_functions); 3151 ICE_RESTORE_FUNC_CAP(txq_first_id); 3152 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3153 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3154 ICE_RESTORE_FUNC_CAP(max_mtu); 3155 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3156 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3157 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3158 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3159 3160 /* one Tx and one Rx queue in safe mode */ 3161 func_caps->common_cap.num_rxq = 1; 3162 func_caps->common_cap.num_txq = 1; 3163 3164 /* two MSIX vectors, one for traffic and one for misc causes */ 3165 func_caps->common_cap.num_msix_vectors = 2; 3166 func_caps->guar_num_vsi = 1; 3167 3168 /* cache some dev_caps values that should be restored after memset */ 3169 cached_caps = dev_caps->common_cap; 3170 num_funcs = dev_caps->num_funcs; 3171 3172 /* unset dev capabilities */ 3173 memset(dev_caps, 0, sizeof(*dev_caps)); 3174 3175 #define ICE_RESTORE_DEV_CAP(name) \ 3176 dev_caps->common_cap.name = cached_caps.name 3177 3178 /* restore cached values */ 3179 ICE_RESTORE_DEV_CAP(valid_functions); 3180 ICE_RESTORE_DEV_CAP(txq_first_id); 3181 ICE_RESTORE_DEV_CAP(rxq_first_id); 3182 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3183 ICE_RESTORE_DEV_CAP(max_mtu); 3184 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3185 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3186 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3187 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3188 dev_caps->num_funcs = num_funcs; 3189 3190 /* one Tx and one Rx queue per function in safe mode */ 3191 dev_caps->common_cap.num_rxq = num_funcs; 3192 dev_caps->common_cap.num_txq = num_funcs; 3193 3194 /* two MSIX vectors per function */ 3195 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3196 } 3197 3198 /** 3199 * ice_get_caps - get info about the HW 3200 * @hw: pointer to the hardware structure 3201 */ 3202 int ice_get_caps(struct ice_hw *hw) 3203 { 3204 int status; 3205 3206 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3207 if (status) 3208 return status; 3209 3210 return ice_discover_func_caps(hw, &hw->func_caps); 3211 } 3212 3213 /** 3214 * ice_aq_manage_mac_write - manage MAC address write command 3215 * @hw: pointer to the HW struct 3216 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3217 * @flags: flags to control write behavior 3218 * @cd: pointer to command details structure or NULL 3219 * 3220 * This function is used to write MAC address to the NVM (0x0108). 3221 */ 3222 int 3223 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3224 struct ice_sq_cd *cd) 3225 { 3226 struct ice_aqc_manage_mac_write *cmd; 3227 struct libie_aq_desc desc; 3228 3229 cmd = libie_aq_raw(&desc); 3230 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3231 3232 cmd->flags = flags; 3233 ether_addr_copy(cmd->mac_addr, mac_addr); 3234 3235 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3236 } 3237 3238 /** 3239 * ice_aq_clear_pxe_mode 3240 * @hw: pointer to the HW struct 3241 * 3242 * Tell the firmware that the driver is taking over from PXE (0x0110). 3243 */ 3244 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3245 { 3246 struct ice_aqc_clear_pxe *cmd; 3247 struct libie_aq_desc desc; 3248 3249 cmd = libie_aq_raw(&desc); 3250 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3251 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3252 3253 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3254 } 3255 3256 /** 3257 * ice_clear_pxe_mode - clear pxe operations mode 3258 * @hw: pointer to the HW struct 3259 * 3260 * Make sure all PXE mode settings are cleared, including things 3261 * like descriptor fetch/write-back mode. 3262 */ 3263 void ice_clear_pxe_mode(struct ice_hw *hw) 3264 { 3265 if (ice_check_sq_alive(hw, &hw->adminq)) 3266 ice_aq_clear_pxe_mode(hw); 3267 } 3268 3269 /** 3270 * ice_aq_set_port_params - set physical port parameters. 3271 * @pi: pointer to the port info struct 3272 * @double_vlan: if set double VLAN is enabled 3273 * @cd: pointer to command details structure or NULL 3274 * 3275 * Set Physical port parameters (0x0203) 3276 */ 3277 int 3278 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3279 struct ice_sq_cd *cd) 3280 3281 { 3282 struct ice_aqc_set_port_params *cmd; 3283 struct ice_hw *hw = pi->hw; 3284 struct libie_aq_desc desc; 3285 u16 cmd_flags = 0; 3286 3287 cmd = libie_aq_raw(&desc); 3288 3289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3290 if (double_vlan) 3291 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3292 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3293 3294 cmd->local_fwd_mode = pi->local_fwd_mode | 3295 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3296 3297 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3298 } 3299 3300 /** 3301 * ice_is_100m_speed_supported 3302 * @hw: pointer to the HW struct 3303 * 3304 * returns true if 100M speeds are supported by the device, 3305 * false otherwise. 3306 */ 3307 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3308 { 3309 switch (hw->device_id) { 3310 case ICE_DEV_ID_E822C_SGMII: 3311 case ICE_DEV_ID_E822L_SGMII: 3312 case ICE_DEV_ID_E823L_1GBE: 3313 case ICE_DEV_ID_E823C_SGMII: 3314 return true; 3315 default: 3316 return false; 3317 } 3318 } 3319 3320 /** 3321 * ice_get_link_speed_based_on_phy_type - returns link speed 3322 * @phy_type_low: lower part of phy_type 3323 * @phy_type_high: higher part of phy_type 3324 * 3325 * This helper function will convert an entry in PHY type structure 3326 * [phy_type_low, phy_type_high] to its corresponding link speed. 3327 * Note: In the structure of [phy_type_low, phy_type_high], there should 3328 * be one bit set, as this function will convert one PHY type to its 3329 * speed. 3330 * 3331 * Return: 3332 * * PHY speed for recognized PHY type 3333 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3334 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3335 */ 3336 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3337 { 3338 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3339 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3340 3341 switch (phy_type_low) { 3342 case ICE_PHY_TYPE_LOW_100BASE_TX: 3343 case ICE_PHY_TYPE_LOW_100M_SGMII: 3344 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3345 break; 3346 case ICE_PHY_TYPE_LOW_1000BASE_T: 3347 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3348 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3349 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3350 case ICE_PHY_TYPE_LOW_1G_SGMII: 3351 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3352 break; 3353 case ICE_PHY_TYPE_LOW_2500BASE_T: 3354 case ICE_PHY_TYPE_LOW_2500BASE_X: 3355 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3356 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3357 break; 3358 case ICE_PHY_TYPE_LOW_5GBASE_T: 3359 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3360 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3361 break; 3362 case ICE_PHY_TYPE_LOW_10GBASE_T: 3363 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3364 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3365 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3366 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3367 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3368 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3369 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3370 break; 3371 case ICE_PHY_TYPE_LOW_25GBASE_T: 3372 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3373 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3374 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3375 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3376 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3377 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3378 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3379 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3380 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3381 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3382 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3383 break; 3384 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3385 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3386 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3387 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3388 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3389 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3390 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3391 break; 3392 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3393 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3394 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3395 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3396 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3397 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3398 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3399 case ICE_PHY_TYPE_LOW_50G_AUI2: 3400 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3401 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3402 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3403 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3404 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3405 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3406 case ICE_PHY_TYPE_LOW_50G_AUI1: 3407 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3408 break; 3409 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3410 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3411 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3412 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3413 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3414 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3415 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3416 case ICE_PHY_TYPE_LOW_100G_AUI4: 3417 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3418 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3419 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3420 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3421 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3422 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3423 break; 3424 default: 3425 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3426 break; 3427 } 3428 3429 switch (phy_type_high) { 3430 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3431 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3432 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3433 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3434 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3435 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3436 break; 3437 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3438 case ICE_PHY_TYPE_HIGH_200G_SR4: 3439 case ICE_PHY_TYPE_HIGH_200G_FR4: 3440 case ICE_PHY_TYPE_HIGH_200G_LR4: 3441 case ICE_PHY_TYPE_HIGH_200G_DR4: 3442 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3443 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3444 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3445 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3446 break; 3447 default: 3448 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3449 break; 3450 } 3451 3452 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3453 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3454 return ICE_AQ_LINK_SPEED_UNKNOWN; 3455 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3456 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3457 return ICE_AQ_LINK_SPEED_UNKNOWN; 3458 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3459 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3460 return speed_phy_type_low; 3461 else 3462 return speed_phy_type_high; 3463 } 3464 3465 /** 3466 * ice_update_phy_type 3467 * @phy_type_low: pointer to the lower part of phy_type 3468 * @phy_type_high: pointer to the higher part of phy_type 3469 * @link_speeds_bitmap: targeted link speeds bitmap 3470 * 3471 * Note: For the link_speeds_bitmap structure, you can check it at 3472 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3473 * link_speeds_bitmap include multiple speeds. 3474 * 3475 * Each entry in this [phy_type_low, phy_type_high] structure will 3476 * present a certain link speed. This helper function will turn on bits 3477 * in [phy_type_low, phy_type_high] structure based on the value of 3478 * link_speeds_bitmap input parameter. 3479 */ 3480 void 3481 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3482 u16 link_speeds_bitmap) 3483 { 3484 u64 pt_high; 3485 u64 pt_low; 3486 int index; 3487 u16 speed; 3488 3489 /* We first check with low part of phy_type */ 3490 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3491 pt_low = BIT_ULL(index); 3492 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3493 3494 if (link_speeds_bitmap & speed) 3495 *phy_type_low |= BIT_ULL(index); 3496 } 3497 3498 /* We then check with high part of phy_type */ 3499 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3500 pt_high = BIT_ULL(index); 3501 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3502 3503 if (link_speeds_bitmap & speed) 3504 *phy_type_high |= BIT_ULL(index); 3505 } 3506 } 3507 3508 /** 3509 * ice_aq_set_phy_cfg 3510 * @hw: pointer to the HW struct 3511 * @pi: port info structure of the interested logical port 3512 * @cfg: structure with PHY configuration data to be set 3513 * @cd: pointer to command details structure or NULL 3514 * 3515 * Set the various PHY configuration parameters supported on the Port. 3516 * One or more of the Set PHY config parameters may be ignored in an MFP 3517 * mode as the PF may not have the privilege to set some of the PHY Config 3518 * parameters. This status will be indicated by the command response (0x0601). 3519 */ 3520 int 3521 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3522 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3523 { 3524 struct ice_aqc_set_phy_cfg *cmd; 3525 struct libie_aq_desc desc; 3526 int status; 3527 3528 if (!cfg) 3529 return -EINVAL; 3530 3531 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3532 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3533 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3534 cfg->caps); 3535 3536 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3537 } 3538 3539 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3540 cmd = libie_aq_raw(&desc); 3541 cmd->lport_num = pi->lport; 3542 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3543 3544 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3545 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3546 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3547 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3548 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3549 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3550 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3551 cfg->low_power_ctrl_an); 3552 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3553 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3554 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3555 cfg->link_fec_opt); 3556 3557 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3558 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3559 status = 0; 3560 3561 if (!status) 3562 pi->phy.curr_user_phy_cfg = *cfg; 3563 3564 return status; 3565 } 3566 3567 /** 3568 * ice_update_link_info - update status of the HW network link 3569 * @pi: port info structure of the interested logical port 3570 */ 3571 int ice_update_link_info(struct ice_port_info *pi) 3572 { 3573 struct ice_link_status *li; 3574 int status; 3575 3576 if (!pi) 3577 return -EINVAL; 3578 3579 li = &pi->phy.link_info; 3580 3581 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3582 if (status) 3583 return status; 3584 3585 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3586 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3587 3588 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3589 if (!pcaps) 3590 return -ENOMEM; 3591 3592 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3593 pcaps, NULL); 3594 } 3595 3596 return status; 3597 } 3598 3599 /** 3600 * ice_aq_get_phy_equalization - function to read serdes equaliser 3601 * value from firmware using admin queue command. 3602 * @hw: pointer to the HW struct 3603 * @data_in: represents the serdes equalization parameter requested 3604 * @op_code: represents the serdes number and flag to represent tx or rx 3605 * @serdes_num: represents the serdes number 3606 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3607 * 3608 * Return: non-zero status on error and 0 on success. 3609 */ 3610 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3611 u8 serdes_num, int *output) 3612 { 3613 struct ice_aqc_dnl_call_command *cmd; 3614 struct ice_aqc_dnl_call buf = {}; 3615 struct libie_aq_desc desc; 3616 int err; 3617 3618 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3619 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3620 cpu_to_le16(op_code | (serdes_num & 0xF)); 3621 cmd = libie_aq_raw(&desc); 3622 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3623 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3624 LIBIE_AQ_FLAG_RD | 3625 LIBIE_AQ_FLAG_SI); 3626 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3627 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3628 3629 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3630 NULL); 3631 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3632 3633 return err; 3634 } 3635 3636 #define FEC_REG_PORT(port) { \ 3637 FEC_CORR_LOW_REG_PORT##port, \ 3638 FEC_CORR_HIGH_REG_PORT##port, \ 3639 FEC_UNCORR_LOW_REG_PORT##port, \ 3640 FEC_UNCORR_HIGH_REG_PORT##port, \ 3641 } 3642 3643 static const u32 fec_reg[][ICE_FEC_MAX] = { 3644 FEC_REG_PORT(0), 3645 FEC_REG_PORT(1), 3646 FEC_REG_PORT(2), 3647 FEC_REG_PORT(3) 3648 }; 3649 3650 /** 3651 * ice_aq_get_fec_stats - reads fec stats from phy 3652 * @hw: pointer to the HW struct 3653 * @pcs_quad: represents pcsquad of user input serdes 3654 * @pcs_port: represents the pcs port number part of above pcs quad 3655 * @fec_type: represents FEC stats type 3656 * @output: pointer to the caller-supplied buffer to return requested fec stats 3657 * 3658 * Return: non-zero status on error and 0 on success. 3659 */ 3660 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3661 enum ice_fec_stats_types fec_type, u32 *output) 3662 { 3663 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3664 struct ice_sbq_msg_input msg = {}; 3665 u32 receiver_id, reg_offset; 3666 int err; 3667 3668 if (pcs_port > 3) 3669 return -EINVAL; 3670 3671 reg_offset = fec_reg[pcs_port][fec_type]; 3672 3673 if (pcs_quad == 0) 3674 receiver_id = FEC_RECEIVER_ID_PCS0; 3675 else if (pcs_quad == 1) 3676 receiver_id = FEC_RECEIVER_ID_PCS1; 3677 else 3678 return -EINVAL; 3679 3680 msg.msg_addr_low = lower_16_bits(reg_offset); 3681 msg.msg_addr_high = receiver_id; 3682 msg.opcode = ice_sbq_msg_rd; 3683 msg.dest_dev = ice_sbq_dev_phy_0; 3684 3685 err = ice_sbq_rw_reg(hw, &msg, flag); 3686 if (err) 3687 return err; 3688 3689 *output = msg.data; 3690 return 0; 3691 } 3692 3693 /** 3694 * ice_cache_phy_user_req 3695 * @pi: port information structure 3696 * @cache_data: PHY logging data 3697 * @cache_mode: PHY logging mode 3698 * 3699 * Log the user request on (FC, FEC, SPEED) for later use. 3700 */ 3701 static void 3702 ice_cache_phy_user_req(struct ice_port_info *pi, 3703 struct ice_phy_cache_mode_data cache_data, 3704 enum ice_phy_cache_mode cache_mode) 3705 { 3706 if (!pi) 3707 return; 3708 3709 switch (cache_mode) { 3710 case ICE_FC_MODE: 3711 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3712 break; 3713 case ICE_SPEED_MODE: 3714 pi->phy.curr_user_speed_req = 3715 cache_data.data.curr_user_speed_req; 3716 break; 3717 case ICE_FEC_MODE: 3718 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3719 break; 3720 default: 3721 break; 3722 } 3723 } 3724 3725 /** 3726 * ice_caps_to_fc_mode 3727 * @caps: PHY capabilities 3728 * 3729 * Convert PHY FC capabilities to ice FC mode 3730 */ 3731 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3732 { 3733 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3734 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3735 return ICE_FC_FULL; 3736 3737 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3738 return ICE_FC_TX_PAUSE; 3739 3740 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3741 return ICE_FC_RX_PAUSE; 3742 3743 return ICE_FC_NONE; 3744 } 3745 3746 /** 3747 * ice_caps_to_fec_mode 3748 * @caps: PHY capabilities 3749 * @fec_options: Link FEC options 3750 * 3751 * Convert PHY FEC capabilities to ice FEC mode 3752 */ 3753 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3754 { 3755 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3756 return ICE_FEC_AUTO; 3757 3758 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3759 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3760 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3761 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3762 return ICE_FEC_BASER; 3763 3764 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3765 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3766 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3767 return ICE_FEC_RS; 3768 3769 return ICE_FEC_NONE; 3770 } 3771 3772 /** 3773 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3774 * @pi: port information structure 3775 * @cfg: PHY configuration data to set FC mode 3776 * @req_mode: FC mode to configure 3777 */ 3778 int 3779 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3780 enum ice_fc_mode req_mode) 3781 { 3782 struct ice_phy_cache_mode_data cache_data; 3783 u8 pause_mask = 0x0; 3784 3785 if (!pi || !cfg) 3786 return -EINVAL; 3787 3788 switch (req_mode) { 3789 case ICE_FC_FULL: 3790 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3791 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3792 break; 3793 case ICE_FC_RX_PAUSE: 3794 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3795 break; 3796 case ICE_FC_TX_PAUSE: 3797 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3798 break; 3799 default: 3800 break; 3801 } 3802 3803 /* clear the old pause settings */ 3804 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3805 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3806 3807 /* set the new capabilities */ 3808 cfg->caps |= pause_mask; 3809 3810 /* Cache user FC request */ 3811 cache_data.data.curr_user_fc_req = req_mode; 3812 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3813 3814 return 0; 3815 } 3816 3817 /** 3818 * ice_set_fc 3819 * @pi: port information structure 3820 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3821 * @ena_auto_link_update: enable automatic link update 3822 * 3823 * Set the requested flow control mode. 3824 */ 3825 int 3826 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3827 { 3828 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3829 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3830 struct ice_hw *hw; 3831 int status; 3832 3833 if (!pi || !aq_failures) 3834 return -EINVAL; 3835 3836 *aq_failures = 0; 3837 hw = pi->hw; 3838 3839 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3840 if (!pcaps) 3841 return -ENOMEM; 3842 3843 /* Get the current PHY config */ 3844 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3845 pcaps, NULL); 3846 if (status) { 3847 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3848 goto out; 3849 } 3850 3851 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3852 3853 /* Configure the set PHY data */ 3854 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3855 if (status) 3856 goto out; 3857 3858 /* If the capabilities have changed, then set the new config */ 3859 if (cfg.caps != pcaps->caps) { 3860 int retry_count, retry_max = 10; 3861 3862 /* Auto restart link so settings take effect */ 3863 if (ena_auto_link_update) 3864 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3865 3866 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3867 if (status) { 3868 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3869 goto out; 3870 } 3871 3872 /* Update the link info 3873 * It sometimes takes a really long time for link to 3874 * come back from the atomic reset. Thus, we wait a 3875 * little bit. 3876 */ 3877 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3878 status = ice_update_link_info(pi); 3879 3880 if (!status) 3881 break; 3882 3883 mdelay(100); 3884 } 3885 3886 if (status) 3887 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3888 } 3889 3890 out: 3891 return status; 3892 } 3893 3894 /** 3895 * ice_phy_caps_equals_cfg 3896 * @phy_caps: PHY capabilities 3897 * @phy_cfg: PHY configuration 3898 * 3899 * Helper function to determine if PHY capabilities matches PHY 3900 * configuration 3901 */ 3902 bool 3903 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3904 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3905 { 3906 u8 caps_mask, cfg_mask; 3907 3908 if (!phy_caps || !phy_cfg) 3909 return false; 3910 3911 /* These bits are not common between capabilities and configuration. 3912 * Do not use them to determine equality. 3913 */ 3914 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3915 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3916 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3917 3918 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3919 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3920 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3921 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3922 phy_caps->eee_cap != phy_cfg->eee_cap || 3923 phy_caps->eeer_value != phy_cfg->eeer_value || 3924 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3925 return false; 3926 3927 return true; 3928 } 3929 3930 /** 3931 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3932 * @pi: port information structure 3933 * @caps: PHY ability structure to copy date from 3934 * @cfg: PHY configuration structure to copy data to 3935 * 3936 * Helper function to copy AQC PHY get ability data to PHY set configuration 3937 * data structure 3938 */ 3939 void 3940 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3941 struct ice_aqc_get_phy_caps_data *caps, 3942 struct ice_aqc_set_phy_cfg_data *cfg) 3943 { 3944 if (!pi || !caps || !cfg) 3945 return; 3946 3947 memset(cfg, 0, sizeof(*cfg)); 3948 cfg->phy_type_low = caps->phy_type_low; 3949 cfg->phy_type_high = caps->phy_type_high; 3950 cfg->caps = caps->caps; 3951 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3952 cfg->eee_cap = caps->eee_cap; 3953 cfg->eeer_value = caps->eeer_value; 3954 cfg->link_fec_opt = caps->link_fec_options; 3955 cfg->module_compliance_enforcement = 3956 caps->module_compliance_enforcement; 3957 } 3958 3959 /** 3960 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3961 * @pi: port information structure 3962 * @cfg: PHY configuration data to set FEC mode 3963 * @fec: FEC mode to configure 3964 */ 3965 int 3966 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3967 enum ice_fec_mode fec) 3968 { 3969 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3970 struct ice_hw *hw; 3971 int status; 3972 3973 if (!pi || !cfg) 3974 return -EINVAL; 3975 3976 hw = pi->hw; 3977 3978 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3979 if (!pcaps) 3980 return -ENOMEM; 3981 3982 status = ice_aq_get_phy_caps(pi, false, 3983 (ice_fw_supports_report_dflt_cfg(hw) ? 3984 ICE_AQC_REPORT_DFLT_CFG : 3985 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3986 if (status) 3987 goto out; 3988 3989 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3990 cfg->link_fec_opt = pcaps->link_fec_options; 3991 3992 switch (fec) { 3993 case ICE_FEC_BASER: 3994 /* Clear RS bits, and AND BASE-R ability 3995 * bits and OR request bits. 3996 */ 3997 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3998 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3999 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4000 ICE_AQC_PHY_FEC_25G_KR_REQ; 4001 break; 4002 case ICE_FEC_RS: 4003 /* Clear BASE-R bits, and AND RS ability 4004 * bits and OR request bits. 4005 */ 4006 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4007 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4008 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4009 break; 4010 case ICE_FEC_NONE: 4011 /* Clear all FEC option bits. */ 4012 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4013 break; 4014 case ICE_FEC_AUTO: 4015 /* AND auto FEC bit, and all caps bits. */ 4016 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4017 cfg->link_fec_opt |= pcaps->link_fec_options; 4018 break; 4019 default: 4020 status = -EINVAL; 4021 break; 4022 } 4023 4024 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4025 !ice_fw_supports_report_dflt_cfg(hw)) { 4026 struct ice_link_default_override_tlv tlv = { 0 }; 4027 4028 status = ice_get_link_default_override(&tlv, pi); 4029 if (status) 4030 goto out; 4031 4032 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4033 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4034 cfg->link_fec_opt = tlv.fec_options; 4035 } 4036 4037 out: 4038 return status; 4039 } 4040 4041 /** 4042 * ice_get_link_status - get status of the HW network link 4043 * @pi: port information structure 4044 * @link_up: pointer to bool (true/false = linkup/linkdown) 4045 * 4046 * Variable link_up is true if link is up, false if link is down. 4047 * The variable link_up is invalid if status is non zero. As a 4048 * result of this call, link status reporting becomes enabled 4049 */ 4050 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4051 { 4052 struct ice_phy_info *phy_info; 4053 int status = 0; 4054 4055 if (!pi || !link_up) 4056 return -EINVAL; 4057 4058 phy_info = &pi->phy; 4059 4060 if (phy_info->get_link_info) { 4061 status = ice_update_link_info(pi); 4062 4063 if (status) 4064 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4065 status); 4066 } 4067 4068 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4069 4070 return status; 4071 } 4072 4073 /** 4074 * ice_aq_set_link_restart_an 4075 * @pi: pointer to the port information structure 4076 * @ena_link: if true: enable link, if false: disable link 4077 * @cd: pointer to command details structure or NULL 4078 * 4079 * Sets up the link and restarts the Auto-Negotiation over the link. 4080 */ 4081 int 4082 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4083 struct ice_sq_cd *cd) 4084 { 4085 struct ice_aqc_restart_an *cmd; 4086 struct libie_aq_desc desc; 4087 4088 cmd = libie_aq_raw(&desc); 4089 4090 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4091 4092 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4093 cmd->lport_num = pi->lport; 4094 if (ena_link) 4095 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4096 else 4097 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4098 4099 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4100 } 4101 4102 /** 4103 * ice_aq_set_event_mask 4104 * @hw: pointer to the HW struct 4105 * @port_num: port number of the physical function 4106 * @mask: event mask to be set 4107 * @cd: pointer to command details structure or NULL 4108 * 4109 * Set event mask (0x0613) 4110 */ 4111 int 4112 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4113 struct ice_sq_cd *cd) 4114 { 4115 struct ice_aqc_set_event_mask *cmd; 4116 struct libie_aq_desc desc; 4117 4118 cmd = libie_aq_raw(&desc); 4119 4120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4121 4122 cmd->lport_num = port_num; 4123 4124 cmd->event_mask = cpu_to_le16(mask); 4125 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4126 } 4127 4128 /** 4129 * ice_aq_set_mac_loopback 4130 * @hw: pointer to the HW struct 4131 * @ena_lpbk: Enable or Disable loopback 4132 * @cd: pointer to command details structure or NULL 4133 * 4134 * Enable/disable loopback on a given port 4135 */ 4136 int 4137 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4138 { 4139 struct ice_aqc_set_mac_lb *cmd; 4140 struct libie_aq_desc desc; 4141 4142 cmd = libie_aq_raw(&desc); 4143 4144 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4145 if (ena_lpbk) 4146 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4147 4148 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4149 } 4150 4151 /** 4152 * ice_aq_set_port_id_led 4153 * @pi: pointer to the port information 4154 * @is_orig_mode: is this LED set to original mode (by the net-list) 4155 * @cd: pointer to command details structure or NULL 4156 * 4157 * Set LED value for the given port (0x06e9) 4158 */ 4159 int 4160 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4161 struct ice_sq_cd *cd) 4162 { 4163 struct ice_aqc_set_port_id_led *cmd; 4164 struct ice_hw *hw = pi->hw; 4165 struct libie_aq_desc desc; 4166 4167 cmd = libie_aq_raw(&desc); 4168 4169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4170 4171 if (is_orig_mode) 4172 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4173 else 4174 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4175 4176 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4177 } 4178 4179 /** 4180 * ice_aq_get_port_options 4181 * @hw: pointer to the HW struct 4182 * @options: buffer for the resultant port options 4183 * @option_count: input - size of the buffer in port options structures, 4184 * output - number of returned port options 4185 * @lport: logical port to call the command with (optional) 4186 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4187 * when PF owns more than 1 port it must be true 4188 * @active_option_idx: index of active port option in returned buffer 4189 * @active_option_valid: active option in returned buffer is valid 4190 * @pending_option_idx: index of pending port option in returned buffer 4191 * @pending_option_valid: pending option in returned buffer is valid 4192 * 4193 * Calls Get Port Options AQC (0x06ea) and verifies result. 4194 */ 4195 int 4196 ice_aq_get_port_options(struct ice_hw *hw, 4197 struct ice_aqc_get_port_options_elem *options, 4198 u8 *option_count, u8 lport, bool lport_valid, 4199 u8 *active_option_idx, bool *active_option_valid, 4200 u8 *pending_option_idx, bool *pending_option_valid) 4201 { 4202 struct ice_aqc_get_port_options *cmd; 4203 struct libie_aq_desc desc; 4204 int status; 4205 u8 i; 4206 4207 /* options buffer shall be able to hold max returned options */ 4208 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4209 return -EINVAL; 4210 4211 cmd = libie_aq_raw(&desc); 4212 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4213 4214 if (lport_valid) 4215 cmd->lport_num = lport; 4216 cmd->lport_num_valid = lport_valid; 4217 4218 status = ice_aq_send_cmd(hw, &desc, options, 4219 *option_count * sizeof(*options), NULL); 4220 if (status) 4221 return status; 4222 4223 /* verify direct FW response & set output parameters */ 4224 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4225 cmd->port_options_count); 4226 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4227 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4228 cmd->port_options); 4229 if (*active_option_valid) { 4230 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4231 cmd->port_options); 4232 if (*active_option_idx > (*option_count - 1)) 4233 return -EIO; 4234 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4235 *active_option_idx); 4236 } 4237 4238 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4239 cmd->pending_port_option_status); 4240 if (*pending_option_valid) { 4241 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4242 cmd->pending_port_option_status); 4243 if (*pending_option_idx > (*option_count - 1)) 4244 return -EIO; 4245 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4246 *pending_option_idx); 4247 } 4248 4249 /* mask output options fields */ 4250 for (i = 0; i < *option_count; i++) { 4251 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4252 options[i].pmd); 4253 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4254 options[i].max_lane_speed); 4255 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4256 options[i].pmd, options[i].max_lane_speed); 4257 } 4258 4259 return 0; 4260 } 4261 4262 /** 4263 * ice_aq_set_port_option 4264 * @hw: pointer to the HW struct 4265 * @lport: logical port to call the command with 4266 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4267 * when PF owns more than 1 port it must be true 4268 * @new_option: new port option to be written 4269 * 4270 * Calls Set Port Options AQC (0x06eb). 4271 */ 4272 int 4273 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4274 u8 new_option) 4275 { 4276 struct ice_aqc_set_port_option *cmd; 4277 struct libie_aq_desc desc; 4278 4279 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4280 return -EINVAL; 4281 4282 cmd = libie_aq_raw(&desc); 4283 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4284 4285 if (lport_valid) 4286 cmd->lport_num = lport; 4287 4288 cmd->lport_num_valid = lport_valid; 4289 cmd->selected_port_option = new_option; 4290 4291 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4292 } 4293 4294 /** 4295 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4296 * @hw: pointer to the hw struct 4297 * 4298 * Return: PHY lane number on success, negative error code otherwise. 4299 */ 4300 int ice_get_phy_lane_number(struct ice_hw *hw) 4301 { 4302 struct ice_aqc_get_port_options_elem *options; 4303 unsigned int lport = 0; 4304 unsigned int lane; 4305 int err; 4306 4307 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4308 if (!options) 4309 return -ENOMEM; 4310 4311 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4312 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4313 u8 speed, active_idx, pending_idx; 4314 bool active_valid, pending_valid; 4315 4316 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4317 true, &active_idx, &active_valid, 4318 &pending_idx, &pending_valid); 4319 if (err) 4320 goto err; 4321 4322 if (!active_valid) 4323 continue; 4324 4325 speed = options[active_idx].max_lane_speed; 4326 /* If we don't get speed for this lane, it's unoccupied */ 4327 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4328 continue; 4329 4330 if (hw->pf_id == lport) { 4331 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4332 ice_is_dual(hw) && !ice_is_primary(hw)) 4333 lane += ICE_PORTS_PER_QUAD; 4334 kfree(options); 4335 return lane; 4336 } 4337 lport++; 4338 } 4339 4340 /* PHY lane not found */ 4341 err = -ENXIO; 4342 err: 4343 kfree(options); 4344 return err; 4345 } 4346 4347 /** 4348 * ice_aq_sff_eeprom 4349 * @hw: pointer to the HW struct 4350 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4351 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4352 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4353 * @page: QSFP page 4354 * @set_page: set or ignore the page 4355 * @data: pointer to data buffer to be read/written to the I2C device. 4356 * @length: 1-16 for read, 1 for write. 4357 * @write: 0 read, 1 for write. 4358 * @cd: pointer to command details structure or NULL 4359 * 4360 * Read/Write SFF EEPROM (0x06EE) 4361 */ 4362 int 4363 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4364 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4365 bool write, struct ice_sq_cd *cd) 4366 { 4367 struct ice_aqc_sff_eeprom *cmd; 4368 struct libie_aq_desc desc; 4369 u16 i2c_bus_addr; 4370 int status; 4371 4372 if (!data || (mem_addr & 0xff00)) 4373 return -EINVAL; 4374 4375 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4376 cmd = libie_aq_raw(&desc); 4377 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4378 cmd->lport_num = (u8)(lport & 0xff); 4379 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4380 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4381 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4382 if (write) 4383 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4384 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4385 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4386 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4387 4388 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4389 return status; 4390 } 4391 4392 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4393 { 4394 switch (type) { 4395 case ICE_LUT_VSI: 4396 return ICE_LUT_VSI_SIZE; 4397 case ICE_LUT_GLOBAL: 4398 return ICE_LUT_GLOBAL_SIZE; 4399 case ICE_LUT_PF: 4400 return ICE_LUT_PF_SIZE; 4401 } 4402 WARN_ONCE(1, "incorrect type passed"); 4403 return ICE_LUT_VSI_SIZE; 4404 } 4405 4406 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4407 { 4408 switch (size) { 4409 case ICE_LUT_VSI_SIZE: 4410 return ICE_AQC_LUT_SIZE_SMALL; 4411 case ICE_LUT_GLOBAL_SIZE: 4412 return ICE_AQC_LUT_SIZE_512; 4413 case ICE_LUT_PF_SIZE: 4414 return ICE_AQC_LUT_SIZE_2K; 4415 } 4416 WARN_ONCE(1, "incorrect size passed"); 4417 return 0; 4418 } 4419 4420 /** 4421 * __ice_aq_get_set_rss_lut 4422 * @hw: pointer to the hardware structure 4423 * @params: RSS LUT parameters 4424 * @set: set true to set the table, false to get the table 4425 * 4426 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4427 */ 4428 static int 4429 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4430 struct ice_aq_get_set_rss_lut_params *params, bool set) 4431 { 4432 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4433 enum ice_lut_type lut_type = params->lut_type; 4434 struct ice_aqc_get_set_rss_lut *desc_params; 4435 enum ice_aqc_lut_flags flags; 4436 enum ice_lut_size lut_size; 4437 struct libie_aq_desc desc; 4438 u8 *lut = params->lut; 4439 4440 4441 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4442 return -EINVAL; 4443 4444 lut_size = ice_lut_type_to_size(lut_type); 4445 if (lut_size > params->lut_size) 4446 return -EINVAL; 4447 else if (set && lut_size != params->lut_size) 4448 return -EINVAL; 4449 4450 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4451 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4452 if (set) 4453 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4454 4455 desc_params = libie_aq_raw(&desc); 4456 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4457 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4458 4459 if (lut_type == ICE_LUT_GLOBAL) 4460 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4461 params->global_lut_id); 4462 4463 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4464 desc_params->flags = cpu_to_le16(flags); 4465 4466 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4467 } 4468 4469 /** 4470 * ice_aq_get_rss_lut 4471 * @hw: pointer to the hardware structure 4472 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4473 * 4474 * get the RSS lookup table, PF or VSI type 4475 */ 4476 int 4477 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4478 { 4479 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4480 } 4481 4482 /** 4483 * ice_aq_set_rss_lut 4484 * @hw: pointer to the hardware structure 4485 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4486 * 4487 * set the RSS lookup table, PF or VSI type 4488 */ 4489 int 4490 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4491 { 4492 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4493 } 4494 4495 /** 4496 * __ice_aq_get_set_rss_key 4497 * @hw: pointer to the HW struct 4498 * @vsi_id: VSI FW index 4499 * @key: pointer to key info struct 4500 * @set: set true to set the key, false to get the key 4501 * 4502 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4503 */ 4504 static int 4505 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4506 struct ice_aqc_get_set_rss_keys *key, bool set) 4507 { 4508 struct ice_aqc_get_set_rss_key *desc_params; 4509 u16 key_size = sizeof(*key); 4510 struct libie_aq_desc desc; 4511 4512 if (set) { 4513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4514 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4515 } else { 4516 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4517 } 4518 4519 desc_params = libie_aq_raw(&desc); 4520 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4521 4522 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4523 } 4524 4525 /** 4526 * ice_aq_get_rss_key 4527 * @hw: pointer to the HW struct 4528 * @vsi_handle: software VSI handle 4529 * @key: pointer to key info struct 4530 * 4531 * get the RSS key per VSI 4532 */ 4533 int 4534 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4535 struct ice_aqc_get_set_rss_keys *key) 4536 { 4537 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4538 return -EINVAL; 4539 4540 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4541 key, false); 4542 } 4543 4544 /** 4545 * ice_aq_set_rss_key 4546 * @hw: pointer to the HW struct 4547 * @vsi_handle: software VSI handle 4548 * @keys: pointer to key info struct 4549 * 4550 * set the RSS key per VSI 4551 */ 4552 int 4553 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4554 struct ice_aqc_get_set_rss_keys *keys) 4555 { 4556 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4557 return -EINVAL; 4558 4559 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4560 keys, true); 4561 } 4562 4563 /** 4564 * ice_aq_add_lan_txq 4565 * @hw: pointer to the hardware structure 4566 * @num_qgrps: Number of added queue groups 4567 * @qg_list: list of queue groups to be added 4568 * @buf_size: size of buffer for indirect command 4569 * @cd: pointer to command details structure or NULL 4570 * 4571 * Add Tx LAN queue (0x0C30) 4572 * 4573 * NOTE: 4574 * Prior to calling add Tx LAN queue: 4575 * Initialize the following as part of the Tx queue context: 4576 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4577 * Cache profile and Packet shaper profile. 4578 * 4579 * After add Tx LAN queue AQ command is completed: 4580 * Interrupts should be associated with specific queues, 4581 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4582 * flow. 4583 */ 4584 static int 4585 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4586 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4587 struct ice_sq_cd *cd) 4588 { 4589 struct ice_aqc_add_tx_qgrp *list; 4590 struct ice_aqc_add_txqs *cmd; 4591 struct libie_aq_desc desc; 4592 u16 i, sum_size = 0; 4593 4594 cmd = libie_aq_raw(&desc); 4595 4596 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4597 4598 if (!qg_list) 4599 return -EINVAL; 4600 4601 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4602 return -EINVAL; 4603 4604 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4605 sum_size += struct_size(list, txqs, list->num_txqs); 4606 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4607 list->num_txqs); 4608 } 4609 4610 if (buf_size != sum_size) 4611 return -EINVAL; 4612 4613 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4614 4615 cmd->num_qgrps = num_qgrps; 4616 4617 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4618 } 4619 4620 /** 4621 * ice_aq_dis_lan_txq 4622 * @hw: pointer to the hardware structure 4623 * @num_qgrps: number of groups in the list 4624 * @qg_list: the list of groups to disable 4625 * @buf_size: the total size of the qg_list buffer in bytes 4626 * @rst_src: if called due to reset, specifies the reset source 4627 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4628 * @cd: pointer to command details structure or NULL 4629 * 4630 * Disable LAN Tx queue (0x0C31) 4631 */ 4632 static int 4633 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4634 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4635 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4636 struct ice_sq_cd *cd) 4637 { 4638 struct ice_aqc_dis_txq_item *item; 4639 struct ice_aqc_dis_txqs *cmd; 4640 struct libie_aq_desc desc; 4641 u16 vmvf_and_timeout; 4642 u16 i, sz = 0; 4643 int status; 4644 4645 cmd = libie_aq_raw(&desc); 4646 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4647 4648 /* qg_list can be NULL only in VM/VF reset flow */ 4649 if (!qg_list && !rst_src) 4650 return -EINVAL; 4651 4652 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4653 return -EINVAL; 4654 4655 cmd->num_entries = num_qgrps; 4656 4657 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4658 4659 switch (rst_src) { 4660 case ICE_VM_RESET: 4661 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4662 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4663 break; 4664 case ICE_VF_RESET: 4665 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4666 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4667 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4668 ICE_AQC_Q_DIS_VMVF_NUM_M; 4669 break; 4670 case ICE_NO_RESET: 4671 default: 4672 break; 4673 } 4674 4675 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4676 4677 /* flush pipe on time out */ 4678 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4679 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4680 if (!qg_list) 4681 goto do_aq; 4682 4683 /* set RD bit to indicate that command buffer is provided by the driver 4684 * and it needs to be read by the firmware 4685 */ 4686 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4687 4688 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4689 u16 item_size = struct_size(item, q_id, item->num_qs); 4690 4691 /* If the num of queues is even, add 2 bytes of padding */ 4692 if ((item->num_qs % 2) == 0) 4693 item_size += 2; 4694 4695 sz += item_size; 4696 4697 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4698 } 4699 4700 if (buf_size != sz) 4701 return -EINVAL; 4702 4703 do_aq: 4704 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4705 if (status) { 4706 if (!qg_list) 4707 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4708 vmvf_num, hw->adminq.sq_last_status); 4709 else 4710 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4711 le16_to_cpu(qg_list[0].q_id[0]), 4712 hw->adminq.sq_last_status); 4713 } 4714 return status; 4715 } 4716 4717 /** 4718 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4719 * @hw: pointer to the hardware structure 4720 * @buf: buffer for command 4721 * @buf_size: size of buffer in bytes 4722 * @num_qs: number of queues being configured 4723 * @oldport: origination lport 4724 * @newport: destination lport 4725 * @mode: cmd_type for move to use 4726 * @cd: pointer to command details structure or NULL 4727 * 4728 * Move/Configure LAN Tx queue (0x0C32) 4729 * 4730 * Return: Zero on success, associated error code on failure. 4731 */ 4732 int 4733 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4734 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4735 u8 mode, struct ice_sq_cd *cd) 4736 { 4737 struct ice_aqc_cfg_txqs *cmd; 4738 struct libie_aq_desc desc; 4739 int status; 4740 4741 cmd = libie_aq_raw(&desc); 4742 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4743 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4744 4745 if (!buf) 4746 return -EINVAL; 4747 4748 cmd->cmd_type = mode; 4749 cmd->num_qs = num_qs; 4750 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4751 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4752 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4753 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4754 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4755 cmd->blocked_cgds = 0; 4756 4757 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4758 if (status) 4759 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4760 hw->adminq.sq_last_status); 4761 return status; 4762 } 4763 4764 /** 4765 * ice_aq_add_rdma_qsets 4766 * @hw: pointer to the hardware structure 4767 * @num_qset_grps: Number of RDMA Qset groups 4768 * @qset_list: list of Qset groups to be added 4769 * @buf_size: size of buffer for indirect command 4770 * @cd: pointer to command details structure or NULL 4771 * 4772 * Add Tx RDMA Qsets (0x0C33) 4773 */ 4774 static int 4775 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4776 struct ice_aqc_add_rdma_qset_data *qset_list, 4777 u16 buf_size, struct ice_sq_cd *cd) 4778 { 4779 struct ice_aqc_add_rdma_qset_data *list; 4780 struct ice_aqc_add_rdma_qset *cmd; 4781 struct libie_aq_desc desc; 4782 u16 i, sum_size = 0; 4783 4784 cmd = libie_aq_raw(&desc); 4785 4786 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4787 4788 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4789 return -EINVAL; 4790 4791 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4792 u16 num_qsets = le16_to_cpu(list->num_qsets); 4793 4794 sum_size += struct_size(list, rdma_qsets, num_qsets); 4795 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4796 num_qsets); 4797 } 4798 4799 if (buf_size != sum_size) 4800 return -EINVAL; 4801 4802 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4803 4804 cmd->num_qset_grps = num_qset_grps; 4805 4806 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4807 } 4808 4809 /* End of FW Admin Queue command wrappers */ 4810 4811 /** 4812 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4813 * @hw: pointer to the HW struct 4814 * @vsi_handle: software VSI handle 4815 * @tc: TC number 4816 * @q_handle: software queue handle 4817 */ 4818 struct ice_q_ctx * 4819 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4820 { 4821 struct ice_vsi_ctx *vsi; 4822 struct ice_q_ctx *q_ctx; 4823 4824 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4825 if (!vsi) 4826 return NULL; 4827 if (q_handle >= vsi->num_lan_q_entries[tc]) 4828 return NULL; 4829 if (!vsi->lan_q_ctx[tc]) 4830 return NULL; 4831 q_ctx = vsi->lan_q_ctx[tc]; 4832 return &q_ctx[q_handle]; 4833 } 4834 4835 /** 4836 * ice_ena_vsi_txq 4837 * @pi: port information structure 4838 * @vsi_handle: software VSI handle 4839 * @tc: TC number 4840 * @q_handle: software queue handle 4841 * @num_qgrps: Number of added queue groups 4842 * @buf: list of queue groups to be added 4843 * @buf_size: size of buffer for indirect command 4844 * @cd: pointer to command details structure or NULL 4845 * 4846 * This function adds one LAN queue 4847 */ 4848 int 4849 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4850 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4851 struct ice_sq_cd *cd) 4852 { 4853 struct ice_aqc_txsched_elem_data node = { 0 }; 4854 struct ice_sched_node *parent; 4855 struct ice_q_ctx *q_ctx; 4856 struct ice_hw *hw; 4857 int status; 4858 4859 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4860 return -EIO; 4861 4862 if (num_qgrps > 1 || buf->num_txqs > 1) 4863 return -ENOSPC; 4864 4865 hw = pi->hw; 4866 4867 if (!ice_is_vsi_valid(hw, vsi_handle)) 4868 return -EINVAL; 4869 4870 mutex_lock(&pi->sched_lock); 4871 4872 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4873 if (!q_ctx) { 4874 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4875 q_handle); 4876 status = -EINVAL; 4877 goto ena_txq_exit; 4878 } 4879 4880 /* find a parent node */ 4881 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4882 ICE_SCHED_NODE_OWNER_LAN); 4883 if (!parent) { 4884 status = -EINVAL; 4885 goto ena_txq_exit; 4886 } 4887 4888 buf->parent_teid = parent->info.node_teid; 4889 node.parent_teid = parent->info.node_teid; 4890 /* Mark that the values in the "generic" section as valid. The default 4891 * value in the "generic" section is zero. This means that : 4892 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4893 * - 0 priority among siblings, indicated by Bit 1-3. 4894 * - WFQ, indicated by Bit 4. 4895 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4896 * Bit 5-6. 4897 * - Bit 7 is reserved. 4898 * Without setting the generic section as valid in valid_sections, the 4899 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4900 */ 4901 buf->txqs[0].info.valid_sections = 4902 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4903 ICE_AQC_ELEM_VALID_EIR; 4904 buf->txqs[0].info.generic = 0; 4905 buf->txqs[0].info.cir_bw.bw_profile_idx = 4906 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4907 buf->txqs[0].info.cir_bw.bw_alloc = 4908 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4909 buf->txqs[0].info.eir_bw.bw_profile_idx = 4910 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4911 buf->txqs[0].info.eir_bw.bw_alloc = 4912 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4913 4914 /* add the LAN queue */ 4915 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4916 if (status) { 4917 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4918 le16_to_cpu(buf->txqs[0].txq_id), 4919 hw->adminq.sq_last_status); 4920 goto ena_txq_exit; 4921 } 4922 4923 node.node_teid = buf->txqs[0].q_teid; 4924 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4925 q_ctx->q_handle = q_handle; 4926 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4927 4928 /* add a leaf node into scheduler tree queue layer */ 4929 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4930 if (!status) 4931 status = ice_sched_replay_q_bw(pi, q_ctx); 4932 4933 ena_txq_exit: 4934 mutex_unlock(&pi->sched_lock); 4935 return status; 4936 } 4937 4938 /** 4939 * ice_dis_vsi_txq 4940 * @pi: port information structure 4941 * @vsi_handle: software VSI handle 4942 * @tc: TC number 4943 * @num_queues: number of queues 4944 * @q_handles: pointer to software queue handle array 4945 * @q_ids: pointer to the q_id array 4946 * @q_teids: pointer to queue node teids 4947 * @rst_src: if called due to reset, specifies the reset source 4948 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4949 * @cd: pointer to command details structure or NULL 4950 * 4951 * This function removes queues and their corresponding nodes in SW DB 4952 */ 4953 int 4954 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4955 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4956 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4957 struct ice_sq_cd *cd) 4958 { 4959 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4960 u16 i, buf_size = __struct_size(qg_list); 4961 struct ice_q_ctx *q_ctx; 4962 int status = -ENOENT; 4963 struct ice_hw *hw; 4964 4965 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4966 return -EIO; 4967 4968 hw = pi->hw; 4969 4970 if (!num_queues) { 4971 /* if queue is disabled already yet the disable queue command 4972 * has to be sent to complete the VF reset, then call 4973 * ice_aq_dis_lan_txq without any queue information 4974 */ 4975 if (rst_src) 4976 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4977 vmvf_num, NULL); 4978 return -EIO; 4979 } 4980 4981 mutex_lock(&pi->sched_lock); 4982 4983 for (i = 0; i < num_queues; i++) { 4984 struct ice_sched_node *node; 4985 4986 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4987 if (!node) 4988 continue; 4989 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4990 if (!q_ctx) { 4991 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4992 q_handles[i]); 4993 continue; 4994 } 4995 if (q_ctx->q_handle != q_handles[i]) { 4996 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4997 q_ctx->q_handle, q_handles[i]); 4998 continue; 4999 } 5000 qg_list->parent_teid = node->info.parent_teid; 5001 qg_list->num_qs = 1; 5002 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5003 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5004 vmvf_num, cd); 5005 5006 if (status) 5007 break; 5008 ice_free_sched_node(pi, node); 5009 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5010 q_ctx->q_teid = ICE_INVAL_TEID; 5011 } 5012 mutex_unlock(&pi->sched_lock); 5013 return status; 5014 } 5015 5016 /** 5017 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5018 * @pi: port information structure 5019 * @vsi_handle: software VSI handle 5020 * @tc_bitmap: TC bitmap 5021 * @maxqs: max queues array per TC 5022 * @owner: LAN or RDMA 5023 * 5024 * This function adds/updates the VSI queues per TC. 5025 */ 5026 static int 5027 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5028 u16 *maxqs, u8 owner) 5029 { 5030 int status = 0; 5031 u8 i; 5032 5033 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5034 return -EIO; 5035 5036 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5037 return -EINVAL; 5038 5039 mutex_lock(&pi->sched_lock); 5040 5041 ice_for_each_traffic_class(i) { 5042 /* configuration is possible only if TC node is present */ 5043 if (!ice_sched_get_tc_node(pi, i)) 5044 continue; 5045 5046 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5047 ice_is_tc_ena(tc_bitmap, i)); 5048 if (status) 5049 break; 5050 } 5051 5052 mutex_unlock(&pi->sched_lock); 5053 return status; 5054 } 5055 5056 /** 5057 * ice_cfg_vsi_lan - configure VSI LAN queues 5058 * @pi: port information structure 5059 * @vsi_handle: software VSI handle 5060 * @tc_bitmap: TC bitmap 5061 * @max_lanqs: max LAN queues array per TC 5062 * 5063 * This function adds/updates the VSI LAN queues per TC. 5064 */ 5065 int 5066 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5067 u16 *max_lanqs) 5068 { 5069 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5070 ICE_SCHED_NODE_OWNER_LAN); 5071 } 5072 5073 /** 5074 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5075 * @pi: port information structure 5076 * @vsi_handle: software VSI handle 5077 * @tc_bitmap: TC bitmap 5078 * @max_rdmaqs: max RDMA queues array per TC 5079 * 5080 * This function adds/updates the VSI RDMA queues per TC. 5081 */ 5082 int 5083 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5084 u16 *max_rdmaqs) 5085 { 5086 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5087 ICE_SCHED_NODE_OWNER_RDMA); 5088 } 5089 5090 /** 5091 * ice_ena_vsi_rdma_qset 5092 * @pi: port information structure 5093 * @vsi_handle: software VSI handle 5094 * @tc: TC number 5095 * @rdma_qset: pointer to RDMA Qset 5096 * @num_qsets: number of RDMA Qsets 5097 * @qset_teid: pointer to Qset node TEIDs 5098 * 5099 * This function adds RDMA Qset 5100 */ 5101 int 5102 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5103 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5104 { 5105 struct ice_aqc_txsched_elem_data node = { 0 }; 5106 struct ice_aqc_add_rdma_qset_data *buf; 5107 struct ice_sched_node *parent; 5108 struct ice_hw *hw; 5109 u16 i, buf_size; 5110 int ret; 5111 5112 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5113 return -EIO; 5114 hw = pi->hw; 5115 5116 if (!ice_is_vsi_valid(hw, vsi_handle)) 5117 return -EINVAL; 5118 5119 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5120 buf = kzalloc(buf_size, GFP_KERNEL); 5121 if (!buf) 5122 return -ENOMEM; 5123 mutex_lock(&pi->sched_lock); 5124 5125 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5126 ICE_SCHED_NODE_OWNER_RDMA); 5127 if (!parent) { 5128 ret = -EINVAL; 5129 goto rdma_error_exit; 5130 } 5131 buf->parent_teid = parent->info.node_teid; 5132 node.parent_teid = parent->info.node_teid; 5133 5134 buf->num_qsets = cpu_to_le16(num_qsets); 5135 for (i = 0; i < num_qsets; i++) { 5136 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5137 buf->rdma_qsets[i].info.valid_sections = 5138 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5139 ICE_AQC_ELEM_VALID_EIR; 5140 buf->rdma_qsets[i].info.generic = 0; 5141 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5142 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5143 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5144 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5145 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5146 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5147 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5148 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5149 } 5150 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5151 if (ret) { 5152 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5153 goto rdma_error_exit; 5154 } 5155 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5156 for (i = 0; i < num_qsets; i++) { 5157 node.node_teid = buf->rdma_qsets[i].qset_teid; 5158 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5159 &node, NULL); 5160 if (ret) 5161 break; 5162 qset_teid[i] = le32_to_cpu(node.node_teid); 5163 } 5164 rdma_error_exit: 5165 mutex_unlock(&pi->sched_lock); 5166 kfree(buf); 5167 return ret; 5168 } 5169 5170 /** 5171 * ice_dis_vsi_rdma_qset - free RDMA resources 5172 * @pi: port_info struct 5173 * @count: number of RDMA Qsets to free 5174 * @qset_teid: TEID of Qset node 5175 * @q_id: list of queue IDs being disabled 5176 */ 5177 int 5178 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5179 u16 *q_id) 5180 { 5181 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5182 u16 qg_size = __struct_size(qg_list); 5183 struct ice_hw *hw; 5184 int status = 0; 5185 int i; 5186 5187 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5188 return -EIO; 5189 5190 hw = pi->hw; 5191 5192 mutex_lock(&pi->sched_lock); 5193 5194 for (i = 0; i < count; i++) { 5195 struct ice_sched_node *node; 5196 5197 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5198 if (!node) 5199 continue; 5200 5201 qg_list->parent_teid = node->info.parent_teid; 5202 qg_list->num_qs = 1; 5203 qg_list->q_id[0] = 5204 cpu_to_le16(q_id[i] | 5205 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5206 5207 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5208 ICE_NO_RESET, 0, NULL); 5209 if (status) 5210 break; 5211 5212 ice_free_sched_node(pi, node); 5213 } 5214 5215 mutex_unlock(&pi->sched_lock); 5216 return status; 5217 } 5218 5219 /** 5220 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5221 * @hw: pointer to the HW struct 5222 * @dpll_idx: index of dpll to be measured 5223 * @meas: array to be filled with results 5224 * @meas_num: max number of results array can hold 5225 * 5226 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5227 * pins on given dpll. 5228 * 5229 * Return: 0 on success or negative value on failure. 5230 */ 5231 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5232 struct ice_cgu_input_measure *meas, 5233 u16 meas_num) 5234 { 5235 struct ice_aqc_get_cgu_input_measure *cmd; 5236 struct libie_aq_desc desc; 5237 5238 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5239 cmd = libie_aq_raw(&desc); 5240 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5241 5242 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5243 } 5244 5245 /** 5246 * ice_aq_get_cgu_abilities - get cgu abilities 5247 * @hw: pointer to the HW struct 5248 * @abilities: CGU abilities 5249 * 5250 * Get CGU abilities (0x0C61) 5251 * Return: 0 on success or negative value on failure. 5252 */ 5253 int 5254 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5255 struct ice_aqc_get_cgu_abilities *abilities) 5256 { 5257 struct libie_aq_desc desc; 5258 5259 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5260 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5261 } 5262 5263 /** 5264 * ice_aq_set_input_pin_cfg - set input pin config 5265 * @hw: pointer to the HW struct 5266 * @input_idx: Input index 5267 * @flags1: Input flags 5268 * @flags2: Input flags 5269 * @freq: Frequency in Hz 5270 * @phase_delay: Delay in ps 5271 * 5272 * Set CGU input config (0x0C62) 5273 * Return: 0 on success or negative value on failure. 5274 */ 5275 int 5276 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5277 u32 freq, s32 phase_delay) 5278 { 5279 struct ice_aqc_set_cgu_input_config *cmd; 5280 struct libie_aq_desc desc; 5281 5282 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5283 cmd = libie_aq_raw(&desc); 5284 cmd->input_idx = input_idx; 5285 cmd->flags1 = flags1; 5286 cmd->flags2 = flags2; 5287 cmd->freq = cpu_to_le32(freq); 5288 cmd->phase_delay = cpu_to_le32(phase_delay); 5289 5290 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5291 } 5292 5293 /** 5294 * ice_aq_get_input_pin_cfg - get input pin config 5295 * @hw: pointer to the HW struct 5296 * @input_idx: Input index 5297 * @status: Pin status 5298 * @type: Pin type 5299 * @flags1: Input flags 5300 * @flags2: Input flags 5301 * @freq: Frequency in Hz 5302 * @phase_delay: Delay in ps 5303 * 5304 * Get CGU input config (0x0C63) 5305 * Return: 0 on success or negative value on failure. 5306 */ 5307 int 5308 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5309 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5310 { 5311 struct ice_aqc_get_cgu_input_config *cmd; 5312 struct libie_aq_desc desc; 5313 int ret; 5314 5315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5316 cmd = libie_aq_raw(&desc); 5317 cmd->input_idx = input_idx; 5318 5319 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5320 if (!ret) { 5321 if (status) 5322 *status = cmd->status; 5323 if (type) 5324 *type = cmd->type; 5325 if (flags1) 5326 *flags1 = cmd->flags1; 5327 if (flags2) 5328 *flags2 = cmd->flags2; 5329 if (freq) 5330 *freq = le32_to_cpu(cmd->freq); 5331 if (phase_delay) 5332 *phase_delay = le32_to_cpu(cmd->phase_delay); 5333 } 5334 5335 return ret; 5336 } 5337 5338 /** 5339 * ice_aq_set_output_pin_cfg - set output pin config 5340 * @hw: pointer to the HW struct 5341 * @output_idx: Output index 5342 * @flags: Output flags 5343 * @src_sel: Index of DPLL block 5344 * @freq: Output frequency 5345 * @phase_delay: Output phase compensation 5346 * 5347 * Set CGU output config (0x0C64) 5348 * Return: 0 on success or negative value on failure. 5349 */ 5350 int 5351 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5352 u8 src_sel, u32 freq, s32 phase_delay) 5353 { 5354 struct ice_aqc_set_cgu_output_config *cmd; 5355 struct libie_aq_desc desc; 5356 5357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5358 cmd = libie_aq_raw(&desc); 5359 cmd->output_idx = output_idx; 5360 cmd->flags = flags; 5361 cmd->src_sel = src_sel; 5362 cmd->freq = cpu_to_le32(freq); 5363 cmd->phase_delay = cpu_to_le32(phase_delay); 5364 5365 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5366 } 5367 5368 /** 5369 * ice_aq_get_output_pin_cfg - get output pin config 5370 * @hw: pointer to the HW struct 5371 * @output_idx: Output index 5372 * @flags: Output flags 5373 * @src_sel: Internal DPLL source 5374 * @freq: Output frequency 5375 * @src_freq: Source frequency 5376 * 5377 * Get CGU output config (0x0C65) 5378 * Return: 0 on success or negative value on failure. 5379 */ 5380 int 5381 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5382 u8 *src_sel, u32 *freq, u32 *src_freq) 5383 { 5384 struct ice_aqc_get_cgu_output_config *cmd; 5385 struct libie_aq_desc desc; 5386 int ret; 5387 5388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5389 cmd = libie_aq_raw(&desc); 5390 cmd->output_idx = output_idx; 5391 5392 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5393 if (!ret) { 5394 if (flags) 5395 *flags = cmd->flags; 5396 if (src_sel) 5397 *src_sel = cmd->src_sel; 5398 if (freq) 5399 *freq = le32_to_cpu(cmd->freq); 5400 if (src_freq) 5401 *src_freq = le32_to_cpu(cmd->src_freq); 5402 } 5403 5404 return ret; 5405 } 5406 5407 /** 5408 * ice_aq_get_cgu_dpll_status - get dpll status 5409 * @hw: pointer to the HW struct 5410 * @dpll_num: DPLL index 5411 * @ref_state: Reference clock state 5412 * @config: current DPLL config 5413 * @dpll_state: current DPLL state 5414 * @phase_offset: Phase offset in ns 5415 * @eec_mode: EEC_mode 5416 * 5417 * Get CGU DPLL status (0x0C66) 5418 * Return: 0 on success or negative value on failure. 5419 */ 5420 int 5421 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5422 u8 *dpll_state, u8 *config, s64 *phase_offset, 5423 u8 *eec_mode) 5424 { 5425 struct ice_aqc_get_cgu_dpll_status *cmd; 5426 struct libie_aq_desc desc; 5427 int status; 5428 5429 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5430 cmd = libie_aq_raw(&desc); 5431 cmd->dpll_num = dpll_num; 5432 5433 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5434 if (!status) { 5435 *ref_state = cmd->ref_state; 5436 *dpll_state = cmd->dpll_state; 5437 *config = cmd->config; 5438 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5439 *phase_offset <<= 32; 5440 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5441 *phase_offset = sign_extend64(*phase_offset, 47); 5442 *eec_mode = cmd->eec_mode; 5443 } 5444 5445 return status; 5446 } 5447 5448 /** 5449 * ice_aq_set_cgu_dpll_config - set dpll config 5450 * @hw: pointer to the HW struct 5451 * @dpll_num: DPLL index 5452 * @ref_state: Reference clock state 5453 * @config: DPLL config 5454 * @eec_mode: EEC mode 5455 * 5456 * Set CGU DPLL config (0x0C67) 5457 * Return: 0 on success or negative value on failure. 5458 */ 5459 int 5460 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5461 u8 config, u8 eec_mode) 5462 { 5463 struct ice_aqc_set_cgu_dpll_config *cmd; 5464 struct libie_aq_desc desc; 5465 5466 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5467 cmd = libie_aq_raw(&desc); 5468 cmd->dpll_num = dpll_num; 5469 cmd->ref_state = ref_state; 5470 cmd->config = config; 5471 cmd->eec_mode = eec_mode; 5472 5473 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5474 } 5475 5476 /** 5477 * ice_aq_set_cgu_ref_prio - set input reference priority 5478 * @hw: pointer to the HW struct 5479 * @dpll_num: DPLL index 5480 * @ref_idx: Reference pin index 5481 * @ref_priority: Reference input priority 5482 * 5483 * Set CGU reference priority (0x0C68) 5484 * Return: 0 on success or negative value on failure. 5485 */ 5486 int 5487 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5488 u8 ref_priority) 5489 { 5490 struct ice_aqc_set_cgu_ref_prio *cmd; 5491 struct libie_aq_desc desc; 5492 5493 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5494 cmd = libie_aq_raw(&desc); 5495 cmd->dpll_num = dpll_num; 5496 cmd->ref_idx = ref_idx; 5497 cmd->ref_priority = ref_priority; 5498 5499 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5500 } 5501 5502 /** 5503 * ice_aq_get_cgu_ref_prio - get input reference priority 5504 * @hw: pointer to the HW struct 5505 * @dpll_num: DPLL index 5506 * @ref_idx: Reference pin index 5507 * @ref_prio: Reference input priority 5508 * 5509 * Get CGU reference priority (0x0C69) 5510 * Return: 0 on success or negative value on failure. 5511 */ 5512 int 5513 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5514 u8 *ref_prio) 5515 { 5516 struct ice_aqc_get_cgu_ref_prio *cmd; 5517 struct libie_aq_desc desc; 5518 int status; 5519 5520 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5521 cmd = libie_aq_raw(&desc); 5522 cmd->dpll_num = dpll_num; 5523 cmd->ref_idx = ref_idx; 5524 5525 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5526 if (!status) 5527 *ref_prio = cmd->ref_priority; 5528 5529 return status; 5530 } 5531 5532 /** 5533 * ice_aq_get_cgu_info - get cgu info 5534 * @hw: pointer to the HW struct 5535 * @cgu_id: CGU ID 5536 * @cgu_cfg_ver: CGU config version 5537 * @cgu_fw_ver: CGU firmware version 5538 * 5539 * Get CGU info (0x0C6A) 5540 * Return: 0 on success or negative value on failure. 5541 */ 5542 int 5543 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5544 u32 *cgu_fw_ver) 5545 { 5546 struct ice_aqc_get_cgu_info *cmd; 5547 struct libie_aq_desc desc; 5548 int status; 5549 5550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5551 cmd = libie_aq_raw(&desc); 5552 5553 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5554 if (!status) { 5555 *cgu_id = le32_to_cpu(cmd->cgu_id); 5556 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5557 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5558 } 5559 5560 return status; 5561 } 5562 5563 /** 5564 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5565 * @hw: pointer to the HW struct 5566 * @phy_output: PHY reference clock output pin 5567 * @enable: GPIO state to be applied 5568 * @freq: PHY output frequency 5569 * 5570 * Set phy recovered clock as reference (0x0630) 5571 * Return: 0 on success or negative value on failure. 5572 */ 5573 int 5574 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5575 u32 *freq) 5576 { 5577 struct ice_aqc_set_phy_rec_clk_out *cmd; 5578 struct libie_aq_desc desc; 5579 int status; 5580 5581 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5582 cmd = libie_aq_raw(&desc); 5583 cmd->phy_output = phy_output; 5584 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5585 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5586 cmd->freq = cpu_to_le32(*freq); 5587 5588 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5589 if (!status) 5590 *freq = le32_to_cpu(cmd->freq); 5591 5592 return status; 5593 } 5594 5595 /** 5596 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5597 * @hw: pointer to the HW struct 5598 * @phy_output: PHY reference clock output pin 5599 * @port_num: Port number 5600 * @flags: PHY flags 5601 * @node_handle: PHY output frequency 5602 * 5603 * Get PHY recovered clock output info (0x0631) 5604 * Return: 0 on success or negative value on failure. 5605 */ 5606 int 5607 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5608 u8 *flags, u16 *node_handle) 5609 { 5610 struct ice_aqc_get_phy_rec_clk_out *cmd; 5611 struct libie_aq_desc desc; 5612 int status; 5613 5614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5615 cmd = libie_aq_raw(&desc); 5616 cmd->phy_output = *phy_output; 5617 5618 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5619 if (!status) { 5620 *phy_output = cmd->phy_output; 5621 if (port_num) 5622 *port_num = cmd->port_num; 5623 if (flags) 5624 *flags = cmd->flags; 5625 if (node_handle) 5626 *node_handle = le16_to_cpu(cmd->node_handle); 5627 } 5628 5629 return status; 5630 } 5631 5632 /** 5633 * ice_aq_get_sensor_reading 5634 * @hw: pointer to the HW struct 5635 * @data: pointer to data to be read from the sensor 5636 * 5637 * Get sensor reading (0x0632) 5638 */ 5639 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5640 struct ice_aqc_get_sensor_reading_resp *data) 5641 { 5642 struct ice_aqc_get_sensor_reading *cmd; 5643 struct libie_aq_desc desc; 5644 int status; 5645 5646 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5647 cmd = libie_aq_raw(&desc); 5648 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5649 #define ICE_INTERNAL_TEMP_SENSOR 0 5650 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5651 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5652 5653 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5654 if (!status) 5655 memcpy(data, &desc.params.raw, 5656 sizeof(*data)); 5657 5658 return status; 5659 } 5660 5661 /** 5662 * ice_replay_pre_init - replay pre initialization 5663 * @hw: pointer to the HW struct 5664 * 5665 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5666 */ 5667 static int ice_replay_pre_init(struct ice_hw *hw) 5668 { 5669 struct ice_switch_info *sw = hw->switch_info; 5670 u8 i; 5671 5672 /* Delete old entries from replay filter list head if there is any */ 5673 ice_rm_all_sw_replay_rule_info(hw); 5674 /* In start of replay, move entries into replay_rules list, it 5675 * will allow adding rules entries back to filt_rules list, 5676 * which is operational list. 5677 */ 5678 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5679 list_replace_init(&sw->recp_list[i].filt_rules, 5680 &sw->recp_list[i].filt_replay_rules); 5681 ice_sched_replay_agg_vsi_preinit(hw); 5682 5683 return 0; 5684 } 5685 5686 /** 5687 * ice_replay_vsi - replay VSI configuration 5688 * @hw: pointer to the HW struct 5689 * @vsi_handle: driver VSI handle 5690 * 5691 * Restore all VSI configuration after reset. It is required to call this 5692 * function with main VSI first. 5693 */ 5694 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5695 { 5696 int status; 5697 5698 if (!ice_is_vsi_valid(hw, vsi_handle)) 5699 return -EINVAL; 5700 5701 /* Replay pre-initialization if there is any */ 5702 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5703 status = ice_replay_pre_init(hw); 5704 if (status) 5705 return status; 5706 } 5707 /* Replay per VSI all RSS configurations */ 5708 status = ice_replay_rss_cfg(hw, vsi_handle); 5709 if (status) 5710 return status; 5711 /* Replay per VSI all filters */ 5712 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5713 if (!status) 5714 status = ice_replay_vsi_agg(hw, vsi_handle); 5715 return status; 5716 } 5717 5718 /** 5719 * ice_replay_post - post replay configuration cleanup 5720 * @hw: pointer to the HW struct 5721 * 5722 * Post replay cleanup. 5723 */ 5724 void ice_replay_post(struct ice_hw *hw) 5725 { 5726 /* Delete old entries from replay filter list head */ 5727 ice_rm_all_sw_replay_rule_info(hw); 5728 ice_sched_replay_agg(hw); 5729 } 5730 5731 /** 5732 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5733 * @hw: ptr to the hardware info 5734 * @reg: offset of 64 bit HW register to read from 5735 * @prev_stat_loaded: bool to specify if previous stats are loaded 5736 * @prev_stat: ptr to previous loaded stat value 5737 * @cur_stat: ptr to current stat value 5738 */ 5739 void 5740 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5741 u64 *prev_stat, u64 *cur_stat) 5742 { 5743 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5744 5745 /* device stats are not reset at PFR, they likely will not be zeroed 5746 * when the driver starts. Thus, save the value from the first read 5747 * without adding to the statistic value so that we report stats which 5748 * count up from zero. 5749 */ 5750 if (!prev_stat_loaded) { 5751 *prev_stat = new_data; 5752 return; 5753 } 5754 5755 /* Calculate the difference between the new and old values, and then 5756 * add it to the software stat value. 5757 */ 5758 if (new_data >= *prev_stat) 5759 *cur_stat += new_data - *prev_stat; 5760 else 5761 /* to manage the potential roll-over */ 5762 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5763 5764 /* Update the previously stored value to prepare for next read */ 5765 *prev_stat = new_data; 5766 } 5767 5768 /** 5769 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5770 * @hw: ptr to the hardware info 5771 * @reg: offset of HW register to read from 5772 * @prev_stat_loaded: bool to specify if previous stats are loaded 5773 * @prev_stat: ptr to previous loaded stat value 5774 * @cur_stat: ptr to current stat value 5775 */ 5776 void 5777 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5778 u64 *prev_stat, u64 *cur_stat) 5779 { 5780 u32 new_data; 5781 5782 new_data = rd32(hw, reg); 5783 5784 /* device stats are not reset at PFR, they likely will not be zeroed 5785 * when the driver starts. Thus, save the value from the first read 5786 * without adding to the statistic value so that we report stats which 5787 * count up from zero. 5788 */ 5789 if (!prev_stat_loaded) { 5790 *prev_stat = new_data; 5791 return; 5792 } 5793 5794 /* Calculate the difference between the new and old values, and then 5795 * add it to the software stat value. 5796 */ 5797 if (new_data >= *prev_stat) 5798 *cur_stat += new_data - *prev_stat; 5799 else 5800 /* to manage the potential roll-over */ 5801 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5802 5803 /* Update the previously stored value to prepare for next read */ 5804 *prev_stat = new_data; 5805 } 5806 5807 /** 5808 * ice_sched_query_elem - query element information from HW 5809 * @hw: pointer to the HW struct 5810 * @node_teid: node TEID to be queried 5811 * @buf: buffer to element information 5812 * 5813 * This function queries HW element information 5814 */ 5815 int 5816 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5817 struct ice_aqc_txsched_elem_data *buf) 5818 { 5819 u16 buf_size, num_elem_ret = 0; 5820 int status; 5821 5822 buf_size = sizeof(*buf); 5823 memset(buf, 0, buf_size); 5824 buf->node_teid = cpu_to_le32(node_teid); 5825 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5826 NULL); 5827 if (status || num_elem_ret != 1) 5828 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5829 return status; 5830 } 5831 5832 /** 5833 * ice_aq_read_i2c 5834 * @hw: pointer to the hw struct 5835 * @topo_addr: topology address for a device to communicate with 5836 * @bus_addr: 7-bit I2C bus address 5837 * @addr: I2C memory address (I2C offset) with up to 16 bits 5838 * @params: I2C parameters: bit [7] - Repeated start, 5839 * bits [6:5] data offset size, 5840 * bit [4] - I2C address type, 5841 * bits [3:0] - data size to read (0-16 bytes) 5842 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5843 * @cd: pointer to command details structure or NULL 5844 * 5845 * Read I2C (0x06E2) 5846 */ 5847 int 5848 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5849 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5850 struct ice_sq_cd *cd) 5851 { 5852 struct libie_aq_desc desc = { 0 }; 5853 struct ice_aqc_i2c *cmd; 5854 u8 data_size; 5855 int status; 5856 5857 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5858 cmd = libie_aq_raw(&desc); 5859 5860 if (!data) 5861 return -EINVAL; 5862 5863 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5864 5865 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5866 cmd->topo_addr = topo_addr; 5867 cmd->i2c_params = params; 5868 cmd->i2c_addr = addr; 5869 5870 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5871 if (!status) { 5872 struct ice_aqc_read_i2c_resp *resp; 5873 u8 i; 5874 5875 resp = libie_aq_raw(&desc); 5876 for (i = 0; i < data_size; i++) { 5877 *data = resp->i2c_data[i]; 5878 data++; 5879 } 5880 } 5881 5882 return status; 5883 } 5884 5885 /** 5886 * ice_aq_write_i2c 5887 * @hw: pointer to the hw struct 5888 * @topo_addr: topology address for a device to communicate with 5889 * @bus_addr: 7-bit I2C bus address 5890 * @addr: I2C memory address (I2C offset) with up to 16 bits 5891 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5892 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5893 * @cd: pointer to command details structure or NULL 5894 * 5895 * Write I2C (0x06E3) 5896 * 5897 * * Return: 5898 * * 0 - Successful write to the i2c device 5899 * * -EINVAL - Data size greater than 4 bytes 5900 * * -EIO - FW error 5901 */ 5902 int 5903 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5904 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5905 struct ice_sq_cd *cd) 5906 { 5907 struct libie_aq_desc desc = { 0 }; 5908 struct ice_aqc_i2c *cmd; 5909 u8 data_size; 5910 5911 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5912 cmd = libie_aq_raw(&desc); 5913 5914 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5915 5916 /* data_size limited to 4 */ 5917 if (data_size > 4) 5918 return -EINVAL; 5919 5920 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5921 cmd->topo_addr = topo_addr; 5922 cmd->i2c_params = params; 5923 cmd->i2c_addr = addr; 5924 5925 memcpy(cmd->i2c_data, data, data_size); 5926 5927 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5928 } 5929 5930 /** 5931 * ice_get_pca9575_handle - find and return the PCA9575 controller 5932 * @hw: pointer to the hw struct 5933 * @pca9575_handle: GPIO controller's handle 5934 * 5935 * Find and return the GPIO controller's handle in the netlist. 5936 * When found - the value will be cached in the hw structure and following calls 5937 * will return cached value. 5938 * 5939 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5940 */ 5941 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5942 { 5943 struct ice_aqc_get_link_topo *cmd; 5944 struct libie_aq_desc desc; 5945 int err; 5946 u8 idx; 5947 5948 /* If handle was read previously return cached value */ 5949 if (hw->io_expander_handle) { 5950 *pca9575_handle = hw->io_expander_handle; 5951 return 0; 5952 } 5953 5954 #define SW_PCA9575_SFP_TOPO_IDX 2 5955 #define SW_PCA9575_QSFP_TOPO_IDX 1 5956 5957 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5958 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5959 idx = SW_PCA9575_SFP_TOPO_IDX; 5960 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5961 idx = SW_PCA9575_QSFP_TOPO_IDX; 5962 else 5963 return -ENXIO; 5964 5965 /* If handle was not detected read it from the netlist */ 5966 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5967 cmd = libie_aq_raw(&desc); 5968 cmd->addr.topo_params.node_type_ctx = 5969 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5970 cmd->addr.topo_params.index = idx; 5971 5972 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5973 if (err) 5974 return -ENXIO; 5975 5976 /* Verify if we found the right IO expander type */ 5977 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5978 return -ENXIO; 5979 5980 /* If present save the handle and return it */ 5981 hw->io_expander_handle = 5982 le16_to_cpu(cmd->addr.handle); 5983 *pca9575_handle = hw->io_expander_handle; 5984 5985 return 0; 5986 } 5987 5988 /** 5989 * ice_read_pca9575_reg - read the register from the PCA9575 controller 5990 * @hw: pointer to the hw struct 5991 * @offset: GPIO controller register offset 5992 * @data: pointer to data to be read from the GPIO controller 5993 * 5994 * Return: 0 on success, negative error code otherwise. 5995 */ 5996 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5997 { 5998 struct ice_aqc_link_topo_addr link_topo; 5999 __le16 addr; 6000 u16 handle; 6001 int err; 6002 6003 memset(&link_topo, 0, sizeof(link_topo)); 6004 6005 err = ice_get_pca9575_handle(hw, &handle); 6006 if (err) 6007 return err; 6008 6009 link_topo.handle = cpu_to_le16(handle); 6010 link_topo.topo_params.node_type_ctx = 6011 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6012 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6013 6014 addr = cpu_to_le16((u16)offset); 6015 6016 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6017 } 6018 6019 /** 6020 * ice_aq_set_gpio 6021 * @hw: pointer to the hw struct 6022 * @gpio_ctrl_handle: GPIO controller node handle 6023 * @pin_idx: IO Number of the GPIO that needs to be set 6024 * @value: SW provide IO value to set in the LSB 6025 * @cd: pointer to command details structure or NULL 6026 * 6027 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6028 */ 6029 int 6030 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6031 struct ice_sq_cd *cd) 6032 { 6033 struct libie_aq_desc desc; 6034 struct ice_aqc_gpio *cmd; 6035 6036 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6037 cmd = libie_aq_raw(&desc); 6038 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6039 cmd->gpio_num = pin_idx; 6040 cmd->gpio_val = value ? 1 : 0; 6041 6042 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6043 } 6044 6045 /** 6046 * ice_aq_get_gpio 6047 * @hw: pointer to the hw struct 6048 * @gpio_ctrl_handle: GPIO controller node handle 6049 * @pin_idx: IO Number of the GPIO that needs to be set 6050 * @value: IO value read 6051 * @cd: pointer to command details structure or NULL 6052 * 6053 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6054 * the topology 6055 */ 6056 int 6057 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6058 bool *value, struct ice_sq_cd *cd) 6059 { 6060 struct libie_aq_desc desc; 6061 struct ice_aqc_gpio *cmd; 6062 int status; 6063 6064 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6065 cmd = libie_aq_raw(&desc); 6066 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6067 cmd->gpio_num = pin_idx; 6068 6069 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6070 if (status) 6071 return status; 6072 6073 *value = !!cmd->gpio_val; 6074 return 0; 6075 } 6076 6077 /** 6078 * ice_is_fw_api_min_ver 6079 * @hw: pointer to the hardware structure 6080 * @maj: major version 6081 * @min: minor version 6082 * @patch: patch version 6083 * 6084 * Checks if the firmware API is minimum version 6085 */ 6086 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6087 { 6088 if (hw->api_maj_ver == maj) { 6089 if (hw->api_min_ver > min) 6090 return true; 6091 if (hw->api_min_ver == min && hw->api_patch >= patch) 6092 return true; 6093 } else if (hw->api_maj_ver > maj) { 6094 return true; 6095 } 6096 6097 return false; 6098 } 6099 6100 /** 6101 * ice_fw_supports_link_override 6102 * @hw: pointer to the hardware structure 6103 * 6104 * Checks if the firmware supports link override 6105 */ 6106 bool ice_fw_supports_link_override(struct ice_hw *hw) 6107 { 6108 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6109 ICE_FW_API_LINK_OVERRIDE_MIN, 6110 ICE_FW_API_LINK_OVERRIDE_PATCH); 6111 } 6112 6113 /** 6114 * ice_get_link_default_override 6115 * @ldo: pointer to the link default override struct 6116 * @pi: pointer to the port info struct 6117 * 6118 * Gets the link default override for a port 6119 */ 6120 int 6121 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6122 struct ice_port_info *pi) 6123 { 6124 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6125 struct ice_hw *hw = pi->hw; 6126 int status; 6127 6128 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6129 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6130 if (status) { 6131 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6132 return status; 6133 } 6134 6135 /* Each port has its own config; calculate for our port */ 6136 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6137 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6138 6139 /* link options first */ 6140 status = ice_read_sr_word(hw, tlv_start, &buf); 6141 if (status) { 6142 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6143 return status; 6144 } 6145 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6146 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6147 ICE_LINK_OVERRIDE_PHY_CFG_S; 6148 6149 /* link PHY config */ 6150 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6151 status = ice_read_sr_word(hw, offset, &buf); 6152 if (status) { 6153 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6154 return status; 6155 } 6156 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6157 6158 /* PHY types low */ 6159 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6160 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6161 status = ice_read_sr_word(hw, (offset + i), &buf); 6162 if (status) { 6163 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6164 return status; 6165 } 6166 /* shift 16 bits at a time to fill 64 bits */ 6167 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6168 } 6169 6170 /* PHY types high */ 6171 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6172 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6173 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6174 status = ice_read_sr_word(hw, (offset + i), &buf); 6175 if (status) { 6176 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6177 return status; 6178 } 6179 /* shift 16 bits at a time to fill 64 bits */ 6180 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6181 } 6182 6183 return status; 6184 } 6185 6186 /** 6187 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6188 * @caps: get PHY capability data 6189 */ 6190 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6191 { 6192 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6193 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6194 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6195 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6196 return true; 6197 6198 return false; 6199 } 6200 6201 /** 6202 * ice_is_fw_health_report_supported - checks if firmware supports health events 6203 * @hw: pointer to the hardware structure 6204 * 6205 * Return: true if firmware supports health status reports, 6206 * false otherwise 6207 */ 6208 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6209 { 6210 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6211 ICE_FW_API_HEALTH_REPORT_MIN, 6212 ICE_FW_API_HEALTH_REPORT_PATCH); 6213 } 6214 6215 /** 6216 * ice_aq_set_health_status_cfg - Configure FW health events 6217 * @hw: pointer to the HW struct 6218 * @event_source: type of diagnostic events to enable 6219 * 6220 * Configure the health status event types that the firmware will send to this 6221 * PF. The supported event types are: PF-specific, all PFs, and global. 6222 * 6223 * Return: 0 on success, negative error code otherwise. 6224 */ 6225 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6226 { 6227 struct ice_aqc_set_health_status_cfg *cmd; 6228 struct libie_aq_desc desc; 6229 6230 cmd = libie_aq_raw(&desc); 6231 6232 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6233 6234 cmd->event_source = event_source; 6235 6236 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6237 } 6238 6239 /** 6240 * ice_aq_set_lldp_mib - Set the LLDP MIB 6241 * @hw: pointer to the HW struct 6242 * @mib_type: Local, Remote or both Local and Remote MIBs 6243 * @buf: pointer to the caller-supplied buffer to store the MIB block 6244 * @buf_size: size of the buffer (in bytes) 6245 * @cd: pointer to command details structure or NULL 6246 * 6247 * Set the LLDP MIB. (0x0A08) 6248 */ 6249 int 6250 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6251 struct ice_sq_cd *cd) 6252 { 6253 struct ice_aqc_lldp_set_local_mib *cmd; 6254 struct libie_aq_desc desc; 6255 6256 cmd = libie_aq_raw(&desc); 6257 6258 if (buf_size == 0 || !buf) 6259 return -EINVAL; 6260 6261 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6262 6263 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6264 desc.datalen = cpu_to_le16(buf_size); 6265 6266 cmd->type = mib_type; 6267 cmd->length = cpu_to_le16(buf_size); 6268 6269 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6270 } 6271 6272 /** 6273 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6274 * @hw: pointer to HW struct 6275 */ 6276 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6277 { 6278 if (hw->mac_type != ICE_MAC_E810) 6279 return false; 6280 6281 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6282 ICE_FW_API_LLDP_FLTR_MIN, 6283 ICE_FW_API_LLDP_FLTR_PATCH); 6284 } 6285 6286 /** 6287 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6288 * @hw: pointer to HW struct 6289 * @vsi: VSI to add the filter to 6290 * @add: boolean for if adding or removing a filter 6291 * 6292 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6293 * with this HW or VSI, otherwise an error corresponding to 6294 * the AQ transaction result. 6295 */ 6296 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6297 { 6298 struct ice_aqc_lldp_filter_ctrl *cmd; 6299 struct libie_aq_desc desc; 6300 6301 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6302 return -EOPNOTSUPP; 6303 6304 cmd = libie_aq_raw(&desc); 6305 6306 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6307 6308 if (add) 6309 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6310 else 6311 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6312 6313 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6314 6315 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6316 } 6317 6318 /** 6319 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6320 * @hw: pointer to HW struct 6321 */ 6322 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6323 { 6324 struct libie_aq_desc desc; 6325 6326 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6327 6328 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6329 } 6330 6331 /** 6332 * ice_fw_supports_report_dflt_cfg 6333 * @hw: pointer to the hardware structure 6334 * 6335 * Checks if the firmware supports report default configuration 6336 */ 6337 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6338 { 6339 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6340 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6341 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6342 } 6343 6344 /* each of the indexes into the following array match the speed of a return 6345 * value from the list of AQ returned speeds like the range: 6346 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6347 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6348 * array. The array is defined as 15 elements long because the link_speed 6349 * returned by the firmware is a 16 bit * value, but is indexed 6350 * by [fls(speed) - 1] 6351 */ 6352 static const u32 ice_aq_to_link_speed[] = { 6353 SPEED_10, /* BIT(0) */ 6354 SPEED_100, 6355 SPEED_1000, 6356 SPEED_2500, 6357 SPEED_5000, 6358 SPEED_10000, 6359 SPEED_20000, 6360 SPEED_25000, 6361 SPEED_40000, 6362 SPEED_50000, 6363 SPEED_100000, /* BIT(10) */ 6364 SPEED_200000, 6365 }; 6366 6367 /** 6368 * ice_get_link_speed - get integer speed from table 6369 * @index: array index from fls(aq speed) - 1 6370 * 6371 * Returns: u32 value containing integer speed 6372 */ 6373 u32 ice_get_link_speed(u16 index) 6374 { 6375 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6376 return 0; 6377 6378 return ice_aq_to_link_speed[index]; 6379 } 6380 6381 /** 6382 * ice_read_cgu_reg - Read a CGU register 6383 * @hw: Pointer to the HW struct 6384 * @addr: Register address to read 6385 * @val: Storage for register value read 6386 * 6387 * Read the contents of a register of the Clock Generation Unit. Only 6388 * applicable to E82X devices. 6389 * 6390 * Return: 0 on success, other error codes when failed to read from CGU. 6391 */ 6392 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6393 { 6394 struct ice_sbq_msg_input cgu_msg = { 6395 .opcode = ice_sbq_msg_rd, 6396 .dest_dev = ice_sbq_dev_cgu, 6397 .msg_addr_low = addr 6398 }; 6399 int err; 6400 6401 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6402 if (err) { 6403 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6404 addr, err); 6405 return err; 6406 } 6407 6408 *val = cgu_msg.data; 6409 6410 return 0; 6411 } 6412 6413 /** 6414 * ice_write_cgu_reg - Write a CGU register 6415 * @hw: Pointer to the HW struct 6416 * @addr: Register address to write 6417 * @val: Value to write into the register 6418 * 6419 * Write the specified value to a register of the Clock Generation Unit. Only 6420 * applicable to E82X devices. 6421 * 6422 * Return: 0 on success, other error codes when failed to write to CGU. 6423 */ 6424 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6425 { 6426 struct ice_sbq_msg_input cgu_msg = { 6427 .opcode = ice_sbq_msg_wr, 6428 .dest_dev = ice_sbq_dev_cgu, 6429 .msg_addr_low = addr, 6430 .data = val 6431 }; 6432 int err; 6433 6434 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6435 if (err) 6436 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6437 addr, err); 6438 6439 return err; 6440 } 6441