1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 hw->mac_type = ICE_MAC_E830; 175 break; 176 default: 177 hw->mac_type = ICE_MAC_UNKNOWN; 178 break; 179 } 180 181 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 182 return 0; 183 } 184 185 /** 186 * ice_is_generic_mac - check if device's mac_type is generic 187 * @hw: pointer to the hardware structure 188 * 189 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 190 */ 191 bool ice_is_generic_mac(struct ice_hw *hw) 192 { 193 return (hw->mac_type == ICE_MAC_GENERIC || 194 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 195 } 196 197 /** 198 * ice_is_pf_c827 - check if pf contains c827 phy 199 * @hw: pointer to the hw struct 200 * 201 * Return: true if the device has c827 phy. 202 */ 203 static bool ice_is_pf_c827(struct ice_hw *hw) 204 { 205 struct ice_aqc_get_link_topo cmd = {}; 206 u8 node_part_number; 207 u16 node_handle; 208 int status; 209 210 if (hw->mac_type != ICE_MAC_E810) 211 return false; 212 213 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 214 return true; 215 216 cmd.addr.topo_params.node_type_ctx = 217 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 218 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 219 cmd.addr.topo_params.index = 0; 220 221 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 222 &node_handle); 223 224 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 225 return false; 226 227 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 228 return true; 229 230 return false; 231 } 232 233 /** 234 * ice_clear_pf_cfg - Clear PF configuration 235 * @hw: pointer to the hardware structure 236 * 237 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 238 * configuration, flow director filters, etc.). 239 */ 240 int ice_clear_pf_cfg(struct ice_hw *hw) 241 { 242 struct ice_aq_desc desc; 243 244 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 245 246 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 247 } 248 249 /** 250 * ice_aq_manage_mac_read - manage MAC address read command 251 * @hw: pointer to the HW struct 252 * @buf: a virtual buffer to hold the manage MAC read response 253 * @buf_size: Size of the virtual buffer 254 * @cd: pointer to command details structure or NULL 255 * 256 * This function is used to return per PF station MAC address (0x0107). 257 * NOTE: Upon successful completion of this command, MAC address information 258 * is returned in user specified buffer. Please interpret user specified 259 * buffer as "manage_mac_read" response. 260 * Response such as various MAC addresses are stored in HW struct (port.mac) 261 * ice_discover_dev_caps is expected to be called before this function is 262 * called. 263 */ 264 static int 265 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 266 struct ice_sq_cd *cd) 267 { 268 struct ice_aqc_manage_mac_read_resp *resp; 269 struct ice_aqc_manage_mac_read *cmd; 270 struct ice_aq_desc desc; 271 int status; 272 u16 flags; 273 u8 i; 274 275 cmd = &desc.params.mac_read; 276 277 if (buf_size < sizeof(*resp)) 278 return -EINVAL; 279 280 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 281 282 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 283 if (status) 284 return status; 285 286 resp = buf; 287 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 288 289 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 290 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 291 return -EIO; 292 } 293 294 /* A single port can report up to two (LAN and WoL) addresses */ 295 for (i = 0; i < cmd->num_addr; i++) 296 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 297 ether_addr_copy(hw->port_info->mac.lan_addr, 298 resp[i].mac_addr); 299 ether_addr_copy(hw->port_info->mac.perm_addr, 300 resp[i].mac_addr); 301 break; 302 } 303 304 return 0; 305 } 306 307 /** 308 * ice_aq_get_phy_caps - returns PHY capabilities 309 * @pi: port information structure 310 * @qual_mods: report qualified modules 311 * @report_mode: report mode capabilities 312 * @pcaps: structure for PHY capabilities to be filled 313 * @cd: pointer to command details structure or NULL 314 * 315 * Returns the various PHY capabilities supported on the Port (0x0600) 316 */ 317 int 318 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 319 struct ice_aqc_get_phy_caps_data *pcaps, 320 struct ice_sq_cd *cd) 321 { 322 struct ice_aqc_get_phy_caps *cmd; 323 u16 pcaps_size = sizeof(*pcaps); 324 struct ice_aq_desc desc; 325 const char *prefix; 326 struct ice_hw *hw; 327 int status; 328 329 cmd = &desc.params.get_phy; 330 331 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 332 return -EINVAL; 333 hw = pi->hw; 334 335 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 336 !ice_fw_supports_report_dflt_cfg(hw)) 337 return -EINVAL; 338 339 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 340 341 if (qual_mods) 342 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 343 344 cmd->param0 |= cpu_to_le16(report_mode); 345 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 346 347 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 348 349 switch (report_mode) { 350 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 351 prefix = "phy_caps_media"; 352 break; 353 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 354 prefix = "phy_caps_no_media"; 355 break; 356 case ICE_AQC_REPORT_ACTIVE_CFG: 357 prefix = "phy_caps_active"; 358 break; 359 case ICE_AQC_REPORT_DFLT_CFG: 360 prefix = "phy_caps_default"; 361 break; 362 default: 363 prefix = "phy_caps_invalid"; 364 } 365 366 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 367 le64_to_cpu(pcaps->phy_type_high), prefix); 368 369 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 370 prefix, report_mode); 371 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 372 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 373 pcaps->low_power_ctrl_an); 374 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 375 pcaps->eee_cap); 376 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 377 pcaps->eeer_value); 378 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 379 pcaps->link_fec_options); 380 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 381 prefix, pcaps->module_compliance_enforcement); 382 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 383 prefix, pcaps->extended_compliance_code); 384 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 385 pcaps->module_type[0]); 386 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 387 pcaps->module_type[1]); 388 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 389 pcaps->module_type[2]); 390 391 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 392 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 393 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 394 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 395 sizeof(pi->phy.link_info.module_type)); 396 } 397 398 return status; 399 } 400 401 /** 402 * ice_aq_get_link_topo_handle - get link topology node return status 403 * @pi: port information structure 404 * @node_type: requested node type 405 * @cd: pointer to command details structure or NULL 406 * 407 * Get link topology node return status for specified node type (0x06E0) 408 * 409 * Node type cage can be used to determine if cage is present. If AQC 410 * returns error (ENOENT), then no cage present. If no cage present, then 411 * connection type is backplane or BASE-T. 412 */ 413 static int 414 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 415 struct ice_sq_cd *cd) 416 { 417 struct ice_aqc_get_link_topo *cmd; 418 struct ice_aq_desc desc; 419 420 cmd = &desc.params.get_link_topo; 421 422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 423 424 cmd->addr.topo_params.node_type_ctx = 425 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 426 ICE_AQC_LINK_TOPO_NODE_CTX_S); 427 428 /* set node type */ 429 cmd->addr.topo_params.node_type_ctx |= 430 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 431 432 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 433 } 434 435 /** 436 * ice_aq_get_netlist_node 437 * @hw: pointer to the hw struct 438 * @cmd: get_link_topo AQ structure 439 * @node_part_number: output node part number if node found 440 * @node_handle: output node handle parameter if node found 441 * 442 * Get netlist node handle. 443 */ 444 int 445 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 446 u8 *node_part_number, u16 *node_handle) 447 { 448 struct ice_aq_desc desc; 449 450 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 451 desc.params.get_link_topo = *cmd; 452 453 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 454 return -EINTR; 455 456 if (node_handle) 457 *node_handle = 458 le16_to_cpu(desc.params.get_link_topo.addr.handle); 459 if (node_part_number) 460 *node_part_number = desc.params.get_link_topo.node_part_num; 461 462 return 0; 463 } 464 465 /** 466 * ice_find_netlist_node 467 * @hw: pointer to the hw struct 468 * @node_type: type of netlist node to look for 469 * @ctx: context of the search 470 * @node_part_number: node part number to look for 471 * @node_handle: output parameter if node found - optional 472 * 473 * Scan the netlist for a node handle of the given node type and part number. 474 * 475 * If node_handle is non-NULL it will be modified on function exit. It is only 476 * valid if the function returns zero, and should be ignored on any non-zero 477 * return value. 478 * 479 * Return: 480 * * 0 if the node is found, 481 * * -ENOENT if no handle was found, 482 * * negative error code on failure to access the AQ. 483 */ 484 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 485 u8 node_part_number, u16 *node_handle) 486 { 487 u8 idx; 488 489 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 490 struct ice_aqc_get_link_topo cmd = {}; 491 u8 rec_node_part_number; 492 int status; 493 494 cmd.addr.topo_params.node_type_ctx = 495 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 496 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 497 cmd.addr.topo_params.index = idx; 498 499 status = ice_aq_get_netlist_node(hw, &cmd, 500 &rec_node_part_number, 501 node_handle); 502 if (status) 503 return status; 504 505 if (rec_node_part_number == node_part_number) 506 return 0; 507 } 508 509 return -ENOENT; 510 } 511 512 /** 513 * ice_is_media_cage_present 514 * @pi: port information structure 515 * 516 * Returns true if media cage is present, else false. If no cage, then 517 * media type is backplane or BASE-T. 518 */ 519 static bool ice_is_media_cage_present(struct ice_port_info *pi) 520 { 521 /* Node type cage can be used to determine if cage is present. If AQC 522 * returns error (ENOENT), then no cage present. If no cage present then 523 * connection type is backplane or BASE-T. 524 */ 525 return !ice_aq_get_link_topo_handle(pi, 526 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 527 NULL); 528 } 529 530 /** 531 * ice_get_media_type - Gets media type 532 * @pi: port information structure 533 */ 534 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 535 { 536 struct ice_link_status *hw_link_info; 537 538 if (!pi) 539 return ICE_MEDIA_UNKNOWN; 540 541 hw_link_info = &pi->phy.link_info; 542 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 543 /* If more than one media type is selected, report unknown */ 544 return ICE_MEDIA_UNKNOWN; 545 546 if (hw_link_info->phy_type_low) { 547 /* 1G SGMII is a special case where some DA cable PHYs 548 * may show this as an option when it really shouldn't 549 * be since SGMII is meant to be between a MAC and a PHY 550 * in a backplane. Try to detect this case and handle it 551 */ 552 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 553 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 554 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 555 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 556 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 557 return ICE_MEDIA_DA; 558 559 switch (hw_link_info->phy_type_low) { 560 case ICE_PHY_TYPE_LOW_1000BASE_SX: 561 case ICE_PHY_TYPE_LOW_1000BASE_LX: 562 case ICE_PHY_TYPE_LOW_10GBASE_SR: 563 case ICE_PHY_TYPE_LOW_10GBASE_LR: 564 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 565 case ICE_PHY_TYPE_LOW_25GBASE_SR: 566 case ICE_PHY_TYPE_LOW_25GBASE_LR: 567 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 568 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 569 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 570 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 571 case ICE_PHY_TYPE_LOW_50GBASE_SR: 572 case ICE_PHY_TYPE_LOW_50GBASE_FR: 573 case ICE_PHY_TYPE_LOW_50GBASE_LR: 574 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 575 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 577 case ICE_PHY_TYPE_LOW_100GBASE_DR: 578 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 579 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 582 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 583 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 584 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 585 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 586 return ICE_MEDIA_FIBER; 587 case ICE_PHY_TYPE_LOW_100BASE_TX: 588 case ICE_PHY_TYPE_LOW_1000BASE_T: 589 case ICE_PHY_TYPE_LOW_2500BASE_T: 590 case ICE_PHY_TYPE_LOW_5GBASE_T: 591 case ICE_PHY_TYPE_LOW_10GBASE_T: 592 case ICE_PHY_TYPE_LOW_25GBASE_T: 593 return ICE_MEDIA_BASET; 594 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 595 case ICE_PHY_TYPE_LOW_25GBASE_CR: 596 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 597 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 598 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 599 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 600 case ICE_PHY_TYPE_LOW_50GBASE_CP: 601 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 602 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 603 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 604 return ICE_MEDIA_DA; 605 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 606 case ICE_PHY_TYPE_LOW_40G_XLAUI: 607 case ICE_PHY_TYPE_LOW_50G_LAUI2: 608 case ICE_PHY_TYPE_LOW_50G_AUI2: 609 case ICE_PHY_TYPE_LOW_50G_AUI1: 610 case ICE_PHY_TYPE_LOW_100G_AUI4: 611 case ICE_PHY_TYPE_LOW_100G_CAUI4: 612 if (ice_is_media_cage_present(pi)) 613 return ICE_MEDIA_DA; 614 fallthrough; 615 case ICE_PHY_TYPE_LOW_1000BASE_KX: 616 case ICE_PHY_TYPE_LOW_2500BASE_KX: 617 case ICE_PHY_TYPE_LOW_2500BASE_X: 618 case ICE_PHY_TYPE_LOW_5GBASE_KR: 619 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 620 case ICE_PHY_TYPE_LOW_25GBASE_KR: 621 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 622 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 623 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 624 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 625 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 626 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 627 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 628 return ICE_MEDIA_BACKPLANE; 629 } 630 } else { 631 switch (hw_link_info->phy_type_high) { 632 case ICE_PHY_TYPE_HIGH_100G_AUI2: 633 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 634 if (ice_is_media_cage_present(pi)) 635 return ICE_MEDIA_DA; 636 fallthrough; 637 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 640 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 641 return ICE_MEDIA_FIBER; 642 } 643 } 644 return ICE_MEDIA_UNKNOWN; 645 } 646 647 /** 648 * ice_get_link_status_datalen 649 * @hw: pointer to the HW struct 650 * 651 * Returns datalength for the Get Link Status AQ command, which is bigger for 652 * newer adapter families handled by ice driver. 653 */ 654 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 655 { 656 switch (hw->mac_type) { 657 case ICE_MAC_E830: 658 return ICE_AQC_LS_DATA_SIZE_V2; 659 case ICE_MAC_E810: 660 default: 661 return ICE_AQC_LS_DATA_SIZE_V1; 662 } 663 } 664 665 /** 666 * ice_aq_get_link_info 667 * @pi: port information structure 668 * @ena_lse: enable/disable LinkStatusEvent reporting 669 * @link: pointer to link status structure - optional 670 * @cd: pointer to command details structure or NULL 671 * 672 * Get Link Status (0x607). Returns the link status of the adapter. 673 */ 674 int 675 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 676 struct ice_link_status *link, struct ice_sq_cd *cd) 677 { 678 struct ice_aqc_get_link_status_data link_data = { 0 }; 679 struct ice_aqc_get_link_status *resp; 680 struct ice_link_status *li_old, *li; 681 enum ice_media_type *hw_media_type; 682 struct ice_fc_info *hw_fc_info; 683 bool tx_pause, rx_pause; 684 struct ice_aq_desc desc; 685 struct ice_hw *hw; 686 u16 cmd_flags; 687 int status; 688 689 if (!pi) 690 return -EINVAL; 691 hw = pi->hw; 692 li_old = &pi->phy.link_info_old; 693 hw_media_type = &pi->phy.media_type; 694 li = &pi->phy.link_info; 695 hw_fc_info = &pi->fc; 696 697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 698 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 699 resp = &desc.params.get_link_status; 700 resp->cmd_flags = cpu_to_le16(cmd_flags); 701 resp->lport_num = pi->lport; 702 703 status = ice_aq_send_cmd(hw, &desc, &link_data, 704 ice_get_link_status_datalen(hw), cd); 705 if (status) 706 return status; 707 708 /* save off old link status information */ 709 *li_old = *li; 710 711 /* update current link status information */ 712 li->link_speed = le16_to_cpu(link_data.link_speed); 713 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 714 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 715 *hw_media_type = ice_get_media_type(pi); 716 li->link_info = link_data.link_info; 717 li->link_cfg_err = link_data.link_cfg_err; 718 li->an_info = link_data.an_info; 719 li->ext_info = link_data.ext_info; 720 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 721 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 722 li->topo_media_conflict = link_data.topo_media_conflict; 723 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 724 ICE_AQ_CFG_PACING_TYPE_M); 725 726 /* update fc info */ 727 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 728 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 729 if (tx_pause && rx_pause) 730 hw_fc_info->current_mode = ICE_FC_FULL; 731 else if (tx_pause) 732 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 733 else if (rx_pause) 734 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 735 else 736 hw_fc_info->current_mode = ICE_FC_NONE; 737 738 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 739 740 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 741 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 742 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 743 (unsigned long long)li->phy_type_low); 744 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 745 (unsigned long long)li->phy_type_high); 746 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 747 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 748 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 749 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 750 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 751 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 752 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 753 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 754 li->max_frame_size); 755 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 756 757 /* save link status information */ 758 if (link) 759 *link = *li; 760 761 /* flag cleared so calling functions don't call AQ again */ 762 pi->phy.get_link_info = false; 763 764 return 0; 765 } 766 767 /** 768 * ice_fill_tx_timer_and_fc_thresh 769 * @hw: pointer to the HW struct 770 * @cmd: pointer to MAC cfg structure 771 * 772 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 773 * descriptor 774 */ 775 static void 776 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 777 struct ice_aqc_set_mac_cfg *cmd) 778 { 779 u32 val, fc_thres_m; 780 781 /* We read back the transmit timer and FC threshold value of 782 * LFC. Thus, we will use index = 783 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 784 * 785 * Also, because we are operating on transmit timer and FC 786 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 787 */ 788 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 789 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 790 791 if (hw->mac_type == ICE_MAC_E830) { 792 /* Retrieve the transmit timer */ 793 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 794 cmd->tx_tmr_value = 795 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 796 797 /* Retrieve the fc threshold */ 798 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 799 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 800 } else { 801 /* Retrieve the transmit timer */ 802 val = rd32(hw, 803 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, 806 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 807 808 /* Retrieve the fc threshold */ 809 val = rd32(hw, 810 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 811 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 812 } 813 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 814 } 815 816 /** 817 * ice_aq_set_mac_cfg 818 * @hw: pointer to the HW struct 819 * @max_frame_size: Maximum Frame Size to be supported 820 * @cd: pointer to command details structure or NULL 821 * 822 * Set MAC configuration (0x0603) 823 */ 824 int 825 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 826 { 827 struct ice_aqc_set_mac_cfg *cmd; 828 struct ice_aq_desc desc; 829 830 cmd = &desc.params.set_mac_cfg; 831 832 if (max_frame_size == 0) 833 return -EINVAL; 834 835 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 836 837 cmd->max_frame_size = cpu_to_le16(max_frame_size); 838 839 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 840 841 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 842 } 843 844 /** 845 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 846 * @hw: pointer to the HW struct 847 */ 848 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 849 { 850 struct ice_switch_info *sw; 851 int status; 852 853 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 854 sizeof(*hw->switch_info), GFP_KERNEL); 855 sw = hw->switch_info; 856 857 if (!sw) 858 return -ENOMEM; 859 860 INIT_LIST_HEAD(&sw->vsi_list_map_head); 861 sw->prof_res_bm_init = 0; 862 863 /* Initialize recipe count with default recipes read from NVM */ 864 sw->recp_cnt = ICE_SW_LKUP_LAST; 865 866 status = ice_init_def_sw_recp(hw); 867 if (status) { 868 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 869 return status; 870 } 871 return 0; 872 } 873 874 /** 875 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 876 * @hw: pointer to the HW struct 877 */ 878 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 879 { 880 struct ice_switch_info *sw = hw->switch_info; 881 struct ice_vsi_list_map_info *v_pos_map; 882 struct ice_vsi_list_map_info *v_tmp_map; 883 struct ice_sw_recipe *recps; 884 u8 i; 885 886 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 887 list_entry) { 888 list_del(&v_pos_map->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 890 } 891 recps = sw->recp_list; 892 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 893 recps[i].root_rid = i; 894 895 if (recps[i].adv_rule) { 896 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 897 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 898 899 mutex_destroy(&recps[i].filt_rule_lock); 900 list_for_each_entry_safe(lst_itr, tmp_entry, 901 &recps[i].filt_rules, 902 list_entry) { 903 list_del(&lst_itr->list_entry); 904 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 905 devm_kfree(ice_hw_to_dev(hw), lst_itr); 906 } 907 } else { 908 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 909 910 mutex_destroy(&recps[i].filt_rule_lock); 911 list_for_each_entry_safe(lst_itr, tmp_entry, 912 &recps[i].filt_rules, 913 list_entry) { 914 list_del(&lst_itr->list_entry); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } 918 } 919 ice_rm_all_sw_replay_rule_info(hw); 920 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 921 devm_kfree(ice_hw_to_dev(hw), sw); 922 } 923 924 /** 925 * ice_get_itr_intrl_gran 926 * @hw: pointer to the HW struct 927 * 928 * Determines the ITR/INTRL granularities based on the maximum aggregate 929 * bandwidth according to the device's configuration during power-on. 930 */ 931 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 932 { 933 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 934 rd32(hw, GL_PWR_MODE_CTL)); 935 936 switch (max_agg_bw) { 937 case ICE_MAX_AGG_BW_200G: 938 case ICE_MAX_AGG_BW_100G: 939 case ICE_MAX_AGG_BW_50G: 940 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 941 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 942 break; 943 case ICE_MAX_AGG_BW_25G: 944 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 945 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 946 break; 947 } 948 } 949 950 /** 951 * ice_wait_for_fw - wait for full FW readiness 952 * @hw: pointer to the hardware structure 953 * @timeout: milliseconds that can elapse before timing out 954 * 955 * Return: 0 on success, -ETIMEDOUT on timeout. 956 */ 957 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 958 { 959 int fw_loading; 960 u32 elapsed = 0; 961 962 while (elapsed <= timeout) { 963 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 964 965 /* firmware was not yet loaded, we have to wait more */ 966 if (fw_loading) { 967 elapsed += 100; 968 msleep(100); 969 continue; 970 } 971 return 0; 972 } 973 974 return -ETIMEDOUT; 975 } 976 977 /** 978 * ice_init_hw - main hardware initialization routine 979 * @hw: pointer to the hardware structure 980 */ 981 int ice_init_hw(struct ice_hw *hw) 982 { 983 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 984 void *mac_buf __free(kfree) = NULL; 985 u16 mac_buf_len; 986 int status; 987 988 /* Set MAC type based on DeviceID */ 989 status = ice_set_mac_type(hw); 990 if (status) 991 return status; 992 993 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 994 995 status = ice_reset(hw, ICE_RESET_PFR); 996 if (status) 997 return status; 998 999 ice_get_itr_intrl_gran(hw); 1000 1001 status = ice_create_all_ctrlq(hw); 1002 if (status) 1003 goto err_unroll_cqinit; 1004 1005 status = ice_fwlog_init(hw); 1006 if (status) 1007 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1008 status); 1009 1010 status = ice_clear_pf_cfg(hw); 1011 if (status) 1012 goto err_unroll_cqinit; 1013 1014 /* Set bit to enable Flow Director filters */ 1015 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1016 INIT_LIST_HEAD(&hw->fdir_list_head); 1017 1018 ice_clear_pxe_mode(hw); 1019 1020 status = ice_init_nvm(hw); 1021 if (status) 1022 goto err_unroll_cqinit; 1023 1024 status = ice_get_caps(hw); 1025 if (status) 1026 goto err_unroll_cqinit; 1027 1028 if (!hw->port_info) 1029 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1030 sizeof(*hw->port_info), 1031 GFP_KERNEL); 1032 if (!hw->port_info) { 1033 status = -ENOMEM; 1034 goto err_unroll_cqinit; 1035 } 1036 1037 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1038 /* set the back pointer to HW */ 1039 hw->port_info->hw = hw; 1040 1041 /* Initialize port_info struct with switch configuration data */ 1042 status = ice_get_initial_sw_cfg(hw); 1043 if (status) 1044 goto err_unroll_alloc; 1045 1046 hw->evb_veb = true; 1047 1048 /* init xarray for identifying scheduling nodes uniquely */ 1049 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1050 1051 /* Query the allocated resources for Tx scheduler */ 1052 status = ice_sched_query_res_alloc(hw); 1053 if (status) { 1054 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1055 goto err_unroll_alloc; 1056 } 1057 ice_sched_get_psm_clk_freq(hw); 1058 1059 /* Initialize port_info struct with scheduler data */ 1060 status = ice_sched_init_port(hw->port_info); 1061 if (status) 1062 goto err_unroll_sched; 1063 1064 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1065 if (!pcaps) { 1066 status = -ENOMEM; 1067 goto err_unroll_sched; 1068 } 1069 1070 /* Initialize port_info struct with PHY capabilities */ 1071 status = ice_aq_get_phy_caps(hw->port_info, false, 1072 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1073 NULL); 1074 if (status) 1075 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1076 status); 1077 1078 /* Initialize port_info struct with link information */ 1079 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1080 if (status) 1081 goto err_unroll_sched; 1082 1083 /* need a valid SW entry point to build a Tx tree */ 1084 if (!hw->sw_entry_point_layer) { 1085 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1086 status = -EIO; 1087 goto err_unroll_sched; 1088 } 1089 INIT_LIST_HEAD(&hw->agg_list); 1090 /* Initialize max burst size */ 1091 if (!hw->max_burst_size) 1092 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1093 1094 status = ice_init_fltr_mgmt_struct(hw); 1095 if (status) 1096 goto err_unroll_sched; 1097 1098 /* Get MAC information */ 1099 /* A single port can report up to two (LAN and WoL) addresses */ 1100 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1101 GFP_KERNEL); 1102 if (!mac_buf) { 1103 status = -ENOMEM; 1104 goto err_unroll_fltr_mgmt_struct; 1105 } 1106 1107 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1108 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1109 1110 if (status) 1111 goto err_unroll_fltr_mgmt_struct; 1112 /* enable jumbo frame support at MAC level */ 1113 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1114 if (status) 1115 goto err_unroll_fltr_mgmt_struct; 1116 /* Obtain counter base index which would be used by flow director */ 1117 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1118 if (status) 1119 goto err_unroll_fltr_mgmt_struct; 1120 status = ice_init_hw_tbls(hw); 1121 if (status) 1122 goto err_unroll_fltr_mgmt_struct; 1123 mutex_init(&hw->tnl_lock); 1124 ice_init_chk_recipe_reuse_support(hw); 1125 1126 /* Some cards require longer initialization times 1127 * due to necessity of loading FW from an external source. 1128 * This can take even half a minute. 1129 */ 1130 if (ice_is_pf_c827(hw)) { 1131 status = ice_wait_for_fw(hw, 30000); 1132 if (status) { 1133 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1134 goto err_unroll_fltr_mgmt_struct; 1135 } 1136 } 1137 1138 hw->lane_num = ice_get_phy_lane_number(hw); 1139 1140 return 0; 1141 err_unroll_fltr_mgmt_struct: 1142 ice_cleanup_fltr_mgmt_struct(hw); 1143 err_unroll_sched: 1144 ice_sched_cleanup_all(hw); 1145 err_unroll_alloc: 1146 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1147 err_unroll_cqinit: 1148 ice_destroy_all_ctrlq(hw); 1149 return status; 1150 } 1151 1152 /** 1153 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1154 * @hw: pointer to the hardware structure 1155 * 1156 * This should be called only during nominal operation, not as a result of 1157 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1158 * applicable initializations if it fails for any reason. 1159 */ 1160 void ice_deinit_hw(struct ice_hw *hw) 1161 { 1162 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1163 ice_cleanup_fltr_mgmt_struct(hw); 1164 1165 ice_sched_cleanup_all(hw); 1166 ice_sched_clear_agg(hw); 1167 ice_free_seg(hw); 1168 ice_free_hw_tbls(hw); 1169 mutex_destroy(&hw->tnl_lock); 1170 1171 ice_fwlog_deinit(hw); 1172 ice_destroy_all_ctrlq(hw); 1173 1174 /* Clear VSI contexts if not already cleared */ 1175 ice_clear_all_vsi_ctx(hw); 1176 } 1177 1178 /** 1179 * ice_check_reset - Check to see if a global reset is complete 1180 * @hw: pointer to the hardware structure 1181 */ 1182 int ice_check_reset(struct ice_hw *hw) 1183 { 1184 u32 cnt, reg = 0, grst_timeout, uld_mask; 1185 1186 /* Poll for Device Active state in case a recent CORER, GLOBR, 1187 * or EMPR has occurred. The grst delay value is in 100ms units. 1188 * Add 1sec for outstanding AQ commands that can take a long time. 1189 */ 1190 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1191 rd32(hw, GLGEN_RSTCTL)) + 10; 1192 1193 for (cnt = 0; cnt < grst_timeout; cnt++) { 1194 mdelay(100); 1195 reg = rd32(hw, GLGEN_RSTAT); 1196 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1197 break; 1198 } 1199 1200 if (cnt == grst_timeout) { 1201 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1202 return -EIO; 1203 } 1204 1205 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1206 GLNVM_ULD_PCIER_DONE_1_M |\ 1207 GLNVM_ULD_CORER_DONE_M |\ 1208 GLNVM_ULD_GLOBR_DONE_M |\ 1209 GLNVM_ULD_POR_DONE_M |\ 1210 GLNVM_ULD_POR_DONE_1_M |\ 1211 GLNVM_ULD_PCIER_DONE_2_M) 1212 1213 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1214 GLNVM_ULD_PE_DONE_M : 0); 1215 1216 /* Device is Active; check Global Reset processes are done */ 1217 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1218 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1219 if (reg == uld_mask) { 1220 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1221 break; 1222 } 1223 mdelay(10); 1224 } 1225 1226 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1227 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1228 reg); 1229 return -EIO; 1230 } 1231 1232 return 0; 1233 } 1234 1235 /** 1236 * ice_pf_reset - Reset the PF 1237 * @hw: pointer to the hardware structure 1238 * 1239 * If a global reset has been triggered, this function checks 1240 * for its completion and then issues the PF reset 1241 */ 1242 static int ice_pf_reset(struct ice_hw *hw) 1243 { 1244 u32 cnt, reg; 1245 1246 /* If at function entry a global reset was already in progress, i.e. 1247 * state is not 'device active' or any of the reset done bits are not 1248 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1249 * global reset is done. 1250 */ 1251 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1252 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1253 /* poll on global reset currently in progress until done */ 1254 if (ice_check_reset(hw)) 1255 return -EIO; 1256 1257 return 0; 1258 } 1259 1260 /* Reset the PF */ 1261 reg = rd32(hw, PFGEN_CTRL); 1262 1263 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1264 1265 /* Wait for the PFR to complete. The wait time is the global config lock 1266 * timeout plus the PFR timeout which will account for a possible reset 1267 * that is occurring during a download package operation. 1268 */ 1269 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1270 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1271 reg = rd32(hw, PFGEN_CTRL); 1272 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1273 break; 1274 1275 mdelay(1); 1276 } 1277 1278 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1279 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1280 return -EIO; 1281 } 1282 1283 return 0; 1284 } 1285 1286 /** 1287 * ice_reset - Perform different types of reset 1288 * @hw: pointer to the hardware structure 1289 * @req: reset request 1290 * 1291 * This function triggers a reset as specified by the req parameter. 1292 * 1293 * Note: 1294 * If anything other than a PF reset is triggered, PXE mode is restored. 1295 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1296 * interface has been restored in the rebuild flow. 1297 */ 1298 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1299 { 1300 u32 val = 0; 1301 1302 switch (req) { 1303 case ICE_RESET_PFR: 1304 return ice_pf_reset(hw); 1305 case ICE_RESET_CORER: 1306 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1307 val = GLGEN_RTRIG_CORER_M; 1308 break; 1309 case ICE_RESET_GLOBR: 1310 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1311 val = GLGEN_RTRIG_GLOBR_M; 1312 break; 1313 default: 1314 return -EINVAL; 1315 } 1316 1317 val |= rd32(hw, GLGEN_RTRIG); 1318 wr32(hw, GLGEN_RTRIG, val); 1319 ice_flush(hw); 1320 1321 /* wait for the FW to be ready */ 1322 return ice_check_reset(hw); 1323 } 1324 1325 /** 1326 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1327 * @hw: pointer to the hardware structure 1328 * @rxq_ctx: pointer to the packed Rx queue context 1329 * @rxq_index: the index of the Rx queue 1330 */ 1331 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1332 const ice_rxq_ctx_buf_t *rxq_ctx, 1333 u32 rxq_index) 1334 { 1335 /* Copy each dword separately to HW */ 1336 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1337 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1338 1339 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1340 1341 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1342 } 1343 } 1344 1345 /** 1346 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1347 * @hw: pointer to the hardware structure 1348 * @rxq_ctx: pointer to the packed Rx queue context 1349 * @rxq_index: the index of the Rx queue 1350 */ 1351 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1352 ice_rxq_ctx_buf_t *rxq_ctx, 1353 u32 rxq_index) 1354 { 1355 u32 *ctx = (u32 *)rxq_ctx; 1356 1357 /* Copy each dword separately from HW */ 1358 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1359 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1360 1361 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1362 } 1363 } 1364 1365 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1366 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1367 1368 /* LAN Rx Queue Context */ 1369 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1370 /* Field Width LSB */ 1371 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1372 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1373 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1374 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1375 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1376 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1377 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1378 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1379 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1380 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1381 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1382 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1383 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1384 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1385 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1386 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1387 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1388 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1389 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1390 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1391 }; 1392 1393 /** 1394 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1395 * @ctx: the Rx queue context to pack 1396 * @buf: the HW buffer to pack into 1397 * 1398 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1399 * bit-packed HW layout. 1400 */ 1401 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1402 ice_rxq_ctx_buf_t *buf) 1403 { 1404 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1405 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1406 } 1407 1408 /** 1409 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1410 * @buf: the HW buffer to unpack from 1411 * @ctx: the Rx queue context to unpack 1412 * 1413 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1414 * structure. 1415 */ 1416 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1417 struct ice_rlan_ctx *ctx) 1418 { 1419 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1420 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1421 } 1422 1423 /** 1424 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1425 * @hw: pointer to the hardware structure 1426 * @rlan_ctx: pointer to the unpacked Rx queue context 1427 * @rxq_index: the index of the Rx queue 1428 * 1429 * Pack the sparse Rx Queue context into dense hardware format and write it 1430 * into the HW register space. 1431 * 1432 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1433 */ 1434 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1435 u32 rxq_index) 1436 { 1437 ice_rxq_ctx_buf_t buf = {}; 1438 1439 if (rxq_index > QRX_CTRL_MAX_INDEX) 1440 return -EINVAL; 1441 1442 ice_pack_rxq_ctx(rlan_ctx, &buf); 1443 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1444 1445 return 0; 1446 } 1447 1448 /** 1449 * ice_read_rxq_ctx - Read Rx queue context from HW 1450 * @hw: pointer to the hardware structure 1451 * @rlan_ctx: pointer to the Rx queue context 1452 * @rxq_index: the index of the Rx queue 1453 * 1454 * Read the Rx queue context from the hardware registers, and unpack it into 1455 * the sparse Rx queue context structure. 1456 * 1457 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1458 */ 1459 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1460 u32 rxq_index) 1461 { 1462 ice_rxq_ctx_buf_t buf = {}; 1463 1464 if (rxq_index > QRX_CTRL_MAX_INDEX) 1465 return -EINVAL; 1466 1467 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1468 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1469 1470 return 0; 1471 } 1472 1473 /* LAN Tx Queue Context */ 1474 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1475 /* Field Width LSB */ 1476 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1477 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1478 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1479 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1480 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1481 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1482 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1483 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1484 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1485 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1486 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1487 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1488 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1489 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1490 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1491 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1492 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1493 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1494 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1495 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1496 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1497 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1498 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1499 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1500 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1501 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1502 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1503 }; 1504 1505 /** 1506 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1507 * @ctx: the Tx queue context to pack 1508 * @buf: the Admin Queue HW buffer to pack into 1509 * 1510 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1511 * bit-packed Admin Queue layout. 1512 */ 1513 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1514 { 1515 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1516 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1517 } 1518 1519 /** 1520 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1521 * @ctx: the Tx queue context to pack 1522 * @buf: the HW buffer to pack into 1523 * 1524 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1525 * bit-packed HW layout, including the internal data portion. 1526 */ 1527 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1528 ice_txq_ctx_buf_full_t *buf) 1529 { 1530 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1531 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1532 } 1533 1534 /** 1535 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1536 * @buf: the HW buffer to unpack from 1537 * @ctx: the Tx queue context to unpack 1538 * 1539 * Unpack the Tx queue context from the HW buffer (including the full internal 1540 * state) into the CPU-friendly structure. 1541 */ 1542 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1543 struct ice_tlan_ctx *ctx) 1544 { 1545 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1546 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1547 } 1548 1549 /** 1550 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1551 * @hw: pointer to the hardware structure 1552 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1553 * @txq_index: the index of the Tx queue 1554 * 1555 * Copy Tx Queue context from HW register space to dense structure 1556 */ 1557 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1558 ice_txq_ctx_buf_full_t *txq_ctx, 1559 u32 txq_index) 1560 { 1561 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1562 u32 *ctx = (u32 *)txq_ctx; 1563 u32 txq_base, reg; 1564 1565 /* Get Tx queue base within card space */ 1566 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1567 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1568 1569 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1570 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1571 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1572 txq_base + txq_index) | 1573 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1574 1575 /* Prevent other PFs on the same adapter from accessing the Tx queue 1576 * context interface concurrently. 1577 */ 1578 spin_lock(&pf->adapter->txq_ctx_lock); 1579 1580 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1581 ice_flush(hw); 1582 1583 /* Copy each dword separately from HW */ 1584 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1585 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1586 1587 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1588 } 1589 1590 spin_unlock(&pf->adapter->txq_ctx_lock); 1591 } 1592 1593 /** 1594 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1595 * @hw: pointer to the hardware structure 1596 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1597 * @txq_index: the index of the Tx queue 1598 */ 1599 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1600 const ice_txq_ctx_buf_full_t *txq_ctx, 1601 u32 txq_index) 1602 { 1603 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1604 u32 txq_base, reg; 1605 1606 /* Get Tx queue base within card space */ 1607 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1608 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1609 1610 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1611 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1612 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1613 txq_base + txq_index) | 1614 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1615 1616 /* Prevent other PFs on the same adapter from accessing the Tx queue 1617 * context interface concurrently. 1618 */ 1619 spin_lock(&pf->adapter->txq_ctx_lock); 1620 1621 /* Copy each dword separately to HW */ 1622 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1623 u32 ctx = ((const u32 *)txq_ctx)[i]; 1624 1625 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1626 1627 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1628 } 1629 1630 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1631 ice_flush(hw); 1632 1633 spin_unlock(&pf->adapter->txq_ctx_lock); 1634 } 1635 1636 /** 1637 * ice_read_txq_ctx - Read Tx queue context from HW 1638 * @hw: pointer to the hardware structure 1639 * @tlan_ctx: pointer to the Tx queue context 1640 * @txq_index: the index of the Tx queue 1641 * 1642 * Read the Tx queue context from the HW registers, then unpack it into the 1643 * ice_tlan_ctx structure for use. 1644 * 1645 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1646 */ 1647 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1648 u32 txq_index) 1649 { 1650 ice_txq_ctx_buf_full_t buf = {}; 1651 1652 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1653 return -EINVAL; 1654 1655 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1656 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1657 1658 return 0; 1659 } 1660 1661 /** 1662 * ice_write_txq_ctx - Write Tx queue context to HW 1663 * @hw: pointer to the hardware structure 1664 * @tlan_ctx: pointer to the Tx queue context 1665 * @txq_index: the index of the Tx queue 1666 * 1667 * Pack the Tx queue context into the dense HW layout, then write it into the 1668 * HW registers. 1669 * 1670 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1671 */ 1672 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1673 u32 txq_index) 1674 { 1675 ice_txq_ctx_buf_full_t buf = {}; 1676 1677 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1678 return -EINVAL; 1679 1680 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1681 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1682 1683 return 0; 1684 } 1685 1686 /* Sideband Queue command wrappers */ 1687 1688 /** 1689 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1690 * @hw: pointer to the HW struct 1691 * @desc: descriptor describing the command 1692 * @buf: buffer to use for indirect commands (NULL for direct commands) 1693 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1694 * @cd: pointer to command details structure 1695 */ 1696 static int 1697 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1698 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1699 { 1700 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1701 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1702 } 1703 1704 /** 1705 * ice_sbq_rw_reg - Fill Sideband Queue command 1706 * @hw: pointer to the HW struct 1707 * @in: message info to be filled in descriptor 1708 * @flags: control queue descriptor flags 1709 */ 1710 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1711 { 1712 struct ice_sbq_cmd_desc desc = {0}; 1713 struct ice_sbq_msg_req msg = {0}; 1714 u16 msg_len; 1715 int status; 1716 1717 msg_len = sizeof(msg); 1718 1719 msg.dest_dev = in->dest_dev; 1720 msg.opcode = in->opcode; 1721 msg.flags = ICE_SBQ_MSG_FLAGS; 1722 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1723 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1724 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1725 1726 if (in->opcode) 1727 msg.data = cpu_to_le32(in->data); 1728 else 1729 /* data read comes back in completion, so shorten the struct by 1730 * sizeof(msg.data) 1731 */ 1732 msg_len -= sizeof(msg.data); 1733 1734 desc.flags = cpu_to_le16(flags); 1735 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1736 desc.param0.cmd_len = cpu_to_le16(msg_len); 1737 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1738 if (!status && !in->opcode) 1739 in->data = le32_to_cpu 1740 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1741 return status; 1742 } 1743 1744 /* FW Admin Queue command wrappers */ 1745 1746 /* Software lock/mutex that is meant to be held while the Global Config Lock 1747 * in firmware is acquired by the software to prevent most (but not all) types 1748 * of AQ commands from being sent to FW 1749 */ 1750 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1751 1752 /** 1753 * ice_should_retry_sq_send_cmd 1754 * @opcode: AQ opcode 1755 * 1756 * Decide if we should retry the send command routine for the ATQ, depending 1757 * on the opcode. 1758 */ 1759 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1760 { 1761 switch (opcode) { 1762 case ice_aqc_opc_get_link_topo: 1763 case ice_aqc_opc_lldp_stop: 1764 case ice_aqc_opc_lldp_start: 1765 case ice_aqc_opc_lldp_filter_ctrl: 1766 return true; 1767 } 1768 1769 return false; 1770 } 1771 1772 /** 1773 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1774 * @hw: pointer to the HW struct 1775 * @cq: pointer to the specific Control queue 1776 * @desc: prefilled descriptor describing the command 1777 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1778 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1779 * @cd: pointer to command details structure 1780 * 1781 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1782 * Queue if the EBUSY AQ error is returned. 1783 */ 1784 static int 1785 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1786 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1787 struct ice_sq_cd *cd) 1788 { 1789 struct ice_aq_desc desc_cpy; 1790 bool is_cmd_for_retry; 1791 u8 idx = 0; 1792 u16 opcode; 1793 int status; 1794 1795 opcode = le16_to_cpu(desc->opcode); 1796 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1797 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1798 1799 if (is_cmd_for_retry) { 1800 /* All retryable cmds are direct, without buf. */ 1801 WARN_ON(buf); 1802 1803 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1804 } 1805 1806 do { 1807 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1808 1809 if (!is_cmd_for_retry || !status || 1810 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1811 break; 1812 1813 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1814 1815 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1816 1817 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1818 1819 return status; 1820 } 1821 1822 /** 1823 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1824 * @hw: pointer to the HW struct 1825 * @desc: descriptor describing the command 1826 * @buf: buffer to use for indirect commands (NULL for direct commands) 1827 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1828 * @cd: pointer to command details structure 1829 * 1830 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1831 */ 1832 int 1833 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1834 u16 buf_size, struct ice_sq_cd *cd) 1835 { 1836 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1837 bool lock_acquired = false; 1838 int status; 1839 1840 /* When a package download is in process (i.e. when the firmware's 1841 * Global Configuration Lock resource is held), only the Download 1842 * Package, Get Version, Get Package Info List, Upload Section, 1843 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1844 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1845 * Recipes to Profile Association, and Release Resource (with resource 1846 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1847 * must block until the package download completes and the Global Config 1848 * Lock is released. See also ice_acquire_global_cfg_lock(). 1849 */ 1850 switch (le16_to_cpu(desc->opcode)) { 1851 case ice_aqc_opc_download_pkg: 1852 case ice_aqc_opc_get_pkg_info_list: 1853 case ice_aqc_opc_get_ver: 1854 case ice_aqc_opc_upload_section: 1855 case ice_aqc_opc_update_pkg: 1856 case ice_aqc_opc_set_port_params: 1857 case ice_aqc_opc_get_vlan_mode_parameters: 1858 case ice_aqc_opc_set_vlan_mode_parameters: 1859 case ice_aqc_opc_set_tx_topo: 1860 case ice_aqc_opc_get_tx_topo: 1861 case ice_aqc_opc_add_recipe: 1862 case ice_aqc_opc_recipe_to_profile: 1863 case ice_aqc_opc_get_recipe: 1864 case ice_aqc_opc_get_recipe_to_profile: 1865 break; 1866 case ice_aqc_opc_release_res: 1867 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1868 break; 1869 fallthrough; 1870 default: 1871 mutex_lock(&ice_global_cfg_lock_sw); 1872 lock_acquired = true; 1873 break; 1874 } 1875 1876 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1877 if (lock_acquired) 1878 mutex_unlock(&ice_global_cfg_lock_sw); 1879 1880 return status; 1881 } 1882 1883 /** 1884 * ice_aq_get_fw_ver 1885 * @hw: pointer to the HW struct 1886 * @cd: pointer to command details structure or NULL 1887 * 1888 * Get the firmware version (0x0001) from the admin queue commands 1889 */ 1890 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1891 { 1892 struct ice_aqc_get_ver *resp; 1893 struct ice_aq_desc desc; 1894 int status; 1895 1896 resp = &desc.params.get_ver; 1897 1898 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1899 1900 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1901 1902 if (!status) { 1903 hw->fw_branch = resp->fw_branch; 1904 hw->fw_maj_ver = resp->fw_major; 1905 hw->fw_min_ver = resp->fw_minor; 1906 hw->fw_patch = resp->fw_patch; 1907 hw->fw_build = le32_to_cpu(resp->fw_build); 1908 hw->api_branch = resp->api_branch; 1909 hw->api_maj_ver = resp->api_major; 1910 hw->api_min_ver = resp->api_minor; 1911 hw->api_patch = resp->api_patch; 1912 } 1913 1914 return status; 1915 } 1916 1917 /** 1918 * ice_aq_send_driver_ver 1919 * @hw: pointer to the HW struct 1920 * @dv: driver's major, minor version 1921 * @cd: pointer to command details structure or NULL 1922 * 1923 * Send the driver version (0x0002) to the firmware 1924 */ 1925 int 1926 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1927 struct ice_sq_cd *cd) 1928 { 1929 struct ice_aqc_driver_ver *cmd; 1930 struct ice_aq_desc desc; 1931 u16 len; 1932 1933 cmd = &desc.params.driver_ver; 1934 1935 if (!dv) 1936 return -EINVAL; 1937 1938 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1939 1940 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1941 cmd->major_ver = dv->major_ver; 1942 cmd->minor_ver = dv->minor_ver; 1943 cmd->build_ver = dv->build_ver; 1944 cmd->subbuild_ver = dv->subbuild_ver; 1945 1946 len = 0; 1947 while (len < sizeof(dv->driver_string) && 1948 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1949 len++; 1950 1951 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1952 } 1953 1954 /** 1955 * ice_aq_q_shutdown 1956 * @hw: pointer to the HW struct 1957 * @unloading: is the driver unloading itself 1958 * 1959 * Tell the Firmware that we're shutting down the AdminQ and whether 1960 * or not the driver is unloading as well (0x0003). 1961 */ 1962 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1963 { 1964 struct ice_aqc_q_shutdown *cmd; 1965 struct ice_aq_desc desc; 1966 1967 cmd = &desc.params.q_shutdown; 1968 1969 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1970 1971 if (unloading) 1972 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1973 1974 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1975 } 1976 1977 /** 1978 * ice_aq_req_res 1979 * @hw: pointer to the HW struct 1980 * @res: resource ID 1981 * @access: access type 1982 * @sdp_number: resource number 1983 * @timeout: the maximum time in ms that the driver may hold the resource 1984 * @cd: pointer to command details structure or NULL 1985 * 1986 * Requests common resource using the admin queue commands (0x0008). 1987 * When attempting to acquire the Global Config Lock, the driver can 1988 * learn of three states: 1989 * 1) 0 - acquired lock, and can perform download package 1990 * 2) -EIO - did not get lock, driver should fail to load 1991 * 3) -EALREADY - did not get lock, but another driver has 1992 * successfully downloaded the package; the driver does 1993 * not have to download the package and can continue 1994 * loading 1995 * 1996 * Note that if the caller is in an acquire lock, perform action, release lock 1997 * phase of operation, it is possible that the FW may detect a timeout and issue 1998 * a CORER. In this case, the driver will receive a CORER interrupt and will 1999 * have to determine its cause. The calling thread that is handling this flow 2000 * will likely get an error propagated back to it indicating the Download 2001 * Package, Update Package or the Release Resource AQ commands timed out. 2002 */ 2003 static int 2004 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2005 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2006 struct ice_sq_cd *cd) 2007 { 2008 struct ice_aqc_req_res *cmd_resp; 2009 struct ice_aq_desc desc; 2010 int status; 2011 2012 cmd_resp = &desc.params.res_owner; 2013 2014 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2015 2016 cmd_resp->res_id = cpu_to_le16(res); 2017 cmd_resp->access_type = cpu_to_le16(access); 2018 cmd_resp->res_number = cpu_to_le32(sdp_number); 2019 cmd_resp->timeout = cpu_to_le32(*timeout); 2020 *timeout = 0; 2021 2022 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2023 2024 /* The completion specifies the maximum time in ms that the driver 2025 * may hold the resource in the Timeout field. 2026 */ 2027 2028 /* Global config lock response utilizes an additional status field. 2029 * 2030 * If the Global config lock resource is held by some other driver, the 2031 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 2032 * and the timeout field indicates the maximum time the current owner 2033 * of the resource has to free it. 2034 */ 2035 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2036 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 2037 *timeout = le32_to_cpu(cmd_resp->timeout); 2038 return 0; 2039 } else if (le16_to_cpu(cmd_resp->status) == 2040 ICE_AQ_RES_GLBL_IN_PROG) { 2041 *timeout = le32_to_cpu(cmd_resp->timeout); 2042 return -EIO; 2043 } else if (le16_to_cpu(cmd_resp->status) == 2044 ICE_AQ_RES_GLBL_DONE) { 2045 return -EALREADY; 2046 } 2047 2048 /* invalid FW response, force a timeout immediately */ 2049 *timeout = 0; 2050 return -EIO; 2051 } 2052 2053 /* If the resource is held by some other driver, the command completes 2054 * with a busy return value and the timeout field indicates the maximum 2055 * time the current owner of the resource has to free it. 2056 */ 2057 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 2058 *timeout = le32_to_cpu(cmd_resp->timeout); 2059 2060 return status; 2061 } 2062 2063 /** 2064 * ice_aq_release_res 2065 * @hw: pointer to the HW struct 2066 * @res: resource ID 2067 * @sdp_number: resource number 2068 * @cd: pointer to command details structure or NULL 2069 * 2070 * release common resource using the admin queue commands (0x0009) 2071 */ 2072 static int 2073 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2074 struct ice_sq_cd *cd) 2075 { 2076 struct ice_aqc_req_res *cmd; 2077 struct ice_aq_desc desc; 2078 2079 cmd = &desc.params.res_owner; 2080 2081 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2082 2083 cmd->res_id = cpu_to_le16(res); 2084 cmd->res_number = cpu_to_le32(sdp_number); 2085 2086 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2087 } 2088 2089 /** 2090 * ice_acquire_res 2091 * @hw: pointer to the HW structure 2092 * @res: resource ID 2093 * @access: access type (read or write) 2094 * @timeout: timeout in milliseconds 2095 * 2096 * This function will attempt to acquire the ownership of a resource. 2097 */ 2098 int 2099 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2100 enum ice_aq_res_access_type access, u32 timeout) 2101 { 2102 #define ICE_RES_POLLING_DELAY_MS 10 2103 u32 delay = ICE_RES_POLLING_DELAY_MS; 2104 u32 time_left = timeout; 2105 int status; 2106 2107 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2108 2109 /* A return code of -EALREADY means that another driver has 2110 * previously acquired the resource and performed any necessary updates; 2111 * in this case the caller does not obtain the resource and has no 2112 * further work to do. 2113 */ 2114 if (status == -EALREADY) 2115 goto ice_acquire_res_exit; 2116 2117 if (status) 2118 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2119 2120 /* If necessary, poll until the current lock owner timeouts */ 2121 timeout = time_left; 2122 while (status && timeout && time_left) { 2123 mdelay(delay); 2124 timeout = (timeout > delay) ? timeout - delay : 0; 2125 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2126 2127 if (status == -EALREADY) 2128 /* lock free, but no work to do */ 2129 break; 2130 2131 if (!status) 2132 /* lock acquired */ 2133 break; 2134 } 2135 if (status && status != -EALREADY) 2136 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2137 2138 ice_acquire_res_exit: 2139 if (status == -EALREADY) { 2140 if (access == ICE_RES_WRITE) 2141 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2142 else 2143 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2144 } 2145 return status; 2146 } 2147 2148 /** 2149 * ice_release_res 2150 * @hw: pointer to the HW structure 2151 * @res: resource ID 2152 * 2153 * This function will release a resource using the proper Admin Command. 2154 */ 2155 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2156 { 2157 unsigned long timeout; 2158 int status; 2159 2160 /* there are some rare cases when trying to release the resource 2161 * results in an admin queue timeout, so handle them correctly 2162 */ 2163 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2164 do { 2165 status = ice_aq_release_res(hw, res, 0, NULL); 2166 if (status != -EIO) 2167 break; 2168 usleep_range(1000, 2000); 2169 } while (time_before(jiffies, timeout)); 2170 } 2171 2172 /** 2173 * ice_aq_alloc_free_res - command to allocate/free resources 2174 * @hw: pointer to the HW struct 2175 * @buf: Indirect buffer to hold data parameters and response 2176 * @buf_size: size of buffer for indirect commands 2177 * @opc: pass in the command opcode 2178 * 2179 * Helper function to allocate/free resources using the admin queue commands 2180 */ 2181 int ice_aq_alloc_free_res(struct ice_hw *hw, 2182 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2183 enum ice_adminq_opc opc) 2184 { 2185 struct ice_aqc_alloc_free_res_cmd *cmd; 2186 struct ice_aq_desc desc; 2187 2188 cmd = &desc.params.sw_res_ctrl; 2189 2190 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2191 return -EINVAL; 2192 2193 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2194 2195 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2196 2197 cmd->num_entries = cpu_to_le16(1); 2198 2199 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2200 } 2201 2202 /** 2203 * ice_alloc_hw_res - allocate resource 2204 * @hw: pointer to the HW struct 2205 * @type: type of resource 2206 * @num: number of resources to allocate 2207 * @btm: allocate from bottom 2208 * @res: pointer to array that will receive the resources 2209 */ 2210 int 2211 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2212 { 2213 struct ice_aqc_alloc_free_res_elem *buf; 2214 u16 buf_len; 2215 int status; 2216 2217 buf_len = struct_size(buf, elem, num); 2218 buf = kzalloc(buf_len, GFP_KERNEL); 2219 if (!buf) 2220 return -ENOMEM; 2221 2222 /* Prepare buffer to allocate resource. */ 2223 buf->num_elems = cpu_to_le16(num); 2224 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2225 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2226 if (btm) 2227 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2228 2229 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2230 if (status) 2231 goto ice_alloc_res_exit; 2232 2233 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2234 2235 ice_alloc_res_exit: 2236 kfree(buf); 2237 return status; 2238 } 2239 2240 /** 2241 * ice_free_hw_res - free allocated HW resource 2242 * @hw: pointer to the HW struct 2243 * @type: type of resource to free 2244 * @num: number of resources 2245 * @res: pointer to array that contains the resources to free 2246 */ 2247 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2248 { 2249 struct ice_aqc_alloc_free_res_elem *buf; 2250 u16 buf_len; 2251 int status; 2252 2253 buf_len = struct_size(buf, elem, num); 2254 buf = kzalloc(buf_len, GFP_KERNEL); 2255 if (!buf) 2256 return -ENOMEM; 2257 2258 /* Prepare buffer to free resource. */ 2259 buf->num_elems = cpu_to_le16(num); 2260 buf->res_type = cpu_to_le16(type); 2261 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2262 2263 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2264 if (status) 2265 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2266 2267 kfree(buf); 2268 return status; 2269 } 2270 2271 /** 2272 * ice_get_num_per_func - determine number of resources per PF 2273 * @hw: pointer to the HW structure 2274 * @max: value to be evenly split between each PF 2275 * 2276 * Determine the number of valid functions by going through the bitmap returned 2277 * from parsing capabilities and use this to calculate the number of resources 2278 * per PF based on the max value passed in. 2279 */ 2280 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2281 { 2282 u8 funcs; 2283 2284 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2285 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2286 ICE_CAPS_VALID_FUNCS_M); 2287 2288 if (!funcs) 2289 return 0; 2290 2291 return max / funcs; 2292 } 2293 2294 /** 2295 * ice_parse_common_caps - parse common device/function capabilities 2296 * @hw: pointer to the HW struct 2297 * @caps: pointer to common capabilities structure 2298 * @elem: the capability element to parse 2299 * @prefix: message prefix for tracing capabilities 2300 * 2301 * Given a capability element, extract relevant details into the common 2302 * capability structure. 2303 * 2304 * Returns: true if the capability matches one of the common capability ids, 2305 * false otherwise. 2306 */ 2307 static bool 2308 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2309 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2310 { 2311 u32 logical_id = le32_to_cpu(elem->logical_id); 2312 u32 phys_id = le32_to_cpu(elem->phys_id); 2313 u32 number = le32_to_cpu(elem->number); 2314 u16 cap = le16_to_cpu(elem->cap); 2315 bool found = true; 2316 2317 switch (cap) { 2318 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2319 caps->valid_functions = number; 2320 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2321 caps->valid_functions); 2322 break; 2323 case ICE_AQC_CAPS_SRIOV: 2324 caps->sr_iov_1_1 = (number == 1); 2325 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2326 caps->sr_iov_1_1); 2327 break; 2328 case ICE_AQC_CAPS_DCB: 2329 caps->dcb = (number == 1); 2330 caps->active_tc_bitmap = logical_id; 2331 caps->maxtc = phys_id; 2332 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2333 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2334 caps->active_tc_bitmap); 2335 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2336 break; 2337 case ICE_AQC_CAPS_RSS: 2338 caps->rss_table_size = number; 2339 caps->rss_table_entry_width = logical_id; 2340 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2341 caps->rss_table_size); 2342 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2343 caps->rss_table_entry_width); 2344 break; 2345 case ICE_AQC_CAPS_RXQS: 2346 caps->num_rxq = number; 2347 caps->rxq_first_id = phys_id; 2348 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2349 caps->num_rxq); 2350 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2351 caps->rxq_first_id); 2352 break; 2353 case ICE_AQC_CAPS_TXQS: 2354 caps->num_txq = number; 2355 caps->txq_first_id = phys_id; 2356 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2357 caps->num_txq); 2358 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2359 caps->txq_first_id); 2360 break; 2361 case ICE_AQC_CAPS_MSIX: 2362 caps->num_msix_vectors = number; 2363 caps->msix_vector_first_id = phys_id; 2364 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2365 caps->num_msix_vectors); 2366 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2367 caps->msix_vector_first_id); 2368 break; 2369 case ICE_AQC_CAPS_PENDING_NVM_VER: 2370 caps->nvm_update_pending_nvm = true; 2371 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2372 break; 2373 case ICE_AQC_CAPS_PENDING_OROM_VER: 2374 caps->nvm_update_pending_orom = true; 2375 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2376 break; 2377 case ICE_AQC_CAPS_PENDING_NET_VER: 2378 caps->nvm_update_pending_netlist = true; 2379 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2380 break; 2381 case ICE_AQC_CAPS_NVM_MGMT: 2382 caps->nvm_unified_update = 2383 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2384 true : false; 2385 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2386 caps->nvm_unified_update); 2387 break; 2388 case ICE_AQC_CAPS_RDMA: 2389 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2390 caps->rdma = (number == 1); 2391 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2392 break; 2393 case ICE_AQC_CAPS_MAX_MTU: 2394 caps->max_mtu = number; 2395 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2396 prefix, caps->max_mtu); 2397 break; 2398 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2399 caps->pcie_reset_avoidance = (number > 0); 2400 ice_debug(hw, ICE_DBG_INIT, 2401 "%s: pcie_reset_avoidance = %d\n", prefix, 2402 caps->pcie_reset_avoidance); 2403 break; 2404 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2405 caps->reset_restrict_support = (number == 1); 2406 ice_debug(hw, ICE_DBG_INIT, 2407 "%s: reset_restrict_support = %d\n", prefix, 2408 caps->reset_restrict_support); 2409 break; 2410 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2411 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2412 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2413 prefix, caps->roce_lag); 2414 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2415 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2416 prefix, caps->sriov_lag); 2417 break; 2418 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2419 caps->tx_sched_topo_comp_mode_en = (number == 1); 2420 break; 2421 default: 2422 /* Not one of the recognized common capabilities */ 2423 found = false; 2424 } 2425 2426 return found; 2427 } 2428 2429 /** 2430 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2431 * @hw: pointer to the HW structure 2432 * @caps: pointer to capabilities structure to fix 2433 * 2434 * Re-calculate the capabilities that are dependent on the number of physical 2435 * ports; i.e. some features are not supported or function differently on 2436 * devices with more than 4 ports. 2437 */ 2438 static void 2439 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2440 { 2441 /* This assumes device capabilities are always scanned before function 2442 * capabilities during the initialization flow. 2443 */ 2444 if (hw->dev_caps.num_funcs > 4) { 2445 /* Max 4 TCs per port */ 2446 caps->maxtc = 4; 2447 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2448 caps->maxtc); 2449 if (caps->rdma) { 2450 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2451 caps->rdma = 0; 2452 } 2453 2454 /* print message only when processing device capabilities 2455 * during initialization. 2456 */ 2457 if (caps == &hw->dev_caps.common_cap) 2458 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2459 } 2460 } 2461 2462 /** 2463 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2464 * @hw: pointer to the HW struct 2465 * @func_p: pointer to function capabilities structure 2466 * @cap: pointer to the capability element to parse 2467 * 2468 * Extract function capabilities for ICE_AQC_CAPS_VF. 2469 */ 2470 static void 2471 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2472 struct ice_aqc_list_caps_elem *cap) 2473 { 2474 u32 logical_id = le32_to_cpu(cap->logical_id); 2475 u32 number = le32_to_cpu(cap->number); 2476 2477 func_p->num_allocd_vfs = number; 2478 func_p->vf_base_id = logical_id; 2479 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2480 func_p->num_allocd_vfs); 2481 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2482 func_p->vf_base_id); 2483 } 2484 2485 /** 2486 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2487 * @hw: pointer to the HW struct 2488 * @func_p: pointer to function capabilities structure 2489 * @cap: pointer to the capability element to parse 2490 * 2491 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2492 */ 2493 static void 2494 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2495 struct ice_aqc_list_caps_elem *cap) 2496 { 2497 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2498 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2499 le32_to_cpu(cap->number)); 2500 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2501 func_p->guar_num_vsi); 2502 } 2503 2504 /** 2505 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2506 * @hw: pointer to the HW struct 2507 * @func_p: pointer to function capabilities structure 2508 * @cap: pointer to the capability element to parse 2509 * 2510 * Extract function capabilities for ICE_AQC_CAPS_1588. 2511 */ 2512 static void 2513 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2514 struct ice_aqc_list_caps_elem *cap) 2515 { 2516 struct ice_ts_func_info *info = &func_p->ts_func_info; 2517 u32 number = le32_to_cpu(cap->number); 2518 2519 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2520 func_p->common_cap.ieee_1588 = info->ena; 2521 2522 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2523 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2524 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2525 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2526 2527 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2528 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2529 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2530 } else { 2531 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2532 info->clk_src = ICE_CLK_SRC_TIME_REF; 2533 } 2534 2535 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2536 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2537 } else { 2538 /* Unknown clock frequency, so assume a (probably incorrect) 2539 * default to avoid out-of-bounds look ups of frequency 2540 * related information. 2541 */ 2542 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2543 info->clk_freq); 2544 info->time_ref = ICE_TSPLL_FREQ_25_000; 2545 } 2546 2547 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2548 func_p->common_cap.ieee_1588); 2549 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2550 info->src_tmr_owned); 2551 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2552 info->tmr_ena); 2553 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2554 info->tmr_index_owned); 2555 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2556 info->tmr_index_assoc); 2557 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2558 info->clk_freq); 2559 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2560 info->clk_src); 2561 } 2562 2563 /** 2564 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2565 * @hw: pointer to the HW struct 2566 * @func_p: pointer to function capabilities structure 2567 * 2568 * Extract function capabilities for ICE_AQC_CAPS_FD. 2569 */ 2570 static void 2571 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2572 { 2573 u32 reg_val, gsize, bsize; 2574 2575 reg_val = rd32(hw, GLQF_FD_SIZE); 2576 switch (hw->mac_type) { 2577 case ICE_MAC_E830: 2578 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2579 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2580 break; 2581 case ICE_MAC_E810: 2582 default: 2583 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2584 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2585 } 2586 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2587 func_p->fd_fltr_best_effort = bsize; 2588 2589 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2590 func_p->fd_fltr_guar); 2591 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2592 func_p->fd_fltr_best_effort); 2593 } 2594 2595 /** 2596 * ice_parse_func_caps - Parse function capabilities 2597 * @hw: pointer to the HW struct 2598 * @func_p: pointer to function capabilities structure 2599 * @buf: buffer containing the function capability records 2600 * @cap_count: the number of capabilities 2601 * 2602 * Helper function to parse function (0x000A) capabilities list. For 2603 * capabilities shared between device and function, this relies on 2604 * ice_parse_common_caps. 2605 * 2606 * Loop through the list of provided capabilities and extract the relevant 2607 * data into the function capabilities structured. 2608 */ 2609 static void 2610 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2611 void *buf, u32 cap_count) 2612 { 2613 struct ice_aqc_list_caps_elem *cap_resp; 2614 u32 i; 2615 2616 cap_resp = buf; 2617 2618 memset(func_p, 0, sizeof(*func_p)); 2619 2620 for (i = 0; i < cap_count; i++) { 2621 u16 cap = le16_to_cpu(cap_resp[i].cap); 2622 bool found; 2623 2624 found = ice_parse_common_caps(hw, &func_p->common_cap, 2625 &cap_resp[i], "func caps"); 2626 2627 switch (cap) { 2628 case ICE_AQC_CAPS_VF: 2629 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2630 break; 2631 case ICE_AQC_CAPS_VSI: 2632 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2633 break; 2634 case ICE_AQC_CAPS_1588: 2635 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2636 break; 2637 case ICE_AQC_CAPS_FD: 2638 ice_parse_fdir_func_caps(hw, func_p); 2639 break; 2640 default: 2641 /* Don't list common capabilities as unknown */ 2642 if (!found) 2643 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2644 i, cap); 2645 break; 2646 } 2647 } 2648 2649 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2650 } 2651 2652 /** 2653 * ice_func_id_to_logical_id - map from function id to logical pf id 2654 * @active_function_bitmap: active function bitmap 2655 * @pf_id: function number of device 2656 * 2657 * Return: logical PF ID. 2658 */ 2659 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2660 { 2661 u8 logical_id = 0; 2662 u8 i; 2663 2664 for (i = 0; i < pf_id; i++) 2665 if (active_function_bitmap & BIT(i)) 2666 logical_id++; 2667 2668 return logical_id; 2669 } 2670 2671 /** 2672 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2673 * @hw: pointer to the HW struct 2674 * @dev_p: pointer to device capabilities structure 2675 * @cap: capability element to parse 2676 * 2677 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2678 */ 2679 static void 2680 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2681 struct ice_aqc_list_caps_elem *cap) 2682 { 2683 u32 number = le32_to_cpu(cap->number); 2684 2685 dev_p->num_funcs = hweight32(number); 2686 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2687 dev_p->num_funcs); 2688 2689 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2690 } 2691 2692 /** 2693 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2694 * @hw: pointer to the HW struct 2695 * @dev_p: pointer to device capabilities structure 2696 * @cap: capability element to parse 2697 * 2698 * Parse ICE_AQC_CAPS_VF for device capabilities. 2699 */ 2700 static void 2701 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2702 struct ice_aqc_list_caps_elem *cap) 2703 { 2704 u32 number = le32_to_cpu(cap->number); 2705 2706 dev_p->num_vfs_exposed = number; 2707 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2708 dev_p->num_vfs_exposed); 2709 } 2710 2711 /** 2712 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2713 * @hw: pointer to the HW struct 2714 * @dev_p: pointer to device capabilities structure 2715 * @cap: capability element to parse 2716 * 2717 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2718 */ 2719 static void 2720 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2721 struct ice_aqc_list_caps_elem *cap) 2722 { 2723 u32 number = le32_to_cpu(cap->number); 2724 2725 dev_p->num_vsi_allocd_to_host = number; 2726 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2727 dev_p->num_vsi_allocd_to_host); 2728 } 2729 2730 /** 2731 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2732 * @hw: pointer to the HW struct 2733 * @dev_p: pointer to device capabilities structure 2734 * @cap: capability element to parse 2735 * 2736 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2737 */ 2738 static void 2739 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2740 struct ice_aqc_list_caps_elem *cap) 2741 { 2742 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2743 u32 logical_id = le32_to_cpu(cap->logical_id); 2744 u32 phys_id = le32_to_cpu(cap->phys_id); 2745 u32 number = le32_to_cpu(cap->number); 2746 2747 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2748 dev_p->common_cap.ieee_1588 = info->ena; 2749 2750 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2751 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2752 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2753 2754 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2755 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2756 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2757 2758 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2759 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2760 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2761 2762 info->ena_ports = logical_id; 2763 info->tmr_own_map = phys_id; 2764 2765 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2766 dev_p->common_cap.ieee_1588); 2767 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2768 info->tmr0_owner); 2769 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2770 info->tmr0_owned); 2771 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2772 info->tmr0_ena); 2773 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2774 info->tmr1_owner); 2775 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2776 info->tmr1_owned); 2777 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2778 info->tmr1_ena); 2779 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2780 info->ts_ll_read); 2781 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2782 info->ts_ll_int_read); 2783 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2784 info->ll_phy_tmr_update); 2785 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2786 info->ena_ports); 2787 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2788 info->tmr_own_map); 2789 } 2790 2791 /** 2792 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2793 * @hw: pointer to the HW struct 2794 * @dev_p: pointer to device capabilities structure 2795 * @cap: capability element to parse 2796 * 2797 * Parse ICE_AQC_CAPS_FD for device capabilities. 2798 */ 2799 static void 2800 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2801 struct ice_aqc_list_caps_elem *cap) 2802 { 2803 u32 number = le32_to_cpu(cap->number); 2804 2805 dev_p->num_flow_director_fltr = number; 2806 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2807 dev_p->num_flow_director_fltr); 2808 } 2809 2810 /** 2811 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2812 * @hw: pointer to the HW struct 2813 * @dev_p: pointer to device capabilities structure 2814 * @cap: capability element to parse 2815 * 2816 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2817 * enabled sensors. 2818 */ 2819 static void 2820 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2821 struct ice_aqc_list_caps_elem *cap) 2822 { 2823 dev_p->supported_sensors = le32_to_cpu(cap->number); 2824 2825 ice_debug(hw, ICE_DBG_INIT, 2826 "dev caps: supported sensors (bitmap) = 0x%x\n", 2827 dev_p->supported_sensors); 2828 } 2829 2830 /** 2831 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2832 * @hw: pointer to the HW struct 2833 * @dev_p: pointer to device capabilities structure 2834 * @cap: capability element to parse 2835 * 2836 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2837 */ 2838 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2839 struct ice_hw_dev_caps *dev_p, 2840 struct ice_aqc_list_caps_elem *cap) 2841 { 2842 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2843 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2844 2845 dev_info(ice_hw_to_dev(hw), 2846 "PF is configured in %s mode with IP instance ID %d\n", 2847 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2848 "primary" : "secondary", dev_p->nac_topo.id); 2849 2850 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2851 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2852 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2853 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2854 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2855 dev_p->nac_topo.id); 2856 } 2857 2858 /** 2859 * ice_parse_dev_caps - Parse device capabilities 2860 * @hw: pointer to the HW struct 2861 * @dev_p: pointer to device capabilities structure 2862 * @buf: buffer containing the device capability records 2863 * @cap_count: the number of capabilities 2864 * 2865 * Helper device to parse device (0x000B) capabilities list. For 2866 * capabilities shared between device and function, this relies on 2867 * ice_parse_common_caps. 2868 * 2869 * Loop through the list of provided capabilities and extract the relevant 2870 * data into the device capabilities structured. 2871 */ 2872 static void 2873 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2874 void *buf, u32 cap_count) 2875 { 2876 struct ice_aqc_list_caps_elem *cap_resp; 2877 u32 i; 2878 2879 cap_resp = buf; 2880 2881 memset(dev_p, 0, sizeof(*dev_p)); 2882 2883 for (i = 0; i < cap_count; i++) { 2884 u16 cap = le16_to_cpu(cap_resp[i].cap); 2885 bool found; 2886 2887 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2888 &cap_resp[i], "dev caps"); 2889 2890 switch (cap) { 2891 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2892 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2893 break; 2894 case ICE_AQC_CAPS_VF: 2895 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2896 break; 2897 case ICE_AQC_CAPS_VSI: 2898 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2899 break; 2900 case ICE_AQC_CAPS_1588: 2901 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2902 break; 2903 case ICE_AQC_CAPS_FD: 2904 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2905 break; 2906 case ICE_AQC_CAPS_SENSOR_READING: 2907 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2908 break; 2909 case ICE_AQC_CAPS_NAC_TOPOLOGY: 2910 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2911 break; 2912 default: 2913 /* Don't list common capabilities as unknown */ 2914 if (!found) 2915 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2916 i, cap); 2917 break; 2918 } 2919 } 2920 2921 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2922 } 2923 2924 /** 2925 * ice_is_phy_rclk_in_netlist 2926 * @hw: pointer to the hw struct 2927 * 2928 * Check if the PHY Recovered Clock device is present in the netlist 2929 */ 2930 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2931 { 2932 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2933 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2934 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2935 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2936 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2937 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2938 return false; 2939 2940 return true; 2941 } 2942 2943 /** 2944 * ice_is_clock_mux_in_netlist 2945 * @hw: pointer to the hw struct 2946 * 2947 * Check if the Clock Multiplexer device is present in the netlist 2948 */ 2949 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2950 { 2951 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2952 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2953 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2954 NULL)) 2955 return false; 2956 2957 return true; 2958 } 2959 2960 /** 2961 * ice_is_cgu_in_netlist - check for CGU presence 2962 * @hw: pointer to the hw struct 2963 * 2964 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2965 * Save the CGU part number in the hw structure for later use. 2966 * Return: 2967 * * true - cgu is present 2968 * * false - cgu is not present 2969 */ 2970 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2971 { 2972 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2973 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2974 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2975 NULL)) { 2976 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2977 return true; 2978 } else if (!ice_find_netlist_node(hw, 2979 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2980 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2981 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2982 NULL)) { 2983 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2984 return true; 2985 } 2986 2987 return false; 2988 } 2989 2990 /** 2991 * ice_is_gps_in_netlist 2992 * @hw: pointer to the hw struct 2993 * 2994 * Check if the GPS generic device is present in the netlist 2995 */ 2996 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2997 { 2998 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2999 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3000 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3001 return false; 3002 3003 return true; 3004 } 3005 3006 /** 3007 * ice_aq_list_caps - query function/device capabilities 3008 * @hw: pointer to the HW struct 3009 * @buf: a buffer to hold the capabilities 3010 * @buf_size: size of the buffer 3011 * @cap_count: if not NULL, set to the number of capabilities reported 3012 * @opc: capabilities type to discover, device or function 3013 * @cd: pointer to command details structure or NULL 3014 * 3015 * Get the function (0x000A) or device (0x000B) capabilities description from 3016 * firmware and store it in the buffer. 3017 * 3018 * If the cap_count pointer is not NULL, then it is set to the number of 3019 * capabilities firmware will report. Note that if the buffer size is too 3020 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3021 * cap_count will still be updated in this case. It is recommended that the 3022 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3023 * firmware could return) to avoid this. 3024 */ 3025 int 3026 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3027 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3028 { 3029 struct ice_aqc_list_caps *cmd; 3030 struct ice_aq_desc desc; 3031 int status; 3032 3033 cmd = &desc.params.get_cap; 3034 3035 if (opc != ice_aqc_opc_list_func_caps && 3036 opc != ice_aqc_opc_list_dev_caps) 3037 return -EINVAL; 3038 3039 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3040 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3041 3042 if (cap_count) 3043 *cap_count = le32_to_cpu(cmd->count); 3044 3045 return status; 3046 } 3047 3048 /** 3049 * ice_discover_dev_caps - Read and extract device capabilities 3050 * @hw: pointer to the hardware structure 3051 * @dev_caps: pointer to device capabilities structure 3052 * 3053 * Read the device capabilities and extract them into the dev_caps structure 3054 * for later use. 3055 */ 3056 int 3057 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3058 { 3059 u32 cap_count = 0; 3060 void *cbuf; 3061 int status; 3062 3063 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3064 if (!cbuf) 3065 return -ENOMEM; 3066 3067 /* Although the driver doesn't know the number of capabilities the 3068 * device will return, we can simply send a 4KB buffer, the maximum 3069 * possible size that firmware can return. 3070 */ 3071 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3072 3073 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3074 ice_aqc_opc_list_dev_caps, NULL); 3075 if (!status) 3076 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3077 kfree(cbuf); 3078 3079 return status; 3080 } 3081 3082 /** 3083 * ice_discover_func_caps - Read and extract function capabilities 3084 * @hw: pointer to the hardware structure 3085 * @func_caps: pointer to function capabilities structure 3086 * 3087 * Read the function capabilities and extract them into the func_caps structure 3088 * for later use. 3089 */ 3090 static int 3091 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3092 { 3093 u32 cap_count = 0; 3094 void *cbuf; 3095 int status; 3096 3097 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3098 if (!cbuf) 3099 return -ENOMEM; 3100 3101 /* Although the driver doesn't know the number of capabilities the 3102 * device will return, we can simply send a 4KB buffer, the maximum 3103 * possible size that firmware can return. 3104 */ 3105 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3106 3107 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3108 ice_aqc_opc_list_func_caps, NULL); 3109 if (!status) 3110 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3111 kfree(cbuf); 3112 3113 return status; 3114 } 3115 3116 /** 3117 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3118 * @hw: pointer to the hardware structure 3119 */ 3120 void ice_set_safe_mode_caps(struct ice_hw *hw) 3121 { 3122 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3123 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3124 struct ice_hw_common_caps cached_caps; 3125 u32 num_funcs; 3126 3127 /* cache some func_caps values that should be restored after memset */ 3128 cached_caps = func_caps->common_cap; 3129 3130 /* unset func capabilities */ 3131 memset(func_caps, 0, sizeof(*func_caps)); 3132 3133 #define ICE_RESTORE_FUNC_CAP(name) \ 3134 func_caps->common_cap.name = cached_caps.name 3135 3136 /* restore cached values */ 3137 ICE_RESTORE_FUNC_CAP(valid_functions); 3138 ICE_RESTORE_FUNC_CAP(txq_first_id); 3139 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3140 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3141 ICE_RESTORE_FUNC_CAP(max_mtu); 3142 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3143 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3144 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3145 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3146 3147 /* one Tx and one Rx queue in safe mode */ 3148 func_caps->common_cap.num_rxq = 1; 3149 func_caps->common_cap.num_txq = 1; 3150 3151 /* two MSIX vectors, one for traffic and one for misc causes */ 3152 func_caps->common_cap.num_msix_vectors = 2; 3153 func_caps->guar_num_vsi = 1; 3154 3155 /* cache some dev_caps values that should be restored after memset */ 3156 cached_caps = dev_caps->common_cap; 3157 num_funcs = dev_caps->num_funcs; 3158 3159 /* unset dev capabilities */ 3160 memset(dev_caps, 0, sizeof(*dev_caps)); 3161 3162 #define ICE_RESTORE_DEV_CAP(name) \ 3163 dev_caps->common_cap.name = cached_caps.name 3164 3165 /* restore cached values */ 3166 ICE_RESTORE_DEV_CAP(valid_functions); 3167 ICE_RESTORE_DEV_CAP(txq_first_id); 3168 ICE_RESTORE_DEV_CAP(rxq_first_id); 3169 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3170 ICE_RESTORE_DEV_CAP(max_mtu); 3171 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3172 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3173 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3174 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3175 dev_caps->num_funcs = num_funcs; 3176 3177 /* one Tx and one Rx queue per function in safe mode */ 3178 dev_caps->common_cap.num_rxq = num_funcs; 3179 dev_caps->common_cap.num_txq = num_funcs; 3180 3181 /* two MSIX vectors per function */ 3182 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3183 } 3184 3185 /** 3186 * ice_get_caps - get info about the HW 3187 * @hw: pointer to the hardware structure 3188 */ 3189 int ice_get_caps(struct ice_hw *hw) 3190 { 3191 int status; 3192 3193 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3194 if (status) 3195 return status; 3196 3197 return ice_discover_func_caps(hw, &hw->func_caps); 3198 } 3199 3200 /** 3201 * ice_aq_manage_mac_write - manage MAC address write command 3202 * @hw: pointer to the HW struct 3203 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3204 * @flags: flags to control write behavior 3205 * @cd: pointer to command details structure or NULL 3206 * 3207 * This function is used to write MAC address to the NVM (0x0108). 3208 */ 3209 int 3210 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3211 struct ice_sq_cd *cd) 3212 { 3213 struct ice_aqc_manage_mac_write *cmd; 3214 struct ice_aq_desc desc; 3215 3216 cmd = &desc.params.mac_write; 3217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3218 3219 cmd->flags = flags; 3220 ether_addr_copy(cmd->mac_addr, mac_addr); 3221 3222 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3223 } 3224 3225 /** 3226 * ice_aq_clear_pxe_mode 3227 * @hw: pointer to the HW struct 3228 * 3229 * Tell the firmware that the driver is taking over from PXE (0x0110). 3230 */ 3231 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3232 { 3233 struct ice_aq_desc desc; 3234 3235 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3236 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3237 3238 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3239 } 3240 3241 /** 3242 * ice_clear_pxe_mode - clear pxe operations mode 3243 * @hw: pointer to the HW struct 3244 * 3245 * Make sure all PXE mode settings are cleared, including things 3246 * like descriptor fetch/write-back mode. 3247 */ 3248 void ice_clear_pxe_mode(struct ice_hw *hw) 3249 { 3250 if (ice_check_sq_alive(hw, &hw->adminq)) 3251 ice_aq_clear_pxe_mode(hw); 3252 } 3253 3254 /** 3255 * ice_aq_set_port_params - set physical port parameters. 3256 * @pi: pointer to the port info struct 3257 * @double_vlan: if set double VLAN is enabled 3258 * @cd: pointer to command details structure or NULL 3259 * 3260 * Set Physical port parameters (0x0203) 3261 */ 3262 int 3263 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3264 struct ice_sq_cd *cd) 3265 3266 { 3267 struct ice_aqc_set_port_params *cmd; 3268 struct ice_hw *hw = pi->hw; 3269 struct ice_aq_desc desc; 3270 u16 cmd_flags = 0; 3271 3272 cmd = &desc.params.set_port_params; 3273 3274 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3275 if (double_vlan) 3276 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3277 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3278 3279 cmd->local_fwd_mode = pi->local_fwd_mode | 3280 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3281 3282 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3283 } 3284 3285 /** 3286 * ice_is_100m_speed_supported 3287 * @hw: pointer to the HW struct 3288 * 3289 * returns true if 100M speeds are supported by the device, 3290 * false otherwise. 3291 */ 3292 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3293 { 3294 switch (hw->device_id) { 3295 case ICE_DEV_ID_E822C_SGMII: 3296 case ICE_DEV_ID_E822L_SGMII: 3297 case ICE_DEV_ID_E823L_1GBE: 3298 case ICE_DEV_ID_E823C_SGMII: 3299 return true; 3300 default: 3301 return false; 3302 } 3303 } 3304 3305 /** 3306 * ice_get_link_speed_based_on_phy_type - returns link speed 3307 * @phy_type_low: lower part of phy_type 3308 * @phy_type_high: higher part of phy_type 3309 * 3310 * This helper function will convert an entry in PHY type structure 3311 * [phy_type_low, phy_type_high] to its corresponding link speed. 3312 * Note: In the structure of [phy_type_low, phy_type_high], there should 3313 * be one bit set, as this function will convert one PHY type to its 3314 * speed. 3315 * 3316 * Return: 3317 * * PHY speed for recognized PHY type 3318 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3319 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3320 */ 3321 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3322 { 3323 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3324 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3325 3326 switch (phy_type_low) { 3327 case ICE_PHY_TYPE_LOW_100BASE_TX: 3328 case ICE_PHY_TYPE_LOW_100M_SGMII: 3329 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3330 break; 3331 case ICE_PHY_TYPE_LOW_1000BASE_T: 3332 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3333 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3334 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3335 case ICE_PHY_TYPE_LOW_1G_SGMII: 3336 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3337 break; 3338 case ICE_PHY_TYPE_LOW_2500BASE_T: 3339 case ICE_PHY_TYPE_LOW_2500BASE_X: 3340 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3341 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3342 break; 3343 case ICE_PHY_TYPE_LOW_5GBASE_T: 3344 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3345 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3346 break; 3347 case ICE_PHY_TYPE_LOW_10GBASE_T: 3348 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3349 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3350 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3351 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3352 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3353 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3354 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3355 break; 3356 case ICE_PHY_TYPE_LOW_25GBASE_T: 3357 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3358 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3359 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3360 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3361 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3362 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3363 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3364 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3365 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3366 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3367 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3368 break; 3369 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3370 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3371 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3372 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3373 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3374 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3375 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3376 break; 3377 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3378 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3379 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3380 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3381 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3382 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3383 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3384 case ICE_PHY_TYPE_LOW_50G_AUI2: 3385 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3386 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3387 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3388 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3389 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3390 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3391 case ICE_PHY_TYPE_LOW_50G_AUI1: 3392 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3393 break; 3394 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3395 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3396 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3397 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3398 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3399 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3400 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3401 case ICE_PHY_TYPE_LOW_100G_AUI4: 3402 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3403 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3404 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3405 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3406 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3407 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3408 break; 3409 default: 3410 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3411 break; 3412 } 3413 3414 switch (phy_type_high) { 3415 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3416 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3417 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3418 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3419 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3420 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3421 break; 3422 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3423 case ICE_PHY_TYPE_HIGH_200G_SR4: 3424 case ICE_PHY_TYPE_HIGH_200G_FR4: 3425 case ICE_PHY_TYPE_HIGH_200G_LR4: 3426 case ICE_PHY_TYPE_HIGH_200G_DR4: 3427 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3428 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3429 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3430 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3431 break; 3432 default: 3433 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3434 break; 3435 } 3436 3437 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3438 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3439 return ICE_AQ_LINK_SPEED_UNKNOWN; 3440 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3441 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3442 return ICE_AQ_LINK_SPEED_UNKNOWN; 3443 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3444 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3445 return speed_phy_type_low; 3446 else 3447 return speed_phy_type_high; 3448 } 3449 3450 /** 3451 * ice_update_phy_type 3452 * @phy_type_low: pointer to the lower part of phy_type 3453 * @phy_type_high: pointer to the higher part of phy_type 3454 * @link_speeds_bitmap: targeted link speeds bitmap 3455 * 3456 * Note: For the link_speeds_bitmap structure, you can check it at 3457 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3458 * link_speeds_bitmap include multiple speeds. 3459 * 3460 * Each entry in this [phy_type_low, phy_type_high] structure will 3461 * present a certain link speed. This helper function will turn on bits 3462 * in [phy_type_low, phy_type_high] structure based on the value of 3463 * link_speeds_bitmap input parameter. 3464 */ 3465 void 3466 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3467 u16 link_speeds_bitmap) 3468 { 3469 u64 pt_high; 3470 u64 pt_low; 3471 int index; 3472 u16 speed; 3473 3474 /* We first check with low part of phy_type */ 3475 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3476 pt_low = BIT_ULL(index); 3477 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3478 3479 if (link_speeds_bitmap & speed) 3480 *phy_type_low |= BIT_ULL(index); 3481 } 3482 3483 /* We then check with high part of phy_type */ 3484 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3485 pt_high = BIT_ULL(index); 3486 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3487 3488 if (link_speeds_bitmap & speed) 3489 *phy_type_high |= BIT_ULL(index); 3490 } 3491 } 3492 3493 /** 3494 * ice_aq_set_phy_cfg 3495 * @hw: pointer to the HW struct 3496 * @pi: port info structure of the interested logical port 3497 * @cfg: structure with PHY configuration data to be set 3498 * @cd: pointer to command details structure or NULL 3499 * 3500 * Set the various PHY configuration parameters supported on the Port. 3501 * One or more of the Set PHY config parameters may be ignored in an MFP 3502 * mode as the PF may not have the privilege to set some of the PHY Config 3503 * parameters. This status will be indicated by the command response (0x0601). 3504 */ 3505 int 3506 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3507 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3508 { 3509 struct ice_aq_desc desc; 3510 int status; 3511 3512 if (!cfg) 3513 return -EINVAL; 3514 3515 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3516 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3517 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3518 cfg->caps); 3519 3520 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3521 } 3522 3523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3524 desc.params.set_phy.lport_num = pi->lport; 3525 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3526 3527 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3528 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3529 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3530 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3531 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3532 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3533 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3534 cfg->low_power_ctrl_an); 3535 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3536 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3537 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3538 cfg->link_fec_opt); 3539 3540 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3541 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3542 status = 0; 3543 3544 if (!status) 3545 pi->phy.curr_user_phy_cfg = *cfg; 3546 3547 return status; 3548 } 3549 3550 /** 3551 * ice_update_link_info - update status of the HW network link 3552 * @pi: port info structure of the interested logical port 3553 */ 3554 int ice_update_link_info(struct ice_port_info *pi) 3555 { 3556 struct ice_link_status *li; 3557 int status; 3558 3559 if (!pi) 3560 return -EINVAL; 3561 3562 li = &pi->phy.link_info; 3563 3564 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3565 if (status) 3566 return status; 3567 3568 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3569 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3570 3571 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3572 if (!pcaps) 3573 return -ENOMEM; 3574 3575 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3576 pcaps, NULL); 3577 } 3578 3579 return status; 3580 } 3581 3582 /** 3583 * ice_aq_get_phy_equalization - function to read serdes equaliser 3584 * value from firmware using admin queue command. 3585 * @hw: pointer to the HW struct 3586 * @data_in: represents the serdes equalization parameter requested 3587 * @op_code: represents the serdes number and flag to represent tx or rx 3588 * @serdes_num: represents the serdes number 3589 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3590 * 3591 * Return: non-zero status on error and 0 on success. 3592 */ 3593 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3594 u8 serdes_num, int *output) 3595 { 3596 struct ice_aqc_dnl_call_command *cmd; 3597 struct ice_aqc_dnl_call buf = {}; 3598 struct ice_aq_desc desc; 3599 int err; 3600 3601 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3602 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3603 cpu_to_le16(op_code | (serdes_num & 0xF)); 3604 cmd = &desc.params.dnl_call; 3605 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3606 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF | 3607 ICE_AQ_FLAG_RD | 3608 ICE_AQ_FLAG_SI); 3609 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3610 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3611 3612 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3613 NULL); 3614 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3615 3616 return err; 3617 } 3618 3619 #define FEC_REG_PORT(port) { \ 3620 FEC_CORR_LOW_REG_PORT##port, \ 3621 FEC_CORR_HIGH_REG_PORT##port, \ 3622 FEC_UNCORR_LOW_REG_PORT##port, \ 3623 FEC_UNCORR_HIGH_REG_PORT##port, \ 3624 } 3625 3626 static const u32 fec_reg[][ICE_FEC_MAX] = { 3627 FEC_REG_PORT(0), 3628 FEC_REG_PORT(1), 3629 FEC_REG_PORT(2), 3630 FEC_REG_PORT(3) 3631 }; 3632 3633 /** 3634 * ice_aq_get_fec_stats - reads fec stats from phy 3635 * @hw: pointer to the HW struct 3636 * @pcs_quad: represents pcsquad of user input serdes 3637 * @pcs_port: represents the pcs port number part of above pcs quad 3638 * @fec_type: represents FEC stats type 3639 * @output: pointer to the caller-supplied buffer to return requested fec stats 3640 * 3641 * Return: non-zero status on error and 0 on success. 3642 */ 3643 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3644 enum ice_fec_stats_types fec_type, u32 *output) 3645 { 3646 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI); 3647 struct ice_sbq_msg_input msg = {}; 3648 u32 receiver_id, reg_offset; 3649 int err; 3650 3651 if (pcs_port > 3) 3652 return -EINVAL; 3653 3654 reg_offset = fec_reg[pcs_port][fec_type]; 3655 3656 if (pcs_quad == 0) 3657 receiver_id = FEC_RECEIVER_ID_PCS0; 3658 else if (pcs_quad == 1) 3659 receiver_id = FEC_RECEIVER_ID_PCS1; 3660 else 3661 return -EINVAL; 3662 3663 msg.msg_addr_low = lower_16_bits(reg_offset); 3664 msg.msg_addr_high = receiver_id; 3665 msg.opcode = ice_sbq_msg_rd; 3666 msg.dest_dev = ice_sbq_dev_phy_0; 3667 3668 err = ice_sbq_rw_reg(hw, &msg, flag); 3669 if (err) 3670 return err; 3671 3672 *output = msg.data; 3673 return 0; 3674 } 3675 3676 /** 3677 * ice_cache_phy_user_req 3678 * @pi: port information structure 3679 * @cache_data: PHY logging data 3680 * @cache_mode: PHY logging mode 3681 * 3682 * Log the user request on (FC, FEC, SPEED) for later use. 3683 */ 3684 static void 3685 ice_cache_phy_user_req(struct ice_port_info *pi, 3686 struct ice_phy_cache_mode_data cache_data, 3687 enum ice_phy_cache_mode cache_mode) 3688 { 3689 if (!pi) 3690 return; 3691 3692 switch (cache_mode) { 3693 case ICE_FC_MODE: 3694 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3695 break; 3696 case ICE_SPEED_MODE: 3697 pi->phy.curr_user_speed_req = 3698 cache_data.data.curr_user_speed_req; 3699 break; 3700 case ICE_FEC_MODE: 3701 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3702 break; 3703 default: 3704 break; 3705 } 3706 } 3707 3708 /** 3709 * ice_caps_to_fc_mode 3710 * @caps: PHY capabilities 3711 * 3712 * Convert PHY FC capabilities to ice FC mode 3713 */ 3714 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3715 { 3716 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3717 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3718 return ICE_FC_FULL; 3719 3720 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3721 return ICE_FC_TX_PAUSE; 3722 3723 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3724 return ICE_FC_RX_PAUSE; 3725 3726 return ICE_FC_NONE; 3727 } 3728 3729 /** 3730 * ice_caps_to_fec_mode 3731 * @caps: PHY capabilities 3732 * @fec_options: Link FEC options 3733 * 3734 * Convert PHY FEC capabilities to ice FEC mode 3735 */ 3736 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3737 { 3738 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3739 return ICE_FEC_AUTO; 3740 3741 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3742 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3743 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3744 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3745 return ICE_FEC_BASER; 3746 3747 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3748 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3749 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3750 return ICE_FEC_RS; 3751 3752 return ICE_FEC_NONE; 3753 } 3754 3755 /** 3756 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3757 * @pi: port information structure 3758 * @cfg: PHY configuration data to set FC mode 3759 * @req_mode: FC mode to configure 3760 */ 3761 int 3762 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3763 enum ice_fc_mode req_mode) 3764 { 3765 struct ice_phy_cache_mode_data cache_data; 3766 u8 pause_mask = 0x0; 3767 3768 if (!pi || !cfg) 3769 return -EINVAL; 3770 3771 switch (req_mode) { 3772 case ICE_FC_FULL: 3773 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3774 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3775 break; 3776 case ICE_FC_RX_PAUSE: 3777 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3778 break; 3779 case ICE_FC_TX_PAUSE: 3780 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3781 break; 3782 default: 3783 break; 3784 } 3785 3786 /* clear the old pause settings */ 3787 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3788 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3789 3790 /* set the new capabilities */ 3791 cfg->caps |= pause_mask; 3792 3793 /* Cache user FC request */ 3794 cache_data.data.curr_user_fc_req = req_mode; 3795 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3796 3797 return 0; 3798 } 3799 3800 /** 3801 * ice_set_fc 3802 * @pi: port information structure 3803 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3804 * @ena_auto_link_update: enable automatic link update 3805 * 3806 * Set the requested flow control mode. 3807 */ 3808 int 3809 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3810 { 3811 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3812 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3813 struct ice_hw *hw; 3814 int status; 3815 3816 if (!pi || !aq_failures) 3817 return -EINVAL; 3818 3819 *aq_failures = 0; 3820 hw = pi->hw; 3821 3822 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3823 if (!pcaps) 3824 return -ENOMEM; 3825 3826 /* Get the current PHY config */ 3827 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3828 pcaps, NULL); 3829 if (status) { 3830 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3831 goto out; 3832 } 3833 3834 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3835 3836 /* Configure the set PHY data */ 3837 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3838 if (status) 3839 goto out; 3840 3841 /* If the capabilities have changed, then set the new config */ 3842 if (cfg.caps != pcaps->caps) { 3843 int retry_count, retry_max = 10; 3844 3845 /* Auto restart link so settings take effect */ 3846 if (ena_auto_link_update) 3847 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3848 3849 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3850 if (status) { 3851 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3852 goto out; 3853 } 3854 3855 /* Update the link info 3856 * It sometimes takes a really long time for link to 3857 * come back from the atomic reset. Thus, we wait a 3858 * little bit. 3859 */ 3860 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3861 status = ice_update_link_info(pi); 3862 3863 if (!status) 3864 break; 3865 3866 mdelay(100); 3867 } 3868 3869 if (status) 3870 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3871 } 3872 3873 out: 3874 return status; 3875 } 3876 3877 /** 3878 * ice_phy_caps_equals_cfg 3879 * @phy_caps: PHY capabilities 3880 * @phy_cfg: PHY configuration 3881 * 3882 * Helper function to determine if PHY capabilities matches PHY 3883 * configuration 3884 */ 3885 bool 3886 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3887 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3888 { 3889 u8 caps_mask, cfg_mask; 3890 3891 if (!phy_caps || !phy_cfg) 3892 return false; 3893 3894 /* These bits are not common between capabilities and configuration. 3895 * Do not use them to determine equality. 3896 */ 3897 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3898 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3899 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3900 3901 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3902 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3903 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3904 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3905 phy_caps->eee_cap != phy_cfg->eee_cap || 3906 phy_caps->eeer_value != phy_cfg->eeer_value || 3907 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3908 return false; 3909 3910 return true; 3911 } 3912 3913 /** 3914 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3915 * @pi: port information structure 3916 * @caps: PHY ability structure to copy date from 3917 * @cfg: PHY configuration structure to copy data to 3918 * 3919 * Helper function to copy AQC PHY get ability data to PHY set configuration 3920 * data structure 3921 */ 3922 void 3923 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3924 struct ice_aqc_get_phy_caps_data *caps, 3925 struct ice_aqc_set_phy_cfg_data *cfg) 3926 { 3927 if (!pi || !caps || !cfg) 3928 return; 3929 3930 memset(cfg, 0, sizeof(*cfg)); 3931 cfg->phy_type_low = caps->phy_type_low; 3932 cfg->phy_type_high = caps->phy_type_high; 3933 cfg->caps = caps->caps; 3934 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3935 cfg->eee_cap = caps->eee_cap; 3936 cfg->eeer_value = caps->eeer_value; 3937 cfg->link_fec_opt = caps->link_fec_options; 3938 cfg->module_compliance_enforcement = 3939 caps->module_compliance_enforcement; 3940 } 3941 3942 /** 3943 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3944 * @pi: port information structure 3945 * @cfg: PHY configuration data to set FEC mode 3946 * @fec: FEC mode to configure 3947 */ 3948 int 3949 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3950 enum ice_fec_mode fec) 3951 { 3952 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3953 struct ice_hw *hw; 3954 int status; 3955 3956 if (!pi || !cfg) 3957 return -EINVAL; 3958 3959 hw = pi->hw; 3960 3961 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3962 if (!pcaps) 3963 return -ENOMEM; 3964 3965 status = ice_aq_get_phy_caps(pi, false, 3966 (ice_fw_supports_report_dflt_cfg(hw) ? 3967 ICE_AQC_REPORT_DFLT_CFG : 3968 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3969 if (status) 3970 goto out; 3971 3972 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3973 cfg->link_fec_opt = pcaps->link_fec_options; 3974 3975 switch (fec) { 3976 case ICE_FEC_BASER: 3977 /* Clear RS bits, and AND BASE-R ability 3978 * bits and OR request bits. 3979 */ 3980 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3981 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3982 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3983 ICE_AQC_PHY_FEC_25G_KR_REQ; 3984 break; 3985 case ICE_FEC_RS: 3986 /* Clear BASE-R bits, and AND RS ability 3987 * bits and OR request bits. 3988 */ 3989 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3990 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3991 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3992 break; 3993 case ICE_FEC_NONE: 3994 /* Clear all FEC option bits. */ 3995 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3996 break; 3997 case ICE_FEC_AUTO: 3998 /* AND auto FEC bit, and all caps bits. */ 3999 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4000 cfg->link_fec_opt |= pcaps->link_fec_options; 4001 break; 4002 default: 4003 status = -EINVAL; 4004 break; 4005 } 4006 4007 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4008 !ice_fw_supports_report_dflt_cfg(hw)) { 4009 struct ice_link_default_override_tlv tlv = { 0 }; 4010 4011 status = ice_get_link_default_override(&tlv, pi); 4012 if (status) 4013 goto out; 4014 4015 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4016 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4017 cfg->link_fec_opt = tlv.fec_options; 4018 } 4019 4020 out: 4021 return status; 4022 } 4023 4024 /** 4025 * ice_get_link_status - get status of the HW network link 4026 * @pi: port information structure 4027 * @link_up: pointer to bool (true/false = linkup/linkdown) 4028 * 4029 * Variable link_up is true if link is up, false if link is down. 4030 * The variable link_up is invalid if status is non zero. As a 4031 * result of this call, link status reporting becomes enabled 4032 */ 4033 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4034 { 4035 struct ice_phy_info *phy_info; 4036 int status = 0; 4037 4038 if (!pi || !link_up) 4039 return -EINVAL; 4040 4041 phy_info = &pi->phy; 4042 4043 if (phy_info->get_link_info) { 4044 status = ice_update_link_info(pi); 4045 4046 if (status) 4047 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4048 status); 4049 } 4050 4051 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4052 4053 return status; 4054 } 4055 4056 /** 4057 * ice_aq_set_link_restart_an 4058 * @pi: pointer to the port information structure 4059 * @ena_link: if true: enable link, if false: disable link 4060 * @cd: pointer to command details structure or NULL 4061 * 4062 * Sets up the link and restarts the Auto-Negotiation over the link. 4063 */ 4064 int 4065 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4066 struct ice_sq_cd *cd) 4067 { 4068 struct ice_aqc_restart_an *cmd; 4069 struct ice_aq_desc desc; 4070 4071 cmd = &desc.params.restart_an; 4072 4073 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4074 4075 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4076 cmd->lport_num = pi->lport; 4077 if (ena_link) 4078 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4079 else 4080 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4081 4082 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4083 } 4084 4085 /** 4086 * ice_aq_set_event_mask 4087 * @hw: pointer to the HW struct 4088 * @port_num: port number of the physical function 4089 * @mask: event mask to be set 4090 * @cd: pointer to command details structure or NULL 4091 * 4092 * Set event mask (0x0613) 4093 */ 4094 int 4095 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4096 struct ice_sq_cd *cd) 4097 { 4098 struct ice_aqc_set_event_mask *cmd; 4099 struct ice_aq_desc desc; 4100 4101 cmd = &desc.params.set_event_mask; 4102 4103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4104 4105 cmd->lport_num = port_num; 4106 4107 cmd->event_mask = cpu_to_le16(mask); 4108 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4109 } 4110 4111 /** 4112 * ice_aq_set_mac_loopback 4113 * @hw: pointer to the HW struct 4114 * @ena_lpbk: Enable or Disable loopback 4115 * @cd: pointer to command details structure or NULL 4116 * 4117 * Enable/disable loopback on a given port 4118 */ 4119 int 4120 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4121 { 4122 struct ice_aqc_set_mac_lb *cmd; 4123 struct ice_aq_desc desc; 4124 4125 cmd = &desc.params.set_mac_lb; 4126 4127 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4128 if (ena_lpbk) 4129 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4130 4131 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4132 } 4133 4134 /** 4135 * ice_aq_set_port_id_led 4136 * @pi: pointer to the port information 4137 * @is_orig_mode: is this LED set to original mode (by the net-list) 4138 * @cd: pointer to command details structure or NULL 4139 * 4140 * Set LED value for the given port (0x06e9) 4141 */ 4142 int 4143 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4144 struct ice_sq_cd *cd) 4145 { 4146 struct ice_aqc_set_port_id_led *cmd; 4147 struct ice_hw *hw = pi->hw; 4148 struct ice_aq_desc desc; 4149 4150 cmd = &desc.params.set_port_id_led; 4151 4152 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4153 4154 if (is_orig_mode) 4155 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4156 else 4157 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4158 4159 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4160 } 4161 4162 /** 4163 * ice_aq_get_port_options 4164 * @hw: pointer to the HW struct 4165 * @options: buffer for the resultant port options 4166 * @option_count: input - size of the buffer in port options structures, 4167 * output - number of returned port options 4168 * @lport: logical port to call the command with (optional) 4169 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4170 * when PF owns more than 1 port it must be true 4171 * @active_option_idx: index of active port option in returned buffer 4172 * @active_option_valid: active option in returned buffer is valid 4173 * @pending_option_idx: index of pending port option in returned buffer 4174 * @pending_option_valid: pending option in returned buffer is valid 4175 * 4176 * Calls Get Port Options AQC (0x06ea) and verifies result. 4177 */ 4178 int 4179 ice_aq_get_port_options(struct ice_hw *hw, 4180 struct ice_aqc_get_port_options_elem *options, 4181 u8 *option_count, u8 lport, bool lport_valid, 4182 u8 *active_option_idx, bool *active_option_valid, 4183 u8 *pending_option_idx, bool *pending_option_valid) 4184 { 4185 struct ice_aqc_get_port_options *cmd; 4186 struct ice_aq_desc desc; 4187 int status; 4188 u8 i; 4189 4190 /* options buffer shall be able to hold max returned options */ 4191 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4192 return -EINVAL; 4193 4194 cmd = &desc.params.get_port_options; 4195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4196 4197 if (lport_valid) 4198 cmd->lport_num = lport; 4199 cmd->lport_num_valid = lport_valid; 4200 4201 status = ice_aq_send_cmd(hw, &desc, options, 4202 *option_count * sizeof(*options), NULL); 4203 if (status) 4204 return status; 4205 4206 /* verify direct FW response & set output parameters */ 4207 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4208 cmd->port_options_count); 4209 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4210 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4211 cmd->port_options); 4212 if (*active_option_valid) { 4213 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4214 cmd->port_options); 4215 if (*active_option_idx > (*option_count - 1)) 4216 return -EIO; 4217 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4218 *active_option_idx); 4219 } 4220 4221 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4222 cmd->pending_port_option_status); 4223 if (*pending_option_valid) { 4224 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4225 cmd->pending_port_option_status); 4226 if (*pending_option_idx > (*option_count - 1)) 4227 return -EIO; 4228 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4229 *pending_option_idx); 4230 } 4231 4232 /* mask output options fields */ 4233 for (i = 0; i < *option_count; i++) { 4234 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4235 options[i].pmd); 4236 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4237 options[i].max_lane_speed); 4238 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4239 options[i].pmd, options[i].max_lane_speed); 4240 } 4241 4242 return 0; 4243 } 4244 4245 /** 4246 * ice_aq_set_port_option 4247 * @hw: pointer to the HW struct 4248 * @lport: logical port to call the command with 4249 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4250 * when PF owns more than 1 port it must be true 4251 * @new_option: new port option to be written 4252 * 4253 * Calls Set Port Options AQC (0x06eb). 4254 */ 4255 int 4256 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4257 u8 new_option) 4258 { 4259 struct ice_aqc_set_port_option *cmd; 4260 struct ice_aq_desc desc; 4261 4262 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4263 return -EINVAL; 4264 4265 cmd = &desc.params.set_port_option; 4266 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4267 4268 if (lport_valid) 4269 cmd->lport_num = lport; 4270 4271 cmd->lport_num_valid = lport_valid; 4272 cmd->selected_port_option = new_option; 4273 4274 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4275 } 4276 4277 /** 4278 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4279 * @hw: pointer to the hw struct 4280 * 4281 * Return: PHY lane number on success, negative error code otherwise. 4282 */ 4283 int ice_get_phy_lane_number(struct ice_hw *hw) 4284 { 4285 struct ice_aqc_get_port_options_elem *options; 4286 unsigned int lport = 0; 4287 unsigned int lane; 4288 int err; 4289 4290 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4291 if (!options) 4292 return -ENOMEM; 4293 4294 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4295 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4296 u8 speed, active_idx, pending_idx; 4297 bool active_valid, pending_valid; 4298 4299 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4300 true, &active_idx, &active_valid, 4301 &pending_idx, &pending_valid); 4302 if (err) 4303 goto err; 4304 4305 if (!active_valid) 4306 continue; 4307 4308 speed = options[active_idx].max_lane_speed; 4309 /* If we don't get speed for this lane, it's unoccupied */ 4310 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G) 4311 continue; 4312 4313 if (hw->pf_id == lport) { 4314 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4315 ice_is_dual(hw) && !ice_is_primary(hw)) 4316 lane += ICE_PORTS_PER_QUAD; 4317 kfree(options); 4318 return lane; 4319 } 4320 lport++; 4321 } 4322 4323 /* PHY lane not found */ 4324 err = -ENXIO; 4325 err: 4326 kfree(options); 4327 return err; 4328 } 4329 4330 /** 4331 * ice_aq_sff_eeprom 4332 * @hw: pointer to the HW struct 4333 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4334 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4335 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4336 * @page: QSFP page 4337 * @set_page: set or ignore the page 4338 * @data: pointer to data buffer to be read/written to the I2C device. 4339 * @length: 1-16 for read, 1 for write. 4340 * @write: 0 read, 1 for write. 4341 * @cd: pointer to command details structure or NULL 4342 * 4343 * Read/Write SFF EEPROM (0x06EE) 4344 */ 4345 int 4346 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4347 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4348 bool write, struct ice_sq_cd *cd) 4349 { 4350 struct ice_aqc_sff_eeprom *cmd; 4351 struct ice_aq_desc desc; 4352 u16 i2c_bus_addr; 4353 int status; 4354 4355 if (!data || (mem_addr & 0xff00)) 4356 return -EINVAL; 4357 4358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4359 cmd = &desc.params.read_write_sff_param; 4360 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4361 cmd->lport_num = (u8)(lport & 0xff); 4362 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4363 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4364 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4365 if (write) 4366 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4367 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4368 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4369 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4370 4371 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4372 return status; 4373 } 4374 4375 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4376 { 4377 switch (type) { 4378 case ICE_LUT_VSI: 4379 return ICE_LUT_VSI_SIZE; 4380 case ICE_LUT_GLOBAL: 4381 return ICE_LUT_GLOBAL_SIZE; 4382 case ICE_LUT_PF: 4383 return ICE_LUT_PF_SIZE; 4384 } 4385 WARN_ONCE(1, "incorrect type passed"); 4386 return ICE_LUT_VSI_SIZE; 4387 } 4388 4389 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4390 { 4391 switch (size) { 4392 case ICE_LUT_VSI_SIZE: 4393 return ICE_AQC_LUT_SIZE_SMALL; 4394 case ICE_LUT_GLOBAL_SIZE: 4395 return ICE_AQC_LUT_SIZE_512; 4396 case ICE_LUT_PF_SIZE: 4397 return ICE_AQC_LUT_SIZE_2K; 4398 } 4399 WARN_ONCE(1, "incorrect size passed"); 4400 return 0; 4401 } 4402 4403 /** 4404 * __ice_aq_get_set_rss_lut 4405 * @hw: pointer to the hardware structure 4406 * @params: RSS LUT parameters 4407 * @set: set true to set the table, false to get the table 4408 * 4409 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4410 */ 4411 static int 4412 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4413 struct ice_aq_get_set_rss_lut_params *params, bool set) 4414 { 4415 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4416 enum ice_lut_type lut_type = params->lut_type; 4417 struct ice_aqc_get_set_rss_lut *desc_params; 4418 enum ice_aqc_lut_flags flags; 4419 enum ice_lut_size lut_size; 4420 struct ice_aq_desc desc; 4421 u8 *lut = params->lut; 4422 4423 4424 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4425 return -EINVAL; 4426 4427 lut_size = ice_lut_type_to_size(lut_type); 4428 if (lut_size > params->lut_size) 4429 return -EINVAL; 4430 else if (set && lut_size != params->lut_size) 4431 return -EINVAL; 4432 4433 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4434 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4435 if (set) 4436 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4437 4438 desc_params = &desc.params.get_set_rss_lut; 4439 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4440 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4441 4442 if (lut_type == ICE_LUT_GLOBAL) 4443 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4444 params->global_lut_id); 4445 4446 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4447 desc_params->flags = cpu_to_le16(flags); 4448 4449 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4450 } 4451 4452 /** 4453 * ice_aq_get_rss_lut 4454 * @hw: pointer to the hardware structure 4455 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4456 * 4457 * get the RSS lookup table, PF or VSI type 4458 */ 4459 int 4460 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4461 { 4462 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4463 } 4464 4465 /** 4466 * ice_aq_set_rss_lut 4467 * @hw: pointer to the hardware structure 4468 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4469 * 4470 * set the RSS lookup table, PF or VSI type 4471 */ 4472 int 4473 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4474 { 4475 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4476 } 4477 4478 /** 4479 * __ice_aq_get_set_rss_key 4480 * @hw: pointer to the HW struct 4481 * @vsi_id: VSI FW index 4482 * @key: pointer to key info struct 4483 * @set: set true to set the key, false to get the key 4484 * 4485 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4486 */ 4487 static int 4488 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4489 struct ice_aqc_get_set_rss_keys *key, bool set) 4490 { 4491 struct ice_aqc_get_set_rss_key *desc_params; 4492 u16 key_size = sizeof(*key); 4493 struct ice_aq_desc desc; 4494 4495 if (set) { 4496 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4497 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4498 } else { 4499 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4500 } 4501 4502 desc_params = &desc.params.get_set_rss_key; 4503 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4504 4505 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4506 } 4507 4508 /** 4509 * ice_aq_get_rss_key 4510 * @hw: pointer to the HW struct 4511 * @vsi_handle: software VSI handle 4512 * @key: pointer to key info struct 4513 * 4514 * get the RSS key per VSI 4515 */ 4516 int 4517 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4518 struct ice_aqc_get_set_rss_keys *key) 4519 { 4520 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4521 return -EINVAL; 4522 4523 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4524 key, false); 4525 } 4526 4527 /** 4528 * ice_aq_set_rss_key 4529 * @hw: pointer to the HW struct 4530 * @vsi_handle: software VSI handle 4531 * @keys: pointer to key info struct 4532 * 4533 * set the RSS key per VSI 4534 */ 4535 int 4536 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4537 struct ice_aqc_get_set_rss_keys *keys) 4538 { 4539 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4540 return -EINVAL; 4541 4542 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4543 keys, true); 4544 } 4545 4546 /** 4547 * ice_aq_add_lan_txq 4548 * @hw: pointer to the hardware structure 4549 * @num_qgrps: Number of added queue groups 4550 * @qg_list: list of queue groups to be added 4551 * @buf_size: size of buffer for indirect command 4552 * @cd: pointer to command details structure or NULL 4553 * 4554 * Add Tx LAN queue (0x0C30) 4555 * 4556 * NOTE: 4557 * Prior to calling add Tx LAN queue: 4558 * Initialize the following as part of the Tx queue context: 4559 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4560 * Cache profile and Packet shaper profile. 4561 * 4562 * After add Tx LAN queue AQ command is completed: 4563 * Interrupts should be associated with specific queues, 4564 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4565 * flow. 4566 */ 4567 static int 4568 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4569 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4570 struct ice_sq_cd *cd) 4571 { 4572 struct ice_aqc_add_tx_qgrp *list; 4573 struct ice_aqc_add_txqs *cmd; 4574 struct ice_aq_desc desc; 4575 u16 i, sum_size = 0; 4576 4577 cmd = &desc.params.add_txqs; 4578 4579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4580 4581 if (!qg_list) 4582 return -EINVAL; 4583 4584 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4585 return -EINVAL; 4586 4587 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4588 sum_size += struct_size(list, txqs, list->num_txqs); 4589 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4590 list->num_txqs); 4591 } 4592 4593 if (buf_size != sum_size) 4594 return -EINVAL; 4595 4596 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4597 4598 cmd->num_qgrps = num_qgrps; 4599 4600 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4601 } 4602 4603 /** 4604 * ice_aq_dis_lan_txq 4605 * @hw: pointer to the hardware structure 4606 * @num_qgrps: number of groups in the list 4607 * @qg_list: the list of groups to disable 4608 * @buf_size: the total size of the qg_list buffer in bytes 4609 * @rst_src: if called due to reset, specifies the reset source 4610 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4611 * @cd: pointer to command details structure or NULL 4612 * 4613 * Disable LAN Tx queue (0x0C31) 4614 */ 4615 static int 4616 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4617 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4618 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4619 struct ice_sq_cd *cd) 4620 { 4621 struct ice_aqc_dis_txq_item *item; 4622 struct ice_aqc_dis_txqs *cmd; 4623 struct ice_aq_desc desc; 4624 u16 vmvf_and_timeout; 4625 u16 i, sz = 0; 4626 int status; 4627 4628 cmd = &desc.params.dis_txqs; 4629 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4630 4631 /* qg_list can be NULL only in VM/VF reset flow */ 4632 if (!qg_list && !rst_src) 4633 return -EINVAL; 4634 4635 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4636 return -EINVAL; 4637 4638 cmd->num_entries = num_qgrps; 4639 4640 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4641 4642 switch (rst_src) { 4643 case ICE_VM_RESET: 4644 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4645 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4646 break; 4647 case ICE_VF_RESET: 4648 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4649 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4650 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4651 ICE_AQC_Q_DIS_VMVF_NUM_M; 4652 break; 4653 case ICE_NO_RESET: 4654 default: 4655 break; 4656 } 4657 4658 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4659 4660 /* flush pipe on time out */ 4661 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4662 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4663 if (!qg_list) 4664 goto do_aq; 4665 4666 /* set RD bit to indicate that command buffer is provided by the driver 4667 * and it needs to be read by the firmware 4668 */ 4669 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4670 4671 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4672 u16 item_size = struct_size(item, q_id, item->num_qs); 4673 4674 /* If the num of queues is even, add 2 bytes of padding */ 4675 if ((item->num_qs % 2) == 0) 4676 item_size += 2; 4677 4678 sz += item_size; 4679 4680 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4681 } 4682 4683 if (buf_size != sz) 4684 return -EINVAL; 4685 4686 do_aq: 4687 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4688 if (status) { 4689 if (!qg_list) 4690 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4691 vmvf_num, hw->adminq.sq_last_status); 4692 else 4693 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4694 le16_to_cpu(qg_list[0].q_id[0]), 4695 hw->adminq.sq_last_status); 4696 } 4697 return status; 4698 } 4699 4700 /** 4701 * ice_aq_cfg_lan_txq 4702 * @hw: pointer to the hardware structure 4703 * @buf: buffer for command 4704 * @buf_size: size of buffer in bytes 4705 * @num_qs: number of queues being configured 4706 * @oldport: origination lport 4707 * @newport: destination lport 4708 * @cd: pointer to command details structure or NULL 4709 * 4710 * Move/Configure LAN Tx queue (0x0C32) 4711 * 4712 * There is a better AQ command to use for moving nodes, so only coding 4713 * this one for configuring the node. 4714 */ 4715 int 4716 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4717 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4718 struct ice_sq_cd *cd) 4719 { 4720 struct ice_aqc_cfg_txqs *cmd; 4721 struct ice_aq_desc desc; 4722 int status; 4723 4724 cmd = &desc.params.cfg_txqs; 4725 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4726 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4727 4728 if (!buf) 4729 return -EINVAL; 4730 4731 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4732 cmd->num_qs = num_qs; 4733 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4734 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4735 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4736 cmd->blocked_cgds = 0; 4737 4738 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4739 if (status) 4740 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4741 hw->adminq.sq_last_status); 4742 return status; 4743 } 4744 4745 /** 4746 * ice_aq_add_rdma_qsets 4747 * @hw: pointer to the hardware structure 4748 * @num_qset_grps: Number of RDMA Qset groups 4749 * @qset_list: list of Qset groups to be added 4750 * @buf_size: size of buffer for indirect command 4751 * @cd: pointer to command details structure or NULL 4752 * 4753 * Add Tx RDMA Qsets (0x0C33) 4754 */ 4755 static int 4756 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4757 struct ice_aqc_add_rdma_qset_data *qset_list, 4758 u16 buf_size, struct ice_sq_cd *cd) 4759 { 4760 struct ice_aqc_add_rdma_qset_data *list; 4761 struct ice_aqc_add_rdma_qset *cmd; 4762 struct ice_aq_desc desc; 4763 u16 i, sum_size = 0; 4764 4765 cmd = &desc.params.add_rdma_qset; 4766 4767 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4768 4769 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4770 return -EINVAL; 4771 4772 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4773 u16 num_qsets = le16_to_cpu(list->num_qsets); 4774 4775 sum_size += struct_size(list, rdma_qsets, num_qsets); 4776 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4777 num_qsets); 4778 } 4779 4780 if (buf_size != sum_size) 4781 return -EINVAL; 4782 4783 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4784 4785 cmd->num_qset_grps = num_qset_grps; 4786 4787 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4788 } 4789 4790 /* End of FW Admin Queue command wrappers */ 4791 4792 /** 4793 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4794 * @hw: pointer to the HW struct 4795 * @vsi_handle: software VSI handle 4796 * @tc: TC number 4797 * @q_handle: software queue handle 4798 */ 4799 struct ice_q_ctx * 4800 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4801 { 4802 struct ice_vsi_ctx *vsi; 4803 struct ice_q_ctx *q_ctx; 4804 4805 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4806 if (!vsi) 4807 return NULL; 4808 if (q_handle >= vsi->num_lan_q_entries[tc]) 4809 return NULL; 4810 if (!vsi->lan_q_ctx[tc]) 4811 return NULL; 4812 q_ctx = vsi->lan_q_ctx[tc]; 4813 return &q_ctx[q_handle]; 4814 } 4815 4816 /** 4817 * ice_ena_vsi_txq 4818 * @pi: port information structure 4819 * @vsi_handle: software VSI handle 4820 * @tc: TC number 4821 * @q_handle: software queue handle 4822 * @num_qgrps: Number of added queue groups 4823 * @buf: list of queue groups to be added 4824 * @buf_size: size of buffer for indirect command 4825 * @cd: pointer to command details structure or NULL 4826 * 4827 * This function adds one LAN queue 4828 */ 4829 int 4830 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4831 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4832 struct ice_sq_cd *cd) 4833 { 4834 struct ice_aqc_txsched_elem_data node = { 0 }; 4835 struct ice_sched_node *parent; 4836 struct ice_q_ctx *q_ctx; 4837 struct ice_hw *hw; 4838 int status; 4839 4840 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4841 return -EIO; 4842 4843 if (num_qgrps > 1 || buf->num_txqs > 1) 4844 return -ENOSPC; 4845 4846 hw = pi->hw; 4847 4848 if (!ice_is_vsi_valid(hw, vsi_handle)) 4849 return -EINVAL; 4850 4851 mutex_lock(&pi->sched_lock); 4852 4853 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4854 if (!q_ctx) { 4855 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4856 q_handle); 4857 status = -EINVAL; 4858 goto ena_txq_exit; 4859 } 4860 4861 /* find a parent node */ 4862 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4863 ICE_SCHED_NODE_OWNER_LAN); 4864 if (!parent) { 4865 status = -EINVAL; 4866 goto ena_txq_exit; 4867 } 4868 4869 buf->parent_teid = parent->info.node_teid; 4870 node.parent_teid = parent->info.node_teid; 4871 /* Mark that the values in the "generic" section as valid. The default 4872 * value in the "generic" section is zero. This means that : 4873 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4874 * - 0 priority among siblings, indicated by Bit 1-3. 4875 * - WFQ, indicated by Bit 4. 4876 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4877 * Bit 5-6. 4878 * - Bit 7 is reserved. 4879 * Without setting the generic section as valid in valid_sections, the 4880 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4881 */ 4882 buf->txqs[0].info.valid_sections = 4883 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4884 ICE_AQC_ELEM_VALID_EIR; 4885 buf->txqs[0].info.generic = 0; 4886 buf->txqs[0].info.cir_bw.bw_profile_idx = 4887 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4888 buf->txqs[0].info.cir_bw.bw_alloc = 4889 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4890 buf->txqs[0].info.eir_bw.bw_profile_idx = 4891 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4892 buf->txqs[0].info.eir_bw.bw_alloc = 4893 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4894 4895 /* add the LAN queue */ 4896 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4897 if (status) { 4898 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4899 le16_to_cpu(buf->txqs[0].txq_id), 4900 hw->adminq.sq_last_status); 4901 goto ena_txq_exit; 4902 } 4903 4904 node.node_teid = buf->txqs[0].q_teid; 4905 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4906 q_ctx->q_handle = q_handle; 4907 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4908 4909 /* add a leaf node into scheduler tree queue layer */ 4910 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4911 if (!status) 4912 status = ice_sched_replay_q_bw(pi, q_ctx); 4913 4914 ena_txq_exit: 4915 mutex_unlock(&pi->sched_lock); 4916 return status; 4917 } 4918 4919 /** 4920 * ice_dis_vsi_txq 4921 * @pi: port information structure 4922 * @vsi_handle: software VSI handle 4923 * @tc: TC number 4924 * @num_queues: number of queues 4925 * @q_handles: pointer to software queue handle array 4926 * @q_ids: pointer to the q_id array 4927 * @q_teids: pointer to queue node teids 4928 * @rst_src: if called due to reset, specifies the reset source 4929 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4930 * @cd: pointer to command details structure or NULL 4931 * 4932 * This function removes queues and their corresponding nodes in SW DB 4933 */ 4934 int 4935 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4936 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4937 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4938 struct ice_sq_cd *cd) 4939 { 4940 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4941 u16 i, buf_size = __struct_size(qg_list); 4942 struct ice_q_ctx *q_ctx; 4943 int status = -ENOENT; 4944 struct ice_hw *hw; 4945 4946 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4947 return -EIO; 4948 4949 hw = pi->hw; 4950 4951 if (!num_queues) { 4952 /* if queue is disabled already yet the disable queue command 4953 * has to be sent to complete the VF reset, then call 4954 * ice_aq_dis_lan_txq without any queue information 4955 */ 4956 if (rst_src) 4957 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4958 vmvf_num, NULL); 4959 return -EIO; 4960 } 4961 4962 mutex_lock(&pi->sched_lock); 4963 4964 for (i = 0; i < num_queues; i++) { 4965 struct ice_sched_node *node; 4966 4967 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4968 if (!node) 4969 continue; 4970 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4971 if (!q_ctx) { 4972 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4973 q_handles[i]); 4974 continue; 4975 } 4976 if (q_ctx->q_handle != q_handles[i]) { 4977 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4978 q_ctx->q_handle, q_handles[i]); 4979 continue; 4980 } 4981 qg_list->parent_teid = node->info.parent_teid; 4982 qg_list->num_qs = 1; 4983 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4984 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4985 vmvf_num, cd); 4986 4987 if (status) 4988 break; 4989 ice_free_sched_node(pi, node); 4990 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4991 q_ctx->q_teid = ICE_INVAL_TEID; 4992 } 4993 mutex_unlock(&pi->sched_lock); 4994 return status; 4995 } 4996 4997 /** 4998 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4999 * @pi: port information structure 5000 * @vsi_handle: software VSI handle 5001 * @tc_bitmap: TC bitmap 5002 * @maxqs: max queues array per TC 5003 * @owner: LAN or RDMA 5004 * 5005 * This function adds/updates the VSI queues per TC. 5006 */ 5007 static int 5008 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5009 u16 *maxqs, u8 owner) 5010 { 5011 int status = 0; 5012 u8 i; 5013 5014 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5015 return -EIO; 5016 5017 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5018 return -EINVAL; 5019 5020 mutex_lock(&pi->sched_lock); 5021 5022 ice_for_each_traffic_class(i) { 5023 /* configuration is possible only if TC node is present */ 5024 if (!ice_sched_get_tc_node(pi, i)) 5025 continue; 5026 5027 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5028 ice_is_tc_ena(tc_bitmap, i)); 5029 if (status) 5030 break; 5031 } 5032 5033 mutex_unlock(&pi->sched_lock); 5034 return status; 5035 } 5036 5037 /** 5038 * ice_cfg_vsi_lan - configure VSI LAN queues 5039 * @pi: port information structure 5040 * @vsi_handle: software VSI handle 5041 * @tc_bitmap: TC bitmap 5042 * @max_lanqs: max LAN queues array per TC 5043 * 5044 * This function adds/updates the VSI LAN queues per TC. 5045 */ 5046 int 5047 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5048 u16 *max_lanqs) 5049 { 5050 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5051 ICE_SCHED_NODE_OWNER_LAN); 5052 } 5053 5054 /** 5055 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5056 * @pi: port information structure 5057 * @vsi_handle: software VSI handle 5058 * @tc_bitmap: TC bitmap 5059 * @max_rdmaqs: max RDMA queues array per TC 5060 * 5061 * This function adds/updates the VSI RDMA queues per TC. 5062 */ 5063 int 5064 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5065 u16 *max_rdmaqs) 5066 { 5067 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5068 ICE_SCHED_NODE_OWNER_RDMA); 5069 } 5070 5071 /** 5072 * ice_ena_vsi_rdma_qset 5073 * @pi: port information structure 5074 * @vsi_handle: software VSI handle 5075 * @tc: TC number 5076 * @rdma_qset: pointer to RDMA Qset 5077 * @num_qsets: number of RDMA Qsets 5078 * @qset_teid: pointer to Qset node TEIDs 5079 * 5080 * This function adds RDMA Qset 5081 */ 5082 int 5083 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5084 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5085 { 5086 struct ice_aqc_txsched_elem_data node = { 0 }; 5087 struct ice_aqc_add_rdma_qset_data *buf; 5088 struct ice_sched_node *parent; 5089 struct ice_hw *hw; 5090 u16 i, buf_size; 5091 int ret; 5092 5093 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5094 return -EIO; 5095 hw = pi->hw; 5096 5097 if (!ice_is_vsi_valid(hw, vsi_handle)) 5098 return -EINVAL; 5099 5100 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5101 buf = kzalloc(buf_size, GFP_KERNEL); 5102 if (!buf) 5103 return -ENOMEM; 5104 mutex_lock(&pi->sched_lock); 5105 5106 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5107 ICE_SCHED_NODE_OWNER_RDMA); 5108 if (!parent) { 5109 ret = -EINVAL; 5110 goto rdma_error_exit; 5111 } 5112 buf->parent_teid = parent->info.node_teid; 5113 node.parent_teid = parent->info.node_teid; 5114 5115 buf->num_qsets = cpu_to_le16(num_qsets); 5116 for (i = 0; i < num_qsets; i++) { 5117 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5118 buf->rdma_qsets[i].info.valid_sections = 5119 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5120 ICE_AQC_ELEM_VALID_EIR; 5121 buf->rdma_qsets[i].info.generic = 0; 5122 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5123 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5124 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5125 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5126 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5127 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5128 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5129 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5130 } 5131 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5132 if (ret) { 5133 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5134 goto rdma_error_exit; 5135 } 5136 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5137 for (i = 0; i < num_qsets; i++) { 5138 node.node_teid = buf->rdma_qsets[i].qset_teid; 5139 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5140 &node, NULL); 5141 if (ret) 5142 break; 5143 qset_teid[i] = le32_to_cpu(node.node_teid); 5144 } 5145 rdma_error_exit: 5146 mutex_unlock(&pi->sched_lock); 5147 kfree(buf); 5148 return ret; 5149 } 5150 5151 /** 5152 * ice_dis_vsi_rdma_qset - free RDMA resources 5153 * @pi: port_info struct 5154 * @count: number of RDMA Qsets to free 5155 * @qset_teid: TEID of Qset node 5156 * @q_id: list of queue IDs being disabled 5157 */ 5158 int 5159 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5160 u16 *q_id) 5161 { 5162 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5163 u16 qg_size = __struct_size(qg_list); 5164 struct ice_hw *hw; 5165 int status = 0; 5166 int i; 5167 5168 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5169 return -EIO; 5170 5171 hw = pi->hw; 5172 5173 mutex_lock(&pi->sched_lock); 5174 5175 for (i = 0; i < count; i++) { 5176 struct ice_sched_node *node; 5177 5178 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5179 if (!node) 5180 continue; 5181 5182 qg_list->parent_teid = node->info.parent_teid; 5183 qg_list->num_qs = 1; 5184 qg_list->q_id[0] = 5185 cpu_to_le16(q_id[i] | 5186 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5187 5188 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5189 ICE_NO_RESET, 0, NULL); 5190 if (status) 5191 break; 5192 5193 ice_free_sched_node(pi, node); 5194 } 5195 5196 mutex_unlock(&pi->sched_lock); 5197 return status; 5198 } 5199 5200 /** 5201 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5202 * @hw: pointer to the HW struct 5203 * @dpll_idx: index of dpll to be measured 5204 * @meas: array to be filled with results 5205 * @meas_num: max number of results array can hold 5206 * 5207 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5208 * pins on given dpll. 5209 * 5210 * Return: 0 on success or negative value on failure. 5211 */ 5212 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5213 struct ice_cgu_input_measure *meas, 5214 u16 meas_num) 5215 { 5216 struct ice_aqc_get_cgu_input_measure *cmd; 5217 struct ice_aq_desc desc; 5218 5219 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5220 cmd = &desc.params.get_cgu_input_measure; 5221 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5222 5223 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5224 } 5225 5226 /** 5227 * ice_aq_get_cgu_abilities - get cgu abilities 5228 * @hw: pointer to the HW struct 5229 * @abilities: CGU abilities 5230 * 5231 * Get CGU abilities (0x0C61) 5232 * Return: 0 on success or negative value on failure. 5233 */ 5234 int 5235 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5236 struct ice_aqc_get_cgu_abilities *abilities) 5237 { 5238 struct ice_aq_desc desc; 5239 5240 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5241 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5242 } 5243 5244 /** 5245 * ice_aq_set_input_pin_cfg - set input pin config 5246 * @hw: pointer to the HW struct 5247 * @input_idx: Input index 5248 * @flags1: Input flags 5249 * @flags2: Input flags 5250 * @freq: Frequency in Hz 5251 * @phase_delay: Delay in ps 5252 * 5253 * Set CGU input config (0x0C62) 5254 * Return: 0 on success or negative value on failure. 5255 */ 5256 int 5257 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5258 u32 freq, s32 phase_delay) 5259 { 5260 struct ice_aqc_set_cgu_input_config *cmd; 5261 struct ice_aq_desc desc; 5262 5263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5264 cmd = &desc.params.set_cgu_input_config; 5265 cmd->input_idx = input_idx; 5266 cmd->flags1 = flags1; 5267 cmd->flags2 = flags2; 5268 cmd->freq = cpu_to_le32(freq); 5269 cmd->phase_delay = cpu_to_le32(phase_delay); 5270 5271 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5272 } 5273 5274 /** 5275 * ice_aq_get_input_pin_cfg - get input pin config 5276 * @hw: pointer to the HW struct 5277 * @input_idx: Input index 5278 * @status: Pin status 5279 * @type: Pin type 5280 * @flags1: Input flags 5281 * @flags2: Input flags 5282 * @freq: Frequency in Hz 5283 * @phase_delay: Delay in ps 5284 * 5285 * Get CGU input config (0x0C63) 5286 * Return: 0 on success or negative value on failure. 5287 */ 5288 int 5289 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5290 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5291 { 5292 struct ice_aqc_get_cgu_input_config *cmd; 5293 struct ice_aq_desc desc; 5294 int ret; 5295 5296 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5297 cmd = &desc.params.get_cgu_input_config; 5298 cmd->input_idx = input_idx; 5299 5300 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5301 if (!ret) { 5302 if (status) 5303 *status = cmd->status; 5304 if (type) 5305 *type = cmd->type; 5306 if (flags1) 5307 *flags1 = cmd->flags1; 5308 if (flags2) 5309 *flags2 = cmd->flags2; 5310 if (freq) 5311 *freq = le32_to_cpu(cmd->freq); 5312 if (phase_delay) 5313 *phase_delay = le32_to_cpu(cmd->phase_delay); 5314 } 5315 5316 return ret; 5317 } 5318 5319 /** 5320 * ice_aq_set_output_pin_cfg - set output pin config 5321 * @hw: pointer to the HW struct 5322 * @output_idx: Output index 5323 * @flags: Output flags 5324 * @src_sel: Index of DPLL block 5325 * @freq: Output frequency 5326 * @phase_delay: Output phase compensation 5327 * 5328 * Set CGU output config (0x0C64) 5329 * Return: 0 on success or negative value on failure. 5330 */ 5331 int 5332 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5333 u8 src_sel, u32 freq, s32 phase_delay) 5334 { 5335 struct ice_aqc_set_cgu_output_config *cmd; 5336 struct ice_aq_desc desc; 5337 5338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5339 cmd = &desc.params.set_cgu_output_config; 5340 cmd->output_idx = output_idx; 5341 cmd->flags = flags; 5342 cmd->src_sel = src_sel; 5343 cmd->freq = cpu_to_le32(freq); 5344 cmd->phase_delay = cpu_to_le32(phase_delay); 5345 5346 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5347 } 5348 5349 /** 5350 * ice_aq_get_output_pin_cfg - get output pin config 5351 * @hw: pointer to the HW struct 5352 * @output_idx: Output index 5353 * @flags: Output flags 5354 * @src_sel: Internal DPLL source 5355 * @freq: Output frequency 5356 * @src_freq: Source frequency 5357 * 5358 * Get CGU output config (0x0C65) 5359 * Return: 0 on success or negative value on failure. 5360 */ 5361 int 5362 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5363 u8 *src_sel, u32 *freq, u32 *src_freq) 5364 { 5365 struct ice_aqc_get_cgu_output_config *cmd; 5366 struct ice_aq_desc desc; 5367 int ret; 5368 5369 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5370 cmd = &desc.params.get_cgu_output_config; 5371 cmd->output_idx = output_idx; 5372 5373 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5374 if (!ret) { 5375 if (flags) 5376 *flags = cmd->flags; 5377 if (src_sel) 5378 *src_sel = cmd->src_sel; 5379 if (freq) 5380 *freq = le32_to_cpu(cmd->freq); 5381 if (src_freq) 5382 *src_freq = le32_to_cpu(cmd->src_freq); 5383 } 5384 5385 return ret; 5386 } 5387 5388 /** 5389 * ice_aq_get_cgu_dpll_status - get dpll status 5390 * @hw: pointer to the HW struct 5391 * @dpll_num: DPLL index 5392 * @ref_state: Reference clock state 5393 * @config: current DPLL config 5394 * @dpll_state: current DPLL state 5395 * @phase_offset: Phase offset in ns 5396 * @eec_mode: EEC_mode 5397 * 5398 * Get CGU DPLL status (0x0C66) 5399 * Return: 0 on success or negative value on failure. 5400 */ 5401 int 5402 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5403 u8 *dpll_state, u8 *config, s64 *phase_offset, 5404 u8 *eec_mode) 5405 { 5406 struct ice_aqc_get_cgu_dpll_status *cmd; 5407 struct ice_aq_desc desc; 5408 int status; 5409 5410 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5411 cmd = &desc.params.get_cgu_dpll_status; 5412 cmd->dpll_num = dpll_num; 5413 5414 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5415 if (!status) { 5416 *ref_state = cmd->ref_state; 5417 *dpll_state = cmd->dpll_state; 5418 *config = cmd->config; 5419 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5420 *phase_offset <<= 32; 5421 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5422 *phase_offset = sign_extend64(*phase_offset, 47); 5423 *eec_mode = cmd->eec_mode; 5424 } 5425 5426 return status; 5427 } 5428 5429 /** 5430 * ice_aq_set_cgu_dpll_config - set dpll config 5431 * @hw: pointer to the HW struct 5432 * @dpll_num: DPLL index 5433 * @ref_state: Reference clock state 5434 * @config: DPLL config 5435 * @eec_mode: EEC mode 5436 * 5437 * Set CGU DPLL config (0x0C67) 5438 * Return: 0 on success or negative value on failure. 5439 */ 5440 int 5441 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5442 u8 config, u8 eec_mode) 5443 { 5444 struct ice_aqc_set_cgu_dpll_config *cmd; 5445 struct ice_aq_desc desc; 5446 5447 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5448 cmd = &desc.params.set_cgu_dpll_config; 5449 cmd->dpll_num = dpll_num; 5450 cmd->ref_state = ref_state; 5451 cmd->config = config; 5452 cmd->eec_mode = eec_mode; 5453 5454 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5455 } 5456 5457 /** 5458 * ice_aq_set_cgu_ref_prio - set input reference priority 5459 * @hw: pointer to the HW struct 5460 * @dpll_num: DPLL index 5461 * @ref_idx: Reference pin index 5462 * @ref_priority: Reference input priority 5463 * 5464 * Set CGU reference priority (0x0C68) 5465 * Return: 0 on success or negative value on failure. 5466 */ 5467 int 5468 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5469 u8 ref_priority) 5470 { 5471 struct ice_aqc_set_cgu_ref_prio *cmd; 5472 struct ice_aq_desc desc; 5473 5474 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5475 cmd = &desc.params.set_cgu_ref_prio; 5476 cmd->dpll_num = dpll_num; 5477 cmd->ref_idx = ref_idx; 5478 cmd->ref_priority = ref_priority; 5479 5480 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5481 } 5482 5483 /** 5484 * ice_aq_get_cgu_ref_prio - get input reference priority 5485 * @hw: pointer to the HW struct 5486 * @dpll_num: DPLL index 5487 * @ref_idx: Reference pin index 5488 * @ref_prio: Reference input priority 5489 * 5490 * Get CGU reference priority (0x0C69) 5491 * Return: 0 on success or negative value on failure. 5492 */ 5493 int 5494 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5495 u8 *ref_prio) 5496 { 5497 struct ice_aqc_get_cgu_ref_prio *cmd; 5498 struct ice_aq_desc desc; 5499 int status; 5500 5501 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5502 cmd = &desc.params.get_cgu_ref_prio; 5503 cmd->dpll_num = dpll_num; 5504 cmd->ref_idx = ref_idx; 5505 5506 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5507 if (!status) 5508 *ref_prio = cmd->ref_priority; 5509 5510 return status; 5511 } 5512 5513 /** 5514 * ice_aq_get_cgu_info - get cgu info 5515 * @hw: pointer to the HW struct 5516 * @cgu_id: CGU ID 5517 * @cgu_cfg_ver: CGU config version 5518 * @cgu_fw_ver: CGU firmware version 5519 * 5520 * Get CGU info (0x0C6A) 5521 * Return: 0 on success or negative value on failure. 5522 */ 5523 int 5524 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5525 u32 *cgu_fw_ver) 5526 { 5527 struct ice_aqc_get_cgu_info *cmd; 5528 struct ice_aq_desc desc; 5529 int status; 5530 5531 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5532 cmd = &desc.params.get_cgu_info; 5533 5534 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5535 if (!status) { 5536 *cgu_id = le32_to_cpu(cmd->cgu_id); 5537 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5538 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5539 } 5540 5541 return status; 5542 } 5543 5544 /** 5545 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5546 * @hw: pointer to the HW struct 5547 * @phy_output: PHY reference clock output pin 5548 * @enable: GPIO state to be applied 5549 * @freq: PHY output frequency 5550 * 5551 * Set phy recovered clock as reference (0x0630) 5552 * Return: 0 on success or negative value on failure. 5553 */ 5554 int 5555 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5556 u32 *freq) 5557 { 5558 struct ice_aqc_set_phy_rec_clk_out *cmd; 5559 struct ice_aq_desc desc; 5560 int status; 5561 5562 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5563 cmd = &desc.params.set_phy_rec_clk_out; 5564 cmd->phy_output = phy_output; 5565 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5566 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5567 cmd->freq = cpu_to_le32(*freq); 5568 5569 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5570 if (!status) 5571 *freq = le32_to_cpu(cmd->freq); 5572 5573 return status; 5574 } 5575 5576 /** 5577 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5578 * @hw: pointer to the HW struct 5579 * @phy_output: PHY reference clock output pin 5580 * @port_num: Port number 5581 * @flags: PHY flags 5582 * @node_handle: PHY output frequency 5583 * 5584 * Get PHY recovered clock output info (0x0631) 5585 * Return: 0 on success or negative value on failure. 5586 */ 5587 int 5588 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5589 u8 *flags, u16 *node_handle) 5590 { 5591 struct ice_aqc_get_phy_rec_clk_out *cmd; 5592 struct ice_aq_desc desc; 5593 int status; 5594 5595 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5596 cmd = &desc.params.get_phy_rec_clk_out; 5597 cmd->phy_output = *phy_output; 5598 5599 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5600 if (!status) { 5601 *phy_output = cmd->phy_output; 5602 if (port_num) 5603 *port_num = cmd->port_num; 5604 if (flags) 5605 *flags = cmd->flags; 5606 if (node_handle) 5607 *node_handle = le16_to_cpu(cmd->node_handle); 5608 } 5609 5610 return status; 5611 } 5612 5613 /** 5614 * ice_aq_get_sensor_reading 5615 * @hw: pointer to the HW struct 5616 * @data: pointer to data to be read from the sensor 5617 * 5618 * Get sensor reading (0x0632) 5619 */ 5620 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5621 struct ice_aqc_get_sensor_reading_resp *data) 5622 { 5623 struct ice_aqc_get_sensor_reading *cmd; 5624 struct ice_aq_desc desc; 5625 int status; 5626 5627 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5628 cmd = &desc.params.get_sensor_reading; 5629 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5630 #define ICE_INTERNAL_TEMP_SENSOR 0 5631 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5632 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5633 5634 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5635 if (!status) 5636 memcpy(data, &desc.params.get_sensor_reading_resp, 5637 sizeof(*data)); 5638 5639 return status; 5640 } 5641 5642 /** 5643 * ice_replay_pre_init - replay pre initialization 5644 * @hw: pointer to the HW struct 5645 * 5646 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5647 */ 5648 static int ice_replay_pre_init(struct ice_hw *hw) 5649 { 5650 struct ice_switch_info *sw = hw->switch_info; 5651 u8 i; 5652 5653 /* Delete old entries from replay filter list head if there is any */ 5654 ice_rm_all_sw_replay_rule_info(hw); 5655 /* In start of replay, move entries into replay_rules list, it 5656 * will allow adding rules entries back to filt_rules list, 5657 * which is operational list. 5658 */ 5659 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5660 list_replace_init(&sw->recp_list[i].filt_rules, 5661 &sw->recp_list[i].filt_replay_rules); 5662 ice_sched_replay_agg_vsi_preinit(hw); 5663 5664 return 0; 5665 } 5666 5667 /** 5668 * ice_replay_vsi - replay VSI configuration 5669 * @hw: pointer to the HW struct 5670 * @vsi_handle: driver VSI handle 5671 * 5672 * Restore all VSI configuration after reset. It is required to call this 5673 * function with main VSI first. 5674 */ 5675 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5676 { 5677 int status; 5678 5679 if (!ice_is_vsi_valid(hw, vsi_handle)) 5680 return -EINVAL; 5681 5682 /* Replay pre-initialization if there is any */ 5683 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5684 status = ice_replay_pre_init(hw); 5685 if (status) 5686 return status; 5687 } 5688 /* Replay per VSI all RSS configurations */ 5689 status = ice_replay_rss_cfg(hw, vsi_handle); 5690 if (status) 5691 return status; 5692 /* Replay per VSI all filters */ 5693 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5694 if (!status) 5695 status = ice_replay_vsi_agg(hw, vsi_handle); 5696 return status; 5697 } 5698 5699 /** 5700 * ice_replay_post - post replay configuration cleanup 5701 * @hw: pointer to the HW struct 5702 * 5703 * Post replay cleanup. 5704 */ 5705 void ice_replay_post(struct ice_hw *hw) 5706 { 5707 /* Delete old entries from replay filter list head */ 5708 ice_rm_all_sw_replay_rule_info(hw); 5709 ice_sched_replay_agg(hw); 5710 } 5711 5712 /** 5713 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5714 * @hw: ptr to the hardware info 5715 * @reg: offset of 64 bit HW register to read from 5716 * @prev_stat_loaded: bool to specify if previous stats are loaded 5717 * @prev_stat: ptr to previous loaded stat value 5718 * @cur_stat: ptr to current stat value 5719 */ 5720 void 5721 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5722 u64 *prev_stat, u64 *cur_stat) 5723 { 5724 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5725 5726 /* device stats are not reset at PFR, they likely will not be zeroed 5727 * when the driver starts. Thus, save the value from the first read 5728 * without adding to the statistic value so that we report stats which 5729 * count up from zero. 5730 */ 5731 if (!prev_stat_loaded) { 5732 *prev_stat = new_data; 5733 return; 5734 } 5735 5736 /* Calculate the difference between the new and old values, and then 5737 * add it to the software stat value. 5738 */ 5739 if (new_data >= *prev_stat) 5740 *cur_stat += new_data - *prev_stat; 5741 else 5742 /* to manage the potential roll-over */ 5743 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5744 5745 /* Update the previously stored value to prepare for next read */ 5746 *prev_stat = new_data; 5747 } 5748 5749 /** 5750 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5751 * @hw: ptr to the hardware info 5752 * @reg: offset of HW register to read from 5753 * @prev_stat_loaded: bool to specify if previous stats are loaded 5754 * @prev_stat: ptr to previous loaded stat value 5755 * @cur_stat: ptr to current stat value 5756 */ 5757 void 5758 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5759 u64 *prev_stat, u64 *cur_stat) 5760 { 5761 u32 new_data; 5762 5763 new_data = rd32(hw, reg); 5764 5765 /* device stats are not reset at PFR, they likely will not be zeroed 5766 * when the driver starts. Thus, save the value from the first read 5767 * without adding to the statistic value so that we report stats which 5768 * count up from zero. 5769 */ 5770 if (!prev_stat_loaded) { 5771 *prev_stat = new_data; 5772 return; 5773 } 5774 5775 /* Calculate the difference between the new and old values, and then 5776 * add it to the software stat value. 5777 */ 5778 if (new_data >= *prev_stat) 5779 *cur_stat += new_data - *prev_stat; 5780 else 5781 /* to manage the potential roll-over */ 5782 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5783 5784 /* Update the previously stored value to prepare for next read */ 5785 *prev_stat = new_data; 5786 } 5787 5788 /** 5789 * ice_sched_query_elem - query element information from HW 5790 * @hw: pointer to the HW struct 5791 * @node_teid: node TEID to be queried 5792 * @buf: buffer to element information 5793 * 5794 * This function queries HW element information 5795 */ 5796 int 5797 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5798 struct ice_aqc_txsched_elem_data *buf) 5799 { 5800 u16 buf_size, num_elem_ret = 0; 5801 int status; 5802 5803 buf_size = sizeof(*buf); 5804 memset(buf, 0, buf_size); 5805 buf->node_teid = cpu_to_le32(node_teid); 5806 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5807 NULL); 5808 if (status || num_elem_ret != 1) 5809 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5810 return status; 5811 } 5812 5813 /** 5814 * ice_aq_read_i2c 5815 * @hw: pointer to the hw struct 5816 * @topo_addr: topology address for a device to communicate with 5817 * @bus_addr: 7-bit I2C bus address 5818 * @addr: I2C memory address (I2C offset) with up to 16 bits 5819 * @params: I2C parameters: bit [7] - Repeated start, 5820 * bits [6:5] data offset size, 5821 * bit [4] - I2C address type, 5822 * bits [3:0] - data size to read (0-16 bytes) 5823 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5824 * @cd: pointer to command details structure or NULL 5825 * 5826 * Read I2C (0x06E2) 5827 */ 5828 int 5829 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5830 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5831 struct ice_sq_cd *cd) 5832 { 5833 struct ice_aq_desc desc = { 0 }; 5834 struct ice_aqc_i2c *cmd; 5835 u8 data_size; 5836 int status; 5837 5838 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5839 cmd = &desc.params.read_write_i2c; 5840 5841 if (!data) 5842 return -EINVAL; 5843 5844 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5845 5846 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5847 cmd->topo_addr = topo_addr; 5848 cmd->i2c_params = params; 5849 cmd->i2c_addr = addr; 5850 5851 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5852 if (!status) { 5853 struct ice_aqc_read_i2c_resp *resp; 5854 u8 i; 5855 5856 resp = &desc.params.read_i2c_resp; 5857 for (i = 0; i < data_size; i++) { 5858 *data = resp->i2c_data[i]; 5859 data++; 5860 } 5861 } 5862 5863 return status; 5864 } 5865 5866 /** 5867 * ice_aq_write_i2c 5868 * @hw: pointer to the hw struct 5869 * @topo_addr: topology address for a device to communicate with 5870 * @bus_addr: 7-bit I2C bus address 5871 * @addr: I2C memory address (I2C offset) with up to 16 bits 5872 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5873 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5874 * @cd: pointer to command details structure or NULL 5875 * 5876 * Write I2C (0x06E3) 5877 * 5878 * * Return: 5879 * * 0 - Successful write to the i2c device 5880 * * -EINVAL - Data size greater than 4 bytes 5881 * * -EIO - FW error 5882 */ 5883 int 5884 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5885 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5886 struct ice_sq_cd *cd) 5887 { 5888 struct ice_aq_desc desc = { 0 }; 5889 struct ice_aqc_i2c *cmd; 5890 u8 data_size; 5891 5892 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5893 cmd = &desc.params.read_write_i2c; 5894 5895 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5896 5897 /* data_size limited to 4 */ 5898 if (data_size > 4) 5899 return -EINVAL; 5900 5901 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5902 cmd->topo_addr = topo_addr; 5903 cmd->i2c_params = params; 5904 cmd->i2c_addr = addr; 5905 5906 memcpy(cmd->i2c_data, data, data_size); 5907 5908 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5909 } 5910 5911 /** 5912 * ice_get_pca9575_handle - find and return the PCA9575 controller 5913 * @hw: pointer to the hw struct 5914 * @pca9575_handle: GPIO controller's handle 5915 * 5916 * Find and return the GPIO controller's handle in the netlist. 5917 * When found - the value will be cached in the hw structure and following calls 5918 * will return cached value. 5919 * 5920 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5921 */ 5922 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5923 { 5924 struct ice_aqc_get_link_topo *cmd; 5925 struct ice_aq_desc desc; 5926 int err; 5927 u8 idx; 5928 5929 /* If handle was read previously return cached value */ 5930 if (hw->io_expander_handle) { 5931 *pca9575_handle = hw->io_expander_handle; 5932 return 0; 5933 } 5934 5935 #define SW_PCA9575_SFP_TOPO_IDX 2 5936 #define SW_PCA9575_QSFP_TOPO_IDX 1 5937 5938 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5939 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5940 idx = SW_PCA9575_SFP_TOPO_IDX; 5941 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5942 idx = SW_PCA9575_QSFP_TOPO_IDX; 5943 else 5944 return -ENXIO; 5945 5946 /* If handle was not detected read it from the netlist */ 5947 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5948 cmd = &desc.params.get_link_topo; 5949 cmd->addr.topo_params.node_type_ctx = 5950 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5951 cmd->addr.topo_params.index = idx; 5952 5953 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5954 if (err) 5955 return -ENXIO; 5956 5957 /* Verify if we found the right IO expander type */ 5958 if (desc.params.get_link_topo.node_part_num != 5959 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5960 return -ENXIO; 5961 5962 /* If present save the handle and return it */ 5963 hw->io_expander_handle = 5964 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5965 *pca9575_handle = hw->io_expander_handle; 5966 5967 return 0; 5968 } 5969 5970 /** 5971 * ice_read_pca9575_reg - read the register from the PCA9575 controller 5972 * @hw: pointer to the hw struct 5973 * @offset: GPIO controller register offset 5974 * @data: pointer to data to be read from the GPIO controller 5975 * 5976 * Return: 0 on success, negative error code otherwise. 5977 */ 5978 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5979 { 5980 struct ice_aqc_link_topo_addr link_topo; 5981 __le16 addr; 5982 u16 handle; 5983 int err; 5984 5985 memset(&link_topo, 0, sizeof(link_topo)); 5986 5987 err = ice_get_pca9575_handle(hw, &handle); 5988 if (err) 5989 return err; 5990 5991 link_topo.handle = cpu_to_le16(handle); 5992 link_topo.topo_params.node_type_ctx = 5993 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 5994 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 5995 5996 addr = cpu_to_le16((u16)offset); 5997 5998 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 5999 } 6000 6001 /** 6002 * ice_aq_set_gpio 6003 * @hw: pointer to the hw struct 6004 * @gpio_ctrl_handle: GPIO controller node handle 6005 * @pin_idx: IO Number of the GPIO that needs to be set 6006 * @value: SW provide IO value to set in the LSB 6007 * @cd: pointer to command details structure or NULL 6008 * 6009 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6010 */ 6011 int 6012 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6013 struct ice_sq_cd *cd) 6014 { 6015 struct ice_aqc_gpio *cmd; 6016 struct ice_aq_desc desc; 6017 6018 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6019 cmd = &desc.params.read_write_gpio; 6020 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6021 cmd->gpio_num = pin_idx; 6022 cmd->gpio_val = value ? 1 : 0; 6023 6024 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6025 } 6026 6027 /** 6028 * ice_aq_get_gpio 6029 * @hw: pointer to the hw struct 6030 * @gpio_ctrl_handle: GPIO controller node handle 6031 * @pin_idx: IO Number of the GPIO that needs to be set 6032 * @value: IO value read 6033 * @cd: pointer to command details structure or NULL 6034 * 6035 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6036 * the topology 6037 */ 6038 int 6039 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6040 bool *value, struct ice_sq_cd *cd) 6041 { 6042 struct ice_aqc_gpio *cmd; 6043 struct ice_aq_desc desc; 6044 int status; 6045 6046 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6047 cmd = &desc.params.read_write_gpio; 6048 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6049 cmd->gpio_num = pin_idx; 6050 6051 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6052 if (status) 6053 return status; 6054 6055 *value = !!cmd->gpio_val; 6056 return 0; 6057 } 6058 6059 /** 6060 * ice_is_fw_api_min_ver 6061 * @hw: pointer to the hardware structure 6062 * @maj: major version 6063 * @min: minor version 6064 * @patch: patch version 6065 * 6066 * Checks if the firmware API is minimum version 6067 */ 6068 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6069 { 6070 if (hw->api_maj_ver == maj) { 6071 if (hw->api_min_ver > min) 6072 return true; 6073 if (hw->api_min_ver == min && hw->api_patch >= patch) 6074 return true; 6075 } else if (hw->api_maj_ver > maj) { 6076 return true; 6077 } 6078 6079 return false; 6080 } 6081 6082 /** 6083 * ice_fw_supports_link_override 6084 * @hw: pointer to the hardware structure 6085 * 6086 * Checks if the firmware supports link override 6087 */ 6088 bool ice_fw_supports_link_override(struct ice_hw *hw) 6089 { 6090 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6091 ICE_FW_API_LINK_OVERRIDE_MIN, 6092 ICE_FW_API_LINK_OVERRIDE_PATCH); 6093 } 6094 6095 /** 6096 * ice_get_link_default_override 6097 * @ldo: pointer to the link default override struct 6098 * @pi: pointer to the port info struct 6099 * 6100 * Gets the link default override for a port 6101 */ 6102 int 6103 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6104 struct ice_port_info *pi) 6105 { 6106 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6107 struct ice_hw *hw = pi->hw; 6108 int status; 6109 6110 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6111 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6112 if (status) { 6113 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6114 return status; 6115 } 6116 6117 /* Each port has its own config; calculate for our port */ 6118 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6119 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6120 6121 /* link options first */ 6122 status = ice_read_sr_word(hw, tlv_start, &buf); 6123 if (status) { 6124 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6125 return status; 6126 } 6127 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6128 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6129 ICE_LINK_OVERRIDE_PHY_CFG_S; 6130 6131 /* link PHY config */ 6132 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6133 status = ice_read_sr_word(hw, offset, &buf); 6134 if (status) { 6135 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6136 return status; 6137 } 6138 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6139 6140 /* PHY types low */ 6141 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6142 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6143 status = ice_read_sr_word(hw, (offset + i), &buf); 6144 if (status) { 6145 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6146 return status; 6147 } 6148 /* shift 16 bits at a time to fill 64 bits */ 6149 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6150 } 6151 6152 /* PHY types high */ 6153 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6154 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6155 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6156 status = ice_read_sr_word(hw, (offset + i), &buf); 6157 if (status) { 6158 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6159 return status; 6160 } 6161 /* shift 16 bits at a time to fill 64 bits */ 6162 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6163 } 6164 6165 return status; 6166 } 6167 6168 /** 6169 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6170 * @caps: get PHY capability data 6171 */ 6172 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6173 { 6174 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6175 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6176 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6177 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6178 return true; 6179 6180 return false; 6181 } 6182 6183 /** 6184 * ice_is_fw_health_report_supported - checks if firmware supports health events 6185 * @hw: pointer to the hardware structure 6186 * 6187 * Return: true if firmware supports health status reports, 6188 * false otherwise 6189 */ 6190 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6191 { 6192 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6193 ICE_FW_API_HEALTH_REPORT_MIN, 6194 ICE_FW_API_HEALTH_REPORT_PATCH); 6195 } 6196 6197 /** 6198 * ice_aq_set_health_status_cfg - Configure FW health events 6199 * @hw: pointer to the HW struct 6200 * @event_source: type of diagnostic events to enable 6201 * 6202 * Configure the health status event types that the firmware will send to this 6203 * PF. The supported event types are: PF-specific, all PFs, and global. 6204 * 6205 * Return: 0 on success, negative error code otherwise. 6206 */ 6207 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6208 { 6209 struct ice_aqc_set_health_status_cfg *cmd; 6210 struct ice_aq_desc desc; 6211 6212 cmd = &desc.params.set_health_status_cfg; 6213 6214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6215 6216 cmd->event_source = event_source; 6217 6218 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6219 } 6220 6221 /** 6222 * ice_aq_set_lldp_mib - Set the LLDP MIB 6223 * @hw: pointer to the HW struct 6224 * @mib_type: Local, Remote or both Local and Remote MIBs 6225 * @buf: pointer to the caller-supplied buffer to store the MIB block 6226 * @buf_size: size of the buffer (in bytes) 6227 * @cd: pointer to command details structure or NULL 6228 * 6229 * Set the LLDP MIB. (0x0A08) 6230 */ 6231 int 6232 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6233 struct ice_sq_cd *cd) 6234 { 6235 struct ice_aqc_lldp_set_local_mib *cmd; 6236 struct ice_aq_desc desc; 6237 6238 cmd = &desc.params.lldp_set_mib; 6239 6240 if (buf_size == 0 || !buf) 6241 return -EINVAL; 6242 6243 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6244 6245 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 6246 desc.datalen = cpu_to_le16(buf_size); 6247 6248 cmd->type = mib_type; 6249 cmd->length = cpu_to_le16(buf_size); 6250 6251 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6252 } 6253 6254 /** 6255 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6256 * @hw: pointer to HW struct 6257 */ 6258 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6259 { 6260 if (hw->mac_type != ICE_MAC_E810) 6261 return false; 6262 6263 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6264 ICE_FW_API_LLDP_FLTR_MIN, 6265 ICE_FW_API_LLDP_FLTR_PATCH); 6266 } 6267 6268 /** 6269 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6270 * @hw: pointer to HW struct 6271 * @vsi: VSI to add the filter to 6272 * @add: boolean for if adding or removing a filter 6273 * 6274 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6275 * with this HW or VSI, otherwise an error corresponding to 6276 * the AQ transaction result. 6277 */ 6278 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6279 { 6280 struct ice_aqc_lldp_filter_ctrl *cmd; 6281 struct ice_aq_desc desc; 6282 6283 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6284 return -EOPNOTSUPP; 6285 6286 cmd = &desc.params.lldp_filter_ctrl; 6287 6288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6289 6290 if (add) 6291 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6292 else 6293 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6294 6295 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6296 6297 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6298 } 6299 6300 /** 6301 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6302 * @hw: pointer to HW struct 6303 */ 6304 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6305 { 6306 struct ice_aq_desc desc; 6307 6308 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6309 6310 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6311 } 6312 6313 /** 6314 * ice_fw_supports_report_dflt_cfg 6315 * @hw: pointer to the hardware structure 6316 * 6317 * Checks if the firmware supports report default configuration 6318 */ 6319 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6320 { 6321 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6322 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6323 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6324 } 6325 6326 /* each of the indexes into the following array match the speed of a return 6327 * value from the list of AQ returned speeds like the range: 6328 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6329 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6330 * array. The array is defined as 15 elements long because the link_speed 6331 * returned by the firmware is a 16 bit * value, but is indexed 6332 * by [fls(speed) - 1] 6333 */ 6334 static const u32 ice_aq_to_link_speed[] = { 6335 SPEED_10, /* BIT(0) */ 6336 SPEED_100, 6337 SPEED_1000, 6338 SPEED_2500, 6339 SPEED_5000, 6340 SPEED_10000, 6341 SPEED_20000, 6342 SPEED_25000, 6343 SPEED_40000, 6344 SPEED_50000, 6345 SPEED_100000, /* BIT(10) */ 6346 SPEED_200000, 6347 }; 6348 6349 /** 6350 * ice_get_link_speed - get integer speed from table 6351 * @index: array index from fls(aq speed) - 1 6352 * 6353 * Returns: u32 value containing integer speed 6354 */ 6355 u32 ice_get_link_speed(u16 index) 6356 { 6357 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6358 return 0; 6359 6360 return ice_aq_to_link_speed[index]; 6361 } 6362 6363 /** 6364 * ice_read_cgu_reg - Read a CGU register 6365 * @hw: Pointer to the HW struct 6366 * @addr: Register address to read 6367 * @val: Storage for register value read 6368 * 6369 * Read the contents of a register of the Clock Generation Unit. Only 6370 * applicable to E82X devices. 6371 * 6372 * Return: 0 on success, other error codes when failed to read from CGU. 6373 */ 6374 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6375 { 6376 struct ice_sbq_msg_input cgu_msg = { 6377 .opcode = ice_sbq_msg_rd, 6378 .dest_dev = ice_sbq_dev_cgu, 6379 .msg_addr_low = addr 6380 }; 6381 int err; 6382 6383 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6384 if (err) { 6385 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6386 addr, err); 6387 return err; 6388 } 6389 6390 *val = cgu_msg.data; 6391 6392 return 0; 6393 } 6394 6395 /** 6396 * ice_write_cgu_reg - Write a CGU register 6397 * @hw: Pointer to the HW struct 6398 * @addr: Register address to write 6399 * @val: Value to write into the register 6400 * 6401 * Write the specified value to a register of the Clock Generation Unit. Only 6402 * applicable to E82X devices. 6403 * 6404 * Return: 0 on success, other error codes when failed to write to CGU. 6405 */ 6406 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6407 { 6408 struct ice_sbq_msg_input cgu_msg = { 6409 .opcode = ice_sbq_msg_wr, 6410 .dest_dev = ice_sbq_dev_cgu, 6411 .msg_addr_low = addr, 6412 .data = val 6413 }; 6414 int err; 6415 6416 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6417 if (err) 6418 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6419 addr, err); 6420 6421 return err; 6422 } 6423