1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct ice_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct ice_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = &desc.params.mac_read; 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct ice_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = &desc.params.get_phy; 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct ice_aq_desc desc; 428 429 cmd = &desc.params.get_link_topo; 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aq_desc desc; 458 459 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 460 desc.params.get_link_topo = *cmd; 461 462 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 463 return -EINTR; 464 465 if (node_handle) 466 *node_handle = 467 le16_to_cpu(desc.params.get_link_topo.addr.handle); 468 if (node_part_number) 469 *node_part_number = desc.params.get_link_topo.node_part_num; 470 471 return 0; 472 } 473 474 /** 475 * ice_find_netlist_node 476 * @hw: pointer to the hw struct 477 * @node_type: type of netlist node to look for 478 * @ctx: context of the search 479 * @node_part_number: node part number to look for 480 * @node_handle: output parameter if node found - optional 481 * 482 * Scan the netlist for a node handle of the given node type and part number. 483 * 484 * If node_handle is non-NULL it will be modified on function exit. It is only 485 * valid if the function returns zero, and should be ignored on any non-zero 486 * return value. 487 * 488 * Return: 489 * * 0 if the node is found, 490 * * -ENOENT if no handle was found, 491 * * negative error code on failure to access the AQ. 492 */ 493 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 494 u8 node_part_number, u16 *node_handle) 495 { 496 u8 idx; 497 498 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 499 struct ice_aqc_get_link_topo cmd = {}; 500 u8 rec_node_part_number; 501 int status; 502 503 cmd.addr.topo_params.node_type_ctx = 504 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 506 cmd.addr.topo_params.index = idx; 507 508 status = ice_aq_get_netlist_node(hw, &cmd, 509 &rec_node_part_number, 510 node_handle); 511 if (status) 512 return status; 513 514 if (rec_node_part_number == node_part_number) 515 return 0; 516 } 517 518 return -ENOENT; 519 } 520 521 /** 522 * ice_is_media_cage_present 523 * @pi: port information structure 524 * 525 * Returns true if media cage is present, else false. If no cage, then 526 * media type is backplane or BASE-T. 527 */ 528 static bool ice_is_media_cage_present(struct ice_port_info *pi) 529 { 530 /* Node type cage can be used to determine if cage is present. If AQC 531 * returns error (ENOENT), then no cage present. If no cage present then 532 * connection type is backplane or BASE-T. 533 */ 534 return !ice_aq_get_link_topo_handle(pi, 535 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 536 NULL); 537 } 538 539 /** 540 * ice_get_media_type - Gets media type 541 * @pi: port information structure 542 */ 543 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 544 { 545 struct ice_link_status *hw_link_info; 546 547 if (!pi) 548 return ICE_MEDIA_UNKNOWN; 549 550 hw_link_info = &pi->phy.link_info; 551 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 552 /* If more than one media type is selected, report unknown */ 553 return ICE_MEDIA_UNKNOWN; 554 555 if (hw_link_info->phy_type_low) { 556 /* 1G SGMII is a special case where some DA cable PHYs 557 * may show this as an option when it really shouldn't 558 * be since SGMII is meant to be between a MAC and a PHY 559 * in a backplane. Try to detect this case and handle it 560 */ 561 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 562 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 563 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 564 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 565 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 566 return ICE_MEDIA_DA; 567 568 switch (hw_link_info->phy_type_low) { 569 case ICE_PHY_TYPE_LOW_1000BASE_SX: 570 case ICE_PHY_TYPE_LOW_1000BASE_LX: 571 case ICE_PHY_TYPE_LOW_10GBASE_SR: 572 case ICE_PHY_TYPE_LOW_10GBASE_LR: 573 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 574 case ICE_PHY_TYPE_LOW_25GBASE_SR: 575 case ICE_PHY_TYPE_LOW_25GBASE_LR: 576 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 577 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 578 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 579 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_SR: 581 case ICE_PHY_TYPE_LOW_50GBASE_FR: 582 case ICE_PHY_TYPE_LOW_50GBASE_LR: 583 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 584 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 586 case ICE_PHY_TYPE_LOW_100GBASE_DR: 587 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 588 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 595 return ICE_MEDIA_FIBER; 596 case ICE_PHY_TYPE_LOW_100BASE_TX: 597 case ICE_PHY_TYPE_LOW_1000BASE_T: 598 case ICE_PHY_TYPE_LOW_2500BASE_T: 599 case ICE_PHY_TYPE_LOW_5GBASE_T: 600 case ICE_PHY_TYPE_LOW_10GBASE_T: 601 case ICE_PHY_TYPE_LOW_25GBASE_T: 602 return ICE_MEDIA_BASET; 603 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 604 case ICE_PHY_TYPE_LOW_25GBASE_CR: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 607 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 608 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 609 case ICE_PHY_TYPE_LOW_50GBASE_CP: 610 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 613 return ICE_MEDIA_DA; 614 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 615 case ICE_PHY_TYPE_LOW_40G_XLAUI: 616 case ICE_PHY_TYPE_LOW_50G_LAUI2: 617 case ICE_PHY_TYPE_LOW_50G_AUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI1: 619 case ICE_PHY_TYPE_LOW_100G_AUI4: 620 case ICE_PHY_TYPE_LOW_100G_CAUI4: 621 if (ice_is_media_cage_present(pi)) 622 return ICE_MEDIA_DA; 623 fallthrough; 624 case ICE_PHY_TYPE_LOW_1000BASE_KX: 625 case ICE_PHY_TYPE_LOW_2500BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_X: 627 case ICE_PHY_TYPE_LOW_5GBASE_KR: 628 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 629 case ICE_PHY_TYPE_LOW_25GBASE_KR: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 632 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 633 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 635 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 637 return ICE_MEDIA_BACKPLANE; 638 } 639 } else { 640 switch (hw_link_info->phy_type_high) { 641 case ICE_PHY_TYPE_HIGH_100G_AUI2: 642 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 643 if (ice_is_media_cage_present(pi)) 644 return ICE_MEDIA_DA; 645 fallthrough; 646 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 647 return ICE_MEDIA_BACKPLANE; 648 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 649 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 650 return ICE_MEDIA_FIBER; 651 } 652 } 653 return ICE_MEDIA_UNKNOWN; 654 } 655 656 /** 657 * ice_get_link_status_datalen 658 * @hw: pointer to the HW struct 659 * 660 * Returns datalength for the Get Link Status AQ command, which is bigger for 661 * newer adapter families handled by ice driver. 662 */ 663 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 664 { 665 switch (hw->mac_type) { 666 case ICE_MAC_E830: 667 return ICE_AQC_LS_DATA_SIZE_V2; 668 case ICE_MAC_E810: 669 default: 670 return ICE_AQC_LS_DATA_SIZE_V1; 671 } 672 } 673 674 /** 675 * ice_aq_get_link_info 676 * @pi: port information structure 677 * @ena_lse: enable/disable LinkStatusEvent reporting 678 * @link: pointer to link status structure - optional 679 * @cd: pointer to command details structure or NULL 680 * 681 * Get Link Status (0x607). Returns the link status of the adapter. 682 */ 683 int 684 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 685 struct ice_link_status *link, struct ice_sq_cd *cd) 686 { 687 struct ice_aqc_get_link_status_data link_data = { 0 }; 688 struct ice_aqc_get_link_status *resp; 689 struct ice_link_status *li_old, *li; 690 enum ice_media_type *hw_media_type; 691 struct ice_fc_info *hw_fc_info; 692 bool tx_pause, rx_pause; 693 struct ice_aq_desc desc; 694 struct ice_hw *hw; 695 u16 cmd_flags; 696 int status; 697 698 if (!pi) 699 return -EINVAL; 700 hw = pi->hw; 701 li_old = &pi->phy.link_info_old; 702 hw_media_type = &pi->phy.media_type; 703 li = &pi->phy.link_info; 704 hw_fc_info = &pi->fc; 705 706 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 707 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 708 resp = &desc.params.get_link_status; 709 resp->cmd_flags = cpu_to_le16(cmd_flags); 710 resp->lport_num = pi->lport; 711 712 status = ice_aq_send_cmd(hw, &desc, &link_data, 713 ice_get_link_status_datalen(hw), cd); 714 if (status) 715 return status; 716 717 /* save off old link status information */ 718 *li_old = *li; 719 720 /* update current link status information */ 721 li->link_speed = le16_to_cpu(link_data.link_speed); 722 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 723 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 724 *hw_media_type = ice_get_media_type(pi); 725 li->link_info = link_data.link_info; 726 li->link_cfg_err = link_data.link_cfg_err; 727 li->an_info = link_data.an_info; 728 li->ext_info = link_data.ext_info; 729 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 730 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 731 li->topo_media_conflict = link_data.topo_media_conflict; 732 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 733 ICE_AQ_CFG_PACING_TYPE_M); 734 735 /* update fc info */ 736 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 737 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 738 if (tx_pause && rx_pause) 739 hw_fc_info->current_mode = ICE_FC_FULL; 740 else if (tx_pause) 741 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 742 else if (rx_pause) 743 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 744 else 745 hw_fc_info->current_mode = ICE_FC_NONE; 746 747 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 748 749 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 750 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 751 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 752 (unsigned long long)li->phy_type_low); 753 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 754 (unsigned long long)li->phy_type_high); 755 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 756 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 757 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 758 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 759 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 760 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 761 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 762 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 763 li->max_frame_size); 764 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 765 766 /* save link status information */ 767 if (link) 768 *link = *li; 769 770 /* flag cleared so calling functions don't call AQ again */ 771 pi->phy.get_link_info = false; 772 773 return 0; 774 } 775 776 /** 777 * ice_fill_tx_timer_and_fc_thresh 778 * @hw: pointer to the HW struct 779 * @cmd: pointer to MAC cfg structure 780 * 781 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 782 * descriptor 783 */ 784 static void 785 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 786 struct ice_aqc_set_mac_cfg *cmd) 787 { 788 u32 val, fc_thres_m; 789 790 /* We read back the transmit timer and FC threshold value of 791 * LFC. Thus, we will use index = 792 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 793 * 794 * Also, because we are operating on transmit timer and FC 795 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 796 */ 797 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 798 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 799 800 if (hw->mac_type == ICE_MAC_E830) { 801 /* Retrieve the transmit timer */ 802 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 803 cmd->tx_tmr_value = 804 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 805 806 /* Retrieve the fc threshold */ 807 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 808 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 809 } else { 810 /* Retrieve the transmit timer */ 811 val = rd32(hw, 812 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 813 cmd->tx_tmr_value = 814 le16_encode_bits(val, 815 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 816 817 /* Retrieve the fc threshold */ 818 val = rd32(hw, 819 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 820 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 821 } 822 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 823 } 824 825 /** 826 * ice_aq_set_mac_cfg 827 * @hw: pointer to the HW struct 828 * @max_frame_size: Maximum Frame Size to be supported 829 * @cd: pointer to command details structure or NULL 830 * 831 * Set MAC configuration (0x0603) 832 */ 833 int 834 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 835 { 836 struct ice_aqc_set_mac_cfg *cmd; 837 struct ice_aq_desc desc; 838 839 cmd = &desc.params.set_mac_cfg; 840 841 if (max_frame_size == 0) 842 return -EINVAL; 843 844 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 845 846 cmd->max_frame_size = cpu_to_le16(max_frame_size); 847 848 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 849 850 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 851 } 852 853 /** 854 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 855 * @hw: pointer to the HW struct 856 */ 857 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 858 { 859 struct ice_switch_info *sw; 860 int status; 861 862 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 863 sizeof(*hw->switch_info), GFP_KERNEL); 864 sw = hw->switch_info; 865 866 if (!sw) 867 return -ENOMEM; 868 869 INIT_LIST_HEAD(&sw->vsi_list_map_head); 870 sw->prof_res_bm_init = 0; 871 872 /* Initialize recipe count with default recipes read from NVM */ 873 sw->recp_cnt = ICE_SW_LKUP_LAST; 874 875 status = ice_init_def_sw_recp(hw); 876 if (status) { 877 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 878 return status; 879 } 880 return 0; 881 } 882 883 /** 884 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 885 * @hw: pointer to the HW struct 886 */ 887 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 888 { 889 struct ice_switch_info *sw = hw->switch_info; 890 struct ice_vsi_list_map_info *v_pos_map; 891 struct ice_vsi_list_map_info *v_tmp_map; 892 struct ice_sw_recipe *recps; 893 u8 i; 894 895 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 896 list_entry) { 897 list_del(&v_pos_map->list_entry); 898 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 899 } 900 recps = sw->recp_list; 901 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 902 recps[i].root_rid = i; 903 904 if (recps[i].adv_rule) { 905 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 906 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 907 908 mutex_destroy(&recps[i].filt_rule_lock); 909 list_for_each_entry_safe(lst_itr, tmp_entry, 910 &recps[i].filt_rules, 911 list_entry) { 912 list_del(&lst_itr->list_entry); 913 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr); 915 } 916 } else { 917 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 918 919 mutex_destroy(&recps[i].filt_rule_lock); 920 list_for_each_entry_safe(lst_itr, tmp_entry, 921 &recps[i].filt_rules, 922 list_entry) { 923 list_del(&lst_itr->list_entry); 924 devm_kfree(ice_hw_to_dev(hw), lst_itr); 925 } 926 } 927 } 928 ice_rm_all_sw_replay_rule_info(hw); 929 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 930 devm_kfree(ice_hw_to_dev(hw), sw); 931 } 932 933 /** 934 * ice_get_itr_intrl_gran 935 * @hw: pointer to the HW struct 936 * 937 * Determines the ITR/INTRL granularities based on the maximum aggregate 938 * bandwidth according to the device's configuration during power-on. 939 */ 940 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 941 { 942 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 943 rd32(hw, GL_PWR_MODE_CTL)); 944 945 switch (max_agg_bw) { 946 case ICE_MAX_AGG_BW_200G: 947 case ICE_MAX_AGG_BW_100G: 948 case ICE_MAX_AGG_BW_50G: 949 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 950 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 951 break; 952 case ICE_MAX_AGG_BW_25G: 953 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 954 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 955 break; 956 } 957 } 958 959 /** 960 * ice_wait_for_fw - wait for full FW readiness 961 * @hw: pointer to the hardware structure 962 * @timeout: milliseconds that can elapse before timing out 963 * 964 * Return: 0 on success, -ETIMEDOUT on timeout. 965 */ 966 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 967 { 968 int fw_loading; 969 u32 elapsed = 0; 970 971 while (elapsed <= timeout) { 972 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 973 974 /* firmware was not yet loaded, we have to wait more */ 975 if (fw_loading) { 976 elapsed += 100; 977 msleep(100); 978 continue; 979 } 980 return 0; 981 } 982 983 return -ETIMEDOUT; 984 } 985 986 /** 987 * ice_init_hw - main hardware initialization routine 988 * @hw: pointer to the hardware structure 989 */ 990 int ice_init_hw(struct ice_hw *hw) 991 { 992 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 993 void *mac_buf __free(kfree) = NULL; 994 u16 mac_buf_len; 995 int status; 996 997 /* Set MAC type based on DeviceID */ 998 status = ice_set_mac_type(hw); 999 if (status) 1000 return status; 1001 1002 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1003 1004 status = ice_reset(hw, ICE_RESET_PFR); 1005 if (status) 1006 return status; 1007 1008 ice_get_itr_intrl_gran(hw); 1009 1010 status = ice_create_all_ctrlq(hw); 1011 if (status) 1012 goto err_unroll_cqinit; 1013 1014 status = ice_fwlog_init(hw); 1015 if (status) 1016 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1017 status); 1018 1019 status = ice_clear_pf_cfg(hw); 1020 if (status) 1021 goto err_unroll_cqinit; 1022 1023 /* Set bit to enable Flow Director filters */ 1024 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1025 INIT_LIST_HEAD(&hw->fdir_list_head); 1026 1027 ice_clear_pxe_mode(hw); 1028 1029 status = ice_init_nvm(hw); 1030 if (status) 1031 goto err_unroll_cqinit; 1032 1033 status = ice_get_caps(hw); 1034 if (status) 1035 goto err_unroll_cqinit; 1036 1037 if (!hw->port_info) 1038 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1039 sizeof(*hw->port_info), 1040 GFP_KERNEL); 1041 if (!hw->port_info) { 1042 status = -ENOMEM; 1043 goto err_unroll_cqinit; 1044 } 1045 1046 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1047 /* set the back pointer to HW */ 1048 hw->port_info->hw = hw; 1049 1050 /* Initialize port_info struct with switch configuration data */ 1051 status = ice_get_initial_sw_cfg(hw); 1052 if (status) 1053 goto err_unroll_alloc; 1054 1055 hw->evb_veb = true; 1056 1057 /* init xarray for identifying scheduling nodes uniquely */ 1058 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1059 1060 /* Query the allocated resources for Tx scheduler */ 1061 status = ice_sched_query_res_alloc(hw); 1062 if (status) { 1063 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1064 goto err_unroll_alloc; 1065 } 1066 ice_sched_get_psm_clk_freq(hw); 1067 1068 /* Initialize port_info struct with scheduler data */ 1069 status = ice_sched_init_port(hw->port_info); 1070 if (status) 1071 goto err_unroll_sched; 1072 1073 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1074 if (!pcaps) { 1075 status = -ENOMEM; 1076 goto err_unroll_sched; 1077 } 1078 1079 /* Initialize port_info struct with PHY capabilities */ 1080 status = ice_aq_get_phy_caps(hw->port_info, false, 1081 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1082 NULL); 1083 if (status) 1084 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1085 status); 1086 1087 /* Initialize port_info struct with link information */ 1088 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1089 if (status) 1090 goto err_unroll_sched; 1091 1092 /* need a valid SW entry point to build a Tx tree */ 1093 if (!hw->sw_entry_point_layer) { 1094 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1095 status = -EIO; 1096 goto err_unroll_sched; 1097 } 1098 INIT_LIST_HEAD(&hw->agg_list); 1099 /* Initialize max burst size */ 1100 if (!hw->max_burst_size) 1101 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1102 1103 status = ice_init_fltr_mgmt_struct(hw); 1104 if (status) 1105 goto err_unroll_sched; 1106 1107 /* Get MAC information */ 1108 /* A single port can report up to two (LAN and WoL) addresses */ 1109 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1110 GFP_KERNEL); 1111 if (!mac_buf) { 1112 status = -ENOMEM; 1113 goto err_unroll_fltr_mgmt_struct; 1114 } 1115 1116 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1117 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1118 1119 if (status) 1120 goto err_unroll_fltr_mgmt_struct; 1121 /* enable jumbo frame support at MAC level */ 1122 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1123 if (status) 1124 goto err_unroll_fltr_mgmt_struct; 1125 /* Obtain counter base index which would be used by flow director */ 1126 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1127 if (status) 1128 goto err_unroll_fltr_mgmt_struct; 1129 status = ice_init_hw_tbls(hw); 1130 if (status) 1131 goto err_unroll_fltr_mgmt_struct; 1132 mutex_init(&hw->tnl_lock); 1133 ice_init_chk_recipe_reuse_support(hw); 1134 1135 /* Some cards require longer initialization times 1136 * due to necessity of loading FW from an external source. 1137 * This can take even half a minute. 1138 */ 1139 if (ice_is_pf_c827(hw)) { 1140 status = ice_wait_for_fw(hw, 30000); 1141 if (status) { 1142 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1143 goto err_unroll_fltr_mgmt_struct; 1144 } 1145 } 1146 1147 hw->lane_num = ice_get_phy_lane_number(hw); 1148 1149 return 0; 1150 err_unroll_fltr_mgmt_struct: 1151 ice_cleanup_fltr_mgmt_struct(hw); 1152 err_unroll_sched: 1153 ice_sched_cleanup_all(hw); 1154 err_unroll_alloc: 1155 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1156 err_unroll_cqinit: 1157 ice_destroy_all_ctrlq(hw); 1158 return status; 1159 } 1160 1161 /** 1162 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1163 * @hw: pointer to the hardware structure 1164 * 1165 * This should be called only during nominal operation, not as a result of 1166 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1167 * applicable initializations if it fails for any reason. 1168 */ 1169 void ice_deinit_hw(struct ice_hw *hw) 1170 { 1171 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1172 ice_cleanup_fltr_mgmt_struct(hw); 1173 1174 ice_sched_cleanup_all(hw); 1175 ice_sched_clear_agg(hw); 1176 ice_free_seg(hw); 1177 ice_free_hw_tbls(hw); 1178 mutex_destroy(&hw->tnl_lock); 1179 1180 ice_fwlog_deinit(hw); 1181 ice_destroy_all_ctrlq(hw); 1182 1183 /* Clear VSI contexts if not already cleared */ 1184 ice_clear_all_vsi_ctx(hw); 1185 } 1186 1187 /** 1188 * ice_check_reset - Check to see if a global reset is complete 1189 * @hw: pointer to the hardware structure 1190 */ 1191 int ice_check_reset(struct ice_hw *hw) 1192 { 1193 u32 cnt, reg = 0, grst_timeout, uld_mask; 1194 1195 /* Poll for Device Active state in case a recent CORER, GLOBR, 1196 * or EMPR has occurred. The grst delay value is in 100ms units. 1197 * Add 1sec for outstanding AQ commands that can take a long time. 1198 */ 1199 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1200 rd32(hw, GLGEN_RSTCTL)) + 10; 1201 1202 for (cnt = 0; cnt < grst_timeout; cnt++) { 1203 mdelay(100); 1204 reg = rd32(hw, GLGEN_RSTAT); 1205 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1206 break; 1207 } 1208 1209 if (cnt == grst_timeout) { 1210 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1211 return -EIO; 1212 } 1213 1214 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1215 GLNVM_ULD_PCIER_DONE_1_M |\ 1216 GLNVM_ULD_CORER_DONE_M |\ 1217 GLNVM_ULD_GLOBR_DONE_M |\ 1218 GLNVM_ULD_POR_DONE_M |\ 1219 GLNVM_ULD_POR_DONE_1_M |\ 1220 GLNVM_ULD_PCIER_DONE_2_M) 1221 1222 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1223 GLNVM_ULD_PE_DONE_M : 0); 1224 1225 /* Device is Active; check Global Reset processes are done */ 1226 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1227 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1228 if (reg == uld_mask) { 1229 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1230 break; 1231 } 1232 mdelay(10); 1233 } 1234 1235 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1236 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1237 reg); 1238 return -EIO; 1239 } 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * ice_pf_reset - Reset the PF 1246 * @hw: pointer to the hardware structure 1247 * 1248 * If a global reset has been triggered, this function checks 1249 * for its completion and then issues the PF reset 1250 */ 1251 static int ice_pf_reset(struct ice_hw *hw) 1252 { 1253 u32 cnt, reg; 1254 1255 /* If at function entry a global reset was already in progress, i.e. 1256 * state is not 'device active' or any of the reset done bits are not 1257 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1258 * global reset is done. 1259 */ 1260 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1261 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1262 /* poll on global reset currently in progress until done */ 1263 if (ice_check_reset(hw)) 1264 return -EIO; 1265 1266 return 0; 1267 } 1268 1269 /* Reset the PF */ 1270 reg = rd32(hw, PFGEN_CTRL); 1271 1272 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1273 1274 /* Wait for the PFR to complete. The wait time is the global config lock 1275 * timeout plus the PFR timeout which will account for a possible reset 1276 * that is occurring during a download package operation. 1277 */ 1278 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1279 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1280 reg = rd32(hw, PFGEN_CTRL); 1281 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1282 break; 1283 1284 mdelay(1); 1285 } 1286 1287 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1288 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1289 return -EIO; 1290 } 1291 1292 return 0; 1293 } 1294 1295 /** 1296 * ice_reset - Perform different types of reset 1297 * @hw: pointer to the hardware structure 1298 * @req: reset request 1299 * 1300 * This function triggers a reset as specified by the req parameter. 1301 * 1302 * Note: 1303 * If anything other than a PF reset is triggered, PXE mode is restored. 1304 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1305 * interface has been restored in the rebuild flow. 1306 */ 1307 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1308 { 1309 u32 val = 0; 1310 1311 switch (req) { 1312 case ICE_RESET_PFR: 1313 return ice_pf_reset(hw); 1314 case ICE_RESET_CORER: 1315 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1316 val = GLGEN_RTRIG_CORER_M; 1317 break; 1318 case ICE_RESET_GLOBR: 1319 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1320 val = GLGEN_RTRIG_GLOBR_M; 1321 break; 1322 default: 1323 return -EINVAL; 1324 } 1325 1326 val |= rd32(hw, GLGEN_RTRIG); 1327 wr32(hw, GLGEN_RTRIG, val); 1328 ice_flush(hw); 1329 1330 /* wait for the FW to be ready */ 1331 return ice_check_reset(hw); 1332 } 1333 1334 /** 1335 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1336 * @hw: pointer to the hardware structure 1337 * @rxq_ctx: pointer to the packed Rx queue context 1338 * @rxq_index: the index of the Rx queue 1339 */ 1340 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1341 const ice_rxq_ctx_buf_t *rxq_ctx, 1342 u32 rxq_index) 1343 { 1344 /* Copy each dword separately to HW */ 1345 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1346 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1347 1348 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1349 1350 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1351 } 1352 } 1353 1354 /** 1355 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1356 * @hw: pointer to the hardware structure 1357 * @rxq_ctx: pointer to the packed Rx queue context 1358 * @rxq_index: the index of the Rx queue 1359 */ 1360 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1361 ice_rxq_ctx_buf_t *rxq_ctx, 1362 u32 rxq_index) 1363 { 1364 u32 *ctx = (u32 *)rxq_ctx; 1365 1366 /* Copy each dword separately from HW */ 1367 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1368 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1369 1370 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1371 } 1372 } 1373 1374 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1375 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1376 1377 /* LAN Rx Queue Context */ 1378 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1379 /* Field Width LSB */ 1380 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1381 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1382 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1383 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1384 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1385 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1386 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1387 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1388 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1389 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1390 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1391 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1392 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1393 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1394 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1395 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1396 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1397 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1398 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1399 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1400 }; 1401 1402 /** 1403 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1404 * @ctx: the Rx queue context to pack 1405 * @buf: the HW buffer to pack into 1406 * 1407 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1408 * bit-packed HW layout. 1409 */ 1410 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1411 ice_rxq_ctx_buf_t *buf) 1412 { 1413 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1414 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1415 } 1416 1417 /** 1418 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1419 * @buf: the HW buffer to unpack from 1420 * @ctx: the Rx queue context to unpack 1421 * 1422 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1423 * structure. 1424 */ 1425 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1426 struct ice_rlan_ctx *ctx) 1427 { 1428 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1429 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1430 } 1431 1432 /** 1433 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1434 * @hw: pointer to the hardware structure 1435 * @rlan_ctx: pointer to the unpacked Rx queue context 1436 * @rxq_index: the index of the Rx queue 1437 * 1438 * Pack the sparse Rx Queue context into dense hardware format and write it 1439 * into the HW register space. 1440 * 1441 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1442 */ 1443 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1444 u32 rxq_index) 1445 { 1446 ice_rxq_ctx_buf_t buf = {}; 1447 1448 if (rxq_index > QRX_CTRL_MAX_INDEX) 1449 return -EINVAL; 1450 1451 ice_pack_rxq_ctx(rlan_ctx, &buf); 1452 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * ice_read_rxq_ctx - Read Rx queue context from HW 1459 * @hw: pointer to the hardware structure 1460 * @rlan_ctx: pointer to the Rx queue context 1461 * @rxq_index: the index of the Rx queue 1462 * 1463 * Read the Rx queue context from the hardware registers, and unpack it into 1464 * the sparse Rx queue context structure. 1465 * 1466 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1467 */ 1468 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1469 u32 rxq_index) 1470 { 1471 ice_rxq_ctx_buf_t buf = {}; 1472 1473 if (rxq_index > QRX_CTRL_MAX_INDEX) 1474 return -EINVAL; 1475 1476 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1477 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1478 1479 return 0; 1480 } 1481 1482 /* LAN Tx Queue Context */ 1483 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1484 /* Field Width LSB */ 1485 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1486 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1487 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1488 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1489 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1490 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1491 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1492 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1493 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1494 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1495 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1496 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1497 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1498 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1499 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1500 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1501 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1502 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1503 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1504 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1505 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1506 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1507 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1508 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1509 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1510 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1511 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1512 }; 1513 1514 /** 1515 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1516 * @ctx: the Tx queue context to pack 1517 * @buf: the Admin Queue HW buffer to pack into 1518 * 1519 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1520 * bit-packed Admin Queue layout. 1521 */ 1522 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1523 { 1524 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1525 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1526 } 1527 1528 /** 1529 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1530 * @ctx: the Tx queue context to pack 1531 * @buf: the HW buffer to pack into 1532 * 1533 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1534 * bit-packed HW layout, including the internal data portion. 1535 */ 1536 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1537 ice_txq_ctx_buf_full_t *buf) 1538 { 1539 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1540 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1541 } 1542 1543 /** 1544 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1545 * @buf: the HW buffer to unpack from 1546 * @ctx: the Tx queue context to unpack 1547 * 1548 * Unpack the Tx queue context from the HW buffer (including the full internal 1549 * state) into the CPU-friendly structure. 1550 */ 1551 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1552 struct ice_tlan_ctx *ctx) 1553 { 1554 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1555 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1556 } 1557 1558 /** 1559 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1560 * @hw: pointer to the hardware structure 1561 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1562 * @txq_index: the index of the Tx queue 1563 * 1564 * Copy Tx Queue context from HW register space to dense structure 1565 */ 1566 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1567 ice_txq_ctx_buf_full_t *txq_ctx, 1568 u32 txq_index) 1569 { 1570 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1571 u32 *ctx = (u32 *)txq_ctx; 1572 u32 txq_base, reg; 1573 1574 /* Get Tx queue base within card space */ 1575 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1576 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1577 1578 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1579 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1580 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1581 txq_base + txq_index) | 1582 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1583 1584 /* Prevent other PFs on the same adapter from accessing the Tx queue 1585 * context interface concurrently. 1586 */ 1587 spin_lock(&pf->adapter->txq_ctx_lock); 1588 1589 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1590 ice_flush(hw); 1591 1592 /* Copy each dword separately from HW */ 1593 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1594 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1595 1596 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1597 } 1598 1599 spin_unlock(&pf->adapter->txq_ctx_lock); 1600 } 1601 1602 /** 1603 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1604 * @hw: pointer to the hardware structure 1605 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1606 * @txq_index: the index of the Tx queue 1607 */ 1608 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1609 const ice_txq_ctx_buf_full_t *txq_ctx, 1610 u32 txq_index) 1611 { 1612 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1613 u32 txq_base, reg; 1614 1615 /* Get Tx queue base within card space */ 1616 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1617 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1618 1619 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1620 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1621 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1622 txq_base + txq_index) | 1623 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1624 1625 /* Prevent other PFs on the same adapter from accessing the Tx queue 1626 * context interface concurrently. 1627 */ 1628 spin_lock(&pf->adapter->txq_ctx_lock); 1629 1630 /* Copy each dword separately to HW */ 1631 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1632 u32 ctx = ((const u32 *)txq_ctx)[i]; 1633 1634 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1635 1636 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1637 } 1638 1639 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1640 ice_flush(hw); 1641 1642 spin_unlock(&pf->adapter->txq_ctx_lock); 1643 } 1644 1645 /** 1646 * ice_read_txq_ctx - Read Tx queue context from HW 1647 * @hw: pointer to the hardware structure 1648 * @tlan_ctx: pointer to the Tx queue context 1649 * @txq_index: the index of the Tx queue 1650 * 1651 * Read the Tx queue context from the HW registers, then unpack it into the 1652 * ice_tlan_ctx structure for use. 1653 * 1654 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1655 */ 1656 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1657 u32 txq_index) 1658 { 1659 ice_txq_ctx_buf_full_t buf = {}; 1660 1661 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1662 return -EINVAL; 1663 1664 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1665 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1666 1667 return 0; 1668 } 1669 1670 /** 1671 * ice_write_txq_ctx - Write Tx queue context to HW 1672 * @hw: pointer to the hardware structure 1673 * @tlan_ctx: pointer to the Tx queue context 1674 * @txq_index: the index of the Tx queue 1675 * 1676 * Pack the Tx queue context into the dense HW layout, then write it into the 1677 * HW registers. 1678 * 1679 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1680 */ 1681 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1682 u32 txq_index) 1683 { 1684 ice_txq_ctx_buf_full_t buf = {}; 1685 1686 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1687 return -EINVAL; 1688 1689 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1690 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1691 1692 return 0; 1693 } 1694 1695 /* Sideband Queue command wrappers */ 1696 1697 /** 1698 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1699 * @hw: pointer to the HW struct 1700 * @desc: descriptor describing the command 1701 * @buf: buffer to use for indirect commands (NULL for direct commands) 1702 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1703 * @cd: pointer to command details structure 1704 */ 1705 static int 1706 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1707 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1708 { 1709 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1710 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1711 } 1712 1713 /** 1714 * ice_sbq_rw_reg - Fill Sideband Queue command 1715 * @hw: pointer to the HW struct 1716 * @in: message info to be filled in descriptor 1717 * @flags: control queue descriptor flags 1718 */ 1719 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1720 { 1721 struct ice_sbq_cmd_desc desc = {0}; 1722 struct ice_sbq_msg_req msg = {0}; 1723 u16 msg_len; 1724 int status; 1725 1726 msg_len = sizeof(msg); 1727 1728 msg.dest_dev = in->dest_dev; 1729 msg.opcode = in->opcode; 1730 msg.flags = ICE_SBQ_MSG_FLAGS; 1731 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1732 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1733 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1734 1735 if (in->opcode) 1736 msg.data = cpu_to_le32(in->data); 1737 else 1738 /* data read comes back in completion, so shorten the struct by 1739 * sizeof(msg.data) 1740 */ 1741 msg_len -= sizeof(msg.data); 1742 1743 desc.flags = cpu_to_le16(flags); 1744 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1745 desc.param0.cmd_len = cpu_to_le16(msg_len); 1746 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1747 if (!status && !in->opcode) 1748 in->data = le32_to_cpu 1749 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1750 return status; 1751 } 1752 1753 /* FW Admin Queue command wrappers */ 1754 1755 /* Software lock/mutex that is meant to be held while the Global Config Lock 1756 * in firmware is acquired by the software to prevent most (but not all) types 1757 * of AQ commands from being sent to FW 1758 */ 1759 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1760 1761 /** 1762 * ice_should_retry_sq_send_cmd 1763 * @opcode: AQ opcode 1764 * 1765 * Decide if we should retry the send command routine for the ATQ, depending 1766 * on the opcode. 1767 */ 1768 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1769 { 1770 switch (opcode) { 1771 case ice_aqc_opc_get_link_topo: 1772 case ice_aqc_opc_lldp_stop: 1773 case ice_aqc_opc_lldp_start: 1774 case ice_aqc_opc_lldp_filter_ctrl: 1775 return true; 1776 } 1777 1778 return false; 1779 } 1780 1781 /** 1782 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1783 * @hw: pointer to the HW struct 1784 * @cq: pointer to the specific Control queue 1785 * @desc: prefilled descriptor describing the command 1786 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1787 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1788 * @cd: pointer to command details structure 1789 * 1790 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1791 * Queue if the EBUSY AQ error is returned. 1792 */ 1793 static int 1794 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1795 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1796 struct ice_sq_cd *cd) 1797 { 1798 struct ice_aq_desc desc_cpy; 1799 bool is_cmd_for_retry; 1800 u8 idx = 0; 1801 u16 opcode; 1802 int status; 1803 1804 opcode = le16_to_cpu(desc->opcode); 1805 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1806 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1807 1808 if (is_cmd_for_retry) { 1809 /* All retryable cmds are direct, without buf. */ 1810 WARN_ON(buf); 1811 1812 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1813 } 1814 1815 do { 1816 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1817 1818 if (!is_cmd_for_retry || !status || 1819 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1820 break; 1821 1822 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1823 1824 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1825 1826 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1827 1828 return status; 1829 } 1830 1831 /** 1832 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1833 * @hw: pointer to the HW struct 1834 * @desc: descriptor describing the command 1835 * @buf: buffer to use for indirect commands (NULL for direct commands) 1836 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1837 * @cd: pointer to command details structure 1838 * 1839 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1840 */ 1841 int 1842 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1843 u16 buf_size, struct ice_sq_cd *cd) 1844 { 1845 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1846 bool lock_acquired = false; 1847 int status; 1848 1849 /* When a package download is in process (i.e. when the firmware's 1850 * Global Configuration Lock resource is held), only the Download 1851 * Package, Get Version, Get Package Info List, Upload Section, 1852 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1853 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1854 * Recipes to Profile Association, and Release Resource (with resource 1855 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1856 * must block until the package download completes and the Global Config 1857 * Lock is released. See also ice_acquire_global_cfg_lock(). 1858 */ 1859 switch (le16_to_cpu(desc->opcode)) { 1860 case ice_aqc_opc_download_pkg: 1861 case ice_aqc_opc_get_pkg_info_list: 1862 case ice_aqc_opc_get_ver: 1863 case ice_aqc_opc_upload_section: 1864 case ice_aqc_opc_update_pkg: 1865 case ice_aqc_opc_set_port_params: 1866 case ice_aqc_opc_get_vlan_mode_parameters: 1867 case ice_aqc_opc_set_vlan_mode_parameters: 1868 case ice_aqc_opc_set_tx_topo: 1869 case ice_aqc_opc_get_tx_topo: 1870 case ice_aqc_opc_add_recipe: 1871 case ice_aqc_opc_recipe_to_profile: 1872 case ice_aqc_opc_get_recipe: 1873 case ice_aqc_opc_get_recipe_to_profile: 1874 break; 1875 case ice_aqc_opc_release_res: 1876 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1877 break; 1878 fallthrough; 1879 default: 1880 mutex_lock(&ice_global_cfg_lock_sw); 1881 lock_acquired = true; 1882 break; 1883 } 1884 1885 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1886 if (lock_acquired) 1887 mutex_unlock(&ice_global_cfg_lock_sw); 1888 1889 return status; 1890 } 1891 1892 /** 1893 * ice_aq_get_fw_ver 1894 * @hw: pointer to the HW struct 1895 * @cd: pointer to command details structure or NULL 1896 * 1897 * Get the firmware version (0x0001) from the admin queue commands 1898 */ 1899 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1900 { 1901 struct ice_aqc_get_ver *resp; 1902 struct ice_aq_desc desc; 1903 int status; 1904 1905 resp = &desc.params.get_ver; 1906 1907 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1908 1909 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1910 1911 if (!status) { 1912 hw->fw_branch = resp->fw_branch; 1913 hw->fw_maj_ver = resp->fw_major; 1914 hw->fw_min_ver = resp->fw_minor; 1915 hw->fw_patch = resp->fw_patch; 1916 hw->fw_build = le32_to_cpu(resp->fw_build); 1917 hw->api_branch = resp->api_branch; 1918 hw->api_maj_ver = resp->api_major; 1919 hw->api_min_ver = resp->api_minor; 1920 hw->api_patch = resp->api_patch; 1921 } 1922 1923 return status; 1924 } 1925 1926 /** 1927 * ice_aq_send_driver_ver 1928 * @hw: pointer to the HW struct 1929 * @dv: driver's major, minor version 1930 * @cd: pointer to command details structure or NULL 1931 * 1932 * Send the driver version (0x0002) to the firmware 1933 */ 1934 int 1935 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1936 struct ice_sq_cd *cd) 1937 { 1938 struct ice_aqc_driver_ver *cmd; 1939 struct ice_aq_desc desc; 1940 u16 len; 1941 1942 cmd = &desc.params.driver_ver; 1943 1944 if (!dv) 1945 return -EINVAL; 1946 1947 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1948 1949 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1950 cmd->major_ver = dv->major_ver; 1951 cmd->minor_ver = dv->minor_ver; 1952 cmd->build_ver = dv->build_ver; 1953 cmd->subbuild_ver = dv->subbuild_ver; 1954 1955 len = 0; 1956 while (len < sizeof(dv->driver_string) && 1957 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1958 len++; 1959 1960 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1961 } 1962 1963 /** 1964 * ice_aq_q_shutdown 1965 * @hw: pointer to the HW struct 1966 * @unloading: is the driver unloading itself 1967 * 1968 * Tell the Firmware that we're shutting down the AdminQ and whether 1969 * or not the driver is unloading as well (0x0003). 1970 */ 1971 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1972 { 1973 struct ice_aqc_q_shutdown *cmd; 1974 struct ice_aq_desc desc; 1975 1976 cmd = &desc.params.q_shutdown; 1977 1978 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1979 1980 if (unloading) 1981 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1982 1983 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1984 } 1985 1986 /** 1987 * ice_aq_req_res 1988 * @hw: pointer to the HW struct 1989 * @res: resource ID 1990 * @access: access type 1991 * @sdp_number: resource number 1992 * @timeout: the maximum time in ms that the driver may hold the resource 1993 * @cd: pointer to command details structure or NULL 1994 * 1995 * Requests common resource using the admin queue commands (0x0008). 1996 * When attempting to acquire the Global Config Lock, the driver can 1997 * learn of three states: 1998 * 1) 0 - acquired lock, and can perform download package 1999 * 2) -EIO - did not get lock, driver should fail to load 2000 * 3) -EALREADY - did not get lock, but another driver has 2001 * successfully downloaded the package; the driver does 2002 * not have to download the package and can continue 2003 * loading 2004 * 2005 * Note that if the caller is in an acquire lock, perform action, release lock 2006 * phase of operation, it is possible that the FW may detect a timeout and issue 2007 * a CORER. In this case, the driver will receive a CORER interrupt and will 2008 * have to determine its cause. The calling thread that is handling this flow 2009 * will likely get an error propagated back to it indicating the Download 2010 * Package, Update Package or the Release Resource AQ commands timed out. 2011 */ 2012 static int 2013 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2014 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2015 struct ice_sq_cd *cd) 2016 { 2017 struct ice_aqc_req_res *cmd_resp; 2018 struct ice_aq_desc desc; 2019 int status; 2020 2021 cmd_resp = &desc.params.res_owner; 2022 2023 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2024 2025 cmd_resp->res_id = cpu_to_le16(res); 2026 cmd_resp->access_type = cpu_to_le16(access); 2027 cmd_resp->res_number = cpu_to_le32(sdp_number); 2028 cmd_resp->timeout = cpu_to_le32(*timeout); 2029 *timeout = 0; 2030 2031 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2032 2033 /* The completion specifies the maximum time in ms that the driver 2034 * may hold the resource in the Timeout field. 2035 */ 2036 2037 /* Global config lock response utilizes an additional status field. 2038 * 2039 * If the Global config lock resource is held by some other driver, the 2040 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 2041 * and the timeout field indicates the maximum time the current owner 2042 * of the resource has to free it. 2043 */ 2044 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2045 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 2046 *timeout = le32_to_cpu(cmd_resp->timeout); 2047 return 0; 2048 } else if (le16_to_cpu(cmd_resp->status) == 2049 ICE_AQ_RES_GLBL_IN_PROG) { 2050 *timeout = le32_to_cpu(cmd_resp->timeout); 2051 return -EIO; 2052 } else if (le16_to_cpu(cmd_resp->status) == 2053 ICE_AQ_RES_GLBL_DONE) { 2054 return -EALREADY; 2055 } 2056 2057 /* invalid FW response, force a timeout immediately */ 2058 *timeout = 0; 2059 return -EIO; 2060 } 2061 2062 /* If the resource is held by some other driver, the command completes 2063 * with a busy return value and the timeout field indicates the maximum 2064 * time the current owner of the resource has to free it. 2065 */ 2066 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 2067 *timeout = le32_to_cpu(cmd_resp->timeout); 2068 2069 return status; 2070 } 2071 2072 /** 2073 * ice_aq_release_res 2074 * @hw: pointer to the HW struct 2075 * @res: resource ID 2076 * @sdp_number: resource number 2077 * @cd: pointer to command details structure or NULL 2078 * 2079 * release common resource using the admin queue commands (0x0009) 2080 */ 2081 static int 2082 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2083 struct ice_sq_cd *cd) 2084 { 2085 struct ice_aqc_req_res *cmd; 2086 struct ice_aq_desc desc; 2087 2088 cmd = &desc.params.res_owner; 2089 2090 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2091 2092 cmd->res_id = cpu_to_le16(res); 2093 cmd->res_number = cpu_to_le32(sdp_number); 2094 2095 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2096 } 2097 2098 /** 2099 * ice_acquire_res 2100 * @hw: pointer to the HW structure 2101 * @res: resource ID 2102 * @access: access type (read or write) 2103 * @timeout: timeout in milliseconds 2104 * 2105 * This function will attempt to acquire the ownership of a resource. 2106 */ 2107 int 2108 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2109 enum ice_aq_res_access_type access, u32 timeout) 2110 { 2111 #define ICE_RES_POLLING_DELAY_MS 10 2112 u32 delay = ICE_RES_POLLING_DELAY_MS; 2113 u32 time_left = timeout; 2114 int status; 2115 2116 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2117 2118 /* A return code of -EALREADY means that another driver has 2119 * previously acquired the resource and performed any necessary updates; 2120 * in this case the caller does not obtain the resource and has no 2121 * further work to do. 2122 */ 2123 if (status == -EALREADY) 2124 goto ice_acquire_res_exit; 2125 2126 if (status) 2127 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2128 2129 /* If necessary, poll until the current lock owner timeouts */ 2130 timeout = time_left; 2131 while (status && timeout && time_left) { 2132 mdelay(delay); 2133 timeout = (timeout > delay) ? timeout - delay : 0; 2134 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2135 2136 if (status == -EALREADY) 2137 /* lock free, but no work to do */ 2138 break; 2139 2140 if (!status) 2141 /* lock acquired */ 2142 break; 2143 } 2144 if (status && status != -EALREADY) 2145 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2146 2147 ice_acquire_res_exit: 2148 if (status == -EALREADY) { 2149 if (access == ICE_RES_WRITE) 2150 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2151 else 2152 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2153 } 2154 return status; 2155 } 2156 2157 /** 2158 * ice_release_res 2159 * @hw: pointer to the HW structure 2160 * @res: resource ID 2161 * 2162 * This function will release a resource using the proper Admin Command. 2163 */ 2164 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2165 { 2166 unsigned long timeout; 2167 int status; 2168 2169 /* there are some rare cases when trying to release the resource 2170 * results in an admin queue timeout, so handle them correctly 2171 */ 2172 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2173 do { 2174 status = ice_aq_release_res(hw, res, 0, NULL); 2175 if (status != -EIO) 2176 break; 2177 usleep_range(1000, 2000); 2178 } while (time_before(jiffies, timeout)); 2179 } 2180 2181 /** 2182 * ice_aq_alloc_free_res - command to allocate/free resources 2183 * @hw: pointer to the HW struct 2184 * @buf: Indirect buffer to hold data parameters and response 2185 * @buf_size: size of buffer for indirect commands 2186 * @opc: pass in the command opcode 2187 * 2188 * Helper function to allocate/free resources using the admin queue commands 2189 */ 2190 int ice_aq_alloc_free_res(struct ice_hw *hw, 2191 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2192 enum ice_adminq_opc opc) 2193 { 2194 struct ice_aqc_alloc_free_res_cmd *cmd; 2195 struct ice_aq_desc desc; 2196 2197 cmd = &desc.params.sw_res_ctrl; 2198 2199 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2200 return -EINVAL; 2201 2202 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2203 2204 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2205 2206 cmd->num_entries = cpu_to_le16(1); 2207 2208 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2209 } 2210 2211 /** 2212 * ice_alloc_hw_res - allocate resource 2213 * @hw: pointer to the HW struct 2214 * @type: type of resource 2215 * @num: number of resources to allocate 2216 * @btm: allocate from bottom 2217 * @res: pointer to array that will receive the resources 2218 */ 2219 int 2220 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2221 { 2222 struct ice_aqc_alloc_free_res_elem *buf; 2223 u16 buf_len; 2224 int status; 2225 2226 buf_len = struct_size(buf, elem, num); 2227 buf = kzalloc(buf_len, GFP_KERNEL); 2228 if (!buf) 2229 return -ENOMEM; 2230 2231 /* Prepare buffer to allocate resource. */ 2232 buf->num_elems = cpu_to_le16(num); 2233 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2234 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2235 if (btm) 2236 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2237 2238 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2239 if (status) 2240 goto ice_alloc_res_exit; 2241 2242 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2243 2244 ice_alloc_res_exit: 2245 kfree(buf); 2246 return status; 2247 } 2248 2249 /** 2250 * ice_free_hw_res - free allocated HW resource 2251 * @hw: pointer to the HW struct 2252 * @type: type of resource to free 2253 * @num: number of resources 2254 * @res: pointer to array that contains the resources to free 2255 */ 2256 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2257 { 2258 struct ice_aqc_alloc_free_res_elem *buf; 2259 u16 buf_len; 2260 int status; 2261 2262 buf_len = struct_size(buf, elem, num); 2263 buf = kzalloc(buf_len, GFP_KERNEL); 2264 if (!buf) 2265 return -ENOMEM; 2266 2267 /* Prepare buffer to free resource. */ 2268 buf->num_elems = cpu_to_le16(num); 2269 buf->res_type = cpu_to_le16(type); 2270 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2271 2272 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2273 if (status) 2274 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2275 2276 kfree(buf); 2277 return status; 2278 } 2279 2280 /** 2281 * ice_get_num_per_func - determine number of resources per PF 2282 * @hw: pointer to the HW structure 2283 * @max: value to be evenly split between each PF 2284 * 2285 * Determine the number of valid functions by going through the bitmap returned 2286 * from parsing capabilities and use this to calculate the number of resources 2287 * per PF based on the max value passed in. 2288 */ 2289 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2290 { 2291 u8 funcs; 2292 2293 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2294 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2295 ICE_CAPS_VALID_FUNCS_M); 2296 2297 if (!funcs) 2298 return 0; 2299 2300 return max / funcs; 2301 } 2302 2303 /** 2304 * ice_parse_common_caps - parse common device/function capabilities 2305 * @hw: pointer to the HW struct 2306 * @caps: pointer to common capabilities structure 2307 * @elem: the capability element to parse 2308 * @prefix: message prefix for tracing capabilities 2309 * 2310 * Given a capability element, extract relevant details into the common 2311 * capability structure. 2312 * 2313 * Returns: true if the capability matches one of the common capability ids, 2314 * false otherwise. 2315 */ 2316 static bool 2317 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2318 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2319 { 2320 u32 logical_id = le32_to_cpu(elem->logical_id); 2321 u32 phys_id = le32_to_cpu(elem->phys_id); 2322 u32 number = le32_to_cpu(elem->number); 2323 u16 cap = le16_to_cpu(elem->cap); 2324 bool found = true; 2325 2326 switch (cap) { 2327 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2328 caps->valid_functions = number; 2329 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2330 caps->valid_functions); 2331 break; 2332 case ICE_AQC_CAPS_SRIOV: 2333 caps->sr_iov_1_1 = (number == 1); 2334 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2335 caps->sr_iov_1_1); 2336 break; 2337 case ICE_AQC_CAPS_DCB: 2338 caps->dcb = (number == 1); 2339 caps->active_tc_bitmap = logical_id; 2340 caps->maxtc = phys_id; 2341 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2342 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2343 caps->active_tc_bitmap); 2344 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2345 break; 2346 case ICE_AQC_CAPS_RSS: 2347 caps->rss_table_size = number; 2348 caps->rss_table_entry_width = logical_id; 2349 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2350 caps->rss_table_size); 2351 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2352 caps->rss_table_entry_width); 2353 break; 2354 case ICE_AQC_CAPS_RXQS: 2355 caps->num_rxq = number; 2356 caps->rxq_first_id = phys_id; 2357 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2358 caps->num_rxq); 2359 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2360 caps->rxq_first_id); 2361 break; 2362 case ICE_AQC_CAPS_TXQS: 2363 caps->num_txq = number; 2364 caps->txq_first_id = phys_id; 2365 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2366 caps->num_txq); 2367 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2368 caps->txq_first_id); 2369 break; 2370 case ICE_AQC_CAPS_MSIX: 2371 caps->num_msix_vectors = number; 2372 caps->msix_vector_first_id = phys_id; 2373 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2374 caps->num_msix_vectors); 2375 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2376 caps->msix_vector_first_id); 2377 break; 2378 case ICE_AQC_CAPS_PENDING_NVM_VER: 2379 caps->nvm_update_pending_nvm = true; 2380 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2381 break; 2382 case ICE_AQC_CAPS_PENDING_OROM_VER: 2383 caps->nvm_update_pending_orom = true; 2384 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2385 break; 2386 case ICE_AQC_CAPS_PENDING_NET_VER: 2387 caps->nvm_update_pending_netlist = true; 2388 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2389 break; 2390 case ICE_AQC_CAPS_NVM_MGMT: 2391 caps->nvm_unified_update = 2392 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2393 true : false; 2394 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2395 caps->nvm_unified_update); 2396 break; 2397 case ICE_AQC_CAPS_RDMA: 2398 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2399 caps->rdma = (number == 1); 2400 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2401 break; 2402 case ICE_AQC_CAPS_MAX_MTU: 2403 caps->max_mtu = number; 2404 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2405 prefix, caps->max_mtu); 2406 break; 2407 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2408 caps->pcie_reset_avoidance = (number > 0); 2409 ice_debug(hw, ICE_DBG_INIT, 2410 "%s: pcie_reset_avoidance = %d\n", prefix, 2411 caps->pcie_reset_avoidance); 2412 break; 2413 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2414 caps->reset_restrict_support = (number == 1); 2415 ice_debug(hw, ICE_DBG_INIT, 2416 "%s: reset_restrict_support = %d\n", prefix, 2417 caps->reset_restrict_support); 2418 break; 2419 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2420 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2421 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2422 prefix, caps->roce_lag); 2423 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2424 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2425 prefix, caps->sriov_lag); 2426 break; 2427 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2428 caps->tx_sched_topo_comp_mode_en = (number == 1); 2429 break; 2430 default: 2431 /* Not one of the recognized common capabilities */ 2432 found = false; 2433 } 2434 2435 return found; 2436 } 2437 2438 /** 2439 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2440 * @hw: pointer to the HW structure 2441 * @caps: pointer to capabilities structure to fix 2442 * 2443 * Re-calculate the capabilities that are dependent on the number of physical 2444 * ports; i.e. some features are not supported or function differently on 2445 * devices with more than 4 ports. 2446 */ 2447 static void 2448 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2449 { 2450 /* This assumes device capabilities are always scanned before function 2451 * capabilities during the initialization flow. 2452 */ 2453 if (hw->dev_caps.num_funcs > 4) { 2454 /* Max 4 TCs per port */ 2455 caps->maxtc = 4; 2456 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2457 caps->maxtc); 2458 if (caps->rdma) { 2459 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2460 caps->rdma = 0; 2461 } 2462 2463 /* print message only when processing device capabilities 2464 * during initialization. 2465 */ 2466 if (caps == &hw->dev_caps.common_cap) 2467 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2468 } 2469 } 2470 2471 /** 2472 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2473 * @hw: pointer to the HW struct 2474 * @func_p: pointer to function capabilities structure 2475 * @cap: pointer to the capability element to parse 2476 * 2477 * Extract function capabilities for ICE_AQC_CAPS_VF. 2478 */ 2479 static void 2480 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2481 struct ice_aqc_list_caps_elem *cap) 2482 { 2483 u32 logical_id = le32_to_cpu(cap->logical_id); 2484 u32 number = le32_to_cpu(cap->number); 2485 2486 func_p->num_allocd_vfs = number; 2487 func_p->vf_base_id = logical_id; 2488 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2489 func_p->num_allocd_vfs); 2490 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2491 func_p->vf_base_id); 2492 } 2493 2494 /** 2495 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2496 * @hw: pointer to the HW struct 2497 * @func_p: pointer to function capabilities structure 2498 * @cap: pointer to the capability element to parse 2499 * 2500 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2501 */ 2502 static void 2503 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2504 struct ice_aqc_list_caps_elem *cap) 2505 { 2506 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2507 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2508 le32_to_cpu(cap->number)); 2509 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2510 func_p->guar_num_vsi); 2511 } 2512 2513 /** 2514 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2515 * @hw: pointer to the HW struct 2516 * @func_p: pointer to function capabilities structure 2517 * @cap: pointer to the capability element to parse 2518 * 2519 * Extract function capabilities for ICE_AQC_CAPS_1588. 2520 */ 2521 static void 2522 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2523 struct ice_aqc_list_caps_elem *cap) 2524 { 2525 struct ice_ts_func_info *info = &func_p->ts_func_info; 2526 u32 number = le32_to_cpu(cap->number); 2527 2528 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2529 func_p->common_cap.ieee_1588 = info->ena; 2530 2531 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2532 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2533 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2534 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2535 2536 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2537 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2538 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2539 } else { 2540 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2541 info->clk_src = ICE_CLK_SRC_TIME_REF; 2542 } 2543 2544 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2545 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2546 } else { 2547 /* Unknown clock frequency, so assume a (probably incorrect) 2548 * default to avoid out-of-bounds look ups of frequency 2549 * related information. 2550 */ 2551 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2552 info->clk_freq); 2553 info->time_ref = ICE_TSPLL_FREQ_25_000; 2554 } 2555 2556 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2557 func_p->common_cap.ieee_1588); 2558 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2559 info->src_tmr_owned); 2560 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2561 info->tmr_ena); 2562 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2563 info->tmr_index_owned); 2564 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2565 info->tmr_index_assoc); 2566 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2567 info->clk_freq); 2568 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2569 info->clk_src); 2570 } 2571 2572 /** 2573 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2574 * @hw: pointer to the HW struct 2575 * @func_p: pointer to function capabilities structure 2576 * 2577 * Extract function capabilities for ICE_AQC_CAPS_FD. 2578 */ 2579 static void 2580 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2581 { 2582 u32 reg_val, gsize, bsize; 2583 2584 reg_val = rd32(hw, GLQF_FD_SIZE); 2585 switch (hw->mac_type) { 2586 case ICE_MAC_E830: 2587 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2588 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2589 break; 2590 case ICE_MAC_E810: 2591 default: 2592 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2593 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2594 } 2595 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2596 func_p->fd_fltr_best_effort = bsize; 2597 2598 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2599 func_p->fd_fltr_guar); 2600 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2601 func_p->fd_fltr_best_effort); 2602 } 2603 2604 /** 2605 * ice_parse_func_caps - Parse function capabilities 2606 * @hw: pointer to the HW struct 2607 * @func_p: pointer to function capabilities structure 2608 * @buf: buffer containing the function capability records 2609 * @cap_count: the number of capabilities 2610 * 2611 * Helper function to parse function (0x000A) capabilities list. For 2612 * capabilities shared between device and function, this relies on 2613 * ice_parse_common_caps. 2614 * 2615 * Loop through the list of provided capabilities and extract the relevant 2616 * data into the function capabilities structured. 2617 */ 2618 static void 2619 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2620 void *buf, u32 cap_count) 2621 { 2622 struct ice_aqc_list_caps_elem *cap_resp; 2623 u32 i; 2624 2625 cap_resp = buf; 2626 2627 memset(func_p, 0, sizeof(*func_p)); 2628 2629 for (i = 0; i < cap_count; i++) { 2630 u16 cap = le16_to_cpu(cap_resp[i].cap); 2631 bool found; 2632 2633 found = ice_parse_common_caps(hw, &func_p->common_cap, 2634 &cap_resp[i], "func caps"); 2635 2636 switch (cap) { 2637 case ICE_AQC_CAPS_VF: 2638 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2639 break; 2640 case ICE_AQC_CAPS_VSI: 2641 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2642 break; 2643 case ICE_AQC_CAPS_1588: 2644 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2645 break; 2646 case ICE_AQC_CAPS_FD: 2647 ice_parse_fdir_func_caps(hw, func_p); 2648 break; 2649 default: 2650 /* Don't list common capabilities as unknown */ 2651 if (!found) 2652 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2653 i, cap); 2654 break; 2655 } 2656 } 2657 2658 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2659 } 2660 2661 /** 2662 * ice_func_id_to_logical_id - map from function id to logical pf id 2663 * @active_function_bitmap: active function bitmap 2664 * @pf_id: function number of device 2665 * 2666 * Return: logical PF ID. 2667 */ 2668 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2669 { 2670 u8 logical_id = 0; 2671 u8 i; 2672 2673 for (i = 0; i < pf_id; i++) 2674 if (active_function_bitmap & BIT(i)) 2675 logical_id++; 2676 2677 return logical_id; 2678 } 2679 2680 /** 2681 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2682 * @hw: pointer to the HW struct 2683 * @dev_p: pointer to device capabilities structure 2684 * @cap: capability element to parse 2685 * 2686 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2687 */ 2688 static void 2689 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2690 struct ice_aqc_list_caps_elem *cap) 2691 { 2692 u32 number = le32_to_cpu(cap->number); 2693 2694 dev_p->num_funcs = hweight32(number); 2695 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2696 dev_p->num_funcs); 2697 2698 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2699 } 2700 2701 /** 2702 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2703 * @hw: pointer to the HW struct 2704 * @dev_p: pointer to device capabilities structure 2705 * @cap: capability element to parse 2706 * 2707 * Parse ICE_AQC_CAPS_VF for device capabilities. 2708 */ 2709 static void 2710 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2711 struct ice_aqc_list_caps_elem *cap) 2712 { 2713 u32 number = le32_to_cpu(cap->number); 2714 2715 dev_p->num_vfs_exposed = number; 2716 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2717 dev_p->num_vfs_exposed); 2718 } 2719 2720 /** 2721 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2722 * @hw: pointer to the HW struct 2723 * @dev_p: pointer to device capabilities structure 2724 * @cap: capability element to parse 2725 * 2726 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2727 */ 2728 static void 2729 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2730 struct ice_aqc_list_caps_elem *cap) 2731 { 2732 u32 number = le32_to_cpu(cap->number); 2733 2734 dev_p->num_vsi_allocd_to_host = number; 2735 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2736 dev_p->num_vsi_allocd_to_host); 2737 } 2738 2739 /** 2740 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2741 * @hw: pointer to the HW struct 2742 * @dev_p: pointer to device capabilities structure 2743 * @cap: capability element to parse 2744 * 2745 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2746 */ 2747 static void 2748 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2749 struct ice_aqc_list_caps_elem *cap) 2750 { 2751 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2752 u32 logical_id = le32_to_cpu(cap->logical_id); 2753 u32 phys_id = le32_to_cpu(cap->phys_id); 2754 u32 number = le32_to_cpu(cap->number); 2755 2756 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2757 dev_p->common_cap.ieee_1588 = info->ena; 2758 2759 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2760 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2761 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2762 2763 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2764 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2765 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2766 2767 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2768 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2769 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2770 2771 info->ena_ports = logical_id; 2772 info->tmr_own_map = phys_id; 2773 2774 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2775 dev_p->common_cap.ieee_1588); 2776 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2777 info->tmr0_owner); 2778 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2779 info->tmr0_owned); 2780 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2781 info->tmr0_ena); 2782 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2783 info->tmr1_owner); 2784 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2785 info->tmr1_owned); 2786 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2787 info->tmr1_ena); 2788 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2789 info->ts_ll_read); 2790 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2791 info->ts_ll_int_read); 2792 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2793 info->ll_phy_tmr_update); 2794 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2795 info->ena_ports); 2796 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2797 info->tmr_own_map); 2798 } 2799 2800 /** 2801 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2802 * @hw: pointer to the HW struct 2803 * @dev_p: pointer to device capabilities structure 2804 * @cap: capability element to parse 2805 * 2806 * Parse ICE_AQC_CAPS_FD for device capabilities. 2807 */ 2808 static void 2809 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2810 struct ice_aqc_list_caps_elem *cap) 2811 { 2812 u32 number = le32_to_cpu(cap->number); 2813 2814 dev_p->num_flow_director_fltr = number; 2815 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2816 dev_p->num_flow_director_fltr); 2817 } 2818 2819 /** 2820 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2821 * @hw: pointer to the HW struct 2822 * @dev_p: pointer to device capabilities structure 2823 * @cap: capability element to parse 2824 * 2825 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2826 * enabled sensors. 2827 */ 2828 static void 2829 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2830 struct ice_aqc_list_caps_elem *cap) 2831 { 2832 dev_p->supported_sensors = le32_to_cpu(cap->number); 2833 2834 ice_debug(hw, ICE_DBG_INIT, 2835 "dev caps: supported sensors (bitmap) = 0x%x\n", 2836 dev_p->supported_sensors); 2837 } 2838 2839 /** 2840 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2841 * @hw: pointer to the HW struct 2842 * @dev_p: pointer to device capabilities structure 2843 * @cap: capability element to parse 2844 * 2845 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2846 */ 2847 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2848 struct ice_hw_dev_caps *dev_p, 2849 struct ice_aqc_list_caps_elem *cap) 2850 { 2851 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2852 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2853 2854 dev_info(ice_hw_to_dev(hw), 2855 "PF is configured in %s mode with IP instance ID %d\n", 2856 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2857 "primary" : "secondary", dev_p->nac_topo.id); 2858 2859 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2860 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2861 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2862 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2863 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2864 dev_p->nac_topo.id); 2865 } 2866 2867 /** 2868 * ice_parse_dev_caps - Parse device capabilities 2869 * @hw: pointer to the HW struct 2870 * @dev_p: pointer to device capabilities structure 2871 * @buf: buffer containing the device capability records 2872 * @cap_count: the number of capabilities 2873 * 2874 * Helper device to parse device (0x000B) capabilities list. For 2875 * capabilities shared between device and function, this relies on 2876 * ice_parse_common_caps. 2877 * 2878 * Loop through the list of provided capabilities and extract the relevant 2879 * data into the device capabilities structured. 2880 */ 2881 static void 2882 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2883 void *buf, u32 cap_count) 2884 { 2885 struct ice_aqc_list_caps_elem *cap_resp; 2886 u32 i; 2887 2888 cap_resp = buf; 2889 2890 memset(dev_p, 0, sizeof(*dev_p)); 2891 2892 for (i = 0; i < cap_count; i++) { 2893 u16 cap = le16_to_cpu(cap_resp[i].cap); 2894 bool found; 2895 2896 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2897 &cap_resp[i], "dev caps"); 2898 2899 switch (cap) { 2900 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2901 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2902 break; 2903 case ICE_AQC_CAPS_VF: 2904 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2905 break; 2906 case ICE_AQC_CAPS_VSI: 2907 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2908 break; 2909 case ICE_AQC_CAPS_1588: 2910 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2911 break; 2912 case ICE_AQC_CAPS_FD: 2913 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2914 break; 2915 case ICE_AQC_CAPS_SENSOR_READING: 2916 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2917 break; 2918 case ICE_AQC_CAPS_NAC_TOPOLOGY: 2919 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2920 break; 2921 default: 2922 /* Don't list common capabilities as unknown */ 2923 if (!found) 2924 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2925 i, cap); 2926 break; 2927 } 2928 } 2929 2930 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2931 } 2932 2933 /** 2934 * ice_is_phy_rclk_in_netlist 2935 * @hw: pointer to the hw struct 2936 * 2937 * Check if the PHY Recovered Clock device is present in the netlist 2938 */ 2939 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2940 { 2941 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2942 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2943 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2944 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2945 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2946 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2947 return false; 2948 2949 return true; 2950 } 2951 2952 /** 2953 * ice_is_clock_mux_in_netlist 2954 * @hw: pointer to the hw struct 2955 * 2956 * Check if the Clock Multiplexer device is present in the netlist 2957 */ 2958 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2959 { 2960 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2961 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2962 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2963 NULL)) 2964 return false; 2965 2966 return true; 2967 } 2968 2969 /** 2970 * ice_is_cgu_in_netlist - check for CGU presence 2971 * @hw: pointer to the hw struct 2972 * 2973 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2974 * Save the CGU part number in the hw structure for later use. 2975 * Return: 2976 * * true - cgu is present 2977 * * false - cgu is not present 2978 */ 2979 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2980 { 2981 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2982 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2983 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2984 NULL)) { 2985 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2986 return true; 2987 } else if (!ice_find_netlist_node(hw, 2988 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2989 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2990 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2991 NULL)) { 2992 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2993 return true; 2994 } 2995 2996 return false; 2997 } 2998 2999 /** 3000 * ice_is_gps_in_netlist 3001 * @hw: pointer to the hw struct 3002 * 3003 * Check if the GPS generic device is present in the netlist 3004 */ 3005 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3006 { 3007 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3008 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3009 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3010 return false; 3011 3012 return true; 3013 } 3014 3015 /** 3016 * ice_aq_list_caps - query function/device capabilities 3017 * @hw: pointer to the HW struct 3018 * @buf: a buffer to hold the capabilities 3019 * @buf_size: size of the buffer 3020 * @cap_count: if not NULL, set to the number of capabilities reported 3021 * @opc: capabilities type to discover, device or function 3022 * @cd: pointer to command details structure or NULL 3023 * 3024 * Get the function (0x000A) or device (0x000B) capabilities description from 3025 * firmware and store it in the buffer. 3026 * 3027 * If the cap_count pointer is not NULL, then it is set to the number of 3028 * capabilities firmware will report. Note that if the buffer size is too 3029 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3030 * cap_count will still be updated in this case. It is recommended that the 3031 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3032 * firmware could return) to avoid this. 3033 */ 3034 int 3035 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3036 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3037 { 3038 struct ice_aqc_list_caps *cmd; 3039 struct ice_aq_desc desc; 3040 int status; 3041 3042 cmd = &desc.params.get_cap; 3043 3044 if (opc != ice_aqc_opc_list_func_caps && 3045 opc != ice_aqc_opc_list_dev_caps) 3046 return -EINVAL; 3047 3048 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3049 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3050 3051 if (cap_count) 3052 *cap_count = le32_to_cpu(cmd->count); 3053 3054 return status; 3055 } 3056 3057 /** 3058 * ice_discover_dev_caps - Read and extract device capabilities 3059 * @hw: pointer to the hardware structure 3060 * @dev_caps: pointer to device capabilities structure 3061 * 3062 * Read the device capabilities and extract them into the dev_caps structure 3063 * for later use. 3064 */ 3065 int 3066 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3067 { 3068 u32 cap_count = 0; 3069 void *cbuf; 3070 int status; 3071 3072 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3073 if (!cbuf) 3074 return -ENOMEM; 3075 3076 /* Although the driver doesn't know the number of capabilities the 3077 * device will return, we can simply send a 4KB buffer, the maximum 3078 * possible size that firmware can return. 3079 */ 3080 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3081 3082 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3083 ice_aqc_opc_list_dev_caps, NULL); 3084 if (!status) 3085 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3086 kfree(cbuf); 3087 3088 return status; 3089 } 3090 3091 /** 3092 * ice_discover_func_caps - Read and extract function capabilities 3093 * @hw: pointer to the hardware structure 3094 * @func_caps: pointer to function capabilities structure 3095 * 3096 * Read the function capabilities and extract them into the func_caps structure 3097 * for later use. 3098 */ 3099 static int 3100 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3101 { 3102 u32 cap_count = 0; 3103 void *cbuf; 3104 int status; 3105 3106 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3107 if (!cbuf) 3108 return -ENOMEM; 3109 3110 /* Although the driver doesn't know the number of capabilities the 3111 * device will return, we can simply send a 4KB buffer, the maximum 3112 * possible size that firmware can return. 3113 */ 3114 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3115 3116 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3117 ice_aqc_opc_list_func_caps, NULL); 3118 if (!status) 3119 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3120 kfree(cbuf); 3121 3122 return status; 3123 } 3124 3125 /** 3126 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3127 * @hw: pointer to the hardware structure 3128 */ 3129 void ice_set_safe_mode_caps(struct ice_hw *hw) 3130 { 3131 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3132 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3133 struct ice_hw_common_caps cached_caps; 3134 u32 num_funcs; 3135 3136 /* cache some func_caps values that should be restored after memset */ 3137 cached_caps = func_caps->common_cap; 3138 3139 /* unset func capabilities */ 3140 memset(func_caps, 0, sizeof(*func_caps)); 3141 3142 #define ICE_RESTORE_FUNC_CAP(name) \ 3143 func_caps->common_cap.name = cached_caps.name 3144 3145 /* restore cached values */ 3146 ICE_RESTORE_FUNC_CAP(valid_functions); 3147 ICE_RESTORE_FUNC_CAP(txq_first_id); 3148 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3149 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3150 ICE_RESTORE_FUNC_CAP(max_mtu); 3151 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3152 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3153 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3154 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3155 3156 /* one Tx and one Rx queue in safe mode */ 3157 func_caps->common_cap.num_rxq = 1; 3158 func_caps->common_cap.num_txq = 1; 3159 3160 /* two MSIX vectors, one for traffic and one for misc causes */ 3161 func_caps->common_cap.num_msix_vectors = 2; 3162 func_caps->guar_num_vsi = 1; 3163 3164 /* cache some dev_caps values that should be restored after memset */ 3165 cached_caps = dev_caps->common_cap; 3166 num_funcs = dev_caps->num_funcs; 3167 3168 /* unset dev capabilities */ 3169 memset(dev_caps, 0, sizeof(*dev_caps)); 3170 3171 #define ICE_RESTORE_DEV_CAP(name) \ 3172 dev_caps->common_cap.name = cached_caps.name 3173 3174 /* restore cached values */ 3175 ICE_RESTORE_DEV_CAP(valid_functions); 3176 ICE_RESTORE_DEV_CAP(txq_first_id); 3177 ICE_RESTORE_DEV_CAP(rxq_first_id); 3178 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3179 ICE_RESTORE_DEV_CAP(max_mtu); 3180 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3181 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3182 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3183 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3184 dev_caps->num_funcs = num_funcs; 3185 3186 /* one Tx and one Rx queue per function in safe mode */ 3187 dev_caps->common_cap.num_rxq = num_funcs; 3188 dev_caps->common_cap.num_txq = num_funcs; 3189 3190 /* two MSIX vectors per function */ 3191 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3192 } 3193 3194 /** 3195 * ice_get_caps - get info about the HW 3196 * @hw: pointer to the hardware structure 3197 */ 3198 int ice_get_caps(struct ice_hw *hw) 3199 { 3200 int status; 3201 3202 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3203 if (status) 3204 return status; 3205 3206 return ice_discover_func_caps(hw, &hw->func_caps); 3207 } 3208 3209 /** 3210 * ice_aq_manage_mac_write - manage MAC address write command 3211 * @hw: pointer to the HW struct 3212 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3213 * @flags: flags to control write behavior 3214 * @cd: pointer to command details structure or NULL 3215 * 3216 * This function is used to write MAC address to the NVM (0x0108). 3217 */ 3218 int 3219 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3220 struct ice_sq_cd *cd) 3221 { 3222 struct ice_aqc_manage_mac_write *cmd; 3223 struct ice_aq_desc desc; 3224 3225 cmd = &desc.params.mac_write; 3226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3227 3228 cmd->flags = flags; 3229 ether_addr_copy(cmd->mac_addr, mac_addr); 3230 3231 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3232 } 3233 3234 /** 3235 * ice_aq_clear_pxe_mode 3236 * @hw: pointer to the HW struct 3237 * 3238 * Tell the firmware that the driver is taking over from PXE (0x0110). 3239 */ 3240 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3241 { 3242 struct ice_aq_desc desc; 3243 3244 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3245 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3246 3247 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3248 } 3249 3250 /** 3251 * ice_clear_pxe_mode - clear pxe operations mode 3252 * @hw: pointer to the HW struct 3253 * 3254 * Make sure all PXE mode settings are cleared, including things 3255 * like descriptor fetch/write-back mode. 3256 */ 3257 void ice_clear_pxe_mode(struct ice_hw *hw) 3258 { 3259 if (ice_check_sq_alive(hw, &hw->adminq)) 3260 ice_aq_clear_pxe_mode(hw); 3261 } 3262 3263 /** 3264 * ice_aq_set_port_params - set physical port parameters. 3265 * @pi: pointer to the port info struct 3266 * @double_vlan: if set double VLAN is enabled 3267 * @cd: pointer to command details structure or NULL 3268 * 3269 * Set Physical port parameters (0x0203) 3270 */ 3271 int 3272 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3273 struct ice_sq_cd *cd) 3274 3275 { 3276 struct ice_aqc_set_port_params *cmd; 3277 struct ice_hw *hw = pi->hw; 3278 struct ice_aq_desc desc; 3279 u16 cmd_flags = 0; 3280 3281 cmd = &desc.params.set_port_params; 3282 3283 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3284 if (double_vlan) 3285 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3286 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3287 3288 cmd->local_fwd_mode = pi->local_fwd_mode | 3289 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3290 3291 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3292 } 3293 3294 /** 3295 * ice_is_100m_speed_supported 3296 * @hw: pointer to the HW struct 3297 * 3298 * returns true if 100M speeds are supported by the device, 3299 * false otherwise. 3300 */ 3301 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3302 { 3303 switch (hw->device_id) { 3304 case ICE_DEV_ID_E822C_SGMII: 3305 case ICE_DEV_ID_E822L_SGMII: 3306 case ICE_DEV_ID_E823L_1GBE: 3307 case ICE_DEV_ID_E823C_SGMII: 3308 return true; 3309 default: 3310 return false; 3311 } 3312 } 3313 3314 /** 3315 * ice_get_link_speed_based_on_phy_type - returns link speed 3316 * @phy_type_low: lower part of phy_type 3317 * @phy_type_high: higher part of phy_type 3318 * 3319 * This helper function will convert an entry in PHY type structure 3320 * [phy_type_low, phy_type_high] to its corresponding link speed. 3321 * Note: In the structure of [phy_type_low, phy_type_high], there should 3322 * be one bit set, as this function will convert one PHY type to its 3323 * speed. 3324 * 3325 * Return: 3326 * * PHY speed for recognized PHY type 3327 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3328 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3329 */ 3330 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3331 { 3332 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3333 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3334 3335 switch (phy_type_low) { 3336 case ICE_PHY_TYPE_LOW_100BASE_TX: 3337 case ICE_PHY_TYPE_LOW_100M_SGMII: 3338 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3339 break; 3340 case ICE_PHY_TYPE_LOW_1000BASE_T: 3341 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3342 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3343 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3344 case ICE_PHY_TYPE_LOW_1G_SGMII: 3345 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3346 break; 3347 case ICE_PHY_TYPE_LOW_2500BASE_T: 3348 case ICE_PHY_TYPE_LOW_2500BASE_X: 3349 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3350 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3351 break; 3352 case ICE_PHY_TYPE_LOW_5GBASE_T: 3353 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3354 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3355 break; 3356 case ICE_PHY_TYPE_LOW_10GBASE_T: 3357 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3358 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3359 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3360 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3361 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3362 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3363 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3364 break; 3365 case ICE_PHY_TYPE_LOW_25GBASE_T: 3366 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3367 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3368 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3369 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3370 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3371 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3372 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3373 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3374 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3375 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3376 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3377 break; 3378 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3379 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3380 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3381 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3382 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3383 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3384 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3385 break; 3386 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3387 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3388 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3389 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3390 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3391 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3392 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3393 case ICE_PHY_TYPE_LOW_50G_AUI2: 3394 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3395 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3396 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3397 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3398 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3399 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3400 case ICE_PHY_TYPE_LOW_50G_AUI1: 3401 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3402 break; 3403 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3404 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3405 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3406 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3407 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3408 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3409 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3410 case ICE_PHY_TYPE_LOW_100G_AUI4: 3411 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3412 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3413 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3414 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3415 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3416 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3417 break; 3418 default: 3419 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3420 break; 3421 } 3422 3423 switch (phy_type_high) { 3424 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3425 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3426 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3427 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3428 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3429 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3430 break; 3431 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3432 case ICE_PHY_TYPE_HIGH_200G_SR4: 3433 case ICE_PHY_TYPE_HIGH_200G_FR4: 3434 case ICE_PHY_TYPE_HIGH_200G_LR4: 3435 case ICE_PHY_TYPE_HIGH_200G_DR4: 3436 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3437 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3438 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3439 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3440 break; 3441 default: 3442 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3443 break; 3444 } 3445 3446 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3447 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3448 return ICE_AQ_LINK_SPEED_UNKNOWN; 3449 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3450 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3451 return ICE_AQ_LINK_SPEED_UNKNOWN; 3452 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3453 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3454 return speed_phy_type_low; 3455 else 3456 return speed_phy_type_high; 3457 } 3458 3459 /** 3460 * ice_update_phy_type 3461 * @phy_type_low: pointer to the lower part of phy_type 3462 * @phy_type_high: pointer to the higher part of phy_type 3463 * @link_speeds_bitmap: targeted link speeds bitmap 3464 * 3465 * Note: For the link_speeds_bitmap structure, you can check it at 3466 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3467 * link_speeds_bitmap include multiple speeds. 3468 * 3469 * Each entry in this [phy_type_low, phy_type_high] structure will 3470 * present a certain link speed. This helper function will turn on bits 3471 * in [phy_type_low, phy_type_high] structure based on the value of 3472 * link_speeds_bitmap input parameter. 3473 */ 3474 void 3475 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3476 u16 link_speeds_bitmap) 3477 { 3478 u64 pt_high; 3479 u64 pt_low; 3480 int index; 3481 u16 speed; 3482 3483 /* We first check with low part of phy_type */ 3484 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3485 pt_low = BIT_ULL(index); 3486 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3487 3488 if (link_speeds_bitmap & speed) 3489 *phy_type_low |= BIT_ULL(index); 3490 } 3491 3492 /* We then check with high part of phy_type */ 3493 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3494 pt_high = BIT_ULL(index); 3495 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3496 3497 if (link_speeds_bitmap & speed) 3498 *phy_type_high |= BIT_ULL(index); 3499 } 3500 } 3501 3502 /** 3503 * ice_aq_set_phy_cfg 3504 * @hw: pointer to the HW struct 3505 * @pi: port info structure of the interested logical port 3506 * @cfg: structure with PHY configuration data to be set 3507 * @cd: pointer to command details structure or NULL 3508 * 3509 * Set the various PHY configuration parameters supported on the Port. 3510 * One or more of the Set PHY config parameters may be ignored in an MFP 3511 * mode as the PF may not have the privilege to set some of the PHY Config 3512 * parameters. This status will be indicated by the command response (0x0601). 3513 */ 3514 int 3515 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3516 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3517 { 3518 struct ice_aq_desc desc; 3519 int status; 3520 3521 if (!cfg) 3522 return -EINVAL; 3523 3524 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3525 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3526 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3527 cfg->caps); 3528 3529 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3530 } 3531 3532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3533 desc.params.set_phy.lport_num = pi->lport; 3534 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3535 3536 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3537 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3538 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3539 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3540 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3541 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3542 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3543 cfg->low_power_ctrl_an); 3544 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3545 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3546 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3547 cfg->link_fec_opt); 3548 3549 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3550 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3551 status = 0; 3552 3553 if (!status) 3554 pi->phy.curr_user_phy_cfg = *cfg; 3555 3556 return status; 3557 } 3558 3559 /** 3560 * ice_update_link_info - update status of the HW network link 3561 * @pi: port info structure of the interested logical port 3562 */ 3563 int ice_update_link_info(struct ice_port_info *pi) 3564 { 3565 struct ice_link_status *li; 3566 int status; 3567 3568 if (!pi) 3569 return -EINVAL; 3570 3571 li = &pi->phy.link_info; 3572 3573 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3574 if (status) 3575 return status; 3576 3577 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3578 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3579 3580 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3581 if (!pcaps) 3582 return -ENOMEM; 3583 3584 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3585 pcaps, NULL); 3586 } 3587 3588 return status; 3589 } 3590 3591 /** 3592 * ice_aq_get_phy_equalization - function to read serdes equaliser 3593 * value from firmware using admin queue command. 3594 * @hw: pointer to the HW struct 3595 * @data_in: represents the serdes equalization parameter requested 3596 * @op_code: represents the serdes number and flag to represent tx or rx 3597 * @serdes_num: represents the serdes number 3598 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3599 * 3600 * Return: non-zero status on error and 0 on success. 3601 */ 3602 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3603 u8 serdes_num, int *output) 3604 { 3605 struct ice_aqc_dnl_call_command *cmd; 3606 struct ice_aqc_dnl_call buf = {}; 3607 struct ice_aq_desc desc; 3608 int err; 3609 3610 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3611 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3612 cpu_to_le16(op_code | (serdes_num & 0xF)); 3613 cmd = &desc.params.dnl_call; 3614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3615 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF | 3616 ICE_AQ_FLAG_RD | 3617 ICE_AQ_FLAG_SI); 3618 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3619 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3620 3621 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3622 NULL); 3623 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3624 3625 return err; 3626 } 3627 3628 #define FEC_REG_PORT(port) { \ 3629 FEC_CORR_LOW_REG_PORT##port, \ 3630 FEC_CORR_HIGH_REG_PORT##port, \ 3631 FEC_UNCORR_LOW_REG_PORT##port, \ 3632 FEC_UNCORR_HIGH_REG_PORT##port, \ 3633 } 3634 3635 static const u32 fec_reg[][ICE_FEC_MAX] = { 3636 FEC_REG_PORT(0), 3637 FEC_REG_PORT(1), 3638 FEC_REG_PORT(2), 3639 FEC_REG_PORT(3) 3640 }; 3641 3642 /** 3643 * ice_aq_get_fec_stats - reads fec stats from phy 3644 * @hw: pointer to the HW struct 3645 * @pcs_quad: represents pcsquad of user input serdes 3646 * @pcs_port: represents the pcs port number part of above pcs quad 3647 * @fec_type: represents FEC stats type 3648 * @output: pointer to the caller-supplied buffer to return requested fec stats 3649 * 3650 * Return: non-zero status on error and 0 on success. 3651 */ 3652 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3653 enum ice_fec_stats_types fec_type, u32 *output) 3654 { 3655 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI); 3656 struct ice_sbq_msg_input msg = {}; 3657 u32 receiver_id, reg_offset; 3658 int err; 3659 3660 if (pcs_port > 3) 3661 return -EINVAL; 3662 3663 reg_offset = fec_reg[pcs_port][fec_type]; 3664 3665 if (pcs_quad == 0) 3666 receiver_id = FEC_RECEIVER_ID_PCS0; 3667 else if (pcs_quad == 1) 3668 receiver_id = FEC_RECEIVER_ID_PCS1; 3669 else 3670 return -EINVAL; 3671 3672 msg.msg_addr_low = lower_16_bits(reg_offset); 3673 msg.msg_addr_high = receiver_id; 3674 msg.opcode = ice_sbq_msg_rd; 3675 msg.dest_dev = ice_sbq_dev_phy_0; 3676 3677 err = ice_sbq_rw_reg(hw, &msg, flag); 3678 if (err) 3679 return err; 3680 3681 *output = msg.data; 3682 return 0; 3683 } 3684 3685 /** 3686 * ice_cache_phy_user_req 3687 * @pi: port information structure 3688 * @cache_data: PHY logging data 3689 * @cache_mode: PHY logging mode 3690 * 3691 * Log the user request on (FC, FEC, SPEED) for later use. 3692 */ 3693 static void 3694 ice_cache_phy_user_req(struct ice_port_info *pi, 3695 struct ice_phy_cache_mode_data cache_data, 3696 enum ice_phy_cache_mode cache_mode) 3697 { 3698 if (!pi) 3699 return; 3700 3701 switch (cache_mode) { 3702 case ICE_FC_MODE: 3703 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3704 break; 3705 case ICE_SPEED_MODE: 3706 pi->phy.curr_user_speed_req = 3707 cache_data.data.curr_user_speed_req; 3708 break; 3709 case ICE_FEC_MODE: 3710 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3711 break; 3712 default: 3713 break; 3714 } 3715 } 3716 3717 /** 3718 * ice_caps_to_fc_mode 3719 * @caps: PHY capabilities 3720 * 3721 * Convert PHY FC capabilities to ice FC mode 3722 */ 3723 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3724 { 3725 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3726 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3727 return ICE_FC_FULL; 3728 3729 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3730 return ICE_FC_TX_PAUSE; 3731 3732 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3733 return ICE_FC_RX_PAUSE; 3734 3735 return ICE_FC_NONE; 3736 } 3737 3738 /** 3739 * ice_caps_to_fec_mode 3740 * @caps: PHY capabilities 3741 * @fec_options: Link FEC options 3742 * 3743 * Convert PHY FEC capabilities to ice FEC mode 3744 */ 3745 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3746 { 3747 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3748 return ICE_FEC_AUTO; 3749 3750 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3751 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3752 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3753 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3754 return ICE_FEC_BASER; 3755 3756 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3757 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3758 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3759 return ICE_FEC_RS; 3760 3761 return ICE_FEC_NONE; 3762 } 3763 3764 /** 3765 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3766 * @pi: port information structure 3767 * @cfg: PHY configuration data to set FC mode 3768 * @req_mode: FC mode to configure 3769 */ 3770 int 3771 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3772 enum ice_fc_mode req_mode) 3773 { 3774 struct ice_phy_cache_mode_data cache_data; 3775 u8 pause_mask = 0x0; 3776 3777 if (!pi || !cfg) 3778 return -EINVAL; 3779 3780 switch (req_mode) { 3781 case ICE_FC_FULL: 3782 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3783 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3784 break; 3785 case ICE_FC_RX_PAUSE: 3786 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3787 break; 3788 case ICE_FC_TX_PAUSE: 3789 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3790 break; 3791 default: 3792 break; 3793 } 3794 3795 /* clear the old pause settings */ 3796 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3797 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3798 3799 /* set the new capabilities */ 3800 cfg->caps |= pause_mask; 3801 3802 /* Cache user FC request */ 3803 cache_data.data.curr_user_fc_req = req_mode; 3804 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3805 3806 return 0; 3807 } 3808 3809 /** 3810 * ice_set_fc 3811 * @pi: port information structure 3812 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3813 * @ena_auto_link_update: enable automatic link update 3814 * 3815 * Set the requested flow control mode. 3816 */ 3817 int 3818 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3819 { 3820 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3821 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3822 struct ice_hw *hw; 3823 int status; 3824 3825 if (!pi || !aq_failures) 3826 return -EINVAL; 3827 3828 *aq_failures = 0; 3829 hw = pi->hw; 3830 3831 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3832 if (!pcaps) 3833 return -ENOMEM; 3834 3835 /* Get the current PHY config */ 3836 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3837 pcaps, NULL); 3838 if (status) { 3839 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3840 goto out; 3841 } 3842 3843 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3844 3845 /* Configure the set PHY data */ 3846 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3847 if (status) 3848 goto out; 3849 3850 /* If the capabilities have changed, then set the new config */ 3851 if (cfg.caps != pcaps->caps) { 3852 int retry_count, retry_max = 10; 3853 3854 /* Auto restart link so settings take effect */ 3855 if (ena_auto_link_update) 3856 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3857 3858 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3859 if (status) { 3860 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3861 goto out; 3862 } 3863 3864 /* Update the link info 3865 * It sometimes takes a really long time for link to 3866 * come back from the atomic reset. Thus, we wait a 3867 * little bit. 3868 */ 3869 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3870 status = ice_update_link_info(pi); 3871 3872 if (!status) 3873 break; 3874 3875 mdelay(100); 3876 } 3877 3878 if (status) 3879 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3880 } 3881 3882 out: 3883 return status; 3884 } 3885 3886 /** 3887 * ice_phy_caps_equals_cfg 3888 * @phy_caps: PHY capabilities 3889 * @phy_cfg: PHY configuration 3890 * 3891 * Helper function to determine if PHY capabilities matches PHY 3892 * configuration 3893 */ 3894 bool 3895 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3896 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3897 { 3898 u8 caps_mask, cfg_mask; 3899 3900 if (!phy_caps || !phy_cfg) 3901 return false; 3902 3903 /* These bits are not common between capabilities and configuration. 3904 * Do not use them to determine equality. 3905 */ 3906 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3907 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3908 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3909 3910 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3911 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3912 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3913 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3914 phy_caps->eee_cap != phy_cfg->eee_cap || 3915 phy_caps->eeer_value != phy_cfg->eeer_value || 3916 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3917 return false; 3918 3919 return true; 3920 } 3921 3922 /** 3923 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3924 * @pi: port information structure 3925 * @caps: PHY ability structure to copy date from 3926 * @cfg: PHY configuration structure to copy data to 3927 * 3928 * Helper function to copy AQC PHY get ability data to PHY set configuration 3929 * data structure 3930 */ 3931 void 3932 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3933 struct ice_aqc_get_phy_caps_data *caps, 3934 struct ice_aqc_set_phy_cfg_data *cfg) 3935 { 3936 if (!pi || !caps || !cfg) 3937 return; 3938 3939 memset(cfg, 0, sizeof(*cfg)); 3940 cfg->phy_type_low = caps->phy_type_low; 3941 cfg->phy_type_high = caps->phy_type_high; 3942 cfg->caps = caps->caps; 3943 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3944 cfg->eee_cap = caps->eee_cap; 3945 cfg->eeer_value = caps->eeer_value; 3946 cfg->link_fec_opt = caps->link_fec_options; 3947 cfg->module_compliance_enforcement = 3948 caps->module_compliance_enforcement; 3949 } 3950 3951 /** 3952 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3953 * @pi: port information structure 3954 * @cfg: PHY configuration data to set FEC mode 3955 * @fec: FEC mode to configure 3956 */ 3957 int 3958 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3959 enum ice_fec_mode fec) 3960 { 3961 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3962 struct ice_hw *hw; 3963 int status; 3964 3965 if (!pi || !cfg) 3966 return -EINVAL; 3967 3968 hw = pi->hw; 3969 3970 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3971 if (!pcaps) 3972 return -ENOMEM; 3973 3974 status = ice_aq_get_phy_caps(pi, false, 3975 (ice_fw_supports_report_dflt_cfg(hw) ? 3976 ICE_AQC_REPORT_DFLT_CFG : 3977 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3978 if (status) 3979 goto out; 3980 3981 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3982 cfg->link_fec_opt = pcaps->link_fec_options; 3983 3984 switch (fec) { 3985 case ICE_FEC_BASER: 3986 /* Clear RS bits, and AND BASE-R ability 3987 * bits and OR request bits. 3988 */ 3989 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3990 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3991 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3992 ICE_AQC_PHY_FEC_25G_KR_REQ; 3993 break; 3994 case ICE_FEC_RS: 3995 /* Clear BASE-R bits, and AND RS ability 3996 * bits and OR request bits. 3997 */ 3998 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3999 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4000 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4001 break; 4002 case ICE_FEC_NONE: 4003 /* Clear all FEC option bits. */ 4004 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4005 break; 4006 case ICE_FEC_AUTO: 4007 /* AND auto FEC bit, and all caps bits. */ 4008 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4009 cfg->link_fec_opt |= pcaps->link_fec_options; 4010 break; 4011 default: 4012 status = -EINVAL; 4013 break; 4014 } 4015 4016 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4017 !ice_fw_supports_report_dflt_cfg(hw)) { 4018 struct ice_link_default_override_tlv tlv = { 0 }; 4019 4020 status = ice_get_link_default_override(&tlv, pi); 4021 if (status) 4022 goto out; 4023 4024 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4025 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4026 cfg->link_fec_opt = tlv.fec_options; 4027 } 4028 4029 out: 4030 return status; 4031 } 4032 4033 /** 4034 * ice_get_link_status - get status of the HW network link 4035 * @pi: port information structure 4036 * @link_up: pointer to bool (true/false = linkup/linkdown) 4037 * 4038 * Variable link_up is true if link is up, false if link is down. 4039 * The variable link_up is invalid if status is non zero. As a 4040 * result of this call, link status reporting becomes enabled 4041 */ 4042 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4043 { 4044 struct ice_phy_info *phy_info; 4045 int status = 0; 4046 4047 if (!pi || !link_up) 4048 return -EINVAL; 4049 4050 phy_info = &pi->phy; 4051 4052 if (phy_info->get_link_info) { 4053 status = ice_update_link_info(pi); 4054 4055 if (status) 4056 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4057 status); 4058 } 4059 4060 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4061 4062 return status; 4063 } 4064 4065 /** 4066 * ice_aq_set_link_restart_an 4067 * @pi: pointer to the port information structure 4068 * @ena_link: if true: enable link, if false: disable link 4069 * @cd: pointer to command details structure or NULL 4070 * 4071 * Sets up the link and restarts the Auto-Negotiation over the link. 4072 */ 4073 int 4074 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4075 struct ice_sq_cd *cd) 4076 { 4077 struct ice_aqc_restart_an *cmd; 4078 struct ice_aq_desc desc; 4079 4080 cmd = &desc.params.restart_an; 4081 4082 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4083 4084 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4085 cmd->lport_num = pi->lport; 4086 if (ena_link) 4087 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4088 else 4089 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4090 4091 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4092 } 4093 4094 /** 4095 * ice_aq_set_event_mask 4096 * @hw: pointer to the HW struct 4097 * @port_num: port number of the physical function 4098 * @mask: event mask to be set 4099 * @cd: pointer to command details structure or NULL 4100 * 4101 * Set event mask (0x0613) 4102 */ 4103 int 4104 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4105 struct ice_sq_cd *cd) 4106 { 4107 struct ice_aqc_set_event_mask *cmd; 4108 struct ice_aq_desc desc; 4109 4110 cmd = &desc.params.set_event_mask; 4111 4112 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4113 4114 cmd->lport_num = port_num; 4115 4116 cmd->event_mask = cpu_to_le16(mask); 4117 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4118 } 4119 4120 /** 4121 * ice_aq_set_mac_loopback 4122 * @hw: pointer to the HW struct 4123 * @ena_lpbk: Enable or Disable loopback 4124 * @cd: pointer to command details structure or NULL 4125 * 4126 * Enable/disable loopback on a given port 4127 */ 4128 int 4129 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4130 { 4131 struct ice_aqc_set_mac_lb *cmd; 4132 struct ice_aq_desc desc; 4133 4134 cmd = &desc.params.set_mac_lb; 4135 4136 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4137 if (ena_lpbk) 4138 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4139 4140 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4141 } 4142 4143 /** 4144 * ice_aq_set_port_id_led 4145 * @pi: pointer to the port information 4146 * @is_orig_mode: is this LED set to original mode (by the net-list) 4147 * @cd: pointer to command details structure or NULL 4148 * 4149 * Set LED value for the given port (0x06e9) 4150 */ 4151 int 4152 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4153 struct ice_sq_cd *cd) 4154 { 4155 struct ice_aqc_set_port_id_led *cmd; 4156 struct ice_hw *hw = pi->hw; 4157 struct ice_aq_desc desc; 4158 4159 cmd = &desc.params.set_port_id_led; 4160 4161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4162 4163 if (is_orig_mode) 4164 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4165 else 4166 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4167 4168 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4169 } 4170 4171 /** 4172 * ice_aq_get_port_options 4173 * @hw: pointer to the HW struct 4174 * @options: buffer for the resultant port options 4175 * @option_count: input - size of the buffer in port options structures, 4176 * output - number of returned port options 4177 * @lport: logical port to call the command with (optional) 4178 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4179 * when PF owns more than 1 port it must be true 4180 * @active_option_idx: index of active port option in returned buffer 4181 * @active_option_valid: active option in returned buffer is valid 4182 * @pending_option_idx: index of pending port option in returned buffer 4183 * @pending_option_valid: pending option in returned buffer is valid 4184 * 4185 * Calls Get Port Options AQC (0x06ea) and verifies result. 4186 */ 4187 int 4188 ice_aq_get_port_options(struct ice_hw *hw, 4189 struct ice_aqc_get_port_options_elem *options, 4190 u8 *option_count, u8 lport, bool lport_valid, 4191 u8 *active_option_idx, bool *active_option_valid, 4192 u8 *pending_option_idx, bool *pending_option_valid) 4193 { 4194 struct ice_aqc_get_port_options *cmd; 4195 struct ice_aq_desc desc; 4196 int status; 4197 u8 i; 4198 4199 /* options buffer shall be able to hold max returned options */ 4200 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4201 return -EINVAL; 4202 4203 cmd = &desc.params.get_port_options; 4204 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4205 4206 if (lport_valid) 4207 cmd->lport_num = lport; 4208 cmd->lport_num_valid = lport_valid; 4209 4210 status = ice_aq_send_cmd(hw, &desc, options, 4211 *option_count * sizeof(*options), NULL); 4212 if (status) 4213 return status; 4214 4215 /* verify direct FW response & set output parameters */ 4216 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4217 cmd->port_options_count); 4218 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4219 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4220 cmd->port_options); 4221 if (*active_option_valid) { 4222 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4223 cmd->port_options); 4224 if (*active_option_idx > (*option_count - 1)) 4225 return -EIO; 4226 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4227 *active_option_idx); 4228 } 4229 4230 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4231 cmd->pending_port_option_status); 4232 if (*pending_option_valid) { 4233 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4234 cmd->pending_port_option_status); 4235 if (*pending_option_idx > (*option_count - 1)) 4236 return -EIO; 4237 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4238 *pending_option_idx); 4239 } 4240 4241 /* mask output options fields */ 4242 for (i = 0; i < *option_count; i++) { 4243 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4244 options[i].pmd); 4245 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4246 options[i].max_lane_speed); 4247 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4248 options[i].pmd, options[i].max_lane_speed); 4249 } 4250 4251 return 0; 4252 } 4253 4254 /** 4255 * ice_aq_set_port_option 4256 * @hw: pointer to the HW struct 4257 * @lport: logical port to call the command with 4258 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4259 * when PF owns more than 1 port it must be true 4260 * @new_option: new port option to be written 4261 * 4262 * Calls Set Port Options AQC (0x06eb). 4263 */ 4264 int 4265 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4266 u8 new_option) 4267 { 4268 struct ice_aqc_set_port_option *cmd; 4269 struct ice_aq_desc desc; 4270 4271 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4272 return -EINVAL; 4273 4274 cmd = &desc.params.set_port_option; 4275 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4276 4277 if (lport_valid) 4278 cmd->lport_num = lport; 4279 4280 cmd->lport_num_valid = lport_valid; 4281 cmd->selected_port_option = new_option; 4282 4283 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4284 } 4285 4286 /** 4287 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4288 * @hw: pointer to the hw struct 4289 * 4290 * Return: PHY lane number on success, negative error code otherwise. 4291 */ 4292 int ice_get_phy_lane_number(struct ice_hw *hw) 4293 { 4294 struct ice_aqc_get_port_options_elem *options; 4295 unsigned int lport = 0; 4296 unsigned int lane; 4297 int err; 4298 4299 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4300 if (!options) 4301 return -ENOMEM; 4302 4303 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4304 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4305 u8 speed, active_idx, pending_idx; 4306 bool active_valid, pending_valid; 4307 4308 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4309 true, &active_idx, &active_valid, 4310 &pending_idx, &pending_valid); 4311 if (err) 4312 goto err; 4313 4314 if (!active_valid) 4315 continue; 4316 4317 speed = options[active_idx].max_lane_speed; 4318 /* If we don't get speed for this lane, it's unoccupied */ 4319 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4320 continue; 4321 4322 if (hw->pf_id == lport) { 4323 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4324 ice_is_dual(hw) && !ice_is_primary(hw)) 4325 lane += ICE_PORTS_PER_QUAD; 4326 kfree(options); 4327 return lane; 4328 } 4329 lport++; 4330 } 4331 4332 /* PHY lane not found */ 4333 err = -ENXIO; 4334 err: 4335 kfree(options); 4336 return err; 4337 } 4338 4339 /** 4340 * ice_aq_sff_eeprom 4341 * @hw: pointer to the HW struct 4342 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4343 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4344 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4345 * @page: QSFP page 4346 * @set_page: set or ignore the page 4347 * @data: pointer to data buffer to be read/written to the I2C device. 4348 * @length: 1-16 for read, 1 for write. 4349 * @write: 0 read, 1 for write. 4350 * @cd: pointer to command details structure or NULL 4351 * 4352 * Read/Write SFF EEPROM (0x06EE) 4353 */ 4354 int 4355 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4356 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4357 bool write, struct ice_sq_cd *cd) 4358 { 4359 struct ice_aqc_sff_eeprom *cmd; 4360 struct ice_aq_desc desc; 4361 u16 i2c_bus_addr; 4362 int status; 4363 4364 if (!data || (mem_addr & 0xff00)) 4365 return -EINVAL; 4366 4367 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4368 cmd = &desc.params.read_write_sff_param; 4369 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4370 cmd->lport_num = (u8)(lport & 0xff); 4371 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4372 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4373 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4374 if (write) 4375 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4376 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4377 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4378 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4379 4380 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4381 return status; 4382 } 4383 4384 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4385 { 4386 switch (type) { 4387 case ICE_LUT_VSI: 4388 return ICE_LUT_VSI_SIZE; 4389 case ICE_LUT_GLOBAL: 4390 return ICE_LUT_GLOBAL_SIZE; 4391 case ICE_LUT_PF: 4392 return ICE_LUT_PF_SIZE; 4393 } 4394 WARN_ONCE(1, "incorrect type passed"); 4395 return ICE_LUT_VSI_SIZE; 4396 } 4397 4398 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4399 { 4400 switch (size) { 4401 case ICE_LUT_VSI_SIZE: 4402 return ICE_AQC_LUT_SIZE_SMALL; 4403 case ICE_LUT_GLOBAL_SIZE: 4404 return ICE_AQC_LUT_SIZE_512; 4405 case ICE_LUT_PF_SIZE: 4406 return ICE_AQC_LUT_SIZE_2K; 4407 } 4408 WARN_ONCE(1, "incorrect size passed"); 4409 return 0; 4410 } 4411 4412 /** 4413 * __ice_aq_get_set_rss_lut 4414 * @hw: pointer to the hardware structure 4415 * @params: RSS LUT parameters 4416 * @set: set true to set the table, false to get the table 4417 * 4418 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4419 */ 4420 static int 4421 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4422 struct ice_aq_get_set_rss_lut_params *params, bool set) 4423 { 4424 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4425 enum ice_lut_type lut_type = params->lut_type; 4426 struct ice_aqc_get_set_rss_lut *desc_params; 4427 enum ice_aqc_lut_flags flags; 4428 enum ice_lut_size lut_size; 4429 struct ice_aq_desc desc; 4430 u8 *lut = params->lut; 4431 4432 4433 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4434 return -EINVAL; 4435 4436 lut_size = ice_lut_type_to_size(lut_type); 4437 if (lut_size > params->lut_size) 4438 return -EINVAL; 4439 else if (set && lut_size != params->lut_size) 4440 return -EINVAL; 4441 4442 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4443 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4444 if (set) 4445 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4446 4447 desc_params = &desc.params.get_set_rss_lut; 4448 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4449 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4450 4451 if (lut_type == ICE_LUT_GLOBAL) 4452 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4453 params->global_lut_id); 4454 4455 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4456 desc_params->flags = cpu_to_le16(flags); 4457 4458 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4459 } 4460 4461 /** 4462 * ice_aq_get_rss_lut 4463 * @hw: pointer to the hardware structure 4464 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4465 * 4466 * get the RSS lookup table, PF or VSI type 4467 */ 4468 int 4469 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4470 { 4471 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4472 } 4473 4474 /** 4475 * ice_aq_set_rss_lut 4476 * @hw: pointer to the hardware structure 4477 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4478 * 4479 * set the RSS lookup table, PF or VSI type 4480 */ 4481 int 4482 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4483 { 4484 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4485 } 4486 4487 /** 4488 * __ice_aq_get_set_rss_key 4489 * @hw: pointer to the HW struct 4490 * @vsi_id: VSI FW index 4491 * @key: pointer to key info struct 4492 * @set: set true to set the key, false to get the key 4493 * 4494 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4495 */ 4496 static int 4497 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4498 struct ice_aqc_get_set_rss_keys *key, bool set) 4499 { 4500 struct ice_aqc_get_set_rss_key *desc_params; 4501 u16 key_size = sizeof(*key); 4502 struct ice_aq_desc desc; 4503 4504 if (set) { 4505 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4506 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4507 } else { 4508 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4509 } 4510 4511 desc_params = &desc.params.get_set_rss_key; 4512 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4513 4514 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4515 } 4516 4517 /** 4518 * ice_aq_get_rss_key 4519 * @hw: pointer to the HW struct 4520 * @vsi_handle: software VSI handle 4521 * @key: pointer to key info struct 4522 * 4523 * get the RSS key per VSI 4524 */ 4525 int 4526 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4527 struct ice_aqc_get_set_rss_keys *key) 4528 { 4529 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4530 return -EINVAL; 4531 4532 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4533 key, false); 4534 } 4535 4536 /** 4537 * ice_aq_set_rss_key 4538 * @hw: pointer to the HW struct 4539 * @vsi_handle: software VSI handle 4540 * @keys: pointer to key info struct 4541 * 4542 * set the RSS key per VSI 4543 */ 4544 int 4545 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4546 struct ice_aqc_get_set_rss_keys *keys) 4547 { 4548 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4549 return -EINVAL; 4550 4551 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4552 keys, true); 4553 } 4554 4555 /** 4556 * ice_aq_add_lan_txq 4557 * @hw: pointer to the hardware structure 4558 * @num_qgrps: Number of added queue groups 4559 * @qg_list: list of queue groups to be added 4560 * @buf_size: size of buffer for indirect command 4561 * @cd: pointer to command details structure or NULL 4562 * 4563 * Add Tx LAN queue (0x0C30) 4564 * 4565 * NOTE: 4566 * Prior to calling add Tx LAN queue: 4567 * Initialize the following as part of the Tx queue context: 4568 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4569 * Cache profile and Packet shaper profile. 4570 * 4571 * After add Tx LAN queue AQ command is completed: 4572 * Interrupts should be associated with specific queues, 4573 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4574 * flow. 4575 */ 4576 static int 4577 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4578 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4579 struct ice_sq_cd *cd) 4580 { 4581 struct ice_aqc_add_tx_qgrp *list; 4582 struct ice_aqc_add_txqs *cmd; 4583 struct ice_aq_desc desc; 4584 u16 i, sum_size = 0; 4585 4586 cmd = &desc.params.add_txqs; 4587 4588 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4589 4590 if (!qg_list) 4591 return -EINVAL; 4592 4593 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4594 return -EINVAL; 4595 4596 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4597 sum_size += struct_size(list, txqs, list->num_txqs); 4598 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4599 list->num_txqs); 4600 } 4601 4602 if (buf_size != sum_size) 4603 return -EINVAL; 4604 4605 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4606 4607 cmd->num_qgrps = num_qgrps; 4608 4609 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4610 } 4611 4612 /** 4613 * ice_aq_dis_lan_txq 4614 * @hw: pointer to the hardware structure 4615 * @num_qgrps: number of groups in the list 4616 * @qg_list: the list of groups to disable 4617 * @buf_size: the total size of the qg_list buffer in bytes 4618 * @rst_src: if called due to reset, specifies the reset source 4619 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4620 * @cd: pointer to command details structure or NULL 4621 * 4622 * Disable LAN Tx queue (0x0C31) 4623 */ 4624 static int 4625 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4626 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4627 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4628 struct ice_sq_cd *cd) 4629 { 4630 struct ice_aqc_dis_txq_item *item; 4631 struct ice_aqc_dis_txqs *cmd; 4632 struct ice_aq_desc desc; 4633 u16 vmvf_and_timeout; 4634 u16 i, sz = 0; 4635 int status; 4636 4637 cmd = &desc.params.dis_txqs; 4638 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4639 4640 /* qg_list can be NULL only in VM/VF reset flow */ 4641 if (!qg_list && !rst_src) 4642 return -EINVAL; 4643 4644 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4645 return -EINVAL; 4646 4647 cmd->num_entries = num_qgrps; 4648 4649 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4650 4651 switch (rst_src) { 4652 case ICE_VM_RESET: 4653 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4654 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4655 break; 4656 case ICE_VF_RESET: 4657 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4658 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4659 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4660 ICE_AQC_Q_DIS_VMVF_NUM_M; 4661 break; 4662 case ICE_NO_RESET: 4663 default: 4664 break; 4665 } 4666 4667 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4668 4669 /* flush pipe on time out */ 4670 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4671 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4672 if (!qg_list) 4673 goto do_aq; 4674 4675 /* set RD bit to indicate that command buffer is provided by the driver 4676 * and it needs to be read by the firmware 4677 */ 4678 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4679 4680 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4681 u16 item_size = struct_size(item, q_id, item->num_qs); 4682 4683 /* If the num of queues is even, add 2 bytes of padding */ 4684 if ((item->num_qs % 2) == 0) 4685 item_size += 2; 4686 4687 sz += item_size; 4688 4689 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4690 } 4691 4692 if (buf_size != sz) 4693 return -EINVAL; 4694 4695 do_aq: 4696 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4697 if (status) { 4698 if (!qg_list) 4699 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4700 vmvf_num, hw->adminq.sq_last_status); 4701 else 4702 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4703 le16_to_cpu(qg_list[0].q_id[0]), 4704 hw->adminq.sq_last_status); 4705 } 4706 return status; 4707 } 4708 4709 /** 4710 * ice_aq_cfg_lan_txq 4711 * @hw: pointer to the hardware structure 4712 * @buf: buffer for command 4713 * @buf_size: size of buffer in bytes 4714 * @num_qs: number of queues being configured 4715 * @oldport: origination lport 4716 * @newport: destination lport 4717 * @cd: pointer to command details structure or NULL 4718 * 4719 * Move/Configure LAN Tx queue (0x0C32) 4720 * 4721 * There is a better AQ command to use for moving nodes, so only coding 4722 * this one for configuring the node. 4723 */ 4724 int 4725 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4726 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4727 struct ice_sq_cd *cd) 4728 { 4729 struct ice_aqc_cfg_txqs *cmd; 4730 struct ice_aq_desc desc; 4731 int status; 4732 4733 cmd = &desc.params.cfg_txqs; 4734 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4735 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4736 4737 if (!buf) 4738 return -EINVAL; 4739 4740 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4741 cmd->num_qs = num_qs; 4742 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4743 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4744 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4745 cmd->blocked_cgds = 0; 4746 4747 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4748 if (status) 4749 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4750 hw->adminq.sq_last_status); 4751 return status; 4752 } 4753 4754 /** 4755 * ice_aq_add_rdma_qsets 4756 * @hw: pointer to the hardware structure 4757 * @num_qset_grps: Number of RDMA Qset groups 4758 * @qset_list: list of Qset groups to be added 4759 * @buf_size: size of buffer for indirect command 4760 * @cd: pointer to command details structure or NULL 4761 * 4762 * Add Tx RDMA Qsets (0x0C33) 4763 */ 4764 static int 4765 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4766 struct ice_aqc_add_rdma_qset_data *qset_list, 4767 u16 buf_size, struct ice_sq_cd *cd) 4768 { 4769 struct ice_aqc_add_rdma_qset_data *list; 4770 struct ice_aqc_add_rdma_qset *cmd; 4771 struct ice_aq_desc desc; 4772 u16 i, sum_size = 0; 4773 4774 cmd = &desc.params.add_rdma_qset; 4775 4776 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4777 4778 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4779 return -EINVAL; 4780 4781 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4782 u16 num_qsets = le16_to_cpu(list->num_qsets); 4783 4784 sum_size += struct_size(list, rdma_qsets, num_qsets); 4785 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4786 num_qsets); 4787 } 4788 4789 if (buf_size != sum_size) 4790 return -EINVAL; 4791 4792 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4793 4794 cmd->num_qset_grps = num_qset_grps; 4795 4796 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4797 } 4798 4799 /* End of FW Admin Queue command wrappers */ 4800 4801 /** 4802 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4803 * @hw: pointer to the HW struct 4804 * @vsi_handle: software VSI handle 4805 * @tc: TC number 4806 * @q_handle: software queue handle 4807 */ 4808 struct ice_q_ctx * 4809 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4810 { 4811 struct ice_vsi_ctx *vsi; 4812 struct ice_q_ctx *q_ctx; 4813 4814 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4815 if (!vsi) 4816 return NULL; 4817 if (q_handle >= vsi->num_lan_q_entries[tc]) 4818 return NULL; 4819 if (!vsi->lan_q_ctx[tc]) 4820 return NULL; 4821 q_ctx = vsi->lan_q_ctx[tc]; 4822 return &q_ctx[q_handle]; 4823 } 4824 4825 /** 4826 * ice_ena_vsi_txq 4827 * @pi: port information structure 4828 * @vsi_handle: software VSI handle 4829 * @tc: TC number 4830 * @q_handle: software queue handle 4831 * @num_qgrps: Number of added queue groups 4832 * @buf: list of queue groups to be added 4833 * @buf_size: size of buffer for indirect command 4834 * @cd: pointer to command details structure or NULL 4835 * 4836 * This function adds one LAN queue 4837 */ 4838 int 4839 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4840 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4841 struct ice_sq_cd *cd) 4842 { 4843 struct ice_aqc_txsched_elem_data node = { 0 }; 4844 struct ice_sched_node *parent; 4845 struct ice_q_ctx *q_ctx; 4846 struct ice_hw *hw; 4847 int status; 4848 4849 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4850 return -EIO; 4851 4852 if (num_qgrps > 1 || buf->num_txqs > 1) 4853 return -ENOSPC; 4854 4855 hw = pi->hw; 4856 4857 if (!ice_is_vsi_valid(hw, vsi_handle)) 4858 return -EINVAL; 4859 4860 mutex_lock(&pi->sched_lock); 4861 4862 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4863 if (!q_ctx) { 4864 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4865 q_handle); 4866 status = -EINVAL; 4867 goto ena_txq_exit; 4868 } 4869 4870 /* find a parent node */ 4871 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4872 ICE_SCHED_NODE_OWNER_LAN); 4873 if (!parent) { 4874 status = -EINVAL; 4875 goto ena_txq_exit; 4876 } 4877 4878 buf->parent_teid = parent->info.node_teid; 4879 node.parent_teid = parent->info.node_teid; 4880 /* Mark that the values in the "generic" section as valid. The default 4881 * value in the "generic" section is zero. This means that : 4882 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4883 * - 0 priority among siblings, indicated by Bit 1-3. 4884 * - WFQ, indicated by Bit 4. 4885 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4886 * Bit 5-6. 4887 * - Bit 7 is reserved. 4888 * Without setting the generic section as valid in valid_sections, the 4889 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4890 */ 4891 buf->txqs[0].info.valid_sections = 4892 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4893 ICE_AQC_ELEM_VALID_EIR; 4894 buf->txqs[0].info.generic = 0; 4895 buf->txqs[0].info.cir_bw.bw_profile_idx = 4896 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4897 buf->txqs[0].info.cir_bw.bw_alloc = 4898 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4899 buf->txqs[0].info.eir_bw.bw_profile_idx = 4900 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4901 buf->txqs[0].info.eir_bw.bw_alloc = 4902 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4903 4904 /* add the LAN queue */ 4905 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4906 if (status) { 4907 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4908 le16_to_cpu(buf->txqs[0].txq_id), 4909 hw->adminq.sq_last_status); 4910 goto ena_txq_exit; 4911 } 4912 4913 node.node_teid = buf->txqs[0].q_teid; 4914 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4915 q_ctx->q_handle = q_handle; 4916 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4917 4918 /* add a leaf node into scheduler tree queue layer */ 4919 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4920 if (!status) 4921 status = ice_sched_replay_q_bw(pi, q_ctx); 4922 4923 ena_txq_exit: 4924 mutex_unlock(&pi->sched_lock); 4925 return status; 4926 } 4927 4928 /** 4929 * ice_dis_vsi_txq 4930 * @pi: port information structure 4931 * @vsi_handle: software VSI handle 4932 * @tc: TC number 4933 * @num_queues: number of queues 4934 * @q_handles: pointer to software queue handle array 4935 * @q_ids: pointer to the q_id array 4936 * @q_teids: pointer to queue node teids 4937 * @rst_src: if called due to reset, specifies the reset source 4938 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4939 * @cd: pointer to command details structure or NULL 4940 * 4941 * This function removes queues and their corresponding nodes in SW DB 4942 */ 4943 int 4944 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4945 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4946 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4947 struct ice_sq_cd *cd) 4948 { 4949 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4950 u16 i, buf_size = __struct_size(qg_list); 4951 struct ice_q_ctx *q_ctx; 4952 int status = -ENOENT; 4953 struct ice_hw *hw; 4954 4955 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4956 return -EIO; 4957 4958 hw = pi->hw; 4959 4960 if (!num_queues) { 4961 /* if queue is disabled already yet the disable queue command 4962 * has to be sent to complete the VF reset, then call 4963 * ice_aq_dis_lan_txq without any queue information 4964 */ 4965 if (rst_src) 4966 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4967 vmvf_num, NULL); 4968 return -EIO; 4969 } 4970 4971 mutex_lock(&pi->sched_lock); 4972 4973 for (i = 0; i < num_queues; i++) { 4974 struct ice_sched_node *node; 4975 4976 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4977 if (!node) 4978 continue; 4979 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4980 if (!q_ctx) { 4981 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4982 q_handles[i]); 4983 continue; 4984 } 4985 if (q_ctx->q_handle != q_handles[i]) { 4986 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4987 q_ctx->q_handle, q_handles[i]); 4988 continue; 4989 } 4990 qg_list->parent_teid = node->info.parent_teid; 4991 qg_list->num_qs = 1; 4992 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4993 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4994 vmvf_num, cd); 4995 4996 if (status) 4997 break; 4998 ice_free_sched_node(pi, node); 4999 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5000 q_ctx->q_teid = ICE_INVAL_TEID; 5001 } 5002 mutex_unlock(&pi->sched_lock); 5003 return status; 5004 } 5005 5006 /** 5007 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5008 * @pi: port information structure 5009 * @vsi_handle: software VSI handle 5010 * @tc_bitmap: TC bitmap 5011 * @maxqs: max queues array per TC 5012 * @owner: LAN or RDMA 5013 * 5014 * This function adds/updates the VSI queues per TC. 5015 */ 5016 static int 5017 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5018 u16 *maxqs, u8 owner) 5019 { 5020 int status = 0; 5021 u8 i; 5022 5023 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5024 return -EIO; 5025 5026 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5027 return -EINVAL; 5028 5029 mutex_lock(&pi->sched_lock); 5030 5031 ice_for_each_traffic_class(i) { 5032 /* configuration is possible only if TC node is present */ 5033 if (!ice_sched_get_tc_node(pi, i)) 5034 continue; 5035 5036 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5037 ice_is_tc_ena(tc_bitmap, i)); 5038 if (status) 5039 break; 5040 } 5041 5042 mutex_unlock(&pi->sched_lock); 5043 return status; 5044 } 5045 5046 /** 5047 * ice_cfg_vsi_lan - configure VSI LAN queues 5048 * @pi: port information structure 5049 * @vsi_handle: software VSI handle 5050 * @tc_bitmap: TC bitmap 5051 * @max_lanqs: max LAN queues array per TC 5052 * 5053 * This function adds/updates the VSI LAN queues per TC. 5054 */ 5055 int 5056 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5057 u16 *max_lanqs) 5058 { 5059 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5060 ICE_SCHED_NODE_OWNER_LAN); 5061 } 5062 5063 /** 5064 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5065 * @pi: port information structure 5066 * @vsi_handle: software VSI handle 5067 * @tc_bitmap: TC bitmap 5068 * @max_rdmaqs: max RDMA queues array per TC 5069 * 5070 * This function adds/updates the VSI RDMA queues per TC. 5071 */ 5072 int 5073 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5074 u16 *max_rdmaqs) 5075 { 5076 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5077 ICE_SCHED_NODE_OWNER_RDMA); 5078 } 5079 5080 /** 5081 * ice_ena_vsi_rdma_qset 5082 * @pi: port information structure 5083 * @vsi_handle: software VSI handle 5084 * @tc: TC number 5085 * @rdma_qset: pointer to RDMA Qset 5086 * @num_qsets: number of RDMA Qsets 5087 * @qset_teid: pointer to Qset node TEIDs 5088 * 5089 * This function adds RDMA Qset 5090 */ 5091 int 5092 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5093 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5094 { 5095 struct ice_aqc_txsched_elem_data node = { 0 }; 5096 struct ice_aqc_add_rdma_qset_data *buf; 5097 struct ice_sched_node *parent; 5098 struct ice_hw *hw; 5099 u16 i, buf_size; 5100 int ret; 5101 5102 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5103 return -EIO; 5104 hw = pi->hw; 5105 5106 if (!ice_is_vsi_valid(hw, vsi_handle)) 5107 return -EINVAL; 5108 5109 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5110 buf = kzalloc(buf_size, GFP_KERNEL); 5111 if (!buf) 5112 return -ENOMEM; 5113 mutex_lock(&pi->sched_lock); 5114 5115 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5116 ICE_SCHED_NODE_OWNER_RDMA); 5117 if (!parent) { 5118 ret = -EINVAL; 5119 goto rdma_error_exit; 5120 } 5121 buf->parent_teid = parent->info.node_teid; 5122 node.parent_teid = parent->info.node_teid; 5123 5124 buf->num_qsets = cpu_to_le16(num_qsets); 5125 for (i = 0; i < num_qsets; i++) { 5126 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5127 buf->rdma_qsets[i].info.valid_sections = 5128 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5129 ICE_AQC_ELEM_VALID_EIR; 5130 buf->rdma_qsets[i].info.generic = 0; 5131 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5132 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5133 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5134 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5135 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5136 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5137 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5138 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5139 } 5140 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5141 if (ret) { 5142 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5143 goto rdma_error_exit; 5144 } 5145 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5146 for (i = 0; i < num_qsets; i++) { 5147 node.node_teid = buf->rdma_qsets[i].qset_teid; 5148 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5149 &node, NULL); 5150 if (ret) 5151 break; 5152 qset_teid[i] = le32_to_cpu(node.node_teid); 5153 } 5154 rdma_error_exit: 5155 mutex_unlock(&pi->sched_lock); 5156 kfree(buf); 5157 return ret; 5158 } 5159 5160 /** 5161 * ice_dis_vsi_rdma_qset - free RDMA resources 5162 * @pi: port_info struct 5163 * @count: number of RDMA Qsets to free 5164 * @qset_teid: TEID of Qset node 5165 * @q_id: list of queue IDs being disabled 5166 */ 5167 int 5168 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5169 u16 *q_id) 5170 { 5171 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5172 u16 qg_size = __struct_size(qg_list); 5173 struct ice_hw *hw; 5174 int status = 0; 5175 int i; 5176 5177 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5178 return -EIO; 5179 5180 hw = pi->hw; 5181 5182 mutex_lock(&pi->sched_lock); 5183 5184 for (i = 0; i < count; i++) { 5185 struct ice_sched_node *node; 5186 5187 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5188 if (!node) 5189 continue; 5190 5191 qg_list->parent_teid = node->info.parent_teid; 5192 qg_list->num_qs = 1; 5193 qg_list->q_id[0] = 5194 cpu_to_le16(q_id[i] | 5195 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5196 5197 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5198 ICE_NO_RESET, 0, NULL); 5199 if (status) 5200 break; 5201 5202 ice_free_sched_node(pi, node); 5203 } 5204 5205 mutex_unlock(&pi->sched_lock); 5206 return status; 5207 } 5208 5209 /** 5210 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5211 * @hw: pointer to the HW struct 5212 * @dpll_idx: index of dpll to be measured 5213 * @meas: array to be filled with results 5214 * @meas_num: max number of results array can hold 5215 * 5216 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5217 * pins on given dpll. 5218 * 5219 * Return: 0 on success or negative value on failure. 5220 */ 5221 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5222 struct ice_cgu_input_measure *meas, 5223 u16 meas_num) 5224 { 5225 struct ice_aqc_get_cgu_input_measure *cmd; 5226 struct ice_aq_desc desc; 5227 5228 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5229 cmd = &desc.params.get_cgu_input_measure; 5230 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5231 5232 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5233 } 5234 5235 /** 5236 * ice_aq_get_cgu_abilities - get cgu abilities 5237 * @hw: pointer to the HW struct 5238 * @abilities: CGU abilities 5239 * 5240 * Get CGU abilities (0x0C61) 5241 * Return: 0 on success or negative value on failure. 5242 */ 5243 int 5244 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5245 struct ice_aqc_get_cgu_abilities *abilities) 5246 { 5247 struct ice_aq_desc desc; 5248 5249 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5250 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5251 } 5252 5253 /** 5254 * ice_aq_set_input_pin_cfg - set input pin config 5255 * @hw: pointer to the HW struct 5256 * @input_idx: Input index 5257 * @flags1: Input flags 5258 * @flags2: Input flags 5259 * @freq: Frequency in Hz 5260 * @phase_delay: Delay in ps 5261 * 5262 * Set CGU input config (0x0C62) 5263 * Return: 0 on success or negative value on failure. 5264 */ 5265 int 5266 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5267 u32 freq, s32 phase_delay) 5268 { 5269 struct ice_aqc_set_cgu_input_config *cmd; 5270 struct ice_aq_desc desc; 5271 5272 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5273 cmd = &desc.params.set_cgu_input_config; 5274 cmd->input_idx = input_idx; 5275 cmd->flags1 = flags1; 5276 cmd->flags2 = flags2; 5277 cmd->freq = cpu_to_le32(freq); 5278 cmd->phase_delay = cpu_to_le32(phase_delay); 5279 5280 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5281 } 5282 5283 /** 5284 * ice_aq_get_input_pin_cfg - get input pin config 5285 * @hw: pointer to the HW struct 5286 * @input_idx: Input index 5287 * @status: Pin status 5288 * @type: Pin type 5289 * @flags1: Input flags 5290 * @flags2: Input flags 5291 * @freq: Frequency in Hz 5292 * @phase_delay: Delay in ps 5293 * 5294 * Get CGU input config (0x0C63) 5295 * Return: 0 on success or negative value on failure. 5296 */ 5297 int 5298 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5299 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5300 { 5301 struct ice_aqc_get_cgu_input_config *cmd; 5302 struct ice_aq_desc desc; 5303 int ret; 5304 5305 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5306 cmd = &desc.params.get_cgu_input_config; 5307 cmd->input_idx = input_idx; 5308 5309 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5310 if (!ret) { 5311 if (status) 5312 *status = cmd->status; 5313 if (type) 5314 *type = cmd->type; 5315 if (flags1) 5316 *flags1 = cmd->flags1; 5317 if (flags2) 5318 *flags2 = cmd->flags2; 5319 if (freq) 5320 *freq = le32_to_cpu(cmd->freq); 5321 if (phase_delay) 5322 *phase_delay = le32_to_cpu(cmd->phase_delay); 5323 } 5324 5325 return ret; 5326 } 5327 5328 /** 5329 * ice_aq_set_output_pin_cfg - set output pin config 5330 * @hw: pointer to the HW struct 5331 * @output_idx: Output index 5332 * @flags: Output flags 5333 * @src_sel: Index of DPLL block 5334 * @freq: Output frequency 5335 * @phase_delay: Output phase compensation 5336 * 5337 * Set CGU output config (0x0C64) 5338 * Return: 0 on success or negative value on failure. 5339 */ 5340 int 5341 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5342 u8 src_sel, u32 freq, s32 phase_delay) 5343 { 5344 struct ice_aqc_set_cgu_output_config *cmd; 5345 struct ice_aq_desc desc; 5346 5347 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5348 cmd = &desc.params.set_cgu_output_config; 5349 cmd->output_idx = output_idx; 5350 cmd->flags = flags; 5351 cmd->src_sel = src_sel; 5352 cmd->freq = cpu_to_le32(freq); 5353 cmd->phase_delay = cpu_to_le32(phase_delay); 5354 5355 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5356 } 5357 5358 /** 5359 * ice_aq_get_output_pin_cfg - get output pin config 5360 * @hw: pointer to the HW struct 5361 * @output_idx: Output index 5362 * @flags: Output flags 5363 * @src_sel: Internal DPLL source 5364 * @freq: Output frequency 5365 * @src_freq: Source frequency 5366 * 5367 * Get CGU output config (0x0C65) 5368 * Return: 0 on success or negative value on failure. 5369 */ 5370 int 5371 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5372 u8 *src_sel, u32 *freq, u32 *src_freq) 5373 { 5374 struct ice_aqc_get_cgu_output_config *cmd; 5375 struct ice_aq_desc desc; 5376 int ret; 5377 5378 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5379 cmd = &desc.params.get_cgu_output_config; 5380 cmd->output_idx = output_idx; 5381 5382 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5383 if (!ret) { 5384 if (flags) 5385 *flags = cmd->flags; 5386 if (src_sel) 5387 *src_sel = cmd->src_sel; 5388 if (freq) 5389 *freq = le32_to_cpu(cmd->freq); 5390 if (src_freq) 5391 *src_freq = le32_to_cpu(cmd->src_freq); 5392 } 5393 5394 return ret; 5395 } 5396 5397 /** 5398 * ice_aq_get_cgu_dpll_status - get dpll status 5399 * @hw: pointer to the HW struct 5400 * @dpll_num: DPLL index 5401 * @ref_state: Reference clock state 5402 * @config: current DPLL config 5403 * @dpll_state: current DPLL state 5404 * @phase_offset: Phase offset in ns 5405 * @eec_mode: EEC_mode 5406 * 5407 * Get CGU DPLL status (0x0C66) 5408 * Return: 0 on success or negative value on failure. 5409 */ 5410 int 5411 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5412 u8 *dpll_state, u8 *config, s64 *phase_offset, 5413 u8 *eec_mode) 5414 { 5415 struct ice_aqc_get_cgu_dpll_status *cmd; 5416 struct ice_aq_desc desc; 5417 int status; 5418 5419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5420 cmd = &desc.params.get_cgu_dpll_status; 5421 cmd->dpll_num = dpll_num; 5422 5423 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5424 if (!status) { 5425 *ref_state = cmd->ref_state; 5426 *dpll_state = cmd->dpll_state; 5427 *config = cmd->config; 5428 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5429 *phase_offset <<= 32; 5430 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5431 *phase_offset = sign_extend64(*phase_offset, 47); 5432 *eec_mode = cmd->eec_mode; 5433 } 5434 5435 return status; 5436 } 5437 5438 /** 5439 * ice_aq_set_cgu_dpll_config - set dpll config 5440 * @hw: pointer to the HW struct 5441 * @dpll_num: DPLL index 5442 * @ref_state: Reference clock state 5443 * @config: DPLL config 5444 * @eec_mode: EEC mode 5445 * 5446 * Set CGU DPLL config (0x0C67) 5447 * Return: 0 on success or negative value on failure. 5448 */ 5449 int 5450 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5451 u8 config, u8 eec_mode) 5452 { 5453 struct ice_aqc_set_cgu_dpll_config *cmd; 5454 struct ice_aq_desc desc; 5455 5456 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5457 cmd = &desc.params.set_cgu_dpll_config; 5458 cmd->dpll_num = dpll_num; 5459 cmd->ref_state = ref_state; 5460 cmd->config = config; 5461 cmd->eec_mode = eec_mode; 5462 5463 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5464 } 5465 5466 /** 5467 * ice_aq_set_cgu_ref_prio - set input reference priority 5468 * @hw: pointer to the HW struct 5469 * @dpll_num: DPLL index 5470 * @ref_idx: Reference pin index 5471 * @ref_priority: Reference input priority 5472 * 5473 * Set CGU reference priority (0x0C68) 5474 * Return: 0 on success or negative value on failure. 5475 */ 5476 int 5477 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5478 u8 ref_priority) 5479 { 5480 struct ice_aqc_set_cgu_ref_prio *cmd; 5481 struct ice_aq_desc desc; 5482 5483 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5484 cmd = &desc.params.set_cgu_ref_prio; 5485 cmd->dpll_num = dpll_num; 5486 cmd->ref_idx = ref_idx; 5487 cmd->ref_priority = ref_priority; 5488 5489 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5490 } 5491 5492 /** 5493 * ice_aq_get_cgu_ref_prio - get input reference priority 5494 * @hw: pointer to the HW struct 5495 * @dpll_num: DPLL index 5496 * @ref_idx: Reference pin index 5497 * @ref_prio: Reference input priority 5498 * 5499 * Get CGU reference priority (0x0C69) 5500 * Return: 0 on success or negative value on failure. 5501 */ 5502 int 5503 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5504 u8 *ref_prio) 5505 { 5506 struct ice_aqc_get_cgu_ref_prio *cmd; 5507 struct ice_aq_desc desc; 5508 int status; 5509 5510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5511 cmd = &desc.params.get_cgu_ref_prio; 5512 cmd->dpll_num = dpll_num; 5513 cmd->ref_idx = ref_idx; 5514 5515 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5516 if (!status) 5517 *ref_prio = cmd->ref_priority; 5518 5519 return status; 5520 } 5521 5522 /** 5523 * ice_aq_get_cgu_info - get cgu info 5524 * @hw: pointer to the HW struct 5525 * @cgu_id: CGU ID 5526 * @cgu_cfg_ver: CGU config version 5527 * @cgu_fw_ver: CGU firmware version 5528 * 5529 * Get CGU info (0x0C6A) 5530 * Return: 0 on success or negative value on failure. 5531 */ 5532 int 5533 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5534 u32 *cgu_fw_ver) 5535 { 5536 struct ice_aqc_get_cgu_info *cmd; 5537 struct ice_aq_desc desc; 5538 int status; 5539 5540 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5541 cmd = &desc.params.get_cgu_info; 5542 5543 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5544 if (!status) { 5545 *cgu_id = le32_to_cpu(cmd->cgu_id); 5546 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5547 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5548 } 5549 5550 return status; 5551 } 5552 5553 /** 5554 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5555 * @hw: pointer to the HW struct 5556 * @phy_output: PHY reference clock output pin 5557 * @enable: GPIO state to be applied 5558 * @freq: PHY output frequency 5559 * 5560 * Set phy recovered clock as reference (0x0630) 5561 * Return: 0 on success or negative value on failure. 5562 */ 5563 int 5564 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5565 u32 *freq) 5566 { 5567 struct ice_aqc_set_phy_rec_clk_out *cmd; 5568 struct ice_aq_desc desc; 5569 int status; 5570 5571 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5572 cmd = &desc.params.set_phy_rec_clk_out; 5573 cmd->phy_output = phy_output; 5574 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5575 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5576 cmd->freq = cpu_to_le32(*freq); 5577 5578 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5579 if (!status) 5580 *freq = le32_to_cpu(cmd->freq); 5581 5582 return status; 5583 } 5584 5585 /** 5586 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5587 * @hw: pointer to the HW struct 5588 * @phy_output: PHY reference clock output pin 5589 * @port_num: Port number 5590 * @flags: PHY flags 5591 * @node_handle: PHY output frequency 5592 * 5593 * Get PHY recovered clock output info (0x0631) 5594 * Return: 0 on success or negative value on failure. 5595 */ 5596 int 5597 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5598 u8 *flags, u16 *node_handle) 5599 { 5600 struct ice_aqc_get_phy_rec_clk_out *cmd; 5601 struct ice_aq_desc desc; 5602 int status; 5603 5604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5605 cmd = &desc.params.get_phy_rec_clk_out; 5606 cmd->phy_output = *phy_output; 5607 5608 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5609 if (!status) { 5610 *phy_output = cmd->phy_output; 5611 if (port_num) 5612 *port_num = cmd->port_num; 5613 if (flags) 5614 *flags = cmd->flags; 5615 if (node_handle) 5616 *node_handle = le16_to_cpu(cmd->node_handle); 5617 } 5618 5619 return status; 5620 } 5621 5622 /** 5623 * ice_aq_get_sensor_reading 5624 * @hw: pointer to the HW struct 5625 * @data: pointer to data to be read from the sensor 5626 * 5627 * Get sensor reading (0x0632) 5628 */ 5629 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5630 struct ice_aqc_get_sensor_reading_resp *data) 5631 { 5632 struct ice_aqc_get_sensor_reading *cmd; 5633 struct ice_aq_desc desc; 5634 int status; 5635 5636 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5637 cmd = &desc.params.get_sensor_reading; 5638 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5639 #define ICE_INTERNAL_TEMP_SENSOR 0 5640 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5641 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5642 5643 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5644 if (!status) 5645 memcpy(data, &desc.params.get_sensor_reading_resp, 5646 sizeof(*data)); 5647 5648 return status; 5649 } 5650 5651 /** 5652 * ice_replay_pre_init - replay pre initialization 5653 * @hw: pointer to the HW struct 5654 * 5655 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5656 */ 5657 static int ice_replay_pre_init(struct ice_hw *hw) 5658 { 5659 struct ice_switch_info *sw = hw->switch_info; 5660 u8 i; 5661 5662 /* Delete old entries from replay filter list head if there is any */ 5663 ice_rm_all_sw_replay_rule_info(hw); 5664 /* In start of replay, move entries into replay_rules list, it 5665 * will allow adding rules entries back to filt_rules list, 5666 * which is operational list. 5667 */ 5668 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5669 list_replace_init(&sw->recp_list[i].filt_rules, 5670 &sw->recp_list[i].filt_replay_rules); 5671 ice_sched_replay_agg_vsi_preinit(hw); 5672 5673 return 0; 5674 } 5675 5676 /** 5677 * ice_replay_vsi - replay VSI configuration 5678 * @hw: pointer to the HW struct 5679 * @vsi_handle: driver VSI handle 5680 * 5681 * Restore all VSI configuration after reset. It is required to call this 5682 * function with main VSI first. 5683 */ 5684 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5685 { 5686 int status; 5687 5688 if (!ice_is_vsi_valid(hw, vsi_handle)) 5689 return -EINVAL; 5690 5691 /* Replay pre-initialization if there is any */ 5692 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5693 status = ice_replay_pre_init(hw); 5694 if (status) 5695 return status; 5696 } 5697 /* Replay per VSI all RSS configurations */ 5698 status = ice_replay_rss_cfg(hw, vsi_handle); 5699 if (status) 5700 return status; 5701 /* Replay per VSI all filters */ 5702 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5703 if (!status) 5704 status = ice_replay_vsi_agg(hw, vsi_handle); 5705 return status; 5706 } 5707 5708 /** 5709 * ice_replay_post - post replay configuration cleanup 5710 * @hw: pointer to the HW struct 5711 * 5712 * Post replay cleanup. 5713 */ 5714 void ice_replay_post(struct ice_hw *hw) 5715 { 5716 /* Delete old entries from replay filter list head */ 5717 ice_rm_all_sw_replay_rule_info(hw); 5718 ice_sched_replay_agg(hw); 5719 } 5720 5721 /** 5722 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5723 * @hw: ptr to the hardware info 5724 * @reg: offset of 64 bit HW register to read from 5725 * @prev_stat_loaded: bool to specify if previous stats are loaded 5726 * @prev_stat: ptr to previous loaded stat value 5727 * @cur_stat: ptr to current stat value 5728 */ 5729 void 5730 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5731 u64 *prev_stat, u64 *cur_stat) 5732 { 5733 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5734 5735 /* device stats are not reset at PFR, they likely will not be zeroed 5736 * when the driver starts. Thus, save the value from the first read 5737 * without adding to the statistic value so that we report stats which 5738 * count up from zero. 5739 */ 5740 if (!prev_stat_loaded) { 5741 *prev_stat = new_data; 5742 return; 5743 } 5744 5745 /* Calculate the difference between the new and old values, and then 5746 * add it to the software stat value. 5747 */ 5748 if (new_data >= *prev_stat) 5749 *cur_stat += new_data - *prev_stat; 5750 else 5751 /* to manage the potential roll-over */ 5752 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5753 5754 /* Update the previously stored value to prepare for next read */ 5755 *prev_stat = new_data; 5756 } 5757 5758 /** 5759 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5760 * @hw: ptr to the hardware info 5761 * @reg: offset of HW register to read from 5762 * @prev_stat_loaded: bool to specify if previous stats are loaded 5763 * @prev_stat: ptr to previous loaded stat value 5764 * @cur_stat: ptr to current stat value 5765 */ 5766 void 5767 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5768 u64 *prev_stat, u64 *cur_stat) 5769 { 5770 u32 new_data; 5771 5772 new_data = rd32(hw, reg); 5773 5774 /* device stats are not reset at PFR, they likely will not be zeroed 5775 * when the driver starts. Thus, save the value from the first read 5776 * without adding to the statistic value so that we report stats which 5777 * count up from zero. 5778 */ 5779 if (!prev_stat_loaded) { 5780 *prev_stat = new_data; 5781 return; 5782 } 5783 5784 /* Calculate the difference between the new and old values, and then 5785 * add it to the software stat value. 5786 */ 5787 if (new_data >= *prev_stat) 5788 *cur_stat += new_data - *prev_stat; 5789 else 5790 /* to manage the potential roll-over */ 5791 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5792 5793 /* Update the previously stored value to prepare for next read */ 5794 *prev_stat = new_data; 5795 } 5796 5797 /** 5798 * ice_sched_query_elem - query element information from HW 5799 * @hw: pointer to the HW struct 5800 * @node_teid: node TEID to be queried 5801 * @buf: buffer to element information 5802 * 5803 * This function queries HW element information 5804 */ 5805 int 5806 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5807 struct ice_aqc_txsched_elem_data *buf) 5808 { 5809 u16 buf_size, num_elem_ret = 0; 5810 int status; 5811 5812 buf_size = sizeof(*buf); 5813 memset(buf, 0, buf_size); 5814 buf->node_teid = cpu_to_le32(node_teid); 5815 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5816 NULL); 5817 if (status || num_elem_ret != 1) 5818 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5819 return status; 5820 } 5821 5822 /** 5823 * ice_aq_read_i2c 5824 * @hw: pointer to the hw struct 5825 * @topo_addr: topology address for a device to communicate with 5826 * @bus_addr: 7-bit I2C bus address 5827 * @addr: I2C memory address (I2C offset) with up to 16 bits 5828 * @params: I2C parameters: bit [7] - Repeated start, 5829 * bits [6:5] data offset size, 5830 * bit [4] - I2C address type, 5831 * bits [3:0] - data size to read (0-16 bytes) 5832 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5833 * @cd: pointer to command details structure or NULL 5834 * 5835 * Read I2C (0x06E2) 5836 */ 5837 int 5838 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5839 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5840 struct ice_sq_cd *cd) 5841 { 5842 struct ice_aq_desc desc = { 0 }; 5843 struct ice_aqc_i2c *cmd; 5844 u8 data_size; 5845 int status; 5846 5847 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5848 cmd = &desc.params.read_write_i2c; 5849 5850 if (!data) 5851 return -EINVAL; 5852 5853 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5854 5855 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5856 cmd->topo_addr = topo_addr; 5857 cmd->i2c_params = params; 5858 cmd->i2c_addr = addr; 5859 5860 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5861 if (!status) { 5862 struct ice_aqc_read_i2c_resp *resp; 5863 u8 i; 5864 5865 resp = &desc.params.read_i2c_resp; 5866 for (i = 0; i < data_size; i++) { 5867 *data = resp->i2c_data[i]; 5868 data++; 5869 } 5870 } 5871 5872 return status; 5873 } 5874 5875 /** 5876 * ice_aq_write_i2c 5877 * @hw: pointer to the hw struct 5878 * @topo_addr: topology address for a device to communicate with 5879 * @bus_addr: 7-bit I2C bus address 5880 * @addr: I2C memory address (I2C offset) with up to 16 bits 5881 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5882 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5883 * @cd: pointer to command details structure or NULL 5884 * 5885 * Write I2C (0x06E3) 5886 * 5887 * * Return: 5888 * * 0 - Successful write to the i2c device 5889 * * -EINVAL - Data size greater than 4 bytes 5890 * * -EIO - FW error 5891 */ 5892 int 5893 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5894 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5895 struct ice_sq_cd *cd) 5896 { 5897 struct ice_aq_desc desc = { 0 }; 5898 struct ice_aqc_i2c *cmd; 5899 u8 data_size; 5900 5901 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5902 cmd = &desc.params.read_write_i2c; 5903 5904 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5905 5906 /* data_size limited to 4 */ 5907 if (data_size > 4) 5908 return -EINVAL; 5909 5910 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5911 cmd->topo_addr = topo_addr; 5912 cmd->i2c_params = params; 5913 cmd->i2c_addr = addr; 5914 5915 memcpy(cmd->i2c_data, data, data_size); 5916 5917 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5918 } 5919 5920 /** 5921 * ice_get_pca9575_handle - find and return the PCA9575 controller 5922 * @hw: pointer to the hw struct 5923 * @pca9575_handle: GPIO controller's handle 5924 * 5925 * Find and return the GPIO controller's handle in the netlist. 5926 * When found - the value will be cached in the hw structure and following calls 5927 * will return cached value. 5928 * 5929 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5930 */ 5931 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5932 { 5933 struct ice_aqc_get_link_topo *cmd; 5934 struct ice_aq_desc desc; 5935 int err; 5936 u8 idx; 5937 5938 /* If handle was read previously return cached value */ 5939 if (hw->io_expander_handle) { 5940 *pca9575_handle = hw->io_expander_handle; 5941 return 0; 5942 } 5943 5944 #define SW_PCA9575_SFP_TOPO_IDX 2 5945 #define SW_PCA9575_QSFP_TOPO_IDX 1 5946 5947 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5948 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5949 idx = SW_PCA9575_SFP_TOPO_IDX; 5950 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5951 idx = SW_PCA9575_QSFP_TOPO_IDX; 5952 else 5953 return -ENXIO; 5954 5955 /* If handle was not detected read it from the netlist */ 5956 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5957 cmd = &desc.params.get_link_topo; 5958 cmd->addr.topo_params.node_type_ctx = 5959 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5960 cmd->addr.topo_params.index = idx; 5961 5962 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5963 if (err) 5964 return -ENXIO; 5965 5966 /* Verify if we found the right IO expander type */ 5967 if (desc.params.get_link_topo.node_part_num != 5968 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5969 return -ENXIO; 5970 5971 /* If present save the handle and return it */ 5972 hw->io_expander_handle = 5973 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5974 *pca9575_handle = hw->io_expander_handle; 5975 5976 return 0; 5977 } 5978 5979 /** 5980 * ice_read_pca9575_reg - read the register from the PCA9575 controller 5981 * @hw: pointer to the hw struct 5982 * @offset: GPIO controller register offset 5983 * @data: pointer to data to be read from the GPIO controller 5984 * 5985 * Return: 0 on success, negative error code otherwise. 5986 */ 5987 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5988 { 5989 struct ice_aqc_link_topo_addr link_topo; 5990 __le16 addr; 5991 u16 handle; 5992 int err; 5993 5994 memset(&link_topo, 0, sizeof(link_topo)); 5995 5996 err = ice_get_pca9575_handle(hw, &handle); 5997 if (err) 5998 return err; 5999 6000 link_topo.handle = cpu_to_le16(handle); 6001 link_topo.topo_params.node_type_ctx = 6002 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6003 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6004 6005 addr = cpu_to_le16((u16)offset); 6006 6007 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6008 } 6009 6010 /** 6011 * ice_aq_set_gpio 6012 * @hw: pointer to the hw struct 6013 * @gpio_ctrl_handle: GPIO controller node handle 6014 * @pin_idx: IO Number of the GPIO that needs to be set 6015 * @value: SW provide IO value to set in the LSB 6016 * @cd: pointer to command details structure or NULL 6017 * 6018 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6019 */ 6020 int 6021 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6022 struct ice_sq_cd *cd) 6023 { 6024 struct ice_aqc_gpio *cmd; 6025 struct ice_aq_desc desc; 6026 6027 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6028 cmd = &desc.params.read_write_gpio; 6029 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6030 cmd->gpio_num = pin_idx; 6031 cmd->gpio_val = value ? 1 : 0; 6032 6033 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6034 } 6035 6036 /** 6037 * ice_aq_get_gpio 6038 * @hw: pointer to the hw struct 6039 * @gpio_ctrl_handle: GPIO controller node handle 6040 * @pin_idx: IO Number of the GPIO that needs to be set 6041 * @value: IO value read 6042 * @cd: pointer to command details structure or NULL 6043 * 6044 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6045 * the topology 6046 */ 6047 int 6048 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6049 bool *value, struct ice_sq_cd *cd) 6050 { 6051 struct ice_aqc_gpio *cmd; 6052 struct ice_aq_desc desc; 6053 int status; 6054 6055 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6056 cmd = &desc.params.read_write_gpio; 6057 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6058 cmd->gpio_num = pin_idx; 6059 6060 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6061 if (status) 6062 return status; 6063 6064 *value = !!cmd->gpio_val; 6065 return 0; 6066 } 6067 6068 /** 6069 * ice_is_fw_api_min_ver 6070 * @hw: pointer to the hardware structure 6071 * @maj: major version 6072 * @min: minor version 6073 * @patch: patch version 6074 * 6075 * Checks if the firmware API is minimum version 6076 */ 6077 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6078 { 6079 if (hw->api_maj_ver == maj) { 6080 if (hw->api_min_ver > min) 6081 return true; 6082 if (hw->api_min_ver == min && hw->api_patch >= patch) 6083 return true; 6084 } else if (hw->api_maj_ver > maj) { 6085 return true; 6086 } 6087 6088 return false; 6089 } 6090 6091 /** 6092 * ice_fw_supports_link_override 6093 * @hw: pointer to the hardware structure 6094 * 6095 * Checks if the firmware supports link override 6096 */ 6097 bool ice_fw_supports_link_override(struct ice_hw *hw) 6098 { 6099 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6100 ICE_FW_API_LINK_OVERRIDE_MIN, 6101 ICE_FW_API_LINK_OVERRIDE_PATCH); 6102 } 6103 6104 /** 6105 * ice_get_link_default_override 6106 * @ldo: pointer to the link default override struct 6107 * @pi: pointer to the port info struct 6108 * 6109 * Gets the link default override for a port 6110 */ 6111 int 6112 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6113 struct ice_port_info *pi) 6114 { 6115 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6116 struct ice_hw *hw = pi->hw; 6117 int status; 6118 6119 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6120 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6121 if (status) { 6122 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6123 return status; 6124 } 6125 6126 /* Each port has its own config; calculate for our port */ 6127 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6128 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6129 6130 /* link options first */ 6131 status = ice_read_sr_word(hw, tlv_start, &buf); 6132 if (status) { 6133 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6134 return status; 6135 } 6136 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6137 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6138 ICE_LINK_OVERRIDE_PHY_CFG_S; 6139 6140 /* link PHY config */ 6141 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6142 status = ice_read_sr_word(hw, offset, &buf); 6143 if (status) { 6144 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6145 return status; 6146 } 6147 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6148 6149 /* PHY types low */ 6150 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6151 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6152 status = ice_read_sr_word(hw, (offset + i), &buf); 6153 if (status) { 6154 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6155 return status; 6156 } 6157 /* shift 16 bits at a time to fill 64 bits */ 6158 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6159 } 6160 6161 /* PHY types high */ 6162 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6163 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6164 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6165 status = ice_read_sr_word(hw, (offset + i), &buf); 6166 if (status) { 6167 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6168 return status; 6169 } 6170 /* shift 16 bits at a time to fill 64 bits */ 6171 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6172 } 6173 6174 return status; 6175 } 6176 6177 /** 6178 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6179 * @caps: get PHY capability data 6180 */ 6181 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6182 { 6183 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6184 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6185 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6186 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6187 return true; 6188 6189 return false; 6190 } 6191 6192 /** 6193 * ice_is_fw_health_report_supported - checks if firmware supports health events 6194 * @hw: pointer to the hardware structure 6195 * 6196 * Return: true if firmware supports health status reports, 6197 * false otherwise 6198 */ 6199 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6200 { 6201 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6202 ICE_FW_API_HEALTH_REPORT_MIN, 6203 ICE_FW_API_HEALTH_REPORT_PATCH); 6204 } 6205 6206 /** 6207 * ice_aq_set_health_status_cfg - Configure FW health events 6208 * @hw: pointer to the HW struct 6209 * @event_source: type of diagnostic events to enable 6210 * 6211 * Configure the health status event types that the firmware will send to this 6212 * PF. The supported event types are: PF-specific, all PFs, and global. 6213 * 6214 * Return: 0 on success, negative error code otherwise. 6215 */ 6216 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6217 { 6218 struct ice_aqc_set_health_status_cfg *cmd; 6219 struct ice_aq_desc desc; 6220 6221 cmd = &desc.params.set_health_status_cfg; 6222 6223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6224 6225 cmd->event_source = event_source; 6226 6227 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6228 } 6229 6230 /** 6231 * ice_aq_set_lldp_mib - Set the LLDP MIB 6232 * @hw: pointer to the HW struct 6233 * @mib_type: Local, Remote or both Local and Remote MIBs 6234 * @buf: pointer to the caller-supplied buffer to store the MIB block 6235 * @buf_size: size of the buffer (in bytes) 6236 * @cd: pointer to command details structure or NULL 6237 * 6238 * Set the LLDP MIB. (0x0A08) 6239 */ 6240 int 6241 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6242 struct ice_sq_cd *cd) 6243 { 6244 struct ice_aqc_lldp_set_local_mib *cmd; 6245 struct ice_aq_desc desc; 6246 6247 cmd = &desc.params.lldp_set_mib; 6248 6249 if (buf_size == 0 || !buf) 6250 return -EINVAL; 6251 6252 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6253 6254 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 6255 desc.datalen = cpu_to_le16(buf_size); 6256 6257 cmd->type = mib_type; 6258 cmd->length = cpu_to_le16(buf_size); 6259 6260 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6261 } 6262 6263 /** 6264 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6265 * @hw: pointer to HW struct 6266 */ 6267 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6268 { 6269 if (hw->mac_type != ICE_MAC_E810) 6270 return false; 6271 6272 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6273 ICE_FW_API_LLDP_FLTR_MIN, 6274 ICE_FW_API_LLDP_FLTR_PATCH); 6275 } 6276 6277 /** 6278 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6279 * @hw: pointer to HW struct 6280 * @vsi: VSI to add the filter to 6281 * @add: boolean for if adding or removing a filter 6282 * 6283 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6284 * with this HW or VSI, otherwise an error corresponding to 6285 * the AQ transaction result. 6286 */ 6287 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6288 { 6289 struct ice_aqc_lldp_filter_ctrl *cmd; 6290 struct ice_aq_desc desc; 6291 6292 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6293 return -EOPNOTSUPP; 6294 6295 cmd = &desc.params.lldp_filter_ctrl; 6296 6297 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6298 6299 if (add) 6300 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6301 else 6302 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6303 6304 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6305 6306 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6307 } 6308 6309 /** 6310 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6311 * @hw: pointer to HW struct 6312 */ 6313 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6314 { 6315 struct ice_aq_desc desc; 6316 6317 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6318 6319 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6320 } 6321 6322 /** 6323 * ice_fw_supports_report_dflt_cfg 6324 * @hw: pointer to the hardware structure 6325 * 6326 * Checks if the firmware supports report default configuration 6327 */ 6328 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6329 { 6330 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6331 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6332 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6333 } 6334 6335 /* each of the indexes into the following array match the speed of a return 6336 * value from the list of AQ returned speeds like the range: 6337 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6338 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6339 * array. The array is defined as 15 elements long because the link_speed 6340 * returned by the firmware is a 16 bit * value, but is indexed 6341 * by [fls(speed) - 1] 6342 */ 6343 static const u32 ice_aq_to_link_speed[] = { 6344 SPEED_10, /* BIT(0) */ 6345 SPEED_100, 6346 SPEED_1000, 6347 SPEED_2500, 6348 SPEED_5000, 6349 SPEED_10000, 6350 SPEED_20000, 6351 SPEED_25000, 6352 SPEED_40000, 6353 SPEED_50000, 6354 SPEED_100000, /* BIT(10) */ 6355 SPEED_200000, 6356 }; 6357 6358 /** 6359 * ice_get_link_speed - get integer speed from table 6360 * @index: array index from fls(aq speed) - 1 6361 * 6362 * Returns: u32 value containing integer speed 6363 */ 6364 u32 ice_get_link_speed(u16 index) 6365 { 6366 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6367 return 0; 6368 6369 return ice_aq_to_link_speed[index]; 6370 } 6371 6372 /** 6373 * ice_read_cgu_reg - Read a CGU register 6374 * @hw: Pointer to the HW struct 6375 * @addr: Register address to read 6376 * @val: Storage for register value read 6377 * 6378 * Read the contents of a register of the Clock Generation Unit. Only 6379 * applicable to E82X devices. 6380 * 6381 * Return: 0 on success, other error codes when failed to read from CGU. 6382 */ 6383 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6384 { 6385 struct ice_sbq_msg_input cgu_msg = { 6386 .opcode = ice_sbq_msg_rd, 6387 .dest_dev = ice_sbq_dev_cgu, 6388 .msg_addr_low = addr 6389 }; 6390 int err; 6391 6392 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6393 if (err) { 6394 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6395 addr, err); 6396 return err; 6397 } 6398 6399 *val = cgu_msg.data; 6400 6401 return 0; 6402 } 6403 6404 /** 6405 * ice_write_cgu_reg - Write a CGU register 6406 * @hw: Pointer to the HW struct 6407 * @addr: Register address to write 6408 * @val: Value to write into the register 6409 * 6410 * Write the specified value to a register of the Clock Generation Unit. Only 6411 * applicable to E82X devices. 6412 * 6413 * Return: 0 on success, other error codes when failed to write to CGU. 6414 */ 6415 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6416 { 6417 struct ice_sbq_msg_input cgu_msg = { 6418 .opcode = ice_sbq_msg_wr, 6419 .dest_dev = ice_sbq_dev_cgu, 6420 .msg_addr_low = addr, 6421 .data = val 6422 }; 6423 int err; 6424 6425 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6426 if (err) 6427 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6428 addr, err); 6429 6430 return err; 6431 } 6432