1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 10 #define ICE_PF_RESET_WAIT_COUNT 300 11 #define ICE_MAX_NETLIST_SIZE 10 12 13 static const char * const ice_link_mode_str_low[] = { 14 [0] = "100BASE_TX", 15 [1] = "100M_SGMII", 16 [2] = "1000BASE_T", 17 [3] = "1000BASE_SX", 18 [4] = "1000BASE_LX", 19 [5] = "1000BASE_KX", 20 [6] = "1G_SGMII", 21 [7] = "2500BASE_T", 22 [8] = "2500BASE_X", 23 [9] = "2500BASE_KX", 24 [10] = "5GBASE_T", 25 [11] = "5GBASE_KR", 26 [12] = "10GBASE_T", 27 [13] = "10G_SFI_DA", 28 [14] = "10GBASE_SR", 29 [15] = "10GBASE_LR", 30 [16] = "10GBASE_KR_CR1", 31 [17] = "10G_SFI_AOC_ACC", 32 [18] = "10G_SFI_C2C", 33 [19] = "25GBASE_T", 34 [20] = "25GBASE_CR", 35 [21] = "25GBASE_CR_S", 36 [22] = "25GBASE_CR1", 37 [23] = "25GBASE_SR", 38 [24] = "25GBASE_LR", 39 [25] = "25GBASE_KR", 40 [26] = "25GBASE_KR_S", 41 [27] = "25GBASE_KR1", 42 [28] = "25G_AUI_AOC_ACC", 43 [29] = "25G_AUI_C2C", 44 [30] = "40GBASE_CR4", 45 [31] = "40GBASE_SR4", 46 [32] = "40GBASE_LR4", 47 [33] = "40GBASE_KR4", 48 [34] = "40G_XLAUI_AOC_ACC", 49 [35] = "40G_XLAUI", 50 [36] = "50GBASE_CR2", 51 [37] = "50GBASE_SR2", 52 [38] = "50GBASE_LR2", 53 [39] = "50GBASE_KR2", 54 [40] = "50G_LAUI2_AOC_ACC", 55 [41] = "50G_LAUI2", 56 [42] = "50G_AUI2_AOC_ACC", 57 [43] = "50G_AUI2", 58 [44] = "50GBASE_CP", 59 [45] = "50GBASE_SR", 60 [46] = "50GBASE_FR", 61 [47] = "50GBASE_LR", 62 [48] = "50GBASE_KR_PAM4", 63 [49] = "50G_AUI1_AOC_ACC", 64 [50] = "50G_AUI1", 65 [51] = "100GBASE_CR4", 66 [52] = "100GBASE_SR4", 67 [53] = "100GBASE_LR4", 68 [54] = "100GBASE_KR4", 69 [55] = "100G_CAUI4_AOC_ACC", 70 [56] = "100G_CAUI4", 71 [57] = "100G_AUI4_AOC_ACC", 72 [58] = "100G_AUI4", 73 [59] = "100GBASE_CR_PAM4", 74 [60] = "100GBASE_KR_PAM4", 75 [61] = "100GBASE_CP2", 76 [62] = "100GBASE_SR2", 77 [63] = "100GBASE_DR", 78 }; 79 80 static const char * const ice_link_mode_str_high[] = { 81 [0] = "100GBASE_KR2_PAM4", 82 [1] = "100G_CAUI2_AOC_ACC", 83 [2] = "100G_CAUI2", 84 [3] = "100G_AUI2_AOC_ACC", 85 [4] = "100G_AUI2", 86 }; 87 88 /** 89 * ice_dump_phy_type - helper function to dump phy_type 90 * @hw: pointer to the HW structure 91 * @low: 64 bit value for phy_type_low 92 * @high: 64 bit value for phy_type_high 93 * @prefix: prefix string to differentiate multiple dumps 94 */ 95 static void 96 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 97 { 98 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 99 100 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 101 if (low & BIT_ULL(i)) 102 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 103 prefix, i, ice_link_mode_str_low[i]); 104 } 105 106 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 107 108 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 109 if (high & BIT_ULL(i)) 110 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 111 prefix, i, ice_link_mode_str_high[i]); 112 } 113 } 114 115 /** 116 * ice_set_mac_type - Sets MAC type 117 * @hw: pointer to the HW structure 118 * 119 * This function sets the MAC type of the adapter based on the 120 * vendor ID and device ID stored in the HW structure. 121 */ 122 static int ice_set_mac_type(struct ice_hw *hw) 123 { 124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 125 return -ENODEV; 126 127 switch (hw->device_id) { 128 case ICE_DEV_ID_E810C_BACKPLANE: 129 case ICE_DEV_ID_E810C_QSFP: 130 case ICE_DEV_ID_E810C_SFP: 131 case ICE_DEV_ID_E810_XXV_BACKPLANE: 132 case ICE_DEV_ID_E810_XXV_QSFP: 133 case ICE_DEV_ID_E810_XXV_SFP: 134 hw->mac_type = ICE_MAC_E810; 135 break; 136 case ICE_DEV_ID_E823C_10G_BASE_T: 137 case ICE_DEV_ID_E823C_BACKPLANE: 138 case ICE_DEV_ID_E823C_QSFP: 139 case ICE_DEV_ID_E823C_SFP: 140 case ICE_DEV_ID_E823C_SGMII: 141 case ICE_DEV_ID_E822C_10G_BASE_T: 142 case ICE_DEV_ID_E822C_BACKPLANE: 143 case ICE_DEV_ID_E822C_QSFP: 144 case ICE_DEV_ID_E822C_SFP: 145 case ICE_DEV_ID_E822C_SGMII: 146 case ICE_DEV_ID_E822L_10G_BASE_T: 147 case ICE_DEV_ID_E822L_BACKPLANE: 148 case ICE_DEV_ID_E822L_SFP: 149 case ICE_DEV_ID_E822L_SGMII: 150 case ICE_DEV_ID_E823L_10G_BASE_T: 151 case ICE_DEV_ID_E823L_1GBE: 152 case ICE_DEV_ID_E823L_BACKPLANE: 153 case ICE_DEV_ID_E823L_QSFP: 154 case ICE_DEV_ID_E823L_SFP: 155 hw->mac_type = ICE_MAC_GENERIC; 156 break; 157 case ICE_DEV_ID_E825C_BACKPLANE: 158 case ICE_DEV_ID_E825C_QSFP: 159 case ICE_DEV_ID_E825C_SFP: 160 case ICE_DEV_ID_E825C_SGMII: 161 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 162 break; 163 case ICE_DEV_ID_E830CC_BACKPLANE: 164 case ICE_DEV_ID_E830CC_QSFP56: 165 case ICE_DEV_ID_E830CC_SFP: 166 case ICE_DEV_ID_E830CC_SFP_DD: 167 case ICE_DEV_ID_E830C_BACKPLANE: 168 case ICE_DEV_ID_E830_XXV_BACKPLANE: 169 case ICE_DEV_ID_E830C_QSFP: 170 case ICE_DEV_ID_E830_XXV_QSFP: 171 case ICE_DEV_ID_E830C_SFP: 172 case ICE_DEV_ID_E830_XXV_SFP: 173 hw->mac_type = ICE_MAC_E830; 174 break; 175 default: 176 hw->mac_type = ICE_MAC_UNKNOWN; 177 break; 178 } 179 180 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 181 return 0; 182 } 183 184 /** 185 * ice_is_generic_mac - check if device's mac_type is generic 186 * @hw: pointer to the hardware structure 187 * 188 * Return: true if mac_type is generic (with SBQ support), false if not 189 */ 190 bool ice_is_generic_mac(struct ice_hw *hw) 191 { 192 return (hw->mac_type == ICE_MAC_GENERIC || 193 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 194 } 195 196 /** 197 * ice_is_e810 198 * @hw: pointer to the hardware structure 199 * 200 * returns true if the device is E810 based, false if not. 201 */ 202 bool ice_is_e810(struct ice_hw *hw) 203 { 204 return hw->mac_type == ICE_MAC_E810; 205 } 206 207 /** 208 * ice_is_e810t 209 * @hw: pointer to the hardware structure 210 * 211 * returns true if the device is E810T based, false if not. 212 */ 213 bool ice_is_e810t(struct ice_hw *hw) 214 { 215 switch (hw->device_id) { 216 case ICE_DEV_ID_E810C_SFP: 217 switch (hw->subsystem_device_id) { 218 case ICE_SUBDEV_ID_E810T: 219 case ICE_SUBDEV_ID_E810T2: 220 case ICE_SUBDEV_ID_E810T3: 221 case ICE_SUBDEV_ID_E810T4: 222 case ICE_SUBDEV_ID_E810T6: 223 case ICE_SUBDEV_ID_E810T7: 224 return true; 225 } 226 break; 227 case ICE_DEV_ID_E810C_QSFP: 228 switch (hw->subsystem_device_id) { 229 case ICE_SUBDEV_ID_E810T2: 230 case ICE_SUBDEV_ID_E810T3: 231 case ICE_SUBDEV_ID_E810T5: 232 return true; 233 } 234 break; 235 default: 236 break; 237 } 238 239 return false; 240 } 241 242 /** 243 * ice_is_e822 - Check if a device is E822 family device 244 * @hw: pointer to the hardware structure 245 * 246 * Return: true if the device is E822 based, false if not. 247 */ 248 bool ice_is_e822(struct ice_hw *hw) 249 { 250 switch (hw->device_id) { 251 case ICE_DEV_ID_E822C_BACKPLANE: 252 case ICE_DEV_ID_E822C_QSFP: 253 case ICE_DEV_ID_E822C_SFP: 254 case ICE_DEV_ID_E822C_10G_BASE_T: 255 case ICE_DEV_ID_E822C_SGMII: 256 case ICE_DEV_ID_E822L_BACKPLANE: 257 case ICE_DEV_ID_E822L_SFP: 258 case ICE_DEV_ID_E822L_10G_BASE_T: 259 case ICE_DEV_ID_E822L_SGMII: 260 return true; 261 default: 262 return false; 263 } 264 } 265 266 /** 267 * ice_is_e823 268 * @hw: pointer to the hardware structure 269 * 270 * returns true if the device is E823-L or E823-C based, false if not. 271 */ 272 bool ice_is_e823(struct ice_hw *hw) 273 { 274 switch (hw->device_id) { 275 case ICE_DEV_ID_E823L_BACKPLANE: 276 case ICE_DEV_ID_E823L_SFP: 277 case ICE_DEV_ID_E823L_10G_BASE_T: 278 case ICE_DEV_ID_E823L_1GBE: 279 case ICE_DEV_ID_E823L_QSFP: 280 case ICE_DEV_ID_E823C_BACKPLANE: 281 case ICE_DEV_ID_E823C_QSFP: 282 case ICE_DEV_ID_E823C_SFP: 283 case ICE_DEV_ID_E823C_10G_BASE_T: 284 case ICE_DEV_ID_E823C_SGMII: 285 return true; 286 default: 287 return false; 288 } 289 } 290 291 /** 292 * ice_is_e825c - Check if a device is E825C family device 293 * @hw: pointer to the hardware structure 294 * 295 * Return: true if the device is E825-C based, false if not. 296 */ 297 bool ice_is_e825c(struct ice_hw *hw) 298 { 299 switch (hw->device_id) { 300 case ICE_DEV_ID_E825C_BACKPLANE: 301 case ICE_DEV_ID_E825C_QSFP: 302 case ICE_DEV_ID_E825C_SFP: 303 case ICE_DEV_ID_E825C_SGMII: 304 return true; 305 default: 306 return false; 307 } 308 } 309 310 /** 311 * ice_clear_pf_cfg - Clear PF configuration 312 * @hw: pointer to the hardware structure 313 * 314 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 315 * configuration, flow director filters, etc.). 316 */ 317 int ice_clear_pf_cfg(struct ice_hw *hw) 318 { 319 struct ice_aq_desc desc; 320 321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 322 323 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 324 } 325 326 /** 327 * ice_aq_manage_mac_read - manage MAC address read command 328 * @hw: pointer to the HW struct 329 * @buf: a virtual buffer to hold the manage MAC read response 330 * @buf_size: Size of the virtual buffer 331 * @cd: pointer to command details structure or NULL 332 * 333 * This function is used to return per PF station MAC address (0x0107). 334 * NOTE: Upon successful completion of this command, MAC address information 335 * is returned in user specified buffer. Please interpret user specified 336 * buffer as "manage_mac_read" response. 337 * Response such as various MAC addresses are stored in HW struct (port.mac) 338 * ice_discover_dev_caps is expected to be called before this function is 339 * called. 340 */ 341 static int 342 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 343 struct ice_sq_cd *cd) 344 { 345 struct ice_aqc_manage_mac_read_resp *resp; 346 struct ice_aqc_manage_mac_read *cmd; 347 struct ice_aq_desc desc; 348 int status; 349 u16 flags; 350 u8 i; 351 352 cmd = &desc.params.mac_read; 353 354 if (buf_size < sizeof(*resp)) 355 return -EINVAL; 356 357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 358 359 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 360 if (status) 361 return status; 362 363 resp = buf; 364 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 365 366 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 367 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 368 return -EIO; 369 } 370 371 /* A single port can report up to two (LAN and WoL) addresses */ 372 for (i = 0; i < cmd->num_addr; i++) 373 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 374 ether_addr_copy(hw->port_info->mac.lan_addr, 375 resp[i].mac_addr); 376 ether_addr_copy(hw->port_info->mac.perm_addr, 377 resp[i].mac_addr); 378 break; 379 } 380 381 return 0; 382 } 383 384 /** 385 * ice_aq_get_phy_caps - returns PHY capabilities 386 * @pi: port information structure 387 * @qual_mods: report qualified modules 388 * @report_mode: report mode capabilities 389 * @pcaps: structure for PHY capabilities to be filled 390 * @cd: pointer to command details structure or NULL 391 * 392 * Returns the various PHY capabilities supported on the Port (0x0600) 393 */ 394 int 395 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 396 struct ice_aqc_get_phy_caps_data *pcaps, 397 struct ice_sq_cd *cd) 398 { 399 struct ice_aqc_get_phy_caps *cmd; 400 u16 pcaps_size = sizeof(*pcaps); 401 struct ice_aq_desc desc; 402 const char *prefix; 403 struct ice_hw *hw; 404 int status; 405 406 cmd = &desc.params.get_phy; 407 408 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 409 return -EINVAL; 410 hw = pi->hw; 411 412 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 413 !ice_fw_supports_report_dflt_cfg(hw)) 414 return -EINVAL; 415 416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 417 418 if (qual_mods) 419 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 420 421 cmd->param0 |= cpu_to_le16(report_mode); 422 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 423 424 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 425 426 switch (report_mode) { 427 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 428 prefix = "phy_caps_media"; 429 break; 430 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 431 prefix = "phy_caps_no_media"; 432 break; 433 case ICE_AQC_REPORT_ACTIVE_CFG: 434 prefix = "phy_caps_active"; 435 break; 436 case ICE_AQC_REPORT_DFLT_CFG: 437 prefix = "phy_caps_default"; 438 break; 439 default: 440 prefix = "phy_caps_invalid"; 441 } 442 443 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 444 le64_to_cpu(pcaps->phy_type_high), prefix); 445 446 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 447 prefix, report_mode); 448 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 449 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 450 pcaps->low_power_ctrl_an); 451 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 452 pcaps->eee_cap); 453 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 454 pcaps->eeer_value); 455 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 456 pcaps->link_fec_options); 457 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 458 prefix, pcaps->module_compliance_enforcement); 459 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 460 prefix, pcaps->extended_compliance_code); 461 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 462 pcaps->module_type[0]); 463 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 464 pcaps->module_type[1]); 465 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 466 pcaps->module_type[2]); 467 468 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 469 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 470 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 471 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 472 sizeof(pi->phy.link_info.module_type)); 473 } 474 475 return status; 476 } 477 478 /** 479 * ice_aq_get_link_topo_handle - get link topology node return status 480 * @pi: port information structure 481 * @node_type: requested node type 482 * @cd: pointer to command details structure or NULL 483 * 484 * Get link topology node return status for specified node type (0x06E0) 485 * 486 * Node type cage can be used to determine if cage is present. If AQC 487 * returns error (ENOENT), then no cage present. If no cage present, then 488 * connection type is backplane or BASE-T. 489 */ 490 static int 491 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 492 struct ice_sq_cd *cd) 493 { 494 struct ice_aqc_get_link_topo *cmd; 495 struct ice_aq_desc desc; 496 497 cmd = &desc.params.get_link_topo; 498 499 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 500 501 cmd->addr.topo_params.node_type_ctx = 502 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 503 ICE_AQC_LINK_TOPO_NODE_CTX_S); 504 505 /* set node type */ 506 cmd->addr.topo_params.node_type_ctx |= 507 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 508 509 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 510 } 511 512 /** 513 * ice_aq_get_netlist_node 514 * @hw: pointer to the hw struct 515 * @cmd: get_link_topo AQ structure 516 * @node_part_number: output node part number if node found 517 * @node_handle: output node handle parameter if node found 518 * 519 * Get netlist node handle. 520 */ 521 int 522 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 523 u8 *node_part_number, u16 *node_handle) 524 { 525 struct ice_aq_desc desc; 526 527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 528 desc.params.get_link_topo = *cmd; 529 530 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 531 return -EINTR; 532 533 if (node_handle) 534 *node_handle = 535 le16_to_cpu(desc.params.get_link_topo.addr.handle); 536 if (node_part_number) 537 *node_part_number = desc.params.get_link_topo.node_part_num; 538 539 return 0; 540 } 541 542 /** 543 * ice_find_netlist_node 544 * @hw: pointer to the hw struct 545 * @node_type_ctx: type of netlist node to look for 546 * @node_part_number: node part number to look for 547 * @node_handle: output parameter if node found - optional 548 * 549 * Scan the netlist for a node handle of the given node type and part number. 550 * 551 * If node_handle is non-NULL it will be modified on function exit. It is only 552 * valid if the function returns zero, and should be ignored on any non-zero 553 * return value. 554 * 555 * Returns: 0 if the node is found, -ENOENT if no handle was found, and 556 * a negative error code on failure to access the AQ. 557 */ 558 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, 559 u8 node_part_number, u16 *node_handle) 560 { 561 u8 idx; 562 563 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 564 struct ice_aqc_get_link_topo cmd = {}; 565 u8 rec_node_part_number; 566 int status; 567 568 cmd.addr.topo_params.node_type_ctx = 569 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, 570 node_type_ctx); 571 cmd.addr.topo_params.index = idx; 572 573 status = ice_aq_get_netlist_node(hw, &cmd, 574 &rec_node_part_number, 575 node_handle); 576 if (status) 577 return status; 578 579 if (rec_node_part_number == node_part_number) 580 return 0; 581 } 582 583 return -ENOENT; 584 } 585 586 /** 587 * ice_is_media_cage_present 588 * @pi: port information structure 589 * 590 * Returns true if media cage is present, else false. If no cage, then 591 * media type is backplane or BASE-T. 592 */ 593 static bool ice_is_media_cage_present(struct ice_port_info *pi) 594 { 595 /* Node type cage can be used to determine if cage is present. If AQC 596 * returns error (ENOENT), then no cage present. If no cage present then 597 * connection type is backplane or BASE-T. 598 */ 599 return !ice_aq_get_link_topo_handle(pi, 600 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 601 NULL); 602 } 603 604 /** 605 * ice_get_media_type - Gets media type 606 * @pi: port information structure 607 */ 608 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 609 { 610 struct ice_link_status *hw_link_info; 611 612 if (!pi) 613 return ICE_MEDIA_UNKNOWN; 614 615 hw_link_info = &pi->phy.link_info; 616 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 617 /* If more than one media type is selected, report unknown */ 618 return ICE_MEDIA_UNKNOWN; 619 620 if (hw_link_info->phy_type_low) { 621 /* 1G SGMII is a special case where some DA cable PHYs 622 * may show this as an option when it really shouldn't 623 * be since SGMII is meant to be between a MAC and a PHY 624 * in a backplane. Try to detect this case and handle it 625 */ 626 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 627 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 628 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 629 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 630 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 631 return ICE_MEDIA_DA; 632 633 switch (hw_link_info->phy_type_low) { 634 case ICE_PHY_TYPE_LOW_1000BASE_SX: 635 case ICE_PHY_TYPE_LOW_1000BASE_LX: 636 case ICE_PHY_TYPE_LOW_10GBASE_SR: 637 case ICE_PHY_TYPE_LOW_10GBASE_LR: 638 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 639 case ICE_PHY_TYPE_LOW_25GBASE_SR: 640 case ICE_PHY_TYPE_LOW_25GBASE_LR: 641 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 642 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 643 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 644 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 645 case ICE_PHY_TYPE_LOW_50GBASE_SR: 646 case ICE_PHY_TYPE_LOW_50GBASE_FR: 647 case ICE_PHY_TYPE_LOW_50GBASE_LR: 648 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 649 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 650 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 651 case ICE_PHY_TYPE_LOW_100GBASE_DR: 652 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 653 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 654 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 655 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 656 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 657 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 658 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 659 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 660 return ICE_MEDIA_FIBER; 661 case ICE_PHY_TYPE_LOW_100BASE_TX: 662 case ICE_PHY_TYPE_LOW_1000BASE_T: 663 case ICE_PHY_TYPE_LOW_2500BASE_T: 664 case ICE_PHY_TYPE_LOW_5GBASE_T: 665 case ICE_PHY_TYPE_LOW_10GBASE_T: 666 case ICE_PHY_TYPE_LOW_25GBASE_T: 667 return ICE_MEDIA_BASET; 668 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 669 case ICE_PHY_TYPE_LOW_25GBASE_CR: 670 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 671 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 672 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 673 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 674 case ICE_PHY_TYPE_LOW_50GBASE_CP: 675 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 676 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 677 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 678 return ICE_MEDIA_DA; 679 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 680 case ICE_PHY_TYPE_LOW_40G_XLAUI: 681 case ICE_PHY_TYPE_LOW_50G_LAUI2: 682 case ICE_PHY_TYPE_LOW_50G_AUI2: 683 case ICE_PHY_TYPE_LOW_50G_AUI1: 684 case ICE_PHY_TYPE_LOW_100G_AUI4: 685 case ICE_PHY_TYPE_LOW_100G_CAUI4: 686 if (ice_is_media_cage_present(pi)) 687 return ICE_MEDIA_DA; 688 fallthrough; 689 case ICE_PHY_TYPE_LOW_1000BASE_KX: 690 case ICE_PHY_TYPE_LOW_2500BASE_KX: 691 case ICE_PHY_TYPE_LOW_2500BASE_X: 692 case ICE_PHY_TYPE_LOW_5GBASE_KR: 693 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 694 case ICE_PHY_TYPE_LOW_25GBASE_KR: 695 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 696 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 697 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 698 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 699 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 700 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 701 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 702 return ICE_MEDIA_BACKPLANE; 703 } 704 } else { 705 switch (hw_link_info->phy_type_high) { 706 case ICE_PHY_TYPE_HIGH_100G_AUI2: 707 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 708 if (ice_is_media_cage_present(pi)) 709 return ICE_MEDIA_DA; 710 fallthrough; 711 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 712 return ICE_MEDIA_BACKPLANE; 713 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 714 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 715 return ICE_MEDIA_FIBER; 716 } 717 } 718 return ICE_MEDIA_UNKNOWN; 719 } 720 721 /** 722 * ice_get_link_status_datalen 723 * @hw: pointer to the HW struct 724 * 725 * Returns datalength for the Get Link Status AQ command, which is bigger for 726 * newer adapter families handled by ice driver. 727 */ 728 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 729 { 730 switch (hw->mac_type) { 731 case ICE_MAC_E830: 732 return ICE_AQC_LS_DATA_SIZE_V2; 733 case ICE_MAC_E810: 734 default: 735 return ICE_AQC_LS_DATA_SIZE_V1; 736 } 737 } 738 739 /** 740 * ice_aq_get_link_info 741 * @pi: port information structure 742 * @ena_lse: enable/disable LinkStatusEvent reporting 743 * @link: pointer to link status structure - optional 744 * @cd: pointer to command details structure or NULL 745 * 746 * Get Link Status (0x607). Returns the link status of the adapter. 747 */ 748 int 749 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 750 struct ice_link_status *link, struct ice_sq_cd *cd) 751 { 752 struct ice_aqc_get_link_status_data link_data = { 0 }; 753 struct ice_aqc_get_link_status *resp; 754 struct ice_link_status *li_old, *li; 755 enum ice_media_type *hw_media_type; 756 struct ice_fc_info *hw_fc_info; 757 bool tx_pause, rx_pause; 758 struct ice_aq_desc desc; 759 struct ice_hw *hw; 760 u16 cmd_flags; 761 int status; 762 763 if (!pi) 764 return -EINVAL; 765 hw = pi->hw; 766 li_old = &pi->phy.link_info_old; 767 hw_media_type = &pi->phy.media_type; 768 li = &pi->phy.link_info; 769 hw_fc_info = &pi->fc; 770 771 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 772 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 773 resp = &desc.params.get_link_status; 774 resp->cmd_flags = cpu_to_le16(cmd_flags); 775 resp->lport_num = pi->lport; 776 777 status = ice_aq_send_cmd(hw, &desc, &link_data, 778 ice_get_link_status_datalen(hw), cd); 779 if (status) 780 return status; 781 782 /* save off old link status information */ 783 *li_old = *li; 784 785 /* update current link status information */ 786 li->link_speed = le16_to_cpu(link_data.link_speed); 787 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 788 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 789 *hw_media_type = ice_get_media_type(pi); 790 li->link_info = link_data.link_info; 791 li->link_cfg_err = link_data.link_cfg_err; 792 li->an_info = link_data.an_info; 793 li->ext_info = link_data.ext_info; 794 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 795 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 796 li->topo_media_conflict = link_data.topo_media_conflict; 797 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 798 ICE_AQ_CFG_PACING_TYPE_M); 799 800 /* update fc info */ 801 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 802 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 803 if (tx_pause && rx_pause) 804 hw_fc_info->current_mode = ICE_FC_FULL; 805 else if (tx_pause) 806 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 807 else if (rx_pause) 808 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 809 else 810 hw_fc_info->current_mode = ICE_FC_NONE; 811 812 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 813 814 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 815 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 816 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 817 (unsigned long long)li->phy_type_low); 818 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 819 (unsigned long long)li->phy_type_high); 820 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 821 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 822 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 823 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 824 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 825 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 826 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 827 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 828 li->max_frame_size); 829 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 830 831 /* save link status information */ 832 if (link) 833 *link = *li; 834 835 /* flag cleared so calling functions don't call AQ again */ 836 pi->phy.get_link_info = false; 837 838 return 0; 839 } 840 841 /** 842 * ice_fill_tx_timer_and_fc_thresh 843 * @hw: pointer to the HW struct 844 * @cmd: pointer to MAC cfg structure 845 * 846 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 847 * descriptor 848 */ 849 static void 850 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 851 struct ice_aqc_set_mac_cfg *cmd) 852 { 853 u32 val, fc_thres_m; 854 855 /* We read back the transmit timer and FC threshold value of 856 * LFC. Thus, we will use index = 857 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 858 * 859 * Also, because we are operating on transmit timer and FC 860 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 861 */ 862 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 863 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 864 865 if (hw->mac_type == ICE_MAC_E830) { 866 /* Retrieve the transmit timer */ 867 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 868 cmd->tx_tmr_value = 869 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 870 871 /* Retrieve the fc threshold */ 872 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 873 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 874 } else { 875 /* Retrieve the transmit timer */ 876 val = rd32(hw, 877 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 878 cmd->tx_tmr_value = 879 le16_encode_bits(val, 880 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 881 882 /* Retrieve the fc threshold */ 883 val = rd32(hw, 884 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 885 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 886 } 887 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 888 } 889 890 /** 891 * ice_aq_set_mac_cfg 892 * @hw: pointer to the HW struct 893 * @max_frame_size: Maximum Frame Size to be supported 894 * @cd: pointer to command details structure or NULL 895 * 896 * Set MAC configuration (0x0603) 897 */ 898 int 899 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 900 { 901 struct ice_aqc_set_mac_cfg *cmd; 902 struct ice_aq_desc desc; 903 904 cmd = &desc.params.set_mac_cfg; 905 906 if (max_frame_size == 0) 907 return -EINVAL; 908 909 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 910 911 cmd->max_frame_size = cpu_to_le16(max_frame_size); 912 913 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 914 915 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 916 } 917 918 /** 919 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 920 * @hw: pointer to the HW struct 921 */ 922 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 923 { 924 struct ice_switch_info *sw; 925 int status; 926 927 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 928 sizeof(*hw->switch_info), GFP_KERNEL); 929 sw = hw->switch_info; 930 931 if (!sw) 932 return -ENOMEM; 933 934 INIT_LIST_HEAD(&sw->vsi_list_map_head); 935 sw->prof_res_bm_init = 0; 936 937 status = ice_init_def_sw_recp(hw); 938 if (status) { 939 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 940 return status; 941 } 942 return 0; 943 } 944 945 /** 946 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 947 * @hw: pointer to the HW struct 948 */ 949 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 950 { 951 struct ice_switch_info *sw = hw->switch_info; 952 struct ice_vsi_list_map_info *v_pos_map; 953 struct ice_vsi_list_map_info *v_tmp_map; 954 struct ice_sw_recipe *recps; 955 u8 i; 956 957 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 958 list_entry) { 959 list_del(&v_pos_map->list_entry); 960 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 961 } 962 recps = sw->recp_list; 963 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 964 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 965 966 recps[i].root_rid = i; 967 list_for_each_entry_safe(rg_entry, tmprg_entry, 968 &recps[i].rg_list, l_entry) { 969 list_del(&rg_entry->l_entry); 970 devm_kfree(ice_hw_to_dev(hw), rg_entry); 971 } 972 973 if (recps[i].adv_rule) { 974 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 975 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 976 977 mutex_destroy(&recps[i].filt_rule_lock); 978 list_for_each_entry_safe(lst_itr, tmp_entry, 979 &recps[i].filt_rules, 980 list_entry) { 981 list_del(&lst_itr->list_entry); 982 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 983 devm_kfree(ice_hw_to_dev(hw), lst_itr); 984 } 985 } else { 986 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 987 988 mutex_destroy(&recps[i].filt_rule_lock); 989 list_for_each_entry_safe(lst_itr, tmp_entry, 990 &recps[i].filt_rules, 991 list_entry) { 992 list_del(&lst_itr->list_entry); 993 devm_kfree(ice_hw_to_dev(hw), lst_itr); 994 } 995 } 996 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 997 } 998 ice_rm_all_sw_replay_rule_info(hw); 999 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 1000 devm_kfree(ice_hw_to_dev(hw), sw); 1001 } 1002 1003 /** 1004 * ice_get_itr_intrl_gran 1005 * @hw: pointer to the HW struct 1006 * 1007 * Determines the ITR/INTRL granularities based on the maximum aggregate 1008 * bandwidth according to the device's configuration during power-on. 1009 */ 1010 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1011 { 1012 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 1013 rd32(hw, GL_PWR_MODE_CTL)); 1014 1015 switch (max_agg_bw) { 1016 case ICE_MAX_AGG_BW_200G: 1017 case ICE_MAX_AGG_BW_100G: 1018 case ICE_MAX_AGG_BW_50G: 1019 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1020 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1021 break; 1022 case ICE_MAX_AGG_BW_25G: 1023 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1024 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1025 break; 1026 } 1027 } 1028 1029 /** 1030 * ice_init_hw - main hardware initialization routine 1031 * @hw: pointer to the hardware structure 1032 */ 1033 int ice_init_hw(struct ice_hw *hw) 1034 { 1035 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1036 void *mac_buf __free(kfree) = NULL; 1037 u16 mac_buf_len; 1038 int status; 1039 1040 /* Set MAC type based on DeviceID */ 1041 status = ice_set_mac_type(hw); 1042 if (status) 1043 return status; 1044 1045 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1046 1047 status = ice_reset(hw, ICE_RESET_PFR); 1048 if (status) 1049 return status; 1050 1051 ice_get_itr_intrl_gran(hw); 1052 1053 status = ice_create_all_ctrlq(hw); 1054 if (status) 1055 goto err_unroll_cqinit; 1056 1057 status = ice_fwlog_init(hw); 1058 if (status) 1059 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1060 status); 1061 1062 status = ice_clear_pf_cfg(hw); 1063 if (status) 1064 goto err_unroll_cqinit; 1065 1066 /* Set bit to enable Flow Director filters */ 1067 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1068 INIT_LIST_HEAD(&hw->fdir_list_head); 1069 1070 ice_clear_pxe_mode(hw); 1071 1072 status = ice_init_nvm(hw); 1073 if (status) 1074 goto err_unroll_cqinit; 1075 1076 status = ice_get_caps(hw); 1077 if (status) 1078 goto err_unroll_cqinit; 1079 1080 if (!hw->port_info) 1081 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1082 sizeof(*hw->port_info), 1083 GFP_KERNEL); 1084 if (!hw->port_info) { 1085 status = -ENOMEM; 1086 goto err_unroll_cqinit; 1087 } 1088 1089 /* set the back pointer to HW */ 1090 hw->port_info->hw = hw; 1091 1092 /* Initialize port_info struct with switch configuration data */ 1093 status = ice_get_initial_sw_cfg(hw); 1094 if (status) 1095 goto err_unroll_alloc; 1096 1097 hw->evb_veb = true; 1098 1099 /* init xarray for identifying scheduling nodes uniquely */ 1100 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1101 1102 /* Query the allocated resources for Tx scheduler */ 1103 status = ice_sched_query_res_alloc(hw); 1104 if (status) { 1105 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1106 goto err_unroll_alloc; 1107 } 1108 ice_sched_get_psm_clk_freq(hw); 1109 1110 /* Initialize port_info struct with scheduler data */ 1111 status = ice_sched_init_port(hw->port_info); 1112 if (status) 1113 goto err_unroll_sched; 1114 1115 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1116 if (!pcaps) { 1117 status = -ENOMEM; 1118 goto err_unroll_sched; 1119 } 1120 1121 /* Initialize port_info struct with PHY capabilities */ 1122 status = ice_aq_get_phy_caps(hw->port_info, false, 1123 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1124 NULL); 1125 if (status) 1126 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1127 status); 1128 1129 /* Initialize port_info struct with link information */ 1130 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1131 if (status) 1132 goto err_unroll_sched; 1133 1134 /* need a valid SW entry point to build a Tx tree */ 1135 if (!hw->sw_entry_point_layer) { 1136 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1137 status = -EIO; 1138 goto err_unroll_sched; 1139 } 1140 INIT_LIST_HEAD(&hw->agg_list); 1141 /* Initialize max burst size */ 1142 if (!hw->max_burst_size) 1143 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1144 1145 status = ice_init_fltr_mgmt_struct(hw); 1146 if (status) 1147 goto err_unroll_sched; 1148 1149 /* Get MAC information */ 1150 /* A single port can report up to two (LAN and WoL) addresses */ 1151 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1152 GFP_KERNEL); 1153 if (!mac_buf) { 1154 status = -ENOMEM; 1155 goto err_unroll_fltr_mgmt_struct; 1156 } 1157 1158 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1159 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1160 1161 if (status) 1162 goto err_unroll_fltr_mgmt_struct; 1163 /* enable jumbo frame support at MAC level */ 1164 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1165 if (status) 1166 goto err_unroll_fltr_mgmt_struct; 1167 /* Obtain counter base index which would be used by flow director */ 1168 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1169 if (status) 1170 goto err_unroll_fltr_mgmt_struct; 1171 status = ice_init_hw_tbls(hw); 1172 if (status) 1173 goto err_unroll_fltr_mgmt_struct; 1174 mutex_init(&hw->tnl_lock); 1175 ice_init_chk_recipe_reuse_support(hw); 1176 1177 return 0; 1178 1179 err_unroll_fltr_mgmt_struct: 1180 ice_cleanup_fltr_mgmt_struct(hw); 1181 err_unroll_sched: 1182 ice_sched_cleanup_all(hw); 1183 err_unroll_alloc: 1184 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1185 err_unroll_cqinit: 1186 ice_destroy_all_ctrlq(hw); 1187 return status; 1188 } 1189 1190 /** 1191 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1192 * @hw: pointer to the hardware structure 1193 * 1194 * This should be called only during nominal operation, not as a result of 1195 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1196 * applicable initializations if it fails for any reason. 1197 */ 1198 void ice_deinit_hw(struct ice_hw *hw) 1199 { 1200 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1201 ice_cleanup_fltr_mgmt_struct(hw); 1202 1203 ice_sched_cleanup_all(hw); 1204 ice_sched_clear_agg(hw); 1205 ice_free_seg(hw); 1206 ice_free_hw_tbls(hw); 1207 mutex_destroy(&hw->tnl_lock); 1208 1209 ice_fwlog_deinit(hw); 1210 ice_destroy_all_ctrlq(hw); 1211 1212 /* Clear VSI contexts if not already cleared */ 1213 ice_clear_all_vsi_ctx(hw); 1214 } 1215 1216 /** 1217 * ice_check_reset - Check to see if a global reset is complete 1218 * @hw: pointer to the hardware structure 1219 */ 1220 int ice_check_reset(struct ice_hw *hw) 1221 { 1222 u32 cnt, reg = 0, grst_timeout, uld_mask; 1223 1224 /* Poll for Device Active state in case a recent CORER, GLOBR, 1225 * or EMPR has occurred. The grst delay value is in 100ms units. 1226 * Add 1sec for outstanding AQ commands that can take a long time. 1227 */ 1228 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1229 rd32(hw, GLGEN_RSTCTL)) + 10; 1230 1231 for (cnt = 0; cnt < grst_timeout; cnt++) { 1232 mdelay(100); 1233 reg = rd32(hw, GLGEN_RSTAT); 1234 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1235 break; 1236 } 1237 1238 if (cnt == grst_timeout) { 1239 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1240 return -EIO; 1241 } 1242 1243 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1244 GLNVM_ULD_PCIER_DONE_1_M |\ 1245 GLNVM_ULD_CORER_DONE_M |\ 1246 GLNVM_ULD_GLOBR_DONE_M |\ 1247 GLNVM_ULD_POR_DONE_M |\ 1248 GLNVM_ULD_POR_DONE_1_M |\ 1249 GLNVM_ULD_PCIER_DONE_2_M) 1250 1251 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1252 GLNVM_ULD_PE_DONE_M : 0); 1253 1254 /* Device is Active; check Global Reset processes are done */ 1255 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1256 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1257 if (reg == uld_mask) { 1258 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1259 break; 1260 } 1261 mdelay(10); 1262 } 1263 1264 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1265 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1266 reg); 1267 return -EIO; 1268 } 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * ice_pf_reset - Reset the PF 1275 * @hw: pointer to the hardware structure 1276 * 1277 * If a global reset has been triggered, this function checks 1278 * for its completion and then issues the PF reset 1279 */ 1280 static int ice_pf_reset(struct ice_hw *hw) 1281 { 1282 u32 cnt, reg; 1283 1284 /* If at function entry a global reset was already in progress, i.e. 1285 * state is not 'device active' or any of the reset done bits are not 1286 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1287 * global reset is done. 1288 */ 1289 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1290 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1291 /* poll on global reset currently in progress until done */ 1292 if (ice_check_reset(hw)) 1293 return -EIO; 1294 1295 return 0; 1296 } 1297 1298 /* Reset the PF */ 1299 reg = rd32(hw, PFGEN_CTRL); 1300 1301 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1302 1303 /* Wait for the PFR to complete. The wait time is the global config lock 1304 * timeout plus the PFR timeout which will account for a possible reset 1305 * that is occurring during a download package operation. 1306 */ 1307 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1308 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1309 reg = rd32(hw, PFGEN_CTRL); 1310 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1311 break; 1312 1313 mdelay(1); 1314 } 1315 1316 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1317 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1318 return -EIO; 1319 } 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * ice_reset - Perform different types of reset 1326 * @hw: pointer to the hardware structure 1327 * @req: reset request 1328 * 1329 * This function triggers a reset as specified by the req parameter. 1330 * 1331 * Note: 1332 * If anything other than a PF reset is triggered, PXE mode is restored. 1333 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1334 * interface has been restored in the rebuild flow. 1335 */ 1336 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1337 { 1338 u32 val = 0; 1339 1340 switch (req) { 1341 case ICE_RESET_PFR: 1342 return ice_pf_reset(hw); 1343 case ICE_RESET_CORER: 1344 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1345 val = GLGEN_RTRIG_CORER_M; 1346 break; 1347 case ICE_RESET_GLOBR: 1348 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1349 val = GLGEN_RTRIG_GLOBR_M; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 val |= rd32(hw, GLGEN_RTRIG); 1356 wr32(hw, GLGEN_RTRIG, val); 1357 ice_flush(hw); 1358 1359 /* wait for the FW to be ready */ 1360 return ice_check_reset(hw); 1361 } 1362 1363 /** 1364 * ice_copy_rxq_ctx_to_hw 1365 * @hw: pointer to the hardware structure 1366 * @ice_rxq_ctx: pointer to the rxq context 1367 * @rxq_index: the index of the Rx queue 1368 * 1369 * Copies rxq context from dense structure to HW register space 1370 */ 1371 static int 1372 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1373 { 1374 u8 i; 1375 1376 if (!ice_rxq_ctx) 1377 return -EINVAL; 1378 1379 if (rxq_index > QRX_CTRL_MAX_INDEX) 1380 return -EINVAL; 1381 1382 /* Copy each dword separately to HW */ 1383 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1384 wr32(hw, QRX_CONTEXT(i, rxq_index), 1385 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1386 1387 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1388 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1389 } 1390 1391 return 0; 1392 } 1393 1394 /* LAN Rx Queue Context */ 1395 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1396 /* Field Width LSB */ 1397 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1398 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1399 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1400 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1401 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1402 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1403 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1404 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1405 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1406 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1407 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1408 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1409 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1410 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1411 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1412 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1413 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1414 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1415 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1416 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1417 { 0 } 1418 }; 1419 1420 /** 1421 * ice_write_rxq_ctx 1422 * @hw: pointer to the hardware structure 1423 * @rlan_ctx: pointer to the rxq context 1424 * @rxq_index: the index of the Rx queue 1425 * 1426 * Converts rxq context from sparse to dense structure and then writes 1427 * it to HW register space and enables the hardware to prefetch descriptors 1428 * instead of only fetching them on demand 1429 */ 1430 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1431 u32 rxq_index) 1432 { 1433 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1434 1435 if (!rlan_ctx) 1436 return -EINVAL; 1437 1438 rlan_ctx->prefena = 1; 1439 1440 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1441 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1442 } 1443 1444 /* LAN Tx Queue Context */ 1445 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1446 /* Field Width LSB */ 1447 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1448 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1449 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1450 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1451 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1452 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1453 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1454 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1455 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1456 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1457 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1458 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1459 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1460 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1461 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1462 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1463 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1464 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1465 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1466 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1467 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1468 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1469 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1470 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1471 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1472 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1473 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1474 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1475 { 0 } 1476 }; 1477 1478 /* Sideband Queue command wrappers */ 1479 1480 /** 1481 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1482 * @hw: pointer to the HW struct 1483 * @desc: descriptor describing the command 1484 * @buf: buffer to use for indirect commands (NULL for direct commands) 1485 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1486 * @cd: pointer to command details structure 1487 */ 1488 static int 1489 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1490 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1491 { 1492 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1493 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1494 } 1495 1496 /** 1497 * ice_sbq_rw_reg - Fill Sideband Queue command 1498 * @hw: pointer to the HW struct 1499 * @in: message info to be filled in descriptor 1500 */ 1501 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1502 { 1503 struct ice_sbq_cmd_desc desc = {0}; 1504 struct ice_sbq_msg_req msg = {0}; 1505 u16 msg_len; 1506 int status; 1507 1508 msg_len = sizeof(msg); 1509 1510 msg.dest_dev = in->dest_dev; 1511 msg.opcode = in->opcode; 1512 msg.flags = ICE_SBQ_MSG_FLAGS; 1513 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1514 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1515 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1516 1517 if (in->opcode) 1518 msg.data = cpu_to_le32(in->data); 1519 else 1520 /* data read comes back in completion, so shorten the struct by 1521 * sizeof(msg.data) 1522 */ 1523 msg_len -= sizeof(msg.data); 1524 1525 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1526 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1527 desc.param0.cmd_len = cpu_to_le16(msg_len); 1528 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1529 if (!status && !in->opcode) 1530 in->data = le32_to_cpu 1531 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1532 return status; 1533 } 1534 1535 /* FW Admin Queue command wrappers */ 1536 1537 /* Software lock/mutex that is meant to be held while the Global Config Lock 1538 * in firmware is acquired by the software to prevent most (but not all) types 1539 * of AQ commands from being sent to FW 1540 */ 1541 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1542 1543 /** 1544 * ice_should_retry_sq_send_cmd 1545 * @opcode: AQ opcode 1546 * 1547 * Decide if we should retry the send command routine for the ATQ, depending 1548 * on the opcode. 1549 */ 1550 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1551 { 1552 switch (opcode) { 1553 case ice_aqc_opc_get_link_topo: 1554 case ice_aqc_opc_lldp_stop: 1555 case ice_aqc_opc_lldp_start: 1556 case ice_aqc_opc_lldp_filter_ctrl: 1557 return true; 1558 } 1559 1560 return false; 1561 } 1562 1563 /** 1564 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1565 * @hw: pointer to the HW struct 1566 * @cq: pointer to the specific Control queue 1567 * @desc: prefilled descriptor describing the command 1568 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1569 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1570 * @cd: pointer to command details structure 1571 * 1572 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1573 * Queue if the EBUSY AQ error is returned. 1574 */ 1575 static int 1576 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1577 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1578 struct ice_sq_cd *cd) 1579 { 1580 struct ice_aq_desc desc_cpy; 1581 bool is_cmd_for_retry; 1582 u8 idx = 0; 1583 u16 opcode; 1584 int status; 1585 1586 opcode = le16_to_cpu(desc->opcode); 1587 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1588 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1589 1590 if (is_cmd_for_retry) { 1591 /* All retryable cmds are direct, without buf. */ 1592 WARN_ON(buf); 1593 1594 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1595 } 1596 1597 do { 1598 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1599 1600 if (!is_cmd_for_retry || !status || 1601 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1602 break; 1603 1604 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1605 1606 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1607 1608 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1609 1610 return status; 1611 } 1612 1613 /** 1614 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1615 * @hw: pointer to the HW struct 1616 * @desc: descriptor describing the command 1617 * @buf: buffer to use for indirect commands (NULL for direct commands) 1618 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1619 * @cd: pointer to command details structure 1620 * 1621 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1622 */ 1623 int 1624 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1625 u16 buf_size, struct ice_sq_cd *cd) 1626 { 1627 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1628 bool lock_acquired = false; 1629 int status; 1630 1631 /* When a package download is in process (i.e. when the firmware's 1632 * Global Configuration Lock resource is held), only the Download 1633 * Package, Get Version, Get Package Info List, Upload Section, 1634 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1635 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1636 * Recipes to Profile Association, and Release Resource (with resource 1637 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1638 * must block until the package download completes and the Global Config 1639 * Lock is released. See also ice_acquire_global_cfg_lock(). 1640 */ 1641 switch (le16_to_cpu(desc->opcode)) { 1642 case ice_aqc_opc_download_pkg: 1643 case ice_aqc_opc_get_pkg_info_list: 1644 case ice_aqc_opc_get_ver: 1645 case ice_aqc_opc_upload_section: 1646 case ice_aqc_opc_update_pkg: 1647 case ice_aqc_opc_set_port_params: 1648 case ice_aqc_opc_get_vlan_mode_parameters: 1649 case ice_aqc_opc_set_vlan_mode_parameters: 1650 case ice_aqc_opc_set_tx_topo: 1651 case ice_aqc_opc_get_tx_topo: 1652 case ice_aqc_opc_add_recipe: 1653 case ice_aqc_opc_recipe_to_profile: 1654 case ice_aqc_opc_get_recipe: 1655 case ice_aqc_opc_get_recipe_to_profile: 1656 break; 1657 case ice_aqc_opc_release_res: 1658 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1659 break; 1660 fallthrough; 1661 default: 1662 mutex_lock(&ice_global_cfg_lock_sw); 1663 lock_acquired = true; 1664 break; 1665 } 1666 1667 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1668 if (lock_acquired) 1669 mutex_unlock(&ice_global_cfg_lock_sw); 1670 1671 return status; 1672 } 1673 1674 /** 1675 * ice_aq_get_fw_ver 1676 * @hw: pointer to the HW struct 1677 * @cd: pointer to command details structure or NULL 1678 * 1679 * Get the firmware version (0x0001) from the admin queue commands 1680 */ 1681 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1682 { 1683 struct ice_aqc_get_ver *resp; 1684 struct ice_aq_desc desc; 1685 int status; 1686 1687 resp = &desc.params.get_ver; 1688 1689 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1690 1691 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1692 1693 if (!status) { 1694 hw->fw_branch = resp->fw_branch; 1695 hw->fw_maj_ver = resp->fw_major; 1696 hw->fw_min_ver = resp->fw_minor; 1697 hw->fw_patch = resp->fw_patch; 1698 hw->fw_build = le32_to_cpu(resp->fw_build); 1699 hw->api_branch = resp->api_branch; 1700 hw->api_maj_ver = resp->api_major; 1701 hw->api_min_ver = resp->api_minor; 1702 hw->api_patch = resp->api_patch; 1703 } 1704 1705 return status; 1706 } 1707 1708 /** 1709 * ice_aq_send_driver_ver 1710 * @hw: pointer to the HW struct 1711 * @dv: driver's major, minor version 1712 * @cd: pointer to command details structure or NULL 1713 * 1714 * Send the driver version (0x0002) to the firmware 1715 */ 1716 int 1717 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1718 struct ice_sq_cd *cd) 1719 { 1720 struct ice_aqc_driver_ver *cmd; 1721 struct ice_aq_desc desc; 1722 u16 len; 1723 1724 cmd = &desc.params.driver_ver; 1725 1726 if (!dv) 1727 return -EINVAL; 1728 1729 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1730 1731 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1732 cmd->major_ver = dv->major_ver; 1733 cmd->minor_ver = dv->minor_ver; 1734 cmd->build_ver = dv->build_ver; 1735 cmd->subbuild_ver = dv->subbuild_ver; 1736 1737 len = 0; 1738 while (len < sizeof(dv->driver_string) && 1739 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1740 len++; 1741 1742 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1743 } 1744 1745 /** 1746 * ice_aq_q_shutdown 1747 * @hw: pointer to the HW struct 1748 * @unloading: is the driver unloading itself 1749 * 1750 * Tell the Firmware that we're shutting down the AdminQ and whether 1751 * or not the driver is unloading as well (0x0003). 1752 */ 1753 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1754 { 1755 struct ice_aqc_q_shutdown *cmd; 1756 struct ice_aq_desc desc; 1757 1758 cmd = &desc.params.q_shutdown; 1759 1760 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1761 1762 if (unloading) 1763 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1764 1765 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1766 } 1767 1768 /** 1769 * ice_aq_req_res 1770 * @hw: pointer to the HW struct 1771 * @res: resource ID 1772 * @access: access type 1773 * @sdp_number: resource number 1774 * @timeout: the maximum time in ms that the driver may hold the resource 1775 * @cd: pointer to command details structure or NULL 1776 * 1777 * Requests common resource using the admin queue commands (0x0008). 1778 * When attempting to acquire the Global Config Lock, the driver can 1779 * learn of three states: 1780 * 1) 0 - acquired lock, and can perform download package 1781 * 2) -EIO - did not get lock, driver should fail to load 1782 * 3) -EALREADY - did not get lock, but another driver has 1783 * successfully downloaded the package; the driver does 1784 * not have to download the package and can continue 1785 * loading 1786 * 1787 * Note that if the caller is in an acquire lock, perform action, release lock 1788 * phase of operation, it is possible that the FW may detect a timeout and issue 1789 * a CORER. In this case, the driver will receive a CORER interrupt and will 1790 * have to determine its cause. The calling thread that is handling this flow 1791 * will likely get an error propagated back to it indicating the Download 1792 * Package, Update Package or the Release Resource AQ commands timed out. 1793 */ 1794 static int 1795 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1796 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1797 struct ice_sq_cd *cd) 1798 { 1799 struct ice_aqc_req_res *cmd_resp; 1800 struct ice_aq_desc desc; 1801 int status; 1802 1803 cmd_resp = &desc.params.res_owner; 1804 1805 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1806 1807 cmd_resp->res_id = cpu_to_le16(res); 1808 cmd_resp->access_type = cpu_to_le16(access); 1809 cmd_resp->res_number = cpu_to_le32(sdp_number); 1810 cmd_resp->timeout = cpu_to_le32(*timeout); 1811 *timeout = 0; 1812 1813 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1814 1815 /* The completion specifies the maximum time in ms that the driver 1816 * may hold the resource in the Timeout field. 1817 */ 1818 1819 /* Global config lock response utilizes an additional status field. 1820 * 1821 * If the Global config lock resource is held by some other driver, the 1822 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1823 * and the timeout field indicates the maximum time the current owner 1824 * of the resource has to free it. 1825 */ 1826 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1827 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1828 *timeout = le32_to_cpu(cmd_resp->timeout); 1829 return 0; 1830 } else if (le16_to_cpu(cmd_resp->status) == 1831 ICE_AQ_RES_GLBL_IN_PROG) { 1832 *timeout = le32_to_cpu(cmd_resp->timeout); 1833 return -EIO; 1834 } else if (le16_to_cpu(cmd_resp->status) == 1835 ICE_AQ_RES_GLBL_DONE) { 1836 return -EALREADY; 1837 } 1838 1839 /* invalid FW response, force a timeout immediately */ 1840 *timeout = 0; 1841 return -EIO; 1842 } 1843 1844 /* If the resource is held by some other driver, the command completes 1845 * with a busy return value and the timeout field indicates the maximum 1846 * time the current owner of the resource has to free it. 1847 */ 1848 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1849 *timeout = le32_to_cpu(cmd_resp->timeout); 1850 1851 return status; 1852 } 1853 1854 /** 1855 * ice_aq_release_res 1856 * @hw: pointer to the HW struct 1857 * @res: resource ID 1858 * @sdp_number: resource number 1859 * @cd: pointer to command details structure or NULL 1860 * 1861 * release common resource using the admin queue commands (0x0009) 1862 */ 1863 static int 1864 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1865 struct ice_sq_cd *cd) 1866 { 1867 struct ice_aqc_req_res *cmd; 1868 struct ice_aq_desc desc; 1869 1870 cmd = &desc.params.res_owner; 1871 1872 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1873 1874 cmd->res_id = cpu_to_le16(res); 1875 cmd->res_number = cpu_to_le32(sdp_number); 1876 1877 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1878 } 1879 1880 /** 1881 * ice_acquire_res 1882 * @hw: pointer to the HW structure 1883 * @res: resource ID 1884 * @access: access type (read or write) 1885 * @timeout: timeout in milliseconds 1886 * 1887 * This function will attempt to acquire the ownership of a resource. 1888 */ 1889 int 1890 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1891 enum ice_aq_res_access_type access, u32 timeout) 1892 { 1893 #define ICE_RES_POLLING_DELAY_MS 10 1894 u32 delay = ICE_RES_POLLING_DELAY_MS; 1895 u32 time_left = timeout; 1896 int status; 1897 1898 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1899 1900 /* A return code of -EALREADY means that another driver has 1901 * previously acquired the resource and performed any necessary updates; 1902 * in this case the caller does not obtain the resource and has no 1903 * further work to do. 1904 */ 1905 if (status == -EALREADY) 1906 goto ice_acquire_res_exit; 1907 1908 if (status) 1909 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1910 1911 /* If necessary, poll until the current lock owner timeouts */ 1912 timeout = time_left; 1913 while (status && timeout && time_left) { 1914 mdelay(delay); 1915 timeout = (timeout > delay) ? timeout - delay : 0; 1916 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1917 1918 if (status == -EALREADY) 1919 /* lock free, but no work to do */ 1920 break; 1921 1922 if (!status) 1923 /* lock acquired */ 1924 break; 1925 } 1926 if (status && status != -EALREADY) 1927 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1928 1929 ice_acquire_res_exit: 1930 if (status == -EALREADY) { 1931 if (access == ICE_RES_WRITE) 1932 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1933 else 1934 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1935 } 1936 return status; 1937 } 1938 1939 /** 1940 * ice_release_res 1941 * @hw: pointer to the HW structure 1942 * @res: resource ID 1943 * 1944 * This function will release a resource using the proper Admin Command. 1945 */ 1946 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1947 { 1948 unsigned long timeout; 1949 int status; 1950 1951 /* there are some rare cases when trying to release the resource 1952 * results in an admin queue timeout, so handle them correctly 1953 */ 1954 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 1955 do { 1956 status = ice_aq_release_res(hw, res, 0, NULL); 1957 if (status != -EIO) 1958 break; 1959 usleep_range(1000, 2000); 1960 } while (time_before(jiffies, timeout)); 1961 } 1962 1963 /** 1964 * ice_aq_alloc_free_res - command to allocate/free resources 1965 * @hw: pointer to the HW struct 1966 * @buf: Indirect buffer to hold data parameters and response 1967 * @buf_size: size of buffer for indirect commands 1968 * @opc: pass in the command opcode 1969 * 1970 * Helper function to allocate/free resources using the admin queue commands 1971 */ 1972 int ice_aq_alloc_free_res(struct ice_hw *hw, 1973 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1974 enum ice_adminq_opc opc) 1975 { 1976 struct ice_aqc_alloc_free_res_cmd *cmd; 1977 struct ice_aq_desc desc; 1978 1979 cmd = &desc.params.sw_res_ctrl; 1980 1981 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 1982 return -EINVAL; 1983 1984 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1985 1986 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1987 1988 cmd->num_entries = cpu_to_le16(1); 1989 1990 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 1991 } 1992 1993 /** 1994 * ice_alloc_hw_res - allocate resource 1995 * @hw: pointer to the HW struct 1996 * @type: type of resource 1997 * @num: number of resources to allocate 1998 * @btm: allocate from bottom 1999 * @res: pointer to array that will receive the resources 2000 */ 2001 int 2002 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2003 { 2004 struct ice_aqc_alloc_free_res_elem *buf; 2005 u16 buf_len; 2006 int status; 2007 2008 buf_len = struct_size(buf, elem, num); 2009 buf = kzalloc(buf_len, GFP_KERNEL); 2010 if (!buf) 2011 return -ENOMEM; 2012 2013 /* Prepare buffer to allocate resource. */ 2014 buf->num_elems = cpu_to_le16(num); 2015 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2016 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2017 if (btm) 2018 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2019 2020 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2021 if (status) 2022 goto ice_alloc_res_exit; 2023 2024 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2025 2026 ice_alloc_res_exit: 2027 kfree(buf); 2028 return status; 2029 } 2030 2031 /** 2032 * ice_free_hw_res - free allocated HW resource 2033 * @hw: pointer to the HW struct 2034 * @type: type of resource to free 2035 * @num: number of resources 2036 * @res: pointer to array that contains the resources to free 2037 */ 2038 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2039 { 2040 struct ice_aqc_alloc_free_res_elem *buf; 2041 u16 buf_len; 2042 int status; 2043 2044 buf_len = struct_size(buf, elem, num); 2045 buf = kzalloc(buf_len, GFP_KERNEL); 2046 if (!buf) 2047 return -ENOMEM; 2048 2049 /* Prepare buffer to free resource. */ 2050 buf->num_elems = cpu_to_le16(num); 2051 buf->res_type = cpu_to_le16(type); 2052 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2053 2054 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2055 if (status) 2056 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2057 2058 kfree(buf); 2059 return status; 2060 } 2061 2062 /** 2063 * ice_get_num_per_func - determine number of resources per PF 2064 * @hw: pointer to the HW structure 2065 * @max: value to be evenly split between each PF 2066 * 2067 * Determine the number of valid functions by going through the bitmap returned 2068 * from parsing capabilities and use this to calculate the number of resources 2069 * per PF based on the max value passed in. 2070 */ 2071 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2072 { 2073 u8 funcs; 2074 2075 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2076 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2077 ICE_CAPS_VALID_FUNCS_M); 2078 2079 if (!funcs) 2080 return 0; 2081 2082 return max / funcs; 2083 } 2084 2085 /** 2086 * ice_parse_common_caps - parse common device/function capabilities 2087 * @hw: pointer to the HW struct 2088 * @caps: pointer to common capabilities structure 2089 * @elem: the capability element to parse 2090 * @prefix: message prefix for tracing capabilities 2091 * 2092 * Given a capability element, extract relevant details into the common 2093 * capability structure. 2094 * 2095 * Returns: true if the capability matches one of the common capability ids, 2096 * false otherwise. 2097 */ 2098 static bool 2099 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2100 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2101 { 2102 u32 logical_id = le32_to_cpu(elem->logical_id); 2103 u32 phys_id = le32_to_cpu(elem->phys_id); 2104 u32 number = le32_to_cpu(elem->number); 2105 u16 cap = le16_to_cpu(elem->cap); 2106 bool found = true; 2107 2108 switch (cap) { 2109 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2110 caps->valid_functions = number; 2111 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2112 caps->valid_functions); 2113 break; 2114 case ICE_AQC_CAPS_SRIOV: 2115 caps->sr_iov_1_1 = (number == 1); 2116 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2117 caps->sr_iov_1_1); 2118 break; 2119 case ICE_AQC_CAPS_DCB: 2120 caps->dcb = (number == 1); 2121 caps->active_tc_bitmap = logical_id; 2122 caps->maxtc = phys_id; 2123 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2124 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2125 caps->active_tc_bitmap); 2126 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2127 break; 2128 case ICE_AQC_CAPS_RSS: 2129 caps->rss_table_size = number; 2130 caps->rss_table_entry_width = logical_id; 2131 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2132 caps->rss_table_size); 2133 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2134 caps->rss_table_entry_width); 2135 break; 2136 case ICE_AQC_CAPS_RXQS: 2137 caps->num_rxq = number; 2138 caps->rxq_first_id = phys_id; 2139 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2140 caps->num_rxq); 2141 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2142 caps->rxq_first_id); 2143 break; 2144 case ICE_AQC_CAPS_TXQS: 2145 caps->num_txq = number; 2146 caps->txq_first_id = phys_id; 2147 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2148 caps->num_txq); 2149 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2150 caps->txq_first_id); 2151 break; 2152 case ICE_AQC_CAPS_MSIX: 2153 caps->num_msix_vectors = number; 2154 caps->msix_vector_first_id = phys_id; 2155 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2156 caps->num_msix_vectors); 2157 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2158 caps->msix_vector_first_id); 2159 break; 2160 case ICE_AQC_CAPS_PENDING_NVM_VER: 2161 caps->nvm_update_pending_nvm = true; 2162 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2163 break; 2164 case ICE_AQC_CAPS_PENDING_OROM_VER: 2165 caps->nvm_update_pending_orom = true; 2166 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2167 break; 2168 case ICE_AQC_CAPS_PENDING_NET_VER: 2169 caps->nvm_update_pending_netlist = true; 2170 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2171 break; 2172 case ICE_AQC_CAPS_NVM_MGMT: 2173 caps->nvm_unified_update = 2174 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2175 true : false; 2176 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2177 caps->nvm_unified_update); 2178 break; 2179 case ICE_AQC_CAPS_RDMA: 2180 caps->rdma = (number == 1); 2181 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2182 break; 2183 case ICE_AQC_CAPS_MAX_MTU: 2184 caps->max_mtu = number; 2185 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2186 prefix, caps->max_mtu); 2187 break; 2188 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2189 caps->pcie_reset_avoidance = (number > 0); 2190 ice_debug(hw, ICE_DBG_INIT, 2191 "%s: pcie_reset_avoidance = %d\n", prefix, 2192 caps->pcie_reset_avoidance); 2193 break; 2194 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2195 caps->reset_restrict_support = (number == 1); 2196 ice_debug(hw, ICE_DBG_INIT, 2197 "%s: reset_restrict_support = %d\n", prefix, 2198 caps->reset_restrict_support); 2199 break; 2200 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2201 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2202 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2203 prefix, caps->roce_lag); 2204 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2205 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2206 prefix, caps->sriov_lag); 2207 break; 2208 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2209 caps->tx_sched_topo_comp_mode_en = (number == 1); 2210 break; 2211 default: 2212 /* Not one of the recognized common capabilities */ 2213 found = false; 2214 } 2215 2216 return found; 2217 } 2218 2219 /** 2220 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2221 * @hw: pointer to the HW structure 2222 * @caps: pointer to capabilities structure to fix 2223 * 2224 * Re-calculate the capabilities that are dependent on the number of physical 2225 * ports; i.e. some features are not supported or function differently on 2226 * devices with more than 4 ports. 2227 */ 2228 static void 2229 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2230 { 2231 /* This assumes device capabilities are always scanned before function 2232 * capabilities during the initialization flow. 2233 */ 2234 if (hw->dev_caps.num_funcs > 4) { 2235 /* Max 4 TCs per port */ 2236 caps->maxtc = 4; 2237 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2238 caps->maxtc); 2239 if (caps->rdma) { 2240 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2241 caps->rdma = 0; 2242 } 2243 2244 /* print message only when processing device capabilities 2245 * during initialization. 2246 */ 2247 if (caps == &hw->dev_caps.common_cap) 2248 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2249 } 2250 } 2251 2252 /** 2253 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2254 * @hw: pointer to the HW struct 2255 * @func_p: pointer to function capabilities structure 2256 * @cap: pointer to the capability element to parse 2257 * 2258 * Extract function capabilities for ICE_AQC_CAPS_VF. 2259 */ 2260 static void 2261 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2262 struct ice_aqc_list_caps_elem *cap) 2263 { 2264 u32 logical_id = le32_to_cpu(cap->logical_id); 2265 u32 number = le32_to_cpu(cap->number); 2266 2267 func_p->num_allocd_vfs = number; 2268 func_p->vf_base_id = logical_id; 2269 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2270 func_p->num_allocd_vfs); 2271 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2272 func_p->vf_base_id); 2273 } 2274 2275 /** 2276 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2277 * @hw: pointer to the HW struct 2278 * @func_p: pointer to function capabilities structure 2279 * @cap: pointer to the capability element to parse 2280 * 2281 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2282 */ 2283 static void 2284 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2285 struct ice_aqc_list_caps_elem *cap) 2286 { 2287 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2288 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2289 le32_to_cpu(cap->number)); 2290 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2291 func_p->guar_num_vsi); 2292 } 2293 2294 /** 2295 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2296 * @hw: pointer to the HW struct 2297 * @func_p: pointer to function capabilities structure 2298 * @cap: pointer to the capability element to parse 2299 * 2300 * Extract function capabilities for ICE_AQC_CAPS_1588. 2301 */ 2302 static void 2303 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2304 struct ice_aqc_list_caps_elem *cap) 2305 { 2306 struct ice_ts_func_info *info = &func_p->ts_func_info; 2307 u32 number = le32_to_cpu(cap->number); 2308 2309 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2310 func_p->common_cap.ieee_1588 = info->ena; 2311 2312 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2313 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2314 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2315 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2316 2317 if (!ice_is_e825c(hw)) { 2318 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2319 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2320 } else { 2321 info->clk_freq = ICE_TIME_REF_FREQ_156_250; 2322 info->clk_src = ICE_CLK_SRC_TCXO; 2323 } 2324 2325 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2326 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2327 } else { 2328 /* Unknown clock frequency, so assume a (probably incorrect) 2329 * default to avoid out-of-bounds look ups of frequency 2330 * related information. 2331 */ 2332 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2333 info->clk_freq); 2334 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2335 } 2336 2337 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2338 func_p->common_cap.ieee_1588); 2339 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2340 info->src_tmr_owned); 2341 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2342 info->tmr_ena); 2343 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2344 info->tmr_index_owned); 2345 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2346 info->tmr_index_assoc); 2347 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2348 info->clk_freq); 2349 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2350 info->clk_src); 2351 } 2352 2353 /** 2354 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2355 * @hw: pointer to the HW struct 2356 * @func_p: pointer to function capabilities structure 2357 * 2358 * Extract function capabilities for ICE_AQC_CAPS_FD. 2359 */ 2360 static void 2361 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2362 { 2363 u32 reg_val, gsize, bsize; 2364 2365 reg_val = rd32(hw, GLQF_FD_SIZE); 2366 switch (hw->mac_type) { 2367 case ICE_MAC_E830: 2368 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2369 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2370 break; 2371 case ICE_MAC_E810: 2372 default: 2373 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2374 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2375 } 2376 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2377 func_p->fd_fltr_best_effort = bsize; 2378 2379 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2380 func_p->fd_fltr_guar); 2381 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2382 func_p->fd_fltr_best_effort); 2383 } 2384 2385 /** 2386 * ice_parse_func_caps - Parse function capabilities 2387 * @hw: pointer to the HW struct 2388 * @func_p: pointer to function capabilities structure 2389 * @buf: buffer containing the function capability records 2390 * @cap_count: the number of capabilities 2391 * 2392 * Helper function to parse function (0x000A) capabilities list. For 2393 * capabilities shared between device and function, this relies on 2394 * ice_parse_common_caps. 2395 * 2396 * Loop through the list of provided capabilities and extract the relevant 2397 * data into the function capabilities structured. 2398 */ 2399 static void 2400 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2401 void *buf, u32 cap_count) 2402 { 2403 struct ice_aqc_list_caps_elem *cap_resp; 2404 u32 i; 2405 2406 cap_resp = buf; 2407 2408 memset(func_p, 0, sizeof(*func_p)); 2409 2410 for (i = 0; i < cap_count; i++) { 2411 u16 cap = le16_to_cpu(cap_resp[i].cap); 2412 bool found; 2413 2414 found = ice_parse_common_caps(hw, &func_p->common_cap, 2415 &cap_resp[i], "func caps"); 2416 2417 switch (cap) { 2418 case ICE_AQC_CAPS_VF: 2419 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2420 break; 2421 case ICE_AQC_CAPS_VSI: 2422 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2423 break; 2424 case ICE_AQC_CAPS_1588: 2425 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2426 break; 2427 case ICE_AQC_CAPS_FD: 2428 ice_parse_fdir_func_caps(hw, func_p); 2429 break; 2430 default: 2431 /* Don't list common capabilities as unknown */ 2432 if (!found) 2433 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2434 i, cap); 2435 break; 2436 } 2437 } 2438 2439 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2440 } 2441 2442 /** 2443 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2444 * @hw: pointer to the HW struct 2445 * @dev_p: pointer to device capabilities structure 2446 * @cap: capability element to parse 2447 * 2448 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2449 */ 2450 static void 2451 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2452 struct ice_aqc_list_caps_elem *cap) 2453 { 2454 u32 number = le32_to_cpu(cap->number); 2455 2456 dev_p->num_funcs = hweight32(number); 2457 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2458 dev_p->num_funcs); 2459 } 2460 2461 /** 2462 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2463 * @hw: pointer to the HW struct 2464 * @dev_p: pointer to device capabilities structure 2465 * @cap: capability element to parse 2466 * 2467 * Parse ICE_AQC_CAPS_VF for device capabilities. 2468 */ 2469 static void 2470 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2471 struct ice_aqc_list_caps_elem *cap) 2472 { 2473 u32 number = le32_to_cpu(cap->number); 2474 2475 dev_p->num_vfs_exposed = number; 2476 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2477 dev_p->num_vfs_exposed); 2478 } 2479 2480 /** 2481 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2482 * @hw: pointer to the HW struct 2483 * @dev_p: pointer to device capabilities structure 2484 * @cap: capability element to parse 2485 * 2486 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2487 */ 2488 static void 2489 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2490 struct ice_aqc_list_caps_elem *cap) 2491 { 2492 u32 number = le32_to_cpu(cap->number); 2493 2494 dev_p->num_vsi_allocd_to_host = number; 2495 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2496 dev_p->num_vsi_allocd_to_host); 2497 } 2498 2499 /** 2500 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2501 * @hw: pointer to the HW struct 2502 * @dev_p: pointer to device capabilities structure 2503 * @cap: capability element to parse 2504 * 2505 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2506 */ 2507 static void 2508 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2509 struct ice_aqc_list_caps_elem *cap) 2510 { 2511 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2512 u32 logical_id = le32_to_cpu(cap->logical_id); 2513 u32 phys_id = le32_to_cpu(cap->phys_id); 2514 u32 number = le32_to_cpu(cap->number); 2515 2516 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2517 dev_p->common_cap.ieee_1588 = info->ena; 2518 2519 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2520 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2521 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2522 2523 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2524 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2525 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2526 2527 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2528 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2529 2530 info->ena_ports = logical_id; 2531 info->tmr_own_map = phys_id; 2532 2533 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2534 dev_p->common_cap.ieee_1588); 2535 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2536 info->tmr0_owner); 2537 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2538 info->tmr0_owned); 2539 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2540 info->tmr0_ena); 2541 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2542 info->tmr1_owner); 2543 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2544 info->tmr1_owned); 2545 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2546 info->tmr1_ena); 2547 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2548 info->ts_ll_read); 2549 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2550 info->ts_ll_int_read); 2551 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2552 info->ena_ports); 2553 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2554 info->tmr_own_map); 2555 } 2556 2557 /** 2558 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2559 * @hw: pointer to the HW struct 2560 * @dev_p: pointer to device capabilities structure 2561 * @cap: capability element to parse 2562 * 2563 * Parse ICE_AQC_CAPS_FD for device capabilities. 2564 */ 2565 static void 2566 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2567 struct ice_aqc_list_caps_elem *cap) 2568 { 2569 u32 number = le32_to_cpu(cap->number); 2570 2571 dev_p->num_flow_director_fltr = number; 2572 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2573 dev_p->num_flow_director_fltr); 2574 } 2575 2576 /** 2577 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2578 * @hw: pointer to the HW struct 2579 * @dev_p: pointer to device capabilities structure 2580 * @cap: capability element to parse 2581 * 2582 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2583 * enabled sensors. 2584 */ 2585 static void 2586 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2587 struct ice_aqc_list_caps_elem *cap) 2588 { 2589 dev_p->supported_sensors = le32_to_cpu(cap->number); 2590 2591 ice_debug(hw, ICE_DBG_INIT, 2592 "dev caps: supported sensors (bitmap) = 0x%x\n", 2593 dev_p->supported_sensors); 2594 } 2595 2596 /** 2597 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2598 * @hw: pointer to the HW struct 2599 * @dev_p: pointer to device capabilities structure 2600 * @cap: capability element to parse 2601 * 2602 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2603 */ 2604 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2605 struct ice_hw_dev_caps *dev_p, 2606 struct ice_aqc_list_caps_elem *cap) 2607 { 2608 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2609 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2610 2611 dev_info(ice_hw_to_dev(hw), 2612 "PF is configured in %s mode with IP instance ID %d\n", 2613 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2614 "primary" : "secondary", dev_p->nac_topo.id); 2615 2616 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2617 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2618 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2619 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2620 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2621 dev_p->nac_topo.id); 2622 } 2623 2624 /** 2625 * ice_parse_dev_caps - Parse device capabilities 2626 * @hw: pointer to the HW struct 2627 * @dev_p: pointer to device capabilities structure 2628 * @buf: buffer containing the device capability records 2629 * @cap_count: the number of capabilities 2630 * 2631 * Helper device to parse device (0x000B) capabilities list. For 2632 * capabilities shared between device and function, this relies on 2633 * ice_parse_common_caps. 2634 * 2635 * Loop through the list of provided capabilities and extract the relevant 2636 * data into the device capabilities structured. 2637 */ 2638 static void 2639 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2640 void *buf, u32 cap_count) 2641 { 2642 struct ice_aqc_list_caps_elem *cap_resp; 2643 u32 i; 2644 2645 cap_resp = buf; 2646 2647 memset(dev_p, 0, sizeof(*dev_p)); 2648 2649 for (i = 0; i < cap_count; i++) { 2650 u16 cap = le16_to_cpu(cap_resp[i].cap); 2651 bool found; 2652 2653 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2654 &cap_resp[i], "dev caps"); 2655 2656 switch (cap) { 2657 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2658 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2659 break; 2660 case ICE_AQC_CAPS_VF: 2661 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2662 break; 2663 case ICE_AQC_CAPS_VSI: 2664 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2665 break; 2666 case ICE_AQC_CAPS_1588: 2667 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2668 break; 2669 case ICE_AQC_CAPS_FD: 2670 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2671 break; 2672 case ICE_AQC_CAPS_SENSOR_READING: 2673 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2674 break; 2675 case ICE_AQC_CAPS_NAC_TOPOLOGY: 2676 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2677 break; 2678 default: 2679 /* Don't list common capabilities as unknown */ 2680 if (!found) 2681 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2682 i, cap); 2683 break; 2684 } 2685 } 2686 2687 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2688 } 2689 2690 /** 2691 * ice_is_pf_c827 - check if pf contains c827 phy 2692 * @hw: pointer to the hw struct 2693 */ 2694 bool ice_is_pf_c827(struct ice_hw *hw) 2695 { 2696 struct ice_aqc_get_link_topo cmd = {}; 2697 u8 node_part_number; 2698 u16 node_handle; 2699 int status; 2700 2701 if (hw->mac_type != ICE_MAC_E810) 2702 return false; 2703 2704 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 2705 return true; 2706 2707 cmd.addr.topo_params.node_type_ctx = 2708 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 2709 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 2710 cmd.addr.topo_params.index = 0; 2711 2712 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 2713 &node_handle); 2714 2715 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 2716 return false; 2717 2718 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 2719 return true; 2720 2721 return false; 2722 } 2723 2724 /** 2725 * ice_is_phy_rclk_in_netlist 2726 * @hw: pointer to the hw struct 2727 * 2728 * Check if the PHY Recovered Clock device is present in the netlist 2729 */ 2730 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2731 { 2732 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2733 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2734 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2735 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2736 return false; 2737 2738 return true; 2739 } 2740 2741 /** 2742 * ice_is_clock_mux_in_netlist 2743 * @hw: pointer to the hw struct 2744 * 2745 * Check if the Clock Multiplexer device is present in the netlist 2746 */ 2747 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2748 { 2749 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2750 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2751 NULL)) 2752 return false; 2753 2754 return true; 2755 } 2756 2757 /** 2758 * ice_is_cgu_in_netlist - check for CGU presence 2759 * @hw: pointer to the hw struct 2760 * 2761 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2762 * Save the CGU part number in the hw structure for later use. 2763 * Return: 2764 * * true - cgu is present 2765 * * false - cgu is not present 2766 */ 2767 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2768 { 2769 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2770 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2771 NULL)) { 2772 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2773 return true; 2774 } else if (!ice_find_netlist_node(hw, 2775 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2776 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2777 NULL)) { 2778 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2779 return true; 2780 } 2781 2782 return false; 2783 } 2784 2785 /** 2786 * ice_is_gps_in_netlist 2787 * @hw: pointer to the hw struct 2788 * 2789 * Check if the GPS generic device is present in the netlist 2790 */ 2791 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2792 { 2793 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2794 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 2795 return false; 2796 2797 return true; 2798 } 2799 2800 /** 2801 * ice_aq_list_caps - query function/device capabilities 2802 * @hw: pointer to the HW struct 2803 * @buf: a buffer to hold the capabilities 2804 * @buf_size: size of the buffer 2805 * @cap_count: if not NULL, set to the number of capabilities reported 2806 * @opc: capabilities type to discover, device or function 2807 * @cd: pointer to command details structure or NULL 2808 * 2809 * Get the function (0x000A) or device (0x000B) capabilities description from 2810 * firmware and store it in the buffer. 2811 * 2812 * If the cap_count pointer is not NULL, then it is set to the number of 2813 * capabilities firmware will report. Note that if the buffer size is too 2814 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2815 * cap_count will still be updated in this case. It is recommended that the 2816 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2817 * firmware could return) to avoid this. 2818 */ 2819 int 2820 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2821 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2822 { 2823 struct ice_aqc_list_caps *cmd; 2824 struct ice_aq_desc desc; 2825 int status; 2826 2827 cmd = &desc.params.get_cap; 2828 2829 if (opc != ice_aqc_opc_list_func_caps && 2830 opc != ice_aqc_opc_list_dev_caps) 2831 return -EINVAL; 2832 2833 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2834 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2835 2836 if (cap_count) 2837 *cap_count = le32_to_cpu(cmd->count); 2838 2839 return status; 2840 } 2841 2842 /** 2843 * ice_discover_dev_caps - Read and extract device capabilities 2844 * @hw: pointer to the hardware structure 2845 * @dev_caps: pointer to device capabilities structure 2846 * 2847 * Read the device capabilities and extract them into the dev_caps structure 2848 * for later use. 2849 */ 2850 int 2851 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2852 { 2853 u32 cap_count = 0; 2854 void *cbuf; 2855 int status; 2856 2857 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2858 if (!cbuf) 2859 return -ENOMEM; 2860 2861 /* Although the driver doesn't know the number of capabilities the 2862 * device will return, we can simply send a 4KB buffer, the maximum 2863 * possible size that firmware can return. 2864 */ 2865 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2866 2867 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2868 ice_aqc_opc_list_dev_caps, NULL); 2869 if (!status) 2870 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2871 kfree(cbuf); 2872 2873 return status; 2874 } 2875 2876 /** 2877 * ice_discover_func_caps - Read and extract function capabilities 2878 * @hw: pointer to the hardware structure 2879 * @func_caps: pointer to function capabilities structure 2880 * 2881 * Read the function capabilities and extract them into the func_caps structure 2882 * for later use. 2883 */ 2884 static int 2885 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2886 { 2887 u32 cap_count = 0; 2888 void *cbuf; 2889 int status; 2890 2891 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2892 if (!cbuf) 2893 return -ENOMEM; 2894 2895 /* Although the driver doesn't know the number of capabilities the 2896 * device will return, we can simply send a 4KB buffer, the maximum 2897 * possible size that firmware can return. 2898 */ 2899 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2900 2901 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2902 ice_aqc_opc_list_func_caps, NULL); 2903 if (!status) 2904 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2905 kfree(cbuf); 2906 2907 return status; 2908 } 2909 2910 /** 2911 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2912 * @hw: pointer to the hardware structure 2913 */ 2914 void ice_set_safe_mode_caps(struct ice_hw *hw) 2915 { 2916 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2917 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2918 struct ice_hw_common_caps cached_caps; 2919 u32 num_funcs; 2920 2921 /* cache some func_caps values that should be restored after memset */ 2922 cached_caps = func_caps->common_cap; 2923 2924 /* unset func capabilities */ 2925 memset(func_caps, 0, sizeof(*func_caps)); 2926 2927 #define ICE_RESTORE_FUNC_CAP(name) \ 2928 func_caps->common_cap.name = cached_caps.name 2929 2930 /* restore cached values */ 2931 ICE_RESTORE_FUNC_CAP(valid_functions); 2932 ICE_RESTORE_FUNC_CAP(txq_first_id); 2933 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2934 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2935 ICE_RESTORE_FUNC_CAP(max_mtu); 2936 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2937 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2938 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2939 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2940 2941 /* one Tx and one Rx queue in safe mode */ 2942 func_caps->common_cap.num_rxq = 1; 2943 func_caps->common_cap.num_txq = 1; 2944 2945 /* two MSIX vectors, one for traffic and one for misc causes */ 2946 func_caps->common_cap.num_msix_vectors = 2; 2947 func_caps->guar_num_vsi = 1; 2948 2949 /* cache some dev_caps values that should be restored after memset */ 2950 cached_caps = dev_caps->common_cap; 2951 num_funcs = dev_caps->num_funcs; 2952 2953 /* unset dev capabilities */ 2954 memset(dev_caps, 0, sizeof(*dev_caps)); 2955 2956 #define ICE_RESTORE_DEV_CAP(name) \ 2957 dev_caps->common_cap.name = cached_caps.name 2958 2959 /* restore cached values */ 2960 ICE_RESTORE_DEV_CAP(valid_functions); 2961 ICE_RESTORE_DEV_CAP(txq_first_id); 2962 ICE_RESTORE_DEV_CAP(rxq_first_id); 2963 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2964 ICE_RESTORE_DEV_CAP(max_mtu); 2965 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2966 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2967 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2968 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2969 dev_caps->num_funcs = num_funcs; 2970 2971 /* one Tx and one Rx queue per function in safe mode */ 2972 dev_caps->common_cap.num_rxq = num_funcs; 2973 dev_caps->common_cap.num_txq = num_funcs; 2974 2975 /* two MSIX vectors per function */ 2976 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2977 } 2978 2979 /** 2980 * ice_get_caps - get info about the HW 2981 * @hw: pointer to the hardware structure 2982 */ 2983 int ice_get_caps(struct ice_hw *hw) 2984 { 2985 int status; 2986 2987 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2988 if (status) 2989 return status; 2990 2991 return ice_discover_func_caps(hw, &hw->func_caps); 2992 } 2993 2994 /** 2995 * ice_aq_manage_mac_write - manage MAC address write command 2996 * @hw: pointer to the HW struct 2997 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2998 * @flags: flags to control write behavior 2999 * @cd: pointer to command details structure or NULL 3000 * 3001 * This function is used to write MAC address to the NVM (0x0108). 3002 */ 3003 int 3004 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3005 struct ice_sq_cd *cd) 3006 { 3007 struct ice_aqc_manage_mac_write *cmd; 3008 struct ice_aq_desc desc; 3009 3010 cmd = &desc.params.mac_write; 3011 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3012 3013 cmd->flags = flags; 3014 ether_addr_copy(cmd->mac_addr, mac_addr); 3015 3016 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3017 } 3018 3019 /** 3020 * ice_aq_clear_pxe_mode 3021 * @hw: pointer to the HW struct 3022 * 3023 * Tell the firmware that the driver is taking over from PXE (0x0110). 3024 */ 3025 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3026 { 3027 struct ice_aq_desc desc; 3028 3029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3030 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3031 3032 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3033 } 3034 3035 /** 3036 * ice_clear_pxe_mode - clear pxe operations mode 3037 * @hw: pointer to the HW struct 3038 * 3039 * Make sure all PXE mode settings are cleared, including things 3040 * like descriptor fetch/write-back mode. 3041 */ 3042 void ice_clear_pxe_mode(struct ice_hw *hw) 3043 { 3044 if (ice_check_sq_alive(hw, &hw->adminq)) 3045 ice_aq_clear_pxe_mode(hw); 3046 } 3047 3048 /** 3049 * ice_aq_set_port_params - set physical port parameters. 3050 * @pi: pointer to the port info struct 3051 * @double_vlan: if set double VLAN is enabled 3052 * @cd: pointer to command details structure or NULL 3053 * 3054 * Set Physical port parameters (0x0203) 3055 */ 3056 int 3057 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3058 struct ice_sq_cd *cd) 3059 3060 { 3061 struct ice_aqc_set_port_params *cmd; 3062 struct ice_hw *hw = pi->hw; 3063 struct ice_aq_desc desc; 3064 u16 cmd_flags = 0; 3065 3066 cmd = &desc.params.set_port_params; 3067 3068 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3069 if (double_vlan) 3070 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3071 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3072 3073 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3074 } 3075 3076 /** 3077 * ice_is_100m_speed_supported 3078 * @hw: pointer to the HW struct 3079 * 3080 * returns true if 100M speeds are supported by the device, 3081 * false otherwise. 3082 */ 3083 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3084 { 3085 switch (hw->device_id) { 3086 case ICE_DEV_ID_E822C_SGMII: 3087 case ICE_DEV_ID_E822L_SGMII: 3088 case ICE_DEV_ID_E823L_1GBE: 3089 case ICE_DEV_ID_E823C_SGMII: 3090 return true; 3091 default: 3092 return false; 3093 } 3094 } 3095 3096 /** 3097 * ice_get_link_speed_based_on_phy_type - returns link speed 3098 * @phy_type_low: lower part of phy_type 3099 * @phy_type_high: higher part of phy_type 3100 * 3101 * This helper function will convert an entry in PHY type structure 3102 * [phy_type_low, phy_type_high] to its corresponding link speed. 3103 * Note: In the structure of [phy_type_low, phy_type_high], there should 3104 * be one bit set, as this function will convert one PHY type to its 3105 * speed. 3106 * 3107 * Return: 3108 * * PHY speed for recognized PHY type 3109 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3110 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3111 */ 3112 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3113 { 3114 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3115 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3116 3117 switch (phy_type_low) { 3118 case ICE_PHY_TYPE_LOW_100BASE_TX: 3119 case ICE_PHY_TYPE_LOW_100M_SGMII: 3120 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3121 break; 3122 case ICE_PHY_TYPE_LOW_1000BASE_T: 3123 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3124 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3125 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3126 case ICE_PHY_TYPE_LOW_1G_SGMII: 3127 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3128 break; 3129 case ICE_PHY_TYPE_LOW_2500BASE_T: 3130 case ICE_PHY_TYPE_LOW_2500BASE_X: 3131 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3132 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3133 break; 3134 case ICE_PHY_TYPE_LOW_5GBASE_T: 3135 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3136 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3137 break; 3138 case ICE_PHY_TYPE_LOW_10GBASE_T: 3139 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3140 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3141 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3142 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3143 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3144 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3145 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3146 break; 3147 case ICE_PHY_TYPE_LOW_25GBASE_T: 3148 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3149 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3150 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3151 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3152 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3153 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3154 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3155 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3156 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3157 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3158 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3159 break; 3160 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3161 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3162 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3163 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3164 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3165 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3166 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3167 break; 3168 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3169 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3170 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3171 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3172 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3173 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3174 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3175 case ICE_PHY_TYPE_LOW_50G_AUI2: 3176 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3177 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3178 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3179 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3180 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3181 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3182 case ICE_PHY_TYPE_LOW_50G_AUI1: 3183 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3184 break; 3185 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3186 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3187 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3188 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3189 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3190 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3191 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3192 case ICE_PHY_TYPE_LOW_100G_AUI4: 3193 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3194 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3195 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3196 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3197 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3198 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3199 break; 3200 default: 3201 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3202 break; 3203 } 3204 3205 switch (phy_type_high) { 3206 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3207 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3208 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3209 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3210 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3211 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3212 break; 3213 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3214 case ICE_PHY_TYPE_HIGH_200G_SR4: 3215 case ICE_PHY_TYPE_HIGH_200G_FR4: 3216 case ICE_PHY_TYPE_HIGH_200G_LR4: 3217 case ICE_PHY_TYPE_HIGH_200G_DR4: 3218 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3219 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3220 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3221 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3222 break; 3223 default: 3224 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3225 break; 3226 } 3227 3228 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3229 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3230 return ICE_AQ_LINK_SPEED_UNKNOWN; 3231 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3232 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3233 return ICE_AQ_LINK_SPEED_UNKNOWN; 3234 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3235 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3236 return speed_phy_type_low; 3237 else 3238 return speed_phy_type_high; 3239 } 3240 3241 /** 3242 * ice_update_phy_type 3243 * @phy_type_low: pointer to the lower part of phy_type 3244 * @phy_type_high: pointer to the higher part of phy_type 3245 * @link_speeds_bitmap: targeted link speeds bitmap 3246 * 3247 * Note: For the link_speeds_bitmap structure, you can check it at 3248 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3249 * link_speeds_bitmap include multiple speeds. 3250 * 3251 * Each entry in this [phy_type_low, phy_type_high] structure will 3252 * present a certain link speed. This helper function will turn on bits 3253 * in [phy_type_low, phy_type_high] structure based on the value of 3254 * link_speeds_bitmap input parameter. 3255 */ 3256 void 3257 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3258 u16 link_speeds_bitmap) 3259 { 3260 u64 pt_high; 3261 u64 pt_low; 3262 int index; 3263 u16 speed; 3264 3265 /* We first check with low part of phy_type */ 3266 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3267 pt_low = BIT_ULL(index); 3268 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3269 3270 if (link_speeds_bitmap & speed) 3271 *phy_type_low |= BIT_ULL(index); 3272 } 3273 3274 /* We then check with high part of phy_type */ 3275 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3276 pt_high = BIT_ULL(index); 3277 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3278 3279 if (link_speeds_bitmap & speed) 3280 *phy_type_high |= BIT_ULL(index); 3281 } 3282 } 3283 3284 /** 3285 * ice_aq_set_phy_cfg 3286 * @hw: pointer to the HW struct 3287 * @pi: port info structure of the interested logical port 3288 * @cfg: structure with PHY configuration data to be set 3289 * @cd: pointer to command details structure or NULL 3290 * 3291 * Set the various PHY configuration parameters supported on the Port. 3292 * One or more of the Set PHY config parameters may be ignored in an MFP 3293 * mode as the PF may not have the privilege to set some of the PHY Config 3294 * parameters. This status will be indicated by the command response (0x0601). 3295 */ 3296 int 3297 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3298 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3299 { 3300 struct ice_aq_desc desc; 3301 int status; 3302 3303 if (!cfg) 3304 return -EINVAL; 3305 3306 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3307 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3308 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3309 cfg->caps); 3310 3311 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3312 } 3313 3314 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3315 desc.params.set_phy.lport_num = pi->lport; 3316 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3317 3318 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3319 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3320 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3321 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3322 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3323 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3324 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3325 cfg->low_power_ctrl_an); 3326 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3327 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3328 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3329 cfg->link_fec_opt); 3330 3331 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3332 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3333 status = 0; 3334 3335 if (!status) 3336 pi->phy.curr_user_phy_cfg = *cfg; 3337 3338 return status; 3339 } 3340 3341 /** 3342 * ice_update_link_info - update status of the HW network link 3343 * @pi: port info structure of the interested logical port 3344 */ 3345 int ice_update_link_info(struct ice_port_info *pi) 3346 { 3347 struct ice_link_status *li; 3348 int status; 3349 3350 if (!pi) 3351 return -EINVAL; 3352 3353 li = &pi->phy.link_info; 3354 3355 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3356 if (status) 3357 return status; 3358 3359 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3360 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3361 3362 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3363 if (!pcaps) 3364 return -ENOMEM; 3365 3366 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3367 pcaps, NULL); 3368 } 3369 3370 return status; 3371 } 3372 3373 /** 3374 * ice_cache_phy_user_req 3375 * @pi: port information structure 3376 * @cache_data: PHY logging data 3377 * @cache_mode: PHY logging mode 3378 * 3379 * Log the user request on (FC, FEC, SPEED) for later use. 3380 */ 3381 static void 3382 ice_cache_phy_user_req(struct ice_port_info *pi, 3383 struct ice_phy_cache_mode_data cache_data, 3384 enum ice_phy_cache_mode cache_mode) 3385 { 3386 if (!pi) 3387 return; 3388 3389 switch (cache_mode) { 3390 case ICE_FC_MODE: 3391 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3392 break; 3393 case ICE_SPEED_MODE: 3394 pi->phy.curr_user_speed_req = 3395 cache_data.data.curr_user_speed_req; 3396 break; 3397 case ICE_FEC_MODE: 3398 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3399 break; 3400 default: 3401 break; 3402 } 3403 } 3404 3405 /** 3406 * ice_caps_to_fc_mode 3407 * @caps: PHY capabilities 3408 * 3409 * Convert PHY FC capabilities to ice FC mode 3410 */ 3411 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3412 { 3413 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3414 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3415 return ICE_FC_FULL; 3416 3417 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3418 return ICE_FC_TX_PAUSE; 3419 3420 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3421 return ICE_FC_RX_PAUSE; 3422 3423 return ICE_FC_NONE; 3424 } 3425 3426 /** 3427 * ice_caps_to_fec_mode 3428 * @caps: PHY capabilities 3429 * @fec_options: Link FEC options 3430 * 3431 * Convert PHY FEC capabilities to ice FEC mode 3432 */ 3433 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3434 { 3435 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3436 return ICE_FEC_AUTO; 3437 3438 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3439 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3440 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3441 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3442 return ICE_FEC_BASER; 3443 3444 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3445 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3446 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3447 return ICE_FEC_RS; 3448 3449 return ICE_FEC_NONE; 3450 } 3451 3452 /** 3453 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3454 * @pi: port information structure 3455 * @cfg: PHY configuration data to set FC mode 3456 * @req_mode: FC mode to configure 3457 */ 3458 int 3459 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3460 enum ice_fc_mode req_mode) 3461 { 3462 struct ice_phy_cache_mode_data cache_data; 3463 u8 pause_mask = 0x0; 3464 3465 if (!pi || !cfg) 3466 return -EINVAL; 3467 3468 switch (req_mode) { 3469 case ICE_FC_FULL: 3470 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3471 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3472 break; 3473 case ICE_FC_RX_PAUSE: 3474 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3475 break; 3476 case ICE_FC_TX_PAUSE: 3477 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3478 break; 3479 default: 3480 break; 3481 } 3482 3483 /* clear the old pause settings */ 3484 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3485 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3486 3487 /* set the new capabilities */ 3488 cfg->caps |= pause_mask; 3489 3490 /* Cache user FC request */ 3491 cache_data.data.curr_user_fc_req = req_mode; 3492 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3493 3494 return 0; 3495 } 3496 3497 /** 3498 * ice_set_fc 3499 * @pi: port information structure 3500 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3501 * @ena_auto_link_update: enable automatic link update 3502 * 3503 * Set the requested flow control mode. 3504 */ 3505 int 3506 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3507 { 3508 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3509 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3510 struct ice_hw *hw; 3511 int status; 3512 3513 if (!pi || !aq_failures) 3514 return -EINVAL; 3515 3516 *aq_failures = 0; 3517 hw = pi->hw; 3518 3519 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3520 if (!pcaps) 3521 return -ENOMEM; 3522 3523 /* Get the current PHY config */ 3524 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3525 pcaps, NULL); 3526 if (status) { 3527 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3528 goto out; 3529 } 3530 3531 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3532 3533 /* Configure the set PHY data */ 3534 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3535 if (status) 3536 goto out; 3537 3538 /* If the capabilities have changed, then set the new config */ 3539 if (cfg.caps != pcaps->caps) { 3540 int retry_count, retry_max = 10; 3541 3542 /* Auto restart link so settings take effect */ 3543 if (ena_auto_link_update) 3544 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3545 3546 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3547 if (status) { 3548 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3549 goto out; 3550 } 3551 3552 /* Update the link info 3553 * It sometimes takes a really long time for link to 3554 * come back from the atomic reset. Thus, we wait a 3555 * little bit. 3556 */ 3557 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3558 status = ice_update_link_info(pi); 3559 3560 if (!status) 3561 break; 3562 3563 mdelay(100); 3564 } 3565 3566 if (status) 3567 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3568 } 3569 3570 out: 3571 return status; 3572 } 3573 3574 /** 3575 * ice_phy_caps_equals_cfg 3576 * @phy_caps: PHY capabilities 3577 * @phy_cfg: PHY configuration 3578 * 3579 * Helper function to determine if PHY capabilities matches PHY 3580 * configuration 3581 */ 3582 bool 3583 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3584 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3585 { 3586 u8 caps_mask, cfg_mask; 3587 3588 if (!phy_caps || !phy_cfg) 3589 return false; 3590 3591 /* These bits are not common between capabilities and configuration. 3592 * Do not use them to determine equality. 3593 */ 3594 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3595 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3596 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3597 3598 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3599 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3600 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3601 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3602 phy_caps->eee_cap != phy_cfg->eee_cap || 3603 phy_caps->eeer_value != phy_cfg->eeer_value || 3604 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3605 return false; 3606 3607 return true; 3608 } 3609 3610 /** 3611 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3612 * @pi: port information structure 3613 * @caps: PHY ability structure to copy date from 3614 * @cfg: PHY configuration structure to copy data to 3615 * 3616 * Helper function to copy AQC PHY get ability data to PHY set configuration 3617 * data structure 3618 */ 3619 void 3620 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3621 struct ice_aqc_get_phy_caps_data *caps, 3622 struct ice_aqc_set_phy_cfg_data *cfg) 3623 { 3624 if (!pi || !caps || !cfg) 3625 return; 3626 3627 memset(cfg, 0, sizeof(*cfg)); 3628 cfg->phy_type_low = caps->phy_type_low; 3629 cfg->phy_type_high = caps->phy_type_high; 3630 cfg->caps = caps->caps; 3631 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3632 cfg->eee_cap = caps->eee_cap; 3633 cfg->eeer_value = caps->eeer_value; 3634 cfg->link_fec_opt = caps->link_fec_options; 3635 cfg->module_compliance_enforcement = 3636 caps->module_compliance_enforcement; 3637 } 3638 3639 /** 3640 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3641 * @pi: port information structure 3642 * @cfg: PHY configuration data to set FEC mode 3643 * @fec: FEC mode to configure 3644 */ 3645 int 3646 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3647 enum ice_fec_mode fec) 3648 { 3649 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3650 struct ice_hw *hw; 3651 int status; 3652 3653 if (!pi || !cfg) 3654 return -EINVAL; 3655 3656 hw = pi->hw; 3657 3658 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3659 if (!pcaps) 3660 return -ENOMEM; 3661 3662 status = ice_aq_get_phy_caps(pi, false, 3663 (ice_fw_supports_report_dflt_cfg(hw) ? 3664 ICE_AQC_REPORT_DFLT_CFG : 3665 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3666 if (status) 3667 goto out; 3668 3669 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3670 cfg->link_fec_opt = pcaps->link_fec_options; 3671 3672 switch (fec) { 3673 case ICE_FEC_BASER: 3674 /* Clear RS bits, and AND BASE-R ability 3675 * bits and OR request bits. 3676 */ 3677 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3678 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3679 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3680 ICE_AQC_PHY_FEC_25G_KR_REQ; 3681 break; 3682 case ICE_FEC_RS: 3683 /* Clear BASE-R bits, and AND RS ability 3684 * bits and OR request bits. 3685 */ 3686 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3687 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3688 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3689 break; 3690 case ICE_FEC_NONE: 3691 /* Clear all FEC option bits. */ 3692 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3693 break; 3694 case ICE_FEC_AUTO: 3695 /* AND auto FEC bit, and all caps bits. */ 3696 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3697 cfg->link_fec_opt |= pcaps->link_fec_options; 3698 break; 3699 default: 3700 status = -EINVAL; 3701 break; 3702 } 3703 3704 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3705 !ice_fw_supports_report_dflt_cfg(hw)) { 3706 struct ice_link_default_override_tlv tlv = { 0 }; 3707 3708 status = ice_get_link_default_override(&tlv, pi); 3709 if (status) 3710 goto out; 3711 3712 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3713 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3714 cfg->link_fec_opt = tlv.fec_options; 3715 } 3716 3717 out: 3718 return status; 3719 } 3720 3721 /** 3722 * ice_get_link_status - get status of the HW network link 3723 * @pi: port information structure 3724 * @link_up: pointer to bool (true/false = linkup/linkdown) 3725 * 3726 * Variable link_up is true if link is up, false if link is down. 3727 * The variable link_up is invalid if status is non zero. As a 3728 * result of this call, link status reporting becomes enabled 3729 */ 3730 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3731 { 3732 struct ice_phy_info *phy_info; 3733 int status = 0; 3734 3735 if (!pi || !link_up) 3736 return -EINVAL; 3737 3738 phy_info = &pi->phy; 3739 3740 if (phy_info->get_link_info) { 3741 status = ice_update_link_info(pi); 3742 3743 if (status) 3744 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3745 status); 3746 } 3747 3748 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3749 3750 return status; 3751 } 3752 3753 /** 3754 * ice_aq_set_link_restart_an 3755 * @pi: pointer to the port information structure 3756 * @ena_link: if true: enable link, if false: disable link 3757 * @cd: pointer to command details structure or NULL 3758 * 3759 * Sets up the link and restarts the Auto-Negotiation over the link. 3760 */ 3761 int 3762 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3763 struct ice_sq_cd *cd) 3764 { 3765 struct ice_aqc_restart_an *cmd; 3766 struct ice_aq_desc desc; 3767 3768 cmd = &desc.params.restart_an; 3769 3770 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3771 3772 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3773 cmd->lport_num = pi->lport; 3774 if (ena_link) 3775 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3776 else 3777 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3778 3779 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3780 } 3781 3782 /** 3783 * ice_aq_set_event_mask 3784 * @hw: pointer to the HW struct 3785 * @port_num: port number of the physical function 3786 * @mask: event mask to be set 3787 * @cd: pointer to command details structure or NULL 3788 * 3789 * Set event mask (0x0613) 3790 */ 3791 int 3792 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3793 struct ice_sq_cd *cd) 3794 { 3795 struct ice_aqc_set_event_mask *cmd; 3796 struct ice_aq_desc desc; 3797 3798 cmd = &desc.params.set_event_mask; 3799 3800 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3801 3802 cmd->lport_num = port_num; 3803 3804 cmd->event_mask = cpu_to_le16(mask); 3805 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3806 } 3807 3808 /** 3809 * ice_aq_set_mac_loopback 3810 * @hw: pointer to the HW struct 3811 * @ena_lpbk: Enable or Disable loopback 3812 * @cd: pointer to command details structure or NULL 3813 * 3814 * Enable/disable loopback on a given port 3815 */ 3816 int 3817 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3818 { 3819 struct ice_aqc_set_mac_lb *cmd; 3820 struct ice_aq_desc desc; 3821 3822 cmd = &desc.params.set_mac_lb; 3823 3824 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3825 if (ena_lpbk) 3826 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3827 3828 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3829 } 3830 3831 /** 3832 * ice_aq_set_port_id_led 3833 * @pi: pointer to the port information 3834 * @is_orig_mode: is this LED set to original mode (by the net-list) 3835 * @cd: pointer to command details structure or NULL 3836 * 3837 * Set LED value for the given port (0x06e9) 3838 */ 3839 int 3840 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3841 struct ice_sq_cd *cd) 3842 { 3843 struct ice_aqc_set_port_id_led *cmd; 3844 struct ice_hw *hw = pi->hw; 3845 struct ice_aq_desc desc; 3846 3847 cmd = &desc.params.set_port_id_led; 3848 3849 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3850 3851 if (is_orig_mode) 3852 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3853 else 3854 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3855 3856 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3857 } 3858 3859 /** 3860 * ice_aq_get_port_options 3861 * @hw: pointer to the HW struct 3862 * @options: buffer for the resultant port options 3863 * @option_count: input - size of the buffer in port options structures, 3864 * output - number of returned port options 3865 * @lport: logical port to call the command with (optional) 3866 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3867 * when PF owns more than 1 port it must be true 3868 * @active_option_idx: index of active port option in returned buffer 3869 * @active_option_valid: active option in returned buffer is valid 3870 * @pending_option_idx: index of pending port option in returned buffer 3871 * @pending_option_valid: pending option in returned buffer is valid 3872 * 3873 * Calls Get Port Options AQC (0x06ea) and verifies result. 3874 */ 3875 int 3876 ice_aq_get_port_options(struct ice_hw *hw, 3877 struct ice_aqc_get_port_options_elem *options, 3878 u8 *option_count, u8 lport, bool lport_valid, 3879 u8 *active_option_idx, bool *active_option_valid, 3880 u8 *pending_option_idx, bool *pending_option_valid) 3881 { 3882 struct ice_aqc_get_port_options *cmd; 3883 struct ice_aq_desc desc; 3884 int status; 3885 u8 i; 3886 3887 /* options buffer shall be able to hold max returned options */ 3888 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3889 return -EINVAL; 3890 3891 cmd = &desc.params.get_port_options; 3892 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3893 3894 if (lport_valid) 3895 cmd->lport_num = lport; 3896 cmd->lport_num_valid = lport_valid; 3897 3898 status = ice_aq_send_cmd(hw, &desc, options, 3899 *option_count * sizeof(*options), NULL); 3900 if (status) 3901 return status; 3902 3903 /* verify direct FW response & set output parameters */ 3904 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3905 cmd->port_options_count); 3906 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3907 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3908 cmd->port_options); 3909 if (*active_option_valid) { 3910 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3911 cmd->port_options); 3912 if (*active_option_idx > (*option_count - 1)) 3913 return -EIO; 3914 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3915 *active_option_idx); 3916 } 3917 3918 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3919 cmd->pending_port_option_status); 3920 if (*pending_option_valid) { 3921 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3922 cmd->pending_port_option_status); 3923 if (*pending_option_idx > (*option_count - 1)) 3924 return -EIO; 3925 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3926 *pending_option_idx); 3927 } 3928 3929 /* mask output options fields */ 3930 for (i = 0; i < *option_count; i++) { 3931 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3932 options[i].pmd); 3933 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3934 options[i].max_lane_speed); 3935 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3936 options[i].pmd, options[i].max_lane_speed); 3937 } 3938 3939 return 0; 3940 } 3941 3942 /** 3943 * ice_aq_set_port_option 3944 * @hw: pointer to the HW struct 3945 * @lport: logical port to call the command with 3946 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3947 * when PF owns more than 1 port it must be true 3948 * @new_option: new port option to be written 3949 * 3950 * Calls Set Port Options AQC (0x06eb). 3951 */ 3952 int 3953 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3954 u8 new_option) 3955 { 3956 struct ice_aqc_set_port_option *cmd; 3957 struct ice_aq_desc desc; 3958 3959 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3960 return -EINVAL; 3961 3962 cmd = &desc.params.set_port_option; 3963 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3964 3965 if (lport_valid) 3966 cmd->lport_num = lport; 3967 3968 cmd->lport_num_valid = lport_valid; 3969 cmd->selected_port_option = new_option; 3970 3971 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3972 } 3973 3974 /** 3975 * ice_aq_sff_eeprom 3976 * @hw: pointer to the HW struct 3977 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3978 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3979 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3980 * @page: QSFP page 3981 * @set_page: set or ignore the page 3982 * @data: pointer to data buffer to be read/written to the I2C device. 3983 * @length: 1-16 for read, 1 for write. 3984 * @write: 0 read, 1 for write. 3985 * @cd: pointer to command details structure or NULL 3986 * 3987 * Read/Write SFF EEPROM (0x06EE) 3988 */ 3989 int 3990 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3991 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3992 bool write, struct ice_sq_cd *cd) 3993 { 3994 struct ice_aqc_sff_eeprom *cmd; 3995 struct ice_aq_desc desc; 3996 u16 i2c_bus_addr; 3997 int status; 3998 3999 if (!data || (mem_addr & 0xff00)) 4000 return -EINVAL; 4001 4002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4003 cmd = &desc.params.read_write_sff_param; 4004 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4005 cmd->lport_num = (u8)(lport & 0xff); 4006 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4007 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4008 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4009 if (write) 4010 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4011 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4012 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4013 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4014 4015 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4016 return status; 4017 } 4018 4019 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4020 { 4021 switch (type) { 4022 case ICE_LUT_VSI: 4023 return ICE_LUT_VSI_SIZE; 4024 case ICE_LUT_GLOBAL: 4025 return ICE_LUT_GLOBAL_SIZE; 4026 case ICE_LUT_PF: 4027 return ICE_LUT_PF_SIZE; 4028 } 4029 WARN_ONCE(1, "incorrect type passed"); 4030 return ICE_LUT_VSI_SIZE; 4031 } 4032 4033 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4034 { 4035 switch (size) { 4036 case ICE_LUT_VSI_SIZE: 4037 return ICE_AQC_LUT_SIZE_SMALL; 4038 case ICE_LUT_GLOBAL_SIZE: 4039 return ICE_AQC_LUT_SIZE_512; 4040 case ICE_LUT_PF_SIZE: 4041 return ICE_AQC_LUT_SIZE_2K; 4042 } 4043 WARN_ONCE(1, "incorrect size passed"); 4044 return 0; 4045 } 4046 4047 /** 4048 * __ice_aq_get_set_rss_lut 4049 * @hw: pointer to the hardware structure 4050 * @params: RSS LUT parameters 4051 * @set: set true to set the table, false to get the table 4052 * 4053 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4054 */ 4055 static int 4056 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4057 struct ice_aq_get_set_rss_lut_params *params, bool set) 4058 { 4059 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4060 enum ice_lut_type lut_type = params->lut_type; 4061 struct ice_aqc_get_set_rss_lut *desc_params; 4062 enum ice_aqc_lut_flags flags; 4063 enum ice_lut_size lut_size; 4064 struct ice_aq_desc desc; 4065 u8 *lut = params->lut; 4066 4067 4068 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4069 return -EINVAL; 4070 4071 lut_size = ice_lut_type_to_size(lut_type); 4072 if (lut_size > params->lut_size) 4073 return -EINVAL; 4074 else if (set && lut_size != params->lut_size) 4075 return -EINVAL; 4076 4077 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4078 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4079 if (set) 4080 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4081 4082 desc_params = &desc.params.get_set_rss_lut; 4083 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4084 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4085 4086 if (lut_type == ICE_LUT_GLOBAL) 4087 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4088 params->global_lut_id); 4089 4090 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4091 desc_params->flags = cpu_to_le16(flags); 4092 4093 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4094 } 4095 4096 /** 4097 * ice_aq_get_rss_lut 4098 * @hw: pointer to the hardware structure 4099 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4100 * 4101 * get the RSS lookup table, PF or VSI type 4102 */ 4103 int 4104 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4105 { 4106 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4107 } 4108 4109 /** 4110 * ice_aq_set_rss_lut 4111 * @hw: pointer to the hardware structure 4112 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4113 * 4114 * set the RSS lookup table, PF or VSI type 4115 */ 4116 int 4117 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4118 { 4119 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4120 } 4121 4122 /** 4123 * __ice_aq_get_set_rss_key 4124 * @hw: pointer to the HW struct 4125 * @vsi_id: VSI FW index 4126 * @key: pointer to key info struct 4127 * @set: set true to set the key, false to get the key 4128 * 4129 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4130 */ 4131 static int 4132 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4133 struct ice_aqc_get_set_rss_keys *key, bool set) 4134 { 4135 struct ice_aqc_get_set_rss_key *desc_params; 4136 u16 key_size = sizeof(*key); 4137 struct ice_aq_desc desc; 4138 4139 if (set) { 4140 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4141 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4142 } else { 4143 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4144 } 4145 4146 desc_params = &desc.params.get_set_rss_key; 4147 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4148 4149 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4150 } 4151 4152 /** 4153 * ice_aq_get_rss_key 4154 * @hw: pointer to the HW struct 4155 * @vsi_handle: software VSI handle 4156 * @key: pointer to key info struct 4157 * 4158 * get the RSS key per VSI 4159 */ 4160 int 4161 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4162 struct ice_aqc_get_set_rss_keys *key) 4163 { 4164 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4165 return -EINVAL; 4166 4167 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4168 key, false); 4169 } 4170 4171 /** 4172 * ice_aq_set_rss_key 4173 * @hw: pointer to the HW struct 4174 * @vsi_handle: software VSI handle 4175 * @keys: pointer to key info struct 4176 * 4177 * set the RSS key per VSI 4178 */ 4179 int 4180 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4181 struct ice_aqc_get_set_rss_keys *keys) 4182 { 4183 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4184 return -EINVAL; 4185 4186 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4187 keys, true); 4188 } 4189 4190 /** 4191 * ice_aq_add_lan_txq 4192 * @hw: pointer to the hardware structure 4193 * @num_qgrps: Number of added queue groups 4194 * @qg_list: list of queue groups to be added 4195 * @buf_size: size of buffer for indirect command 4196 * @cd: pointer to command details structure or NULL 4197 * 4198 * Add Tx LAN queue (0x0C30) 4199 * 4200 * NOTE: 4201 * Prior to calling add Tx LAN queue: 4202 * Initialize the following as part of the Tx queue context: 4203 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4204 * Cache profile and Packet shaper profile. 4205 * 4206 * After add Tx LAN queue AQ command is completed: 4207 * Interrupts should be associated with specific queues, 4208 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4209 * flow. 4210 */ 4211 static int 4212 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4213 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4214 struct ice_sq_cd *cd) 4215 { 4216 struct ice_aqc_add_tx_qgrp *list; 4217 struct ice_aqc_add_txqs *cmd; 4218 struct ice_aq_desc desc; 4219 u16 i, sum_size = 0; 4220 4221 cmd = &desc.params.add_txqs; 4222 4223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4224 4225 if (!qg_list) 4226 return -EINVAL; 4227 4228 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4229 return -EINVAL; 4230 4231 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4232 sum_size += struct_size(list, txqs, list->num_txqs); 4233 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4234 list->num_txqs); 4235 } 4236 4237 if (buf_size != sum_size) 4238 return -EINVAL; 4239 4240 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4241 4242 cmd->num_qgrps = num_qgrps; 4243 4244 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4245 } 4246 4247 /** 4248 * ice_aq_dis_lan_txq 4249 * @hw: pointer to the hardware structure 4250 * @num_qgrps: number of groups in the list 4251 * @qg_list: the list of groups to disable 4252 * @buf_size: the total size of the qg_list buffer in bytes 4253 * @rst_src: if called due to reset, specifies the reset source 4254 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4255 * @cd: pointer to command details structure or NULL 4256 * 4257 * Disable LAN Tx queue (0x0C31) 4258 */ 4259 static int 4260 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4261 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4262 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4263 struct ice_sq_cd *cd) 4264 { 4265 struct ice_aqc_dis_txq_item *item; 4266 struct ice_aqc_dis_txqs *cmd; 4267 struct ice_aq_desc desc; 4268 u16 vmvf_and_timeout; 4269 u16 i, sz = 0; 4270 int status; 4271 4272 cmd = &desc.params.dis_txqs; 4273 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4274 4275 /* qg_list can be NULL only in VM/VF reset flow */ 4276 if (!qg_list && !rst_src) 4277 return -EINVAL; 4278 4279 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4280 return -EINVAL; 4281 4282 cmd->num_entries = num_qgrps; 4283 4284 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4285 4286 switch (rst_src) { 4287 case ICE_VM_RESET: 4288 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4289 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4290 break; 4291 case ICE_VF_RESET: 4292 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4293 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4294 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4295 ICE_AQC_Q_DIS_VMVF_NUM_M; 4296 break; 4297 case ICE_NO_RESET: 4298 default: 4299 break; 4300 } 4301 4302 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4303 4304 /* flush pipe on time out */ 4305 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4306 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4307 if (!qg_list) 4308 goto do_aq; 4309 4310 /* set RD bit to indicate that command buffer is provided by the driver 4311 * and it needs to be read by the firmware 4312 */ 4313 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4314 4315 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4316 u16 item_size = struct_size(item, q_id, item->num_qs); 4317 4318 /* If the num of queues is even, add 2 bytes of padding */ 4319 if ((item->num_qs % 2) == 0) 4320 item_size += 2; 4321 4322 sz += item_size; 4323 4324 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4325 } 4326 4327 if (buf_size != sz) 4328 return -EINVAL; 4329 4330 do_aq: 4331 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4332 if (status) { 4333 if (!qg_list) 4334 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4335 vmvf_num, hw->adminq.sq_last_status); 4336 else 4337 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4338 le16_to_cpu(qg_list[0].q_id[0]), 4339 hw->adminq.sq_last_status); 4340 } 4341 return status; 4342 } 4343 4344 /** 4345 * ice_aq_cfg_lan_txq 4346 * @hw: pointer to the hardware structure 4347 * @buf: buffer for command 4348 * @buf_size: size of buffer in bytes 4349 * @num_qs: number of queues being configured 4350 * @oldport: origination lport 4351 * @newport: destination lport 4352 * @cd: pointer to command details structure or NULL 4353 * 4354 * Move/Configure LAN Tx queue (0x0C32) 4355 * 4356 * There is a better AQ command to use for moving nodes, so only coding 4357 * this one for configuring the node. 4358 */ 4359 int 4360 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4361 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4362 struct ice_sq_cd *cd) 4363 { 4364 struct ice_aqc_cfg_txqs *cmd; 4365 struct ice_aq_desc desc; 4366 int status; 4367 4368 cmd = &desc.params.cfg_txqs; 4369 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4370 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4371 4372 if (!buf) 4373 return -EINVAL; 4374 4375 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4376 cmd->num_qs = num_qs; 4377 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4378 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4379 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4380 cmd->blocked_cgds = 0; 4381 4382 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4383 if (status) 4384 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4385 hw->adminq.sq_last_status); 4386 return status; 4387 } 4388 4389 /** 4390 * ice_aq_add_rdma_qsets 4391 * @hw: pointer to the hardware structure 4392 * @num_qset_grps: Number of RDMA Qset groups 4393 * @qset_list: list of Qset groups to be added 4394 * @buf_size: size of buffer for indirect command 4395 * @cd: pointer to command details structure or NULL 4396 * 4397 * Add Tx RDMA Qsets (0x0C33) 4398 */ 4399 static int 4400 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4401 struct ice_aqc_add_rdma_qset_data *qset_list, 4402 u16 buf_size, struct ice_sq_cd *cd) 4403 { 4404 struct ice_aqc_add_rdma_qset_data *list; 4405 struct ice_aqc_add_rdma_qset *cmd; 4406 struct ice_aq_desc desc; 4407 u16 i, sum_size = 0; 4408 4409 cmd = &desc.params.add_rdma_qset; 4410 4411 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4412 4413 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4414 return -EINVAL; 4415 4416 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4417 u16 num_qsets = le16_to_cpu(list->num_qsets); 4418 4419 sum_size += struct_size(list, rdma_qsets, num_qsets); 4420 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4421 num_qsets); 4422 } 4423 4424 if (buf_size != sum_size) 4425 return -EINVAL; 4426 4427 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4428 4429 cmd->num_qset_grps = num_qset_grps; 4430 4431 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4432 } 4433 4434 /* End of FW Admin Queue command wrappers */ 4435 4436 /** 4437 * ice_pack_ctx_byte - write a byte to a packed context structure 4438 * @src_ctx: unpacked source context structure 4439 * @dest_ctx: packed destination context data 4440 * @ce_info: context element description 4441 */ 4442 static void ice_pack_ctx_byte(u8 *src_ctx, u8 *dest_ctx, 4443 const struct ice_ctx_ele *ce_info) 4444 { 4445 u8 src_byte, dest_byte, mask; 4446 u8 *from, *dest; 4447 u16 shift_width; 4448 4449 /* copy from the next struct field */ 4450 from = src_ctx + ce_info->offset; 4451 4452 /* prepare the bits and mask */ 4453 shift_width = ce_info->lsb % 8; 4454 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4455 4456 src_byte = *from; 4457 src_byte <<= shift_width; 4458 src_byte &= mask; 4459 4460 /* get the current bits from the target bit string */ 4461 dest = dest_ctx + (ce_info->lsb / 8); 4462 4463 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4464 4465 dest_byte &= ~mask; /* get the bits not changing */ 4466 dest_byte |= src_byte; /* add in the new bits */ 4467 4468 /* put it all back */ 4469 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4470 } 4471 4472 /** 4473 * ice_pack_ctx_word - write a word to a packed context structure 4474 * @src_ctx: unpacked source context structure 4475 * @dest_ctx: packed destination context data 4476 * @ce_info: context element description 4477 */ 4478 static void ice_pack_ctx_word(u8 *src_ctx, u8 *dest_ctx, 4479 const struct ice_ctx_ele *ce_info) 4480 { 4481 u16 src_word, mask; 4482 __le16 dest_word; 4483 u8 *from, *dest; 4484 u16 shift_width; 4485 4486 /* copy from the next struct field */ 4487 from = src_ctx + ce_info->offset; 4488 4489 /* prepare the bits and mask */ 4490 shift_width = ce_info->lsb % 8; 4491 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4492 4493 /* don't swizzle the bits until after the mask because the mask bits 4494 * will be in a different bit position on big endian machines 4495 */ 4496 src_word = *(u16 *)from; 4497 src_word <<= shift_width; 4498 src_word &= mask; 4499 4500 /* get the current bits from the target bit string */ 4501 dest = dest_ctx + (ce_info->lsb / 8); 4502 4503 memcpy(&dest_word, dest, sizeof(dest_word)); 4504 4505 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4506 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4507 4508 /* put it all back */ 4509 memcpy(dest, &dest_word, sizeof(dest_word)); 4510 } 4511 4512 /** 4513 * ice_pack_ctx_dword - write a dword to a packed context structure 4514 * @src_ctx: unpacked source context structure 4515 * @dest_ctx: packed destination context data 4516 * @ce_info: context element description 4517 */ 4518 static void ice_pack_ctx_dword(u8 *src_ctx, u8 *dest_ctx, 4519 const struct ice_ctx_ele *ce_info) 4520 { 4521 u32 src_dword, mask; 4522 __le32 dest_dword; 4523 u8 *from, *dest; 4524 u16 shift_width; 4525 4526 /* copy from the next struct field */ 4527 from = src_ctx + ce_info->offset; 4528 4529 /* prepare the bits and mask */ 4530 shift_width = ce_info->lsb % 8; 4531 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4532 4533 /* don't swizzle the bits until after the mask because the mask bits 4534 * will be in a different bit position on big endian machines 4535 */ 4536 src_dword = *(u32 *)from; 4537 src_dword <<= shift_width; 4538 src_dword &= mask; 4539 4540 /* get the current bits from the target bit string */ 4541 dest = dest_ctx + (ce_info->lsb / 8); 4542 4543 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4544 4545 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4546 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4547 4548 /* put it all back */ 4549 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4550 } 4551 4552 /** 4553 * ice_pack_ctx_qword - write a qword to a packed context structure 4554 * @src_ctx: unpacked source context structure 4555 * @dest_ctx: packed destination context data 4556 * @ce_info: context element description 4557 */ 4558 static void ice_pack_ctx_qword(u8 *src_ctx, u8 *dest_ctx, 4559 const struct ice_ctx_ele *ce_info) 4560 { 4561 u64 src_qword, mask; 4562 __le64 dest_qword; 4563 u8 *from, *dest; 4564 u16 shift_width; 4565 4566 /* copy from the next struct field */ 4567 from = src_ctx + ce_info->offset; 4568 4569 /* prepare the bits and mask */ 4570 shift_width = ce_info->lsb % 8; 4571 mask = GENMASK_ULL(ce_info->width - 1 + shift_width, shift_width); 4572 4573 /* don't swizzle the bits until after the mask because the mask bits 4574 * will be in a different bit position on big endian machines 4575 */ 4576 src_qword = *(u64 *)from; 4577 src_qword <<= shift_width; 4578 src_qword &= mask; 4579 4580 /* get the current bits from the target bit string */ 4581 dest = dest_ctx + (ce_info->lsb / 8); 4582 4583 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4584 4585 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4586 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4587 4588 /* put it all back */ 4589 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4590 } 4591 4592 /** 4593 * ice_set_ctx - set context bits in packed structure 4594 * @hw: pointer to the hardware structure 4595 * @src_ctx: pointer to a generic non-packed context structure 4596 * @dest_ctx: pointer to memory for the packed structure 4597 * @ce_info: List of Rx context elements 4598 */ 4599 int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4600 const struct ice_ctx_ele *ce_info) 4601 { 4602 int f; 4603 4604 for (f = 0; ce_info[f].width; f++) { 4605 /* We have to deal with each element of the FW response 4606 * using the correct size so that we are correct regardless 4607 * of the endianness of the machine. 4608 */ 4609 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4610 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4611 f, ce_info[f].width, ce_info[f].size_of); 4612 continue; 4613 } 4614 switch (ce_info[f].size_of) { 4615 case sizeof(u8): 4616 ice_pack_ctx_byte(src_ctx, dest_ctx, &ce_info[f]); 4617 break; 4618 case sizeof(u16): 4619 ice_pack_ctx_word(src_ctx, dest_ctx, &ce_info[f]); 4620 break; 4621 case sizeof(u32): 4622 ice_pack_ctx_dword(src_ctx, dest_ctx, &ce_info[f]); 4623 break; 4624 case sizeof(u64): 4625 ice_pack_ctx_qword(src_ctx, dest_ctx, &ce_info[f]); 4626 break; 4627 default: 4628 return -EINVAL; 4629 } 4630 } 4631 4632 return 0; 4633 } 4634 4635 /** 4636 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4637 * @hw: pointer to the HW struct 4638 * @vsi_handle: software VSI handle 4639 * @tc: TC number 4640 * @q_handle: software queue handle 4641 */ 4642 struct ice_q_ctx * 4643 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4644 { 4645 struct ice_vsi_ctx *vsi; 4646 struct ice_q_ctx *q_ctx; 4647 4648 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4649 if (!vsi) 4650 return NULL; 4651 if (q_handle >= vsi->num_lan_q_entries[tc]) 4652 return NULL; 4653 if (!vsi->lan_q_ctx[tc]) 4654 return NULL; 4655 q_ctx = vsi->lan_q_ctx[tc]; 4656 return &q_ctx[q_handle]; 4657 } 4658 4659 /** 4660 * ice_ena_vsi_txq 4661 * @pi: port information structure 4662 * @vsi_handle: software VSI handle 4663 * @tc: TC number 4664 * @q_handle: software queue handle 4665 * @num_qgrps: Number of added queue groups 4666 * @buf: list of queue groups to be added 4667 * @buf_size: size of buffer for indirect command 4668 * @cd: pointer to command details structure or NULL 4669 * 4670 * This function adds one LAN queue 4671 */ 4672 int 4673 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4674 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4675 struct ice_sq_cd *cd) 4676 { 4677 struct ice_aqc_txsched_elem_data node = { 0 }; 4678 struct ice_sched_node *parent; 4679 struct ice_q_ctx *q_ctx; 4680 struct ice_hw *hw; 4681 int status; 4682 4683 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4684 return -EIO; 4685 4686 if (num_qgrps > 1 || buf->num_txqs > 1) 4687 return -ENOSPC; 4688 4689 hw = pi->hw; 4690 4691 if (!ice_is_vsi_valid(hw, vsi_handle)) 4692 return -EINVAL; 4693 4694 mutex_lock(&pi->sched_lock); 4695 4696 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4697 if (!q_ctx) { 4698 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4699 q_handle); 4700 status = -EINVAL; 4701 goto ena_txq_exit; 4702 } 4703 4704 /* find a parent node */ 4705 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4706 ICE_SCHED_NODE_OWNER_LAN); 4707 if (!parent) { 4708 status = -EINVAL; 4709 goto ena_txq_exit; 4710 } 4711 4712 buf->parent_teid = parent->info.node_teid; 4713 node.parent_teid = parent->info.node_teid; 4714 /* Mark that the values in the "generic" section as valid. The default 4715 * value in the "generic" section is zero. This means that : 4716 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4717 * - 0 priority among siblings, indicated by Bit 1-3. 4718 * - WFQ, indicated by Bit 4. 4719 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4720 * Bit 5-6. 4721 * - Bit 7 is reserved. 4722 * Without setting the generic section as valid in valid_sections, the 4723 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4724 */ 4725 buf->txqs[0].info.valid_sections = 4726 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4727 ICE_AQC_ELEM_VALID_EIR; 4728 buf->txqs[0].info.generic = 0; 4729 buf->txqs[0].info.cir_bw.bw_profile_idx = 4730 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4731 buf->txqs[0].info.cir_bw.bw_alloc = 4732 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4733 buf->txqs[0].info.eir_bw.bw_profile_idx = 4734 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4735 buf->txqs[0].info.eir_bw.bw_alloc = 4736 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4737 4738 /* add the LAN queue */ 4739 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4740 if (status) { 4741 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4742 le16_to_cpu(buf->txqs[0].txq_id), 4743 hw->adminq.sq_last_status); 4744 goto ena_txq_exit; 4745 } 4746 4747 node.node_teid = buf->txqs[0].q_teid; 4748 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4749 q_ctx->q_handle = q_handle; 4750 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4751 4752 /* add a leaf node into scheduler tree queue layer */ 4753 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4754 if (!status) 4755 status = ice_sched_replay_q_bw(pi, q_ctx); 4756 4757 ena_txq_exit: 4758 mutex_unlock(&pi->sched_lock); 4759 return status; 4760 } 4761 4762 /** 4763 * ice_dis_vsi_txq 4764 * @pi: port information structure 4765 * @vsi_handle: software VSI handle 4766 * @tc: TC number 4767 * @num_queues: number of queues 4768 * @q_handles: pointer to software queue handle array 4769 * @q_ids: pointer to the q_id array 4770 * @q_teids: pointer to queue node teids 4771 * @rst_src: if called due to reset, specifies the reset source 4772 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4773 * @cd: pointer to command details structure or NULL 4774 * 4775 * This function removes queues and their corresponding nodes in SW DB 4776 */ 4777 int 4778 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4779 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4780 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4781 struct ice_sq_cd *cd) 4782 { 4783 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4784 u16 i, buf_size = __struct_size(qg_list); 4785 struct ice_q_ctx *q_ctx; 4786 int status = -ENOENT; 4787 struct ice_hw *hw; 4788 4789 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4790 return -EIO; 4791 4792 hw = pi->hw; 4793 4794 if (!num_queues) { 4795 /* if queue is disabled already yet the disable queue command 4796 * has to be sent to complete the VF reset, then call 4797 * ice_aq_dis_lan_txq without any queue information 4798 */ 4799 if (rst_src) 4800 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4801 vmvf_num, NULL); 4802 return -EIO; 4803 } 4804 4805 mutex_lock(&pi->sched_lock); 4806 4807 for (i = 0; i < num_queues; i++) { 4808 struct ice_sched_node *node; 4809 4810 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4811 if (!node) 4812 continue; 4813 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4814 if (!q_ctx) { 4815 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4816 q_handles[i]); 4817 continue; 4818 } 4819 if (q_ctx->q_handle != q_handles[i]) { 4820 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4821 q_ctx->q_handle, q_handles[i]); 4822 continue; 4823 } 4824 qg_list->parent_teid = node->info.parent_teid; 4825 qg_list->num_qs = 1; 4826 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4827 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4828 vmvf_num, cd); 4829 4830 if (status) 4831 break; 4832 ice_free_sched_node(pi, node); 4833 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4834 q_ctx->q_teid = ICE_INVAL_TEID; 4835 } 4836 mutex_unlock(&pi->sched_lock); 4837 return status; 4838 } 4839 4840 /** 4841 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4842 * @pi: port information structure 4843 * @vsi_handle: software VSI handle 4844 * @tc_bitmap: TC bitmap 4845 * @maxqs: max queues array per TC 4846 * @owner: LAN or RDMA 4847 * 4848 * This function adds/updates the VSI queues per TC. 4849 */ 4850 static int 4851 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4852 u16 *maxqs, u8 owner) 4853 { 4854 int status = 0; 4855 u8 i; 4856 4857 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4858 return -EIO; 4859 4860 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4861 return -EINVAL; 4862 4863 mutex_lock(&pi->sched_lock); 4864 4865 ice_for_each_traffic_class(i) { 4866 /* configuration is possible only if TC node is present */ 4867 if (!ice_sched_get_tc_node(pi, i)) 4868 continue; 4869 4870 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4871 ice_is_tc_ena(tc_bitmap, i)); 4872 if (status) 4873 break; 4874 } 4875 4876 mutex_unlock(&pi->sched_lock); 4877 return status; 4878 } 4879 4880 /** 4881 * ice_cfg_vsi_lan - configure VSI LAN queues 4882 * @pi: port information structure 4883 * @vsi_handle: software VSI handle 4884 * @tc_bitmap: TC bitmap 4885 * @max_lanqs: max LAN queues array per TC 4886 * 4887 * This function adds/updates the VSI LAN queues per TC. 4888 */ 4889 int 4890 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4891 u16 *max_lanqs) 4892 { 4893 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4894 ICE_SCHED_NODE_OWNER_LAN); 4895 } 4896 4897 /** 4898 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4899 * @pi: port information structure 4900 * @vsi_handle: software VSI handle 4901 * @tc_bitmap: TC bitmap 4902 * @max_rdmaqs: max RDMA queues array per TC 4903 * 4904 * This function adds/updates the VSI RDMA queues per TC. 4905 */ 4906 int 4907 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4908 u16 *max_rdmaqs) 4909 { 4910 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4911 ICE_SCHED_NODE_OWNER_RDMA); 4912 } 4913 4914 /** 4915 * ice_ena_vsi_rdma_qset 4916 * @pi: port information structure 4917 * @vsi_handle: software VSI handle 4918 * @tc: TC number 4919 * @rdma_qset: pointer to RDMA Qset 4920 * @num_qsets: number of RDMA Qsets 4921 * @qset_teid: pointer to Qset node TEIDs 4922 * 4923 * This function adds RDMA Qset 4924 */ 4925 int 4926 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4927 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4928 { 4929 struct ice_aqc_txsched_elem_data node = { 0 }; 4930 struct ice_aqc_add_rdma_qset_data *buf; 4931 struct ice_sched_node *parent; 4932 struct ice_hw *hw; 4933 u16 i, buf_size; 4934 int ret; 4935 4936 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4937 return -EIO; 4938 hw = pi->hw; 4939 4940 if (!ice_is_vsi_valid(hw, vsi_handle)) 4941 return -EINVAL; 4942 4943 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4944 buf = kzalloc(buf_size, GFP_KERNEL); 4945 if (!buf) 4946 return -ENOMEM; 4947 mutex_lock(&pi->sched_lock); 4948 4949 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4950 ICE_SCHED_NODE_OWNER_RDMA); 4951 if (!parent) { 4952 ret = -EINVAL; 4953 goto rdma_error_exit; 4954 } 4955 buf->parent_teid = parent->info.node_teid; 4956 node.parent_teid = parent->info.node_teid; 4957 4958 buf->num_qsets = cpu_to_le16(num_qsets); 4959 for (i = 0; i < num_qsets; i++) { 4960 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4961 buf->rdma_qsets[i].info.valid_sections = 4962 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4963 ICE_AQC_ELEM_VALID_EIR; 4964 buf->rdma_qsets[i].info.generic = 0; 4965 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4966 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4967 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4968 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4969 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4970 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4971 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4972 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4973 } 4974 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4975 if (ret) { 4976 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4977 goto rdma_error_exit; 4978 } 4979 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4980 for (i = 0; i < num_qsets; i++) { 4981 node.node_teid = buf->rdma_qsets[i].qset_teid; 4982 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4983 &node, NULL); 4984 if (ret) 4985 break; 4986 qset_teid[i] = le32_to_cpu(node.node_teid); 4987 } 4988 rdma_error_exit: 4989 mutex_unlock(&pi->sched_lock); 4990 kfree(buf); 4991 return ret; 4992 } 4993 4994 /** 4995 * ice_dis_vsi_rdma_qset - free RDMA resources 4996 * @pi: port_info struct 4997 * @count: number of RDMA Qsets to free 4998 * @qset_teid: TEID of Qset node 4999 * @q_id: list of queue IDs being disabled 5000 */ 5001 int 5002 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5003 u16 *q_id) 5004 { 5005 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5006 u16 qg_size = __struct_size(qg_list); 5007 struct ice_hw *hw; 5008 int status = 0; 5009 int i; 5010 5011 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5012 return -EIO; 5013 5014 hw = pi->hw; 5015 5016 mutex_lock(&pi->sched_lock); 5017 5018 for (i = 0; i < count; i++) { 5019 struct ice_sched_node *node; 5020 5021 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5022 if (!node) 5023 continue; 5024 5025 qg_list->parent_teid = node->info.parent_teid; 5026 qg_list->num_qs = 1; 5027 qg_list->q_id[0] = 5028 cpu_to_le16(q_id[i] | 5029 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5030 5031 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5032 ICE_NO_RESET, 0, NULL); 5033 if (status) 5034 break; 5035 5036 ice_free_sched_node(pi, node); 5037 } 5038 5039 mutex_unlock(&pi->sched_lock); 5040 return status; 5041 } 5042 5043 /** 5044 * ice_aq_get_cgu_abilities - get cgu abilities 5045 * @hw: pointer to the HW struct 5046 * @abilities: CGU abilities 5047 * 5048 * Get CGU abilities (0x0C61) 5049 * Return: 0 on success or negative value on failure. 5050 */ 5051 int 5052 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5053 struct ice_aqc_get_cgu_abilities *abilities) 5054 { 5055 struct ice_aq_desc desc; 5056 5057 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5058 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5059 } 5060 5061 /** 5062 * ice_aq_set_input_pin_cfg - set input pin config 5063 * @hw: pointer to the HW struct 5064 * @input_idx: Input index 5065 * @flags1: Input flags 5066 * @flags2: Input flags 5067 * @freq: Frequency in Hz 5068 * @phase_delay: Delay in ps 5069 * 5070 * Set CGU input config (0x0C62) 5071 * Return: 0 on success or negative value on failure. 5072 */ 5073 int 5074 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5075 u32 freq, s32 phase_delay) 5076 { 5077 struct ice_aqc_set_cgu_input_config *cmd; 5078 struct ice_aq_desc desc; 5079 5080 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5081 cmd = &desc.params.set_cgu_input_config; 5082 cmd->input_idx = input_idx; 5083 cmd->flags1 = flags1; 5084 cmd->flags2 = flags2; 5085 cmd->freq = cpu_to_le32(freq); 5086 cmd->phase_delay = cpu_to_le32(phase_delay); 5087 5088 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5089 } 5090 5091 /** 5092 * ice_aq_get_input_pin_cfg - get input pin config 5093 * @hw: pointer to the HW struct 5094 * @input_idx: Input index 5095 * @status: Pin status 5096 * @type: Pin type 5097 * @flags1: Input flags 5098 * @flags2: Input flags 5099 * @freq: Frequency in Hz 5100 * @phase_delay: Delay in ps 5101 * 5102 * Get CGU input config (0x0C63) 5103 * Return: 0 on success or negative value on failure. 5104 */ 5105 int 5106 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5107 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5108 { 5109 struct ice_aqc_get_cgu_input_config *cmd; 5110 struct ice_aq_desc desc; 5111 int ret; 5112 5113 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5114 cmd = &desc.params.get_cgu_input_config; 5115 cmd->input_idx = input_idx; 5116 5117 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5118 if (!ret) { 5119 if (status) 5120 *status = cmd->status; 5121 if (type) 5122 *type = cmd->type; 5123 if (flags1) 5124 *flags1 = cmd->flags1; 5125 if (flags2) 5126 *flags2 = cmd->flags2; 5127 if (freq) 5128 *freq = le32_to_cpu(cmd->freq); 5129 if (phase_delay) 5130 *phase_delay = le32_to_cpu(cmd->phase_delay); 5131 } 5132 5133 return ret; 5134 } 5135 5136 /** 5137 * ice_aq_set_output_pin_cfg - set output pin config 5138 * @hw: pointer to the HW struct 5139 * @output_idx: Output index 5140 * @flags: Output flags 5141 * @src_sel: Index of DPLL block 5142 * @freq: Output frequency 5143 * @phase_delay: Output phase compensation 5144 * 5145 * Set CGU output config (0x0C64) 5146 * Return: 0 on success or negative value on failure. 5147 */ 5148 int 5149 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5150 u8 src_sel, u32 freq, s32 phase_delay) 5151 { 5152 struct ice_aqc_set_cgu_output_config *cmd; 5153 struct ice_aq_desc desc; 5154 5155 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5156 cmd = &desc.params.set_cgu_output_config; 5157 cmd->output_idx = output_idx; 5158 cmd->flags = flags; 5159 cmd->src_sel = src_sel; 5160 cmd->freq = cpu_to_le32(freq); 5161 cmd->phase_delay = cpu_to_le32(phase_delay); 5162 5163 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5164 } 5165 5166 /** 5167 * ice_aq_get_output_pin_cfg - get output pin config 5168 * @hw: pointer to the HW struct 5169 * @output_idx: Output index 5170 * @flags: Output flags 5171 * @src_sel: Internal DPLL source 5172 * @freq: Output frequency 5173 * @src_freq: Source frequency 5174 * 5175 * Get CGU output config (0x0C65) 5176 * Return: 0 on success or negative value on failure. 5177 */ 5178 int 5179 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5180 u8 *src_sel, u32 *freq, u32 *src_freq) 5181 { 5182 struct ice_aqc_get_cgu_output_config *cmd; 5183 struct ice_aq_desc desc; 5184 int ret; 5185 5186 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5187 cmd = &desc.params.get_cgu_output_config; 5188 cmd->output_idx = output_idx; 5189 5190 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5191 if (!ret) { 5192 if (flags) 5193 *flags = cmd->flags; 5194 if (src_sel) 5195 *src_sel = cmd->src_sel; 5196 if (freq) 5197 *freq = le32_to_cpu(cmd->freq); 5198 if (src_freq) 5199 *src_freq = le32_to_cpu(cmd->src_freq); 5200 } 5201 5202 return ret; 5203 } 5204 5205 /** 5206 * ice_aq_get_cgu_dpll_status - get dpll status 5207 * @hw: pointer to the HW struct 5208 * @dpll_num: DPLL index 5209 * @ref_state: Reference clock state 5210 * @config: current DPLL config 5211 * @dpll_state: current DPLL state 5212 * @phase_offset: Phase offset in ns 5213 * @eec_mode: EEC_mode 5214 * 5215 * Get CGU DPLL status (0x0C66) 5216 * Return: 0 on success or negative value on failure. 5217 */ 5218 int 5219 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5220 u8 *dpll_state, u8 *config, s64 *phase_offset, 5221 u8 *eec_mode) 5222 { 5223 struct ice_aqc_get_cgu_dpll_status *cmd; 5224 struct ice_aq_desc desc; 5225 int status; 5226 5227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5228 cmd = &desc.params.get_cgu_dpll_status; 5229 cmd->dpll_num = dpll_num; 5230 5231 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5232 if (!status) { 5233 *ref_state = cmd->ref_state; 5234 *dpll_state = cmd->dpll_state; 5235 *config = cmd->config; 5236 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5237 *phase_offset <<= 32; 5238 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5239 *phase_offset = sign_extend64(*phase_offset, 47); 5240 *eec_mode = cmd->eec_mode; 5241 } 5242 5243 return status; 5244 } 5245 5246 /** 5247 * ice_aq_set_cgu_dpll_config - set dpll config 5248 * @hw: pointer to the HW struct 5249 * @dpll_num: DPLL index 5250 * @ref_state: Reference clock state 5251 * @config: DPLL config 5252 * @eec_mode: EEC mode 5253 * 5254 * Set CGU DPLL config (0x0C67) 5255 * Return: 0 on success or negative value on failure. 5256 */ 5257 int 5258 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5259 u8 config, u8 eec_mode) 5260 { 5261 struct ice_aqc_set_cgu_dpll_config *cmd; 5262 struct ice_aq_desc desc; 5263 5264 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5265 cmd = &desc.params.set_cgu_dpll_config; 5266 cmd->dpll_num = dpll_num; 5267 cmd->ref_state = ref_state; 5268 cmd->config = config; 5269 cmd->eec_mode = eec_mode; 5270 5271 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5272 } 5273 5274 /** 5275 * ice_aq_set_cgu_ref_prio - set input reference priority 5276 * @hw: pointer to the HW struct 5277 * @dpll_num: DPLL index 5278 * @ref_idx: Reference pin index 5279 * @ref_priority: Reference input priority 5280 * 5281 * Set CGU reference priority (0x0C68) 5282 * Return: 0 on success or negative value on failure. 5283 */ 5284 int 5285 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5286 u8 ref_priority) 5287 { 5288 struct ice_aqc_set_cgu_ref_prio *cmd; 5289 struct ice_aq_desc desc; 5290 5291 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5292 cmd = &desc.params.set_cgu_ref_prio; 5293 cmd->dpll_num = dpll_num; 5294 cmd->ref_idx = ref_idx; 5295 cmd->ref_priority = ref_priority; 5296 5297 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5298 } 5299 5300 /** 5301 * ice_aq_get_cgu_ref_prio - get input reference priority 5302 * @hw: pointer to the HW struct 5303 * @dpll_num: DPLL index 5304 * @ref_idx: Reference pin index 5305 * @ref_prio: Reference input priority 5306 * 5307 * Get CGU reference priority (0x0C69) 5308 * Return: 0 on success or negative value on failure. 5309 */ 5310 int 5311 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5312 u8 *ref_prio) 5313 { 5314 struct ice_aqc_get_cgu_ref_prio *cmd; 5315 struct ice_aq_desc desc; 5316 int status; 5317 5318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5319 cmd = &desc.params.get_cgu_ref_prio; 5320 cmd->dpll_num = dpll_num; 5321 cmd->ref_idx = ref_idx; 5322 5323 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5324 if (!status) 5325 *ref_prio = cmd->ref_priority; 5326 5327 return status; 5328 } 5329 5330 /** 5331 * ice_aq_get_cgu_info - get cgu info 5332 * @hw: pointer to the HW struct 5333 * @cgu_id: CGU ID 5334 * @cgu_cfg_ver: CGU config version 5335 * @cgu_fw_ver: CGU firmware version 5336 * 5337 * Get CGU info (0x0C6A) 5338 * Return: 0 on success or negative value on failure. 5339 */ 5340 int 5341 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5342 u32 *cgu_fw_ver) 5343 { 5344 struct ice_aqc_get_cgu_info *cmd; 5345 struct ice_aq_desc desc; 5346 int status; 5347 5348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5349 cmd = &desc.params.get_cgu_info; 5350 5351 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5352 if (!status) { 5353 *cgu_id = le32_to_cpu(cmd->cgu_id); 5354 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5355 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5356 } 5357 5358 return status; 5359 } 5360 5361 /** 5362 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5363 * @hw: pointer to the HW struct 5364 * @phy_output: PHY reference clock output pin 5365 * @enable: GPIO state to be applied 5366 * @freq: PHY output frequency 5367 * 5368 * Set phy recovered clock as reference (0x0630) 5369 * Return: 0 on success or negative value on failure. 5370 */ 5371 int 5372 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5373 u32 *freq) 5374 { 5375 struct ice_aqc_set_phy_rec_clk_out *cmd; 5376 struct ice_aq_desc desc; 5377 int status; 5378 5379 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5380 cmd = &desc.params.set_phy_rec_clk_out; 5381 cmd->phy_output = phy_output; 5382 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5383 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5384 cmd->freq = cpu_to_le32(*freq); 5385 5386 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5387 if (!status) 5388 *freq = le32_to_cpu(cmd->freq); 5389 5390 return status; 5391 } 5392 5393 /** 5394 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5395 * @hw: pointer to the HW struct 5396 * @phy_output: PHY reference clock output pin 5397 * @port_num: Port number 5398 * @flags: PHY flags 5399 * @node_handle: PHY output frequency 5400 * 5401 * Get PHY recovered clock output info (0x0631) 5402 * Return: 0 on success or negative value on failure. 5403 */ 5404 int 5405 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5406 u8 *flags, u16 *node_handle) 5407 { 5408 struct ice_aqc_get_phy_rec_clk_out *cmd; 5409 struct ice_aq_desc desc; 5410 int status; 5411 5412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5413 cmd = &desc.params.get_phy_rec_clk_out; 5414 cmd->phy_output = *phy_output; 5415 5416 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5417 if (!status) { 5418 *phy_output = cmd->phy_output; 5419 if (port_num) 5420 *port_num = cmd->port_num; 5421 if (flags) 5422 *flags = cmd->flags; 5423 if (node_handle) 5424 *node_handle = le16_to_cpu(cmd->node_handle); 5425 } 5426 5427 return status; 5428 } 5429 5430 /** 5431 * ice_aq_get_sensor_reading 5432 * @hw: pointer to the HW struct 5433 * @data: pointer to data to be read from the sensor 5434 * 5435 * Get sensor reading (0x0632) 5436 */ 5437 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5438 struct ice_aqc_get_sensor_reading_resp *data) 5439 { 5440 struct ice_aqc_get_sensor_reading *cmd; 5441 struct ice_aq_desc desc; 5442 int status; 5443 5444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5445 cmd = &desc.params.get_sensor_reading; 5446 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5447 #define ICE_INTERNAL_TEMP_SENSOR 0 5448 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5449 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5450 5451 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5452 if (!status) 5453 memcpy(data, &desc.params.get_sensor_reading_resp, 5454 sizeof(*data)); 5455 5456 return status; 5457 } 5458 5459 /** 5460 * ice_replay_pre_init - replay pre initialization 5461 * @hw: pointer to the HW struct 5462 * 5463 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5464 */ 5465 static int ice_replay_pre_init(struct ice_hw *hw) 5466 { 5467 struct ice_switch_info *sw = hw->switch_info; 5468 u8 i; 5469 5470 /* Delete old entries from replay filter list head if there is any */ 5471 ice_rm_all_sw_replay_rule_info(hw); 5472 /* In start of replay, move entries into replay_rules list, it 5473 * will allow adding rules entries back to filt_rules list, 5474 * which is operational list. 5475 */ 5476 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5477 list_replace_init(&sw->recp_list[i].filt_rules, 5478 &sw->recp_list[i].filt_replay_rules); 5479 ice_sched_replay_agg_vsi_preinit(hw); 5480 5481 return 0; 5482 } 5483 5484 /** 5485 * ice_replay_vsi - replay VSI configuration 5486 * @hw: pointer to the HW struct 5487 * @vsi_handle: driver VSI handle 5488 * 5489 * Restore all VSI configuration after reset. It is required to call this 5490 * function with main VSI first. 5491 */ 5492 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5493 { 5494 int status; 5495 5496 if (!ice_is_vsi_valid(hw, vsi_handle)) 5497 return -EINVAL; 5498 5499 /* Replay pre-initialization if there is any */ 5500 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5501 status = ice_replay_pre_init(hw); 5502 if (status) 5503 return status; 5504 } 5505 /* Replay per VSI all RSS configurations */ 5506 status = ice_replay_rss_cfg(hw, vsi_handle); 5507 if (status) 5508 return status; 5509 /* Replay per VSI all filters */ 5510 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5511 if (!status) 5512 status = ice_replay_vsi_agg(hw, vsi_handle); 5513 return status; 5514 } 5515 5516 /** 5517 * ice_replay_post - post replay configuration cleanup 5518 * @hw: pointer to the HW struct 5519 * 5520 * Post replay cleanup. 5521 */ 5522 void ice_replay_post(struct ice_hw *hw) 5523 { 5524 /* Delete old entries from replay filter list head */ 5525 ice_rm_all_sw_replay_rule_info(hw); 5526 ice_sched_replay_agg(hw); 5527 } 5528 5529 /** 5530 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5531 * @hw: ptr to the hardware info 5532 * @reg: offset of 64 bit HW register to read from 5533 * @prev_stat_loaded: bool to specify if previous stats are loaded 5534 * @prev_stat: ptr to previous loaded stat value 5535 * @cur_stat: ptr to current stat value 5536 */ 5537 void 5538 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5539 u64 *prev_stat, u64 *cur_stat) 5540 { 5541 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5542 5543 /* device stats are not reset at PFR, they likely will not be zeroed 5544 * when the driver starts. Thus, save the value from the first read 5545 * without adding to the statistic value so that we report stats which 5546 * count up from zero. 5547 */ 5548 if (!prev_stat_loaded) { 5549 *prev_stat = new_data; 5550 return; 5551 } 5552 5553 /* Calculate the difference between the new and old values, and then 5554 * add it to the software stat value. 5555 */ 5556 if (new_data >= *prev_stat) 5557 *cur_stat += new_data - *prev_stat; 5558 else 5559 /* to manage the potential roll-over */ 5560 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5561 5562 /* Update the previously stored value to prepare for next read */ 5563 *prev_stat = new_data; 5564 } 5565 5566 /** 5567 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5568 * @hw: ptr to the hardware info 5569 * @reg: offset of HW register to read from 5570 * @prev_stat_loaded: bool to specify if previous stats are loaded 5571 * @prev_stat: ptr to previous loaded stat value 5572 * @cur_stat: ptr to current stat value 5573 */ 5574 void 5575 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5576 u64 *prev_stat, u64 *cur_stat) 5577 { 5578 u32 new_data; 5579 5580 new_data = rd32(hw, reg); 5581 5582 /* device stats are not reset at PFR, they likely will not be zeroed 5583 * when the driver starts. Thus, save the value from the first read 5584 * without adding to the statistic value so that we report stats which 5585 * count up from zero. 5586 */ 5587 if (!prev_stat_loaded) { 5588 *prev_stat = new_data; 5589 return; 5590 } 5591 5592 /* Calculate the difference between the new and old values, and then 5593 * add it to the software stat value. 5594 */ 5595 if (new_data >= *prev_stat) 5596 *cur_stat += new_data - *prev_stat; 5597 else 5598 /* to manage the potential roll-over */ 5599 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5600 5601 /* Update the previously stored value to prepare for next read */ 5602 *prev_stat = new_data; 5603 } 5604 5605 /** 5606 * ice_sched_query_elem - query element information from HW 5607 * @hw: pointer to the HW struct 5608 * @node_teid: node TEID to be queried 5609 * @buf: buffer to element information 5610 * 5611 * This function queries HW element information 5612 */ 5613 int 5614 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5615 struct ice_aqc_txsched_elem_data *buf) 5616 { 5617 u16 buf_size, num_elem_ret = 0; 5618 int status; 5619 5620 buf_size = sizeof(*buf); 5621 memset(buf, 0, buf_size); 5622 buf->node_teid = cpu_to_le32(node_teid); 5623 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5624 NULL); 5625 if (status || num_elem_ret != 1) 5626 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5627 return status; 5628 } 5629 5630 /** 5631 * ice_aq_read_i2c 5632 * @hw: pointer to the hw struct 5633 * @topo_addr: topology address for a device to communicate with 5634 * @bus_addr: 7-bit I2C bus address 5635 * @addr: I2C memory address (I2C offset) with up to 16 bits 5636 * @params: I2C parameters: bit [7] - Repeated start, 5637 * bits [6:5] data offset size, 5638 * bit [4] - I2C address type, 5639 * bits [3:0] - data size to read (0-16 bytes) 5640 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5641 * @cd: pointer to command details structure or NULL 5642 * 5643 * Read I2C (0x06E2) 5644 */ 5645 int 5646 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5647 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5648 struct ice_sq_cd *cd) 5649 { 5650 struct ice_aq_desc desc = { 0 }; 5651 struct ice_aqc_i2c *cmd; 5652 u8 data_size; 5653 int status; 5654 5655 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5656 cmd = &desc.params.read_write_i2c; 5657 5658 if (!data) 5659 return -EINVAL; 5660 5661 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5662 5663 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5664 cmd->topo_addr = topo_addr; 5665 cmd->i2c_params = params; 5666 cmd->i2c_addr = addr; 5667 5668 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5669 if (!status) { 5670 struct ice_aqc_read_i2c_resp *resp; 5671 u8 i; 5672 5673 resp = &desc.params.read_i2c_resp; 5674 for (i = 0; i < data_size; i++) { 5675 *data = resp->i2c_data[i]; 5676 data++; 5677 } 5678 } 5679 5680 return status; 5681 } 5682 5683 /** 5684 * ice_aq_write_i2c 5685 * @hw: pointer to the hw struct 5686 * @topo_addr: topology address for a device to communicate with 5687 * @bus_addr: 7-bit I2C bus address 5688 * @addr: I2C memory address (I2C offset) with up to 16 bits 5689 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5690 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5691 * @cd: pointer to command details structure or NULL 5692 * 5693 * Write I2C (0x06E3) 5694 * 5695 * * Return: 5696 * * 0 - Successful write to the i2c device 5697 * * -EINVAL - Data size greater than 4 bytes 5698 * * -EIO - FW error 5699 */ 5700 int 5701 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5702 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5703 struct ice_sq_cd *cd) 5704 { 5705 struct ice_aq_desc desc = { 0 }; 5706 struct ice_aqc_i2c *cmd; 5707 u8 data_size; 5708 5709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5710 cmd = &desc.params.read_write_i2c; 5711 5712 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5713 5714 /* data_size limited to 4 */ 5715 if (data_size > 4) 5716 return -EINVAL; 5717 5718 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5719 cmd->topo_addr = topo_addr; 5720 cmd->i2c_params = params; 5721 cmd->i2c_addr = addr; 5722 5723 memcpy(cmd->i2c_data, data, data_size); 5724 5725 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5726 } 5727 5728 /** 5729 * ice_aq_set_gpio 5730 * @hw: pointer to the hw struct 5731 * @gpio_ctrl_handle: GPIO controller node handle 5732 * @pin_idx: IO Number of the GPIO that needs to be set 5733 * @value: SW provide IO value to set in the LSB 5734 * @cd: pointer to command details structure or NULL 5735 * 5736 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5737 */ 5738 int 5739 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5740 struct ice_sq_cd *cd) 5741 { 5742 struct ice_aqc_gpio *cmd; 5743 struct ice_aq_desc desc; 5744 5745 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5746 cmd = &desc.params.read_write_gpio; 5747 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5748 cmd->gpio_num = pin_idx; 5749 cmd->gpio_val = value ? 1 : 0; 5750 5751 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5752 } 5753 5754 /** 5755 * ice_aq_get_gpio 5756 * @hw: pointer to the hw struct 5757 * @gpio_ctrl_handle: GPIO controller node handle 5758 * @pin_idx: IO Number of the GPIO that needs to be set 5759 * @value: IO value read 5760 * @cd: pointer to command details structure or NULL 5761 * 5762 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5763 * the topology 5764 */ 5765 int 5766 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5767 bool *value, struct ice_sq_cd *cd) 5768 { 5769 struct ice_aqc_gpio *cmd; 5770 struct ice_aq_desc desc; 5771 int status; 5772 5773 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5774 cmd = &desc.params.read_write_gpio; 5775 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5776 cmd->gpio_num = pin_idx; 5777 5778 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5779 if (status) 5780 return status; 5781 5782 *value = !!cmd->gpio_val; 5783 return 0; 5784 } 5785 5786 /** 5787 * ice_is_fw_api_min_ver 5788 * @hw: pointer to the hardware structure 5789 * @maj: major version 5790 * @min: minor version 5791 * @patch: patch version 5792 * 5793 * Checks if the firmware API is minimum version 5794 */ 5795 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5796 { 5797 if (hw->api_maj_ver == maj) { 5798 if (hw->api_min_ver > min) 5799 return true; 5800 if (hw->api_min_ver == min && hw->api_patch >= patch) 5801 return true; 5802 } else if (hw->api_maj_ver > maj) { 5803 return true; 5804 } 5805 5806 return false; 5807 } 5808 5809 /** 5810 * ice_fw_supports_link_override 5811 * @hw: pointer to the hardware structure 5812 * 5813 * Checks if the firmware supports link override 5814 */ 5815 bool ice_fw_supports_link_override(struct ice_hw *hw) 5816 { 5817 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5818 ICE_FW_API_LINK_OVERRIDE_MIN, 5819 ICE_FW_API_LINK_OVERRIDE_PATCH); 5820 } 5821 5822 /** 5823 * ice_get_link_default_override 5824 * @ldo: pointer to the link default override struct 5825 * @pi: pointer to the port info struct 5826 * 5827 * Gets the link default override for a port 5828 */ 5829 int 5830 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5831 struct ice_port_info *pi) 5832 { 5833 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5834 struct ice_hw *hw = pi->hw; 5835 int status; 5836 5837 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5838 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5839 if (status) { 5840 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5841 return status; 5842 } 5843 5844 /* Each port has its own config; calculate for our port */ 5845 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5846 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5847 5848 /* link options first */ 5849 status = ice_read_sr_word(hw, tlv_start, &buf); 5850 if (status) { 5851 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5852 return status; 5853 } 5854 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 5855 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5856 ICE_LINK_OVERRIDE_PHY_CFG_S; 5857 5858 /* link PHY config */ 5859 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5860 status = ice_read_sr_word(hw, offset, &buf); 5861 if (status) { 5862 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5863 return status; 5864 } 5865 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5866 5867 /* PHY types low */ 5868 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5869 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5870 status = ice_read_sr_word(hw, (offset + i), &buf); 5871 if (status) { 5872 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5873 return status; 5874 } 5875 /* shift 16 bits at a time to fill 64 bits */ 5876 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5877 } 5878 5879 /* PHY types high */ 5880 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5881 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5882 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5883 status = ice_read_sr_word(hw, (offset + i), &buf); 5884 if (status) { 5885 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5886 return status; 5887 } 5888 /* shift 16 bits at a time to fill 64 bits */ 5889 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5890 } 5891 5892 return status; 5893 } 5894 5895 /** 5896 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5897 * @caps: get PHY capability data 5898 */ 5899 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5900 { 5901 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5902 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5903 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5904 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5905 return true; 5906 5907 return false; 5908 } 5909 5910 /** 5911 * ice_aq_set_lldp_mib - Set the LLDP MIB 5912 * @hw: pointer to the HW struct 5913 * @mib_type: Local, Remote or both Local and Remote MIBs 5914 * @buf: pointer to the caller-supplied buffer to store the MIB block 5915 * @buf_size: size of the buffer (in bytes) 5916 * @cd: pointer to command details structure or NULL 5917 * 5918 * Set the LLDP MIB. (0x0A08) 5919 */ 5920 int 5921 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5922 struct ice_sq_cd *cd) 5923 { 5924 struct ice_aqc_lldp_set_local_mib *cmd; 5925 struct ice_aq_desc desc; 5926 5927 cmd = &desc.params.lldp_set_mib; 5928 5929 if (buf_size == 0 || !buf) 5930 return -EINVAL; 5931 5932 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5933 5934 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5935 desc.datalen = cpu_to_le16(buf_size); 5936 5937 cmd->type = mib_type; 5938 cmd->length = cpu_to_le16(buf_size); 5939 5940 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5941 } 5942 5943 /** 5944 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5945 * @hw: pointer to HW struct 5946 */ 5947 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5948 { 5949 if (hw->mac_type != ICE_MAC_E810) 5950 return false; 5951 5952 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5953 ICE_FW_API_LLDP_FLTR_MIN, 5954 ICE_FW_API_LLDP_FLTR_PATCH); 5955 } 5956 5957 /** 5958 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5959 * @hw: pointer to HW struct 5960 * @vsi_num: absolute HW index for VSI 5961 * @add: boolean for if adding or removing a filter 5962 */ 5963 int 5964 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5965 { 5966 struct ice_aqc_lldp_filter_ctrl *cmd; 5967 struct ice_aq_desc desc; 5968 5969 cmd = &desc.params.lldp_filter_ctrl; 5970 5971 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5972 5973 if (add) 5974 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5975 else 5976 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5977 5978 cmd->vsi_num = cpu_to_le16(vsi_num); 5979 5980 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5981 } 5982 5983 /** 5984 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 5985 * @hw: pointer to HW struct 5986 */ 5987 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 5988 { 5989 struct ice_aq_desc desc; 5990 5991 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 5992 5993 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5994 } 5995 5996 /** 5997 * ice_fw_supports_report_dflt_cfg 5998 * @hw: pointer to the hardware structure 5999 * 6000 * Checks if the firmware supports report default configuration 6001 */ 6002 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6003 { 6004 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6005 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6006 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6007 } 6008 6009 /* each of the indexes into the following array match the speed of a return 6010 * value from the list of AQ returned speeds like the range: 6011 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6012 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6013 * array. The array is defined as 15 elements long because the link_speed 6014 * returned by the firmware is a 16 bit * value, but is indexed 6015 * by [fls(speed) - 1] 6016 */ 6017 static const u32 ice_aq_to_link_speed[] = { 6018 SPEED_10, /* BIT(0) */ 6019 SPEED_100, 6020 SPEED_1000, 6021 SPEED_2500, 6022 SPEED_5000, 6023 SPEED_10000, 6024 SPEED_20000, 6025 SPEED_25000, 6026 SPEED_40000, 6027 SPEED_50000, 6028 SPEED_100000, /* BIT(10) */ 6029 SPEED_200000, 6030 }; 6031 6032 /** 6033 * ice_get_link_speed - get integer speed from table 6034 * @index: array index from fls(aq speed) - 1 6035 * 6036 * Returns: u32 value containing integer speed 6037 */ 6038 u32 ice_get_link_speed(u16 index) 6039 { 6040 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6041 return 0; 6042 6043 return ice_aq_to_link_speed[index]; 6044 } 6045