1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 hw->mac_type = ICE_MAC_E830; 175 break; 176 default: 177 hw->mac_type = ICE_MAC_UNKNOWN; 178 break; 179 } 180 181 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 182 return 0; 183 } 184 185 /** 186 * ice_is_generic_mac - check if device's mac_type is generic 187 * @hw: pointer to the hardware structure 188 * 189 * Return: true if mac_type is generic (with SBQ support), false if not 190 */ 191 bool ice_is_generic_mac(struct ice_hw *hw) 192 { 193 return (hw->mac_type == ICE_MAC_GENERIC || 194 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 195 } 196 197 /** 198 * ice_is_e810 199 * @hw: pointer to the hardware structure 200 * 201 * returns true if the device is E810 based, false if not. 202 */ 203 bool ice_is_e810(struct ice_hw *hw) 204 { 205 return hw->mac_type == ICE_MAC_E810; 206 } 207 208 /** 209 * ice_is_e810t 210 * @hw: pointer to the hardware structure 211 * 212 * returns true if the device is E810T based, false if not. 213 */ 214 bool ice_is_e810t(struct ice_hw *hw) 215 { 216 switch (hw->device_id) { 217 case ICE_DEV_ID_E810C_SFP: 218 switch (hw->subsystem_device_id) { 219 case ICE_SUBDEV_ID_E810T: 220 case ICE_SUBDEV_ID_E810T2: 221 case ICE_SUBDEV_ID_E810T3: 222 case ICE_SUBDEV_ID_E810T4: 223 case ICE_SUBDEV_ID_E810T6: 224 case ICE_SUBDEV_ID_E810T7: 225 return true; 226 } 227 break; 228 case ICE_DEV_ID_E810C_QSFP: 229 switch (hw->subsystem_device_id) { 230 case ICE_SUBDEV_ID_E810T2: 231 case ICE_SUBDEV_ID_E810T3: 232 case ICE_SUBDEV_ID_E810T5: 233 return true; 234 } 235 break; 236 default: 237 break; 238 } 239 240 return false; 241 } 242 243 /** 244 * ice_is_e822 - Check if a device is E822 family device 245 * @hw: pointer to the hardware structure 246 * 247 * Return: true if the device is E822 based, false if not. 248 */ 249 bool ice_is_e822(struct ice_hw *hw) 250 { 251 switch (hw->device_id) { 252 case ICE_DEV_ID_E822C_BACKPLANE: 253 case ICE_DEV_ID_E822C_QSFP: 254 case ICE_DEV_ID_E822C_SFP: 255 case ICE_DEV_ID_E822C_10G_BASE_T: 256 case ICE_DEV_ID_E822C_SGMII: 257 case ICE_DEV_ID_E822L_BACKPLANE: 258 case ICE_DEV_ID_E822L_SFP: 259 case ICE_DEV_ID_E822L_10G_BASE_T: 260 case ICE_DEV_ID_E822L_SGMII: 261 return true; 262 default: 263 return false; 264 } 265 } 266 267 /** 268 * ice_is_e823 269 * @hw: pointer to the hardware structure 270 * 271 * returns true if the device is E823-L or E823-C based, false if not. 272 */ 273 bool ice_is_e823(struct ice_hw *hw) 274 { 275 switch (hw->device_id) { 276 case ICE_DEV_ID_E823L_BACKPLANE: 277 case ICE_DEV_ID_E823L_SFP: 278 case ICE_DEV_ID_E823L_10G_BASE_T: 279 case ICE_DEV_ID_E823L_1GBE: 280 case ICE_DEV_ID_E823L_QSFP: 281 case ICE_DEV_ID_E823C_BACKPLANE: 282 case ICE_DEV_ID_E823C_QSFP: 283 case ICE_DEV_ID_E823C_SFP: 284 case ICE_DEV_ID_E823C_10G_BASE_T: 285 case ICE_DEV_ID_E823C_SGMII: 286 return true; 287 default: 288 return false; 289 } 290 } 291 292 /** 293 * ice_is_e825c - Check if a device is E825C family device 294 * @hw: pointer to the hardware structure 295 * 296 * Return: true if the device is E825-C based, false if not. 297 */ 298 bool ice_is_e825c(struct ice_hw *hw) 299 { 300 switch (hw->device_id) { 301 case ICE_DEV_ID_E825C_BACKPLANE: 302 case ICE_DEV_ID_E825C_QSFP: 303 case ICE_DEV_ID_E825C_SFP: 304 case ICE_DEV_ID_E825C_SGMII: 305 return true; 306 default: 307 return false; 308 } 309 } 310 311 /** 312 * ice_clear_pf_cfg - Clear PF configuration 313 * @hw: pointer to the hardware structure 314 * 315 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 316 * configuration, flow director filters, etc.). 317 */ 318 int ice_clear_pf_cfg(struct ice_hw *hw) 319 { 320 struct ice_aq_desc desc; 321 322 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 323 324 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 325 } 326 327 /** 328 * ice_aq_manage_mac_read - manage MAC address read command 329 * @hw: pointer to the HW struct 330 * @buf: a virtual buffer to hold the manage MAC read response 331 * @buf_size: Size of the virtual buffer 332 * @cd: pointer to command details structure or NULL 333 * 334 * This function is used to return per PF station MAC address (0x0107). 335 * NOTE: Upon successful completion of this command, MAC address information 336 * is returned in user specified buffer. Please interpret user specified 337 * buffer as "manage_mac_read" response. 338 * Response such as various MAC addresses are stored in HW struct (port.mac) 339 * ice_discover_dev_caps is expected to be called before this function is 340 * called. 341 */ 342 static int 343 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 344 struct ice_sq_cd *cd) 345 { 346 struct ice_aqc_manage_mac_read_resp *resp; 347 struct ice_aqc_manage_mac_read *cmd; 348 struct ice_aq_desc desc; 349 int status; 350 u16 flags; 351 u8 i; 352 353 cmd = &desc.params.mac_read; 354 355 if (buf_size < sizeof(*resp)) 356 return -EINVAL; 357 358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 359 360 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 361 if (status) 362 return status; 363 364 resp = buf; 365 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 366 367 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 368 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 369 return -EIO; 370 } 371 372 /* A single port can report up to two (LAN and WoL) addresses */ 373 for (i = 0; i < cmd->num_addr; i++) 374 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 375 ether_addr_copy(hw->port_info->mac.lan_addr, 376 resp[i].mac_addr); 377 ether_addr_copy(hw->port_info->mac.perm_addr, 378 resp[i].mac_addr); 379 break; 380 } 381 382 return 0; 383 } 384 385 /** 386 * ice_aq_get_phy_caps - returns PHY capabilities 387 * @pi: port information structure 388 * @qual_mods: report qualified modules 389 * @report_mode: report mode capabilities 390 * @pcaps: structure for PHY capabilities to be filled 391 * @cd: pointer to command details structure or NULL 392 * 393 * Returns the various PHY capabilities supported on the Port (0x0600) 394 */ 395 int 396 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 397 struct ice_aqc_get_phy_caps_data *pcaps, 398 struct ice_sq_cd *cd) 399 { 400 struct ice_aqc_get_phy_caps *cmd; 401 u16 pcaps_size = sizeof(*pcaps); 402 struct ice_aq_desc desc; 403 const char *prefix; 404 struct ice_hw *hw; 405 int status; 406 407 cmd = &desc.params.get_phy; 408 409 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 410 return -EINVAL; 411 hw = pi->hw; 412 413 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 414 !ice_fw_supports_report_dflt_cfg(hw)) 415 return -EINVAL; 416 417 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 418 419 if (qual_mods) 420 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 421 422 cmd->param0 |= cpu_to_le16(report_mode); 423 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 424 425 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 426 427 switch (report_mode) { 428 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 429 prefix = "phy_caps_media"; 430 break; 431 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 432 prefix = "phy_caps_no_media"; 433 break; 434 case ICE_AQC_REPORT_ACTIVE_CFG: 435 prefix = "phy_caps_active"; 436 break; 437 case ICE_AQC_REPORT_DFLT_CFG: 438 prefix = "phy_caps_default"; 439 break; 440 default: 441 prefix = "phy_caps_invalid"; 442 } 443 444 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 445 le64_to_cpu(pcaps->phy_type_high), prefix); 446 447 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 448 prefix, report_mode); 449 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 450 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 451 pcaps->low_power_ctrl_an); 452 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 453 pcaps->eee_cap); 454 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 455 pcaps->eeer_value); 456 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 457 pcaps->link_fec_options); 458 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 459 prefix, pcaps->module_compliance_enforcement); 460 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 461 prefix, pcaps->extended_compliance_code); 462 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 463 pcaps->module_type[0]); 464 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 465 pcaps->module_type[1]); 466 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 467 pcaps->module_type[2]); 468 469 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 470 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 471 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 472 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 473 sizeof(pi->phy.link_info.module_type)); 474 } 475 476 return status; 477 } 478 479 /** 480 * ice_aq_get_link_topo_handle - get link topology node return status 481 * @pi: port information structure 482 * @node_type: requested node type 483 * @cd: pointer to command details structure or NULL 484 * 485 * Get link topology node return status for specified node type (0x06E0) 486 * 487 * Node type cage can be used to determine if cage is present. If AQC 488 * returns error (ENOENT), then no cage present. If no cage present, then 489 * connection type is backplane or BASE-T. 490 */ 491 static int 492 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 493 struct ice_sq_cd *cd) 494 { 495 struct ice_aqc_get_link_topo *cmd; 496 struct ice_aq_desc desc; 497 498 cmd = &desc.params.get_link_topo; 499 500 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 501 502 cmd->addr.topo_params.node_type_ctx = 503 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 504 ICE_AQC_LINK_TOPO_NODE_CTX_S); 505 506 /* set node type */ 507 cmd->addr.topo_params.node_type_ctx |= 508 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 509 510 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 511 } 512 513 /** 514 * ice_aq_get_netlist_node 515 * @hw: pointer to the hw struct 516 * @cmd: get_link_topo AQ structure 517 * @node_part_number: output node part number if node found 518 * @node_handle: output node handle parameter if node found 519 * 520 * Get netlist node handle. 521 */ 522 int 523 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 524 u8 *node_part_number, u16 *node_handle) 525 { 526 struct ice_aq_desc desc; 527 528 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 529 desc.params.get_link_topo = *cmd; 530 531 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 532 return -EINTR; 533 534 if (node_handle) 535 *node_handle = 536 le16_to_cpu(desc.params.get_link_topo.addr.handle); 537 if (node_part_number) 538 *node_part_number = desc.params.get_link_topo.node_part_num; 539 540 return 0; 541 } 542 543 /** 544 * ice_find_netlist_node 545 * @hw: pointer to the hw struct 546 * @node_type: type of netlist node to look for 547 * @ctx: context of the search 548 * @node_part_number: node part number to look for 549 * @node_handle: output parameter if node found - optional 550 * 551 * Scan the netlist for a node handle of the given node type and part number. 552 * 553 * If node_handle is non-NULL it will be modified on function exit. It is only 554 * valid if the function returns zero, and should be ignored on any non-zero 555 * return value. 556 * 557 * Return: 558 * * 0 if the node is found, 559 * * -ENOENT if no handle was found, 560 * * negative error code on failure to access the AQ. 561 */ 562 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 563 u8 node_part_number, u16 *node_handle) 564 { 565 u8 idx; 566 567 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 568 struct ice_aqc_get_link_topo cmd = {}; 569 u8 rec_node_part_number; 570 int status; 571 572 cmd.addr.topo_params.node_type_ctx = 573 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 574 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 575 cmd.addr.topo_params.index = idx; 576 577 status = ice_aq_get_netlist_node(hw, &cmd, 578 &rec_node_part_number, 579 node_handle); 580 if (status) 581 return status; 582 583 if (rec_node_part_number == node_part_number) 584 return 0; 585 } 586 587 return -ENOENT; 588 } 589 590 /** 591 * ice_is_media_cage_present 592 * @pi: port information structure 593 * 594 * Returns true if media cage is present, else false. If no cage, then 595 * media type is backplane or BASE-T. 596 */ 597 static bool ice_is_media_cage_present(struct ice_port_info *pi) 598 { 599 /* Node type cage can be used to determine if cage is present. If AQC 600 * returns error (ENOENT), then no cage present. If no cage present then 601 * connection type is backplane or BASE-T. 602 */ 603 return !ice_aq_get_link_topo_handle(pi, 604 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 605 NULL); 606 } 607 608 /** 609 * ice_get_media_type - Gets media type 610 * @pi: port information structure 611 */ 612 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 613 { 614 struct ice_link_status *hw_link_info; 615 616 if (!pi) 617 return ICE_MEDIA_UNKNOWN; 618 619 hw_link_info = &pi->phy.link_info; 620 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 621 /* If more than one media type is selected, report unknown */ 622 return ICE_MEDIA_UNKNOWN; 623 624 if (hw_link_info->phy_type_low) { 625 /* 1G SGMII is a special case where some DA cable PHYs 626 * may show this as an option when it really shouldn't 627 * be since SGMII is meant to be between a MAC and a PHY 628 * in a backplane. Try to detect this case and handle it 629 */ 630 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 631 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 632 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 633 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 634 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 635 return ICE_MEDIA_DA; 636 637 switch (hw_link_info->phy_type_low) { 638 case ICE_PHY_TYPE_LOW_1000BASE_SX: 639 case ICE_PHY_TYPE_LOW_1000BASE_LX: 640 case ICE_PHY_TYPE_LOW_10GBASE_SR: 641 case ICE_PHY_TYPE_LOW_10GBASE_LR: 642 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 643 case ICE_PHY_TYPE_LOW_25GBASE_SR: 644 case ICE_PHY_TYPE_LOW_25GBASE_LR: 645 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 646 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 647 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 648 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 649 case ICE_PHY_TYPE_LOW_50GBASE_SR: 650 case ICE_PHY_TYPE_LOW_50GBASE_FR: 651 case ICE_PHY_TYPE_LOW_50GBASE_LR: 652 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 653 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 654 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 655 case ICE_PHY_TYPE_LOW_100GBASE_DR: 656 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 657 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 658 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 659 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 660 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 661 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 662 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 663 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 664 return ICE_MEDIA_FIBER; 665 case ICE_PHY_TYPE_LOW_100BASE_TX: 666 case ICE_PHY_TYPE_LOW_1000BASE_T: 667 case ICE_PHY_TYPE_LOW_2500BASE_T: 668 case ICE_PHY_TYPE_LOW_5GBASE_T: 669 case ICE_PHY_TYPE_LOW_10GBASE_T: 670 case ICE_PHY_TYPE_LOW_25GBASE_T: 671 return ICE_MEDIA_BASET; 672 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 673 case ICE_PHY_TYPE_LOW_25GBASE_CR: 674 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 675 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 676 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 677 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 678 case ICE_PHY_TYPE_LOW_50GBASE_CP: 679 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 680 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 681 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 682 return ICE_MEDIA_DA; 683 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 684 case ICE_PHY_TYPE_LOW_40G_XLAUI: 685 case ICE_PHY_TYPE_LOW_50G_LAUI2: 686 case ICE_PHY_TYPE_LOW_50G_AUI2: 687 case ICE_PHY_TYPE_LOW_50G_AUI1: 688 case ICE_PHY_TYPE_LOW_100G_AUI4: 689 case ICE_PHY_TYPE_LOW_100G_CAUI4: 690 if (ice_is_media_cage_present(pi)) 691 return ICE_MEDIA_DA; 692 fallthrough; 693 case ICE_PHY_TYPE_LOW_1000BASE_KX: 694 case ICE_PHY_TYPE_LOW_2500BASE_KX: 695 case ICE_PHY_TYPE_LOW_2500BASE_X: 696 case ICE_PHY_TYPE_LOW_5GBASE_KR: 697 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 698 case ICE_PHY_TYPE_LOW_25GBASE_KR: 699 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 700 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 701 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 702 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 703 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 704 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 705 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 706 return ICE_MEDIA_BACKPLANE; 707 } 708 } else { 709 switch (hw_link_info->phy_type_high) { 710 case ICE_PHY_TYPE_HIGH_100G_AUI2: 711 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 712 if (ice_is_media_cage_present(pi)) 713 return ICE_MEDIA_DA; 714 fallthrough; 715 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 716 return ICE_MEDIA_BACKPLANE; 717 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 718 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 719 return ICE_MEDIA_FIBER; 720 } 721 } 722 return ICE_MEDIA_UNKNOWN; 723 } 724 725 /** 726 * ice_get_link_status_datalen 727 * @hw: pointer to the HW struct 728 * 729 * Returns datalength for the Get Link Status AQ command, which is bigger for 730 * newer adapter families handled by ice driver. 731 */ 732 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 733 { 734 switch (hw->mac_type) { 735 case ICE_MAC_E830: 736 return ICE_AQC_LS_DATA_SIZE_V2; 737 case ICE_MAC_E810: 738 default: 739 return ICE_AQC_LS_DATA_SIZE_V1; 740 } 741 } 742 743 /** 744 * ice_aq_get_link_info 745 * @pi: port information structure 746 * @ena_lse: enable/disable LinkStatusEvent reporting 747 * @link: pointer to link status structure - optional 748 * @cd: pointer to command details structure or NULL 749 * 750 * Get Link Status (0x607). Returns the link status of the adapter. 751 */ 752 int 753 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 754 struct ice_link_status *link, struct ice_sq_cd *cd) 755 { 756 struct ice_aqc_get_link_status_data link_data = { 0 }; 757 struct ice_aqc_get_link_status *resp; 758 struct ice_link_status *li_old, *li; 759 enum ice_media_type *hw_media_type; 760 struct ice_fc_info *hw_fc_info; 761 bool tx_pause, rx_pause; 762 struct ice_aq_desc desc; 763 struct ice_hw *hw; 764 u16 cmd_flags; 765 int status; 766 767 if (!pi) 768 return -EINVAL; 769 hw = pi->hw; 770 li_old = &pi->phy.link_info_old; 771 hw_media_type = &pi->phy.media_type; 772 li = &pi->phy.link_info; 773 hw_fc_info = &pi->fc; 774 775 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 776 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 777 resp = &desc.params.get_link_status; 778 resp->cmd_flags = cpu_to_le16(cmd_flags); 779 resp->lport_num = pi->lport; 780 781 status = ice_aq_send_cmd(hw, &desc, &link_data, 782 ice_get_link_status_datalen(hw), cd); 783 if (status) 784 return status; 785 786 /* save off old link status information */ 787 *li_old = *li; 788 789 /* update current link status information */ 790 li->link_speed = le16_to_cpu(link_data.link_speed); 791 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 792 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 793 *hw_media_type = ice_get_media_type(pi); 794 li->link_info = link_data.link_info; 795 li->link_cfg_err = link_data.link_cfg_err; 796 li->an_info = link_data.an_info; 797 li->ext_info = link_data.ext_info; 798 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 799 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 800 li->topo_media_conflict = link_data.topo_media_conflict; 801 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 802 ICE_AQ_CFG_PACING_TYPE_M); 803 804 /* update fc info */ 805 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 806 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 807 if (tx_pause && rx_pause) 808 hw_fc_info->current_mode = ICE_FC_FULL; 809 else if (tx_pause) 810 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 811 else if (rx_pause) 812 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 813 else 814 hw_fc_info->current_mode = ICE_FC_NONE; 815 816 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 817 818 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 819 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 820 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 821 (unsigned long long)li->phy_type_low); 822 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 823 (unsigned long long)li->phy_type_high); 824 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 825 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 826 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 827 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 828 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 829 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 830 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 831 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 832 li->max_frame_size); 833 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 834 835 /* save link status information */ 836 if (link) 837 *link = *li; 838 839 /* flag cleared so calling functions don't call AQ again */ 840 pi->phy.get_link_info = false; 841 842 return 0; 843 } 844 845 /** 846 * ice_fill_tx_timer_and_fc_thresh 847 * @hw: pointer to the HW struct 848 * @cmd: pointer to MAC cfg structure 849 * 850 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 851 * descriptor 852 */ 853 static void 854 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 855 struct ice_aqc_set_mac_cfg *cmd) 856 { 857 u32 val, fc_thres_m; 858 859 /* We read back the transmit timer and FC threshold value of 860 * LFC. Thus, we will use index = 861 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 862 * 863 * Also, because we are operating on transmit timer and FC 864 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 865 */ 866 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 867 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 868 869 if (hw->mac_type == ICE_MAC_E830) { 870 /* Retrieve the transmit timer */ 871 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 872 cmd->tx_tmr_value = 873 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 874 875 /* Retrieve the fc threshold */ 876 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 877 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 878 } else { 879 /* Retrieve the transmit timer */ 880 val = rd32(hw, 881 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 882 cmd->tx_tmr_value = 883 le16_encode_bits(val, 884 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 885 886 /* Retrieve the fc threshold */ 887 val = rd32(hw, 888 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 889 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 890 } 891 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 892 } 893 894 /** 895 * ice_aq_set_mac_cfg 896 * @hw: pointer to the HW struct 897 * @max_frame_size: Maximum Frame Size to be supported 898 * @cd: pointer to command details structure or NULL 899 * 900 * Set MAC configuration (0x0603) 901 */ 902 int 903 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 904 { 905 struct ice_aqc_set_mac_cfg *cmd; 906 struct ice_aq_desc desc; 907 908 cmd = &desc.params.set_mac_cfg; 909 910 if (max_frame_size == 0) 911 return -EINVAL; 912 913 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 914 915 cmd->max_frame_size = cpu_to_le16(max_frame_size); 916 917 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 918 919 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 920 } 921 922 /** 923 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 924 * @hw: pointer to the HW struct 925 */ 926 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 927 { 928 struct ice_switch_info *sw; 929 int status; 930 931 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 932 sizeof(*hw->switch_info), GFP_KERNEL); 933 sw = hw->switch_info; 934 935 if (!sw) 936 return -ENOMEM; 937 938 INIT_LIST_HEAD(&sw->vsi_list_map_head); 939 sw->prof_res_bm_init = 0; 940 941 /* Initialize recipe count with default recipes read from NVM */ 942 sw->recp_cnt = ICE_SW_LKUP_LAST; 943 944 status = ice_init_def_sw_recp(hw); 945 if (status) { 946 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 947 return status; 948 } 949 return 0; 950 } 951 952 /** 953 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 954 * @hw: pointer to the HW struct 955 */ 956 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 957 { 958 struct ice_switch_info *sw = hw->switch_info; 959 struct ice_vsi_list_map_info *v_pos_map; 960 struct ice_vsi_list_map_info *v_tmp_map; 961 struct ice_sw_recipe *recps; 962 u8 i; 963 964 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 965 list_entry) { 966 list_del(&v_pos_map->list_entry); 967 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 968 } 969 recps = sw->recp_list; 970 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 971 recps[i].root_rid = i; 972 973 if (recps[i].adv_rule) { 974 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 975 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 976 977 mutex_destroy(&recps[i].filt_rule_lock); 978 list_for_each_entry_safe(lst_itr, tmp_entry, 979 &recps[i].filt_rules, 980 list_entry) { 981 list_del(&lst_itr->list_entry); 982 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 983 devm_kfree(ice_hw_to_dev(hw), lst_itr); 984 } 985 } else { 986 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 987 988 mutex_destroy(&recps[i].filt_rule_lock); 989 list_for_each_entry_safe(lst_itr, tmp_entry, 990 &recps[i].filt_rules, 991 list_entry) { 992 list_del(&lst_itr->list_entry); 993 devm_kfree(ice_hw_to_dev(hw), lst_itr); 994 } 995 } 996 } 997 ice_rm_all_sw_replay_rule_info(hw); 998 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 999 devm_kfree(ice_hw_to_dev(hw), sw); 1000 } 1001 1002 /** 1003 * ice_get_itr_intrl_gran 1004 * @hw: pointer to the HW struct 1005 * 1006 * Determines the ITR/INTRL granularities based on the maximum aggregate 1007 * bandwidth according to the device's configuration during power-on. 1008 */ 1009 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1010 { 1011 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 1012 rd32(hw, GL_PWR_MODE_CTL)); 1013 1014 switch (max_agg_bw) { 1015 case ICE_MAX_AGG_BW_200G: 1016 case ICE_MAX_AGG_BW_100G: 1017 case ICE_MAX_AGG_BW_50G: 1018 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1019 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1020 break; 1021 case ICE_MAX_AGG_BW_25G: 1022 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1023 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1024 break; 1025 } 1026 } 1027 1028 /** 1029 * ice_init_hw - main hardware initialization routine 1030 * @hw: pointer to the hardware structure 1031 */ 1032 int ice_init_hw(struct ice_hw *hw) 1033 { 1034 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1035 void *mac_buf __free(kfree) = NULL; 1036 u16 mac_buf_len; 1037 int status; 1038 1039 /* Set MAC type based on DeviceID */ 1040 status = ice_set_mac_type(hw); 1041 if (status) 1042 return status; 1043 1044 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1045 1046 status = ice_reset(hw, ICE_RESET_PFR); 1047 if (status) 1048 return status; 1049 1050 ice_get_itr_intrl_gran(hw); 1051 1052 status = ice_create_all_ctrlq(hw); 1053 if (status) 1054 goto err_unroll_cqinit; 1055 1056 status = ice_fwlog_init(hw); 1057 if (status) 1058 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1059 status); 1060 1061 status = ice_clear_pf_cfg(hw); 1062 if (status) 1063 goto err_unroll_cqinit; 1064 1065 /* Set bit to enable Flow Director filters */ 1066 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1067 INIT_LIST_HEAD(&hw->fdir_list_head); 1068 1069 ice_clear_pxe_mode(hw); 1070 1071 status = ice_init_nvm(hw); 1072 if (status) 1073 goto err_unroll_cqinit; 1074 1075 status = ice_get_caps(hw); 1076 if (status) 1077 goto err_unroll_cqinit; 1078 1079 if (!hw->port_info) 1080 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1081 sizeof(*hw->port_info), 1082 GFP_KERNEL); 1083 if (!hw->port_info) { 1084 status = -ENOMEM; 1085 goto err_unroll_cqinit; 1086 } 1087 1088 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1089 /* set the back pointer to HW */ 1090 hw->port_info->hw = hw; 1091 1092 /* Initialize port_info struct with switch configuration data */ 1093 status = ice_get_initial_sw_cfg(hw); 1094 if (status) 1095 goto err_unroll_alloc; 1096 1097 hw->evb_veb = true; 1098 1099 /* init xarray for identifying scheduling nodes uniquely */ 1100 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1101 1102 /* Query the allocated resources for Tx scheduler */ 1103 status = ice_sched_query_res_alloc(hw); 1104 if (status) { 1105 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1106 goto err_unroll_alloc; 1107 } 1108 ice_sched_get_psm_clk_freq(hw); 1109 1110 /* Initialize port_info struct with scheduler data */ 1111 status = ice_sched_init_port(hw->port_info); 1112 if (status) 1113 goto err_unroll_sched; 1114 1115 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1116 if (!pcaps) { 1117 status = -ENOMEM; 1118 goto err_unroll_sched; 1119 } 1120 1121 /* Initialize port_info struct with PHY capabilities */ 1122 status = ice_aq_get_phy_caps(hw->port_info, false, 1123 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1124 NULL); 1125 if (status) 1126 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1127 status); 1128 1129 /* Initialize port_info struct with link information */ 1130 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1131 if (status) 1132 goto err_unroll_sched; 1133 1134 /* need a valid SW entry point to build a Tx tree */ 1135 if (!hw->sw_entry_point_layer) { 1136 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1137 status = -EIO; 1138 goto err_unroll_sched; 1139 } 1140 INIT_LIST_HEAD(&hw->agg_list); 1141 /* Initialize max burst size */ 1142 if (!hw->max_burst_size) 1143 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1144 1145 status = ice_init_fltr_mgmt_struct(hw); 1146 if (status) 1147 goto err_unroll_sched; 1148 1149 /* Get MAC information */ 1150 /* A single port can report up to two (LAN and WoL) addresses */ 1151 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1152 GFP_KERNEL); 1153 if (!mac_buf) { 1154 status = -ENOMEM; 1155 goto err_unroll_fltr_mgmt_struct; 1156 } 1157 1158 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1159 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1160 1161 if (status) 1162 goto err_unroll_fltr_mgmt_struct; 1163 /* enable jumbo frame support at MAC level */ 1164 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1165 if (status) 1166 goto err_unroll_fltr_mgmt_struct; 1167 /* Obtain counter base index which would be used by flow director */ 1168 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1169 if (status) 1170 goto err_unroll_fltr_mgmt_struct; 1171 status = ice_init_hw_tbls(hw); 1172 if (status) 1173 goto err_unroll_fltr_mgmt_struct; 1174 mutex_init(&hw->tnl_lock); 1175 ice_init_chk_recipe_reuse_support(hw); 1176 1177 return 0; 1178 1179 err_unroll_fltr_mgmt_struct: 1180 ice_cleanup_fltr_mgmt_struct(hw); 1181 err_unroll_sched: 1182 ice_sched_cleanup_all(hw); 1183 err_unroll_alloc: 1184 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1185 err_unroll_cqinit: 1186 ice_destroy_all_ctrlq(hw); 1187 return status; 1188 } 1189 1190 /** 1191 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1192 * @hw: pointer to the hardware structure 1193 * 1194 * This should be called only during nominal operation, not as a result of 1195 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1196 * applicable initializations if it fails for any reason. 1197 */ 1198 void ice_deinit_hw(struct ice_hw *hw) 1199 { 1200 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1201 ice_cleanup_fltr_mgmt_struct(hw); 1202 1203 ice_sched_cleanup_all(hw); 1204 ice_sched_clear_agg(hw); 1205 ice_free_seg(hw); 1206 ice_free_hw_tbls(hw); 1207 mutex_destroy(&hw->tnl_lock); 1208 1209 ice_fwlog_deinit(hw); 1210 ice_destroy_all_ctrlq(hw); 1211 1212 /* Clear VSI contexts if not already cleared */ 1213 ice_clear_all_vsi_ctx(hw); 1214 } 1215 1216 /** 1217 * ice_check_reset - Check to see if a global reset is complete 1218 * @hw: pointer to the hardware structure 1219 */ 1220 int ice_check_reset(struct ice_hw *hw) 1221 { 1222 u32 cnt, reg = 0, grst_timeout, uld_mask; 1223 1224 /* Poll for Device Active state in case a recent CORER, GLOBR, 1225 * or EMPR has occurred. The grst delay value is in 100ms units. 1226 * Add 1sec for outstanding AQ commands that can take a long time. 1227 */ 1228 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1229 rd32(hw, GLGEN_RSTCTL)) + 10; 1230 1231 for (cnt = 0; cnt < grst_timeout; cnt++) { 1232 mdelay(100); 1233 reg = rd32(hw, GLGEN_RSTAT); 1234 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1235 break; 1236 } 1237 1238 if (cnt == grst_timeout) { 1239 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1240 return -EIO; 1241 } 1242 1243 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1244 GLNVM_ULD_PCIER_DONE_1_M |\ 1245 GLNVM_ULD_CORER_DONE_M |\ 1246 GLNVM_ULD_GLOBR_DONE_M |\ 1247 GLNVM_ULD_POR_DONE_M |\ 1248 GLNVM_ULD_POR_DONE_1_M |\ 1249 GLNVM_ULD_PCIER_DONE_2_M) 1250 1251 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1252 GLNVM_ULD_PE_DONE_M : 0); 1253 1254 /* Device is Active; check Global Reset processes are done */ 1255 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1256 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1257 if (reg == uld_mask) { 1258 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1259 break; 1260 } 1261 mdelay(10); 1262 } 1263 1264 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1265 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1266 reg); 1267 return -EIO; 1268 } 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * ice_pf_reset - Reset the PF 1275 * @hw: pointer to the hardware structure 1276 * 1277 * If a global reset has been triggered, this function checks 1278 * for its completion and then issues the PF reset 1279 */ 1280 static int ice_pf_reset(struct ice_hw *hw) 1281 { 1282 u32 cnt, reg; 1283 1284 /* If at function entry a global reset was already in progress, i.e. 1285 * state is not 'device active' or any of the reset done bits are not 1286 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1287 * global reset is done. 1288 */ 1289 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1290 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1291 /* poll on global reset currently in progress until done */ 1292 if (ice_check_reset(hw)) 1293 return -EIO; 1294 1295 return 0; 1296 } 1297 1298 /* Reset the PF */ 1299 reg = rd32(hw, PFGEN_CTRL); 1300 1301 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1302 1303 /* Wait for the PFR to complete. The wait time is the global config lock 1304 * timeout plus the PFR timeout which will account for a possible reset 1305 * that is occurring during a download package operation. 1306 */ 1307 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1308 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1309 reg = rd32(hw, PFGEN_CTRL); 1310 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1311 break; 1312 1313 mdelay(1); 1314 } 1315 1316 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1317 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1318 return -EIO; 1319 } 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * ice_reset - Perform different types of reset 1326 * @hw: pointer to the hardware structure 1327 * @req: reset request 1328 * 1329 * This function triggers a reset as specified by the req parameter. 1330 * 1331 * Note: 1332 * If anything other than a PF reset is triggered, PXE mode is restored. 1333 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1334 * interface has been restored in the rebuild flow. 1335 */ 1336 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1337 { 1338 u32 val = 0; 1339 1340 switch (req) { 1341 case ICE_RESET_PFR: 1342 return ice_pf_reset(hw); 1343 case ICE_RESET_CORER: 1344 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1345 val = GLGEN_RTRIG_CORER_M; 1346 break; 1347 case ICE_RESET_GLOBR: 1348 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1349 val = GLGEN_RTRIG_GLOBR_M; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 val |= rd32(hw, GLGEN_RTRIG); 1356 wr32(hw, GLGEN_RTRIG, val); 1357 ice_flush(hw); 1358 1359 /* wait for the FW to be ready */ 1360 return ice_check_reset(hw); 1361 } 1362 1363 /** 1364 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1365 * @hw: pointer to the hardware structure 1366 * @rxq_ctx: pointer to the packed Rx queue context 1367 * @rxq_index: the index of the Rx queue 1368 */ 1369 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1370 const ice_rxq_ctx_buf_t *rxq_ctx, 1371 u32 rxq_index) 1372 { 1373 /* Copy each dword separately to HW */ 1374 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1375 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1376 1377 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1378 1379 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1380 } 1381 } 1382 1383 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1384 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1385 1386 /* LAN Rx Queue Context */ 1387 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1388 /* Field Width LSB */ 1389 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1390 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1391 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1392 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1393 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1394 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1395 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1396 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1397 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1398 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1399 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1400 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1401 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1402 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1403 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1404 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1405 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1406 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1407 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1408 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1409 }; 1410 1411 /** 1412 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1413 * @ctx: the Rx queue context to pack 1414 * @buf: the HW buffer to pack into 1415 * 1416 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1417 * bit-packed HW layout. 1418 */ 1419 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1420 ice_rxq_ctx_buf_t *buf) 1421 { 1422 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1423 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1424 } 1425 1426 /** 1427 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1428 * @hw: pointer to the hardware structure 1429 * @rlan_ctx: pointer to the unpacked Rx queue context 1430 * @rxq_index: the index of the Rx queue 1431 * 1432 * Pack the sparse Rx Queue context into dense hardware format and write it 1433 * into the HW register space. 1434 * 1435 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1436 */ 1437 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1438 u32 rxq_index) 1439 { 1440 ice_rxq_ctx_buf_t buf = {}; 1441 1442 if (rxq_index > QRX_CTRL_MAX_INDEX) 1443 return -EINVAL; 1444 1445 ice_pack_rxq_ctx(rlan_ctx, &buf); 1446 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1447 1448 return 0; 1449 } 1450 1451 /* LAN Tx Queue Context */ 1452 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1453 /* Field Width LSB */ 1454 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1455 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1456 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1457 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1458 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1459 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1460 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1461 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1462 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1463 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1464 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1465 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1466 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1467 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1468 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1469 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1470 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1471 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1472 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1473 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1474 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1475 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1476 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1477 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1478 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1479 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1480 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1481 }; 1482 1483 /** 1484 * ice_pack_txq_ctx - Pack Tx queue context into a HW buffer 1485 * @ctx: the Tx queue context to pack 1486 * @buf: the HW buffer to pack into 1487 * 1488 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1489 * bit-packed HW layout. 1490 */ 1491 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1492 { 1493 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1494 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1495 } 1496 1497 /* Sideband Queue command wrappers */ 1498 1499 /** 1500 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1501 * @hw: pointer to the HW struct 1502 * @desc: descriptor describing the command 1503 * @buf: buffer to use for indirect commands (NULL for direct commands) 1504 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1505 * @cd: pointer to command details structure 1506 */ 1507 static int 1508 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1509 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1510 { 1511 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1512 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1513 } 1514 1515 /** 1516 * ice_sbq_rw_reg - Fill Sideband Queue command 1517 * @hw: pointer to the HW struct 1518 * @in: message info to be filled in descriptor 1519 * @flags: control queue descriptor flags 1520 */ 1521 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1522 { 1523 struct ice_sbq_cmd_desc desc = {0}; 1524 struct ice_sbq_msg_req msg = {0}; 1525 u16 msg_len; 1526 int status; 1527 1528 msg_len = sizeof(msg); 1529 1530 msg.dest_dev = in->dest_dev; 1531 msg.opcode = in->opcode; 1532 msg.flags = ICE_SBQ_MSG_FLAGS; 1533 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1534 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1535 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1536 1537 if (in->opcode) 1538 msg.data = cpu_to_le32(in->data); 1539 else 1540 /* data read comes back in completion, so shorten the struct by 1541 * sizeof(msg.data) 1542 */ 1543 msg_len -= sizeof(msg.data); 1544 1545 desc.flags = cpu_to_le16(flags); 1546 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1547 desc.param0.cmd_len = cpu_to_le16(msg_len); 1548 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1549 if (!status && !in->opcode) 1550 in->data = le32_to_cpu 1551 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1552 return status; 1553 } 1554 1555 /* FW Admin Queue command wrappers */ 1556 1557 /* Software lock/mutex that is meant to be held while the Global Config Lock 1558 * in firmware is acquired by the software to prevent most (but not all) types 1559 * of AQ commands from being sent to FW 1560 */ 1561 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1562 1563 /** 1564 * ice_should_retry_sq_send_cmd 1565 * @opcode: AQ opcode 1566 * 1567 * Decide if we should retry the send command routine for the ATQ, depending 1568 * on the opcode. 1569 */ 1570 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1571 { 1572 switch (opcode) { 1573 case ice_aqc_opc_get_link_topo: 1574 case ice_aqc_opc_lldp_stop: 1575 case ice_aqc_opc_lldp_start: 1576 case ice_aqc_opc_lldp_filter_ctrl: 1577 return true; 1578 } 1579 1580 return false; 1581 } 1582 1583 /** 1584 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1585 * @hw: pointer to the HW struct 1586 * @cq: pointer to the specific Control queue 1587 * @desc: prefilled descriptor describing the command 1588 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1589 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1590 * @cd: pointer to command details structure 1591 * 1592 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1593 * Queue if the EBUSY AQ error is returned. 1594 */ 1595 static int 1596 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1597 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1598 struct ice_sq_cd *cd) 1599 { 1600 struct ice_aq_desc desc_cpy; 1601 bool is_cmd_for_retry; 1602 u8 idx = 0; 1603 u16 opcode; 1604 int status; 1605 1606 opcode = le16_to_cpu(desc->opcode); 1607 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1608 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1609 1610 if (is_cmd_for_retry) { 1611 /* All retryable cmds are direct, without buf. */ 1612 WARN_ON(buf); 1613 1614 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1615 } 1616 1617 do { 1618 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1619 1620 if (!is_cmd_for_retry || !status || 1621 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1622 break; 1623 1624 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1625 1626 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1627 1628 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1629 1630 return status; 1631 } 1632 1633 /** 1634 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1635 * @hw: pointer to the HW struct 1636 * @desc: descriptor describing the command 1637 * @buf: buffer to use for indirect commands (NULL for direct commands) 1638 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1639 * @cd: pointer to command details structure 1640 * 1641 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1642 */ 1643 int 1644 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1645 u16 buf_size, struct ice_sq_cd *cd) 1646 { 1647 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1648 bool lock_acquired = false; 1649 int status; 1650 1651 /* When a package download is in process (i.e. when the firmware's 1652 * Global Configuration Lock resource is held), only the Download 1653 * Package, Get Version, Get Package Info List, Upload Section, 1654 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1655 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1656 * Recipes to Profile Association, and Release Resource (with resource 1657 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1658 * must block until the package download completes and the Global Config 1659 * Lock is released. See also ice_acquire_global_cfg_lock(). 1660 */ 1661 switch (le16_to_cpu(desc->opcode)) { 1662 case ice_aqc_opc_download_pkg: 1663 case ice_aqc_opc_get_pkg_info_list: 1664 case ice_aqc_opc_get_ver: 1665 case ice_aqc_opc_upload_section: 1666 case ice_aqc_opc_update_pkg: 1667 case ice_aqc_opc_set_port_params: 1668 case ice_aqc_opc_get_vlan_mode_parameters: 1669 case ice_aqc_opc_set_vlan_mode_parameters: 1670 case ice_aqc_opc_set_tx_topo: 1671 case ice_aqc_opc_get_tx_topo: 1672 case ice_aqc_opc_add_recipe: 1673 case ice_aqc_opc_recipe_to_profile: 1674 case ice_aqc_opc_get_recipe: 1675 case ice_aqc_opc_get_recipe_to_profile: 1676 break; 1677 case ice_aqc_opc_release_res: 1678 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1679 break; 1680 fallthrough; 1681 default: 1682 mutex_lock(&ice_global_cfg_lock_sw); 1683 lock_acquired = true; 1684 break; 1685 } 1686 1687 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1688 if (lock_acquired) 1689 mutex_unlock(&ice_global_cfg_lock_sw); 1690 1691 return status; 1692 } 1693 1694 /** 1695 * ice_aq_get_fw_ver 1696 * @hw: pointer to the HW struct 1697 * @cd: pointer to command details structure or NULL 1698 * 1699 * Get the firmware version (0x0001) from the admin queue commands 1700 */ 1701 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1702 { 1703 struct ice_aqc_get_ver *resp; 1704 struct ice_aq_desc desc; 1705 int status; 1706 1707 resp = &desc.params.get_ver; 1708 1709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1710 1711 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1712 1713 if (!status) { 1714 hw->fw_branch = resp->fw_branch; 1715 hw->fw_maj_ver = resp->fw_major; 1716 hw->fw_min_ver = resp->fw_minor; 1717 hw->fw_patch = resp->fw_patch; 1718 hw->fw_build = le32_to_cpu(resp->fw_build); 1719 hw->api_branch = resp->api_branch; 1720 hw->api_maj_ver = resp->api_major; 1721 hw->api_min_ver = resp->api_minor; 1722 hw->api_patch = resp->api_patch; 1723 } 1724 1725 return status; 1726 } 1727 1728 /** 1729 * ice_aq_send_driver_ver 1730 * @hw: pointer to the HW struct 1731 * @dv: driver's major, minor version 1732 * @cd: pointer to command details structure or NULL 1733 * 1734 * Send the driver version (0x0002) to the firmware 1735 */ 1736 int 1737 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1738 struct ice_sq_cd *cd) 1739 { 1740 struct ice_aqc_driver_ver *cmd; 1741 struct ice_aq_desc desc; 1742 u16 len; 1743 1744 cmd = &desc.params.driver_ver; 1745 1746 if (!dv) 1747 return -EINVAL; 1748 1749 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1750 1751 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1752 cmd->major_ver = dv->major_ver; 1753 cmd->minor_ver = dv->minor_ver; 1754 cmd->build_ver = dv->build_ver; 1755 cmd->subbuild_ver = dv->subbuild_ver; 1756 1757 len = 0; 1758 while (len < sizeof(dv->driver_string) && 1759 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1760 len++; 1761 1762 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1763 } 1764 1765 /** 1766 * ice_aq_q_shutdown 1767 * @hw: pointer to the HW struct 1768 * @unloading: is the driver unloading itself 1769 * 1770 * Tell the Firmware that we're shutting down the AdminQ and whether 1771 * or not the driver is unloading as well (0x0003). 1772 */ 1773 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1774 { 1775 struct ice_aqc_q_shutdown *cmd; 1776 struct ice_aq_desc desc; 1777 1778 cmd = &desc.params.q_shutdown; 1779 1780 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1781 1782 if (unloading) 1783 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1784 1785 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1786 } 1787 1788 /** 1789 * ice_aq_req_res 1790 * @hw: pointer to the HW struct 1791 * @res: resource ID 1792 * @access: access type 1793 * @sdp_number: resource number 1794 * @timeout: the maximum time in ms that the driver may hold the resource 1795 * @cd: pointer to command details structure or NULL 1796 * 1797 * Requests common resource using the admin queue commands (0x0008). 1798 * When attempting to acquire the Global Config Lock, the driver can 1799 * learn of three states: 1800 * 1) 0 - acquired lock, and can perform download package 1801 * 2) -EIO - did not get lock, driver should fail to load 1802 * 3) -EALREADY - did not get lock, but another driver has 1803 * successfully downloaded the package; the driver does 1804 * not have to download the package and can continue 1805 * loading 1806 * 1807 * Note that if the caller is in an acquire lock, perform action, release lock 1808 * phase of operation, it is possible that the FW may detect a timeout and issue 1809 * a CORER. In this case, the driver will receive a CORER interrupt and will 1810 * have to determine its cause. The calling thread that is handling this flow 1811 * will likely get an error propagated back to it indicating the Download 1812 * Package, Update Package or the Release Resource AQ commands timed out. 1813 */ 1814 static int 1815 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1816 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1817 struct ice_sq_cd *cd) 1818 { 1819 struct ice_aqc_req_res *cmd_resp; 1820 struct ice_aq_desc desc; 1821 int status; 1822 1823 cmd_resp = &desc.params.res_owner; 1824 1825 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1826 1827 cmd_resp->res_id = cpu_to_le16(res); 1828 cmd_resp->access_type = cpu_to_le16(access); 1829 cmd_resp->res_number = cpu_to_le32(sdp_number); 1830 cmd_resp->timeout = cpu_to_le32(*timeout); 1831 *timeout = 0; 1832 1833 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1834 1835 /* The completion specifies the maximum time in ms that the driver 1836 * may hold the resource in the Timeout field. 1837 */ 1838 1839 /* Global config lock response utilizes an additional status field. 1840 * 1841 * If the Global config lock resource is held by some other driver, the 1842 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1843 * and the timeout field indicates the maximum time the current owner 1844 * of the resource has to free it. 1845 */ 1846 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1847 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1848 *timeout = le32_to_cpu(cmd_resp->timeout); 1849 return 0; 1850 } else if (le16_to_cpu(cmd_resp->status) == 1851 ICE_AQ_RES_GLBL_IN_PROG) { 1852 *timeout = le32_to_cpu(cmd_resp->timeout); 1853 return -EIO; 1854 } else if (le16_to_cpu(cmd_resp->status) == 1855 ICE_AQ_RES_GLBL_DONE) { 1856 return -EALREADY; 1857 } 1858 1859 /* invalid FW response, force a timeout immediately */ 1860 *timeout = 0; 1861 return -EIO; 1862 } 1863 1864 /* If the resource is held by some other driver, the command completes 1865 * with a busy return value and the timeout field indicates the maximum 1866 * time the current owner of the resource has to free it. 1867 */ 1868 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1869 *timeout = le32_to_cpu(cmd_resp->timeout); 1870 1871 return status; 1872 } 1873 1874 /** 1875 * ice_aq_release_res 1876 * @hw: pointer to the HW struct 1877 * @res: resource ID 1878 * @sdp_number: resource number 1879 * @cd: pointer to command details structure or NULL 1880 * 1881 * release common resource using the admin queue commands (0x0009) 1882 */ 1883 static int 1884 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1885 struct ice_sq_cd *cd) 1886 { 1887 struct ice_aqc_req_res *cmd; 1888 struct ice_aq_desc desc; 1889 1890 cmd = &desc.params.res_owner; 1891 1892 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1893 1894 cmd->res_id = cpu_to_le16(res); 1895 cmd->res_number = cpu_to_le32(sdp_number); 1896 1897 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1898 } 1899 1900 /** 1901 * ice_acquire_res 1902 * @hw: pointer to the HW structure 1903 * @res: resource ID 1904 * @access: access type (read or write) 1905 * @timeout: timeout in milliseconds 1906 * 1907 * This function will attempt to acquire the ownership of a resource. 1908 */ 1909 int 1910 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1911 enum ice_aq_res_access_type access, u32 timeout) 1912 { 1913 #define ICE_RES_POLLING_DELAY_MS 10 1914 u32 delay = ICE_RES_POLLING_DELAY_MS; 1915 u32 time_left = timeout; 1916 int status; 1917 1918 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1919 1920 /* A return code of -EALREADY means that another driver has 1921 * previously acquired the resource and performed any necessary updates; 1922 * in this case the caller does not obtain the resource and has no 1923 * further work to do. 1924 */ 1925 if (status == -EALREADY) 1926 goto ice_acquire_res_exit; 1927 1928 if (status) 1929 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1930 1931 /* If necessary, poll until the current lock owner timeouts */ 1932 timeout = time_left; 1933 while (status && timeout && time_left) { 1934 mdelay(delay); 1935 timeout = (timeout > delay) ? timeout - delay : 0; 1936 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1937 1938 if (status == -EALREADY) 1939 /* lock free, but no work to do */ 1940 break; 1941 1942 if (!status) 1943 /* lock acquired */ 1944 break; 1945 } 1946 if (status && status != -EALREADY) 1947 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1948 1949 ice_acquire_res_exit: 1950 if (status == -EALREADY) { 1951 if (access == ICE_RES_WRITE) 1952 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1953 else 1954 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1955 } 1956 return status; 1957 } 1958 1959 /** 1960 * ice_release_res 1961 * @hw: pointer to the HW structure 1962 * @res: resource ID 1963 * 1964 * This function will release a resource using the proper Admin Command. 1965 */ 1966 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1967 { 1968 unsigned long timeout; 1969 int status; 1970 1971 /* there are some rare cases when trying to release the resource 1972 * results in an admin queue timeout, so handle them correctly 1973 */ 1974 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 1975 do { 1976 status = ice_aq_release_res(hw, res, 0, NULL); 1977 if (status != -EIO) 1978 break; 1979 usleep_range(1000, 2000); 1980 } while (time_before(jiffies, timeout)); 1981 } 1982 1983 /** 1984 * ice_aq_alloc_free_res - command to allocate/free resources 1985 * @hw: pointer to the HW struct 1986 * @buf: Indirect buffer to hold data parameters and response 1987 * @buf_size: size of buffer for indirect commands 1988 * @opc: pass in the command opcode 1989 * 1990 * Helper function to allocate/free resources using the admin queue commands 1991 */ 1992 int ice_aq_alloc_free_res(struct ice_hw *hw, 1993 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1994 enum ice_adminq_opc opc) 1995 { 1996 struct ice_aqc_alloc_free_res_cmd *cmd; 1997 struct ice_aq_desc desc; 1998 1999 cmd = &desc.params.sw_res_ctrl; 2000 2001 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2002 return -EINVAL; 2003 2004 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2005 2006 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2007 2008 cmd->num_entries = cpu_to_le16(1); 2009 2010 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2011 } 2012 2013 /** 2014 * ice_alloc_hw_res - allocate resource 2015 * @hw: pointer to the HW struct 2016 * @type: type of resource 2017 * @num: number of resources to allocate 2018 * @btm: allocate from bottom 2019 * @res: pointer to array that will receive the resources 2020 */ 2021 int 2022 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2023 { 2024 struct ice_aqc_alloc_free_res_elem *buf; 2025 u16 buf_len; 2026 int status; 2027 2028 buf_len = struct_size(buf, elem, num); 2029 buf = kzalloc(buf_len, GFP_KERNEL); 2030 if (!buf) 2031 return -ENOMEM; 2032 2033 /* Prepare buffer to allocate resource. */ 2034 buf->num_elems = cpu_to_le16(num); 2035 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2036 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2037 if (btm) 2038 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2039 2040 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2041 if (status) 2042 goto ice_alloc_res_exit; 2043 2044 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2045 2046 ice_alloc_res_exit: 2047 kfree(buf); 2048 return status; 2049 } 2050 2051 /** 2052 * ice_free_hw_res - free allocated HW resource 2053 * @hw: pointer to the HW struct 2054 * @type: type of resource to free 2055 * @num: number of resources 2056 * @res: pointer to array that contains the resources to free 2057 */ 2058 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2059 { 2060 struct ice_aqc_alloc_free_res_elem *buf; 2061 u16 buf_len; 2062 int status; 2063 2064 buf_len = struct_size(buf, elem, num); 2065 buf = kzalloc(buf_len, GFP_KERNEL); 2066 if (!buf) 2067 return -ENOMEM; 2068 2069 /* Prepare buffer to free resource. */ 2070 buf->num_elems = cpu_to_le16(num); 2071 buf->res_type = cpu_to_le16(type); 2072 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2073 2074 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2075 if (status) 2076 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2077 2078 kfree(buf); 2079 return status; 2080 } 2081 2082 /** 2083 * ice_get_num_per_func - determine number of resources per PF 2084 * @hw: pointer to the HW structure 2085 * @max: value to be evenly split between each PF 2086 * 2087 * Determine the number of valid functions by going through the bitmap returned 2088 * from parsing capabilities and use this to calculate the number of resources 2089 * per PF based on the max value passed in. 2090 */ 2091 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2092 { 2093 u8 funcs; 2094 2095 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2096 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2097 ICE_CAPS_VALID_FUNCS_M); 2098 2099 if (!funcs) 2100 return 0; 2101 2102 return max / funcs; 2103 } 2104 2105 /** 2106 * ice_parse_common_caps - parse common device/function capabilities 2107 * @hw: pointer to the HW struct 2108 * @caps: pointer to common capabilities structure 2109 * @elem: the capability element to parse 2110 * @prefix: message prefix for tracing capabilities 2111 * 2112 * Given a capability element, extract relevant details into the common 2113 * capability structure. 2114 * 2115 * Returns: true if the capability matches one of the common capability ids, 2116 * false otherwise. 2117 */ 2118 static bool 2119 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2120 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2121 { 2122 u32 logical_id = le32_to_cpu(elem->logical_id); 2123 u32 phys_id = le32_to_cpu(elem->phys_id); 2124 u32 number = le32_to_cpu(elem->number); 2125 u16 cap = le16_to_cpu(elem->cap); 2126 bool found = true; 2127 2128 switch (cap) { 2129 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2130 caps->valid_functions = number; 2131 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2132 caps->valid_functions); 2133 break; 2134 case ICE_AQC_CAPS_SRIOV: 2135 caps->sr_iov_1_1 = (number == 1); 2136 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2137 caps->sr_iov_1_1); 2138 break; 2139 case ICE_AQC_CAPS_DCB: 2140 caps->dcb = (number == 1); 2141 caps->active_tc_bitmap = logical_id; 2142 caps->maxtc = phys_id; 2143 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2144 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2145 caps->active_tc_bitmap); 2146 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2147 break; 2148 case ICE_AQC_CAPS_RSS: 2149 caps->rss_table_size = number; 2150 caps->rss_table_entry_width = logical_id; 2151 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2152 caps->rss_table_size); 2153 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2154 caps->rss_table_entry_width); 2155 break; 2156 case ICE_AQC_CAPS_RXQS: 2157 caps->num_rxq = number; 2158 caps->rxq_first_id = phys_id; 2159 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2160 caps->num_rxq); 2161 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2162 caps->rxq_first_id); 2163 break; 2164 case ICE_AQC_CAPS_TXQS: 2165 caps->num_txq = number; 2166 caps->txq_first_id = phys_id; 2167 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2168 caps->num_txq); 2169 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2170 caps->txq_first_id); 2171 break; 2172 case ICE_AQC_CAPS_MSIX: 2173 caps->num_msix_vectors = number; 2174 caps->msix_vector_first_id = phys_id; 2175 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2176 caps->num_msix_vectors); 2177 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2178 caps->msix_vector_first_id); 2179 break; 2180 case ICE_AQC_CAPS_PENDING_NVM_VER: 2181 caps->nvm_update_pending_nvm = true; 2182 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2183 break; 2184 case ICE_AQC_CAPS_PENDING_OROM_VER: 2185 caps->nvm_update_pending_orom = true; 2186 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2187 break; 2188 case ICE_AQC_CAPS_PENDING_NET_VER: 2189 caps->nvm_update_pending_netlist = true; 2190 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2191 break; 2192 case ICE_AQC_CAPS_NVM_MGMT: 2193 caps->nvm_unified_update = 2194 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2195 true : false; 2196 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2197 caps->nvm_unified_update); 2198 break; 2199 case ICE_AQC_CAPS_RDMA: 2200 caps->rdma = (number == 1); 2201 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2202 break; 2203 case ICE_AQC_CAPS_MAX_MTU: 2204 caps->max_mtu = number; 2205 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2206 prefix, caps->max_mtu); 2207 break; 2208 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2209 caps->pcie_reset_avoidance = (number > 0); 2210 ice_debug(hw, ICE_DBG_INIT, 2211 "%s: pcie_reset_avoidance = %d\n", prefix, 2212 caps->pcie_reset_avoidance); 2213 break; 2214 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2215 caps->reset_restrict_support = (number == 1); 2216 ice_debug(hw, ICE_DBG_INIT, 2217 "%s: reset_restrict_support = %d\n", prefix, 2218 caps->reset_restrict_support); 2219 break; 2220 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2221 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2222 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2223 prefix, caps->roce_lag); 2224 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2225 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2226 prefix, caps->sriov_lag); 2227 break; 2228 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2229 caps->tx_sched_topo_comp_mode_en = (number == 1); 2230 break; 2231 default: 2232 /* Not one of the recognized common capabilities */ 2233 found = false; 2234 } 2235 2236 return found; 2237 } 2238 2239 /** 2240 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2241 * @hw: pointer to the HW structure 2242 * @caps: pointer to capabilities structure to fix 2243 * 2244 * Re-calculate the capabilities that are dependent on the number of physical 2245 * ports; i.e. some features are not supported or function differently on 2246 * devices with more than 4 ports. 2247 */ 2248 static void 2249 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2250 { 2251 /* This assumes device capabilities are always scanned before function 2252 * capabilities during the initialization flow. 2253 */ 2254 if (hw->dev_caps.num_funcs > 4) { 2255 /* Max 4 TCs per port */ 2256 caps->maxtc = 4; 2257 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2258 caps->maxtc); 2259 if (caps->rdma) { 2260 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2261 caps->rdma = 0; 2262 } 2263 2264 /* print message only when processing device capabilities 2265 * during initialization. 2266 */ 2267 if (caps == &hw->dev_caps.common_cap) 2268 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2269 } 2270 } 2271 2272 /** 2273 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2274 * @hw: pointer to the HW struct 2275 * @func_p: pointer to function capabilities structure 2276 * @cap: pointer to the capability element to parse 2277 * 2278 * Extract function capabilities for ICE_AQC_CAPS_VF. 2279 */ 2280 static void 2281 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2282 struct ice_aqc_list_caps_elem *cap) 2283 { 2284 u32 logical_id = le32_to_cpu(cap->logical_id); 2285 u32 number = le32_to_cpu(cap->number); 2286 2287 func_p->num_allocd_vfs = number; 2288 func_p->vf_base_id = logical_id; 2289 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2290 func_p->num_allocd_vfs); 2291 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2292 func_p->vf_base_id); 2293 } 2294 2295 /** 2296 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2297 * @hw: pointer to the HW struct 2298 * @func_p: pointer to function capabilities structure 2299 * @cap: pointer to the capability element to parse 2300 * 2301 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2302 */ 2303 static void 2304 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2305 struct ice_aqc_list_caps_elem *cap) 2306 { 2307 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2308 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2309 le32_to_cpu(cap->number)); 2310 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2311 func_p->guar_num_vsi); 2312 } 2313 2314 /** 2315 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2316 * @hw: pointer to the HW struct 2317 * @func_p: pointer to function capabilities structure 2318 * @cap: pointer to the capability element to parse 2319 * 2320 * Extract function capabilities for ICE_AQC_CAPS_1588. 2321 */ 2322 static void 2323 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2324 struct ice_aqc_list_caps_elem *cap) 2325 { 2326 struct ice_ts_func_info *info = &func_p->ts_func_info; 2327 u32 number = le32_to_cpu(cap->number); 2328 2329 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2330 func_p->common_cap.ieee_1588 = info->ena; 2331 2332 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2333 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2334 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2335 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2336 2337 if (!ice_is_e825c(hw)) { 2338 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2339 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2340 } else { 2341 info->clk_freq = ICE_TIME_REF_FREQ_156_250; 2342 info->clk_src = ICE_CLK_SRC_TCXO; 2343 } 2344 2345 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2346 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2347 } else { 2348 /* Unknown clock frequency, so assume a (probably incorrect) 2349 * default to avoid out-of-bounds look ups of frequency 2350 * related information. 2351 */ 2352 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2353 info->clk_freq); 2354 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2355 } 2356 2357 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2358 func_p->common_cap.ieee_1588); 2359 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2360 info->src_tmr_owned); 2361 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2362 info->tmr_ena); 2363 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2364 info->tmr_index_owned); 2365 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2366 info->tmr_index_assoc); 2367 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2368 info->clk_freq); 2369 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2370 info->clk_src); 2371 } 2372 2373 /** 2374 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2375 * @hw: pointer to the HW struct 2376 * @func_p: pointer to function capabilities structure 2377 * 2378 * Extract function capabilities for ICE_AQC_CAPS_FD. 2379 */ 2380 static void 2381 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2382 { 2383 u32 reg_val, gsize, bsize; 2384 2385 reg_val = rd32(hw, GLQF_FD_SIZE); 2386 switch (hw->mac_type) { 2387 case ICE_MAC_E830: 2388 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2389 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2390 break; 2391 case ICE_MAC_E810: 2392 default: 2393 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2394 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2395 } 2396 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2397 func_p->fd_fltr_best_effort = bsize; 2398 2399 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2400 func_p->fd_fltr_guar); 2401 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2402 func_p->fd_fltr_best_effort); 2403 } 2404 2405 /** 2406 * ice_parse_func_caps - Parse function capabilities 2407 * @hw: pointer to the HW struct 2408 * @func_p: pointer to function capabilities structure 2409 * @buf: buffer containing the function capability records 2410 * @cap_count: the number of capabilities 2411 * 2412 * Helper function to parse function (0x000A) capabilities list. For 2413 * capabilities shared between device and function, this relies on 2414 * ice_parse_common_caps. 2415 * 2416 * Loop through the list of provided capabilities and extract the relevant 2417 * data into the function capabilities structured. 2418 */ 2419 static void 2420 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2421 void *buf, u32 cap_count) 2422 { 2423 struct ice_aqc_list_caps_elem *cap_resp; 2424 u32 i; 2425 2426 cap_resp = buf; 2427 2428 memset(func_p, 0, sizeof(*func_p)); 2429 2430 for (i = 0; i < cap_count; i++) { 2431 u16 cap = le16_to_cpu(cap_resp[i].cap); 2432 bool found; 2433 2434 found = ice_parse_common_caps(hw, &func_p->common_cap, 2435 &cap_resp[i], "func caps"); 2436 2437 switch (cap) { 2438 case ICE_AQC_CAPS_VF: 2439 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2440 break; 2441 case ICE_AQC_CAPS_VSI: 2442 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2443 break; 2444 case ICE_AQC_CAPS_1588: 2445 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2446 break; 2447 case ICE_AQC_CAPS_FD: 2448 ice_parse_fdir_func_caps(hw, func_p); 2449 break; 2450 default: 2451 /* Don't list common capabilities as unknown */ 2452 if (!found) 2453 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2454 i, cap); 2455 break; 2456 } 2457 } 2458 2459 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2460 } 2461 2462 /** 2463 * ice_func_id_to_logical_id - map from function id to logical pf id 2464 * @active_function_bitmap: active function bitmap 2465 * @pf_id: function number of device 2466 * 2467 * Return: logical PF ID. 2468 */ 2469 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2470 { 2471 u8 logical_id = 0; 2472 u8 i; 2473 2474 for (i = 0; i < pf_id; i++) 2475 if (active_function_bitmap & BIT(i)) 2476 logical_id++; 2477 2478 return logical_id; 2479 } 2480 2481 /** 2482 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2483 * @hw: pointer to the HW struct 2484 * @dev_p: pointer to device capabilities structure 2485 * @cap: capability element to parse 2486 * 2487 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2488 */ 2489 static void 2490 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2491 struct ice_aqc_list_caps_elem *cap) 2492 { 2493 u32 number = le32_to_cpu(cap->number); 2494 2495 dev_p->num_funcs = hweight32(number); 2496 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2497 dev_p->num_funcs); 2498 2499 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2500 } 2501 2502 /** 2503 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2504 * @hw: pointer to the HW struct 2505 * @dev_p: pointer to device capabilities structure 2506 * @cap: capability element to parse 2507 * 2508 * Parse ICE_AQC_CAPS_VF for device capabilities. 2509 */ 2510 static void 2511 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2512 struct ice_aqc_list_caps_elem *cap) 2513 { 2514 u32 number = le32_to_cpu(cap->number); 2515 2516 dev_p->num_vfs_exposed = number; 2517 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2518 dev_p->num_vfs_exposed); 2519 } 2520 2521 /** 2522 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2523 * @hw: pointer to the HW struct 2524 * @dev_p: pointer to device capabilities structure 2525 * @cap: capability element to parse 2526 * 2527 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2528 */ 2529 static void 2530 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2531 struct ice_aqc_list_caps_elem *cap) 2532 { 2533 u32 number = le32_to_cpu(cap->number); 2534 2535 dev_p->num_vsi_allocd_to_host = number; 2536 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2537 dev_p->num_vsi_allocd_to_host); 2538 } 2539 2540 /** 2541 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2542 * @hw: pointer to the HW struct 2543 * @dev_p: pointer to device capabilities structure 2544 * @cap: capability element to parse 2545 * 2546 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2547 */ 2548 static void 2549 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2550 struct ice_aqc_list_caps_elem *cap) 2551 { 2552 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2553 u32 logical_id = le32_to_cpu(cap->logical_id); 2554 u32 phys_id = le32_to_cpu(cap->phys_id); 2555 u32 number = le32_to_cpu(cap->number); 2556 2557 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2558 dev_p->common_cap.ieee_1588 = info->ena; 2559 2560 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2561 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2562 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2563 2564 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2565 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2566 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2567 2568 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2569 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2570 2571 info->ena_ports = logical_id; 2572 info->tmr_own_map = phys_id; 2573 2574 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2575 dev_p->common_cap.ieee_1588); 2576 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2577 info->tmr0_owner); 2578 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2579 info->tmr0_owned); 2580 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2581 info->tmr0_ena); 2582 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2583 info->tmr1_owner); 2584 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2585 info->tmr1_owned); 2586 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2587 info->tmr1_ena); 2588 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2589 info->ts_ll_read); 2590 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2591 info->ts_ll_int_read); 2592 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2593 info->ena_ports); 2594 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2595 info->tmr_own_map); 2596 } 2597 2598 /** 2599 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2600 * @hw: pointer to the HW struct 2601 * @dev_p: pointer to device capabilities structure 2602 * @cap: capability element to parse 2603 * 2604 * Parse ICE_AQC_CAPS_FD for device capabilities. 2605 */ 2606 static void 2607 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2608 struct ice_aqc_list_caps_elem *cap) 2609 { 2610 u32 number = le32_to_cpu(cap->number); 2611 2612 dev_p->num_flow_director_fltr = number; 2613 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2614 dev_p->num_flow_director_fltr); 2615 } 2616 2617 /** 2618 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2619 * @hw: pointer to the HW struct 2620 * @dev_p: pointer to device capabilities structure 2621 * @cap: capability element to parse 2622 * 2623 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2624 * enabled sensors. 2625 */ 2626 static void 2627 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2628 struct ice_aqc_list_caps_elem *cap) 2629 { 2630 dev_p->supported_sensors = le32_to_cpu(cap->number); 2631 2632 ice_debug(hw, ICE_DBG_INIT, 2633 "dev caps: supported sensors (bitmap) = 0x%x\n", 2634 dev_p->supported_sensors); 2635 } 2636 2637 /** 2638 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2639 * @hw: pointer to the HW struct 2640 * @dev_p: pointer to device capabilities structure 2641 * @cap: capability element to parse 2642 * 2643 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2644 */ 2645 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2646 struct ice_hw_dev_caps *dev_p, 2647 struct ice_aqc_list_caps_elem *cap) 2648 { 2649 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2650 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2651 2652 dev_info(ice_hw_to_dev(hw), 2653 "PF is configured in %s mode with IP instance ID %d\n", 2654 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2655 "primary" : "secondary", dev_p->nac_topo.id); 2656 2657 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2658 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2659 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2660 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2661 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2662 dev_p->nac_topo.id); 2663 } 2664 2665 /** 2666 * ice_parse_dev_caps - Parse device capabilities 2667 * @hw: pointer to the HW struct 2668 * @dev_p: pointer to device capabilities structure 2669 * @buf: buffer containing the device capability records 2670 * @cap_count: the number of capabilities 2671 * 2672 * Helper device to parse device (0x000B) capabilities list. For 2673 * capabilities shared between device and function, this relies on 2674 * ice_parse_common_caps. 2675 * 2676 * Loop through the list of provided capabilities and extract the relevant 2677 * data into the device capabilities structured. 2678 */ 2679 static void 2680 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2681 void *buf, u32 cap_count) 2682 { 2683 struct ice_aqc_list_caps_elem *cap_resp; 2684 u32 i; 2685 2686 cap_resp = buf; 2687 2688 memset(dev_p, 0, sizeof(*dev_p)); 2689 2690 for (i = 0; i < cap_count; i++) { 2691 u16 cap = le16_to_cpu(cap_resp[i].cap); 2692 bool found; 2693 2694 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2695 &cap_resp[i], "dev caps"); 2696 2697 switch (cap) { 2698 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2699 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2700 break; 2701 case ICE_AQC_CAPS_VF: 2702 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2703 break; 2704 case ICE_AQC_CAPS_VSI: 2705 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2706 break; 2707 case ICE_AQC_CAPS_1588: 2708 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2709 break; 2710 case ICE_AQC_CAPS_FD: 2711 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2712 break; 2713 case ICE_AQC_CAPS_SENSOR_READING: 2714 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2715 break; 2716 case ICE_AQC_CAPS_NAC_TOPOLOGY: 2717 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2718 break; 2719 default: 2720 /* Don't list common capabilities as unknown */ 2721 if (!found) 2722 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2723 i, cap); 2724 break; 2725 } 2726 } 2727 2728 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2729 } 2730 2731 /** 2732 * ice_is_pf_c827 - check if pf contains c827 phy 2733 * @hw: pointer to the hw struct 2734 */ 2735 bool ice_is_pf_c827(struct ice_hw *hw) 2736 { 2737 struct ice_aqc_get_link_topo cmd = {}; 2738 u8 node_part_number; 2739 u16 node_handle; 2740 int status; 2741 2742 if (hw->mac_type != ICE_MAC_E810) 2743 return false; 2744 2745 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 2746 return true; 2747 2748 cmd.addr.topo_params.node_type_ctx = 2749 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 2750 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 2751 cmd.addr.topo_params.index = 0; 2752 2753 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 2754 &node_handle); 2755 2756 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 2757 return false; 2758 2759 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 2760 return true; 2761 2762 return false; 2763 } 2764 2765 /** 2766 * ice_is_phy_rclk_in_netlist 2767 * @hw: pointer to the hw struct 2768 * 2769 * Check if the PHY Recovered Clock device is present in the netlist 2770 */ 2771 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2772 { 2773 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2774 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2775 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2776 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2777 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2778 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2779 return false; 2780 2781 return true; 2782 } 2783 2784 /** 2785 * ice_is_clock_mux_in_netlist 2786 * @hw: pointer to the hw struct 2787 * 2788 * Check if the Clock Multiplexer device is present in the netlist 2789 */ 2790 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2791 { 2792 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2793 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2794 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2795 NULL)) 2796 return false; 2797 2798 return true; 2799 } 2800 2801 /** 2802 * ice_is_cgu_in_netlist - check for CGU presence 2803 * @hw: pointer to the hw struct 2804 * 2805 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2806 * Save the CGU part number in the hw structure for later use. 2807 * Return: 2808 * * true - cgu is present 2809 * * false - cgu is not present 2810 */ 2811 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2812 { 2813 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2814 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2815 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2816 NULL)) { 2817 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2818 return true; 2819 } else if (!ice_find_netlist_node(hw, 2820 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2821 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2822 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2823 NULL)) { 2824 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2825 return true; 2826 } 2827 2828 return false; 2829 } 2830 2831 /** 2832 * ice_is_gps_in_netlist 2833 * @hw: pointer to the hw struct 2834 * 2835 * Check if the GPS generic device is present in the netlist 2836 */ 2837 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2838 { 2839 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2840 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2841 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 2842 return false; 2843 2844 return true; 2845 } 2846 2847 /** 2848 * ice_aq_list_caps - query function/device capabilities 2849 * @hw: pointer to the HW struct 2850 * @buf: a buffer to hold the capabilities 2851 * @buf_size: size of the buffer 2852 * @cap_count: if not NULL, set to the number of capabilities reported 2853 * @opc: capabilities type to discover, device or function 2854 * @cd: pointer to command details structure or NULL 2855 * 2856 * Get the function (0x000A) or device (0x000B) capabilities description from 2857 * firmware and store it in the buffer. 2858 * 2859 * If the cap_count pointer is not NULL, then it is set to the number of 2860 * capabilities firmware will report. Note that if the buffer size is too 2861 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2862 * cap_count will still be updated in this case. It is recommended that the 2863 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2864 * firmware could return) to avoid this. 2865 */ 2866 int 2867 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2868 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2869 { 2870 struct ice_aqc_list_caps *cmd; 2871 struct ice_aq_desc desc; 2872 int status; 2873 2874 cmd = &desc.params.get_cap; 2875 2876 if (opc != ice_aqc_opc_list_func_caps && 2877 opc != ice_aqc_opc_list_dev_caps) 2878 return -EINVAL; 2879 2880 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2881 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2882 2883 if (cap_count) 2884 *cap_count = le32_to_cpu(cmd->count); 2885 2886 return status; 2887 } 2888 2889 /** 2890 * ice_discover_dev_caps - Read and extract device capabilities 2891 * @hw: pointer to the hardware structure 2892 * @dev_caps: pointer to device capabilities structure 2893 * 2894 * Read the device capabilities and extract them into the dev_caps structure 2895 * for later use. 2896 */ 2897 int 2898 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2899 { 2900 u32 cap_count = 0; 2901 void *cbuf; 2902 int status; 2903 2904 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2905 if (!cbuf) 2906 return -ENOMEM; 2907 2908 /* Although the driver doesn't know the number of capabilities the 2909 * device will return, we can simply send a 4KB buffer, the maximum 2910 * possible size that firmware can return. 2911 */ 2912 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2913 2914 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2915 ice_aqc_opc_list_dev_caps, NULL); 2916 if (!status) 2917 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2918 kfree(cbuf); 2919 2920 return status; 2921 } 2922 2923 /** 2924 * ice_discover_func_caps - Read and extract function capabilities 2925 * @hw: pointer to the hardware structure 2926 * @func_caps: pointer to function capabilities structure 2927 * 2928 * Read the function capabilities and extract them into the func_caps structure 2929 * for later use. 2930 */ 2931 static int 2932 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2933 { 2934 u32 cap_count = 0; 2935 void *cbuf; 2936 int status; 2937 2938 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2939 if (!cbuf) 2940 return -ENOMEM; 2941 2942 /* Although the driver doesn't know the number of capabilities the 2943 * device will return, we can simply send a 4KB buffer, the maximum 2944 * possible size that firmware can return. 2945 */ 2946 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2947 2948 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2949 ice_aqc_opc_list_func_caps, NULL); 2950 if (!status) 2951 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2952 kfree(cbuf); 2953 2954 return status; 2955 } 2956 2957 /** 2958 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2959 * @hw: pointer to the hardware structure 2960 */ 2961 void ice_set_safe_mode_caps(struct ice_hw *hw) 2962 { 2963 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2964 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2965 struct ice_hw_common_caps cached_caps; 2966 u32 num_funcs; 2967 2968 /* cache some func_caps values that should be restored after memset */ 2969 cached_caps = func_caps->common_cap; 2970 2971 /* unset func capabilities */ 2972 memset(func_caps, 0, sizeof(*func_caps)); 2973 2974 #define ICE_RESTORE_FUNC_CAP(name) \ 2975 func_caps->common_cap.name = cached_caps.name 2976 2977 /* restore cached values */ 2978 ICE_RESTORE_FUNC_CAP(valid_functions); 2979 ICE_RESTORE_FUNC_CAP(txq_first_id); 2980 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2981 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2982 ICE_RESTORE_FUNC_CAP(max_mtu); 2983 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2984 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2985 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2986 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2987 2988 /* one Tx and one Rx queue in safe mode */ 2989 func_caps->common_cap.num_rxq = 1; 2990 func_caps->common_cap.num_txq = 1; 2991 2992 /* two MSIX vectors, one for traffic and one for misc causes */ 2993 func_caps->common_cap.num_msix_vectors = 2; 2994 func_caps->guar_num_vsi = 1; 2995 2996 /* cache some dev_caps values that should be restored after memset */ 2997 cached_caps = dev_caps->common_cap; 2998 num_funcs = dev_caps->num_funcs; 2999 3000 /* unset dev capabilities */ 3001 memset(dev_caps, 0, sizeof(*dev_caps)); 3002 3003 #define ICE_RESTORE_DEV_CAP(name) \ 3004 dev_caps->common_cap.name = cached_caps.name 3005 3006 /* restore cached values */ 3007 ICE_RESTORE_DEV_CAP(valid_functions); 3008 ICE_RESTORE_DEV_CAP(txq_first_id); 3009 ICE_RESTORE_DEV_CAP(rxq_first_id); 3010 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3011 ICE_RESTORE_DEV_CAP(max_mtu); 3012 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3013 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3014 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3015 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3016 dev_caps->num_funcs = num_funcs; 3017 3018 /* one Tx and one Rx queue per function in safe mode */ 3019 dev_caps->common_cap.num_rxq = num_funcs; 3020 dev_caps->common_cap.num_txq = num_funcs; 3021 3022 /* two MSIX vectors per function */ 3023 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3024 } 3025 3026 /** 3027 * ice_get_caps - get info about the HW 3028 * @hw: pointer to the hardware structure 3029 */ 3030 int ice_get_caps(struct ice_hw *hw) 3031 { 3032 int status; 3033 3034 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3035 if (status) 3036 return status; 3037 3038 return ice_discover_func_caps(hw, &hw->func_caps); 3039 } 3040 3041 /** 3042 * ice_aq_manage_mac_write - manage MAC address write command 3043 * @hw: pointer to the HW struct 3044 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3045 * @flags: flags to control write behavior 3046 * @cd: pointer to command details structure or NULL 3047 * 3048 * This function is used to write MAC address to the NVM (0x0108). 3049 */ 3050 int 3051 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3052 struct ice_sq_cd *cd) 3053 { 3054 struct ice_aqc_manage_mac_write *cmd; 3055 struct ice_aq_desc desc; 3056 3057 cmd = &desc.params.mac_write; 3058 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3059 3060 cmd->flags = flags; 3061 ether_addr_copy(cmd->mac_addr, mac_addr); 3062 3063 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3064 } 3065 3066 /** 3067 * ice_aq_clear_pxe_mode 3068 * @hw: pointer to the HW struct 3069 * 3070 * Tell the firmware that the driver is taking over from PXE (0x0110). 3071 */ 3072 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3073 { 3074 struct ice_aq_desc desc; 3075 3076 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3077 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3078 3079 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3080 } 3081 3082 /** 3083 * ice_clear_pxe_mode - clear pxe operations mode 3084 * @hw: pointer to the HW struct 3085 * 3086 * Make sure all PXE mode settings are cleared, including things 3087 * like descriptor fetch/write-back mode. 3088 */ 3089 void ice_clear_pxe_mode(struct ice_hw *hw) 3090 { 3091 if (ice_check_sq_alive(hw, &hw->adminq)) 3092 ice_aq_clear_pxe_mode(hw); 3093 } 3094 3095 /** 3096 * ice_aq_set_port_params - set physical port parameters. 3097 * @pi: pointer to the port info struct 3098 * @double_vlan: if set double VLAN is enabled 3099 * @cd: pointer to command details structure or NULL 3100 * 3101 * Set Physical port parameters (0x0203) 3102 */ 3103 int 3104 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3105 struct ice_sq_cd *cd) 3106 3107 { 3108 struct ice_aqc_set_port_params *cmd; 3109 struct ice_hw *hw = pi->hw; 3110 struct ice_aq_desc desc; 3111 u16 cmd_flags = 0; 3112 3113 cmd = &desc.params.set_port_params; 3114 3115 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3116 if (double_vlan) 3117 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3118 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3119 3120 cmd->local_fwd_mode = pi->local_fwd_mode | 3121 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3122 3123 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3124 } 3125 3126 /** 3127 * ice_is_100m_speed_supported 3128 * @hw: pointer to the HW struct 3129 * 3130 * returns true if 100M speeds are supported by the device, 3131 * false otherwise. 3132 */ 3133 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3134 { 3135 switch (hw->device_id) { 3136 case ICE_DEV_ID_E822C_SGMII: 3137 case ICE_DEV_ID_E822L_SGMII: 3138 case ICE_DEV_ID_E823L_1GBE: 3139 case ICE_DEV_ID_E823C_SGMII: 3140 return true; 3141 default: 3142 return false; 3143 } 3144 } 3145 3146 /** 3147 * ice_get_link_speed_based_on_phy_type - returns link speed 3148 * @phy_type_low: lower part of phy_type 3149 * @phy_type_high: higher part of phy_type 3150 * 3151 * This helper function will convert an entry in PHY type structure 3152 * [phy_type_low, phy_type_high] to its corresponding link speed. 3153 * Note: In the structure of [phy_type_low, phy_type_high], there should 3154 * be one bit set, as this function will convert one PHY type to its 3155 * speed. 3156 * 3157 * Return: 3158 * * PHY speed for recognized PHY type 3159 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3160 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3161 */ 3162 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3163 { 3164 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3165 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3166 3167 switch (phy_type_low) { 3168 case ICE_PHY_TYPE_LOW_100BASE_TX: 3169 case ICE_PHY_TYPE_LOW_100M_SGMII: 3170 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3171 break; 3172 case ICE_PHY_TYPE_LOW_1000BASE_T: 3173 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3174 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3175 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3176 case ICE_PHY_TYPE_LOW_1G_SGMII: 3177 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3178 break; 3179 case ICE_PHY_TYPE_LOW_2500BASE_T: 3180 case ICE_PHY_TYPE_LOW_2500BASE_X: 3181 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3182 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3183 break; 3184 case ICE_PHY_TYPE_LOW_5GBASE_T: 3185 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3186 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3187 break; 3188 case ICE_PHY_TYPE_LOW_10GBASE_T: 3189 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3190 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3191 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3192 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3193 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3194 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3195 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3196 break; 3197 case ICE_PHY_TYPE_LOW_25GBASE_T: 3198 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3199 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3200 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3201 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3202 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3203 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3204 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3205 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3206 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3207 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3208 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3209 break; 3210 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3211 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3212 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3213 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3214 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3215 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3216 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3217 break; 3218 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3219 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3220 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3221 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3222 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3223 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3224 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3225 case ICE_PHY_TYPE_LOW_50G_AUI2: 3226 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3227 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3228 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3229 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3230 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3231 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3232 case ICE_PHY_TYPE_LOW_50G_AUI1: 3233 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3234 break; 3235 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3236 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3237 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3238 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3239 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3240 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3241 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3242 case ICE_PHY_TYPE_LOW_100G_AUI4: 3243 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3244 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3245 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3246 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3247 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3248 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3249 break; 3250 default: 3251 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3252 break; 3253 } 3254 3255 switch (phy_type_high) { 3256 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3257 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3258 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3259 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3260 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3261 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3262 break; 3263 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3264 case ICE_PHY_TYPE_HIGH_200G_SR4: 3265 case ICE_PHY_TYPE_HIGH_200G_FR4: 3266 case ICE_PHY_TYPE_HIGH_200G_LR4: 3267 case ICE_PHY_TYPE_HIGH_200G_DR4: 3268 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3269 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3270 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3271 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3272 break; 3273 default: 3274 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3275 break; 3276 } 3277 3278 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3279 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3280 return ICE_AQ_LINK_SPEED_UNKNOWN; 3281 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3282 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3283 return ICE_AQ_LINK_SPEED_UNKNOWN; 3284 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3285 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3286 return speed_phy_type_low; 3287 else 3288 return speed_phy_type_high; 3289 } 3290 3291 /** 3292 * ice_update_phy_type 3293 * @phy_type_low: pointer to the lower part of phy_type 3294 * @phy_type_high: pointer to the higher part of phy_type 3295 * @link_speeds_bitmap: targeted link speeds bitmap 3296 * 3297 * Note: For the link_speeds_bitmap structure, you can check it at 3298 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3299 * link_speeds_bitmap include multiple speeds. 3300 * 3301 * Each entry in this [phy_type_low, phy_type_high] structure will 3302 * present a certain link speed. This helper function will turn on bits 3303 * in [phy_type_low, phy_type_high] structure based on the value of 3304 * link_speeds_bitmap input parameter. 3305 */ 3306 void 3307 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3308 u16 link_speeds_bitmap) 3309 { 3310 u64 pt_high; 3311 u64 pt_low; 3312 int index; 3313 u16 speed; 3314 3315 /* We first check with low part of phy_type */ 3316 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3317 pt_low = BIT_ULL(index); 3318 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3319 3320 if (link_speeds_bitmap & speed) 3321 *phy_type_low |= BIT_ULL(index); 3322 } 3323 3324 /* We then check with high part of phy_type */ 3325 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3326 pt_high = BIT_ULL(index); 3327 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3328 3329 if (link_speeds_bitmap & speed) 3330 *phy_type_high |= BIT_ULL(index); 3331 } 3332 } 3333 3334 /** 3335 * ice_aq_set_phy_cfg 3336 * @hw: pointer to the HW struct 3337 * @pi: port info structure of the interested logical port 3338 * @cfg: structure with PHY configuration data to be set 3339 * @cd: pointer to command details structure or NULL 3340 * 3341 * Set the various PHY configuration parameters supported on the Port. 3342 * One or more of the Set PHY config parameters may be ignored in an MFP 3343 * mode as the PF may not have the privilege to set some of the PHY Config 3344 * parameters. This status will be indicated by the command response (0x0601). 3345 */ 3346 int 3347 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3348 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3349 { 3350 struct ice_aq_desc desc; 3351 int status; 3352 3353 if (!cfg) 3354 return -EINVAL; 3355 3356 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3357 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3358 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3359 cfg->caps); 3360 3361 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3362 } 3363 3364 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3365 desc.params.set_phy.lport_num = pi->lport; 3366 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3367 3368 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3369 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3370 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3371 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3372 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3373 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3374 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3375 cfg->low_power_ctrl_an); 3376 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3377 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3378 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3379 cfg->link_fec_opt); 3380 3381 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3382 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3383 status = 0; 3384 3385 if (!status) 3386 pi->phy.curr_user_phy_cfg = *cfg; 3387 3388 return status; 3389 } 3390 3391 /** 3392 * ice_update_link_info - update status of the HW network link 3393 * @pi: port info structure of the interested logical port 3394 */ 3395 int ice_update_link_info(struct ice_port_info *pi) 3396 { 3397 struct ice_link_status *li; 3398 int status; 3399 3400 if (!pi) 3401 return -EINVAL; 3402 3403 li = &pi->phy.link_info; 3404 3405 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3406 if (status) 3407 return status; 3408 3409 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3410 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3411 3412 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3413 if (!pcaps) 3414 return -ENOMEM; 3415 3416 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3417 pcaps, NULL); 3418 } 3419 3420 return status; 3421 } 3422 3423 /** 3424 * ice_aq_get_phy_equalization - function to read serdes equaliser 3425 * value from firmware using admin queue command. 3426 * @hw: pointer to the HW struct 3427 * @data_in: represents the serdes equalization parameter requested 3428 * @op_code: represents the serdes number and flag to represent tx or rx 3429 * @serdes_num: represents the serdes number 3430 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3431 * 3432 * Return: non-zero status on error and 0 on success. 3433 */ 3434 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3435 u8 serdes_num, int *output) 3436 { 3437 struct ice_aqc_dnl_call_command *cmd; 3438 struct ice_aqc_dnl_call buf = {}; 3439 struct ice_aq_desc desc; 3440 int err; 3441 3442 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3443 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3444 cpu_to_le16(op_code | (serdes_num & 0xF)); 3445 cmd = &desc.params.dnl_call; 3446 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3447 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF | 3448 ICE_AQ_FLAG_RD | 3449 ICE_AQ_FLAG_SI); 3450 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3451 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3452 3453 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3454 NULL); 3455 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3456 3457 return err; 3458 } 3459 3460 #define FEC_REG_PORT(port) { \ 3461 FEC_CORR_LOW_REG_PORT##port, \ 3462 FEC_CORR_HIGH_REG_PORT##port, \ 3463 FEC_UNCORR_LOW_REG_PORT##port, \ 3464 FEC_UNCORR_HIGH_REG_PORT##port, \ 3465 } 3466 3467 static const u32 fec_reg[][ICE_FEC_MAX] = { 3468 FEC_REG_PORT(0), 3469 FEC_REG_PORT(1), 3470 FEC_REG_PORT(2), 3471 FEC_REG_PORT(3) 3472 }; 3473 3474 /** 3475 * ice_aq_get_fec_stats - reads fec stats from phy 3476 * @hw: pointer to the HW struct 3477 * @pcs_quad: represents pcsquad of user input serdes 3478 * @pcs_port: represents the pcs port number part of above pcs quad 3479 * @fec_type: represents FEC stats type 3480 * @output: pointer to the caller-supplied buffer to return requested fec stats 3481 * 3482 * Return: non-zero status on error and 0 on success. 3483 */ 3484 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3485 enum ice_fec_stats_types fec_type, u32 *output) 3486 { 3487 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI); 3488 struct ice_sbq_msg_input msg = {}; 3489 u32 receiver_id, reg_offset; 3490 int err; 3491 3492 if (pcs_port > 3) 3493 return -EINVAL; 3494 3495 reg_offset = fec_reg[pcs_port][fec_type]; 3496 3497 if (pcs_quad == 0) 3498 receiver_id = FEC_RECEIVER_ID_PCS0; 3499 else if (pcs_quad == 1) 3500 receiver_id = FEC_RECEIVER_ID_PCS1; 3501 else 3502 return -EINVAL; 3503 3504 msg.msg_addr_low = lower_16_bits(reg_offset); 3505 msg.msg_addr_high = receiver_id; 3506 msg.opcode = ice_sbq_msg_rd; 3507 msg.dest_dev = rmn_0; 3508 3509 err = ice_sbq_rw_reg(hw, &msg, flag); 3510 if (err) 3511 return err; 3512 3513 *output = msg.data; 3514 return 0; 3515 } 3516 3517 /** 3518 * ice_cache_phy_user_req 3519 * @pi: port information structure 3520 * @cache_data: PHY logging data 3521 * @cache_mode: PHY logging mode 3522 * 3523 * Log the user request on (FC, FEC, SPEED) for later use. 3524 */ 3525 static void 3526 ice_cache_phy_user_req(struct ice_port_info *pi, 3527 struct ice_phy_cache_mode_data cache_data, 3528 enum ice_phy_cache_mode cache_mode) 3529 { 3530 if (!pi) 3531 return; 3532 3533 switch (cache_mode) { 3534 case ICE_FC_MODE: 3535 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3536 break; 3537 case ICE_SPEED_MODE: 3538 pi->phy.curr_user_speed_req = 3539 cache_data.data.curr_user_speed_req; 3540 break; 3541 case ICE_FEC_MODE: 3542 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3543 break; 3544 default: 3545 break; 3546 } 3547 } 3548 3549 /** 3550 * ice_caps_to_fc_mode 3551 * @caps: PHY capabilities 3552 * 3553 * Convert PHY FC capabilities to ice FC mode 3554 */ 3555 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3556 { 3557 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3558 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3559 return ICE_FC_FULL; 3560 3561 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3562 return ICE_FC_TX_PAUSE; 3563 3564 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3565 return ICE_FC_RX_PAUSE; 3566 3567 return ICE_FC_NONE; 3568 } 3569 3570 /** 3571 * ice_caps_to_fec_mode 3572 * @caps: PHY capabilities 3573 * @fec_options: Link FEC options 3574 * 3575 * Convert PHY FEC capabilities to ice FEC mode 3576 */ 3577 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3578 { 3579 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3580 return ICE_FEC_AUTO; 3581 3582 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3583 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3584 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3585 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3586 return ICE_FEC_BASER; 3587 3588 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3589 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3590 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3591 return ICE_FEC_RS; 3592 3593 return ICE_FEC_NONE; 3594 } 3595 3596 /** 3597 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3598 * @pi: port information structure 3599 * @cfg: PHY configuration data to set FC mode 3600 * @req_mode: FC mode to configure 3601 */ 3602 int 3603 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3604 enum ice_fc_mode req_mode) 3605 { 3606 struct ice_phy_cache_mode_data cache_data; 3607 u8 pause_mask = 0x0; 3608 3609 if (!pi || !cfg) 3610 return -EINVAL; 3611 3612 switch (req_mode) { 3613 case ICE_FC_FULL: 3614 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3615 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3616 break; 3617 case ICE_FC_RX_PAUSE: 3618 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3619 break; 3620 case ICE_FC_TX_PAUSE: 3621 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3622 break; 3623 default: 3624 break; 3625 } 3626 3627 /* clear the old pause settings */ 3628 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3629 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3630 3631 /* set the new capabilities */ 3632 cfg->caps |= pause_mask; 3633 3634 /* Cache user FC request */ 3635 cache_data.data.curr_user_fc_req = req_mode; 3636 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3637 3638 return 0; 3639 } 3640 3641 /** 3642 * ice_set_fc 3643 * @pi: port information structure 3644 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3645 * @ena_auto_link_update: enable automatic link update 3646 * 3647 * Set the requested flow control mode. 3648 */ 3649 int 3650 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3651 { 3652 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3653 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3654 struct ice_hw *hw; 3655 int status; 3656 3657 if (!pi || !aq_failures) 3658 return -EINVAL; 3659 3660 *aq_failures = 0; 3661 hw = pi->hw; 3662 3663 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3664 if (!pcaps) 3665 return -ENOMEM; 3666 3667 /* Get the current PHY config */ 3668 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3669 pcaps, NULL); 3670 if (status) { 3671 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3672 goto out; 3673 } 3674 3675 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3676 3677 /* Configure the set PHY data */ 3678 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3679 if (status) 3680 goto out; 3681 3682 /* If the capabilities have changed, then set the new config */ 3683 if (cfg.caps != pcaps->caps) { 3684 int retry_count, retry_max = 10; 3685 3686 /* Auto restart link so settings take effect */ 3687 if (ena_auto_link_update) 3688 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3689 3690 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3691 if (status) { 3692 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3693 goto out; 3694 } 3695 3696 /* Update the link info 3697 * It sometimes takes a really long time for link to 3698 * come back from the atomic reset. Thus, we wait a 3699 * little bit. 3700 */ 3701 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3702 status = ice_update_link_info(pi); 3703 3704 if (!status) 3705 break; 3706 3707 mdelay(100); 3708 } 3709 3710 if (status) 3711 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3712 } 3713 3714 out: 3715 return status; 3716 } 3717 3718 /** 3719 * ice_phy_caps_equals_cfg 3720 * @phy_caps: PHY capabilities 3721 * @phy_cfg: PHY configuration 3722 * 3723 * Helper function to determine if PHY capabilities matches PHY 3724 * configuration 3725 */ 3726 bool 3727 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3728 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3729 { 3730 u8 caps_mask, cfg_mask; 3731 3732 if (!phy_caps || !phy_cfg) 3733 return false; 3734 3735 /* These bits are not common between capabilities and configuration. 3736 * Do not use them to determine equality. 3737 */ 3738 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3739 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3740 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3741 3742 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3743 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3744 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3745 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3746 phy_caps->eee_cap != phy_cfg->eee_cap || 3747 phy_caps->eeer_value != phy_cfg->eeer_value || 3748 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3749 return false; 3750 3751 return true; 3752 } 3753 3754 /** 3755 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3756 * @pi: port information structure 3757 * @caps: PHY ability structure to copy date from 3758 * @cfg: PHY configuration structure to copy data to 3759 * 3760 * Helper function to copy AQC PHY get ability data to PHY set configuration 3761 * data structure 3762 */ 3763 void 3764 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3765 struct ice_aqc_get_phy_caps_data *caps, 3766 struct ice_aqc_set_phy_cfg_data *cfg) 3767 { 3768 if (!pi || !caps || !cfg) 3769 return; 3770 3771 memset(cfg, 0, sizeof(*cfg)); 3772 cfg->phy_type_low = caps->phy_type_low; 3773 cfg->phy_type_high = caps->phy_type_high; 3774 cfg->caps = caps->caps; 3775 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3776 cfg->eee_cap = caps->eee_cap; 3777 cfg->eeer_value = caps->eeer_value; 3778 cfg->link_fec_opt = caps->link_fec_options; 3779 cfg->module_compliance_enforcement = 3780 caps->module_compliance_enforcement; 3781 } 3782 3783 /** 3784 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3785 * @pi: port information structure 3786 * @cfg: PHY configuration data to set FEC mode 3787 * @fec: FEC mode to configure 3788 */ 3789 int 3790 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3791 enum ice_fec_mode fec) 3792 { 3793 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3794 struct ice_hw *hw; 3795 int status; 3796 3797 if (!pi || !cfg) 3798 return -EINVAL; 3799 3800 hw = pi->hw; 3801 3802 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3803 if (!pcaps) 3804 return -ENOMEM; 3805 3806 status = ice_aq_get_phy_caps(pi, false, 3807 (ice_fw_supports_report_dflt_cfg(hw) ? 3808 ICE_AQC_REPORT_DFLT_CFG : 3809 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3810 if (status) 3811 goto out; 3812 3813 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3814 cfg->link_fec_opt = pcaps->link_fec_options; 3815 3816 switch (fec) { 3817 case ICE_FEC_BASER: 3818 /* Clear RS bits, and AND BASE-R ability 3819 * bits and OR request bits. 3820 */ 3821 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3822 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3823 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3824 ICE_AQC_PHY_FEC_25G_KR_REQ; 3825 break; 3826 case ICE_FEC_RS: 3827 /* Clear BASE-R bits, and AND RS ability 3828 * bits and OR request bits. 3829 */ 3830 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3831 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3832 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3833 break; 3834 case ICE_FEC_NONE: 3835 /* Clear all FEC option bits. */ 3836 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3837 break; 3838 case ICE_FEC_AUTO: 3839 /* AND auto FEC bit, and all caps bits. */ 3840 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3841 cfg->link_fec_opt |= pcaps->link_fec_options; 3842 break; 3843 default: 3844 status = -EINVAL; 3845 break; 3846 } 3847 3848 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3849 !ice_fw_supports_report_dflt_cfg(hw)) { 3850 struct ice_link_default_override_tlv tlv = { 0 }; 3851 3852 status = ice_get_link_default_override(&tlv, pi); 3853 if (status) 3854 goto out; 3855 3856 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3857 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3858 cfg->link_fec_opt = tlv.fec_options; 3859 } 3860 3861 out: 3862 return status; 3863 } 3864 3865 /** 3866 * ice_get_link_status - get status of the HW network link 3867 * @pi: port information structure 3868 * @link_up: pointer to bool (true/false = linkup/linkdown) 3869 * 3870 * Variable link_up is true if link is up, false if link is down. 3871 * The variable link_up is invalid if status is non zero. As a 3872 * result of this call, link status reporting becomes enabled 3873 */ 3874 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3875 { 3876 struct ice_phy_info *phy_info; 3877 int status = 0; 3878 3879 if (!pi || !link_up) 3880 return -EINVAL; 3881 3882 phy_info = &pi->phy; 3883 3884 if (phy_info->get_link_info) { 3885 status = ice_update_link_info(pi); 3886 3887 if (status) 3888 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3889 status); 3890 } 3891 3892 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3893 3894 return status; 3895 } 3896 3897 /** 3898 * ice_aq_set_link_restart_an 3899 * @pi: pointer to the port information structure 3900 * @ena_link: if true: enable link, if false: disable link 3901 * @cd: pointer to command details structure or NULL 3902 * 3903 * Sets up the link and restarts the Auto-Negotiation over the link. 3904 */ 3905 int 3906 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3907 struct ice_sq_cd *cd) 3908 { 3909 struct ice_aqc_restart_an *cmd; 3910 struct ice_aq_desc desc; 3911 3912 cmd = &desc.params.restart_an; 3913 3914 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3915 3916 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3917 cmd->lport_num = pi->lport; 3918 if (ena_link) 3919 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3920 else 3921 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3922 3923 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3924 } 3925 3926 /** 3927 * ice_aq_set_event_mask 3928 * @hw: pointer to the HW struct 3929 * @port_num: port number of the physical function 3930 * @mask: event mask to be set 3931 * @cd: pointer to command details structure or NULL 3932 * 3933 * Set event mask (0x0613) 3934 */ 3935 int 3936 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3937 struct ice_sq_cd *cd) 3938 { 3939 struct ice_aqc_set_event_mask *cmd; 3940 struct ice_aq_desc desc; 3941 3942 cmd = &desc.params.set_event_mask; 3943 3944 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3945 3946 cmd->lport_num = port_num; 3947 3948 cmd->event_mask = cpu_to_le16(mask); 3949 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3950 } 3951 3952 /** 3953 * ice_aq_set_mac_loopback 3954 * @hw: pointer to the HW struct 3955 * @ena_lpbk: Enable or Disable loopback 3956 * @cd: pointer to command details structure or NULL 3957 * 3958 * Enable/disable loopback on a given port 3959 */ 3960 int 3961 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3962 { 3963 struct ice_aqc_set_mac_lb *cmd; 3964 struct ice_aq_desc desc; 3965 3966 cmd = &desc.params.set_mac_lb; 3967 3968 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3969 if (ena_lpbk) 3970 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3971 3972 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3973 } 3974 3975 /** 3976 * ice_aq_set_port_id_led 3977 * @pi: pointer to the port information 3978 * @is_orig_mode: is this LED set to original mode (by the net-list) 3979 * @cd: pointer to command details structure or NULL 3980 * 3981 * Set LED value for the given port (0x06e9) 3982 */ 3983 int 3984 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3985 struct ice_sq_cd *cd) 3986 { 3987 struct ice_aqc_set_port_id_led *cmd; 3988 struct ice_hw *hw = pi->hw; 3989 struct ice_aq_desc desc; 3990 3991 cmd = &desc.params.set_port_id_led; 3992 3993 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3994 3995 if (is_orig_mode) 3996 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3997 else 3998 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3999 4000 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4001 } 4002 4003 /** 4004 * ice_aq_get_port_options 4005 * @hw: pointer to the HW struct 4006 * @options: buffer for the resultant port options 4007 * @option_count: input - size of the buffer in port options structures, 4008 * output - number of returned port options 4009 * @lport: logical port to call the command with (optional) 4010 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4011 * when PF owns more than 1 port it must be true 4012 * @active_option_idx: index of active port option in returned buffer 4013 * @active_option_valid: active option in returned buffer is valid 4014 * @pending_option_idx: index of pending port option in returned buffer 4015 * @pending_option_valid: pending option in returned buffer is valid 4016 * 4017 * Calls Get Port Options AQC (0x06ea) and verifies result. 4018 */ 4019 int 4020 ice_aq_get_port_options(struct ice_hw *hw, 4021 struct ice_aqc_get_port_options_elem *options, 4022 u8 *option_count, u8 lport, bool lport_valid, 4023 u8 *active_option_idx, bool *active_option_valid, 4024 u8 *pending_option_idx, bool *pending_option_valid) 4025 { 4026 struct ice_aqc_get_port_options *cmd; 4027 struct ice_aq_desc desc; 4028 int status; 4029 u8 i; 4030 4031 /* options buffer shall be able to hold max returned options */ 4032 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4033 return -EINVAL; 4034 4035 cmd = &desc.params.get_port_options; 4036 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4037 4038 if (lport_valid) 4039 cmd->lport_num = lport; 4040 cmd->lport_num_valid = lport_valid; 4041 4042 status = ice_aq_send_cmd(hw, &desc, options, 4043 *option_count * sizeof(*options), NULL); 4044 if (status) 4045 return status; 4046 4047 /* verify direct FW response & set output parameters */ 4048 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4049 cmd->port_options_count); 4050 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4051 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4052 cmd->port_options); 4053 if (*active_option_valid) { 4054 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4055 cmd->port_options); 4056 if (*active_option_idx > (*option_count - 1)) 4057 return -EIO; 4058 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4059 *active_option_idx); 4060 } 4061 4062 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4063 cmd->pending_port_option_status); 4064 if (*pending_option_valid) { 4065 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4066 cmd->pending_port_option_status); 4067 if (*pending_option_idx > (*option_count - 1)) 4068 return -EIO; 4069 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4070 *pending_option_idx); 4071 } 4072 4073 /* mask output options fields */ 4074 for (i = 0; i < *option_count; i++) { 4075 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4076 options[i].pmd); 4077 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4078 options[i].max_lane_speed); 4079 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4080 options[i].pmd, options[i].max_lane_speed); 4081 } 4082 4083 return 0; 4084 } 4085 4086 /** 4087 * ice_aq_set_port_option 4088 * @hw: pointer to the HW struct 4089 * @lport: logical port to call the command with 4090 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4091 * when PF owns more than 1 port it must be true 4092 * @new_option: new port option to be written 4093 * 4094 * Calls Set Port Options AQC (0x06eb). 4095 */ 4096 int 4097 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4098 u8 new_option) 4099 { 4100 struct ice_aqc_set_port_option *cmd; 4101 struct ice_aq_desc desc; 4102 4103 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4104 return -EINVAL; 4105 4106 cmd = &desc.params.set_port_option; 4107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4108 4109 if (lport_valid) 4110 cmd->lport_num = lport; 4111 4112 cmd->lport_num_valid = lport_valid; 4113 cmd->selected_port_option = new_option; 4114 4115 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4116 } 4117 4118 /** 4119 * ice_aq_sff_eeprom 4120 * @hw: pointer to the HW struct 4121 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4122 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4123 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4124 * @page: QSFP page 4125 * @set_page: set or ignore the page 4126 * @data: pointer to data buffer to be read/written to the I2C device. 4127 * @length: 1-16 for read, 1 for write. 4128 * @write: 0 read, 1 for write. 4129 * @cd: pointer to command details structure or NULL 4130 * 4131 * Read/Write SFF EEPROM (0x06EE) 4132 */ 4133 int 4134 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4135 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4136 bool write, struct ice_sq_cd *cd) 4137 { 4138 struct ice_aqc_sff_eeprom *cmd; 4139 struct ice_aq_desc desc; 4140 u16 i2c_bus_addr; 4141 int status; 4142 4143 if (!data || (mem_addr & 0xff00)) 4144 return -EINVAL; 4145 4146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4147 cmd = &desc.params.read_write_sff_param; 4148 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4149 cmd->lport_num = (u8)(lport & 0xff); 4150 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4151 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4152 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4153 if (write) 4154 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4155 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4156 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4157 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4158 4159 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4160 return status; 4161 } 4162 4163 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4164 { 4165 switch (type) { 4166 case ICE_LUT_VSI: 4167 return ICE_LUT_VSI_SIZE; 4168 case ICE_LUT_GLOBAL: 4169 return ICE_LUT_GLOBAL_SIZE; 4170 case ICE_LUT_PF: 4171 return ICE_LUT_PF_SIZE; 4172 } 4173 WARN_ONCE(1, "incorrect type passed"); 4174 return ICE_LUT_VSI_SIZE; 4175 } 4176 4177 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4178 { 4179 switch (size) { 4180 case ICE_LUT_VSI_SIZE: 4181 return ICE_AQC_LUT_SIZE_SMALL; 4182 case ICE_LUT_GLOBAL_SIZE: 4183 return ICE_AQC_LUT_SIZE_512; 4184 case ICE_LUT_PF_SIZE: 4185 return ICE_AQC_LUT_SIZE_2K; 4186 } 4187 WARN_ONCE(1, "incorrect size passed"); 4188 return 0; 4189 } 4190 4191 /** 4192 * __ice_aq_get_set_rss_lut 4193 * @hw: pointer to the hardware structure 4194 * @params: RSS LUT parameters 4195 * @set: set true to set the table, false to get the table 4196 * 4197 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4198 */ 4199 static int 4200 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4201 struct ice_aq_get_set_rss_lut_params *params, bool set) 4202 { 4203 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4204 enum ice_lut_type lut_type = params->lut_type; 4205 struct ice_aqc_get_set_rss_lut *desc_params; 4206 enum ice_aqc_lut_flags flags; 4207 enum ice_lut_size lut_size; 4208 struct ice_aq_desc desc; 4209 u8 *lut = params->lut; 4210 4211 4212 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4213 return -EINVAL; 4214 4215 lut_size = ice_lut_type_to_size(lut_type); 4216 if (lut_size > params->lut_size) 4217 return -EINVAL; 4218 else if (set && lut_size != params->lut_size) 4219 return -EINVAL; 4220 4221 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4222 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4223 if (set) 4224 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4225 4226 desc_params = &desc.params.get_set_rss_lut; 4227 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4228 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4229 4230 if (lut_type == ICE_LUT_GLOBAL) 4231 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4232 params->global_lut_id); 4233 4234 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4235 desc_params->flags = cpu_to_le16(flags); 4236 4237 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4238 } 4239 4240 /** 4241 * ice_aq_get_rss_lut 4242 * @hw: pointer to the hardware structure 4243 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4244 * 4245 * get the RSS lookup table, PF or VSI type 4246 */ 4247 int 4248 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4249 { 4250 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4251 } 4252 4253 /** 4254 * ice_aq_set_rss_lut 4255 * @hw: pointer to the hardware structure 4256 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4257 * 4258 * set the RSS lookup table, PF or VSI type 4259 */ 4260 int 4261 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4262 { 4263 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4264 } 4265 4266 /** 4267 * __ice_aq_get_set_rss_key 4268 * @hw: pointer to the HW struct 4269 * @vsi_id: VSI FW index 4270 * @key: pointer to key info struct 4271 * @set: set true to set the key, false to get the key 4272 * 4273 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4274 */ 4275 static int 4276 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4277 struct ice_aqc_get_set_rss_keys *key, bool set) 4278 { 4279 struct ice_aqc_get_set_rss_key *desc_params; 4280 u16 key_size = sizeof(*key); 4281 struct ice_aq_desc desc; 4282 4283 if (set) { 4284 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4285 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4286 } else { 4287 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4288 } 4289 4290 desc_params = &desc.params.get_set_rss_key; 4291 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4292 4293 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4294 } 4295 4296 /** 4297 * ice_aq_get_rss_key 4298 * @hw: pointer to the HW struct 4299 * @vsi_handle: software VSI handle 4300 * @key: pointer to key info struct 4301 * 4302 * get the RSS key per VSI 4303 */ 4304 int 4305 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4306 struct ice_aqc_get_set_rss_keys *key) 4307 { 4308 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4309 return -EINVAL; 4310 4311 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4312 key, false); 4313 } 4314 4315 /** 4316 * ice_aq_set_rss_key 4317 * @hw: pointer to the HW struct 4318 * @vsi_handle: software VSI handle 4319 * @keys: pointer to key info struct 4320 * 4321 * set the RSS key per VSI 4322 */ 4323 int 4324 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4325 struct ice_aqc_get_set_rss_keys *keys) 4326 { 4327 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4328 return -EINVAL; 4329 4330 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4331 keys, true); 4332 } 4333 4334 /** 4335 * ice_aq_add_lan_txq 4336 * @hw: pointer to the hardware structure 4337 * @num_qgrps: Number of added queue groups 4338 * @qg_list: list of queue groups to be added 4339 * @buf_size: size of buffer for indirect command 4340 * @cd: pointer to command details structure or NULL 4341 * 4342 * Add Tx LAN queue (0x0C30) 4343 * 4344 * NOTE: 4345 * Prior to calling add Tx LAN queue: 4346 * Initialize the following as part of the Tx queue context: 4347 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4348 * Cache profile and Packet shaper profile. 4349 * 4350 * After add Tx LAN queue AQ command is completed: 4351 * Interrupts should be associated with specific queues, 4352 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4353 * flow. 4354 */ 4355 static int 4356 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4357 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4358 struct ice_sq_cd *cd) 4359 { 4360 struct ice_aqc_add_tx_qgrp *list; 4361 struct ice_aqc_add_txqs *cmd; 4362 struct ice_aq_desc desc; 4363 u16 i, sum_size = 0; 4364 4365 cmd = &desc.params.add_txqs; 4366 4367 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4368 4369 if (!qg_list) 4370 return -EINVAL; 4371 4372 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4373 return -EINVAL; 4374 4375 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4376 sum_size += struct_size(list, txqs, list->num_txqs); 4377 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4378 list->num_txqs); 4379 } 4380 4381 if (buf_size != sum_size) 4382 return -EINVAL; 4383 4384 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4385 4386 cmd->num_qgrps = num_qgrps; 4387 4388 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4389 } 4390 4391 /** 4392 * ice_aq_dis_lan_txq 4393 * @hw: pointer to the hardware structure 4394 * @num_qgrps: number of groups in the list 4395 * @qg_list: the list of groups to disable 4396 * @buf_size: the total size of the qg_list buffer in bytes 4397 * @rst_src: if called due to reset, specifies the reset source 4398 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4399 * @cd: pointer to command details structure or NULL 4400 * 4401 * Disable LAN Tx queue (0x0C31) 4402 */ 4403 static int 4404 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4405 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4406 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4407 struct ice_sq_cd *cd) 4408 { 4409 struct ice_aqc_dis_txq_item *item; 4410 struct ice_aqc_dis_txqs *cmd; 4411 struct ice_aq_desc desc; 4412 u16 vmvf_and_timeout; 4413 u16 i, sz = 0; 4414 int status; 4415 4416 cmd = &desc.params.dis_txqs; 4417 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4418 4419 /* qg_list can be NULL only in VM/VF reset flow */ 4420 if (!qg_list && !rst_src) 4421 return -EINVAL; 4422 4423 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4424 return -EINVAL; 4425 4426 cmd->num_entries = num_qgrps; 4427 4428 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4429 4430 switch (rst_src) { 4431 case ICE_VM_RESET: 4432 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4433 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4434 break; 4435 case ICE_VF_RESET: 4436 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4437 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4438 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4439 ICE_AQC_Q_DIS_VMVF_NUM_M; 4440 break; 4441 case ICE_NO_RESET: 4442 default: 4443 break; 4444 } 4445 4446 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4447 4448 /* flush pipe on time out */ 4449 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4450 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4451 if (!qg_list) 4452 goto do_aq; 4453 4454 /* set RD bit to indicate that command buffer is provided by the driver 4455 * and it needs to be read by the firmware 4456 */ 4457 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4458 4459 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4460 u16 item_size = struct_size(item, q_id, item->num_qs); 4461 4462 /* If the num of queues is even, add 2 bytes of padding */ 4463 if ((item->num_qs % 2) == 0) 4464 item_size += 2; 4465 4466 sz += item_size; 4467 4468 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4469 } 4470 4471 if (buf_size != sz) 4472 return -EINVAL; 4473 4474 do_aq: 4475 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4476 if (status) { 4477 if (!qg_list) 4478 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4479 vmvf_num, hw->adminq.sq_last_status); 4480 else 4481 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4482 le16_to_cpu(qg_list[0].q_id[0]), 4483 hw->adminq.sq_last_status); 4484 } 4485 return status; 4486 } 4487 4488 /** 4489 * ice_aq_cfg_lan_txq 4490 * @hw: pointer to the hardware structure 4491 * @buf: buffer for command 4492 * @buf_size: size of buffer in bytes 4493 * @num_qs: number of queues being configured 4494 * @oldport: origination lport 4495 * @newport: destination lport 4496 * @cd: pointer to command details structure or NULL 4497 * 4498 * Move/Configure LAN Tx queue (0x0C32) 4499 * 4500 * There is a better AQ command to use for moving nodes, so only coding 4501 * this one for configuring the node. 4502 */ 4503 int 4504 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4505 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4506 struct ice_sq_cd *cd) 4507 { 4508 struct ice_aqc_cfg_txqs *cmd; 4509 struct ice_aq_desc desc; 4510 int status; 4511 4512 cmd = &desc.params.cfg_txqs; 4513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4514 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4515 4516 if (!buf) 4517 return -EINVAL; 4518 4519 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4520 cmd->num_qs = num_qs; 4521 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4522 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4523 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4524 cmd->blocked_cgds = 0; 4525 4526 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4527 if (status) 4528 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4529 hw->adminq.sq_last_status); 4530 return status; 4531 } 4532 4533 /** 4534 * ice_aq_add_rdma_qsets 4535 * @hw: pointer to the hardware structure 4536 * @num_qset_grps: Number of RDMA Qset groups 4537 * @qset_list: list of Qset groups to be added 4538 * @buf_size: size of buffer for indirect command 4539 * @cd: pointer to command details structure or NULL 4540 * 4541 * Add Tx RDMA Qsets (0x0C33) 4542 */ 4543 static int 4544 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4545 struct ice_aqc_add_rdma_qset_data *qset_list, 4546 u16 buf_size, struct ice_sq_cd *cd) 4547 { 4548 struct ice_aqc_add_rdma_qset_data *list; 4549 struct ice_aqc_add_rdma_qset *cmd; 4550 struct ice_aq_desc desc; 4551 u16 i, sum_size = 0; 4552 4553 cmd = &desc.params.add_rdma_qset; 4554 4555 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4556 4557 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4558 return -EINVAL; 4559 4560 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4561 u16 num_qsets = le16_to_cpu(list->num_qsets); 4562 4563 sum_size += struct_size(list, rdma_qsets, num_qsets); 4564 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4565 num_qsets); 4566 } 4567 4568 if (buf_size != sum_size) 4569 return -EINVAL; 4570 4571 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4572 4573 cmd->num_qset_grps = num_qset_grps; 4574 4575 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4576 } 4577 4578 /* End of FW Admin Queue command wrappers */ 4579 4580 /** 4581 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4582 * @hw: pointer to the HW struct 4583 * @vsi_handle: software VSI handle 4584 * @tc: TC number 4585 * @q_handle: software queue handle 4586 */ 4587 struct ice_q_ctx * 4588 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4589 { 4590 struct ice_vsi_ctx *vsi; 4591 struct ice_q_ctx *q_ctx; 4592 4593 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4594 if (!vsi) 4595 return NULL; 4596 if (q_handle >= vsi->num_lan_q_entries[tc]) 4597 return NULL; 4598 if (!vsi->lan_q_ctx[tc]) 4599 return NULL; 4600 q_ctx = vsi->lan_q_ctx[tc]; 4601 return &q_ctx[q_handle]; 4602 } 4603 4604 /** 4605 * ice_ena_vsi_txq 4606 * @pi: port information structure 4607 * @vsi_handle: software VSI handle 4608 * @tc: TC number 4609 * @q_handle: software queue handle 4610 * @num_qgrps: Number of added queue groups 4611 * @buf: list of queue groups to be added 4612 * @buf_size: size of buffer for indirect command 4613 * @cd: pointer to command details structure or NULL 4614 * 4615 * This function adds one LAN queue 4616 */ 4617 int 4618 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4619 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4620 struct ice_sq_cd *cd) 4621 { 4622 struct ice_aqc_txsched_elem_data node = { 0 }; 4623 struct ice_sched_node *parent; 4624 struct ice_q_ctx *q_ctx; 4625 struct ice_hw *hw; 4626 int status; 4627 4628 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4629 return -EIO; 4630 4631 if (num_qgrps > 1 || buf->num_txqs > 1) 4632 return -ENOSPC; 4633 4634 hw = pi->hw; 4635 4636 if (!ice_is_vsi_valid(hw, vsi_handle)) 4637 return -EINVAL; 4638 4639 mutex_lock(&pi->sched_lock); 4640 4641 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4642 if (!q_ctx) { 4643 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4644 q_handle); 4645 status = -EINVAL; 4646 goto ena_txq_exit; 4647 } 4648 4649 /* find a parent node */ 4650 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4651 ICE_SCHED_NODE_OWNER_LAN); 4652 if (!parent) { 4653 status = -EINVAL; 4654 goto ena_txq_exit; 4655 } 4656 4657 buf->parent_teid = parent->info.node_teid; 4658 node.parent_teid = parent->info.node_teid; 4659 /* Mark that the values in the "generic" section as valid. The default 4660 * value in the "generic" section is zero. This means that : 4661 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4662 * - 0 priority among siblings, indicated by Bit 1-3. 4663 * - WFQ, indicated by Bit 4. 4664 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4665 * Bit 5-6. 4666 * - Bit 7 is reserved. 4667 * Without setting the generic section as valid in valid_sections, the 4668 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4669 */ 4670 buf->txqs[0].info.valid_sections = 4671 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4672 ICE_AQC_ELEM_VALID_EIR; 4673 buf->txqs[0].info.generic = 0; 4674 buf->txqs[0].info.cir_bw.bw_profile_idx = 4675 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4676 buf->txqs[0].info.cir_bw.bw_alloc = 4677 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4678 buf->txqs[0].info.eir_bw.bw_profile_idx = 4679 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4680 buf->txqs[0].info.eir_bw.bw_alloc = 4681 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4682 4683 /* add the LAN queue */ 4684 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4685 if (status) { 4686 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4687 le16_to_cpu(buf->txqs[0].txq_id), 4688 hw->adminq.sq_last_status); 4689 goto ena_txq_exit; 4690 } 4691 4692 node.node_teid = buf->txqs[0].q_teid; 4693 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4694 q_ctx->q_handle = q_handle; 4695 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4696 4697 /* add a leaf node into scheduler tree queue layer */ 4698 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4699 if (!status) 4700 status = ice_sched_replay_q_bw(pi, q_ctx); 4701 4702 ena_txq_exit: 4703 mutex_unlock(&pi->sched_lock); 4704 return status; 4705 } 4706 4707 /** 4708 * ice_dis_vsi_txq 4709 * @pi: port information structure 4710 * @vsi_handle: software VSI handle 4711 * @tc: TC number 4712 * @num_queues: number of queues 4713 * @q_handles: pointer to software queue handle array 4714 * @q_ids: pointer to the q_id array 4715 * @q_teids: pointer to queue node teids 4716 * @rst_src: if called due to reset, specifies the reset source 4717 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4718 * @cd: pointer to command details structure or NULL 4719 * 4720 * This function removes queues and their corresponding nodes in SW DB 4721 */ 4722 int 4723 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4724 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4725 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4726 struct ice_sq_cd *cd) 4727 { 4728 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4729 u16 i, buf_size = __struct_size(qg_list); 4730 struct ice_q_ctx *q_ctx; 4731 int status = -ENOENT; 4732 struct ice_hw *hw; 4733 4734 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4735 return -EIO; 4736 4737 hw = pi->hw; 4738 4739 if (!num_queues) { 4740 /* if queue is disabled already yet the disable queue command 4741 * has to be sent to complete the VF reset, then call 4742 * ice_aq_dis_lan_txq without any queue information 4743 */ 4744 if (rst_src) 4745 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4746 vmvf_num, NULL); 4747 return -EIO; 4748 } 4749 4750 mutex_lock(&pi->sched_lock); 4751 4752 for (i = 0; i < num_queues; i++) { 4753 struct ice_sched_node *node; 4754 4755 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4756 if (!node) 4757 continue; 4758 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4759 if (!q_ctx) { 4760 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4761 q_handles[i]); 4762 continue; 4763 } 4764 if (q_ctx->q_handle != q_handles[i]) { 4765 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4766 q_ctx->q_handle, q_handles[i]); 4767 continue; 4768 } 4769 qg_list->parent_teid = node->info.parent_teid; 4770 qg_list->num_qs = 1; 4771 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4772 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4773 vmvf_num, cd); 4774 4775 if (status) 4776 break; 4777 ice_free_sched_node(pi, node); 4778 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4779 q_ctx->q_teid = ICE_INVAL_TEID; 4780 } 4781 mutex_unlock(&pi->sched_lock); 4782 return status; 4783 } 4784 4785 /** 4786 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4787 * @pi: port information structure 4788 * @vsi_handle: software VSI handle 4789 * @tc_bitmap: TC bitmap 4790 * @maxqs: max queues array per TC 4791 * @owner: LAN or RDMA 4792 * 4793 * This function adds/updates the VSI queues per TC. 4794 */ 4795 static int 4796 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4797 u16 *maxqs, u8 owner) 4798 { 4799 int status = 0; 4800 u8 i; 4801 4802 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4803 return -EIO; 4804 4805 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4806 return -EINVAL; 4807 4808 mutex_lock(&pi->sched_lock); 4809 4810 ice_for_each_traffic_class(i) { 4811 /* configuration is possible only if TC node is present */ 4812 if (!ice_sched_get_tc_node(pi, i)) 4813 continue; 4814 4815 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4816 ice_is_tc_ena(tc_bitmap, i)); 4817 if (status) 4818 break; 4819 } 4820 4821 mutex_unlock(&pi->sched_lock); 4822 return status; 4823 } 4824 4825 /** 4826 * ice_cfg_vsi_lan - configure VSI LAN queues 4827 * @pi: port information structure 4828 * @vsi_handle: software VSI handle 4829 * @tc_bitmap: TC bitmap 4830 * @max_lanqs: max LAN queues array per TC 4831 * 4832 * This function adds/updates the VSI LAN queues per TC. 4833 */ 4834 int 4835 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4836 u16 *max_lanqs) 4837 { 4838 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4839 ICE_SCHED_NODE_OWNER_LAN); 4840 } 4841 4842 /** 4843 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4844 * @pi: port information structure 4845 * @vsi_handle: software VSI handle 4846 * @tc_bitmap: TC bitmap 4847 * @max_rdmaqs: max RDMA queues array per TC 4848 * 4849 * This function adds/updates the VSI RDMA queues per TC. 4850 */ 4851 int 4852 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4853 u16 *max_rdmaqs) 4854 { 4855 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4856 ICE_SCHED_NODE_OWNER_RDMA); 4857 } 4858 4859 /** 4860 * ice_ena_vsi_rdma_qset 4861 * @pi: port information structure 4862 * @vsi_handle: software VSI handle 4863 * @tc: TC number 4864 * @rdma_qset: pointer to RDMA Qset 4865 * @num_qsets: number of RDMA Qsets 4866 * @qset_teid: pointer to Qset node TEIDs 4867 * 4868 * This function adds RDMA Qset 4869 */ 4870 int 4871 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4872 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4873 { 4874 struct ice_aqc_txsched_elem_data node = { 0 }; 4875 struct ice_aqc_add_rdma_qset_data *buf; 4876 struct ice_sched_node *parent; 4877 struct ice_hw *hw; 4878 u16 i, buf_size; 4879 int ret; 4880 4881 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4882 return -EIO; 4883 hw = pi->hw; 4884 4885 if (!ice_is_vsi_valid(hw, vsi_handle)) 4886 return -EINVAL; 4887 4888 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4889 buf = kzalloc(buf_size, GFP_KERNEL); 4890 if (!buf) 4891 return -ENOMEM; 4892 mutex_lock(&pi->sched_lock); 4893 4894 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4895 ICE_SCHED_NODE_OWNER_RDMA); 4896 if (!parent) { 4897 ret = -EINVAL; 4898 goto rdma_error_exit; 4899 } 4900 buf->parent_teid = parent->info.node_teid; 4901 node.parent_teid = parent->info.node_teid; 4902 4903 buf->num_qsets = cpu_to_le16(num_qsets); 4904 for (i = 0; i < num_qsets; i++) { 4905 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4906 buf->rdma_qsets[i].info.valid_sections = 4907 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4908 ICE_AQC_ELEM_VALID_EIR; 4909 buf->rdma_qsets[i].info.generic = 0; 4910 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4911 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4912 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4913 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4914 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4915 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4916 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4917 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4918 } 4919 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4920 if (ret) { 4921 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4922 goto rdma_error_exit; 4923 } 4924 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4925 for (i = 0; i < num_qsets; i++) { 4926 node.node_teid = buf->rdma_qsets[i].qset_teid; 4927 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4928 &node, NULL); 4929 if (ret) 4930 break; 4931 qset_teid[i] = le32_to_cpu(node.node_teid); 4932 } 4933 rdma_error_exit: 4934 mutex_unlock(&pi->sched_lock); 4935 kfree(buf); 4936 return ret; 4937 } 4938 4939 /** 4940 * ice_dis_vsi_rdma_qset - free RDMA resources 4941 * @pi: port_info struct 4942 * @count: number of RDMA Qsets to free 4943 * @qset_teid: TEID of Qset node 4944 * @q_id: list of queue IDs being disabled 4945 */ 4946 int 4947 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4948 u16 *q_id) 4949 { 4950 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4951 u16 qg_size = __struct_size(qg_list); 4952 struct ice_hw *hw; 4953 int status = 0; 4954 int i; 4955 4956 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4957 return -EIO; 4958 4959 hw = pi->hw; 4960 4961 mutex_lock(&pi->sched_lock); 4962 4963 for (i = 0; i < count; i++) { 4964 struct ice_sched_node *node; 4965 4966 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4967 if (!node) 4968 continue; 4969 4970 qg_list->parent_teid = node->info.parent_teid; 4971 qg_list->num_qs = 1; 4972 qg_list->q_id[0] = 4973 cpu_to_le16(q_id[i] | 4974 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4975 4976 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4977 ICE_NO_RESET, 0, NULL); 4978 if (status) 4979 break; 4980 4981 ice_free_sched_node(pi, node); 4982 } 4983 4984 mutex_unlock(&pi->sched_lock); 4985 return status; 4986 } 4987 4988 /** 4989 * ice_aq_get_cgu_abilities - get cgu abilities 4990 * @hw: pointer to the HW struct 4991 * @abilities: CGU abilities 4992 * 4993 * Get CGU abilities (0x0C61) 4994 * Return: 0 on success or negative value on failure. 4995 */ 4996 int 4997 ice_aq_get_cgu_abilities(struct ice_hw *hw, 4998 struct ice_aqc_get_cgu_abilities *abilities) 4999 { 5000 struct ice_aq_desc desc; 5001 5002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5003 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5004 } 5005 5006 /** 5007 * ice_aq_set_input_pin_cfg - set input pin config 5008 * @hw: pointer to the HW struct 5009 * @input_idx: Input index 5010 * @flags1: Input flags 5011 * @flags2: Input flags 5012 * @freq: Frequency in Hz 5013 * @phase_delay: Delay in ps 5014 * 5015 * Set CGU input config (0x0C62) 5016 * Return: 0 on success or negative value on failure. 5017 */ 5018 int 5019 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5020 u32 freq, s32 phase_delay) 5021 { 5022 struct ice_aqc_set_cgu_input_config *cmd; 5023 struct ice_aq_desc desc; 5024 5025 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5026 cmd = &desc.params.set_cgu_input_config; 5027 cmd->input_idx = input_idx; 5028 cmd->flags1 = flags1; 5029 cmd->flags2 = flags2; 5030 cmd->freq = cpu_to_le32(freq); 5031 cmd->phase_delay = cpu_to_le32(phase_delay); 5032 5033 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5034 } 5035 5036 /** 5037 * ice_aq_get_input_pin_cfg - get input pin config 5038 * @hw: pointer to the HW struct 5039 * @input_idx: Input index 5040 * @status: Pin status 5041 * @type: Pin type 5042 * @flags1: Input flags 5043 * @flags2: Input flags 5044 * @freq: Frequency in Hz 5045 * @phase_delay: Delay in ps 5046 * 5047 * Get CGU input config (0x0C63) 5048 * Return: 0 on success or negative value on failure. 5049 */ 5050 int 5051 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5052 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5053 { 5054 struct ice_aqc_get_cgu_input_config *cmd; 5055 struct ice_aq_desc desc; 5056 int ret; 5057 5058 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5059 cmd = &desc.params.get_cgu_input_config; 5060 cmd->input_idx = input_idx; 5061 5062 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5063 if (!ret) { 5064 if (status) 5065 *status = cmd->status; 5066 if (type) 5067 *type = cmd->type; 5068 if (flags1) 5069 *flags1 = cmd->flags1; 5070 if (flags2) 5071 *flags2 = cmd->flags2; 5072 if (freq) 5073 *freq = le32_to_cpu(cmd->freq); 5074 if (phase_delay) 5075 *phase_delay = le32_to_cpu(cmd->phase_delay); 5076 } 5077 5078 return ret; 5079 } 5080 5081 /** 5082 * ice_aq_set_output_pin_cfg - set output pin config 5083 * @hw: pointer to the HW struct 5084 * @output_idx: Output index 5085 * @flags: Output flags 5086 * @src_sel: Index of DPLL block 5087 * @freq: Output frequency 5088 * @phase_delay: Output phase compensation 5089 * 5090 * Set CGU output config (0x0C64) 5091 * Return: 0 on success or negative value on failure. 5092 */ 5093 int 5094 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5095 u8 src_sel, u32 freq, s32 phase_delay) 5096 { 5097 struct ice_aqc_set_cgu_output_config *cmd; 5098 struct ice_aq_desc desc; 5099 5100 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5101 cmd = &desc.params.set_cgu_output_config; 5102 cmd->output_idx = output_idx; 5103 cmd->flags = flags; 5104 cmd->src_sel = src_sel; 5105 cmd->freq = cpu_to_le32(freq); 5106 cmd->phase_delay = cpu_to_le32(phase_delay); 5107 5108 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5109 } 5110 5111 /** 5112 * ice_aq_get_output_pin_cfg - get output pin config 5113 * @hw: pointer to the HW struct 5114 * @output_idx: Output index 5115 * @flags: Output flags 5116 * @src_sel: Internal DPLL source 5117 * @freq: Output frequency 5118 * @src_freq: Source frequency 5119 * 5120 * Get CGU output config (0x0C65) 5121 * Return: 0 on success or negative value on failure. 5122 */ 5123 int 5124 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5125 u8 *src_sel, u32 *freq, u32 *src_freq) 5126 { 5127 struct ice_aqc_get_cgu_output_config *cmd; 5128 struct ice_aq_desc desc; 5129 int ret; 5130 5131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5132 cmd = &desc.params.get_cgu_output_config; 5133 cmd->output_idx = output_idx; 5134 5135 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5136 if (!ret) { 5137 if (flags) 5138 *flags = cmd->flags; 5139 if (src_sel) 5140 *src_sel = cmd->src_sel; 5141 if (freq) 5142 *freq = le32_to_cpu(cmd->freq); 5143 if (src_freq) 5144 *src_freq = le32_to_cpu(cmd->src_freq); 5145 } 5146 5147 return ret; 5148 } 5149 5150 /** 5151 * ice_aq_get_cgu_dpll_status - get dpll status 5152 * @hw: pointer to the HW struct 5153 * @dpll_num: DPLL index 5154 * @ref_state: Reference clock state 5155 * @config: current DPLL config 5156 * @dpll_state: current DPLL state 5157 * @phase_offset: Phase offset in ns 5158 * @eec_mode: EEC_mode 5159 * 5160 * Get CGU DPLL status (0x0C66) 5161 * Return: 0 on success or negative value on failure. 5162 */ 5163 int 5164 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5165 u8 *dpll_state, u8 *config, s64 *phase_offset, 5166 u8 *eec_mode) 5167 { 5168 struct ice_aqc_get_cgu_dpll_status *cmd; 5169 struct ice_aq_desc desc; 5170 int status; 5171 5172 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5173 cmd = &desc.params.get_cgu_dpll_status; 5174 cmd->dpll_num = dpll_num; 5175 5176 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5177 if (!status) { 5178 *ref_state = cmd->ref_state; 5179 *dpll_state = cmd->dpll_state; 5180 *config = cmd->config; 5181 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5182 *phase_offset <<= 32; 5183 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5184 *phase_offset = sign_extend64(*phase_offset, 47); 5185 *eec_mode = cmd->eec_mode; 5186 } 5187 5188 return status; 5189 } 5190 5191 /** 5192 * ice_aq_set_cgu_dpll_config - set dpll config 5193 * @hw: pointer to the HW struct 5194 * @dpll_num: DPLL index 5195 * @ref_state: Reference clock state 5196 * @config: DPLL config 5197 * @eec_mode: EEC mode 5198 * 5199 * Set CGU DPLL config (0x0C67) 5200 * Return: 0 on success or negative value on failure. 5201 */ 5202 int 5203 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5204 u8 config, u8 eec_mode) 5205 { 5206 struct ice_aqc_set_cgu_dpll_config *cmd; 5207 struct ice_aq_desc desc; 5208 5209 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5210 cmd = &desc.params.set_cgu_dpll_config; 5211 cmd->dpll_num = dpll_num; 5212 cmd->ref_state = ref_state; 5213 cmd->config = config; 5214 cmd->eec_mode = eec_mode; 5215 5216 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5217 } 5218 5219 /** 5220 * ice_aq_set_cgu_ref_prio - set input reference priority 5221 * @hw: pointer to the HW struct 5222 * @dpll_num: DPLL index 5223 * @ref_idx: Reference pin index 5224 * @ref_priority: Reference input priority 5225 * 5226 * Set CGU reference priority (0x0C68) 5227 * Return: 0 on success or negative value on failure. 5228 */ 5229 int 5230 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5231 u8 ref_priority) 5232 { 5233 struct ice_aqc_set_cgu_ref_prio *cmd; 5234 struct ice_aq_desc desc; 5235 5236 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5237 cmd = &desc.params.set_cgu_ref_prio; 5238 cmd->dpll_num = dpll_num; 5239 cmd->ref_idx = ref_idx; 5240 cmd->ref_priority = ref_priority; 5241 5242 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5243 } 5244 5245 /** 5246 * ice_aq_get_cgu_ref_prio - get input reference priority 5247 * @hw: pointer to the HW struct 5248 * @dpll_num: DPLL index 5249 * @ref_idx: Reference pin index 5250 * @ref_prio: Reference input priority 5251 * 5252 * Get CGU reference priority (0x0C69) 5253 * Return: 0 on success or negative value on failure. 5254 */ 5255 int 5256 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5257 u8 *ref_prio) 5258 { 5259 struct ice_aqc_get_cgu_ref_prio *cmd; 5260 struct ice_aq_desc desc; 5261 int status; 5262 5263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5264 cmd = &desc.params.get_cgu_ref_prio; 5265 cmd->dpll_num = dpll_num; 5266 cmd->ref_idx = ref_idx; 5267 5268 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5269 if (!status) 5270 *ref_prio = cmd->ref_priority; 5271 5272 return status; 5273 } 5274 5275 /** 5276 * ice_aq_get_cgu_info - get cgu info 5277 * @hw: pointer to the HW struct 5278 * @cgu_id: CGU ID 5279 * @cgu_cfg_ver: CGU config version 5280 * @cgu_fw_ver: CGU firmware version 5281 * 5282 * Get CGU info (0x0C6A) 5283 * Return: 0 on success or negative value on failure. 5284 */ 5285 int 5286 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5287 u32 *cgu_fw_ver) 5288 { 5289 struct ice_aqc_get_cgu_info *cmd; 5290 struct ice_aq_desc desc; 5291 int status; 5292 5293 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5294 cmd = &desc.params.get_cgu_info; 5295 5296 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5297 if (!status) { 5298 *cgu_id = le32_to_cpu(cmd->cgu_id); 5299 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5300 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5301 } 5302 5303 return status; 5304 } 5305 5306 /** 5307 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5308 * @hw: pointer to the HW struct 5309 * @phy_output: PHY reference clock output pin 5310 * @enable: GPIO state to be applied 5311 * @freq: PHY output frequency 5312 * 5313 * Set phy recovered clock as reference (0x0630) 5314 * Return: 0 on success or negative value on failure. 5315 */ 5316 int 5317 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5318 u32 *freq) 5319 { 5320 struct ice_aqc_set_phy_rec_clk_out *cmd; 5321 struct ice_aq_desc desc; 5322 int status; 5323 5324 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5325 cmd = &desc.params.set_phy_rec_clk_out; 5326 cmd->phy_output = phy_output; 5327 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5328 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5329 cmd->freq = cpu_to_le32(*freq); 5330 5331 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5332 if (!status) 5333 *freq = le32_to_cpu(cmd->freq); 5334 5335 return status; 5336 } 5337 5338 /** 5339 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5340 * @hw: pointer to the HW struct 5341 * @phy_output: PHY reference clock output pin 5342 * @port_num: Port number 5343 * @flags: PHY flags 5344 * @node_handle: PHY output frequency 5345 * 5346 * Get PHY recovered clock output info (0x0631) 5347 * Return: 0 on success or negative value on failure. 5348 */ 5349 int 5350 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5351 u8 *flags, u16 *node_handle) 5352 { 5353 struct ice_aqc_get_phy_rec_clk_out *cmd; 5354 struct ice_aq_desc desc; 5355 int status; 5356 5357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5358 cmd = &desc.params.get_phy_rec_clk_out; 5359 cmd->phy_output = *phy_output; 5360 5361 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5362 if (!status) { 5363 *phy_output = cmd->phy_output; 5364 if (port_num) 5365 *port_num = cmd->port_num; 5366 if (flags) 5367 *flags = cmd->flags; 5368 if (node_handle) 5369 *node_handle = le16_to_cpu(cmd->node_handle); 5370 } 5371 5372 return status; 5373 } 5374 5375 /** 5376 * ice_aq_get_sensor_reading 5377 * @hw: pointer to the HW struct 5378 * @data: pointer to data to be read from the sensor 5379 * 5380 * Get sensor reading (0x0632) 5381 */ 5382 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5383 struct ice_aqc_get_sensor_reading_resp *data) 5384 { 5385 struct ice_aqc_get_sensor_reading *cmd; 5386 struct ice_aq_desc desc; 5387 int status; 5388 5389 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5390 cmd = &desc.params.get_sensor_reading; 5391 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5392 #define ICE_INTERNAL_TEMP_SENSOR 0 5393 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5394 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5395 5396 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5397 if (!status) 5398 memcpy(data, &desc.params.get_sensor_reading_resp, 5399 sizeof(*data)); 5400 5401 return status; 5402 } 5403 5404 /** 5405 * ice_replay_pre_init - replay pre initialization 5406 * @hw: pointer to the HW struct 5407 * 5408 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5409 */ 5410 static int ice_replay_pre_init(struct ice_hw *hw) 5411 { 5412 struct ice_switch_info *sw = hw->switch_info; 5413 u8 i; 5414 5415 /* Delete old entries from replay filter list head if there is any */ 5416 ice_rm_all_sw_replay_rule_info(hw); 5417 /* In start of replay, move entries into replay_rules list, it 5418 * will allow adding rules entries back to filt_rules list, 5419 * which is operational list. 5420 */ 5421 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5422 list_replace_init(&sw->recp_list[i].filt_rules, 5423 &sw->recp_list[i].filt_replay_rules); 5424 ice_sched_replay_agg_vsi_preinit(hw); 5425 5426 return 0; 5427 } 5428 5429 /** 5430 * ice_replay_vsi - replay VSI configuration 5431 * @hw: pointer to the HW struct 5432 * @vsi_handle: driver VSI handle 5433 * 5434 * Restore all VSI configuration after reset. It is required to call this 5435 * function with main VSI first. 5436 */ 5437 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5438 { 5439 int status; 5440 5441 if (!ice_is_vsi_valid(hw, vsi_handle)) 5442 return -EINVAL; 5443 5444 /* Replay pre-initialization if there is any */ 5445 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5446 status = ice_replay_pre_init(hw); 5447 if (status) 5448 return status; 5449 } 5450 /* Replay per VSI all RSS configurations */ 5451 status = ice_replay_rss_cfg(hw, vsi_handle); 5452 if (status) 5453 return status; 5454 /* Replay per VSI all filters */ 5455 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5456 if (!status) 5457 status = ice_replay_vsi_agg(hw, vsi_handle); 5458 return status; 5459 } 5460 5461 /** 5462 * ice_replay_post - post replay configuration cleanup 5463 * @hw: pointer to the HW struct 5464 * 5465 * Post replay cleanup. 5466 */ 5467 void ice_replay_post(struct ice_hw *hw) 5468 { 5469 /* Delete old entries from replay filter list head */ 5470 ice_rm_all_sw_replay_rule_info(hw); 5471 ice_sched_replay_agg(hw); 5472 } 5473 5474 /** 5475 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5476 * @hw: ptr to the hardware info 5477 * @reg: offset of 64 bit HW register to read from 5478 * @prev_stat_loaded: bool to specify if previous stats are loaded 5479 * @prev_stat: ptr to previous loaded stat value 5480 * @cur_stat: ptr to current stat value 5481 */ 5482 void 5483 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5484 u64 *prev_stat, u64 *cur_stat) 5485 { 5486 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5487 5488 /* device stats are not reset at PFR, they likely will not be zeroed 5489 * when the driver starts. Thus, save the value from the first read 5490 * without adding to the statistic value so that we report stats which 5491 * count up from zero. 5492 */ 5493 if (!prev_stat_loaded) { 5494 *prev_stat = new_data; 5495 return; 5496 } 5497 5498 /* Calculate the difference between the new and old values, and then 5499 * add it to the software stat value. 5500 */ 5501 if (new_data >= *prev_stat) 5502 *cur_stat += new_data - *prev_stat; 5503 else 5504 /* to manage the potential roll-over */ 5505 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5506 5507 /* Update the previously stored value to prepare for next read */ 5508 *prev_stat = new_data; 5509 } 5510 5511 /** 5512 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5513 * @hw: ptr to the hardware info 5514 * @reg: offset of HW register to read from 5515 * @prev_stat_loaded: bool to specify if previous stats are loaded 5516 * @prev_stat: ptr to previous loaded stat value 5517 * @cur_stat: ptr to current stat value 5518 */ 5519 void 5520 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5521 u64 *prev_stat, u64 *cur_stat) 5522 { 5523 u32 new_data; 5524 5525 new_data = rd32(hw, reg); 5526 5527 /* device stats are not reset at PFR, they likely will not be zeroed 5528 * when the driver starts. Thus, save the value from the first read 5529 * without adding to the statistic value so that we report stats which 5530 * count up from zero. 5531 */ 5532 if (!prev_stat_loaded) { 5533 *prev_stat = new_data; 5534 return; 5535 } 5536 5537 /* Calculate the difference between the new and old values, and then 5538 * add it to the software stat value. 5539 */ 5540 if (new_data >= *prev_stat) 5541 *cur_stat += new_data - *prev_stat; 5542 else 5543 /* to manage the potential roll-over */ 5544 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5545 5546 /* Update the previously stored value to prepare for next read */ 5547 *prev_stat = new_data; 5548 } 5549 5550 /** 5551 * ice_sched_query_elem - query element information from HW 5552 * @hw: pointer to the HW struct 5553 * @node_teid: node TEID to be queried 5554 * @buf: buffer to element information 5555 * 5556 * This function queries HW element information 5557 */ 5558 int 5559 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5560 struct ice_aqc_txsched_elem_data *buf) 5561 { 5562 u16 buf_size, num_elem_ret = 0; 5563 int status; 5564 5565 buf_size = sizeof(*buf); 5566 memset(buf, 0, buf_size); 5567 buf->node_teid = cpu_to_le32(node_teid); 5568 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5569 NULL); 5570 if (status || num_elem_ret != 1) 5571 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5572 return status; 5573 } 5574 5575 /** 5576 * ice_aq_read_i2c 5577 * @hw: pointer to the hw struct 5578 * @topo_addr: topology address for a device to communicate with 5579 * @bus_addr: 7-bit I2C bus address 5580 * @addr: I2C memory address (I2C offset) with up to 16 bits 5581 * @params: I2C parameters: bit [7] - Repeated start, 5582 * bits [6:5] data offset size, 5583 * bit [4] - I2C address type, 5584 * bits [3:0] - data size to read (0-16 bytes) 5585 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5586 * @cd: pointer to command details structure or NULL 5587 * 5588 * Read I2C (0x06E2) 5589 */ 5590 int 5591 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5592 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5593 struct ice_sq_cd *cd) 5594 { 5595 struct ice_aq_desc desc = { 0 }; 5596 struct ice_aqc_i2c *cmd; 5597 u8 data_size; 5598 int status; 5599 5600 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5601 cmd = &desc.params.read_write_i2c; 5602 5603 if (!data) 5604 return -EINVAL; 5605 5606 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5607 5608 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5609 cmd->topo_addr = topo_addr; 5610 cmd->i2c_params = params; 5611 cmd->i2c_addr = addr; 5612 5613 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5614 if (!status) { 5615 struct ice_aqc_read_i2c_resp *resp; 5616 u8 i; 5617 5618 resp = &desc.params.read_i2c_resp; 5619 for (i = 0; i < data_size; i++) { 5620 *data = resp->i2c_data[i]; 5621 data++; 5622 } 5623 } 5624 5625 return status; 5626 } 5627 5628 /** 5629 * ice_aq_write_i2c 5630 * @hw: pointer to the hw struct 5631 * @topo_addr: topology address for a device to communicate with 5632 * @bus_addr: 7-bit I2C bus address 5633 * @addr: I2C memory address (I2C offset) with up to 16 bits 5634 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5635 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5636 * @cd: pointer to command details structure or NULL 5637 * 5638 * Write I2C (0x06E3) 5639 * 5640 * * Return: 5641 * * 0 - Successful write to the i2c device 5642 * * -EINVAL - Data size greater than 4 bytes 5643 * * -EIO - FW error 5644 */ 5645 int 5646 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5647 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5648 struct ice_sq_cd *cd) 5649 { 5650 struct ice_aq_desc desc = { 0 }; 5651 struct ice_aqc_i2c *cmd; 5652 u8 data_size; 5653 5654 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5655 cmd = &desc.params.read_write_i2c; 5656 5657 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5658 5659 /* data_size limited to 4 */ 5660 if (data_size > 4) 5661 return -EINVAL; 5662 5663 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5664 cmd->topo_addr = topo_addr; 5665 cmd->i2c_params = params; 5666 cmd->i2c_addr = addr; 5667 5668 memcpy(cmd->i2c_data, data, data_size); 5669 5670 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5671 } 5672 5673 /** 5674 * ice_aq_set_gpio 5675 * @hw: pointer to the hw struct 5676 * @gpio_ctrl_handle: GPIO controller node handle 5677 * @pin_idx: IO Number of the GPIO that needs to be set 5678 * @value: SW provide IO value to set in the LSB 5679 * @cd: pointer to command details structure or NULL 5680 * 5681 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5682 */ 5683 int 5684 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5685 struct ice_sq_cd *cd) 5686 { 5687 struct ice_aqc_gpio *cmd; 5688 struct ice_aq_desc desc; 5689 5690 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5691 cmd = &desc.params.read_write_gpio; 5692 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5693 cmd->gpio_num = pin_idx; 5694 cmd->gpio_val = value ? 1 : 0; 5695 5696 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5697 } 5698 5699 /** 5700 * ice_aq_get_gpio 5701 * @hw: pointer to the hw struct 5702 * @gpio_ctrl_handle: GPIO controller node handle 5703 * @pin_idx: IO Number of the GPIO that needs to be set 5704 * @value: IO value read 5705 * @cd: pointer to command details structure or NULL 5706 * 5707 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5708 * the topology 5709 */ 5710 int 5711 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5712 bool *value, struct ice_sq_cd *cd) 5713 { 5714 struct ice_aqc_gpio *cmd; 5715 struct ice_aq_desc desc; 5716 int status; 5717 5718 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5719 cmd = &desc.params.read_write_gpio; 5720 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5721 cmd->gpio_num = pin_idx; 5722 5723 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5724 if (status) 5725 return status; 5726 5727 *value = !!cmd->gpio_val; 5728 return 0; 5729 } 5730 5731 /** 5732 * ice_is_fw_api_min_ver 5733 * @hw: pointer to the hardware structure 5734 * @maj: major version 5735 * @min: minor version 5736 * @patch: patch version 5737 * 5738 * Checks if the firmware API is minimum version 5739 */ 5740 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5741 { 5742 if (hw->api_maj_ver == maj) { 5743 if (hw->api_min_ver > min) 5744 return true; 5745 if (hw->api_min_ver == min && hw->api_patch >= patch) 5746 return true; 5747 } else if (hw->api_maj_ver > maj) { 5748 return true; 5749 } 5750 5751 return false; 5752 } 5753 5754 /** 5755 * ice_fw_supports_link_override 5756 * @hw: pointer to the hardware structure 5757 * 5758 * Checks if the firmware supports link override 5759 */ 5760 bool ice_fw_supports_link_override(struct ice_hw *hw) 5761 { 5762 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5763 ICE_FW_API_LINK_OVERRIDE_MIN, 5764 ICE_FW_API_LINK_OVERRIDE_PATCH); 5765 } 5766 5767 /** 5768 * ice_get_link_default_override 5769 * @ldo: pointer to the link default override struct 5770 * @pi: pointer to the port info struct 5771 * 5772 * Gets the link default override for a port 5773 */ 5774 int 5775 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5776 struct ice_port_info *pi) 5777 { 5778 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5779 struct ice_hw *hw = pi->hw; 5780 int status; 5781 5782 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5783 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5784 if (status) { 5785 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5786 return status; 5787 } 5788 5789 /* Each port has its own config; calculate for our port */ 5790 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5791 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5792 5793 /* link options first */ 5794 status = ice_read_sr_word(hw, tlv_start, &buf); 5795 if (status) { 5796 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5797 return status; 5798 } 5799 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 5800 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5801 ICE_LINK_OVERRIDE_PHY_CFG_S; 5802 5803 /* link PHY config */ 5804 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5805 status = ice_read_sr_word(hw, offset, &buf); 5806 if (status) { 5807 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5808 return status; 5809 } 5810 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5811 5812 /* PHY types low */ 5813 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5814 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5815 status = ice_read_sr_word(hw, (offset + i), &buf); 5816 if (status) { 5817 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5818 return status; 5819 } 5820 /* shift 16 bits at a time to fill 64 bits */ 5821 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5822 } 5823 5824 /* PHY types high */ 5825 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5826 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5827 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5828 status = ice_read_sr_word(hw, (offset + i), &buf); 5829 if (status) { 5830 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5831 return status; 5832 } 5833 /* shift 16 bits at a time to fill 64 bits */ 5834 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5835 } 5836 5837 return status; 5838 } 5839 5840 /** 5841 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5842 * @caps: get PHY capability data 5843 */ 5844 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5845 { 5846 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5847 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5848 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5849 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5850 return true; 5851 5852 return false; 5853 } 5854 5855 /** 5856 * ice_aq_set_lldp_mib - Set the LLDP MIB 5857 * @hw: pointer to the HW struct 5858 * @mib_type: Local, Remote or both Local and Remote MIBs 5859 * @buf: pointer to the caller-supplied buffer to store the MIB block 5860 * @buf_size: size of the buffer (in bytes) 5861 * @cd: pointer to command details structure or NULL 5862 * 5863 * Set the LLDP MIB. (0x0A08) 5864 */ 5865 int 5866 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5867 struct ice_sq_cd *cd) 5868 { 5869 struct ice_aqc_lldp_set_local_mib *cmd; 5870 struct ice_aq_desc desc; 5871 5872 cmd = &desc.params.lldp_set_mib; 5873 5874 if (buf_size == 0 || !buf) 5875 return -EINVAL; 5876 5877 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5878 5879 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5880 desc.datalen = cpu_to_le16(buf_size); 5881 5882 cmd->type = mib_type; 5883 cmd->length = cpu_to_le16(buf_size); 5884 5885 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5886 } 5887 5888 /** 5889 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5890 * @hw: pointer to HW struct 5891 */ 5892 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5893 { 5894 if (hw->mac_type != ICE_MAC_E810) 5895 return false; 5896 5897 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5898 ICE_FW_API_LLDP_FLTR_MIN, 5899 ICE_FW_API_LLDP_FLTR_PATCH); 5900 } 5901 5902 /** 5903 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5904 * @hw: pointer to HW struct 5905 * @vsi_num: absolute HW index for VSI 5906 * @add: boolean for if adding or removing a filter 5907 */ 5908 int 5909 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5910 { 5911 struct ice_aqc_lldp_filter_ctrl *cmd; 5912 struct ice_aq_desc desc; 5913 5914 cmd = &desc.params.lldp_filter_ctrl; 5915 5916 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5917 5918 if (add) 5919 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5920 else 5921 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5922 5923 cmd->vsi_num = cpu_to_le16(vsi_num); 5924 5925 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5926 } 5927 5928 /** 5929 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 5930 * @hw: pointer to HW struct 5931 */ 5932 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 5933 { 5934 struct ice_aq_desc desc; 5935 5936 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 5937 5938 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5939 } 5940 5941 /** 5942 * ice_fw_supports_report_dflt_cfg 5943 * @hw: pointer to the hardware structure 5944 * 5945 * Checks if the firmware supports report default configuration 5946 */ 5947 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5948 { 5949 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 5950 ICE_FW_API_REPORT_DFLT_CFG_MIN, 5951 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 5952 } 5953 5954 /* each of the indexes into the following array match the speed of a return 5955 * value from the list of AQ returned speeds like the range: 5956 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 5957 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 5958 * array. The array is defined as 15 elements long because the link_speed 5959 * returned by the firmware is a 16 bit * value, but is indexed 5960 * by [fls(speed) - 1] 5961 */ 5962 static const u32 ice_aq_to_link_speed[] = { 5963 SPEED_10, /* BIT(0) */ 5964 SPEED_100, 5965 SPEED_1000, 5966 SPEED_2500, 5967 SPEED_5000, 5968 SPEED_10000, 5969 SPEED_20000, 5970 SPEED_25000, 5971 SPEED_40000, 5972 SPEED_50000, 5973 SPEED_100000, /* BIT(10) */ 5974 SPEED_200000, 5975 }; 5976 5977 /** 5978 * ice_get_link_speed - get integer speed from table 5979 * @index: array index from fls(aq speed) - 1 5980 * 5981 * Returns: u32 value containing integer speed 5982 */ 5983 u32 ice_get_link_speed(u16 index) 5984 { 5985 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 5986 return 0; 5987 5988 return ice_aq_to_link_speed[index]; 5989 } 5990