1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 /** 12 * ice_set_mac_type - Sets MAC type 13 * @hw: pointer to the HW structure 14 * 15 * This function sets the MAC type of the adapter based on the 16 * vendor ID and device ID stored in the HW structure. 17 */ 18 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19 { 20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21 return ICE_ERR_DEVICE_NOT_SUPPORTED; 22 23 switch (hw->device_id) { 24 case ICE_DEV_ID_E810C_BACKPLANE: 25 case ICE_DEV_ID_E810C_QSFP: 26 case ICE_DEV_ID_E810C_SFP: 27 case ICE_DEV_ID_E810_XXV_SFP: 28 hw->mac_type = ICE_MAC_E810; 29 break; 30 case ICE_DEV_ID_E823C_10G_BASE_T: 31 case ICE_DEV_ID_E823C_BACKPLANE: 32 case ICE_DEV_ID_E823C_QSFP: 33 case ICE_DEV_ID_E823C_SFP: 34 case ICE_DEV_ID_E823C_SGMII: 35 case ICE_DEV_ID_E822C_10G_BASE_T: 36 case ICE_DEV_ID_E822C_BACKPLANE: 37 case ICE_DEV_ID_E822C_QSFP: 38 case ICE_DEV_ID_E822C_SFP: 39 case ICE_DEV_ID_E822C_SGMII: 40 case ICE_DEV_ID_E822L_10G_BASE_T: 41 case ICE_DEV_ID_E822L_BACKPLANE: 42 case ICE_DEV_ID_E822L_SFP: 43 case ICE_DEV_ID_E822L_SGMII: 44 case ICE_DEV_ID_E823L_10G_BASE_T: 45 case ICE_DEV_ID_E823L_1GBE: 46 case ICE_DEV_ID_E823L_BACKPLANE: 47 case ICE_DEV_ID_E823L_QSFP: 48 case ICE_DEV_ID_E823L_SFP: 49 hw->mac_type = ICE_MAC_GENERIC; 50 break; 51 default: 52 hw->mac_type = ICE_MAC_UNKNOWN; 53 break; 54 } 55 56 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 57 return 0; 58 } 59 60 /** 61 * ice_clear_pf_cfg - Clear PF configuration 62 * @hw: pointer to the hardware structure 63 * 64 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 65 * configuration, flow director filters, etc.). 66 */ 67 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 68 { 69 struct ice_aq_desc desc; 70 71 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 72 73 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 74 } 75 76 /** 77 * ice_aq_manage_mac_read - manage MAC address read command 78 * @hw: pointer to the HW struct 79 * @buf: a virtual buffer to hold the manage MAC read response 80 * @buf_size: Size of the virtual buffer 81 * @cd: pointer to command details structure or NULL 82 * 83 * This function is used to return per PF station MAC address (0x0107). 84 * NOTE: Upon successful completion of this command, MAC address information 85 * is returned in user specified buffer. Please interpret user specified 86 * buffer as "manage_mac_read" response. 87 * Response such as various MAC addresses are stored in HW struct (port.mac) 88 * ice_discover_dev_caps is expected to be called before this function is 89 * called. 90 */ 91 static enum ice_status 92 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 93 struct ice_sq_cd *cd) 94 { 95 struct ice_aqc_manage_mac_read_resp *resp; 96 struct ice_aqc_manage_mac_read *cmd; 97 struct ice_aq_desc desc; 98 enum ice_status status; 99 u16 flags; 100 u8 i; 101 102 cmd = &desc.params.mac_read; 103 104 if (buf_size < sizeof(*resp)) 105 return ICE_ERR_BUF_TOO_SHORT; 106 107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 108 109 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 110 if (status) 111 return status; 112 113 resp = buf; 114 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 115 116 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 117 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 118 return ICE_ERR_CFG; 119 } 120 121 /* A single port can report up to two (LAN and WoL) addresses */ 122 for (i = 0; i < cmd->num_addr; i++) 123 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 124 ether_addr_copy(hw->port_info->mac.lan_addr, 125 resp[i].mac_addr); 126 ether_addr_copy(hw->port_info->mac.perm_addr, 127 resp[i].mac_addr); 128 break; 129 } 130 131 return 0; 132 } 133 134 /** 135 * ice_aq_get_phy_caps - returns PHY capabilities 136 * @pi: port information structure 137 * @qual_mods: report qualified modules 138 * @report_mode: report mode capabilities 139 * @pcaps: structure for PHY capabilities to be filled 140 * @cd: pointer to command details structure or NULL 141 * 142 * Returns the various PHY capabilities supported on the Port (0x0600) 143 */ 144 enum ice_status 145 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 146 struct ice_aqc_get_phy_caps_data *pcaps, 147 struct ice_sq_cd *cd) 148 { 149 struct ice_aqc_get_phy_caps *cmd; 150 u16 pcaps_size = sizeof(*pcaps); 151 struct ice_aq_desc desc; 152 enum ice_status status; 153 struct ice_hw *hw; 154 155 cmd = &desc.params.get_phy; 156 157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158 return ICE_ERR_PARAM; 159 hw = pi->hw; 160 161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 162 163 if (qual_mods) 164 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 165 166 cmd->param0 |= cpu_to_le16(report_mode); 167 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 168 169 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 170 report_mode); 171 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 172 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 173 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 174 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 175 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 176 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 177 pcaps->low_power_ctrl_an); 178 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 179 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 180 pcaps->eeer_value); 181 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 182 pcaps->link_fec_options); 183 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 184 pcaps->module_compliance_enforcement); 185 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 186 pcaps->extended_compliance_code); 187 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 188 pcaps->module_type[0]); 189 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 190 pcaps->module_type[1]); 191 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 192 pcaps->module_type[2]); 193 194 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 195 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 196 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 197 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 198 sizeof(pi->phy.link_info.module_type)); 199 } 200 201 return status; 202 } 203 204 /** 205 * ice_aq_get_link_topo_handle - get link topology node return status 206 * @pi: port information structure 207 * @node_type: requested node type 208 * @cd: pointer to command details structure or NULL 209 * 210 * Get link topology node return status for specified node type (0x06E0) 211 * 212 * Node type cage can be used to determine if cage is present. If AQC 213 * returns error (ENOENT), then no cage present. If no cage present, then 214 * connection type is backplane or BASE-T. 215 */ 216 static enum ice_status 217 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 218 struct ice_sq_cd *cd) 219 { 220 struct ice_aqc_get_link_topo *cmd; 221 struct ice_aq_desc desc; 222 223 cmd = &desc.params.get_link_topo; 224 225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 226 227 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 228 ICE_AQC_LINK_TOPO_NODE_CTX_S); 229 230 /* set node type */ 231 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 232 233 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 234 } 235 236 /** 237 * ice_is_media_cage_present 238 * @pi: port information structure 239 * 240 * Returns true if media cage is present, else false. If no cage, then 241 * media type is backplane or BASE-T. 242 */ 243 static bool ice_is_media_cage_present(struct ice_port_info *pi) 244 { 245 /* Node type cage can be used to determine if cage is present. If AQC 246 * returns error (ENOENT), then no cage present. If no cage present then 247 * connection type is backplane or BASE-T. 248 */ 249 return !ice_aq_get_link_topo_handle(pi, 250 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 251 NULL); 252 } 253 254 /** 255 * ice_get_media_type - Gets media type 256 * @pi: port information structure 257 */ 258 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 259 { 260 struct ice_link_status *hw_link_info; 261 262 if (!pi) 263 return ICE_MEDIA_UNKNOWN; 264 265 hw_link_info = &pi->phy.link_info; 266 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 267 /* If more than one media type is selected, report unknown */ 268 return ICE_MEDIA_UNKNOWN; 269 270 if (hw_link_info->phy_type_low) { 271 /* 1G SGMII is a special case where some DA cable PHYs 272 * may show this as an option when it really shouldn't 273 * be since SGMII is meant to be between a MAC and a PHY 274 * in a backplane. Try to detect this case and handle it 275 */ 276 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 277 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 278 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 279 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 280 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 281 return ICE_MEDIA_DA; 282 283 switch (hw_link_info->phy_type_low) { 284 case ICE_PHY_TYPE_LOW_1000BASE_SX: 285 case ICE_PHY_TYPE_LOW_1000BASE_LX: 286 case ICE_PHY_TYPE_LOW_10GBASE_SR: 287 case ICE_PHY_TYPE_LOW_10GBASE_LR: 288 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 289 case ICE_PHY_TYPE_LOW_25GBASE_SR: 290 case ICE_PHY_TYPE_LOW_25GBASE_LR: 291 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 292 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 293 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 294 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 295 case ICE_PHY_TYPE_LOW_50GBASE_SR: 296 case ICE_PHY_TYPE_LOW_50GBASE_FR: 297 case ICE_PHY_TYPE_LOW_50GBASE_LR: 298 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 299 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 300 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 301 case ICE_PHY_TYPE_LOW_100GBASE_DR: 302 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 303 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 304 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 305 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 306 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 307 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 308 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 309 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_100BASE_TX: 312 case ICE_PHY_TYPE_LOW_1000BASE_T: 313 case ICE_PHY_TYPE_LOW_2500BASE_T: 314 case ICE_PHY_TYPE_LOW_5GBASE_T: 315 case ICE_PHY_TYPE_LOW_10GBASE_T: 316 case ICE_PHY_TYPE_LOW_25GBASE_T: 317 return ICE_MEDIA_BASET; 318 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 319 case ICE_PHY_TYPE_LOW_25GBASE_CR: 320 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 321 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 322 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 323 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 324 case ICE_PHY_TYPE_LOW_50GBASE_CP: 325 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 326 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 327 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 328 return ICE_MEDIA_DA; 329 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 330 case ICE_PHY_TYPE_LOW_40G_XLAUI: 331 case ICE_PHY_TYPE_LOW_50G_LAUI2: 332 case ICE_PHY_TYPE_LOW_50G_AUI2: 333 case ICE_PHY_TYPE_LOW_50G_AUI1: 334 case ICE_PHY_TYPE_LOW_100G_AUI4: 335 case ICE_PHY_TYPE_LOW_100G_CAUI4: 336 if (ice_is_media_cage_present(pi)) 337 return ICE_MEDIA_DA; 338 fallthrough; 339 case ICE_PHY_TYPE_LOW_1000BASE_KX: 340 case ICE_PHY_TYPE_LOW_2500BASE_KX: 341 case ICE_PHY_TYPE_LOW_2500BASE_X: 342 case ICE_PHY_TYPE_LOW_5GBASE_KR: 343 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 344 case ICE_PHY_TYPE_LOW_25GBASE_KR: 345 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 346 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 347 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 348 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 349 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 350 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 351 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 352 return ICE_MEDIA_BACKPLANE; 353 } 354 } else { 355 switch (hw_link_info->phy_type_high) { 356 case ICE_PHY_TYPE_HIGH_100G_AUI2: 357 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 358 if (ice_is_media_cage_present(pi)) 359 return ICE_MEDIA_DA; 360 fallthrough; 361 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 362 return ICE_MEDIA_BACKPLANE; 363 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 364 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 365 return ICE_MEDIA_FIBER; 366 } 367 } 368 return ICE_MEDIA_UNKNOWN; 369 } 370 371 /** 372 * ice_aq_get_link_info 373 * @pi: port information structure 374 * @ena_lse: enable/disable LinkStatusEvent reporting 375 * @link: pointer to link status structure - optional 376 * @cd: pointer to command details structure or NULL 377 * 378 * Get Link Status (0x607). Returns the link status of the adapter. 379 */ 380 enum ice_status 381 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 382 struct ice_link_status *link, struct ice_sq_cd *cd) 383 { 384 struct ice_aqc_get_link_status_data link_data = { 0 }; 385 struct ice_aqc_get_link_status *resp; 386 struct ice_link_status *li_old, *li; 387 enum ice_media_type *hw_media_type; 388 struct ice_fc_info *hw_fc_info; 389 bool tx_pause, rx_pause; 390 struct ice_aq_desc desc; 391 enum ice_status status; 392 struct ice_hw *hw; 393 u16 cmd_flags; 394 395 if (!pi) 396 return ICE_ERR_PARAM; 397 hw = pi->hw; 398 li_old = &pi->phy.link_info_old; 399 hw_media_type = &pi->phy.media_type; 400 li = &pi->phy.link_info; 401 hw_fc_info = &pi->fc; 402 403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 404 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 405 resp = &desc.params.get_link_status; 406 resp->cmd_flags = cpu_to_le16(cmd_flags); 407 resp->lport_num = pi->lport; 408 409 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 410 411 if (status) 412 return status; 413 414 /* save off old link status information */ 415 *li_old = *li; 416 417 /* update current link status information */ 418 li->link_speed = le16_to_cpu(link_data.link_speed); 419 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 420 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 421 *hw_media_type = ice_get_media_type(pi); 422 li->link_info = link_data.link_info; 423 li->an_info = link_data.an_info; 424 li->ext_info = link_data.ext_info; 425 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 426 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 427 li->topo_media_conflict = link_data.topo_media_conflict; 428 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 429 ICE_AQ_CFG_PACING_TYPE_M); 430 431 /* update fc info */ 432 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 433 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 434 if (tx_pause && rx_pause) 435 hw_fc_info->current_mode = ICE_FC_FULL; 436 else if (tx_pause) 437 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 438 else if (rx_pause) 439 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 440 else 441 hw_fc_info->current_mode = ICE_FC_NONE; 442 443 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 444 445 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 446 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 447 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 448 (unsigned long long)li->phy_type_low); 449 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 450 (unsigned long long)li->phy_type_high); 451 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 452 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 453 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 454 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 455 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 456 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 457 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 458 li->max_frame_size); 459 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 460 461 /* save link status information */ 462 if (link) 463 *link = *li; 464 465 /* flag cleared so calling functions don't call AQ again */ 466 pi->phy.get_link_info = false; 467 468 return 0; 469 } 470 471 /** 472 * ice_fill_tx_timer_and_fc_thresh 473 * @hw: pointer to the HW struct 474 * @cmd: pointer to MAC cfg structure 475 * 476 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 477 * descriptor 478 */ 479 static void 480 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 481 struct ice_aqc_set_mac_cfg *cmd) 482 { 483 u16 fc_thres_val, tx_timer_val; 484 u32 val; 485 486 /* We read back the transmit timer and FC threshold value of 487 * LFC. Thus, we will use index = 488 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 489 * 490 * Also, because we are operating on transmit timer and FC 491 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 492 */ 493 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 494 495 /* Retrieve the transmit timer */ 496 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 497 tx_timer_val = val & 498 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 499 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 500 501 /* Retrieve the FC threshold */ 502 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 503 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 504 505 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 506 } 507 508 /** 509 * ice_aq_set_mac_cfg 510 * @hw: pointer to the HW struct 511 * @max_frame_size: Maximum Frame Size to be supported 512 * @cd: pointer to command details structure or NULL 513 * 514 * Set MAC configuration (0x0603) 515 */ 516 enum ice_status 517 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 518 { 519 struct ice_aqc_set_mac_cfg *cmd; 520 struct ice_aq_desc desc; 521 522 cmd = &desc.params.set_mac_cfg; 523 524 if (max_frame_size == 0) 525 return ICE_ERR_PARAM; 526 527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 528 529 cmd->max_frame_size = cpu_to_le16(max_frame_size); 530 531 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 532 533 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 534 } 535 536 /** 537 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 538 * @hw: pointer to the HW struct 539 */ 540 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 541 { 542 struct ice_switch_info *sw; 543 enum ice_status status; 544 545 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 546 sizeof(*hw->switch_info), GFP_KERNEL); 547 sw = hw->switch_info; 548 549 if (!sw) 550 return ICE_ERR_NO_MEMORY; 551 552 INIT_LIST_HEAD(&sw->vsi_list_map_head); 553 554 status = ice_init_def_sw_recp(hw); 555 if (status) { 556 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 557 return status; 558 } 559 return 0; 560 } 561 562 /** 563 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 564 * @hw: pointer to the HW struct 565 */ 566 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 567 { 568 struct ice_switch_info *sw = hw->switch_info; 569 struct ice_vsi_list_map_info *v_pos_map; 570 struct ice_vsi_list_map_info *v_tmp_map; 571 struct ice_sw_recipe *recps; 572 u8 i; 573 574 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 575 list_entry) { 576 list_del(&v_pos_map->list_entry); 577 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 578 } 579 recps = hw->switch_info->recp_list; 580 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 581 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 582 583 recps[i].root_rid = i; 584 mutex_destroy(&recps[i].filt_rule_lock); 585 list_for_each_entry_safe(lst_itr, tmp_entry, 586 &recps[i].filt_rules, list_entry) { 587 list_del(&lst_itr->list_entry); 588 devm_kfree(ice_hw_to_dev(hw), lst_itr); 589 } 590 } 591 ice_rm_all_sw_replay_rule_info(hw); 592 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 593 devm_kfree(ice_hw_to_dev(hw), sw); 594 } 595 596 /** 597 * ice_get_fw_log_cfg - get FW logging configuration 598 * @hw: pointer to the HW struct 599 */ 600 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 601 { 602 struct ice_aq_desc desc; 603 enum ice_status status; 604 __le16 *config; 605 u16 size; 606 607 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 608 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 609 if (!config) 610 return ICE_ERR_NO_MEMORY; 611 612 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 613 614 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 615 if (!status) { 616 u16 i; 617 618 /* Save FW logging information into the HW structure */ 619 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 620 u16 v, m, flgs; 621 622 v = le16_to_cpu(config[i]); 623 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 624 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 625 626 if (m < ICE_AQC_FW_LOG_ID_MAX) 627 hw->fw_log.evnts[m].cur = flgs; 628 } 629 } 630 631 devm_kfree(ice_hw_to_dev(hw), config); 632 633 return status; 634 } 635 636 /** 637 * ice_cfg_fw_log - configure FW logging 638 * @hw: pointer to the HW struct 639 * @enable: enable certain FW logging events if true, disable all if false 640 * 641 * This function enables/disables the FW logging via Rx CQ events and a UART 642 * port based on predetermined configurations. FW logging via the Rx CQ can be 643 * enabled/disabled for individual PF's. However, FW logging via the UART can 644 * only be enabled/disabled for all PFs on the same device. 645 * 646 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 647 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 648 * before initializing the device. 649 * 650 * When re/configuring FW logging, callers need to update the "cfg" elements of 651 * the hw->fw_log.evnts array with the desired logging event configurations for 652 * modules of interest. When disabling FW logging completely, the callers can 653 * just pass false in the "enable" parameter. On completion, the function will 654 * update the "cur" element of the hw->fw_log.evnts array with the resulting 655 * logging event configurations of the modules that are being re/configured. FW 656 * logging modules that are not part of a reconfiguration operation retain their 657 * previous states. 658 * 659 * Before resetting the device, it is recommended that the driver disables FW 660 * logging before shutting down the control queue. When disabling FW logging 661 * ("enable" = false), the latest configurations of FW logging events stored in 662 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 663 * a device reset. 664 * 665 * When enabling FW logging to emit log messages via the Rx CQ during the 666 * device's initialization phase, a mechanism alternative to interrupt handlers 667 * needs to be used to extract FW log messages from the Rx CQ periodically and 668 * to prevent the Rx CQ from being full and stalling other types of control 669 * messages from FW to SW. Interrupts are typically disabled during the device's 670 * initialization phase. 671 */ 672 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 673 { 674 struct ice_aqc_fw_logging *cmd; 675 enum ice_status status = 0; 676 u16 i, chgs = 0, len = 0; 677 struct ice_aq_desc desc; 678 __le16 *data = NULL; 679 u8 actv_evnts = 0; 680 void *buf = NULL; 681 682 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 683 return 0; 684 685 /* Disable FW logging only when the control queue is still responsive */ 686 if (!enable && 687 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 688 return 0; 689 690 /* Get current FW log settings */ 691 status = ice_get_fw_log_cfg(hw); 692 if (status) 693 return status; 694 695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 696 cmd = &desc.params.fw_logging; 697 698 /* Indicate which controls are valid */ 699 if (hw->fw_log.cq_en) 700 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 701 702 if (hw->fw_log.uart_en) 703 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 704 705 if (enable) { 706 /* Fill in an array of entries with FW logging modules and 707 * logging events being reconfigured. 708 */ 709 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 710 u16 val; 711 712 /* Keep track of enabled event types */ 713 actv_evnts |= hw->fw_log.evnts[i].cfg; 714 715 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 716 continue; 717 718 if (!data) { 719 data = devm_kcalloc(ice_hw_to_dev(hw), 720 sizeof(*data), 721 ICE_AQC_FW_LOG_ID_MAX, 722 GFP_KERNEL); 723 if (!data) 724 return ICE_ERR_NO_MEMORY; 725 } 726 727 val = i << ICE_AQC_FW_LOG_ID_S; 728 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 729 data[chgs++] = cpu_to_le16(val); 730 } 731 732 /* Only enable FW logging if at least one module is specified. 733 * If FW logging is currently enabled but all modules are not 734 * enabled to emit log messages, disable FW logging altogether. 735 */ 736 if (actv_evnts) { 737 /* Leave if there is effectively no change */ 738 if (!chgs) 739 goto out; 740 741 if (hw->fw_log.cq_en) 742 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 743 744 if (hw->fw_log.uart_en) 745 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 746 747 buf = data; 748 len = sizeof(*data) * chgs; 749 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 750 } 751 } 752 753 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 754 if (!status) { 755 /* Update the current configuration to reflect events enabled. 756 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 757 * logging mode is enabled for the device. They do not reflect 758 * actual modules being enabled to emit log messages. So, their 759 * values remain unchanged even when all modules are disabled. 760 */ 761 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 762 763 hw->fw_log.actv_evnts = actv_evnts; 764 for (i = 0; i < cnt; i++) { 765 u16 v, m; 766 767 if (!enable) { 768 /* When disabling all FW logging events as part 769 * of device's de-initialization, the original 770 * configurations are retained, and can be used 771 * to reconfigure FW logging later if the device 772 * is re-initialized. 773 */ 774 hw->fw_log.evnts[i].cur = 0; 775 continue; 776 } 777 778 v = le16_to_cpu(data[i]); 779 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 780 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 781 } 782 } 783 784 out: 785 if (data) 786 devm_kfree(ice_hw_to_dev(hw), data); 787 788 return status; 789 } 790 791 /** 792 * ice_output_fw_log 793 * @hw: pointer to the HW struct 794 * @desc: pointer to the AQ message descriptor 795 * @buf: pointer to the buffer accompanying the AQ message 796 * 797 * Formats a FW Log message and outputs it via the standard driver logs. 798 */ 799 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 800 { 801 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 802 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 803 le16_to_cpu(desc->datalen)); 804 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 805 } 806 807 /** 808 * ice_get_itr_intrl_gran 809 * @hw: pointer to the HW struct 810 * 811 * Determines the ITR/INTRL granularities based on the maximum aggregate 812 * bandwidth according to the device's configuration during power-on. 813 */ 814 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 815 { 816 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 817 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 818 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 819 820 switch (max_agg_bw) { 821 case ICE_MAX_AGG_BW_200G: 822 case ICE_MAX_AGG_BW_100G: 823 case ICE_MAX_AGG_BW_50G: 824 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 825 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 826 break; 827 case ICE_MAX_AGG_BW_25G: 828 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 829 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 830 break; 831 } 832 } 833 834 /** 835 * ice_init_hw - main hardware initialization routine 836 * @hw: pointer to the hardware structure 837 */ 838 enum ice_status ice_init_hw(struct ice_hw *hw) 839 { 840 struct ice_aqc_get_phy_caps_data *pcaps; 841 enum ice_status status; 842 u16 mac_buf_len; 843 void *mac_buf; 844 845 /* Set MAC type based on DeviceID */ 846 status = ice_set_mac_type(hw); 847 if (status) 848 return status; 849 850 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 851 PF_FUNC_RID_FUNC_NUM_M) >> 852 PF_FUNC_RID_FUNC_NUM_S; 853 854 status = ice_reset(hw, ICE_RESET_PFR); 855 if (status) 856 return status; 857 858 ice_get_itr_intrl_gran(hw); 859 860 status = ice_create_all_ctrlq(hw); 861 if (status) 862 goto err_unroll_cqinit; 863 864 /* Enable FW logging. Not fatal if this fails. */ 865 status = ice_cfg_fw_log(hw, true); 866 if (status) 867 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 868 869 status = ice_clear_pf_cfg(hw); 870 if (status) 871 goto err_unroll_cqinit; 872 873 /* Set bit to enable Flow Director filters */ 874 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 875 INIT_LIST_HEAD(&hw->fdir_list_head); 876 877 ice_clear_pxe_mode(hw); 878 879 status = ice_init_nvm(hw); 880 if (status) 881 goto err_unroll_cqinit; 882 883 status = ice_get_caps(hw); 884 if (status) 885 goto err_unroll_cqinit; 886 887 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 888 sizeof(*hw->port_info), GFP_KERNEL); 889 if (!hw->port_info) { 890 status = ICE_ERR_NO_MEMORY; 891 goto err_unroll_cqinit; 892 } 893 894 /* set the back pointer to HW */ 895 hw->port_info->hw = hw; 896 897 /* Initialize port_info struct with switch configuration data */ 898 status = ice_get_initial_sw_cfg(hw); 899 if (status) 900 goto err_unroll_alloc; 901 902 hw->evb_veb = true; 903 904 /* Query the allocated resources for Tx scheduler */ 905 status = ice_sched_query_res_alloc(hw); 906 if (status) { 907 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 908 goto err_unroll_alloc; 909 } 910 ice_sched_get_psm_clk_freq(hw); 911 912 /* Initialize port_info struct with scheduler data */ 913 status = ice_sched_init_port(hw->port_info); 914 if (status) 915 goto err_unroll_sched; 916 917 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 918 if (!pcaps) { 919 status = ICE_ERR_NO_MEMORY; 920 goto err_unroll_sched; 921 } 922 923 /* Initialize port_info struct with PHY capabilities */ 924 status = ice_aq_get_phy_caps(hw->port_info, false, 925 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 926 devm_kfree(ice_hw_to_dev(hw), pcaps); 927 if (status) 928 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 929 status); 930 931 /* Initialize port_info struct with link information */ 932 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 933 if (status) 934 goto err_unroll_sched; 935 936 /* need a valid SW entry point to build a Tx tree */ 937 if (!hw->sw_entry_point_layer) { 938 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 939 status = ICE_ERR_CFG; 940 goto err_unroll_sched; 941 } 942 INIT_LIST_HEAD(&hw->agg_list); 943 /* Initialize max burst size */ 944 if (!hw->max_burst_size) 945 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 946 947 status = ice_init_fltr_mgmt_struct(hw); 948 if (status) 949 goto err_unroll_sched; 950 951 /* Get MAC information */ 952 /* A single port can report up to two (LAN and WoL) addresses */ 953 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 954 sizeof(struct ice_aqc_manage_mac_read_resp), 955 GFP_KERNEL); 956 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 957 958 if (!mac_buf) { 959 status = ICE_ERR_NO_MEMORY; 960 goto err_unroll_fltr_mgmt_struct; 961 } 962 963 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 964 devm_kfree(ice_hw_to_dev(hw), mac_buf); 965 966 if (status) 967 goto err_unroll_fltr_mgmt_struct; 968 /* enable jumbo frame support at MAC level */ 969 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 970 if (status) 971 goto err_unroll_fltr_mgmt_struct; 972 /* Obtain counter base index which would be used by flow director */ 973 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 974 if (status) 975 goto err_unroll_fltr_mgmt_struct; 976 status = ice_init_hw_tbls(hw); 977 if (status) 978 goto err_unroll_fltr_mgmt_struct; 979 mutex_init(&hw->tnl_lock); 980 return 0; 981 982 err_unroll_fltr_mgmt_struct: 983 ice_cleanup_fltr_mgmt_struct(hw); 984 err_unroll_sched: 985 ice_sched_cleanup_all(hw); 986 err_unroll_alloc: 987 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 988 err_unroll_cqinit: 989 ice_destroy_all_ctrlq(hw); 990 return status; 991 } 992 993 /** 994 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 995 * @hw: pointer to the hardware structure 996 * 997 * This should be called only during nominal operation, not as a result of 998 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 999 * applicable initializations if it fails for any reason. 1000 */ 1001 void ice_deinit_hw(struct ice_hw *hw) 1002 { 1003 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1004 ice_cleanup_fltr_mgmt_struct(hw); 1005 1006 ice_sched_cleanup_all(hw); 1007 ice_sched_clear_agg(hw); 1008 ice_free_seg(hw); 1009 ice_free_hw_tbls(hw); 1010 mutex_destroy(&hw->tnl_lock); 1011 1012 if (hw->port_info) { 1013 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1014 hw->port_info = NULL; 1015 } 1016 1017 /* Attempt to disable FW logging before shutting down control queues */ 1018 ice_cfg_fw_log(hw, false); 1019 ice_destroy_all_ctrlq(hw); 1020 1021 /* Clear VSI contexts if not already cleared */ 1022 ice_clear_all_vsi_ctx(hw); 1023 } 1024 1025 /** 1026 * ice_check_reset - Check to see if a global reset is complete 1027 * @hw: pointer to the hardware structure 1028 */ 1029 enum ice_status ice_check_reset(struct ice_hw *hw) 1030 { 1031 u32 cnt, reg = 0, grst_timeout, uld_mask; 1032 1033 /* Poll for Device Active state in case a recent CORER, GLOBR, 1034 * or EMPR has occurred. The grst delay value is in 100ms units. 1035 * Add 1sec for outstanding AQ commands that can take a long time. 1036 */ 1037 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1038 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1039 1040 for (cnt = 0; cnt < grst_timeout; cnt++) { 1041 mdelay(100); 1042 reg = rd32(hw, GLGEN_RSTAT); 1043 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1044 break; 1045 } 1046 1047 if (cnt == grst_timeout) { 1048 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1049 return ICE_ERR_RESET_FAILED; 1050 } 1051 1052 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1053 GLNVM_ULD_PCIER_DONE_1_M |\ 1054 GLNVM_ULD_CORER_DONE_M |\ 1055 GLNVM_ULD_GLOBR_DONE_M |\ 1056 GLNVM_ULD_POR_DONE_M |\ 1057 GLNVM_ULD_POR_DONE_1_M |\ 1058 GLNVM_ULD_PCIER_DONE_2_M) 1059 1060 uld_mask = ICE_RESET_DONE_MASK; 1061 1062 /* Device is Active; check Global Reset processes are done */ 1063 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1064 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1065 if (reg == uld_mask) { 1066 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1067 break; 1068 } 1069 mdelay(10); 1070 } 1071 1072 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1073 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1074 reg); 1075 return ICE_ERR_RESET_FAILED; 1076 } 1077 1078 return 0; 1079 } 1080 1081 /** 1082 * ice_pf_reset - Reset the PF 1083 * @hw: pointer to the hardware structure 1084 * 1085 * If a global reset has been triggered, this function checks 1086 * for its completion and then issues the PF reset 1087 */ 1088 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1089 { 1090 u32 cnt, reg; 1091 1092 /* If at function entry a global reset was already in progress, i.e. 1093 * state is not 'device active' or any of the reset done bits are not 1094 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1095 * global reset is done. 1096 */ 1097 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1098 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1099 /* poll on global reset currently in progress until done */ 1100 if (ice_check_reset(hw)) 1101 return ICE_ERR_RESET_FAILED; 1102 1103 return 0; 1104 } 1105 1106 /* Reset the PF */ 1107 reg = rd32(hw, PFGEN_CTRL); 1108 1109 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1110 1111 /* Wait for the PFR to complete. The wait time is the global config lock 1112 * timeout plus the PFR timeout which will account for a possible reset 1113 * that is occurring during a download package operation. 1114 */ 1115 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1116 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1117 reg = rd32(hw, PFGEN_CTRL); 1118 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1119 break; 1120 1121 mdelay(1); 1122 } 1123 1124 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1125 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1126 return ICE_ERR_RESET_FAILED; 1127 } 1128 1129 return 0; 1130 } 1131 1132 /** 1133 * ice_reset - Perform different types of reset 1134 * @hw: pointer to the hardware structure 1135 * @req: reset request 1136 * 1137 * This function triggers a reset as specified by the req parameter. 1138 * 1139 * Note: 1140 * If anything other than a PF reset is triggered, PXE mode is restored. 1141 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1142 * interface has been restored in the rebuild flow. 1143 */ 1144 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1145 { 1146 u32 val = 0; 1147 1148 switch (req) { 1149 case ICE_RESET_PFR: 1150 return ice_pf_reset(hw); 1151 case ICE_RESET_CORER: 1152 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1153 val = GLGEN_RTRIG_CORER_M; 1154 break; 1155 case ICE_RESET_GLOBR: 1156 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1157 val = GLGEN_RTRIG_GLOBR_M; 1158 break; 1159 default: 1160 return ICE_ERR_PARAM; 1161 } 1162 1163 val |= rd32(hw, GLGEN_RTRIG); 1164 wr32(hw, GLGEN_RTRIG, val); 1165 ice_flush(hw); 1166 1167 /* wait for the FW to be ready */ 1168 return ice_check_reset(hw); 1169 } 1170 1171 /** 1172 * ice_copy_rxq_ctx_to_hw 1173 * @hw: pointer to the hardware structure 1174 * @ice_rxq_ctx: pointer to the rxq context 1175 * @rxq_index: the index of the Rx queue 1176 * 1177 * Copies rxq context from dense structure to HW register space 1178 */ 1179 static enum ice_status 1180 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1181 { 1182 u8 i; 1183 1184 if (!ice_rxq_ctx) 1185 return ICE_ERR_BAD_PTR; 1186 1187 if (rxq_index > QRX_CTRL_MAX_INDEX) 1188 return ICE_ERR_PARAM; 1189 1190 /* Copy each dword separately to HW */ 1191 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1192 wr32(hw, QRX_CONTEXT(i, rxq_index), 1193 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1194 1195 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1196 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1197 } 1198 1199 return 0; 1200 } 1201 1202 /* LAN Rx Queue Context */ 1203 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1204 /* Field Width LSB */ 1205 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1206 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1207 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1208 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1209 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1210 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1211 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1212 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1213 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1214 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1215 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1216 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1217 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1218 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1219 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1220 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1221 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1222 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1223 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1224 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1225 { 0 } 1226 }; 1227 1228 /** 1229 * ice_write_rxq_ctx 1230 * @hw: pointer to the hardware structure 1231 * @rlan_ctx: pointer to the rxq context 1232 * @rxq_index: the index of the Rx queue 1233 * 1234 * Converts rxq context from sparse to dense structure and then writes 1235 * it to HW register space and enables the hardware to prefetch descriptors 1236 * instead of only fetching them on demand 1237 */ 1238 enum ice_status 1239 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1240 u32 rxq_index) 1241 { 1242 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1243 1244 if (!rlan_ctx) 1245 return ICE_ERR_BAD_PTR; 1246 1247 rlan_ctx->prefena = 1; 1248 1249 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1250 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1251 } 1252 1253 /* LAN Tx Queue Context */ 1254 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1255 /* Field Width LSB */ 1256 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1257 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1258 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1259 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1260 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1261 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1262 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1263 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1264 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1265 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1266 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1267 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1268 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1269 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1270 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1271 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1272 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1273 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1274 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1275 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1276 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1277 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1278 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1279 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1280 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1281 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1282 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1283 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1284 { 0 } 1285 }; 1286 1287 /* FW Admin Queue command wrappers */ 1288 1289 /* Software lock/mutex that is meant to be held while the Global Config Lock 1290 * in firmware is acquired by the software to prevent most (but not all) types 1291 * of AQ commands from being sent to FW 1292 */ 1293 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1294 1295 /** 1296 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1297 * @hw: pointer to the HW struct 1298 * @desc: descriptor describing the command 1299 * @buf: buffer to use for indirect commands (NULL for direct commands) 1300 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1301 * @cd: pointer to command details structure 1302 * 1303 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1304 */ 1305 enum ice_status 1306 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1307 u16 buf_size, struct ice_sq_cd *cd) 1308 { 1309 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1310 bool lock_acquired = false; 1311 enum ice_status status; 1312 1313 /* When a package download is in process (i.e. when the firmware's 1314 * Global Configuration Lock resource is held), only the Download 1315 * Package, Get Version, Get Package Info List and Release Resource 1316 * (with resource ID set to Global Config Lock) AdminQ commands are 1317 * allowed; all others must block until the package download completes 1318 * and the Global Config Lock is released. See also 1319 * ice_acquire_global_cfg_lock(). 1320 */ 1321 switch (le16_to_cpu(desc->opcode)) { 1322 case ice_aqc_opc_download_pkg: 1323 case ice_aqc_opc_get_pkg_info_list: 1324 case ice_aqc_opc_get_ver: 1325 break; 1326 case ice_aqc_opc_release_res: 1327 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1328 break; 1329 fallthrough; 1330 default: 1331 mutex_lock(&ice_global_cfg_lock_sw); 1332 lock_acquired = true; 1333 break; 1334 } 1335 1336 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1337 if (lock_acquired) 1338 mutex_unlock(&ice_global_cfg_lock_sw); 1339 1340 return status; 1341 } 1342 1343 /** 1344 * ice_aq_get_fw_ver 1345 * @hw: pointer to the HW struct 1346 * @cd: pointer to command details structure or NULL 1347 * 1348 * Get the firmware version (0x0001) from the admin queue commands 1349 */ 1350 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1351 { 1352 struct ice_aqc_get_ver *resp; 1353 struct ice_aq_desc desc; 1354 enum ice_status status; 1355 1356 resp = &desc.params.get_ver; 1357 1358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1359 1360 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1361 1362 if (!status) { 1363 hw->fw_branch = resp->fw_branch; 1364 hw->fw_maj_ver = resp->fw_major; 1365 hw->fw_min_ver = resp->fw_minor; 1366 hw->fw_patch = resp->fw_patch; 1367 hw->fw_build = le32_to_cpu(resp->fw_build); 1368 hw->api_branch = resp->api_branch; 1369 hw->api_maj_ver = resp->api_major; 1370 hw->api_min_ver = resp->api_minor; 1371 hw->api_patch = resp->api_patch; 1372 } 1373 1374 return status; 1375 } 1376 1377 /** 1378 * ice_aq_send_driver_ver 1379 * @hw: pointer to the HW struct 1380 * @dv: driver's major, minor version 1381 * @cd: pointer to command details structure or NULL 1382 * 1383 * Send the driver version (0x0002) to the firmware 1384 */ 1385 enum ice_status 1386 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1387 struct ice_sq_cd *cd) 1388 { 1389 struct ice_aqc_driver_ver *cmd; 1390 struct ice_aq_desc desc; 1391 u16 len; 1392 1393 cmd = &desc.params.driver_ver; 1394 1395 if (!dv) 1396 return ICE_ERR_PARAM; 1397 1398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1399 1400 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1401 cmd->major_ver = dv->major_ver; 1402 cmd->minor_ver = dv->minor_ver; 1403 cmd->build_ver = dv->build_ver; 1404 cmd->subbuild_ver = dv->subbuild_ver; 1405 1406 len = 0; 1407 while (len < sizeof(dv->driver_string) && 1408 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1409 len++; 1410 1411 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1412 } 1413 1414 /** 1415 * ice_aq_q_shutdown 1416 * @hw: pointer to the HW struct 1417 * @unloading: is the driver unloading itself 1418 * 1419 * Tell the Firmware that we're shutting down the AdminQ and whether 1420 * or not the driver is unloading as well (0x0003). 1421 */ 1422 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1423 { 1424 struct ice_aqc_q_shutdown *cmd; 1425 struct ice_aq_desc desc; 1426 1427 cmd = &desc.params.q_shutdown; 1428 1429 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1430 1431 if (unloading) 1432 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1433 1434 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1435 } 1436 1437 /** 1438 * ice_aq_req_res 1439 * @hw: pointer to the HW struct 1440 * @res: resource ID 1441 * @access: access type 1442 * @sdp_number: resource number 1443 * @timeout: the maximum time in ms that the driver may hold the resource 1444 * @cd: pointer to command details structure or NULL 1445 * 1446 * Requests common resource using the admin queue commands (0x0008). 1447 * When attempting to acquire the Global Config Lock, the driver can 1448 * learn of three states: 1449 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1450 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1451 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1452 * successfully downloaded the package; the driver does 1453 * not have to download the package and can continue 1454 * loading 1455 * 1456 * Note that if the caller is in an acquire lock, perform action, release lock 1457 * phase of operation, it is possible that the FW may detect a timeout and issue 1458 * a CORER. In this case, the driver will receive a CORER interrupt and will 1459 * have to determine its cause. The calling thread that is handling this flow 1460 * will likely get an error propagated back to it indicating the Download 1461 * Package, Update Package or the Release Resource AQ commands timed out. 1462 */ 1463 static enum ice_status 1464 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1465 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1466 struct ice_sq_cd *cd) 1467 { 1468 struct ice_aqc_req_res *cmd_resp; 1469 struct ice_aq_desc desc; 1470 enum ice_status status; 1471 1472 cmd_resp = &desc.params.res_owner; 1473 1474 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1475 1476 cmd_resp->res_id = cpu_to_le16(res); 1477 cmd_resp->access_type = cpu_to_le16(access); 1478 cmd_resp->res_number = cpu_to_le32(sdp_number); 1479 cmd_resp->timeout = cpu_to_le32(*timeout); 1480 *timeout = 0; 1481 1482 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1483 1484 /* The completion specifies the maximum time in ms that the driver 1485 * may hold the resource in the Timeout field. 1486 */ 1487 1488 /* Global config lock response utilizes an additional status field. 1489 * 1490 * If the Global config lock resource is held by some other driver, the 1491 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1492 * and the timeout field indicates the maximum time the current owner 1493 * of the resource has to free it. 1494 */ 1495 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1496 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1497 *timeout = le32_to_cpu(cmd_resp->timeout); 1498 return 0; 1499 } else if (le16_to_cpu(cmd_resp->status) == 1500 ICE_AQ_RES_GLBL_IN_PROG) { 1501 *timeout = le32_to_cpu(cmd_resp->timeout); 1502 return ICE_ERR_AQ_ERROR; 1503 } else if (le16_to_cpu(cmd_resp->status) == 1504 ICE_AQ_RES_GLBL_DONE) { 1505 return ICE_ERR_AQ_NO_WORK; 1506 } 1507 1508 /* invalid FW response, force a timeout immediately */ 1509 *timeout = 0; 1510 return ICE_ERR_AQ_ERROR; 1511 } 1512 1513 /* If the resource is held by some other driver, the command completes 1514 * with a busy return value and the timeout field indicates the maximum 1515 * time the current owner of the resource has to free it. 1516 */ 1517 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1518 *timeout = le32_to_cpu(cmd_resp->timeout); 1519 1520 return status; 1521 } 1522 1523 /** 1524 * ice_aq_release_res 1525 * @hw: pointer to the HW struct 1526 * @res: resource ID 1527 * @sdp_number: resource number 1528 * @cd: pointer to command details structure or NULL 1529 * 1530 * release common resource using the admin queue commands (0x0009) 1531 */ 1532 static enum ice_status 1533 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1534 struct ice_sq_cd *cd) 1535 { 1536 struct ice_aqc_req_res *cmd; 1537 struct ice_aq_desc desc; 1538 1539 cmd = &desc.params.res_owner; 1540 1541 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1542 1543 cmd->res_id = cpu_to_le16(res); 1544 cmd->res_number = cpu_to_le32(sdp_number); 1545 1546 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1547 } 1548 1549 /** 1550 * ice_acquire_res 1551 * @hw: pointer to the HW structure 1552 * @res: resource ID 1553 * @access: access type (read or write) 1554 * @timeout: timeout in milliseconds 1555 * 1556 * This function will attempt to acquire the ownership of a resource. 1557 */ 1558 enum ice_status 1559 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1560 enum ice_aq_res_access_type access, u32 timeout) 1561 { 1562 #define ICE_RES_POLLING_DELAY_MS 10 1563 u32 delay = ICE_RES_POLLING_DELAY_MS; 1564 u32 time_left = timeout; 1565 enum ice_status status; 1566 1567 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1568 1569 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1570 * previously acquired the resource and performed any necessary updates; 1571 * in this case the caller does not obtain the resource and has no 1572 * further work to do. 1573 */ 1574 if (status == ICE_ERR_AQ_NO_WORK) 1575 goto ice_acquire_res_exit; 1576 1577 if (status) 1578 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1579 1580 /* If necessary, poll until the current lock owner timeouts */ 1581 timeout = time_left; 1582 while (status && timeout && time_left) { 1583 mdelay(delay); 1584 timeout = (timeout > delay) ? timeout - delay : 0; 1585 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1586 1587 if (status == ICE_ERR_AQ_NO_WORK) 1588 /* lock free, but no work to do */ 1589 break; 1590 1591 if (!status) 1592 /* lock acquired */ 1593 break; 1594 } 1595 if (status && status != ICE_ERR_AQ_NO_WORK) 1596 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1597 1598 ice_acquire_res_exit: 1599 if (status == ICE_ERR_AQ_NO_WORK) { 1600 if (access == ICE_RES_WRITE) 1601 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1602 else 1603 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1604 } 1605 return status; 1606 } 1607 1608 /** 1609 * ice_release_res 1610 * @hw: pointer to the HW structure 1611 * @res: resource ID 1612 * 1613 * This function will release a resource using the proper Admin Command. 1614 */ 1615 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1616 { 1617 enum ice_status status; 1618 u32 total_delay = 0; 1619 1620 status = ice_aq_release_res(hw, res, 0, NULL); 1621 1622 /* there are some rare cases when trying to release the resource 1623 * results in an admin queue timeout, so handle them correctly 1624 */ 1625 while ((status == ICE_ERR_AQ_TIMEOUT) && 1626 (total_delay < hw->adminq.sq_cmd_timeout)) { 1627 mdelay(1); 1628 status = ice_aq_release_res(hw, res, 0, NULL); 1629 total_delay++; 1630 } 1631 } 1632 1633 /** 1634 * ice_aq_alloc_free_res - command to allocate/free resources 1635 * @hw: pointer to the HW struct 1636 * @num_entries: number of resource entries in buffer 1637 * @buf: Indirect buffer to hold data parameters and response 1638 * @buf_size: size of buffer for indirect commands 1639 * @opc: pass in the command opcode 1640 * @cd: pointer to command details structure or NULL 1641 * 1642 * Helper function to allocate/free resources using the admin queue commands 1643 */ 1644 enum ice_status 1645 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1646 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1647 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1648 { 1649 struct ice_aqc_alloc_free_res_cmd *cmd; 1650 struct ice_aq_desc desc; 1651 1652 cmd = &desc.params.sw_res_ctrl; 1653 1654 if (!buf) 1655 return ICE_ERR_PARAM; 1656 1657 if (buf_size < flex_array_size(buf, elem, num_entries)) 1658 return ICE_ERR_PARAM; 1659 1660 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1661 1662 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1663 1664 cmd->num_entries = cpu_to_le16(num_entries); 1665 1666 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1667 } 1668 1669 /** 1670 * ice_alloc_hw_res - allocate resource 1671 * @hw: pointer to the HW struct 1672 * @type: type of resource 1673 * @num: number of resources to allocate 1674 * @btm: allocate from bottom 1675 * @res: pointer to array that will receive the resources 1676 */ 1677 enum ice_status 1678 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1679 { 1680 struct ice_aqc_alloc_free_res_elem *buf; 1681 enum ice_status status; 1682 u16 buf_len; 1683 1684 buf_len = struct_size(buf, elem, num); 1685 buf = kzalloc(buf_len, GFP_KERNEL); 1686 if (!buf) 1687 return ICE_ERR_NO_MEMORY; 1688 1689 /* Prepare buffer to allocate resource. */ 1690 buf->num_elems = cpu_to_le16(num); 1691 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1692 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1693 if (btm) 1694 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1695 1696 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1697 ice_aqc_opc_alloc_res, NULL); 1698 if (status) 1699 goto ice_alloc_res_exit; 1700 1701 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1702 1703 ice_alloc_res_exit: 1704 kfree(buf); 1705 return status; 1706 } 1707 1708 /** 1709 * ice_free_hw_res - free allocated HW resource 1710 * @hw: pointer to the HW struct 1711 * @type: type of resource to free 1712 * @num: number of resources 1713 * @res: pointer to array that contains the resources to free 1714 */ 1715 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1716 { 1717 struct ice_aqc_alloc_free_res_elem *buf; 1718 enum ice_status status; 1719 u16 buf_len; 1720 1721 buf_len = struct_size(buf, elem, num); 1722 buf = kzalloc(buf_len, GFP_KERNEL); 1723 if (!buf) 1724 return ICE_ERR_NO_MEMORY; 1725 1726 /* Prepare buffer to free resource. */ 1727 buf->num_elems = cpu_to_le16(num); 1728 buf->res_type = cpu_to_le16(type); 1729 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1730 1731 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1732 ice_aqc_opc_free_res, NULL); 1733 if (status) 1734 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1735 1736 kfree(buf); 1737 return status; 1738 } 1739 1740 /** 1741 * ice_get_num_per_func - determine number of resources per PF 1742 * @hw: pointer to the HW structure 1743 * @max: value to be evenly split between each PF 1744 * 1745 * Determine the number of valid functions by going through the bitmap returned 1746 * from parsing capabilities and use this to calculate the number of resources 1747 * per PF based on the max value passed in. 1748 */ 1749 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1750 { 1751 u8 funcs; 1752 1753 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1754 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1755 ICE_CAPS_VALID_FUNCS_M); 1756 1757 if (!funcs) 1758 return 0; 1759 1760 return max / funcs; 1761 } 1762 1763 /** 1764 * ice_parse_common_caps - parse common device/function capabilities 1765 * @hw: pointer to the HW struct 1766 * @caps: pointer to common capabilities structure 1767 * @elem: the capability element to parse 1768 * @prefix: message prefix for tracing capabilities 1769 * 1770 * Given a capability element, extract relevant details into the common 1771 * capability structure. 1772 * 1773 * Returns: true if the capability matches one of the common capability ids, 1774 * false otherwise. 1775 */ 1776 static bool 1777 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1778 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1779 { 1780 u32 logical_id = le32_to_cpu(elem->logical_id); 1781 u32 phys_id = le32_to_cpu(elem->phys_id); 1782 u32 number = le32_to_cpu(elem->number); 1783 u16 cap = le16_to_cpu(elem->cap); 1784 bool found = true; 1785 1786 switch (cap) { 1787 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1788 caps->valid_functions = number; 1789 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1790 caps->valid_functions); 1791 break; 1792 case ICE_AQC_CAPS_SRIOV: 1793 caps->sr_iov_1_1 = (number == 1); 1794 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 1795 caps->sr_iov_1_1); 1796 break; 1797 case ICE_AQC_CAPS_DCB: 1798 caps->dcb = (number == 1); 1799 caps->active_tc_bitmap = logical_id; 1800 caps->maxtc = phys_id; 1801 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1802 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1803 caps->active_tc_bitmap); 1804 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1805 break; 1806 case ICE_AQC_CAPS_RSS: 1807 caps->rss_table_size = number; 1808 caps->rss_table_entry_width = logical_id; 1809 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1810 caps->rss_table_size); 1811 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1812 caps->rss_table_entry_width); 1813 break; 1814 case ICE_AQC_CAPS_RXQS: 1815 caps->num_rxq = number; 1816 caps->rxq_first_id = phys_id; 1817 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1818 caps->num_rxq); 1819 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1820 caps->rxq_first_id); 1821 break; 1822 case ICE_AQC_CAPS_TXQS: 1823 caps->num_txq = number; 1824 caps->txq_first_id = phys_id; 1825 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1826 caps->num_txq); 1827 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1828 caps->txq_first_id); 1829 break; 1830 case ICE_AQC_CAPS_MSIX: 1831 caps->num_msix_vectors = number; 1832 caps->msix_vector_first_id = phys_id; 1833 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1834 caps->num_msix_vectors); 1835 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1836 caps->msix_vector_first_id); 1837 break; 1838 case ICE_AQC_CAPS_PENDING_NVM_VER: 1839 caps->nvm_update_pending_nvm = true; 1840 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 1841 break; 1842 case ICE_AQC_CAPS_PENDING_OROM_VER: 1843 caps->nvm_update_pending_orom = true; 1844 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 1845 break; 1846 case ICE_AQC_CAPS_PENDING_NET_VER: 1847 caps->nvm_update_pending_netlist = true; 1848 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 1849 break; 1850 case ICE_AQC_CAPS_NVM_MGMT: 1851 caps->nvm_unified_update = 1852 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1853 true : false; 1854 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1855 caps->nvm_unified_update); 1856 break; 1857 case ICE_AQC_CAPS_MAX_MTU: 1858 caps->max_mtu = number; 1859 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1860 prefix, caps->max_mtu); 1861 break; 1862 default: 1863 /* Not one of the recognized common capabilities */ 1864 found = false; 1865 } 1866 1867 return found; 1868 } 1869 1870 /** 1871 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1872 * @hw: pointer to the HW structure 1873 * @caps: pointer to capabilities structure to fix 1874 * 1875 * Re-calculate the capabilities that are dependent on the number of physical 1876 * ports; i.e. some features are not supported or function differently on 1877 * devices with more than 4 ports. 1878 */ 1879 static void 1880 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1881 { 1882 /* This assumes device capabilities are always scanned before function 1883 * capabilities during the initialization flow. 1884 */ 1885 if (hw->dev_caps.num_funcs > 4) { 1886 /* Max 4 TCs per port */ 1887 caps->maxtc = 4; 1888 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 1889 caps->maxtc); 1890 } 1891 } 1892 1893 /** 1894 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1895 * @hw: pointer to the HW struct 1896 * @func_p: pointer to function capabilities structure 1897 * @cap: pointer to the capability element to parse 1898 * 1899 * Extract function capabilities for ICE_AQC_CAPS_VF. 1900 */ 1901 static void 1902 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1903 struct ice_aqc_list_caps_elem *cap) 1904 { 1905 u32 logical_id = le32_to_cpu(cap->logical_id); 1906 u32 number = le32_to_cpu(cap->number); 1907 1908 func_p->num_allocd_vfs = number; 1909 func_p->vf_base_id = logical_id; 1910 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 1911 func_p->num_allocd_vfs); 1912 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 1913 func_p->vf_base_id); 1914 } 1915 1916 /** 1917 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 1918 * @hw: pointer to the HW struct 1919 * @func_p: pointer to function capabilities structure 1920 * @cap: pointer to the capability element to parse 1921 * 1922 * Extract function capabilities for ICE_AQC_CAPS_VSI. 1923 */ 1924 static void 1925 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1926 struct ice_aqc_list_caps_elem *cap) 1927 { 1928 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 1929 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 1930 le32_to_cpu(cap->number)); 1931 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 1932 func_p->guar_num_vsi); 1933 } 1934 1935 /** 1936 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 1937 * @hw: pointer to the HW struct 1938 * @func_p: pointer to function capabilities structure 1939 * 1940 * Extract function capabilities for ICE_AQC_CAPS_FD. 1941 */ 1942 static void 1943 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 1944 { 1945 u32 reg_val, val; 1946 1947 reg_val = rd32(hw, GLQF_FD_SIZE); 1948 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1949 GLQF_FD_SIZE_FD_GSIZE_S; 1950 func_p->fd_fltr_guar = 1951 ice_get_num_per_func(hw, val); 1952 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1953 GLQF_FD_SIZE_FD_BSIZE_S; 1954 func_p->fd_fltr_best_effort = val; 1955 1956 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 1957 func_p->fd_fltr_guar); 1958 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 1959 func_p->fd_fltr_best_effort); 1960 } 1961 1962 /** 1963 * ice_parse_func_caps - Parse function capabilities 1964 * @hw: pointer to the HW struct 1965 * @func_p: pointer to function capabilities structure 1966 * @buf: buffer containing the function capability records 1967 * @cap_count: the number of capabilities 1968 * 1969 * Helper function to parse function (0x000A) capabilities list. For 1970 * capabilities shared between device and function, this relies on 1971 * ice_parse_common_caps. 1972 * 1973 * Loop through the list of provided capabilities and extract the relevant 1974 * data into the function capabilities structured. 1975 */ 1976 static void 1977 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1978 void *buf, u32 cap_count) 1979 { 1980 struct ice_aqc_list_caps_elem *cap_resp; 1981 u32 i; 1982 1983 cap_resp = buf; 1984 1985 memset(func_p, 0, sizeof(*func_p)); 1986 1987 for (i = 0; i < cap_count; i++) { 1988 u16 cap = le16_to_cpu(cap_resp[i].cap); 1989 bool found; 1990 1991 found = ice_parse_common_caps(hw, &func_p->common_cap, 1992 &cap_resp[i], "func caps"); 1993 1994 switch (cap) { 1995 case ICE_AQC_CAPS_VF: 1996 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 1997 break; 1998 case ICE_AQC_CAPS_VSI: 1999 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2000 break; 2001 case ICE_AQC_CAPS_FD: 2002 ice_parse_fdir_func_caps(hw, func_p); 2003 break; 2004 default: 2005 /* Don't list common capabilities as unknown */ 2006 if (!found) 2007 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2008 i, cap); 2009 break; 2010 } 2011 } 2012 2013 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2014 } 2015 2016 /** 2017 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2018 * @hw: pointer to the HW struct 2019 * @dev_p: pointer to device capabilities structure 2020 * @cap: capability element to parse 2021 * 2022 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2023 */ 2024 static void 2025 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2026 struct ice_aqc_list_caps_elem *cap) 2027 { 2028 u32 number = le32_to_cpu(cap->number); 2029 2030 dev_p->num_funcs = hweight32(number); 2031 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2032 dev_p->num_funcs); 2033 } 2034 2035 /** 2036 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2037 * @hw: pointer to the HW struct 2038 * @dev_p: pointer to device capabilities structure 2039 * @cap: capability element to parse 2040 * 2041 * Parse ICE_AQC_CAPS_VF for device capabilities. 2042 */ 2043 static void 2044 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2045 struct ice_aqc_list_caps_elem *cap) 2046 { 2047 u32 number = le32_to_cpu(cap->number); 2048 2049 dev_p->num_vfs_exposed = number; 2050 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2051 dev_p->num_vfs_exposed); 2052 } 2053 2054 /** 2055 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2056 * @hw: pointer to the HW struct 2057 * @dev_p: pointer to device capabilities structure 2058 * @cap: capability element to parse 2059 * 2060 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2061 */ 2062 static void 2063 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2064 struct ice_aqc_list_caps_elem *cap) 2065 { 2066 u32 number = le32_to_cpu(cap->number); 2067 2068 dev_p->num_vsi_allocd_to_host = number; 2069 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2070 dev_p->num_vsi_allocd_to_host); 2071 } 2072 2073 /** 2074 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2075 * @hw: pointer to the HW struct 2076 * @dev_p: pointer to device capabilities structure 2077 * @cap: capability element to parse 2078 * 2079 * Parse ICE_AQC_CAPS_FD for device capabilities. 2080 */ 2081 static void 2082 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2083 struct ice_aqc_list_caps_elem *cap) 2084 { 2085 u32 number = le32_to_cpu(cap->number); 2086 2087 dev_p->num_flow_director_fltr = number; 2088 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2089 dev_p->num_flow_director_fltr); 2090 } 2091 2092 /** 2093 * ice_parse_dev_caps - Parse device capabilities 2094 * @hw: pointer to the HW struct 2095 * @dev_p: pointer to device capabilities structure 2096 * @buf: buffer containing the device capability records 2097 * @cap_count: the number of capabilities 2098 * 2099 * Helper device to parse device (0x000B) capabilities list. For 2100 * capabilities shared between device and function, this relies on 2101 * ice_parse_common_caps. 2102 * 2103 * Loop through the list of provided capabilities and extract the relevant 2104 * data into the device capabilities structured. 2105 */ 2106 static void 2107 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2108 void *buf, u32 cap_count) 2109 { 2110 struct ice_aqc_list_caps_elem *cap_resp; 2111 u32 i; 2112 2113 cap_resp = buf; 2114 2115 memset(dev_p, 0, sizeof(*dev_p)); 2116 2117 for (i = 0; i < cap_count; i++) { 2118 u16 cap = le16_to_cpu(cap_resp[i].cap); 2119 bool found; 2120 2121 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2122 &cap_resp[i], "dev caps"); 2123 2124 switch (cap) { 2125 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2126 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2127 break; 2128 case ICE_AQC_CAPS_VF: 2129 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2130 break; 2131 case ICE_AQC_CAPS_VSI: 2132 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2133 break; 2134 case ICE_AQC_CAPS_FD: 2135 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2136 break; 2137 default: 2138 /* Don't list common capabilities as unknown */ 2139 if (!found) 2140 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2141 i, cap); 2142 break; 2143 } 2144 } 2145 2146 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2147 } 2148 2149 /** 2150 * ice_aq_list_caps - query function/device capabilities 2151 * @hw: pointer to the HW struct 2152 * @buf: a buffer to hold the capabilities 2153 * @buf_size: size of the buffer 2154 * @cap_count: if not NULL, set to the number of capabilities reported 2155 * @opc: capabilities type to discover, device or function 2156 * @cd: pointer to command details structure or NULL 2157 * 2158 * Get the function (0x000A) or device (0x000B) capabilities description from 2159 * firmware and store it in the buffer. 2160 * 2161 * If the cap_count pointer is not NULL, then it is set to the number of 2162 * capabilities firmware will report. Note that if the buffer size is too 2163 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2164 * cap_count will still be updated in this case. It is recommended that the 2165 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2166 * firmware could return) to avoid this. 2167 */ 2168 enum ice_status 2169 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2170 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2171 { 2172 struct ice_aqc_list_caps *cmd; 2173 struct ice_aq_desc desc; 2174 enum ice_status status; 2175 2176 cmd = &desc.params.get_cap; 2177 2178 if (opc != ice_aqc_opc_list_func_caps && 2179 opc != ice_aqc_opc_list_dev_caps) 2180 return ICE_ERR_PARAM; 2181 2182 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2183 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2184 2185 if (cap_count) 2186 *cap_count = le32_to_cpu(cmd->count); 2187 2188 return status; 2189 } 2190 2191 /** 2192 * ice_discover_dev_caps - Read and extract device capabilities 2193 * @hw: pointer to the hardware structure 2194 * @dev_caps: pointer to device capabilities structure 2195 * 2196 * Read the device capabilities and extract them into the dev_caps structure 2197 * for later use. 2198 */ 2199 enum ice_status 2200 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2201 { 2202 enum ice_status status; 2203 u32 cap_count = 0; 2204 void *cbuf; 2205 2206 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2207 if (!cbuf) 2208 return ICE_ERR_NO_MEMORY; 2209 2210 /* Although the driver doesn't know the number of capabilities the 2211 * device will return, we can simply send a 4KB buffer, the maximum 2212 * possible size that firmware can return. 2213 */ 2214 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2215 2216 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2217 ice_aqc_opc_list_dev_caps, NULL); 2218 if (!status) 2219 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2220 kfree(cbuf); 2221 2222 return status; 2223 } 2224 2225 /** 2226 * ice_discover_func_caps - Read and extract function capabilities 2227 * @hw: pointer to the hardware structure 2228 * @func_caps: pointer to function capabilities structure 2229 * 2230 * Read the function capabilities and extract them into the func_caps structure 2231 * for later use. 2232 */ 2233 static enum ice_status 2234 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2235 { 2236 enum ice_status status; 2237 u32 cap_count = 0; 2238 void *cbuf; 2239 2240 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2241 if (!cbuf) 2242 return ICE_ERR_NO_MEMORY; 2243 2244 /* Although the driver doesn't know the number of capabilities the 2245 * device will return, we can simply send a 4KB buffer, the maximum 2246 * possible size that firmware can return. 2247 */ 2248 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2249 2250 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2251 ice_aqc_opc_list_func_caps, NULL); 2252 if (!status) 2253 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2254 kfree(cbuf); 2255 2256 return status; 2257 } 2258 2259 /** 2260 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2261 * @hw: pointer to the hardware structure 2262 */ 2263 void ice_set_safe_mode_caps(struct ice_hw *hw) 2264 { 2265 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2266 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2267 struct ice_hw_common_caps cached_caps; 2268 u32 num_funcs; 2269 2270 /* cache some func_caps values that should be restored after memset */ 2271 cached_caps = func_caps->common_cap; 2272 2273 /* unset func capabilities */ 2274 memset(func_caps, 0, sizeof(*func_caps)); 2275 2276 #define ICE_RESTORE_FUNC_CAP(name) \ 2277 func_caps->common_cap.name = cached_caps.name 2278 2279 /* restore cached values */ 2280 ICE_RESTORE_FUNC_CAP(valid_functions); 2281 ICE_RESTORE_FUNC_CAP(txq_first_id); 2282 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2283 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2284 ICE_RESTORE_FUNC_CAP(max_mtu); 2285 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2286 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2287 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2288 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2289 2290 /* one Tx and one Rx queue in safe mode */ 2291 func_caps->common_cap.num_rxq = 1; 2292 func_caps->common_cap.num_txq = 1; 2293 2294 /* two MSIX vectors, one for traffic and one for misc causes */ 2295 func_caps->common_cap.num_msix_vectors = 2; 2296 func_caps->guar_num_vsi = 1; 2297 2298 /* cache some dev_caps values that should be restored after memset */ 2299 cached_caps = dev_caps->common_cap; 2300 num_funcs = dev_caps->num_funcs; 2301 2302 /* unset dev capabilities */ 2303 memset(dev_caps, 0, sizeof(*dev_caps)); 2304 2305 #define ICE_RESTORE_DEV_CAP(name) \ 2306 dev_caps->common_cap.name = cached_caps.name 2307 2308 /* restore cached values */ 2309 ICE_RESTORE_DEV_CAP(valid_functions); 2310 ICE_RESTORE_DEV_CAP(txq_first_id); 2311 ICE_RESTORE_DEV_CAP(rxq_first_id); 2312 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2313 ICE_RESTORE_DEV_CAP(max_mtu); 2314 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2315 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2316 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2317 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2318 dev_caps->num_funcs = num_funcs; 2319 2320 /* one Tx and one Rx queue per function in safe mode */ 2321 dev_caps->common_cap.num_rxq = num_funcs; 2322 dev_caps->common_cap.num_txq = num_funcs; 2323 2324 /* two MSIX vectors per function */ 2325 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2326 } 2327 2328 /** 2329 * ice_get_caps - get info about the HW 2330 * @hw: pointer to the hardware structure 2331 */ 2332 enum ice_status ice_get_caps(struct ice_hw *hw) 2333 { 2334 enum ice_status status; 2335 2336 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2337 if (status) 2338 return status; 2339 2340 return ice_discover_func_caps(hw, &hw->func_caps); 2341 } 2342 2343 /** 2344 * ice_aq_manage_mac_write - manage MAC address write command 2345 * @hw: pointer to the HW struct 2346 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2347 * @flags: flags to control write behavior 2348 * @cd: pointer to command details structure or NULL 2349 * 2350 * This function is used to write MAC address to the NVM (0x0108). 2351 */ 2352 enum ice_status 2353 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2354 struct ice_sq_cd *cd) 2355 { 2356 struct ice_aqc_manage_mac_write *cmd; 2357 struct ice_aq_desc desc; 2358 2359 cmd = &desc.params.mac_write; 2360 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2361 2362 cmd->flags = flags; 2363 ether_addr_copy(cmd->mac_addr, mac_addr); 2364 2365 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2366 } 2367 2368 /** 2369 * ice_aq_clear_pxe_mode 2370 * @hw: pointer to the HW struct 2371 * 2372 * Tell the firmware that the driver is taking over from PXE (0x0110). 2373 */ 2374 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2375 { 2376 struct ice_aq_desc desc; 2377 2378 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2379 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2380 2381 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2382 } 2383 2384 /** 2385 * ice_clear_pxe_mode - clear pxe operations mode 2386 * @hw: pointer to the HW struct 2387 * 2388 * Make sure all PXE mode settings are cleared, including things 2389 * like descriptor fetch/write-back mode. 2390 */ 2391 void ice_clear_pxe_mode(struct ice_hw *hw) 2392 { 2393 if (ice_check_sq_alive(hw, &hw->adminq)) 2394 ice_aq_clear_pxe_mode(hw); 2395 } 2396 2397 /** 2398 * ice_get_link_speed_based_on_phy_type - returns link speed 2399 * @phy_type_low: lower part of phy_type 2400 * @phy_type_high: higher part of phy_type 2401 * 2402 * This helper function will convert an entry in PHY type structure 2403 * [phy_type_low, phy_type_high] to its corresponding link speed. 2404 * Note: In the structure of [phy_type_low, phy_type_high], there should 2405 * be one bit set, as this function will convert one PHY type to its 2406 * speed. 2407 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2408 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2409 */ 2410 static u16 2411 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2412 { 2413 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2414 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2415 2416 switch (phy_type_low) { 2417 case ICE_PHY_TYPE_LOW_100BASE_TX: 2418 case ICE_PHY_TYPE_LOW_100M_SGMII: 2419 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2420 break; 2421 case ICE_PHY_TYPE_LOW_1000BASE_T: 2422 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2423 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2424 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2425 case ICE_PHY_TYPE_LOW_1G_SGMII: 2426 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2427 break; 2428 case ICE_PHY_TYPE_LOW_2500BASE_T: 2429 case ICE_PHY_TYPE_LOW_2500BASE_X: 2430 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2431 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2432 break; 2433 case ICE_PHY_TYPE_LOW_5GBASE_T: 2434 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2435 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2436 break; 2437 case ICE_PHY_TYPE_LOW_10GBASE_T: 2438 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2439 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2440 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2441 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2442 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2443 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2444 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2445 break; 2446 case ICE_PHY_TYPE_LOW_25GBASE_T: 2447 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2448 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2449 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2450 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2451 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2452 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2453 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2454 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2455 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2456 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2457 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2458 break; 2459 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2460 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2461 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2462 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2463 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2464 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2465 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2466 break; 2467 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2468 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2469 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2470 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2471 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2472 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2473 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2474 case ICE_PHY_TYPE_LOW_50G_AUI2: 2475 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2476 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2477 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2478 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2479 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2480 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2481 case ICE_PHY_TYPE_LOW_50G_AUI1: 2482 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2483 break; 2484 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2485 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2486 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2487 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2488 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2489 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2490 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2491 case ICE_PHY_TYPE_LOW_100G_AUI4: 2492 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2493 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2494 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2495 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2496 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2497 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2498 break; 2499 default: 2500 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2501 break; 2502 } 2503 2504 switch (phy_type_high) { 2505 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2506 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2507 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2508 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2509 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2510 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2511 break; 2512 default: 2513 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2514 break; 2515 } 2516 2517 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2518 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2519 return ICE_AQ_LINK_SPEED_UNKNOWN; 2520 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2521 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2522 return ICE_AQ_LINK_SPEED_UNKNOWN; 2523 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2524 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2525 return speed_phy_type_low; 2526 else 2527 return speed_phy_type_high; 2528 } 2529 2530 /** 2531 * ice_update_phy_type 2532 * @phy_type_low: pointer to the lower part of phy_type 2533 * @phy_type_high: pointer to the higher part of phy_type 2534 * @link_speeds_bitmap: targeted link speeds bitmap 2535 * 2536 * Note: For the link_speeds_bitmap structure, you can check it at 2537 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2538 * link_speeds_bitmap include multiple speeds. 2539 * 2540 * Each entry in this [phy_type_low, phy_type_high] structure will 2541 * present a certain link speed. This helper function will turn on bits 2542 * in [phy_type_low, phy_type_high] structure based on the value of 2543 * link_speeds_bitmap input parameter. 2544 */ 2545 void 2546 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2547 u16 link_speeds_bitmap) 2548 { 2549 u64 pt_high; 2550 u64 pt_low; 2551 int index; 2552 u16 speed; 2553 2554 /* We first check with low part of phy_type */ 2555 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2556 pt_low = BIT_ULL(index); 2557 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2558 2559 if (link_speeds_bitmap & speed) 2560 *phy_type_low |= BIT_ULL(index); 2561 } 2562 2563 /* We then check with high part of phy_type */ 2564 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2565 pt_high = BIT_ULL(index); 2566 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2567 2568 if (link_speeds_bitmap & speed) 2569 *phy_type_high |= BIT_ULL(index); 2570 } 2571 } 2572 2573 /** 2574 * ice_aq_set_phy_cfg 2575 * @hw: pointer to the HW struct 2576 * @pi: port info structure of the interested logical port 2577 * @cfg: structure with PHY configuration data to be set 2578 * @cd: pointer to command details structure or NULL 2579 * 2580 * Set the various PHY configuration parameters supported on the Port. 2581 * One or more of the Set PHY config parameters may be ignored in an MFP 2582 * mode as the PF may not have the privilege to set some of the PHY Config 2583 * parameters. This status will be indicated by the command response (0x0601). 2584 */ 2585 enum ice_status 2586 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2587 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2588 { 2589 struct ice_aq_desc desc; 2590 enum ice_status status; 2591 2592 if (!cfg) 2593 return ICE_ERR_PARAM; 2594 2595 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2596 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2597 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2598 cfg->caps); 2599 2600 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2601 } 2602 2603 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2604 desc.params.set_phy.lport_num = pi->lport; 2605 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2606 2607 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2608 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2609 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2610 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2611 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2612 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2613 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2614 cfg->low_power_ctrl_an); 2615 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2616 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2617 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2618 cfg->link_fec_opt); 2619 2620 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2621 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2622 status = 0; 2623 2624 if (!status) 2625 pi->phy.curr_user_phy_cfg = *cfg; 2626 2627 return status; 2628 } 2629 2630 /** 2631 * ice_update_link_info - update status of the HW network link 2632 * @pi: port info structure of the interested logical port 2633 */ 2634 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2635 { 2636 struct ice_link_status *li; 2637 enum ice_status status; 2638 2639 if (!pi) 2640 return ICE_ERR_PARAM; 2641 2642 li = &pi->phy.link_info; 2643 2644 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2645 if (status) 2646 return status; 2647 2648 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2649 struct ice_aqc_get_phy_caps_data *pcaps; 2650 struct ice_hw *hw; 2651 2652 hw = pi->hw; 2653 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2654 GFP_KERNEL); 2655 if (!pcaps) 2656 return ICE_ERR_NO_MEMORY; 2657 2658 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2659 pcaps, NULL); 2660 2661 devm_kfree(ice_hw_to_dev(hw), pcaps); 2662 } 2663 2664 return status; 2665 } 2666 2667 /** 2668 * ice_cache_phy_user_req 2669 * @pi: port information structure 2670 * @cache_data: PHY logging data 2671 * @cache_mode: PHY logging mode 2672 * 2673 * Log the user request on (FC, FEC, SPEED) for later use. 2674 */ 2675 static void 2676 ice_cache_phy_user_req(struct ice_port_info *pi, 2677 struct ice_phy_cache_mode_data cache_data, 2678 enum ice_phy_cache_mode cache_mode) 2679 { 2680 if (!pi) 2681 return; 2682 2683 switch (cache_mode) { 2684 case ICE_FC_MODE: 2685 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2686 break; 2687 case ICE_SPEED_MODE: 2688 pi->phy.curr_user_speed_req = 2689 cache_data.data.curr_user_speed_req; 2690 break; 2691 case ICE_FEC_MODE: 2692 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2693 break; 2694 default: 2695 break; 2696 } 2697 } 2698 2699 /** 2700 * ice_caps_to_fc_mode 2701 * @caps: PHY capabilities 2702 * 2703 * Convert PHY FC capabilities to ice FC mode 2704 */ 2705 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2706 { 2707 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2708 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2709 return ICE_FC_FULL; 2710 2711 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2712 return ICE_FC_TX_PAUSE; 2713 2714 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2715 return ICE_FC_RX_PAUSE; 2716 2717 return ICE_FC_NONE; 2718 } 2719 2720 /** 2721 * ice_caps_to_fec_mode 2722 * @caps: PHY capabilities 2723 * @fec_options: Link FEC options 2724 * 2725 * Convert PHY FEC capabilities to ice FEC mode 2726 */ 2727 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2728 { 2729 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2730 return ICE_FEC_AUTO; 2731 2732 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2733 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2734 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2735 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2736 return ICE_FEC_BASER; 2737 2738 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2739 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2740 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2741 return ICE_FEC_RS; 2742 2743 return ICE_FEC_NONE; 2744 } 2745 2746 /** 2747 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2748 * @pi: port information structure 2749 * @cfg: PHY configuration data to set FC mode 2750 * @req_mode: FC mode to configure 2751 */ 2752 enum ice_status 2753 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2754 enum ice_fc_mode req_mode) 2755 { 2756 struct ice_phy_cache_mode_data cache_data; 2757 u8 pause_mask = 0x0; 2758 2759 if (!pi || !cfg) 2760 return ICE_ERR_BAD_PTR; 2761 2762 switch (req_mode) { 2763 case ICE_FC_FULL: 2764 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2765 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2766 break; 2767 case ICE_FC_RX_PAUSE: 2768 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2769 break; 2770 case ICE_FC_TX_PAUSE: 2771 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2772 break; 2773 default: 2774 break; 2775 } 2776 2777 /* clear the old pause settings */ 2778 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2779 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2780 2781 /* set the new capabilities */ 2782 cfg->caps |= pause_mask; 2783 2784 /* Cache user FC request */ 2785 cache_data.data.curr_user_fc_req = req_mode; 2786 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2787 2788 return 0; 2789 } 2790 2791 /** 2792 * ice_set_fc 2793 * @pi: port information structure 2794 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2795 * @ena_auto_link_update: enable automatic link update 2796 * 2797 * Set the requested flow control mode. 2798 */ 2799 enum ice_status 2800 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2801 { 2802 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2803 struct ice_aqc_get_phy_caps_data *pcaps; 2804 enum ice_status status; 2805 struct ice_hw *hw; 2806 2807 if (!pi || !aq_failures) 2808 return ICE_ERR_BAD_PTR; 2809 2810 *aq_failures = 0; 2811 hw = pi->hw; 2812 2813 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2814 if (!pcaps) 2815 return ICE_ERR_NO_MEMORY; 2816 2817 /* Get the current PHY config */ 2818 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2819 NULL); 2820 if (status) { 2821 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2822 goto out; 2823 } 2824 2825 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2826 2827 /* Configure the set PHY data */ 2828 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2829 if (status) 2830 goto out; 2831 2832 /* If the capabilities have changed, then set the new config */ 2833 if (cfg.caps != pcaps->caps) { 2834 int retry_count, retry_max = 10; 2835 2836 /* Auto restart link so settings take effect */ 2837 if (ena_auto_link_update) 2838 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2839 2840 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2841 if (status) { 2842 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2843 goto out; 2844 } 2845 2846 /* Update the link info 2847 * It sometimes takes a really long time for link to 2848 * come back from the atomic reset. Thus, we wait a 2849 * little bit. 2850 */ 2851 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2852 status = ice_update_link_info(pi); 2853 2854 if (!status) 2855 break; 2856 2857 mdelay(100); 2858 } 2859 2860 if (status) 2861 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2862 } 2863 2864 out: 2865 devm_kfree(ice_hw_to_dev(hw), pcaps); 2866 return status; 2867 } 2868 2869 /** 2870 * ice_phy_caps_equals_cfg 2871 * @phy_caps: PHY capabilities 2872 * @phy_cfg: PHY configuration 2873 * 2874 * Helper function to determine if PHY capabilities matches PHY 2875 * configuration 2876 */ 2877 bool 2878 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2879 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2880 { 2881 u8 caps_mask, cfg_mask; 2882 2883 if (!phy_caps || !phy_cfg) 2884 return false; 2885 2886 /* These bits are not common between capabilities and configuration. 2887 * Do not use them to determine equality. 2888 */ 2889 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2890 ICE_AQC_GET_PHY_EN_MOD_QUAL); 2891 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2892 2893 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2894 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2895 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2896 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 2897 phy_caps->eee_cap != phy_cfg->eee_cap || 2898 phy_caps->eeer_value != phy_cfg->eeer_value || 2899 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 2900 return false; 2901 2902 return true; 2903 } 2904 2905 /** 2906 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2907 * @pi: port information structure 2908 * @caps: PHY ability structure to copy date from 2909 * @cfg: PHY configuration structure to copy data to 2910 * 2911 * Helper function to copy AQC PHY get ability data to PHY set configuration 2912 * data structure 2913 */ 2914 void 2915 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2916 struct ice_aqc_get_phy_caps_data *caps, 2917 struct ice_aqc_set_phy_cfg_data *cfg) 2918 { 2919 if (!pi || !caps || !cfg) 2920 return; 2921 2922 memset(cfg, 0, sizeof(*cfg)); 2923 cfg->phy_type_low = caps->phy_type_low; 2924 cfg->phy_type_high = caps->phy_type_high; 2925 cfg->caps = caps->caps; 2926 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2927 cfg->eee_cap = caps->eee_cap; 2928 cfg->eeer_value = caps->eeer_value; 2929 cfg->link_fec_opt = caps->link_fec_options; 2930 cfg->module_compliance_enforcement = 2931 caps->module_compliance_enforcement; 2932 2933 if (ice_fw_supports_link_override(pi->hw)) { 2934 struct ice_link_default_override_tlv tlv; 2935 2936 if (ice_get_link_default_override(&tlv, pi)) 2937 return; 2938 2939 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2940 cfg->module_compliance_enforcement |= 2941 ICE_LINK_OVERRIDE_STRICT_MODE; 2942 } 2943 } 2944 2945 /** 2946 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2947 * @pi: port information structure 2948 * @cfg: PHY configuration data to set FEC mode 2949 * @fec: FEC mode to configure 2950 */ 2951 enum ice_status 2952 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2953 enum ice_fec_mode fec) 2954 { 2955 struct ice_aqc_get_phy_caps_data *pcaps; 2956 enum ice_status status; 2957 2958 if (!pi || !cfg) 2959 return ICE_ERR_BAD_PTR; 2960 2961 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 2962 if (!pcaps) 2963 return ICE_ERR_NO_MEMORY; 2964 2965 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 2966 NULL); 2967 if (status) 2968 goto out; 2969 2970 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 2971 cfg->link_fec_opt = pcaps->link_fec_options; 2972 2973 switch (fec) { 2974 case ICE_FEC_BASER: 2975 /* Clear RS bits, and AND BASE-R ability 2976 * bits and OR request bits. 2977 */ 2978 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2979 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2980 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2981 ICE_AQC_PHY_FEC_25G_KR_REQ; 2982 break; 2983 case ICE_FEC_RS: 2984 /* Clear BASE-R bits, and AND RS ability 2985 * bits and OR request bits. 2986 */ 2987 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2988 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2989 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2990 break; 2991 case ICE_FEC_NONE: 2992 /* Clear all FEC option bits. */ 2993 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2994 break; 2995 case ICE_FEC_AUTO: 2996 /* AND auto FEC bit, and all caps bits. */ 2997 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2998 cfg->link_fec_opt |= pcaps->link_fec_options; 2999 break; 3000 default: 3001 status = ICE_ERR_PARAM; 3002 break; 3003 } 3004 3005 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 3006 struct ice_link_default_override_tlv tlv; 3007 3008 if (ice_get_link_default_override(&tlv, pi)) 3009 goto out; 3010 3011 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3012 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3013 cfg->link_fec_opt = tlv.fec_options; 3014 } 3015 3016 out: 3017 kfree(pcaps); 3018 3019 return status; 3020 } 3021 3022 /** 3023 * ice_get_link_status - get status of the HW network link 3024 * @pi: port information structure 3025 * @link_up: pointer to bool (true/false = linkup/linkdown) 3026 * 3027 * Variable link_up is true if link is up, false if link is down. 3028 * The variable link_up is invalid if status is non zero. As a 3029 * result of this call, link status reporting becomes enabled 3030 */ 3031 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3032 { 3033 struct ice_phy_info *phy_info; 3034 enum ice_status status = 0; 3035 3036 if (!pi || !link_up) 3037 return ICE_ERR_PARAM; 3038 3039 phy_info = &pi->phy; 3040 3041 if (phy_info->get_link_info) { 3042 status = ice_update_link_info(pi); 3043 3044 if (status) 3045 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3046 status); 3047 } 3048 3049 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3050 3051 return status; 3052 } 3053 3054 /** 3055 * ice_aq_set_link_restart_an 3056 * @pi: pointer to the port information structure 3057 * @ena_link: if true: enable link, if false: disable link 3058 * @cd: pointer to command details structure or NULL 3059 * 3060 * Sets up the link and restarts the Auto-Negotiation over the link. 3061 */ 3062 enum ice_status 3063 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3064 struct ice_sq_cd *cd) 3065 { 3066 struct ice_aqc_restart_an *cmd; 3067 struct ice_aq_desc desc; 3068 3069 cmd = &desc.params.restart_an; 3070 3071 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3072 3073 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3074 cmd->lport_num = pi->lport; 3075 if (ena_link) 3076 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3077 else 3078 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3079 3080 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3081 } 3082 3083 /** 3084 * ice_aq_set_event_mask 3085 * @hw: pointer to the HW struct 3086 * @port_num: port number of the physical function 3087 * @mask: event mask to be set 3088 * @cd: pointer to command details structure or NULL 3089 * 3090 * Set event mask (0x0613) 3091 */ 3092 enum ice_status 3093 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3094 struct ice_sq_cd *cd) 3095 { 3096 struct ice_aqc_set_event_mask *cmd; 3097 struct ice_aq_desc desc; 3098 3099 cmd = &desc.params.set_event_mask; 3100 3101 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3102 3103 cmd->lport_num = port_num; 3104 3105 cmd->event_mask = cpu_to_le16(mask); 3106 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3107 } 3108 3109 /** 3110 * ice_aq_set_mac_loopback 3111 * @hw: pointer to the HW struct 3112 * @ena_lpbk: Enable or Disable loopback 3113 * @cd: pointer to command details structure or NULL 3114 * 3115 * Enable/disable loopback on a given port 3116 */ 3117 enum ice_status 3118 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3119 { 3120 struct ice_aqc_set_mac_lb *cmd; 3121 struct ice_aq_desc desc; 3122 3123 cmd = &desc.params.set_mac_lb; 3124 3125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3126 if (ena_lpbk) 3127 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3128 3129 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3130 } 3131 3132 /** 3133 * ice_aq_set_port_id_led 3134 * @pi: pointer to the port information 3135 * @is_orig_mode: is this LED set to original mode (by the net-list) 3136 * @cd: pointer to command details structure or NULL 3137 * 3138 * Set LED value for the given port (0x06e9) 3139 */ 3140 enum ice_status 3141 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3142 struct ice_sq_cd *cd) 3143 { 3144 struct ice_aqc_set_port_id_led *cmd; 3145 struct ice_hw *hw = pi->hw; 3146 struct ice_aq_desc desc; 3147 3148 cmd = &desc.params.set_port_id_led; 3149 3150 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3151 3152 if (is_orig_mode) 3153 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3154 else 3155 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3156 3157 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3158 } 3159 3160 /** 3161 * ice_aq_sff_eeprom 3162 * @hw: pointer to the HW struct 3163 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3164 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3165 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3166 * @page: QSFP page 3167 * @set_page: set or ignore the page 3168 * @data: pointer to data buffer to be read/written to the I2C device. 3169 * @length: 1-16 for read, 1 for write. 3170 * @write: 0 read, 1 for write. 3171 * @cd: pointer to command details structure or NULL 3172 * 3173 * Read/Write SFF EEPROM (0x06EE) 3174 */ 3175 enum ice_status 3176 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3177 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3178 bool write, struct ice_sq_cd *cd) 3179 { 3180 struct ice_aqc_sff_eeprom *cmd; 3181 struct ice_aq_desc desc; 3182 enum ice_status status; 3183 3184 if (!data || (mem_addr & 0xff00)) 3185 return ICE_ERR_PARAM; 3186 3187 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3188 cmd = &desc.params.read_write_sff_param; 3189 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3190 cmd->lport_num = (u8)(lport & 0xff); 3191 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3192 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3193 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3194 ((set_page << 3195 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3196 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3197 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3198 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3199 if (write) 3200 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3201 3202 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3203 return status; 3204 } 3205 3206 /** 3207 * __ice_aq_get_set_rss_lut 3208 * @hw: pointer to the hardware structure 3209 * @vsi_id: VSI FW index 3210 * @lut_type: LUT table type 3211 * @lut: pointer to the LUT buffer provided by the caller 3212 * @lut_size: size of the LUT buffer 3213 * @glob_lut_idx: global LUT index 3214 * @set: set true to set the table, false to get the table 3215 * 3216 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3217 */ 3218 static enum ice_status 3219 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3220 u16 lut_size, u8 glob_lut_idx, bool set) 3221 { 3222 struct ice_aqc_get_set_rss_lut *cmd_resp; 3223 struct ice_aq_desc desc; 3224 enum ice_status status; 3225 u16 flags = 0; 3226 3227 cmd_resp = &desc.params.get_set_rss_lut; 3228 3229 if (set) { 3230 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3231 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3232 } else { 3233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3234 } 3235 3236 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3237 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3238 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3239 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3240 3241 switch (lut_type) { 3242 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3243 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3244 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3245 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3246 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3247 break; 3248 default: 3249 status = ICE_ERR_PARAM; 3250 goto ice_aq_get_set_rss_lut_exit; 3251 } 3252 3253 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3254 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3255 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3256 3257 if (!set) 3258 goto ice_aq_get_set_rss_lut_send; 3259 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3260 if (!set) 3261 goto ice_aq_get_set_rss_lut_send; 3262 } else { 3263 goto ice_aq_get_set_rss_lut_send; 3264 } 3265 3266 /* LUT size is only valid for Global and PF table types */ 3267 switch (lut_size) { 3268 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3269 break; 3270 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3271 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3272 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3273 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3274 break; 3275 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3276 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3277 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3278 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3279 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3280 break; 3281 } 3282 fallthrough; 3283 default: 3284 status = ICE_ERR_PARAM; 3285 goto ice_aq_get_set_rss_lut_exit; 3286 } 3287 3288 ice_aq_get_set_rss_lut_send: 3289 cmd_resp->flags = cpu_to_le16(flags); 3290 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3291 3292 ice_aq_get_set_rss_lut_exit: 3293 return status; 3294 } 3295 3296 /** 3297 * ice_aq_get_rss_lut 3298 * @hw: pointer to the hardware structure 3299 * @vsi_handle: software VSI handle 3300 * @lut_type: LUT table type 3301 * @lut: pointer to the LUT buffer provided by the caller 3302 * @lut_size: size of the LUT buffer 3303 * 3304 * get the RSS lookup table, PF or VSI type 3305 */ 3306 enum ice_status 3307 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3308 u8 *lut, u16 lut_size) 3309 { 3310 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3311 return ICE_ERR_PARAM; 3312 3313 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3314 lut_type, lut, lut_size, 0, false); 3315 } 3316 3317 /** 3318 * ice_aq_set_rss_lut 3319 * @hw: pointer to the hardware structure 3320 * @vsi_handle: software VSI handle 3321 * @lut_type: LUT table type 3322 * @lut: pointer to the LUT buffer provided by the caller 3323 * @lut_size: size of the LUT buffer 3324 * 3325 * set the RSS lookup table, PF or VSI type 3326 */ 3327 enum ice_status 3328 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3329 u8 *lut, u16 lut_size) 3330 { 3331 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3332 return ICE_ERR_PARAM; 3333 3334 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3335 lut_type, lut, lut_size, 0, true); 3336 } 3337 3338 /** 3339 * __ice_aq_get_set_rss_key 3340 * @hw: pointer to the HW struct 3341 * @vsi_id: VSI FW index 3342 * @key: pointer to key info struct 3343 * @set: set true to set the key, false to get the key 3344 * 3345 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3346 */ 3347 static enum 3348 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3349 struct ice_aqc_get_set_rss_keys *key, 3350 bool set) 3351 { 3352 struct ice_aqc_get_set_rss_key *cmd_resp; 3353 u16 key_size = sizeof(*key); 3354 struct ice_aq_desc desc; 3355 3356 cmd_resp = &desc.params.get_set_rss_key; 3357 3358 if (set) { 3359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3360 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3361 } else { 3362 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3363 } 3364 3365 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3366 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3367 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3368 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3369 3370 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3371 } 3372 3373 /** 3374 * ice_aq_get_rss_key 3375 * @hw: pointer to the HW struct 3376 * @vsi_handle: software VSI handle 3377 * @key: pointer to key info struct 3378 * 3379 * get the RSS key per VSI 3380 */ 3381 enum ice_status 3382 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3383 struct ice_aqc_get_set_rss_keys *key) 3384 { 3385 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3386 return ICE_ERR_PARAM; 3387 3388 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3389 key, false); 3390 } 3391 3392 /** 3393 * ice_aq_set_rss_key 3394 * @hw: pointer to the HW struct 3395 * @vsi_handle: software VSI handle 3396 * @keys: pointer to key info struct 3397 * 3398 * set the RSS key per VSI 3399 */ 3400 enum ice_status 3401 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3402 struct ice_aqc_get_set_rss_keys *keys) 3403 { 3404 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3405 return ICE_ERR_PARAM; 3406 3407 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3408 keys, true); 3409 } 3410 3411 /** 3412 * ice_aq_add_lan_txq 3413 * @hw: pointer to the hardware structure 3414 * @num_qgrps: Number of added queue groups 3415 * @qg_list: list of queue groups to be added 3416 * @buf_size: size of buffer for indirect command 3417 * @cd: pointer to command details structure or NULL 3418 * 3419 * Add Tx LAN queue (0x0C30) 3420 * 3421 * NOTE: 3422 * Prior to calling add Tx LAN queue: 3423 * Initialize the following as part of the Tx queue context: 3424 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3425 * Cache profile and Packet shaper profile. 3426 * 3427 * After add Tx LAN queue AQ command is completed: 3428 * Interrupts should be associated with specific queues, 3429 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3430 * flow. 3431 */ 3432 static enum ice_status 3433 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3434 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3435 struct ice_sq_cd *cd) 3436 { 3437 struct ice_aqc_add_tx_qgrp *list; 3438 struct ice_aqc_add_txqs *cmd; 3439 struct ice_aq_desc desc; 3440 u16 i, sum_size = 0; 3441 3442 cmd = &desc.params.add_txqs; 3443 3444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3445 3446 if (!qg_list) 3447 return ICE_ERR_PARAM; 3448 3449 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3450 return ICE_ERR_PARAM; 3451 3452 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3453 sum_size += struct_size(list, txqs, list->num_txqs); 3454 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3455 list->num_txqs); 3456 } 3457 3458 if (buf_size != sum_size) 3459 return ICE_ERR_PARAM; 3460 3461 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3462 3463 cmd->num_qgrps = num_qgrps; 3464 3465 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3466 } 3467 3468 /** 3469 * ice_aq_dis_lan_txq 3470 * @hw: pointer to the hardware structure 3471 * @num_qgrps: number of groups in the list 3472 * @qg_list: the list of groups to disable 3473 * @buf_size: the total size of the qg_list buffer in bytes 3474 * @rst_src: if called due to reset, specifies the reset source 3475 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3476 * @cd: pointer to command details structure or NULL 3477 * 3478 * Disable LAN Tx queue (0x0C31) 3479 */ 3480 static enum ice_status 3481 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3482 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3483 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3484 struct ice_sq_cd *cd) 3485 { 3486 struct ice_aqc_dis_txq_item *item; 3487 struct ice_aqc_dis_txqs *cmd; 3488 struct ice_aq_desc desc; 3489 enum ice_status status; 3490 u16 i, sz = 0; 3491 3492 cmd = &desc.params.dis_txqs; 3493 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3494 3495 /* qg_list can be NULL only in VM/VF reset flow */ 3496 if (!qg_list && !rst_src) 3497 return ICE_ERR_PARAM; 3498 3499 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3500 return ICE_ERR_PARAM; 3501 3502 cmd->num_entries = num_qgrps; 3503 3504 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3505 ICE_AQC_Q_DIS_TIMEOUT_M); 3506 3507 switch (rst_src) { 3508 case ICE_VM_RESET: 3509 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3510 cmd->vmvf_and_timeout |= 3511 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3512 break; 3513 case ICE_VF_RESET: 3514 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3515 /* In this case, FW expects vmvf_num to be absolute VF ID */ 3516 cmd->vmvf_and_timeout |= 3517 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3518 ICE_AQC_Q_DIS_VMVF_NUM_M); 3519 break; 3520 case ICE_NO_RESET: 3521 default: 3522 break; 3523 } 3524 3525 /* flush pipe on time out */ 3526 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3527 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3528 if (!qg_list) 3529 goto do_aq; 3530 3531 /* set RD bit to indicate that command buffer is provided by the driver 3532 * and it needs to be read by the firmware 3533 */ 3534 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3535 3536 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3537 u16 item_size = struct_size(item, q_id, item->num_qs); 3538 3539 /* If the num of queues is even, add 2 bytes of padding */ 3540 if ((item->num_qs % 2) == 0) 3541 item_size += 2; 3542 3543 sz += item_size; 3544 3545 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3546 } 3547 3548 if (buf_size != sz) 3549 return ICE_ERR_PARAM; 3550 3551 do_aq: 3552 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3553 if (status) { 3554 if (!qg_list) 3555 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3556 vmvf_num, hw->adminq.sq_last_status); 3557 else 3558 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3559 le16_to_cpu(qg_list[0].q_id[0]), 3560 hw->adminq.sq_last_status); 3561 } 3562 return status; 3563 } 3564 3565 /* End of FW Admin Queue command wrappers */ 3566 3567 /** 3568 * ice_write_byte - write a byte to a packed context structure 3569 * @src_ctx: the context structure to read from 3570 * @dest_ctx: the context to be written to 3571 * @ce_info: a description of the struct to be filled 3572 */ 3573 static void 3574 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3575 { 3576 u8 src_byte, dest_byte, mask; 3577 u8 *from, *dest; 3578 u16 shift_width; 3579 3580 /* copy from the next struct field */ 3581 from = src_ctx + ce_info->offset; 3582 3583 /* prepare the bits and mask */ 3584 shift_width = ce_info->lsb % 8; 3585 mask = (u8)(BIT(ce_info->width) - 1); 3586 3587 src_byte = *from; 3588 src_byte &= mask; 3589 3590 /* shift to correct alignment */ 3591 mask <<= shift_width; 3592 src_byte <<= shift_width; 3593 3594 /* get the current bits from the target bit string */ 3595 dest = dest_ctx + (ce_info->lsb / 8); 3596 3597 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3598 3599 dest_byte &= ~mask; /* get the bits not changing */ 3600 dest_byte |= src_byte; /* add in the new bits */ 3601 3602 /* put it all back */ 3603 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3604 } 3605 3606 /** 3607 * ice_write_word - write a word to a packed context structure 3608 * @src_ctx: the context structure to read from 3609 * @dest_ctx: the context to be written to 3610 * @ce_info: a description of the struct to be filled 3611 */ 3612 static void 3613 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3614 { 3615 u16 src_word, mask; 3616 __le16 dest_word; 3617 u8 *from, *dest; 3618 u16 shift_width; 3619 3620 /* copy from the next struct field */ 3621 from = src_ctx + ce_info->offset; 3622 3623 /* prepare the bits and mask */ 3624 shift_width = ce_info->lsb % 8; 3625 mask = BIT(ce_info->width) - 1; 3626 3627 /* don't swizzle the bits until after the mask because the mask bits 3628 * will be in a different bit position on big endian machines 3629 */ 3630 src_word = *(u16 *)from; 3631 src_word &= mask; 3632 3633 /* shift to correct alignment */ 3634 mask <<= shift_width; 3635 src_word <<= shift_width; 3636 3637 /* get the current bits from the target bit string */ 3638 dest = dest_ctx + (ce_info->lsb / 8); 3639 3640 memcpy(&dest_word, dest, sizeof(dest_word)); 3641 3642 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3643 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3644 3645 /* put it all back */ 3646 memcpy(dest, &dest_word, sizeof(dest_word)); 3647 } 3648 3649 /** 3650 * ice_write_dword - write a dword to a packed context structure 3651 * @src_ctx: the context structure to read from 3652 * @dest_ctx: the context to be written to 3653 * @ce_info: a description of the struct to be filled 3654 */ 3655 static void 3656 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3657 { 3658 u32 src_dword, mask; 3659 __le32 dest_dword; 3660 u8 *from, *dest; 3661 u16 shift_width; 3662 3663 /* copy from the next struct field */ 3664 from = src_ctx + ce_info->offset; 3665 3666 /* prepare the bits and mask */ 3667 shift_width = ce_info->lsb % 8; 3668 3669 /* if the field width is exactly 32 on an x86 machine, then the shift 3670 * operation will not work because the SHL instructions count is masked 3671 * to 5 bits so the shift will do nothing 3672 */ 3673 if (ce_info->width < 32) 3674 mask = BIT(ce_info->width) - 1; 3675 else 3676 mask = (u32)~0; 3677 3678 /* don't swizzle the bits until after the mask because the mask bits 3679 * will be in a different bit position on big endian machines 3680 */ 3681 src_dword = *(u32 *)from; 3682 src_dword &= mask; 3683 3684 /* shift to correct alignment */ 3685 mask <<= shift_width; 3686 src_dword <<= shift_width; 3687 3688 /* get the current bits from the target bit string */ 3689 dest = dest_ctx + (ce_info->lsb / 8); 3690 3691 memcpy(&dest_dword, dest, sizeof(dest_dword)); 3692 3693 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3694 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3695 3696 /* put it all back */ 3697 memcpy(dest, &dest_dword, sizeof(dest_dword)); 3698 } 3699 3700 /** 3701 * ice_write_qword - write a qword to a packed context structure 3702 * @src_ctx: the context structure to read from 3703 * @dest_ctx: the context to be written to 3704 * @ce_info: a description of the struct to be filled 3705 */ 3706 static void 3707 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3708 { 3709 u64 src_qword, mask; 3710 __le64 dest_qword; 3711 u8 *from, *dest; 3712 u16 shift_width; 3713 3714 /* copy from the next struct field */ 3715 from = src_ctx + ce_info->offset; 3716 3717 /* prepare the bits and mask */ 3718 shift_width = ce_info->lsb % 8; 3719 3720 /* if the field width is exactly 64 on an x86 machine, then the shift 3721 * operation will not work because the SHL instructions count is masked 3722 * to 6 bits so the shift will do nothing 3723 */ 3724 if (ce_info->width < 64) 3725 mask = BIT_ULL(ce_info->width) - 1; 3726 else 3727 mask = (u64)~0; 3728 3729 /* don't swizzle the bits until after the mask because the mask bits 3730 * will be in a different bit position on big endian machines 3731 */ 3732 src_qword = *(u64 *)from; 3733 src_qword &= mask; 3734 3735 /* shift to correct alignment */ 3736 mask <<= shift_width; 3737 src_qword <<= shift_width; 3738 3739 /* get the current bits from the target bit string */ 3740 dest = dest_ctx + (ce_info->lsb / 8); 3741 3742 memcpy(&dest_qword, dest, sizeof(dest_qword)); 3743 3744 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3745 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3746 3747 /* put it all back */ 3748 memcpy(dest, &dest_qword, sizeof(dest_qword)); 3749 } 3750 3751 /** 3752 * ice_set_ctx - set context bits in packed structure 3753 * @hw: pointer to the hardware structure 3754 * @src_ctx: pointer to a generic non-packed context structure 3755 * @dest_ctx: pointer to memory for the packed structure 3756 * @ce_info: a description of the structure to be transformed 3757 */ 3758 enum ice_status 3759 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3760 const struct ice_ctx_ele *ce_info) 3761 { 3762 int f; 3763 3764 for (f = 0; ce_info[f].width; f++) { 3765 /* We have to deal with each element of the FW response 3766 * using the correct size so that we are correct regardless 3767 * of the endianness of the machine. 3768 */ 3769 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3770 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3771 f, ce_info[f].width, ce_info[f].size_of); 3772 continue; 3773 } 3774 switch (ce_info[f].size_of) { 3775 case sizeof(u8): 3776 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3777 break; 3778 case sizeof(u16): 3779 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3780 break; 3781 case sizeof(u32): 3782 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3783 break; 3784 case sizeof(u64): 3785 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3786 break; 3787 default: 3788 return ICE_ERR_INVAL_SIZE; 3789 } 3790 } 3791 3792 return 0; 3793 } 3794 3795 /** 3796 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3797 * @hw: pointer to the HW struct 3798 * @vsi_handle: software VSI handle 3799 * @tc: TC number 3800 * @q_handle: software queue handle 3801 */ 3802 struct ice_q_ctx * 3803 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3804 { 3805 struct ice_vsi_ctx *vsi; 3806 struct ice_q_ctx *q_ctx; 3807 3808 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3809 if (!vsi) 3810 return NULL; 3811 if (q_handle >= vsi->num_lan_q_entries[tc]) 3812 return NULL; 3813 if (!vsi->lan_q_ctx[tc]) 3814 return NULL; 3815 q_ctx = vsi->lan_q_ctx[tc]; 3816 return &q_ctx[q_handle]; 3817 } 3818 3819 /** 3820 * ice_ena_vsi_txq 3821 * @pi: port information structure 3822 * @vsi_handle: software VSI handle 3823 * @tc: TC number 3824 * @q_handle: software queue handle 3825 * @num_qgrps: Number of added queue groups 3826 * @buf: list of queue groups to be added 3827 * @buf_size: size of buffer for indirect command 3828 * @cd: pointer to command details structure or NULL 3829 * 3830 * This function adds one LAN queue 3831 */ 3832 enum ice_status 3833 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3834 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3835 struct ice_sq_cd *cd) 3836 { 3837 struct ice_aqc_txsched_elem_data node = { 0 }; 3838 struct ice_sched_node *parent; 3839 struct ice_q_ctx *q_ctx; 3840 enum ice_status status; 3841 struct ice_hw *hw; 3842 3843 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3844 return ICE_ERR_CFG; 3845 3846 if (num_qgrps > 1 || buf->num_txqs > 1) 3847 return ICE_ERR_MAX_LIMIT; 3848 3849 hw = pi->hw; 3850 3851 if (!ice_is_vsi_valid(hw, vsi_handle)) 3852 return ICE_ERR_PARAM; 3853 3854 mutex_lock(&pi->sched_lock); 3855 3856 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3857 if (!q_ctx) { 3858 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3859 q_handle); 3860 status = ICE_ERR_PARAM; 3861 goto ena_txq_exit; 3862 } 3863 3864 /* find a parent node */ 3865 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3866 ICE_SCHED_NODE_OWNER_LAN); 3867 if (!parent) { 3868 status = ICE_ERR_PARAM; 3869 goto ena_txq_exit; 3870 } 3871 3872 buf->parent_teid = parent->info.node_teid; 3873 node.parent_teid = parent->info.node_teid; 3874 /* Mark that the values in the "generic" section as valid. The default 3875 * value in the "generic" section is zero. This means that : 3876 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3877 * - 0 priority among siblings, indicated by Bit 1-3. 3878 * - WFQ, indicated by Bit 4. 3879 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3880 * Bit 5-6. 3881 * - Bit 7 is reserved. 3882 * Without setting the generic section as valid in valid_sections, the 3883 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3884 */ 3885 buf->txqs[0].info.valid_sections = 3886 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 3887 ICE_AQC_ELEM_VALID_EIR; 3888 buf->txqs[0].info.generic = 0; 3889 buf->txqs[0].info.cir_bw.bw_profile_idx = 3890 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3891 buf->txqs[0].info.cir_bw.bw_alloc = 3892 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3893 buf->txqs[0].info.eir_bw.bw_profile_idx = 3894 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3895 buf->txqs[0].info.eir_bw.bw_alloc = 3896 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3897 3898 /* add the LAN queue */ 3899 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3900 if (status) { 3901 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3902 le16_to_cpu(buf->txqs[0].txq_id), 3903 hw->adminq.sq_last_status); 3904 goto ena_txq_exit; 3905 } 3906 3907 node.node_teid = buf->txqs[0].q_teid; 3908 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3909 q_ctx->q_handle = q_handle; 3910 q_ctx->q_teid = le32_to_cpu(node.node_teid); 3911 3912 /* add a leaf node into scheduler tree queue layer */ 3913 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3914 if (!status) 3915 status = ice_sched_replay_q_bw(pi, q_ctx); 3916 3917 ena_txq_exit: 3918 mutex_unlock(&pi->sched_lock); 3919 return status; 3920 } 3921 3922 /** 3923 * ice_dis_vsi_txq 3924 * @pi: port information structure 3925 * @vsi_handle: software VSI handle 3926 * @tc: TC number 3927 * @num_queues: number of queues 3928 * @q_handles: pointer to software queue handle array 3929 * @q_ids: pointer to the q_id array 3930 * @q_teids: pointer to queue node teids 3931 * @rst_src: if called due to reset, specifies the reset source 3932 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3933 * @cd: pointer to command details structure or NULL 3934 * 3935 * This function removes queues and their corresponding nodes in SW DB 3936 */ 3937 enum ice_status 3938 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3939 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3940 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3941 struct ice_sq_cd *cd) 3942 { 3943 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3944 struct ice_aqc_dis_txq_item *qg_list; 3945 struct ice_q_ctx *q_ctx; 3946 struct ice_hw *hw; 3947 u16 i, buf_size; 3948 3949 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3950 return ICE_ERR_CFG; 3951 3952 hw = pi->hw; 3953 3954 if (!num_queues) { 3955 /* if queue is disabled already yet the disable queue command 3956 * has to be sent to complete the VF reset, then call 3957 * ice_aq_dis_lan_txq without any queue information 3958 */ 3959 if (rst_src) 3960 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 3961 vmvf_num, NULL); 3962 return ICE_ERR_CFG; 3963 } 3964 3965 buf_size = struct_size(qg_list, q_id, 1); 3966 qg_list = kzalloc(buf_size, GFP_KERNEL); 3967 if (!qg_list) 3968 return ICE_ERR_NO_MEMORY; 3969 3970 mutex_lock(&pi->sched_lock); 3971 3972 for (i = 0; i < num_queues; i++) { 3973 struct ice_sched_node *node; 3974 3975 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3976 if (!node) 3977 continue; 3978 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 3979 if (!q_ctx) { 3980 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3981 q_handles[i]); 3982 continue; 3983 } 3984 if (q_ctx->q_handle != q_handles[i]) { 3985 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3986 q_ctx->q_handle, q_handles[i]); 3987 continue; 3988 } 3989 qg_list->parent_teid = node->info.parent_teid; 3990 qg_list->num_qs = 1; 3991 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 3992 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 3993 vmvf_num, cd); 3994 3995 if (status) 3996 break; 3997 ice_free_sched_node(pi, node); 3998 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3999 } 4000 mutex_unlock(&pi->sched_lock); 4001 kfree(qg_list); 4002 return status; 4003 } 4004 4005 /** 4006 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4007 * @pi: port information structure 4008 * @vsi_handle: software VSI handle 4009 * @tc_bitmap: TC bitmap 4010 * @maxqs: max queues array per TC 4011 * @owner: LAN or RDMA 4012 * 4013 * This function adds/updates the VSI queues per TC. 4014 */ 4015 static enum ice_status 4016 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4017 u16 *maxqs, u8 owner) 4018 { 4019 enum ice_status status = 0; 4020 u8 i; 4021 4022 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4023 return ICE_ERR_CFG; 4024 4025 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4026 return ICE_ERR_PARAM; 4027 4028 mutex_lock(&pi->sched_lock); 4029 4030 ice_for_each_traffic_class(i) { 4031 /* configuration is possible only if TC node is present */ 4032 if (!ice_sched_get_tc_node(pi, i)) 4033 continue; 4034 4035 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4036 ice_is_tc_ena(tc_bitmap, i)); 4037 if (status) 4038 break; 4039 } 4040 4041 mutex_unlock(&pi->sched_lock); 4042 return status; 4043 } 4044 4045 /** 4046 * ice_cfg_vsi_lan - configure VSI LAN queues 4047 * @pi: port information structure 4048 * @vsi_handle: software VSI handle 4049 * @tc_bitmap: TC bitmap 4050 * @max_lanqs: max LAN queues array per TC 4051 * 4052 * This function adds/updates the VSI LAN queues per TC. 4053 */ 4054 enum ice_status 4055 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4056 u16 *max_lanqs) 4057 { 4058 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4059 ICE_SCHED_NODE_OWNER_LAN); 4060 } 4061 4062 /** 4063 * ice_replay_pre_init - replay pre initialization 4064 * @hw: pointer to the HW struct 4065 * 4066 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4067 */ 4068 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4069 { 4070 struct ice_switch_info *sw = hw->switch_info; 4071 u8 i; 4072 4073 /* Delete old entries from replay filter list head if there is any */ 4074 ice_rm_all_sw_replay_rule_info(hw); 4075 /* In start of replay, move entries into replay_rules list, it 4076 * will allow adding rules entries back to filt_rules list, 4077 * which is operational list. 4078 */ 4079 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4080 list_replace_init(&sw->recp_list[i].filt_rules, 4081 &sw->recp_list[i].filt_replay_rules); 4082 ice_sched_replay_agg_vsi_preinit(hw); 4083 4084 return 0; 4085 } 4086 4087 /** 4088 * ice_replay_vsi - replay VSI configuration 4089 * @hw: pointer to the HW struct 4090 * @vsi_handle: driver VSI handle 4091 * 4092 * Restore all VSI configuration after reset. It is required to call this 4093 * function with main VSI first. 4094 */ 4095 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4096 { 4097 enum ice_status status; 4098 4099 if (!ice_is_vsi_valid(hw, vsi_handle)) 4100 return ICE_ERR_PARAM; 4101 4102 /* Replay pre-initialization if there is any */ 4103 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4104 status = ice_replay_pre_init(hw); 4105 if (status) 4106 return status; 4107 } 4108 /* Replay per VSI all RSS configurations */ 4109 status = ice_replay_rss_cfg(hw, vsi_handle); 4110 if (status) 4111 return status; 4112 /* Replay per VSI all filters */ 4113 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4114 if (!status) 4115 status = ice_replay_vsi_agg(hw, vsi_handle); 4116 return status; 4117 } 4118 4119 /** 4120 * ice_replay_post - post replay configuration cleanup 4121 * @hw: pointer to the HW struct 4122 * 4123 * Post replay cleanup. 4124 */ 4125 void ice_replay_post(struct ice_hw *hw) 4126 { 4127 /* Delete old entries from replay filter list head */ 4128 ice_rm_all_sw_replay_rule_info(hw); 4129 ice_sched_replay_agg(hw); 4130 } 4131 4132 /** 4133 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4134 * @hw: ptr to the hardware info 4135 * @reg: offset of 64 bit HW register to read from 4136 * @prev_stat_loaded: bool to specify if previous stats are loaded 4137 * @prev_stat: ptr to previous loaded stat value 4138 * @cur_stat: ptr to current stat value 4139 */ 4140 void 4141 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4142 u64 *prev_stat, u64 *cur_stat) 4143 { 4144 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4145 4146 /* device stats are not reset at PFR, they likely will not be zeroed 4147 * when the driver starts. Thus, save the value from the first read 4148 * without adding to the statistic value so that we report stats which 4149 * count up from zero. 4150 */ 4151 if (!prev_stat_loaded) { 4152 *prev_stat = new_data; 4153 return; 4154 } 4155 4156 /* Calculate the difference between the new and old values, and then 4157 * add it to the software stat value. 4158 */ 4159 if (new_data >= *prev_stat) 4160 *cur_stat += new_data - *prev_stat; 4161 else 4162 /* to manage the potential roll-over */ 4163 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4164 4165 /* Update the previously stored value to prepare for next read */ 4166 *prev_stat = new_data; 4167 } 4168 4169 /** 4170 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4171 * @hw: ptr to the hardware info 4172 * @reg: offset of HW register to read from 4173 * @prev_stat_loaded: bool to specify if previous stats are loaded 4174 * @prev_stat: ptr to previous loaded stat value 4175 * @cur_stat: ptr to current stat value 4176 */ 4177 void 4178 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4179 u64 *prev_stat, u64 *cur_stat) 4180 { 4181 u32 new_data; 4182 4183 new_data = rd32(hw, reg); 4184 4185 /* device stats are not reset at PFR, they likely will not be zeroed 4186 * when the driver starts. Thus, save the value from the first read 4187 * without adding to the statistic value so that we report stats which 4188 * count up from zero. 4189 */ 4190 if (!prev_stat_loaded) { 4191 *prev_stat = new_data; 4192 return; 4193 } 4194 4195 /* Calculate the difference between the new and old values, and then 4196 * add it to the software stat value. 4197 */ 4198 if (new_data >= *prev_stat) 4199 *cur_stat += new_data - *prev_stat; 4200 else 4201 /* to manage the potential roll-over */ 4202 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4203 4204 /* Update the previously stored value to prepare for next read */ 4205 *prev_stat = new_data; 4206 } 4207 4208 /** 4209 * ice_sched_query_elem - query element information from HW 4210 * @hw: pointer to the HW struct 4211 * @node_teid: node TEID to be queried 4212 * @buf: buffer to element information 4213 * 4214 * This function queries HW element information 4215 */ 4216 enum ice_status 4217 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4218 struct ice_aqc_txsched_elem_data *buf) 4219 { 4220 u16 buf_size, num_elem_ret = 0; 4221 enum ice_status status; 4222 4223 buf_size = sizeof(*buf); 4224 memset(buf, 0, buf_size); 4225 buf->node_teid = cpu_to_le32(node_teid); 4226 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4227 NULL); 4228 if (status || num_elem_ret != 1) 4229 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4230 return status; 4231 } 4232 4233 /** 4234 * ice_fw_supports_link_override 4235 * @hw: pointer to the hardware structure 4236 * 4237 * Checks if the firmware supports link override 4238 */ 4239 bool ice_fw_supports_link_override(struct ice_hw *hw) 4240 { 4241 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4242 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4243 return true; 4244 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4245 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4246 return true; 4247 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4248 return true; 4249 } 4250 4251 return false; 4252 } 4253 4254 /** 4255 * ice_get_link_default_override 4256 * @ldo: pointer to the link default override struct 4257 * @pi: pointer to the port info struct 4258 * 4259 * Gets the link default override for a port 4260 */ 4261 enum ice_status 4262 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4263 struct ice_port_info *pi) 4264 { 4265 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4266 struct ice_hw *hw = pi->hw; 4267 enum ice_status status; 4268 4269 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4270 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4271 if (status) { 4272 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4273 return status; 4274 } 4275 4276 /* Each port has its own config; calculate for our port */ 4277 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4278 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4279 4280 /* link options first */ 4281 status = ice_read_sr_word(hw, tlv_start, &buf); 4282 if (status) { 4283 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4284 return status; 4285 } 4286 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4287 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4288 ICE_LINK_OVERRIDE_PHY_CFG_S; 4289 4290 /* link PHY config */ 4291 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4292 status = ice_read_sr_word(hw, offset, &buf); 4293 if (status) { 4294 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4295 return status; 4296 } 4297 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4298 4299 /* PHY types low */ 4300 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4301 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4302 status = ice_read_sr_word(hw, (offset + i), &buf); 4303 if (status) { 4304 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4305 return status; 4306 } 4307 /* shift 16 bits at a time to fill 64 bits */ 4308 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4309 } 4310 4311 /* PHY types high */ 4312 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4313 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4314 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4315 status = ice_read_sr_word(hw, (offset + i), &buf); 4316 if (status) { 4317 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4318 return status; 4319 } 4320 /* shift 16 bits at a time to fill 64 bits */ 4321 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4322 } 4323 4324 return status; 4325 } 4326 4327 /** 4328 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4329 * @caps: get PHY capability data 4330 */ 4331 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4332 { 4333 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4334 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4335 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4336 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4337 return true; 4338 4339 return false; 4340 } 4341 4342 /** 4343 * ice_aq_set_lldp_mib - Set the LLDP MIB 4344 * @hw: pointer to the HW struct 4345 * @mib_type: Local, Remote or both Local and Remote MIBs 4346 * @buf: pointer to the caller-supplied buffer to store the MIB block 4347 * @buf_size: size of the buffer (in bytes) 4348 * @cd: pointer to command details structure or NULL 4349 * 4350 * Set the LLDP MIB. (0x0A08) 4351 */ 4352 enum ice_status 4353 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4354 struct ice_sq_cd *cd) 4355 { 4356 struct ice_aqc_lldp_set_local_mib *cmd; 4357 struct ice_aq_desc desc; 4358 4359 cmd = &desc.params.lldp_set_mib; 4360 4361 if (buf_size == 0 || !buf) 4362 return ICE_ERR_PARAM; 4363 4364 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4365 4366 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 4367 desc.datalen = cpu_to_le16(buf_size); 4368 4369 cmd->type = mib_type; 4370 cmd->length = cpu_to_le16(buf_size); 4371 4372 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4373 } 4374 4375 /** 4376 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 4377 * @hw: pointer to HW struct 4378 */ 4379 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4380 { 4381 if (hw->mac_type != ICE_MAC_E810) 4382 return false; 4383 4384 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4385 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4386 return true; 4387 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4388 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4389 return true; 4390 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4391 return true; 4392 } 4393 return false; 4394 } 4395 4396 /** 4397 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4398 * @hw: pointer to HW struct 4399 * @vsi_num: absolute HW index for VSI 4400 * @add: boolean for if adding or removing a filter 4401 */ 4402 enum ice_status 4403 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4404 { 4405 struct ice_aqc_lldp_filter_ctrl *cmd; 4406 struct ice_aq_desc desc; 4407 4408 cmd = &desc.params.lldp_filter_ctrl; 4409 4410 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4411 4412 if (add) 4413 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4414 else 4415 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4416 4417 cmd->vsi_num = cpu_to_le16(vsi_num); 4418 4419 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4420 } 4421