1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 hw->mac_type = ICE_MAC_E830; 175 break; 176 default: 177 hw->mac_type = ICE_MAC_UNKNOWN; 178 break; 179 } 180 181 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 182 return 0; 183 } 184 185 /** 186 * ice_is_generic_mac - check if device's mac_type is generic 187 * @hw: pointer to the hardware structure 188 * 189 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 190 */ 191 bool ice_is_generic_mac(struct ice_hw *hw) 192 { 193 return (hw->mac_type == ICE_MAC_GENERIC || 194 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 195 } 196 197 /** 198 * ice_is_pf_c827 - check if pf contains c827 phy 199 * @hw: pointer to the hw struct 200 * 201 * Return: true if the device has c827 phy. 202 */ 203 static bool ice_is_pf_c827(struct ice_hw *hw) 204 { 205 struct ice_aqc_get_link_topo cmd = {}; 206 u8 node_part_number; 207 u16 node_handle; 208 int status; 209 210 if (hw->mac_type != ICE_MAC_E810) 211 return false; 212 213 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 214 return true; 215 216 cmd.addr.topo_params.node_type_ctx = 217 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 218 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 219 cmd.addr.topo_params.index = 0; 220 221 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 222 &node_handle); 223 224 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 225 return false; 226 227 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 228 return true; 229 230 return false; 231 } 232 233 /** 234 * ice_clear_pf_cfg - Clear PF configuration 235 * @hw: pointer to the hardware structure 236 * 237 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 238 * configuration, flow director filters, etc.). 239 */ 240 int ice_clear_pf_cfg(struct ice_hw *hw) 241 { 242 struct ice_aq_desc desc; 243 244 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 245 246 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 247 } 248 249 /** 250 * ice_aq_manage_mac_read - manage MAC address read command 251 * @hw: pointer to the HW struct 252 * @buf: a virtual buffer to hold the manage MAC read response 253 * @buf_size: Size of the virtual buffer 254 * @cd: pointer to command details structure or NULL 255 * 256 * This function is used to return per PF station MAC address (0x0107). 257 * NOTE: Upon successful completion of this command, MAC address information 258 * is returned in user specified buffer. Please interpret user specified 259 * buffer as "manage_mac_read" response. 260 * Response such as various MAC addresses are stored in HW struct (port.mac) 261 * ice_discover_dev_caps is expected to be called before this function is 262 * called. 263 */ 264 static int 265 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 266 struct ice_sq_cd *cd) 267 { 268 struct ice_aqc_manage_mac_read_resp *resp; 269 struct ice_aqc_manage_mac_read *cmd; 270 struct ice_aq_desc desc; 271 int status; 272 u16 flags; 273 u8 i; 274 275 cmd = &desc.params.mac_read; 276 277 if (buf_size < sizeof(*resp)) 278 return -EINVAL; 279 280 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 281 282 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 283 if (status) 284 return status; 285 286 resp = buf; 287 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 288 289 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 290 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 291 return -EIO; 292 } 293 294 /* A single port can report up to two (LAN and WoL) addresses */ 295 for (i = 0; i < cmd->num_addr; i++) 296 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 297 ether_addr_copy(hw->port_info->mac.lan_addr, 298 resp[i].mac_addr); 299 ether_addr_copy(hw->port_info->mac.perm_addr, 300 resp[i].mac_addr); 301 break; 302 } 303 304 return 0; 305 } 306 307 /** 308 * ice_aq_get_phy_caps - returns PHY capabilities 309 * @pi: port information structure 310 * @qual_mods: report qualified modules 311 * @report_mode: report mode capabilities 312 * @pcaps: structure for PHY capabilities to be filled 313 * @cd: pointer to command details structure or NULL 314 * 315 * Returns the various PHY capabilities supported on the Port (0x0600) 316 */ 317 int 318 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 319 struct ice_aqc_get_phy_caps_data *pcaps, 320 struct ice_sq_cd *cd) 321 { 322 struct ice_aqc_get_phy_caps *cmd; 323 u16 pcaps_size = sizeof(*pcaps); 324 struct ice_aq_desc desc; 325 const char *prefix; 326 struct ice_hw *hw; 327 int status; 328 329 cmd = &desc.params.get_phy; 330 331 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 332 return -EINVAL; 333 hw = pi->hw; 334 335 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 336 !ice_fw_supports_report_dflt_cfg(hw)) 337 return -EINVAL; 338 339 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 340 341 if (qual_mods) 342 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 343 344 cmd->param0 |= cpu_to_le16(report_mode); 345 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 346 347 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 348 349 switch (report_mode) { 350 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 351 prefix = "phy_caps_media"; 352 break; 353 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 354 prefix = "phy_caps_no_media"; 355 break; 356 case ICE_AQC_REPORT_ACTIVE_CFG: 357 prefix = "phy_caps_active"; 358 break; 359 case ICE_AQC_REPORT_DFLT_CFG: 360 prefix = "phy_caps_default"; 361 break; 362 default: 363 prefix = "phy_caps_invalid"; 364 } 365 366 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 367 le64_to_cpu(pcaps->phy_type_high), prefix); 368 369 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 370 prefix, report_mode); 371 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 372 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 373 pcaps->low_power_ctrl_an); 374 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 375 pcaps->eee_cap); 376 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 377 pcaps->eeer_value); 378 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 379 pcaps->link_fec_options); 380 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 381 prefix, pcaps->module_compliance_enforcement); 382 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 383 prefix, pcaps->extended_compliance_code); 384 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 385 pcaps->module_type[0]); 386 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 387 pcaps->module_type[1]); 388 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 389 pcaps->module_type[2]); 390 391 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 392 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 393 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 394 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 395 sizeof(pi->phy.link_info.module_type)); 396 } 397 398 return status; 399 } 400 401 /** 402 * ice_aq_get_link_topo_handle - get link topology node return status 403 * @pi: port information structure 404 * @node_type: requested node type 405 * @cd: pointer to command details structure or NULL 406 * 407 * Get link topology node return status for specified node type (0x06E0) 408 * 409 * Node type cage can be used to determine if cage is present. If AQC 410 * returns error (ENOENT), then no cage present. If no cage present, then 411 * connection type is backplane or BASE-T. 412 */ 413 static int 414 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 415 struct ice_sq_cd *cd) 416 { 417 struct ice_aqc_get_link_topo *cmd; 418 struct ice_aq_desc desc; 419 420 cmd = &desc.params.get_link_topo; 421 422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 423 424 cmd->addr.topo_params.node_type_ctx = 425 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 426 ICE_AQC_LINK_TOPO_NODE_CTX_S); 427 428 /* set node type */ 429 cmd->addr.topo_params.node_type_ctx |= 430 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 431 432 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 433 } 434 435 /** 436 * ice_aq_get_netlist_node 437 * @hw: pointer to the hw struct 438 * @cmd: get_link_topo AQ structure 439 * @node_part_number: output node part number if node found 440 * @node_handle: output node handle parameter if node found 441 * 442 * Get netlist node handle. 443 */ 444 int 445 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 446 u8 *node_part_number, u16 *node_handle) 447 { 448 struct ice_aq_desc desc; 449 450 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 451 desc.params.get_link_topo = *cmd; 452 453 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 454 return -EINTR; 455 456 if (node_handle) 457 *node_handle = 458 le16_to_cpu(desc.params.get_link_topo.addr.handle); 459 if (node_part_number) 460 *node_part_number = desc.params.get_link_topo.node_part_num; 461 462 return 0; 463 } 464 465 /** 466 * ice_find_netlist_node 467 * @hw: pointer to the hw struct 468 * @node_type: type of netlist node to look for 469 * @ctx: context of the search 470 * @node_part_number: node part number to look for 471 * @node_handle: output parameter if node found - optional 472 * 473 * Scan the netlist for a node handle of the given node type and part number. 474 * 475 * If node_handle is non-NULL it will be modified on function exit. It is only 476 * valid if the function returns zero, and should be ignored on any non-zero 477 * return value. 478 * 479 * Return: 480 * * 0 if the node is found, 481 * * -ENOENT if no handle was found, 482 * * negative error code on failure to access the AQ. 483 */ 484 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 485 u8 node_part_number, u16 *node_handle) 486 { 487 u8 idx; 488 489 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 490 struct ice_aqc_get_link_topo cmd = {}; 491 u8 rec_node_part_number; 492 int status; 493 494 cmd.addr.topo_params.node_type_ctx = 495 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 496 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 497 cmd.addr.topo_params.index = idx; 498 499 status = ice_aq_get_netlist_node(hw, &cmd, 500 &rec_node_part_number, 501 node_handle); 502 if (status) 503 return status; 504 505 if (rec_node_part_number == node_part_number) 506 return 0; 507 } 508 509 return -ENOENT; 510 } 511 512 /** 513 * ice_is_media_cage_present 514 * @pi: port information structure 515 * 516 * Returns true if media cage is present, else false. If no cage, then 517 * media type is backplane or BASE-T. 518 */ 519 static bool ice_is_media_cage_present(struct ice_port_info *pi) 520 { 521 /* Node type cage can be used to determine if cage is present. If AQC 522 * returns error (ENOENT), then no cage present. If no cage present then 523 * connection type is backplane or BASE-T. 524 */ 525 return !ice_aq_get_link_topo_handle(pi, 526 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 527 NULL); 528 } 529 530 /** 531 * ice_get_media_type - Gets media type 532 * @pi: port information structure 533 */ 534 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 535 { 536 struct ice_link_status *hw_link_info; 537 538 if (!pi) 539 return ICE_MEDIA_UNKNOWN; 540 541 hw_link_info = &pi->phy.link_info; 542 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 543 /* If more than one media type is selected, report unknown */ 544 return ICE_MEDIA_UNKNOWN; 545 546 if (hw_link_info->phy_type_low) { 547 /* 1G SGMII is a special case where some DA cable PHYs 548 * may show this as an option when it really shouldn't 549 * be since SGMII is meant to be between a MAC and a PHY 550 * in a backplane. Try to detect this case and handle it 551 */ 552 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 553 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 554 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 555 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 556 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 557 return ICE_MEDIA_DA; 558 559 switch (hw_link_info->phy_type_low) { 560 case ICE_PHY_TYPE_LOW_1000BASE_SX: 561 case ICE_PHY_TYPE_LOW_1000BASE_LX: 562 case ICE_PHY_TYPE_LOW_10GBASE_SR: 563 case ICE_PHY_TYPE_LOW_10GBASE_LR: 564 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 565 case ICE_PHY_TYPE_LOW_25GBASE_SR: 566 case ICE_PHY_TYPE_LOW_25GBASE_LR: 567 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 568 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 569 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 570 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 571 case ICE_PHY_TYPE_LOW_50GBASE_SR: 572 case ICE_PHY_TYPE_LOW_50GBASE_FR: 573 case ICE_PHY_TYPE_LOW_50GBASE_LR: 574 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 575 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 577 case ICE_PHY_TYPE_LOW_100GBASE_DR: 578 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 579 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 582 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 583 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 584 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 585 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 586 return ICE_MEDIA_FIBER; 587 case ICE_PHY_TYPE_LOW_100BASE_TX: 588 case ICE_PHY_TYPE_LOW_1000BASE_T: 589 case ICE_PHY_TYPE_LOW_2500BASE_T: 590 case ICE_PHY_TYPE_LOW_5GBASE_T: 591 case ICE_PHY_TYPE_LOW_10GBASE_T: 592 case ICE_PHY_TYPE_LOW_25GBASE_T: 593 return ICE_MEDIA_BASET; 594 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 595 case ICE_PHY_TYPE_LOW_25GBASE_CR: 596 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 597 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 598 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 599 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 600 case ICE_PHY_TYPE_LOW_50GBASE_CP: 601 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 602 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 603 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 604 return ICE_MEDIA_DA; 605 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 606 case ICE_PHY_TYPE_LOW_40G_XLAUI: 607 case ICE_PHY_TYPE_LOW_50G_LAUI2: 608 case ICE_PHY_TYPE_LOW_50G_AUI2: 609 case ICE_PHY_TYPE_LOW_50G_AUI1: 610 case ICE_PHY_TYPE_LOW_100G_AUI4: 611 case ICE_PHY_TYPE_LOW_100G_CAUI4: 612 if (ice_is_media_cage_present(pi)) 613 return ICE_MEDIA_DA; 614 fallthrough; 615 case ICE_PHY_TYPE_LOW_1000BASE_KX: 616 case ICE_PHY_TYPE_LOW_2500BASE_KX: 617 case ICE_PHY_TYPE_LOW_2500BASE_X: 618 case ICE_PHY_TYPE_LOW_5GBASE_KR: 619 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 620 case ICE_PHY_TYPE_LOW_25GBASE_KR: 621 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 622 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 623 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 624 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 625 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 626 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 627 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 628 return ICE_MEDIA_BACKPLANE; 629 } 630 } else { 631 switch (hw_link_info->phy_type_high) { 632 case ICE_PHY_TYPE_HIGH_100G_AUI2: 633 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 634 if (ice_is_media_cage_present(pi)) 635 return ICE_MEDIA_DA; 636 fallthrough; 637 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 640 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 641 return ICE_MEDIA_FIBER; 642 } 643 } 644 return ICE_MEDIA_UNKNOWN; 645 } 646 647 /** 648 * ice_get_link_status_datalen 649 * @hw: pointer to the HW struct 650 * 651 * Returns datalength for the Get Link Status AQ command, which is bigger for 652 * newer adapter families handled by ice driver. 653 */ 654 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 655 { 656 switch (hw->mac_type) { 657 case ICE_MAC_E830: 658 return ICE_AQC_LS_DATA_SIZE_V2; 659 case ICE_MAC_E810: 660 default: 661 return ICE_AQC_LS_DATA_SIZE_V1; 662 } 663 } 664 665 /** 666 * ice_aq_get_link_info 667 * @pi: port information structure 668 * @ena_lse: enable/disable LinkStatusEvent reporting 669 * @link: pointer to link status structure - optional 670 * @cd: pointer to command details structure or NULL 671 * 672 * Get Link Status (0x607). Returns the link status of the adapter. 673 */ 674 int 675 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 676 struct ice_link_status *link, struct ice_sq_cd *cd) 677 { 678 struct ice_aqc_get_link_status_data link_data = { 0 }; 679 struct ice_aqc_get_link_status *resp; 680 struct ice_link_status *li_old, *li; 681 enum ice_media_type *hw_media_type; 682 struct ice_fc_info *hw_fc_info; 683 bool tx_pause, rx_pause; 684 struct ice_aq_desc desc; 685 struct ice_hw *hw; 686 u16 cmd_flags; 687 int status; 688 689 if (!pi) 690 return -EINVAL; 691 hw = pi->hw; 692 li_old = &pi->phy.link_info_old; 693 hw_media_type = &pi->phy.media_type; 694 li = &pi->phy.link_info; 695 hw_fc_info = &pi->fc; 696 697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 698 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 699 resp = &desc.params.get_link_status; 700 resp->cmd_flags = cpu_to_le16(cmd_flags); 701 resp->lport_num = pi->lport; 702 703 status = ice_aq_send_cmd(hw, &desc, &link_data, 704 ice_get_link_status_datalen(hw), cd); 705 if (status) 706 return status; 707 708 /* save off old link status information */ 709 *li_old = *li; 710 711 /* update current link status information */ 712 li->link_speed = le16_to_cpu(link_data.link_speed); 713 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 714 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 715 *hw_media_type = ice_get_media_type(pi); 716 li->link_info = link_data.link_info; 717 li->link_cfg_err = link_data.link_cfg_err; 718 li->an_info = link_data.an_info; 719 li->ext_info = link_data.ext_info; 720 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 721 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 722 li->topo_media_conflict = link_data.topo_media_conflict; 723 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 724 ICE_AQ_CFG_PACING_TYPE_M); 725 726 /* update fc info */ 727 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 728 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 729 if (tx_pause && rx_pause) 730 hw_fc_info->current_mode = ICE_FC_FULL; 731 else if (tx_pause) 732 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 733 else if (rx_pause) 734 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 735 else 736 hw_fc_info->current_mode = ICE_FC_NONE; 737 738 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 739 740 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 741 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 742 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 743 (unsigned long long)li->phy_type_low); 744 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 745 (unsigned long long)li->phy_type_high); 746 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 747 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 748 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 749 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 750 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 751 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 752 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 753 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 754 li->max_frame_size); 755 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 756 757 /* save link status information */ 758 if (link) 759 *link = *li; 760 761 /* flag cleared so calling functions don't call AQ again */ 762 pi->phy.get_link_info = false; 763 764 return 0; 765 } 766 767 /** 768 * ice_fill_tx_timer_and_fc_thresh 769 * @hw: pointer to the HW struct 770 * @cmd: pointer to MAC cfg structure 771 * 772 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 773 * descriptor 774 */ 775 static void 776 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 777 struct ice_aqc_set_mac_cfg *cmd) 778 { 779 u32 val, fc_thres_m; 780 781 /* We read back the transmit timer and FC threshold value of 782 * LFC. Thus, we will use index = 783 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 784 * 785 * Also, because we are operating on transmit timer and FC 786 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 787 */ 788 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 789 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 790 791 if (hw->mac_type == ICE_MAC_E830) { 792 /* Retrieve the transmit timer */ 793 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 794 cmd->tx_tmr_value = 795 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 796 797 /* Retrieve the fc threshold */ 798 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 799 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 800 } else { 801 /* Retrieve the transmit timer */ 802 val = rd32(hw, 803 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, 806 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 807 808 /* Retrieve the fc threshold */ 809 val = rd32(hw, 810 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 811 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 812 } 813 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 814 } 815 816 /** 817 * ice_aq_set_mac_cfg 818 * @hw: pointer to the HW struct 819 * @max_frame_size: Maximum Frame Size to be supported 820 * @cd: pointer to command details structure or NULL 821 * 822 * Set MAC configuration (0x0603) 823 */ 824 int 825 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 826 { 827 struct ice_aqc_set_mac_cfg *cmd; 828 struct ice_aq_desc desc; 829 830 cmd = &desc.params.set_mac_cfg; 831 832 if (max_frame_size == 0) 833 return -EINVAL; 834 835 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 836 837 cmd->max_frame_size = cpu_to_le16(max_frame_size); 838 839 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 840 841 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 842 } 843 844 /** 845 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 846 * @hw: pointer to the HW struct 847 */ 848 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 849 { 850 struct ice_switch_info *sw; 851 int status; 852 853 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 854 sizeof(*hw->switch_info), GFP_KERNEL); 855 sw = hw->switch_info; 856 857 if (!sw) 858 return -ENOMEM; 859 860 INIT_LIST_HEAD(&sw->vsi_list_map_head); 861 sw->prof_res_bm_init = 0; 862 863 /* Initialize recipe count with default recipes read from NVM */ 864 sw->recp_cnt = ICE_SW_LKUP_LAST; 865 866 status = ice_init_def_sw_recp(hw); 867 if (status) { 868 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 869 return status; 870 } 871 return 0; 872 } 873 874 /** 875 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 876 * @hw: pointer to the HW struct 877 */ 878 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 879 { 880 struct ice_switch_info *sw = hw->switch_info; 881 struct ice_vsi_list_map_info *v_pos_map; 882 struct ice_vsi_list_map_info *v_tmp_map; 883 struct ice_sw_recipe *recps; 884 u8 i; 885 886 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 887 list_entry) { 888 list_del(&v_pos_map->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 890 } 891 recps = sw->recp_list; 892 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 893 recps[i].root_rid = i; 894 895 if (recps[i].adv_rule) { 896 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 897 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 898 899 mutex_destroy(&recps[i].filt_rule_lock); 900 list_for_each_entry_safe(lst_itr, tmp_entry, 901 &recps[i].filt_rules, 902 list_entry) { 903 list_del(&lst_itr->list_entry); 904 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 905 devm_kfree(ice_hw_to_dev(hw), lst_itr); 906 } 907 } else { 908 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 909 910 mutex_destroy(&recps[i].filt_rule_lock); 911 list_for_each_entry_safe(lst_itr, tmp_entry, 912 &recps[i].filt_rules, 913 list_entry) { 914 list_del(&lst_itr->list_entry); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } 918 } 919 ice_rm_all_sw_replay_rule_info(hw); 920 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 921 devm_kfree(ice_hw_to_dev(hw), sw); 922 } 923 924 /** 925 * ice_get_itr_intrl_gran 926 * @hw: pointer to the HW struct 927 * 928 * Determines the ITR/INTRL granularities based on the maximum aggregate 929 * bandwidth according to the device's configuration during power-on. 930 */ 931 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 932 { 933 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 934 rd32(hw, GL_PWR_MODE_CTL)); 935 936 switch (max_agg_bw) { 937 case ICE_MAX_AGG_BW_200G: 938 case ICE_MAX_AGG_BW_100G: 939 case ICE_MAX_AGG_BW_50G: 940 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 941 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 942 break; 943 case ICE_MAX_AGG_BW_25G: 944 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 945 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 946 break; 947 } 948 } 949 950 /** 951 * ice_wait_for_fw - wait for full FW readiness 952 * @hw: pointer to the hardware structure 953 * @timeout: milliseconds that can elapse before timing out 954 * 955 * Return: 0 on success, -ETIMEDOUT on timeout. 956 */ 957 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 958 { 959 int fw_loading; 960 u32 elapsed = 0; 961 962 while (elapsed <= timeout) { 963 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 964 965 /* firmware was not yet loaded, we have to wait more */ 966 if (fw_loading) { 967 elapsed += 100; 968 msleep(100); 969 continue; 970 } 971 return 0; 972 } 973 974 return -ETIMEDOUT; 975 } 976 977 /** 978 * ice_init_hw - main hardware initialization routine 979 * @hw: pointer to the hardware structure 980 */ 981 int ice_init_hw(struct ice_hw *hw) 982 { 983 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 984 void *mac_buf __free(kfree) = NULL; 985 u16 mac_buf_len; 986 int status; 987 988 /* Set MAC type based on DeviceID */ 989 status = ice_set_mac_type(hw); 990 if (status) 991 return status; 992 993 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 994 995 status = ice_reset(hw, ICE_RESET_PFR); 996 if (status) 997 return status; 998 999 ice_get_itr_intrl_gran(hw); 1000 1001 status = ice_create_all_ctrlq(hw); 1002 if (status) 1003 goto err_unroll_cqinit; 1004 1005 status = ice_fwlog_init(hw); 1006 if (status) 1007 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1008 status); 1009 1010 status = ice_clear_pf_cfg(hw); 1011 if (status) 1012 goto err_unroll_cqinit; 1013 1014 /* Set bit to enable Flow Director filters */ 1015 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1016 INIT_LIST_HEAD(&hw->fdir_list_head); 1017 1018 ice_clear_pxe_mode(hw); 1019 1020 status = ice_init_nvm(hw); 1021 if (status) 1022 goto err_unroll_cqinit; 1023 1024 status = ice_get_caps(hw); 1025 if (status) 1026 goto err_unroll_cqinit; 1027 1028 if (!hw->port_info) 1029 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1030 sizeof(*hw->port_info), 1031 GFP_KERNEL); 1032 if (!hw->port_info) { 1033 status = -ENOMEM; 1034 goto err_unroll_cqinit; 1035 } 1036 1037 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1038 /* set the back pointer to HW */ 1039 hw->port_info->hw = hw; 1040 1041 /* Initialize port_info struct with switch configuration data */ 1042 status = ice_get_initial_sw_cfg(hw); 1043 if (status) 1044 goto err_unroll_alloc; 1045 1046 hw->evb_veb = true; 1047 1048 /* init xarray for identifying scheduling nodes uniquely */ 1049 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1050 1051 /* Query the allocated resources for Tx scheduler */ 1052 status = ice_sched_query_res_alloc(hw); 1053 if (status) { 1054 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1055 goto err_unroll_alloc; 1056 } 1057 ice_sched_get_psm_clk_freq(hw); 1058 1059 /* Initialize port_info struct with scheduler data */ 1060 status = ice_sched_init_port(hw->port_info); 1061 if (status) 1062 goto err_unroll_sched; 1063 1064 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1065 if (!pcaps) { 1066 status = -ENOMEM; 1067 goto err_unroll_sched; 1068 } 1069 1070 /* Initialize port_info struct with PHY capabilities */ 1071 status = ice_aq_get_phy_caps(hw->port_info, false, 1072 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1073 NULL); 1074 if (status) 1075 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1076 status); 1077 1078 /* Initialize port_info struct with link information */ 1079 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1080 if (status) 1081 goto err_unroll_sched; 1082 1083 /* need a valid SW entry point to build a Tx tree */ 1084 if (!hw->sw_entry_point_layer) { 1085 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1086 status = -EIO; 1087 goto err_unroll_sched; 1088 } 1089 INIT_LIST_HEAD(&hw->agg_list); 1090 /* Initialize max burst size */ 1091 if (!hw->max_burst_size) 1092 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1093 1094 status = ice_init_fltr_mgmt_struct(hw); 1095 if (status) 1096 goto err_unroll_sched; 1097 1098 /* Get MAC information */ 1099 /* A single port can report up to two (LAN and WoL) addresses */ 1100 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1101 GFP_KERNEL); 1102 if (!mac_buf) { 1103 status = -ENOMEM; 1104 goto err_unroll_fltr_mgmt_struct; 1105 } 1106 1107 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1108 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1109 1110 if (status) 1111 goto err_unroll_fltr_mgmt_struct; 1112 /* enable jumbo frame support at MAC level */ 1113 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1114 if (status) 1115 goto err_unroll_fltr_mgmt_struct; 1116 /* Obtain counter base index which would be used by flow director */ 1117 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1118 if (status) 1119 goto err_unroll_fltr_mgmt_struct; 1120 status = ice_init_hw_tbls(hw); 1121 if (status) 1122 goto err_unroll_fltr_mgmt_struct; 1123 mutex_init(&hw->tnl_lock); 1124 ice_init_chk_recipe_reuse_support(hw); 1125 1126 /* Some cards require longer initialization times 1127 * due to necessity of loading FW from an external source. 1128 * This can take even half a minute. 1129 */ 1130 if (ice_is_pf_c827(hw)) { 1131 status = ice_wait_for_fw(hw, 30000); 1132 if (status) { 1133 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1134 goto err_unroll_fltr_mgmt_struct; 1135 } 1136 } 1137 1138 return 0; 1139 err_unroll_fltr_mgmt_struct: 1140 ice_cleanup_fltr_mgmt_struct(hw); 1141 err_unroll_sched: 1142 ice_sched_cleanup_all(hw); 1143 err_unroll_alloc: 1144 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1145 err_unroll_cqinit: 1146 ice_destroy_all_ctrlq(hw); 1147 return status; 1148 } 1149 1150 /** 1151 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1152 * @hw: pointer to the hardware structure 1153 * 1154 * This should be called only during nominal operation, not as a result of 1155 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1156 * applicable initializations if it fails for any reason. 1157 */ 1158 void ice_deinit_hw(struct ice_hw *hw) 1159 { 1160 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1161 ice_cleanup_fltr_mgmt_struct(hw); 1162 1163 ice_sched_cleanup_all(hw); 1164 ice_sched_clear_agg(hw); 1165 ice_free_seg(hw); 1166 ice_free_hw_tbls(hw); 1167 mutex_destroy(&hw->tnl_lock); 1168 1169 ice_fwlog_deinit(hw); 1170 ice_destroy_all_ctrlq(hw); 1171 1172 /* Clear VSI contexts if not already cleared */ 1173 ice_clear_all_vsi_ctx(hw); 1174 } 1175 1176 /** 1177 * ice_check_reset - Check to see if a global reset is complete 1178 * @hw: pointer to the hardware structure 1179 */ 1180 int ice_check_reset(struct ice_hw *hw) 1181 { 1182 u32 cnt, reg = 0, grst_timeout, uld_mask; 1183 1184 /* Poll for Device Active state in case a recent CORER, GLOBR, 1185 * or EMPR has occurred. The grst delay value is in 100ms units. 1186 * Add 1sec for outstanding AQ commands that can take a long time. 1187 */ 1188 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1189 rd32(hw, GLGEN_RSTCTL)) + 10; 1190 1191 for (cnt = 0; cnt < grst_timeout; cnt++) { 1192 mdelay(100); 1193 reg = rd32(hw, GLGEN_RSTAT); 1194 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1195 break; 1196 } 1197 1198 if (cnt == grst_timeout) { 1199 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1200 return -EIO; 1201 } 1202 1203 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1204 GLNVM_ULD_PCIER_DONE_1_M |\ 1205 GLNVM_ULD_CORER_DONE_M |\ 1206 GLNVM_ULD_GLOBR_DONE_M |\ 1207 GLNVM_ULD_POR_DONE_M |\ 1208 GLNVM_ULD_POR_DONE_1_M |\ 1209 GLNVM_ULD_PCIER_DONE_2_M) 1210 1211 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1212 GLNVM_ULD_PE_DONE_M : 0); 1213 1214 /* Device is Active; check Global Reset processes are done */ 1215 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1216 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1217 if (reg == uld_mask) { 1218 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1219 break; 1220 } 1221 mdelay(10); 1222 } 1223 1224 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1225 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1226 reg); 1227 return -EIO; 1228 } 1229 1230 return 0; 1231 } 1232 1233 /** 1234 * ice_pf_reset - Reset the PF 1235 * @hw: pointer to the hardware structure 1236 * 1237 * If a global reset has been triggered, this function checks 1238 * for its completion and then issues the PF reset 1239 */ 1240 static int ice_pf_reset(struct ice_hw *hw) 1241 { 1242 u32 cnt, reg; 1243 1244 /* If at function entry a global reset was already in progress, i.e. 1245 * state is not 'device active' or any of the reset done bits are not 1246 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1247 * global reset is done. 1248 */ 1249 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1250 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1251 /* poll on global reset currently in progress until done */ 1252 if (ice_check_reset(hw)) 1253 return -EIO; 1254 1255 return 0; 1256 } 1257 1258 /* Reset the PF */ 1259 reg = rd32(hw, PFGEN_CTRL); 1260 1261 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1262 1263 /* Wait for the PFR to complete. The wait time is the global config lock 1264 * timeout plus the PFR timeout which will account for a possible reset 1265 * that is occurring during a download package operation. 1266 */ 1267 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1268 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1269 reg = rd32(hw, PFGEN_CTRL); 1270 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1271 break; 1272 1273 mdelay(1); 1274 } 1275 1276 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1277 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1278 return -EIO; 1279 } 1280 1281 return 0; 1282 } 1283 1284 /** 1285 * ice_reset - Perform different types of reset 1286 * @hw: pointer to the hardware structure 1287 * @req: reset request 1288 * 1289 * This function triggers a reset as specified by the req parameter. 1290 * 1291 * Note: 1292 * If anything other than a PF reset is triggered, PXE mode is restored. 1293 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1294 * interface has been restored in the rebuild flow. 1295 */ 1296 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1297 { 1298 u32 val = 0; 1299 1300 switch (req) { 1301 case ICE_RESET_PFR: 1302 return ice_pf_reset(hw); 1303 case ICE_RESET_CORER: 1304 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1305 val = GLGEN_RTRIG_CORER_M; 1306 break; 1307 case ICE_RESET_GLOBR: 1308 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1309 val = GLGEN_RTRIG_GLOBR_M; 1310 break; 1311 default: 1312 return -EINVAL; 1313 } 1314 1315 val |= rd32(hw, GLGEN_RTRIG); 1316 wr32(hw, GLGEN_RTRIG, val); 1317 ice_flush(hw); 1318 1319 /* wait for the FW to be ready */ 1320 return ice_check_reset(hw); 1321 } 1322 1323 /** 1324 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1325 * @hw: pointer to the hardware structure 1326 * @rxq_ctx: pointer to the packed Rx queue context 1327 * @rxq_index: the index of the Rx queue 1328 */ 1329 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1330 const ice_rxq_ctx_buf_t *rxq_ctx, 1331 u32 rxq_index) 1332 { 1333 /* Copy each dword separately to HW */ 1334 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1335 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1336 1337 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1338 1339 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1340 } 1341 } 1342 1343 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1344 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1345 1346 /* LAN Rx Queue Context */ 1347 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1348 /* Field Width LSB */ 1349 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1350 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1351 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1352 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1353 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1354 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1355 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1356 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1357 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1358 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1359 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1360 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1361 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1362 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1363 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1364 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1365 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1366 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1367 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1368 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1369 }; 1370 1371 /** 1372 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1373 * @ctx: the Rx queue context to pack 1374 * @buf: the HW buffer to pack into 1375 * 1376 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1377 * bit-packed HW layout. 1378 */ 1379 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1380 ice_rxq_ctx_buf_t *buf) 1381 { 1382 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1383 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1384 } 1385 1386 /** 1387 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1388 * @hw: pointer to the hardware structure 1389 * @rlan_ctx: pointer to the unpacked Rx queue context 1390 * @rxq_index: the index of the Rx queue 1391 * 1392 * Pack the sparse Rx Queue context into dense hardware format and write it 1393 * into the HW register space. 1394 * 1395 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1396 */ 1397 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1398 u32 rxq_index) 1399 { 1400 ice_rxq_ctx_buf_t buf = {}; 1401 1402 if (rxq_index > QRX_CTRL_MAX_INDEX) 1403 return -EINVAL; 1404 1405 ice_pack_rxq_ctx(rlan_ctx, &buf); 1406 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1407 1408 return 0; 1409 } 1410 1411 /* LAN Tx Queue Context */ 1412 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1413 /* Field Width LSB */ 1414 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1415 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1416 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1417 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1418 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1419 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1420 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1421 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1422 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1423 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1424 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1425 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1426 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1427 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1428 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1429 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1430 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1431 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1432 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1433 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1434 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1435 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1436 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1437 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1438 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1439 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1440 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1441 }; 1442 1443 /** 1444 * ice_pack_txq_ctx - Pack Tx queue context into a HW buffer 1445 * @ctx: the Tx queue context to pack 1446 * @buf: the HW buffer to pack into 1447 * 1448 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1449 * bit-packed HW layout. 1450 */ 1451 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1452 { 1453 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1454 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1455 } 1456 1457 /* Sideband Queue command wrappers */ 1458 1459 /** 1460 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1461 * @hw: pointer to the HW struct 1462 * @desc: descriptor describing the command 1463 * @buf: buffer to use for indirect commands (NULL for direct commands) 1464 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1465 * @cd: pointer to command details structure 1466 */ 1467 static int 1468 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1469 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1470 { 1471 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1472 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1473 } 1474 1475 /** 1476 * ice_sbq_rw_reg - Fill Sideband Queue command 1477 * @hw: pointer to the HW struct 1478 * @in: message info to be filled in descriptor 1479 * @flags: control queue descriptor flags 1480 */ 1481 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1482 { 1483 struct ice_sbq_cmd_desc desc = {0}; 1484 struct ice_sbq_msg_req msg = {0}; 1485 u16 msg_len; 1486 int status; 1487 1488 msg_len = sizeof(msg); 1489 1490 msg.dest_dev = in->dest_dev; 1491 msg.opcode = in->opcode; 1492 msg.flags = ICE_SBQ_MSG_FLAGS; 1493 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1494 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1495 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1496 1497 if (in->opcode) 1498 msg.data = cpu_to_le32(in->data); 1499 else 1500 /* data read comes back in completion, so shorten the struct by 1501 * sizeof(msg.data) 1502 */ 1503 msg_len -= sizeof(msg.data); 1504 1505 desc.flags = cpu_to_le16(flags); 1506 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1507 desc.param0.cmd_len = cpu_to_le16(msg_len); 1508 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1509 if (!status && !in->opcode) 1510 in->data = le32_to_cpu 1511 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1512 return status; 1513 } 1514 1515 /* FW Admin Queue command wrappers */ 1516 1517 /* Software lock/mutex that is meant to be held while the Global Config Lock 1518 * in firmware is acquired by the software to prevent most (but not all) types 1519 * of AQ commands from being sent to FW 1520 */ 1521 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1522 1523 /** 1524 * ice_should_retry_sq_send_cmd 1525 * @opcode: AQ opcode 1526 * 1527 * Decide if we should retry the send command routine for the ATQ, depending 1528 * on the opcode. 1529 */ 1530 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1531 { 1532 switch (opcode) { 1533 case ice_aqc_opc_get_link_topo: 1534 case ice_aqc_opc_lldp_stop: 1535 case ice_aqc_opc_lldp_start: 1536 case ice_aqc_opc_lldp_filter_ctrl: 1537 return true; 1538 } 1539 1540 return false; 1541 } 1542 1543 /** 1544 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1545 * @hw: pointer to the HW struct 1546 * @cq: pointer to the specific Control queue 1547 * @desc: prefilled descriptor describing the command 1548 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1549 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1550 * @cd: pointer to command details structure 1551 * 1552 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1553 * Queue if the EBUSY AQ error is returned. 1554 */ 1555 static int 1556 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1557 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1558 struct ice_sq_cd *cd) 1559 { 1560 struct ice_aq_desc desc_cpy; 1561 bool is_cmd_for_retry; 1562 u8 idx = 0; 1563 u16 opcode; 1564 int status; 1565 1566 opcode = le16_to_cpu(desc->opcode); 1567 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1568 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1569 1570 if (is_cmd_for_retry) { 1571 /* All retryable cmds are direct, without buf. */ 1572 WARN_ON(buf); 1573 1574 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1575 } 1576 1577 do { 1578 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1579 1580 if (!is_cmd_for_retry || !status || 1581 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1582 break; 1583 1584 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1585 1586 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1587 1588 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1589 1590 return status; 1591 } 1592 1593 /** 1594 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1595 * @hw: pointer to the HW struct 1596 * @desc: descriptor describing the command 1597 * @buf: buffer to use for indirect commands (NULL for direct commands) 1598 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1599 * @cd: pointer to command details structure 1600 * 1601 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1602 */ 1603 int 1604 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1605 u16 buf_size, struct ice_sq_cd *cd) 1606 { 1607 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1608 bool lock_acquired = false; 1609 int status; 1610 1611 /* When a package download is in process (i.e. when the firmware's 1612 * Global Configuration Lock resource is held), only the Download 1613 * Package, Get Version, Get Package Info List, Upload Section, 1614 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1615 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1616 * Recipes to Profile Association, and Release Resource (with resource 1617 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1618 * must block until the package download completes and the Global Config 1619 * Lock is released. See also ice_acquire_global_cfg_lock(). 1620 */ 1621 switch (le16_to_cpu(desc->opcode)) { 1622 case ice_aqc_opc_download_pkg: 1623 case ice_aqc_opc_get_pkg_info_list: 1624 case ice_aqc_opc_get_ver: 1625 case ice_aqc_opc_upload_section: 1626 case ice_aqc_opc_update_pkg: 1627 case ice_aqc_opc_set_port_params: 1628 case ice_aqc_opc_get_vlan_mode_parameters: 1629 case ice_aqc_opc_set_vlan_mode_parameters: 1630 case ice_aqc_opc_set_tx_topo: 1631 case ice_aqc_opc_get_tx_topo: 1632 case ice_aqc_opc_add_recipe: 1633 case ice_aqc_opc_recipe_to_profile: 1634 case ice_aqc_opc_get_recipe: 1635 case ice_aqc_opc_get_recipe_to_profile: 1636 break; 1637 case ice_aqc_opc_release_res: 1638 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1639 break; 1640 fallthrough; 1641 default: 1642 mutex_lock(&ice_global_cfg_lock_sw); 1643 lock_acquired = true; 1644 break; 1645 } 1646 1647 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1648 if (lock_acquired) 1649 mutex_unlock(&ice_global_cfg_lock_sw); 1650 1651 return status; 1652 } 1653 1654 /** 1655 * ice_aq_get_fw_ver 1656 * @hw: pointer to the HW struct 1657 * @cd: pointer to command details structure or NULL 1658 * 1659 * Get the firmware version (0x0001) from the admin queue commands 1660 */ 1661 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1662 { 1663 struct ice_aqc_get_ver *resp; 1664 struct ice_aq_desc desc; 1665 int status; 1666 1667 resp = &desc.params.get_ver; 1668 1669 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1670 1671 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1672 1673 if (!status) { 1674 hw->fw_branch = resp->fw_branch; 1675 hw->fw_maj_ver = resp->fw_major; 1676 hw->fw_min_ver = resp->fw_minor; 1677 hw->fw_patch = resp->fw_patch; 1678 hw->fw_build = le32_to_cpu(resp->fw_build); 1679 hw->api_branch = resp->api_branch; 1680 hw->api_maj_ver = resp->api_major; 1681 hw->api_min_ver = resp->api_minor; 1682 hw->api_patch = resp->api_patch; 1683 } 1684 1685 return status; 1686 } 1687 1688 /** 1689 * ice_aq_send_driver_ver 1690 * @hw: pointer to the HW struct 1691 * @dv: driver's major, minor version 1692 * @cd: pointer to command details structure or NULL 1693 * 1694 * Send the driver version (0x0002) to the firmware 1695 */ 1696 int 1697 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1698 struct ice_sq_cd *cd) 1699 { 1700 struct ice_aqc_driver_ver *cmd; 1701 struct ice_aq_desc desc; 1702 u16 len; 1703 1704 cmd = &desc.params.driver_ver; 1705 1706 if (!dv) 1707 return -EINVAL; 1708 1709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1710 1711 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1712 cmd->major_ver = dv->major_ver; 1713 cmd->minor_ver = dv->minor_ver; 1714 cmd->build_ver = dv->build_ver; 1715 cmd->subbuild_ver = dv->subbuild_ver; 1716 1717 len = 0; 1718 while (len < sizeof(dv->driver_string) && 1719 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1720 len++; 1721 1722 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1723 } 1724 1725 /** 1726 * ice_aq_q_shutdown 1727 * @hw: pointer to the HW struct 1728 * @unloading: is the driver unloading itself 1729 * 1730 * Tell the Firmware that we're shutting down the AdminQ and whether 1731 * or not the driver is unloading as well (0x0003). 1732 */ 1733 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1734 { 1735 struct ice_aqc_q_shutdown *cmd; 1736 struct ice_aq_desc desc; 1737 1738 cmd = &desc.params.q_shutdown; 1739 1740 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1741 1742 if (unloading) 1743 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1744 1745 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1746 } 1747 1748 /** 1749 * ice_aq_req_res 1750 * @hw: pointer to the HW struct 1751 * @res: resource ID 1752 * @access: access type 1753 * @sdp_number: resource number 1754 * @timeout: the maximum time in ms that the driver may hold the resource 1755 * @cd: pointer to command details structure or NULL 1756 * 1757 * Requests common resource using the admin queue commands (0x0008). 1758 * When attempting to acquire the Global Config Lock, the driver can 1759 * learn of three states: 1760 * 1) 0 - acquired lock, and can perform download package 1761 * 2) -EIO - did not get lock, driver should fail to load 1762 * 3) -EALREADY - did not get lock, but another driver has 1763 * successfully downloaded the package; the driver does 1764 * not have to download the package and can continue 1765 * loading 1766 * 1767 * Note that if the caller is in an acquire lock, perform action, release lock 1768 * phase of operation, it is possible that the FW may detect a timeout and issue 1769 * a CORER. In this case, the driver will receive a CORER interrupt and will 1770 * have to determine its cause. The calling thread that is handling this flow 1771 * will likely get an error propagated back to it indicating the Download 1772 * Package, Update Package or the Release Resource AQ commands timed out. 1773 */ 1774 static int 1775 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1776 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1777 struct ice_sq_cd *cd) 1778 { 1779 struct ice_aqc_req_res *cmd_resp; 1780 struct ice_aq_desc desc; 1781 int status; 1782 1783 cmd_resp = &desc.params.res_owner; 1784 1785 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1786 1787 cmd_resp->res_id = cpu_to_le16(res); 1788 cmd_resp->access_type = cpu_to_le16(access); 1789 cmd_resp->res_number = cpu_to_le32(sdp_number); 1790 cmd_resp->timeout = cpu_to_le32(*timeout); 1791 *timeout = 0; 1792 1793 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1794 1795 /* The completion specifies the maximum time in ms that the driver 1796 * may hold the resource in the Timeout field. 1797 */ 1798 1799 /* Global config lock response utilizes an additional status field. 1800 * 1801 * If the Global config lock resource is held by some other driver, the 1802 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1803 * and the timeout field indicates the maximum time the current owner 1804 * of the resource has to free it. 1805 */ 1806 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1807 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1808 *timeout = le32_to_cpu(cmd_resp->timeout); 1809 return 0; 1810 } else if (le16_to_cpu(cmd_resp->status) == 1811 ICE_AQ_RES_GLBL_IN_PROG) { 1812 *timeout = le32_to_cpu(cmd_resp->timeout); 1813 return -EIO; 1814 } else if (le16_to_cpu(cmd_resp->status) == 1815 ICE_AQ_RES_GLBL_DONE) { 1816 return -EALREADY; 1817 } 1818 1819 /* invalid FW response, force a timeout immediately */ 1820 *timeout = 0; 1821 return -EIO; 1822 } 1823 1824 /* If the resource is held by some other driver, the command completes 1825 * with a busy return value and the timeout field indicates the maximum 1826 * time the current owner of the resource has to free it. 1827 */ 1828 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1829 *timeout = le32_to_cpu(cmd_resp->timeout); 1830 1831 return status; 1832 } 1833 1834 /** 1835 * ice_aq_release_res 1836 * @hw: pointer to the HW struct 1837 * @res: resource ID 1838 * @sdp_number: resource number 1839 * @cd: pointer to command details structure or NULL 1840 * 1841 * release common resource using the admin queue commands (0x0009) 1842 */ 1843 static int 1844 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1845 struct ice_sq_cd *cd) 1846 { 1847 struct ice_aqc_req_res *cmd; 1848 struct ice_aq_desc desc; 1849 1850 cmd = &desc.params.res_owner; 1851 1852 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1853 1854 cmd->res_id = cpu_to_le16(res); 1855 cmd->res_number = cpu_to_le32(sdp_number); 1856 1857 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1858 } 1859 1860 /** 1861 * ice_acquire_res 1862 * @hw: pointer to the HW structure 1863 * @res: resource ID 1864 * @access: access type (read or write) 1865 * @timeout: timeout in milliseconds 1866 * 1867 * This function will attempt to acquire the ownership of a resource. 1868 */ 1869 int 1870 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1871 enum ice_aq_res_access_type access, u32 timeout) 1872 { 1873 #define ICE_RES_POLLING_DELAY_MS 10 1874 u32 delay = ICE_RES_POLLING_DELAY_MS; 1875 u32 time_left = timeout; 1876 int status; 1877 1878 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1879 1880 /* A return code of -EALREADY means that another driver has 1881 * previously acquired the resource and performed any necessary updates; 1882 * in this case the caller does not obtain the resource and has no 1883 * further work to do. 1884 */ 1885 if (status == -EALREADY) 1886 goto ice_acquire_res_exit; 1887 1888 if (status) 1889 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1890 1891 /* If necessary, poll until the current lock owner timeouts */ 1892 timeout = time_left; 1893 while (status && timeout && time_left) { 1894 mdelay(delay); 1895 timeout = (timeout > delay) ? timeout - delay : 0; 1896 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1897 1898 if (status == -EALREADY) 1899 /* lock free, but no work to do */ 1900 break; 1901 1902 if (!status) 1903 /* lock acquired */ 1904 break; 1905 } 1906 if (status && status != -EALREADY) 1907 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1908 1909 ice_acquire_res_exit: 1910 if (status == -EALREADY) { 1911 if (access == ICE_RES_WRITE) 1912 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1913 else 1914 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1915 } 1916 return status; 1917 } 1918 1919 /** 1920 * ice_release_res 1921 * @hw: pointer to the HW structure 1922 * @res: resource ID 1923 * 1924 * This function will release a resource using the proper Admin Command. 1925 */ 1926 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1927 { 1928 unsigned long timeout; 1929 int status; 1930 1931 /* there are some rare cases when trying to release the resource 1932 * results in an admin queue timeout, so handle them correctly 1933 */ 1934 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 1935 do { 1936 status = ice_aq_release_res(hw, res, 0, NULL); 1937 if (status != -EIO) 1938 break; 1939 usleep_range(1000, 2000); 1940 } while (time_before(jiffies, timeout)); 1941 } 1942 1943 /** 1944 * ice_aq_alloc_free_res - command to allocate/free resources 1945 * @hw: pointer to the HW struct 1946 * @buf: Indirect buffer to hold data parameters and response 1947 * @buf_size: size of buffer for indirect commands 1948 * @opc: pass in the command opcode 1949 * 1950 * Helper function to allocate/free resources using the admin queue commands 1951 */ 1952 int ice_aq_alloc_free_res(struct ice_hw *hw, 1953 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1954 enum ice_adminq_opc opc) 1955 { 1956 struct ice_aqc_alloc_free_res_cmd *cmd; 1957 struct ice_aq_desc desc; 1958 1959 cmd = &desc.params.sw_res_ctrl; 1960 1961 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 1962 return -EINVAL; 1963 1964 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1965 1966 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1967 1968 cmd->num_entries = cpu_to_le16(1); 1969 1970 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 1971 } 1972 1973 /** 1974 * ice_alloc_hw_res - allocate resource 1975 * @hw: pointer to the HW struct 1976 * @type: type of resource 1977 * @num: number of resources to allocate 1978 * @btm: allocate from bottom 1979 * @res: pointer to array that will receive the resources 1980 */ 1981 int 1982 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1983 { 1984 struct ice_aqc_alloc_free_res_elem *buf; 1985 u16 buf_len; 1986 int status; 1987 1988 buf_len = struct_size(buf, elem, num); 1989 buf = kzalloc(buf_len, GFP_KERNEL); 1990 if (!buf) 1991 return -ENOMEM; 1992 1993 /* Prepare buffer to allocate resource. */ 1994 buf->num_elems = cpu_to_le16(num); 1995 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1996 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1997 if (btm) 1998 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1999 2000 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2001 if (status) 2002 goto ice_alloc_res_exit; 2003 2004 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2005 2006 ice_alloc_res_exit: 2007 kfree(buf); 2008 return status; 2009 } 2010 2011 /** 2012 * ice_free_hw_res - free allocated HW resource 2013 * @hw: pointer to the HW struct 2014 * @type: type of resource to free 2015 * @num: number of resources 2016 * @res: pointer to array that contains the resources to free 2017 */ 2018 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2019 { 2020 struct ice_aqc_alloc_free_res_elem *buf; 2021 u16 buf_len; 2022 int status; 2023 2024 buf_len = struct_size(buf, elem, num); 2025 buf = kzalloc(buf_len, GFP_KERNEL); 2026 if (!buf) 2027 return -ENOMEM; 2028 2029 /* Prepare buffer to free resource. */ 2030 buf->num_elems = cpu_to_le16(num); 2031 buf->res_type = cpu_to_le16(type); 2032 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2033 2034 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2035 if (status) 2036 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2037 2038 kfree(buf); 2039 return status; 2040 } 2041 2042 /** 2043 * ice_get_num_per_func - determine number of resources per PF 2044 * @hw: pointer to the HW structure 2045 * @max: value to be evenly split between each PF 2046 * 2047 * Determine the number of valid functions by going through the bitmap returned 2048 * from parsing capabilities and use this to calculate the number of resources 2049 * per PF based on the max value passed in. 2050 */ 2051 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2052 { 2053 u8 funcs; 2054 2055 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2056 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2057 ICE_CAPS_VALID_FUNCS_M); 2058 2059 if (!funcs) 2060 return 0; 2061 2062 return max / funcs; 2063 } 2064 2065 /** 2066 * ice_parse_common_caps - parse common device/function capabilities 2067 * @hw: pointer to the HW struct 2068 * @caps: pointer to common capabilities structure 2069 * @elem: the capability element to parse 2070 * @prefix: message prefix for tracing capabilities 2071 * 2072 * Given a capability element, extract relevant details into the common 2073 * capability structure. 2074 * 2075 * Returns: true if the capability matches one of the common capability ids, 2076 * false otherwise. 2077 */ 2078 static bool 2079 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2080 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2081 { 2082 u32 logical_id = le32_to_cpu(elem->logical_id); 2083 u32 phys_id = le32_to_cpu(elem->phys_id); 2084 u32 number = le32_to_cpu(elem->number); 2085 u16 cap = le16_to_cpu(elem->cap); 2086 bool found = true; 2087 2088 switch (cap) { 2089 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2090 caps->valid_functions = number; 2091 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2092 caps->valid_functions); 2093 break; 2094 case ICE_AQC_CAPS_SRIOV: 2095 caps->sr_iov_1_1 = (number == 1); 2096 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2097 caps->sr_iov_1_1); 2098 break; 2099 case ICE_AQC_CAPS_DCB: 2100 caps->dcb = (number == 1); 2101 caps->active_tc_bitmap = logical_id; 2102 caps->maxtc = phys_id; 2103 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2104 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2105 caps->active_tc_bitmap); 2106 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2107 break; 2108 case ICE_AQC_CAPS_RSS: 2109 caps->rss_table_size = number; 2110 caps->rss_table_entry_width = logical_id; 2111 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2112 caps->rss_table_size); 2113 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2114 caps->rss_table_entry_width); 2115 break; 2116 case ICE_AQC_CAPS_RXQS: 2117 caps->num_rxq = number; 2118 caps->rxq_first_id = phys_id; 2119 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2120 caps->num_rxq); 2121 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2122 caps->rxq_first_id); 2123 break; 2124 case ICE_AQC_CAPS_TXQS: 2125 caps->num_txq = number; 2126 caps->txq_first_id = phys_id; 2127 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2128 caps->num_txq); 2129 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2130 caps->txq_first_id); 2131 break; 2132 case ICE_AQC_CAPS_MSIX: 2133 caps->num_msix_vectors = number; 2134 caps->msix_vector_first_id = phys_id; 2135 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2136 caps->num_msix_vectors); 2137 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2138 caps->msix_vector_first_id); 2139 break; 2140 case ICE_AQC_CAPS_PENDING_NVM_VER: 2141 caps->nvm_update_pending_nvm = true; 2142 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2143 break; 2144 case ICE_AQC_CAPS_PENDING_OROM_VER: 2145 caps->nvm_update_pending_orom = true; 2146 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2147 break; 2148 case ICE_AQC_CAPS_PENDING_NET_VER: 2149 caps->nvm_update_pending_netlist = true; 2150 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2151 break; 2152 case ICE_AQC_CAPS_NVM_MGMT: 2153 caps->nvm_unified_update = 2154 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2155 true : false; 2156 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2157 caps->nvm_unified_update); 2158 break; 2159 case ICE_AQC_CAPS_RDMA: 2160 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2161 caps->rdma = (number == 1); 2162 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2163 break; 2164 case ICE_AQC_CAPS_MAX_MTU: 2165 caps->max_mtu = number; 2166 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2167 prefix, caps->max_mtu); 2168 break; 2169 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2170 caps->pcie_reset_avoidance = (number > 0); 2171 ice_debug(hw, ICE_DBG_INIT, 2172 "%s: pcie_reset_avoidance = %d\n", prefix, 2173 caps->pcie_reset_avoidance); 2174 break; 2175 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2176 caps->reset_restrict_support = (number == 1); 2177 ice_debug(hw, ICE_DBG_INIT, 2178 "%s: reset_restrict_support = %d\n", prefix, 2179 caps->reset_restrict_support); 2180 break; 2181 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2182 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2183 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2184 prefix, caps->roce_lag); 2185 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2186 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2187 prefix, caps->sriov_lag); 2188 break; 2189 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2190 caps->tx_sched_topo_comp_mode_en = (number == 1); 2191 break; 2192 default: 2193 /* Not one of the recognized common capabilities */ 2194 found = false; 2195 } 2196 2197 return found; 2198 } 2199 2200 /** 2201 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2202 * @hw: pointer to the HW structure 2203 * @caps: pointer to capabilities structure to fix 2204 * 2205 * Re-calculate the capabilities that are dependent on the number of physical 2206 * ports; i.e. some features are not supported or function differently on 2207 * devices with more than 4 ports. 2208 */ 2209 static void 2210 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2211 { 2212 /* This assumes device capabilities are always scanned before function 2213 * capabilities during the initialization flow. 2214 */ 2215 if (hw->dev_caps.num_funcs > 4) { 2216 /* Max 4 TCs per port */ 2217 caps->maxtc = 4; 2218 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2219 caps->maxtc); 2220 if (caps->rdma) { 2221 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2222 caps->rdma = 0; 2223 } 2224 2225 /* print message only when processing device capabilities 2226 * during initialization. 2227 */ 2228 if (caps == &hw->dev_caps.common_cap) 2229 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2230 } 2231 } 2232 2233 /** 2234 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2235 * @hw: pointer to the HW struct 2236 * @func_p: pointer to function capabilities structure 2237 * @cap: pointer to the capability element to parse 2238 * 2239 * Extract function capabilities for ICE_AQC_CAPS_VF. 2240 */ 2241 static void 2242 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2243 struct ice_aqc_list_caps_elem *cap) 2244 { 2245 u32 logical_id = le32_to_cpu(cap->logical_id); 2246 u32 number = le32_to_cpu(cap->number); 2247 2248 func_p->num_allocd_vfs = number; 2249 func_p->vf_base_id = logical_id; 2250 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2251 func_p->num_allocd_vfs); 2252 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2253 func_p->vf_base_id); 2254 } 2255 2256 /** 2257 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2258 * @hw: pointer to the HW struct 2259 * @func_p: pointer to function capabilities structure 2260 * @cap: pointer to the capability element to parse 2261 * 2262 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2263 */ 2264 static void 2265 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2266 struct ice_aqc_list_caps_elem *cap) 2267 { 2268 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2269 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2270 le32_to_cpu(cap->number)); 2271 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2272 func_p->guar_num_vsi); 2273 } 2274 2275 /** 2276 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2277 * @hw: pointer to the HW struct 2278 * @func_p: pointer to function capabilities structure 2279 * @cap: pointer to the capability element to parse 2280 * 2281 * Extract function capabilities for ICE_AQC_CAPS_1588. 2282 */ 2283 static void 2284 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2285 struct ice_aqc_list_caps_elem *cap) 2286 { 2287 struct ice_ts_func_info *info = &func_p->ts_func_info; 2288 u32 number = le32_to_cpu(cap->number); 2289 2290 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2291 func_p->common_cap.ieee_1588 = info->ena; 2292 2293 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2294 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2295 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2296 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2297 2298 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2299 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2300 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2301 } else { 2302 info->clk_freq = ICE_TIME_REF_FREQ_156_250; 2303 info->clk_src = ICE_CLK_SRC_TCXO; 2304 } 2305 2306 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2307 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2308 } else { 2309 /* Unknown clock frequency, so assume a (probably incorrect) 2310 * default to avoid out-of-bounds look ups of frequency 2311 * related information. 2312 */ 2313 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2314 info->clk_freq); 2315 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2316 } 2317 2318 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2319 func_p->common_cap.ieee_1588); 2320 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2321 info->src_tmr_owned); 2322 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2323 info->tmr_ena); 2324 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2325 info->tmr_index_owned); 2326 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2327 info->tmr_index_assoc); 2328 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2329 info->clk_freq); 2330 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2331 info->clk_src); 2332 } 2333 2334 /** 2335 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2336 * @hw: pointer to the HW struct 2337 * @func_p: pointer to function capabilities structure 2338 * 2339 * Extract function capabilities for ICE_AQC_CAPS_FD. 2340 */ 2341 static void 2342 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2343 { 2344 u32 reg_val, gsize, bsize; 2345 2346 reg_val = rd32(hw, GLQF_FD_SIZE); 2347 switch (hw->mac_type) { 2348 case ICE_MAC_E830: 2349 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2350 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2351 break; 2352 case ICE_MAC_E810: 2353 default: 2354 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2355 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2356 } 2357 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2358 func_p->fd_fltr_best_effort = bsize; 2359 2360 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2361 func_p->fd_fltr_guar); 2362 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2363 func_p->fd_fltr_best_effort); 2364 } 2365 2366 /** 2367 * ice_parse_func_caps - Parse function capabilities 2368 * @hw: pointer to the HW struct 2369 * @func_p: pointer to function capabilities structure 2370 * @buf: buffer containing the function capability records 2371 * @cap_count: the number of capabilities 2372 * 2373 * Helper function to parse function (0x000A) capabilities list. For 2374 * capabilities shared between device and function, this relies on 2375 * ice_parse_common_caps. 2376 * 2377 * Loop through the list of provided capabilities and extract the relevant 2378 * data into the function capabilities structured. 2379 */ 2380 static void 2381 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2382 void *buf, u32 cap_count) 2383 { 2384 struct ice_aqc_list_caps_elem *cap_resp; 2385 u32 i; 2386 2387 cap_resp = buf; 2388 2389 memset(func_p, 0, sizeof(*func_p)); 2390 2391 for (i = 0; i < cap_count; i++) { 2392 u16 cap = le16_to_cpu(cap_resp[i].cap); 2393 bool found; 2394 2395 found = ice_parse_common_caps(hw, &func_p->common_cap, 2396 &cap_resp[i], "func caps"); 2397 2398 switch (cap) { 2399 case ICE_AQC_CAPS_VF: 2400 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2401 break; 2402 case ICE_AQC_CAPS_VSI: 2403 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2404 break; 2405 case ICE_AQC_CAPS_1588: 2406 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2407 break; 2408 case ICE_AQC_CAPS_FD: 2409 ice_parse_fdir_func_caps(hw, func_p); 2410 break; 2411 default: 2412 /* Don't list common capabilities as unknown */ 2413 if (!found) 2414 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2415 i, cap); 2416 break; 2417 } 2418 } 2419 2420 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2421 } 2422 2423 /** 2424 * ice_func_id_to_logical_id - map from function id to logical pf id 2425 * @active_function_bitmap: active function bitmap 2426 * @pf_id: function number of device 2427 * 2428 * Return: logical PF ID. 2429 */ 2430 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2431 { 2432 u8 logical_id = 0; 2433 u8 i; 2434 2435 for (i = 0; i < pf_id; i++) 2436 if (active_function_bitmap & BIT(i)) 2437 logical_id++; 2438 2439 return logical_id; 2440 } 2441 2442 /** 2443 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2444 * @hw: pointer to the HW struct 2445 * @dev_p: pointer to device capabilities structure 2446 * @cap: capability element to parse 2447 * 2448 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2449 */ 2450 static void 2451 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2452 struct ice_aqc_list_caps_elem *cap) 2453 { 2454 u32 number = le32_to_cpu(cap->number); 2455 2456 dev_p->num_funcs = hweight32(number); 2457 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2458 dev_p->num_funcs); 2459 2460 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2461 } 2462 2463 /** 2464 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2465 * @hw: pointer to the HW struct 2466 * @dev_p: pointer to device capabilities structure 2467 * @cap: capability element to parse 2468 * 2469 * Parse ICE_AQC_CAPS_VF for device capabilities. 2470 */ 2471 static void 2472 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2473 struct ice_aqc_list_caps_elem *cap) 2474 { 2475 u32 number = le32_to_cpu(cap->number); 2476 2477 dev_p->num_vfs_exposed = number; 2478 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2479 dev_p->num_vfs_exposed); 2480 } 2481 2482 /** 2483 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2484 * @hw: pointer to the HW struct 2485 * @dev_p: pointer to device capabilities structure 2486 * @cap: capability element to parse 2487 * 2488 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2489 */ 2490 static void 2491 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2492 struct ice_aqc_list_caps_elem *cap) 2493 { 2494 u32 number = le32_to_cpu(cap->number); 2495 2496 dev_p->num_vsi_allocd_to_host = number; 2497 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2498 dev_p->num_vsi_allocd_to_host); 2499 } 2500 2501 /** 2502 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2503 * @hw: pointer to the HW struct 2504 * @dev_p: pointer to device capabilities structure 2505 * @cap: capability element to parse 2506 * 2507 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2508 */ 2509 static void 2510 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2511 struct ice_aqc_list_caps_elem *cap) 2512 { 2513 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2514 u32 logical_id = le32_to_cpu(cap->logical_id); 2515 u32 phys_id = le32_to_cpu(cap->phys_id); 2516 u32 number = le32_to_cpu(cap->number); 2517 2518 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2519 dev_p->common_cap.ieee_1588 = info->ena; 2520 2521 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2522 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2523 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2524 2525 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2526 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2527 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2528 2529 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2530 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2531 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2532 2533 info->ena_ports = logical_id; 2534 info->tmr_own_map = phys_id; 2535 2536 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2537 dev_p->common_cap.ieee_1588); 2538 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2539 info->tmr0_owner); 2540 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2541 info->tmr0_owned); 2542 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2543 info->tmr0_ena); 2544 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2545 info->tmr1_owner); 2546 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2547 info->tmr1_owned); 2548 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2549 info->tmr1_ena); 2550 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2551 info->ts_ll_read); 2552 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2553 info->ts_ll_int_read); 2554 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2555 info->ll_phy_tmr_update); 2556 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2557 info->ena_ports); 2558 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2559 info->tmr_own_map); 2560 } 2561 2562 /** 2563 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2564 * @hw: pointer to the HW struct 2565 * @dev_p: pointer to device capabilities structure 2566 * @cap: capability element to parse 2567 * 2568 * Parse ICE_AQC_CAPS_FD for device capabilities. 2569 */ 2570 static void 2571 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2572 struct ice_aqc_list_caps_elem *cap) 2573 { 2574 u32 number = le32_to_cpu(cap->number); 2575 2576 dev_p->num_flow_director_fltr = number; 2577 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2578 dev_p->num_flow_director_fltr); 2579 } 2580 2581 /** 2582 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2583 * @hw: pointer to the HW struct 2584 * @dev_p: pointer to device capabilities structure 2585 * @cap: capability element to parse 2586 * 2587 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2588 * enabled sensors. 2589 */ 2590 static void 2591 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2592 struct ice_aqc_list_caps_elem *cap) 2593 { 2594 dev_p->supported_sensors = le32_to_cpu(cap->number); 2595 2596 ice_debug(hw, ICE_DBG_INIT, 2597 "dev caps: supported sensors (bitmap) = 0x%x\n", 2598 dev_p->supported_sensors); 2599 } 2600 2601 /** 2602 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2603 * @hw: pointer to the HW struct 2604 * @dev_p: pointer to device capabilities structure 2605 * @cap: capability element to parse 2606 * 2607 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2608 */ 2609 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2610 struct ice_hw_dev_caps *dev_p, 2611 struct ice_aqc_list_caps_elem *cap) 2612 { 2613 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2614 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2615 2616 dev_info(ice_hw_to_dev(hw), 2617 "PF is configured in %s mode with IP instance ID %d\n", 2618 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2619 "primary" : "secondary", dev_p->nac_topo.id); 2620 2621 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2622 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2623 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2624 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2625 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2626 dev_p->nac_topo.id); 2627 } 2628 2629 /** 2630 * ice_parse_dev_caps - Parse device capabilities 2631 * @hw: pointer to the HW struct 2632 * @dev_p: pointer to device capabilities structure 2633 * @buf: buffer containing the device capability records 2634 * @cap_count: the number of capabilities 2635 * 2636 * Helper device to parse device (0x000B) capabilities list. For 2637 * capabilities shared between device and function, this relies on 2638 * ice_parse_common_caps. 2639 * 2640 * Loop through the list of provided capabilities and extract the relevant 2641 * data into the device capabilities structured. 2642 */ 2643 static void 2644 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2645 void *buf, u32 cap_count) 2646 { 2647 struct ice_aqc_list_caps_elem *cap_resp; 2648 u32 i; 2649 2650 cap_resp = buf; 2651 2652 memset(dev_p, 0, sizeof(*dev_p)); 2653 2654 for (i = 0; i < cap_count; i++) { 2655 u16 cap = le16_to_cpu(cap_resp[i].cap); 2656 bool found; 2657 2658 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2659 &cap_resp[i], "dev caps"); 2660 2661 switch (cap) { 2662 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2663 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2664 break; 2665 case ICE_AQC_CAPS_VF: 2666 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2667 break; 2668 case ICE_AQC_CAPS_VSI: 2669 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2670 break; 2671 case ICE_AQC_CAPS_1588: 2672 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2673 break; 2674 case ICE_AQC_CAPS_FD: 2675 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2676 break; 2677 case ICE_AQC_CAPS_SENSOR_READING: 2678 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2679 break; 2680 case ICE_AQC_CAPS_NAC_TOPOLOGY: 2681 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2682 break; 2683 default: 2684 /* Don't list common capabilities as unknown */ 2685 if (!found) 2686 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2687 i, cap); 2688 break; 2689 } 2690 } 2691 2692 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2693 } 2694 2695 /** 2696 * ice_is_phy_rclk_in_netlist 2697 * @hw: pointer to the hw struct 2698 * 2699 * Check if the PHY Recovered Clock device is present in the netlist 2700 */ 2701 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2702 { 2703 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2704 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2705 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2706 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2707 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2708 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2709 return false; 2710 2711 return true; 2712 } 2713 2714 /** 2715 * ice_is_clock_mux_in_netlist 2716 * @hw: pointer to the hw struct 2717 * 2718 * Check if the Clock Multiplexer device is present in the netlist 2719 */ 2720 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2721 { 2722 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2723 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2724 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2725 NULL)) 2726 return false; 2727 2728 return true; 2729 } 2730 2731 /** 2732 * ice_is_cgu_in_netlist - check for CGU presence 2733 * @hw: pointer to the hw struct 2734 * 2735 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2736 * Save the CGU part number in the hw structure for later use. 2737 * Return: 2738 * * true - cgu is present 2739 * * false - cgu is not present 2740 */ 2741 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2742 { 2743 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2744 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2745 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2746 NULL)) { 2747 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2748 return true; 2749 } else if (!ice_find_netlist_node(hw, 2750 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2751 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2752 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2753 NULL)) { 2754 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2755 return true; 2756 } 2757 2758 return false; 2759 } 2760 2761 /** 2762 * ice_is_gps_in_netlist 2763 * @hw: pointer to the hw struct 2764 * 2765 * Check if the GPS generic device is present in the netlist 2766 */ 2767 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2768 { 2769 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2770 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2771 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 2772 return false; 2773 2774 return true; 2775 } 2776 2777 /** 2778 * ice_aq_list_caps - query function/device capabilities 2779 * @hw: pointer to the HW struct 2780 * @buf: a buffer to hold the capabilities 2781 * @buf_size: size of the buffer 2782 * @cap_count: if not NULL, set to the number of capabilities reported 2783 * @opc: capabilities type to discover, device or function 2784 * @cd: pointer to command details structure or NULL 2785 * 2786 * Get the function (0x000A) or device (0x000B) capabilities description from 2787 * firmware and store it in the buffer. 2788 * 2789 * If the cap_count pointer is not NULL, then it is set to the number of 2790 * capabilities firmware will report. Note that if the buffer size is too 2791 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2792 * cap_count will still be updated in this case. It is recommended that the 2793 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2794 * firmware could return) to avoid this. 2795 */ 2796 int 2797 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2798 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2799 { 2800 struct ice_aqc_list_caps *cmd; 2801 struct ice_aq_desc desc; 2802 int status; 2803 2804 cmd = &desc.params.get_cap; 2805 2806 if (opc != ice_aqc_opc_list_func_caps && 2807 opc != ice_aqc_opc_list_dev_caps) 2808 return -EINVAL; 2809 2810 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2811 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2812 2813 if (cap_count) 2814 *cap_count = le32_to_cpu(cmd->count); 2815 2816 return status; 2817 } 2818 2819 /** 2820 * ice_discover_dev_caps - Read and extract device capabilities 2821 * @hw: pointer to the hardware structure 2822 * @dev_caps: pointer to device capabilities structure 2823 * 2824 * Read the device capabilities and extract them into the dev_caps structure 2825 * for later use. 2826 */ 2827 int 2828 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2829 { 2830 u32 cap_count = 0; 2831 void *cbuf; 2832 int status; 2833 2834 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2835 if (!cbuf) 2836 return -ENOMEM; 2837 2838 /* Although the driver doesn't know the number of capabilities the 2839 * device will return, we can simply send a 4KB buffer, the maximum 2840 * possible size that firmware can return. 2841 */ 2842 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2843 2844 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2845 ice_aqc_opc_list_dev_caps, NULL); 2846 if (!status) 2847 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2848 kfree(cbuf); 2849 2850 return status; 2851 } 2852 2853 /** 2854 * ice_discover_func_caps - Read and extract function capabilities 2855 * @hw: pointer to the hardware structure 2856 * @func_caps: pointer to function capabilities structure 2857 * 2858 * Read the function capabilities and extract them into the func_caps structure 2859 * for later use. 2860 */ 2861 static int 2862 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2863 { 2864 u32 cap_count = 0; 2865 void *cbuf; 2866 int status; 2867 2868 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2869 if (!cbuf) 2870 return -ENOMEM; 2871 2872 /* Although the driver doesn't know the number of capabilities the 2873 * device will return, we can simply send a 4KB buffer, the maximum 2874 * possible size that firmware can return. 2875 */ 2876 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2877 2878 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2879 ice_aqc_opc_list_func_caps, NULL); 2880 if (!status) 2881 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2882 kfree(cbuf); 2883 2884 return status; 2885 } 2886 2887 /** 2888 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2889 * @hw: pointer to the hardware structure 2890 */ 2891 void ice_set_safe_mode_caps(struct ice_hw *hw) 2892 { 2893 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2894 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2895 struct ice_hw_common_caps cached_caps; 2896 u32 num_funcs; 2897 2898 /* cache some func_caps values that should be restored after memset */ 2899 cached_caps = func_caps->common_cap; 2900 2901 /* unset func capabilities */ 2902 memset(func_caps, 0, sizeof(*func_caps)); 2903 2904 #define ICE_RESTORE_FUNC_CAP(name) \ 2905 func_caps->common_cap.name = cached_caps.name 2906 2907 /* restore cached values */ 2908 ICE_RESTORE_FUNC_CAP(valid_functions); 2909 ICE_RESTORE_FUNC_CAP(txq_first_id); 2910 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2911 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2912 ICE_RESTORE_FUNC_CAP(max_mtu); 2913 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2914 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2915 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2916 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2917 2918 /* one Tx and one Rx queue in safe mode */ 2919 func_caps->common_cap.num_rxq = 1; 2920 func_caps->common_cap.num_txq = 1; 2921 2922 /* two MSIX vectors, one for traffic and one for misc causes */ 2923 func_caps->common_cap.num_msix_vectors = 2; 2924 func_caps->guar_num_vsi = 1; 2925 2926 /* cache some dev_caps values that should be restored after memset */ 2927 cached_caps = dev_caps->common_cap; 2928 num_funcs = dev_caps->num_funcs; 2929 2930 /* unset dev capabilities */ 2931 memset(dev_caps, 0, sizeof(*dev_caps)); 2932 2933 #define ICE_RESTORE_DEV_CAP(name) \ 2934 dev_caps->common_cap.name = cached_caps.name 2935 2936 /* restore cached values */ 2937 ICE_RESTORE_DEV_CAP(valid_functions); 2938 ICE_RESTORE_DEV_CAP(txq_first_id); 2939 ICE_RESTORE_DEV_CAP(rxq_first_id); 2940 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2941 ICE_RESTORE_DEV_CAP(max_mtu); 2942 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2943 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2944 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2945 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2946 dev_caps->num_funcs = num_funcs; 2947 2948 /* one Tx and one Rx queue per function in safe mode */ 2949 dev_caps->common_cap.num_rxq = num_funcs; 2950 dev_caps->common_cap.num_txq = num_funcs; 2951 2952 /* two MSIX vectors per function */ 2953 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2954 } 2955 2956 /** 2957 * ice_get_caps - get info about the HW 2958 * @hw: pointer to the hardware structure 2959 */ 2960 int ice_get_caps(struct ice_hw *hw) 2961 { 2962 int status; 2963 2964 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2965 if (status) 2966 return status; 2967 2968 return ice_discover_func_caps(hw, &hw->func_caps); 2969 } 2970 2971 /** 2972 * ice_aq_manage_mac_write - manage MAC address write command 2973 * @hw: pointer to the HW struct 2974 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2975 * @flags: flags to control write behavior 2976 * @cd: pointer to command details structure or NULL 2977 * 2978 * This function is used to write MAC address to the NVM (0x0108). 2979 */ 2980 int 2981 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2982 struct ice_sq_cd *cd) 2983 { 2984 struct ice_aqc_manage_mac_write *cmd; 2985 struct ice_aq_desc desc; 2986 2987 cmd = &desc.params.mac_write; 2988 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2989 2990 cmd->flags = flags; 2991 ether_addr_copy(cmd->mac_addr, mac_addr); 2992 2993 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2994 } 2995 2996 /** 2997 * ice_aq_clear_pxe_mode 2998 * @hw: pointer to the HW struct 2999 * 3000 * Tell the firmware that the driver is taking over from PXE (0x0110). 3001 */ 3002 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3003 { 3004 struct ice_aq_desc desc; 3005 3006 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3007 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3008 3009 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3010 } 3011 3012 /** 3013 * ice_clear_pxe_mode - clear pxe operations mode 3014 * @hw: pointer to the HW struct 3015 * 3016 * Make sure all PXE mode settings are cleared, including things 3017 * like descriptor fetch/write-back mode. 3018 */ 3019 void ice_clear_pxe_mode(struct ice_hw *hw) 3020 { 3021 if (ice_check_sq_alive(hw, &hw->adminq)) 3022 ice_aq_clear_pxe_mode(hw); 3023 } 3024 3025 /** 3026 * ice_aq_set_port_params - set physical port parameters. 3027 * @pi: pointer to the port info struct 3028 * @double_vlan: if set double VLAN is enabled 3029 * @cd: pointer to command details structure or NULL 3030 * 3031 * Set Physical port parameters (0x0203) 3032 */ 3033 int 3034 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3035 struct ice_sq_cd *cd) 3036 3037 { 3038 struct ice_aqc_set_port_params *cmd; 3039 struct ice_hw *hw = pi->hw; 3040 struct ice_aq_desc desc; 3041 u16 cmd_flags = 0; 3042 3043 cmd = &desc.params.set_port_params; 3044 3045 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3046 if (double_vlan) 3047 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3048 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3049 3050 cmd->local_fwd_mode = pi->local_fwd_mode | 3051 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3052 3053 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3054 } 3055 3056 /** 3057 * ice_is_100m_speed_supported 3058 * @hw: pointer to the HW struct 3059 * 3060 * returns true if 100M speeds are supported by the device, 3061 * false otherwise. 3062 */ 3063 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3064 { 3065 switch (hw->device_id) { 3066 case ICE_DEV_ID_E822C_SGMII: 3067 case ICE_DEV_ID_E822L_SGMII: 3068 case ICE_DEV_ID_E823L_1GBE: 3069 case ICE_DEV_ID_E823C_SGMII: 3070 return true; 3071 default: 3072 return false; 3073 } 3074 } 3075 3076 /** 3077 * ice_get_link_speed_based_on_phy_type - returns link speed 3078 * @phy_type_low: lower part of phy_type 3079 * @phy_type_high: higher part of phy_type 3080 * 3081 * This helper function will convert an entry in PHY type structure 3082 * [phy_type_low, phy_type_high] to its corresponding link speed. 3083 * Note: In the structure of [phy_type_low, phy_type_high], there should 3084 * be one bit set, as this function will convert one PHY type to its 3085 * speed. 3086 * 3087 * Return: 3088 * * PHY speed for recognized PHY type 3089 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3090 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3091 */ 3092 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3093 { 3094 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3095 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3096 3097 switch (phy_type_low) { 3098 case ICE_PHY_TYPE_LOW_100BASE_TX: 3099 case ICE_PHY_TYPE_LOW_100M_SGMII: 3100 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3101 break; 3102 case ICE_PHY_TYPE_LOW_1000BASE_T: 3103 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3104 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3105 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3106 case ICE_PHY_TYPE_LOW_1G_SGMII: 3107 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3108 break; 3109 case ICE_PHY_TYPE_LOW_2500BASE_T: 3110 case ICE_PHY_TYPE_LOW_2500BASE_X: 3111 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3112 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3113 break; 3114 case ICE_PHY_TYPE_LOW_5GBASE_T: 3115 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3116 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3117 break; 3118 case ICE_PHY_TYPE_LOW_10GBASE_T: 3119 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3120 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3121 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3122 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3123 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3124 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3125 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3126 break; 3127 case ICE_PHY_TYPE_LOW_25GBASE_T: 3128 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3129 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3130 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3131 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3132 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3133 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3134 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3135 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3136 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3137 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3138 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3139 break; 3140 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3141 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3142 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3143 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3144 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3145 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3146 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3147 break; 3148 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3149 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3150 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3151 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3152 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3153 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3154 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3155 case ICE_PHY_TYPE_LOW_50G_AUI2: 3156 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3157 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3158 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3159 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3160 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3161 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3162 case ICE_PHY_TYPE_LOW_50G_AUI1: 3163 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3164 break; 3165 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3166 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3167 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3168 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3169 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3170 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3171 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3172 case ICE_PHY_TYPE_LOW_100G_AUI4: 3173 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3174 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3175 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3176 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3177 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3178 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3179 break; 3180 default: 3181 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3182 break; 3183 } 3184 3185 switch (phy_type_high) { 3186 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3187 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3188 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3189 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3190 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3191 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3192 break; 3193 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3194 case ICE_PHY_TYPE_HIGH_200G_SR4: 3195 case ICE_PHY_TYPE_HIGH_200G_FR4: 3196 case ICE_PHY_TYPE_HIGH_200G_LR4: 3197 case ICE_PHY_TYPE_HIGH_200G_DR4: 3198 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3199 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3200 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3201 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3202 break; 3203 default: 3204 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3205 break; 3206 } 3207 3208 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3209 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3210 return ICE_AQ_LINK_SPEED_UNKNOWN; 3211 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3212 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3213 return ICE_AQ_LINK_SPEED_UNKNOWN; 3214 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3215 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3216 return speed_phy_type_low; 3217 else 3218 return speed_phy_type_high; 3219 } 3220 3221 /** 3222 * ice_update_phy_type 3223 * @phy_type_low: pointer to the lower part of phy_type 3224 * @phy_type_high: pointer to the higher part of phy_type 3225 * @link_speeds_bitmap: targeted link speeds bitmap 3226 * 3227 * Note: For the link_speeds_bitmap structure, you can check it at 3228 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3229 * link_speeds_bitmap include multiple speeds. 3230 * 3231 * Each entry in this [phy_type_low, phy_type_high] structure will 3232 * present a certain link speed. This helper function will turn on bits 3233 * in [phy_type_low, phy_type_high] structure based on the value of 3234 * link_speeds_bitmap input parameter. 3235 */ 3236 void 3237 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3238 u16 link_speeds_bitmap) 3239 { 3240 u64 pt_high; 3241 u64 pt_low; 3242 int index; 3243 u16 speed; 3244 3245 /* We first check with low part of phy_type */ 3246 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3247 pt_low = BIT_ULL(index); 3248 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3249 3250 if (link_speeds_bitmap & speed) 3251 *phy_type_low |= BIT_ULL(index); 3252 } 3253 3254 /* We then check with high part of phy_type */ 3255 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3256 pt_high = BIT_ULL(index); 3257 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3258 3259 if (link_speeds_bitmap & speed) 3260 *phy_type_high |= BIT_ULL(index); 3261 } 3262 } 3263 3264 /** 3265 * ice_aq_set_phy_cfg 3266 * @hw: pointer to the HW struct 3267 * @pi: port info structure of the interested logical port 3268 * @cfg: structure with PHY configuration data to be set 3269 * @cd: pointer to command details structure or NULL 3270 * 3271 * Set the various PHY configuration parameters supported on the Port. 3272 * One or more of the Set PHY config parameters may be ignored in an MFP 3273 * mode as the PF may not have the privilege to set some of the PHY Config 3274 * parameters. This status will be indicated by the command response (0x0601). 3275 */ 3276 int 3277 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3278 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3279 { 3280 struct ice_aq_desc desc; 3281 int status; 3282 3283 if (!cfg) 3284 return -EINVAL; 3285 3286 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3287 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3288 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3289 cfg->caps); 3290 3291 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3292 } 3293 3294 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3295 desc.params.set_phy.lport_num = pi->lport; 3296 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3297 3298 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3299 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3300 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3301 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3302 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3303 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3304 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3305 cfg->low_power_ctrl_an); 3306 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3307 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3308 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3309 cfg->link_fec_opt); 3310 3311 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3312 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3313 status = 0; 3314 3315 if (!status) 3316 pi->phy.curr_user_phy_cfg = *cfg; 3317 3318 return status; 3319 } 3320 3321 /** 3322 * ice_update_link_info - update status of the HW network link 3323 * @pi: port info structure of the interested logical port 3324 */ 3325 int ice_update_link_info(struct ice_port_info *pi) 3326 { 3327 struct ice_link_status *li; 3328 int status; 3329 3330 if (!pi) 3331 return -EINVAL; 3332 3333 li = &pi->phy.link_info; 3334 3335 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3336 if (status) 3337 return status; 3338 3339 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3340 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3341 3342 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3343 if (!pcaps) 3344 return -ENOMEM; 3345 3346 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3347 pcaps, NULL); 3348 } 3349 3350 return status; 3351 } 3352 3353 /** 3354 * ice_aq_get_phy_equalization - function to read serdes equaliser 3355 * value from firmware using admin queue command. 3356 * @hw: pointer to the HW struct 3357 * @data_in: represents the serdes equalization parameter requested 3358 * @op_code: represents the serdes number and flag to represent tx or rx 3359 * @serdes_num: represents the serdes number 3360 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3361 * 3362 * Return: non-zero status on error and 0 on success. 3363 */ 3364 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3365 u8 serdes_num, int *output) 3366 { 3367 struct ice_aqc_dnl_call_command *cmd; 3368 struct ice_aqc_dnl_call buf = {}; 3369 struct ice_aq_desc desc; 3370 int err; 3371 3372 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3373 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3374 cpu_to_le16(op_code | (serdes_num & 0xF)); 3375 cmd = &desc.params.dnl_call; 3376 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3377 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF | 3378 ICE_AQ_FLAG_RD | 3379 ICE_AQ_FLAG_SI); 3380 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3381 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3382 3383 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3384 NULL); 3385 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3386 3387 return err; 3388 } 3389 3390 #define FEC_REG_PORT(port) { \ 3391 FEC_CORR_LOW_REG_PORT##port, \ 3392 FEC_CORR_HIGH_REG_PORT##port, \ 3393 FEC_UNCORR_LOW_REG_PORT##port, \ 3394 FEC_UNCORR_HIGH_REG_PORT##port, \ 3395 } 3396 3397 static const u32 fec_reg[][ICE_FEC_MAX] = { 3398 FEC_REG_PORT(0), 3399 FEC_REG_PORT(1), 3400 FEC_REG_PORT(2), 3401 FEC_REG_PORT(3) 3402 }; 3403 3404 /** 3405 * ice_aq_get_fec_stats - reads fec stats from phy 3406 * @hw: pointer to the HW struct 3407 * @pcs_quad: represents pcsquad of user input serdes 3408 * @pcs_port: represents the pcs port number part of above pcs quad 3409 * @fec_type: represents FEC stats type 3410 * @output: pointer to the caller-supplied buffer to return requested fec stats 3411 * 3412 * Return: non-zero status on error and 0 on success. 3413 */ 3414 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3415 enum ice_fec_stats_types fec_type, u32 *output) 3416 { 3417 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI); 3418 struct ice_sbq_msg_input msg = {}; 3419 u32 receiver_id, reg_offset; 3420 int err; 3421 3422 if (pcs_port > 3) 3423 return -EINVAL; 3424 3425 reg_offset = fec_reg[pcs_port][fec_type]; 3426 3427 if (pcs_quad == 0) 3428 receiver_id = FEC_RECEIVER_ID_PCS0; 3429 else if (pcs_quad == 1) 3430 receiver_id = FEC_RECEIVER_ID_PCS1; 3431 else 3432 return -EINVAL; 3433 3434 msg.msg_addr_low = lower_16_bits(reg_offset); 3435 msg.msg_addr_high = receiver_id; 3436 msg.opcode = ice_sbq_msg_rd; 3437 msg.dest_dev = rmn_0; 3438 3439 err = ice_sbq_rw_reg(hw, &msg, flag); 3440 if (err) 3441 return err; 3442 3443 *output = msg.data; 3444 return 0; 3445 } 3446 3447 /** 3448 * ice_cache_phy_user_req 3449 * @pi: port information structure 3450 * @cache_data: PHY logging data 3451 * @cache_mode: PHY logging mode 3452 * 3453 * Log the user request on (FC, FEC, SPEED) for later use. 3454 */ 3455 static void 3456 ice_cache_phy_user_req(struct ice_port_info *pi, 3457 struct ice_phy_cache_mode_data cache_data, 3458 enum ice_phy_cache_mode cache_mode) 3459 { 3460 if (!pi) 3461 return; 3462 3463 switch (cache_mode) { 3464 case ICE_FC_MODE: 3465 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3466 break; 3467 case ICE_SPEED_MODE: 3468 pi->phy.curr_user_speed_req = 3469 cache_data.data.curr_user_speed_req; 3470 break; 3471 case ICE_FEC_MODE: 3472 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3473 break; 3474 default: 3475 break; 3476 } 3477 } 3478 3479 /** 3480 * ice_caps_to_fc_mode 3481 * @caps: PHY capabilities 3482 * 3483 * Convert PHY FC capabilities to ice FC mode 3484 */ 3485 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3486 { 3487 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3488 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3489 return ICE_FC_FULL; 3490 3491 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3492 return ICE_FC_TX_PAUSE; 3493 3494 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3495 return ICE_FC_RX_PAUSE; 3496 3497 return ICE_FC_NONE; 3498 } 3499 3500 /** 3501 * ice_caps_to_fec_mode 3502 * @caps: PHY capabilities 3503 * @fec_options: Link FEC options 3504 * 3505 * Convert PHY FEC capabilities to ice FEC mode 3506 */ 3507 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3508 { 3509 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3510 return ICE_FEC_AUTO; 3511 3512 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3513 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3514 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3515 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3516 return ICE_FEC_BASER; 3517 3518 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3519 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3520 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3521 return ICE_FEC_RS; 3522 3523 return ICE_FEC_NONE; 3524 } 3525 3526 /** 3527 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3528 * @pi: port information structure 3529 * @cfg: PHY configuration data to set FC mode 3530 * @req_mode: FC mode to configure 3531 */ 3532 int 3533 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3534 enum ice_fc_mode req_mode) 3535 { 3536 struct ice_phy_cache_mode_data cache_data; 3537 u8 pause_mask = 0x0; 3538 3539 if (!pi || !cfg) 3540 return -EINVAL; 3541 3542 switch (req_mode) { 3543 case ICE_FC_FULL: 3544 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3545 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3546 break; 3547 case ICE_FC_RX_PAUSE: 3548 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3549 break; 3550 case ICE_FC_TX_PAUSE: 3551 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3552 break; 3553 default: 3554 break; 3555 } 3556 3557 /* clear the old pause settings */ 3558 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3559 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3560 3561 /* set the new capabilities */ 3562 cfg->caps |= pause_mask; 3563 3564 /* Cache user FC request */ 3565 cache_data.data.curr_user_fc_req = req_mode; 3566 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3567 3568 return 0; 3569 } 3570 3571 /** 3572 * ice_set_fc 3573 * @pi: port information structure 3574 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3575 * @ena_auto_link_update: enable automatic link update 3576 * 3577 * Set the requested flow control mode. 3578 */ 3579 int 3580 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3581 { 3582 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3583 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3584 struct ice_hw *hw; 3585 int status; 3586 3587 if (!pi || !aq_failures) 3588 return -EINVAL; 3589 3590 *aq_failures = 0; 3591 hw = pi->hw; 3592 3593 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3594 if (!pcaps) 3595 return -ENOMEM; 3596 3597 /* Get the current PHY config */ 3598 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3599 pcaps, NULL); 3600 if (status) { 3601 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3602 goto out; 3603 } 3604 3605 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3606 3607 /* Configure the set PHY data */ 3608 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3609 if (status) 3610 goto out; 3611 3612 /* If the capabilities have changed, then set the new config */ 3613 if (cfg.caps != pcaps->caps) { 3614 int retry_count, retry_max = 10; 3615 3616 /* Auto restart link so settings take effect */ 3617 if (ena_auto_link_update) 3618 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3619 3620 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3621 if (status) { 3622 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3623 goto out; 3624 } 3625 3626 /* Update the link info 3627 * It sometimes takes a really long time for link to 3628 * come back from the atomic reset. Thus, we wait a 3629 * little bit. 3630 */ 3631 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3632 status = ice_update_link_info(pi); 3633 3634 if (!status) 3635 break; 3636 3637 mdelay(100); 3638 } 3639 3640 if (status) 3641 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3642 } 3643 3644 out: 3645 return status; 3646 } 3647 3648 /** 3649 * ice_phy_caps_equals_cfg 3650 * @phy_caps: PHY capabilities 3651 * @phy_cfg: PHY configuration 3652 * 3653 * Helper function to determine if PHY capabilities matches PHY 3654 * configuration 3655 */ 3656 bool 3657 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3658 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3659 { 3660 u8 caps_mask, cfg_mask; 3661 3662 if (!phy_caps || !phy_cfg) 3663 return false; 3664 3665 /* These bits are not common between capabilities and configuration. 3666 * Do not use them to determine equality. 3667 */ 3668 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3669 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3670 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3671 3672 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3673 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3674 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3675 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3676 phy_caps->eee_cap != phy_cfg->eee_cap || 3677 phy_caps->eeer_value != phy_cfg->eeer_value || 3678 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3679 return false; 3680 3681 return true; 3682 } 3683 3684 /** 3685 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3686 * @pi: port information structure 3687 * @caps: PHY ability structure to copy date from 3688 * @cfg: PHY configuration structure to copy data to 3689 * 3690 * Helper function to copy AQC PHY get ability data to PHY set configuration 3691 * data structure 3692 */ 3693 void 3694 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3695 struct ice_aqc_get_phy_caps_data *caps, 3696 struct ice_aqc_set_phy_cfg_data *cfg) 3697 { 3698 if (!pi || !caps || !cfg) 3699 return; 3700 3701 memset(cfg, 0, sizeof(*cfg)); 3702 cfg->phy_type_low = caps->phy_type_low; 3703 cfg->phy_type_high = caps->phy_type_high; 3704 cfg->caps = caps->caps; 3705 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3706 cfg->eee_cap = caps->eee_cap; 3707 cfg->eeer_value = caps->eeer_value; 3708 cfg->link_fec_opt = caps->link_fec_options; 3709 cfg->module_compliance_enforcement = 3710 caps->module_compliance_enforcement; 3711 } 3712 3713 /** 3714 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3715 * @pi: port information structure 3716 * @cfg: PHY configuration data to set FEC mode 3717 * @fec: FEC mode to configure 3718 */ 3719 int 3720 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3721 enum ice_fec_mode fec) 3722 { 3723 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3724 struct ice_hw *hw; 3725 int status; 3726 3727 if (!pi || !cfg) 3728 return -EINVAL; 3729 3730 hw = pi->hw; 3731 3732 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3733 if (!pcaps) 3734 return -ENOMEM; 3735 3736 status = ice_aq_get_phy_caps(pi, false, 3737 (ice_fw_supports_report_dflt_cfg(hw) ? 3738 ICE_AQC_REPORT_DFLT_CFG : 3739 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3740 if (status) 3741 goto out; 3742 3743 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3744 cfg->link_fec_opt = pcaps->link_fec_options; 3745 3746 switch (fec) { 3747 case ICE_FEC_BASER: 3748 /* Clear RS bits, and AND BASE-R ability 3749 * bits and OR request bits. 3750 */ 3751 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3752 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3753 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3754 ICE_AQC_PHY_FEC_25G_KR_REQ; 3755 break; 3756 case ICE_FEC_RS: 3757 /* Clear BASE-R bits, and AND RS ability 3758 * bits and OR request bits. 3759 */ 3760 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3761 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3762 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3763 break; 3764 case ICE_FEC_NONE: 3765 /* Clear all FEC option bits. */ 3766 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3767 break; 3768 case ICE_FEC_AUTO: 3769 /* AND auto FEC bit, and all caps bits. */ 3770 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3771 cfg->link_fec_opt |= pcaps->link_fec_options; 3772 break; 3773 default: 3774 status = -EINVAL; 3775 break; 3776 } 3777 3778 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3779 !ice_fw_supports_report_dflt_cfg(hw)) { 3780 struct ice_link_default_override_tlv tlv = { 0 }; 3781 3782 status = ice_get_link_default_override(&tlv, pi); 3783 if (status) 3784 goto out; 3785 3786 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3787 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3788 cfg->link_fec_opt = tlv.fec_options; 3789 } 3790 3791 out: 3792 return status; 3793 } 3794 3795 /** 3796 * ice_get_link_status - get status of the HW network link 3797 * @pi: port information structure 3798 * @link_up: pointer to bool (true/false = linkup/linkdown) 3799 * 3800 * Variable link_up is true if link is up, false if link is down. 3801 * The variable link_up is invalid if status is non zero. As a 3802 * result of this call, link status reporting becomes enabled 3803 */ 3804 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3805 { 3806 struct ice_phy_info *phy_info; 3807 int status = 0; 3808 3809 if (!pi || !link_up) 3810 return -EINVAL; 3811 3812 phy_info = &pi->phy; 3813 3814 if (phy_info->get_link_info) { 3815 status = ice_update_link_info(pi); 3816 3817 if (status) 3818 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3819 status); 3820 } 3821 3822 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3823 3824 return status; 3825 } 3826 3827 /** 3828 * ice_aq_set_link_restart_an 3829 * @pi: pointer to the port information structure 3830 * @ena_link: if true: enable link, if false: disable link 3831 * @cd: pointer to command details structure or NULL 3832 * 3833 * Sets up the link and restarts the Auto-Negotiation over the link. 3834 */ 3835 int 3836 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3837 struct ice_sq_cd *cd) 3838 { 3839 struct ice_aqc_restart_an *cmd; 3840 struct ice_aq_desc desc; 3841 3842 cmd = &desc.params.restart_an; 3843 3844 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3845 3846 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3847 cmd->lport_num = pi->lport; 3848 if (ena_link) 3849 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3850 else 3851 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3852 3853 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3854 } 3855 3856 /** 3857 * ice_aq_set_event_mask 3858 * @hw: pointer to the HW struct 3859 * @port_num: port number of the physical function 3860 * @mask: event mask to be set 3861 * @cd: pointer to command details structure or NULL 3862 * 3863 * Set event mask (0x0613) 3864 */ 3865 int 3866 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3867 struct ice_sq_cd *cd) 3868 { 3869 struct ice_aqc_set_event_mask *cmd; 3870 struct ice_aq_desc desc; 3871 3872 cmd = &desc.params.set_event_mask; 3873 3874 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3875 3876 cmd->lport_num = port_num; 3877 3878 cmd->event_mask = cpu_to_le16(mask); 3879 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3880 } 3881 3882 /** 3883 * ice_aq_set_mac_loopback 3884 * @hw: pointer to the HW struct 3885 * @ena_lpbk: Enable or Disable loopback 3886 * @cd: pointer to command details structure or NULL 3887 * 3888 * Enable/disable loopback on a given port 3889 */ 3890 int 3891 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3892 { 3893 struct ice_aqc_set_mac_lb *cmd; 3894 struct ice_aq_desc desc; 3895 3896 cmd = &desc.params.set_mac_lb; 3897 3898 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3899 if (ena_lpbk) 3900 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3901 3902 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3903 } 3904 3905 /** 3906 * ice_aq_set_port_id_led 3907 * @pi: pointer to the port information 3908 * @is_orig_mode: is this LED set to original mode (by the net-list) 3909 * @cd: pointer to command details structure or NULL 3910 * 3911 * Set LED value for the given port (0x06e9) 3912 */ 3913 int 3914 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3915 struct ice_sq_cd *cd) 3916 { 3917 struct ice_aqc_set_port_id_led *cmd; 3918 struct ice_hw *hw = pi->hw; 3919 struct ice_aq_desc desc; 3920 3921 cmd = &desc.params.set_port_id_led; 3922 3923 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3924 3925 if (is_orig_mode) 3926 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3927 else 3928 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3929 3930 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3931 } 3932 3933 /** 3934 * ice_aq_get_port_options 3935 * @hw: pointer to the HW struct 3936 * @options: buffer for the resultant port options 3937 * @option_count: input - size of the buffer in port options structures, 3938 * output - number of returned port options 3939 * @lport: logical port to call the command with (optional) 3940 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3941 * when PF owns more than 1 port it must be true 3942 * @active_option_idx: index of active port option in returned buffer 3943 * @active_option_valid: active option in returned buffer is valid 3944 * @pending_option_idx: index of pending port option in returned buffer 3945 * @pending_option_valid: pending option in returned buffer is valid 3946 * 3947 * Calls Get Port Options AQC (0x06ea) and verifies result. 3948 */ 3949 int 3950 ice_aq_get_port_options(struct ice_hw *hw, 3951 struct ice_aqc_get_port_options_elem *options, 3952 u8 *option_count, u8 lport, bool lport_valid, 3953 u8 *active_option_idx, bool *active_option_valid, 3954 u8 *pending_option_idx, bool *pending_option_valid) 3955 { 3956 struct ice_aqc_get_port_options *cmd; 3957 struct ice_aq_desc desc; 3958 int status; 3959 u8 i; 3960 3961 /* options buffer shall be able to hold max returned options */ 3962 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3963 return -EINVAL; 3964 3965 cmd = &desc.params.get_port_options; 3966 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3967 3968 if (lport_valid) 3969 cmd->lport_num = lport; 3970 cmd->lport_num_valid = lport_valid; 3971 3972 status = ice_aq_send_cmd(hw, &desc, options, 3973 *option_count * sizeof(*options), NULL); 3974 if (status) 3975 return status; 3976 3977 /* verify direct FW response & set output parameters */ 3978 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3979 cmd->port_options_count); 3980 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3981 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3982 cmd->port_options); 3983 if (*active_option_valid) { 3984 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3985 cmd->port_options); 3986 if (*active_option_idx > (*option_count - 1)) 3987 return -EIO; 3988 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3989 *active_option_idx); 3990 } 3991 3992 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3993 cmd->pending_port_option_status); 3994 if (*pending_option_valid) { 3995 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3996 cmd->pending_port_option_status); 3997 if (*pending_option_idx > (*option_count - 1)) 3998 return -EIO; 3999 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4000 *pending_option_idx); 4001 } 4002 4003 /* mask output options fields */ 4004 for (i = 0; i < *option_count; i++) { 4005 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4006 options[i].pmd); 4007 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4008 options[i].max_lane_speed); 4009 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4010 options[i].pmd, options[i].max_lane_speed); 4011 } 4012 4013 return 0; 4014 } 4015 4016 /** 4017 * ice_aq_set_port_option 4018 * @hw: pointer to the HW struct 4019 * @lport: logical port to call the command with 4020 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4021 * when PF owns more than 1 port it must be true 4022 * @new_option: new port option to be written 4023 * 4024 * Calls Set Port Options AQC (0x06eb). 4025 */ 4026 int 4027 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4028 u8 new_option) 4029 { 4030 struct ice_aqc_set_port_option *cmd; 4031 struct ice_aq_desc desc; 4032 4033 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4034 return -EINVAL; 4035 4036 cmd = &desc.params.set_port_option; 4037 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4038 4039 if (lport_valid) 4040 cmd->lport_num = lport; 4041 4042 cmd->lport_num_valid = lport_valid; 4043 cmd->selected_port_option = new_option; 4044 4045 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4046 } 4047 4048 /** 4049 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4050 * @hw: pointer to the hw struct 4051 * 4052 * Return: PHY lane number on success, negative error code otherwise. 4053 */ 4054 int ice_get_phy_lane_number(struct ice_hw *hw) 4055 { 4056 struct ice_aqc_get_port_options_elem *options; 4057 unsigned int lport = 0; 4058 unsigned int lane; 4059 int err; 4060 4061 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4062 if (!options) 4063 return -ENOMEM; 4064 4065 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4066 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4067 u8 speed, active_idx, pending_idx; 4068 bool active_valid, pending_valid; 4069 4070 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4071 true, &active_idx, &active_valid, 4072 &pending_idx, &pending_valid); 4073 if (err) 4074 goto err; 4075 4076 if (!active_valid) 4077 continue; 4078 4079 speed = options[active_idx].max_lane_speed; 4080 /* If we don't get speed for this lane, it's unoccupied */ 4081 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G) 4082 continue; 4083 4084 if (hw->pf_id == lport) { 4085 kfree(options); 4086 return lane; 4087 } 4088 4089 lport++; 4090 } 4091 4092 /* PHY lane not found */ 4093 err = -ENXIO; 4094 err: 4095 kfree(options); 4096 return err; 4097 } 4098 4099 /** 4100 * ice_aq_sff_eeprom 4101 * @hw: pointer to the HW struct 4102 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4103 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4104 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4105 * @page: QSFP page 4106 * @set_page: set or ignore the page 4107 * @data: pointer to data buffer to be read/written to the I2C device. 4108 * @length: 1-16 for read, 1 for write. 4109 * @write: 0 read, 1 for write. 4110 * @cd: pointer to command details structure or NULL 4111 * 4112 * Read/Write SFF EEPROM (0x06EE) 4113 */ 4114 int 4115 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4116 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4117 bool write, struct ice_sq_cd *cd) 4118 { 4119 struct ice_aqc_sff_eeprom *cmd; 4120 struct ice_aq_desc desc; 4121 u16 i2c_bus_addr; 4122 int status; 4123 4124 if (!data || (mem_addr & 0xff00)) 4125 return -EINVAL; 4126 4127 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4128 cmd = &desc.params.read_write_sff_param; 4129 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4130 cmd->lport_num = (u8)(lport & 0xff); 4131 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4132 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4133 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4134 if (write) 4135 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4136 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4137 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4138 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4139 4140 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4141 return status; 4142 } 4143 4144 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4145 { 4146 switch (type) { 4147 case ICE_LUT_VSI: 4148 return ICE_LUT_VSI_SIZE; 4149 case ICE_LUT_GLOBAL: 4150 return ICE_LUT_GLOBAL_SIZE; 4151 case ICE_LUT_PF: 4152 return ICE_LUT_PF_SIZE; 4153 } 4154 WARN_ONCE(1, "incorrect type passed"); 4155 return ICE_LUT_VSI_SIZE; 4156 } 4157 4158 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4159 { 4160 switch (size) { 4161 case ICE_LUT_VSI_SIZE: 4162 return ICE_AQC_LUT_SIZE_SMALL; 4163 case ICE_LUT_GLOBAL_SIZE: 4164 return ICE_AQC_LUT_SIZE_512; 4165 case ICE_LUT_PF_SIZE: 4166 return ICE_AQC_LUT_SIZE_2K; 4167 } 4168 WARN_ONCE(1, "incorrect size passed"); 4169 return 0; 4170 } 4171 4172 /** 4173 * __ice_aq_get_set_rss_lut 4174 * @hw: pointer to the hardware structure 4175 * @params: RSS LUT parameters 4176 * @set: set true to set the table, false to get the table 4177 * 4178 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4179 */ 4180 static int 4181 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4182 struct ice_aq_get_set_rss_lut_params *params, bool set) 4183 { 4184 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4185 enum ice_lut_type lut_type = params->lut_type; 4186 struct ice_aqc_get_set_rss_lut *desc_params; 4187 enum ice_aqc_lut_flags flags; 4188 enum ice_lut_size lut_size; 4189 struct ice_aq_desc desc; 4190 u8 *lut = params->lut; 4191 4192 4193 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4194 return -EINVAL; 4195 4196 lut_size = ice_lut_type_to_size(lut_type); 4197 if (lut_size > params->lut_size) 4198 return -EINVAL; 4199 else if (set && lut_size != params->lut_size) 4200 return -EINVAL; 4201 4202 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4203 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4204 if (set) 4205 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4206 4207 desc_params = &desc.params.get_set_rss_lut; 4208 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4209 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4210 4211 if (lut_type == ICE_LUT_GLOBAL) 4212 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4213 params->global_lut_id); 4214 4215 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4216 desc_params->flags = cpu_to_le16(flags); 4217 4218 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4219 } 4220 4221 /** 4222 * ice_aq_get_rss_lut 4223 * @hw: pointer to the hardware structure 4224 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4225 * 4226 * get the RSS lookup table, PF or VSI type 4227 */ 4228 int 4229 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4230 { 4231 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4232 } 4233 4234 /** 4235 * ice_aq_set_rss_lut 4236 * @hw: pointer to the hardware structure 4237 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4238 * 4239 * set the RSS lookup table, PF or VSI type 4240 */ 4241 int 4242 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4243 { 4244 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4245 } 4246 4247 /** 4248 * __ice_aq_get_set_rss_key 4249 * @hw: pointer to the HW struct 4250 * @vsi_id: VSI FW index 4251 * @key: pointer to key info struct 4252 * @set: set true to set the key, false to get the key 4253 * 4254 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4255 */ 4256 static int 4257 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4258 struct ice_aqc_get_set_rss_keys *key, bool set) 4259 { 4260 struct ice_aqc_get_set_rss_key *desc_params; 4261 u16 key_size = sizeof(*key); 4262 struct ice_aq_desc desc; 4263 4264 if (set) { 4265 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4266 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4267 } else { 4268 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4269 } 4270 4271 desc_params = &desc.params.get_set_rss_key; 4272 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4273 4274 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4275 } 4276 4277 /** 4278 * ice_aq_get_rss_key 4279 * @hw: pointer to the HW struct 4280 * @vsi_handle: software VSI handle 4281 * @key: pointer to key info struct 4282 * 4283 * get the RSS key per VSI 4284 */ 4285 int 4286 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4287 struct ice_aqc_get_set_rss_keys *key) 4288 { 4289 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4290 return -EINVAL; 4291 4292 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4293 key, false); 4294 } 4295 4296 /** 4297 * ice_aq_set_rss_key 4298 * @hw: pointer to the HW struct 4299 * @vsi_handle: software VSI handle 4300 * @keys: pointer to key info struct 4301 * 4302 * set the RSS key per VSI 4303 */ 4304 int 4305 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4306 struct ice_aqc_get_set_rss_keys *keys) 4307 { 4308 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4309 return -EINVAL; 4310 4311 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4312 keys, true); 4313 } 4314 4315 /** 4316 * ice_aq_add_lan_txq 4317 * @hw: pointer to the hardware structure 4318 * @num_qgrps: Number of added queue groups 4319 * @qg_list: list of queue groups to be added 4320 * @buf_size: size of buffer for indirect command 4321 * @cd: pointer to command details structure or NULL 4322 * 4323 * Add Tx LAN queue (0x0C30) 4324 * 4325 * NOTE: 4326 * Prior to calling add Tx LAN queue: 4327 * Initialize the following as part of the Tx queue context: 4328 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4329 * Cache profile and Packet shaper profile. 4330 * 4331 * After add Tx LAN queue AQ command is completed: 4332 * Interrupts should be associated with specific queues, 4333 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4334 * flow. 4335 */ 4336 static int 4337 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4338 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4339 struct ice_sq_cd *cd) 4340 { 4341 struct ice_aqc_add_tx_qgrp *list; 4342 struct ice_aqc_add_txqs *cmd; 4343 struct ice_aq_desc desc; 4344 u16 i, sum_size = 0; 4345 4346 cmd = &desc.params.add_txqs; 4347 4348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4349 4350 if (!qg_list) 4351 return -EINVAL; 4352 4353 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4354 return -EINVAL; 4355 4356 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4357 sum_size += struct_size(list, txqs, list->num_txqs); 4358 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4359 list->num_txqs); 4360 } 4361 4362 if (buf_size != sum_size) 4363 return -EINVAL; 4364 4365 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4366 4367 cmd->num_qgrps = num_qgrps; 4368 4369 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4370 } 4371 4372 /** 4373 * ice_aq_dis_lan_txq 4374 * @hw: pointer to the hardware structure 4375 * @num_qgrps: number of groups in the list 4376 * @qg_list: the list of groups to disable 4377 * @buf_size: the total size of the qg_list buffer in bytes 4378 * @rst_src: if called due to reset, specifies the reset source 4379 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4380 * @cd: pointer to command details structure or NULL 4381 * 4382 * Disable LAN Tx queue (0x0C31) 4383 */ 4384 static int 4385 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4386 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4387 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4388 struct ice_sq_cd *cd) 4389 { 4390 struct ice_aqc_dis_txq_item *item; 4391 struct ice_aqc_dis_txqs *cmd; 4392 struct ice_aq_desc desc; 4393 u16 vmvf_and_timeout; 4394 u16 i, sz = 0; 4395 int status; 4396 4397 cmd = &desc.params.dis_txqs; 4398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4399 4400 /* qg_list can be NULL only in VM/VF reset flow */ 4401 if (!qg_list && !rst_src) 4402 return -EINVAL; 4403 4404 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4405 return -EINVAL; 4406 4407 cmd->num_entries = num_qgrps; 4408 4409 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4410 4411 switch (rst_src) { 4412 case ICE_VM_RESET: 4413 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4414 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4415 break; 4416 case ICE_VF_RESET: 4417 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4418 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4419 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4420 ICE_AQC_Q_DIS_VMVF_NUM_M; 4421 break; 4422 case ICE_NO_RESET: 4423 default: 4424 break; 4425 } 4426 4427 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4428 4429 /* flush pipe on time out */ 4430 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4431 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4432 if (!qg_list) 4433 goto do_aq; 4434 4435 /* set RD bit to indicate that command buffer is provided by the driver 4436 * and it needs to be read by the firmware 4437 */ 4438 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4439 4440 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4441 u16 item_size = struct_size(item, q_id, item->num_qs); 4442 4443 /* If the num of queues is even, add 2 bytes of padding */ 4444 if ((item->num_qs % 2) == 0) 4445 item_size += 2; 4446 4447 sz += item_size; 4448 4449 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4450 } 4451 4452 if (buf_size != sz) 4453 return -EINVAL; 4454 4455 do_aq: 4456 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4457 if (status) { 4458 if (!qg_list) 4459 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4460 vmvf_num, hw->adminq.sq_last_status); 4461 else 4462 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4463 le16_to_cpu(qg_list[0].q_id[0]), 4464 hw->adminq.sq_last_status); 4465 } 4466 return status; 4467 } 4468 4469 /** 4470 * ice_aq_cfg_lan_txq 4471 * @hw: pointer to the hardware structure 4472 * @buf: buffer for command 4473 * @buf_size: size of buffer in bytes 4474 * @num_qs: number of queues being configured 4475 * @oldport: origination lport 4476 * @newport: destination lport 4477 * @cd: pointer to command details structure or NULL 4478 * 4479 * Move/Configure LAN Tx queue (0x0C32) 4480 * 4481 * There is a better AQ command to use for moving nodes, so only coding 4482 * this one for configuring the node. 4483 */ 4484 int 4485 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4486 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4487 struct ice_sq_cd *cd) 4488 { 4489 struct ice_aqc_cfg_txqs *cmd; 4490 struct ice_aq_desc desc; 4491 int status; 4492 4493 cmd = &desc.params.cfg_txqs; 4494 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4495 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4496 4497 if (!buf) 4498 return -EINVAL; 4499 4500 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4501 cmd->num_qs = num_qs; 4502 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4503 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4504 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4505 cmd->blocked_cgds = 0; 4506 4507 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4508 if (status) 4509 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4510 hw->adminq.sq_last_status); 4511 return status; 4512 } 4513 4514 /** 4515 * ice_aq_add_rdma_qsets 4516 * @hw: pointer to the hardware structure 4517 * @num_qset_grps: Number of RDMA Qset groups 4518 * @qset_list: list of Qset groups to be added 4519 * @buf_size: size of buffer for indirect command 4520 * @cd: pointer to command details structure or NULL 4521 * 4522 * Add Tx RDMA Qsets (0x0C33) 4523 */ 4524 static int 4525 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4526 struct ice_aqc_add_rdma_qset_data *qset_list, 4527 u16 buf_size, struct ice_sq_cd *cd) 4528 { 4529 struct ice_aqc_add_rdma_qset_data *list; 4530 struct ice_aqc_add_rdma_qset *cmd; 4531 struct ice_aq_desc desc; 4532 u16 i, sum_size = 0; 4533 4534 cmd = &desc.params.add_rdma_qset; 4535 4536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4537 4538 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4539 return -EINVAL; 4540 4541 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4542 u16 num_qsets = le16_to_cpu(list->num_qsets); 4543 4544 sum_size += struct_size(list, rdma_qsets, num_qsets); 4545 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4546 num_qsets); 4547 } 4548 4549 if (buf_size != sum_size) 4550 return -EINVAL; 4551 4552 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4553 4554 cmd->num_qset_grps = num_qset_grps; 4555 4556 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4557 } 4558 4559 /* End of FW Admin Queue command wrappers */ 4560 4561 /** 4562 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4563 * @hw: pointer to the HW struct 4564 * @vsi_handle: software VSI handle 4565 * @tc: TC number 4566 * @q_handle: software queue handle 4567 */ 4568 struct ice_q_ctx * 4569 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4570 { 4571 struct ice_vsi_ctx *vsi; 4572 struct ice_q_ctx *q_ctx; 4573 4574 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4575 if (!vsi) 4576 return NULL; 4577 if (q_handle >= vsi->num_lan_q_entries[tc]) 4578 return NULL; 4579 if (!vsi->lan_q_ctx[tc]) 4580 return NULL; 4581 q_ctx = vsi->lan_q_ctx[tc]; 4582 return &q_ctx[q_handle]; 4583 } 4584 4585 /** 4586 * ice_ena_vsi_txq 4587 * @pi: port information structure 4588 * @vsi_handle: software VSI handle 4589 * @tc: TC number 4590 * @q_handle: software queue handle 4591 * @num_qgrps: Number of added queue groups 4592 * @buf: list of queue groups to be added 4593 * @buf_size: size of buffer for indirect command 4594 * @cd: pointer to command details structure or NULL 4595 * 4596 * This function adds one LAN queue 4597 */ 4598 int 4599 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4600 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4601 struct ice_sq_cd *cd) 4602 { 4603 struct ice_aqc_txsched_elem_data node = { 0 }; 4604 struct ice_sched_node *parent; 4605 struct ice_q_ctx *q_ctx; 4606 struct ice_hw *hw; 4607 int status; 4608 4609 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4610 return -EIO; 4611 4612 if (num_qgrps > 1 || buf->num_txqs > 1) 4613 return -ENOSPC; 4614 4615 hw = pi->hw; 4616 4617 if (!ice_is_vsi_valid(hw, vsi_handle)) 4618 return -EINVAL; 4619 4620 mutex_lock(&pi->sched_lock); 4621 4622 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4623 if (!q_ctx) { 4624 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4625 q_handle); 4626 status = -EINVAL; 4627 goto ena_txq_exit; 4628 } 4629 4630 /* find a parent node */ 4631 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4632 ICE_SCHED_NODE_OWNER_LAN); 4633 if (!parent) { 4634 status = -EINVAL; 4635 goto ena_txq_exit; 4636 } 4637 4638 buf->parent_teid = parent->info.node_teid; 4639 node.parent_teid = parent->info.node_teid; 4640 /* Mark that the values in the "generic" section as valid. The default 4641 * value in the "generic" section is zero. This means that : 4642 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4643 * - 0 priority among siblings, indicated by Bit 1-3. 4644 * - WFQ, indicated by Bit 4. 4645 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4646 * Bit 5-6. 4647 * - Bit 7 is reserved. 4648 * Without setting the generic section as valid in valid_sections, the 4649 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4650 */ 4651 buf->txqs[0].info.valid_sections = 4652 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4653 ICE_AQC_ELEM_VALID_EIR; 4654 buf->txqs[0].info.generic = 0; 4655 buf->txqs[0].info.cir_bw.bw_profile_idx = 4656 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4657 buf->txqs[0].info.cir_bw.bw_alloc = 4658 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4659 buf->txqs[0].info.eir_bw.bw_profile_idx = 4660 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4661 buf->txqs[0].info.eir_bw.bw_alloc = 4662 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4663 4664 /* add the LAN queue */ 4665 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4666 if (status) { 4667 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4668 le16_to_cpu(buf->txqs[0].txq_id), 4669 hw->adminq.sq_last_status); 4670 goto ena_txq_exit; 4671 } 4672 4673 node.node_teid = buf->txqs[0].q_teid; 4674 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4675 q_ctx->q_handle = q_handle; 4676 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4677 4678 /* add a leaf node into scheduler tree queue layer */ 4679 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4680 if (!status) 4681 status = ice_sched_replay_q_bw(pi, q_ctx); 4682 4683 ena_txq_exit: 4684 mutex_unlock(&pi->sched_lock); 4685 return status; 4686 } 4687 4688 /** 4689 * ice_dis_vsi_txq 4690 * @pi: port information structure 4691 * @vsi_handle: software VSI handle 4692 * @tc: TC number 4693 * @num_queues: number of queues 4694 * @q_handles: pointer to software queue handle array 4695 * @q_ids: pointer to the q_id array 4696 * @q_teids: pointer to queue node teids 4697 * @rst_src: if called due to reset, specifies the reset source 4698 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4699 * @cd: pointer to command details structure or NULL 4700 * 4701 * This function removes queues and their corresponding nodes in SW DB 4702 */ 4703 int 4704 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4705 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4706 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4707 struct ice_sq_cd *cd) 4708 { 4709 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4710 u16 i, buf_size = __struct_size(qg_list); 4711 struct ice_q_ctx *q_ctx; 4712 int status = -ENOENT; 4713 struct ice_hw *hw; 4714 4715 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4716 return -EIO; 4717 4718 hw = pi->hw; 4719 4720 if (!num_queues) { 4721 /* if queue is disabled already yet the disable queue command 4722 * has to be sent to complete the VF reset, then call 4723 * ice_aq_dis_lan_txq without any queue information 4724 */ 4725 if (rst_src) 4726 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4727 vmvf_num, NULL); 4728 return -EIO; 4729 } 4730 4731 mutex_lock(&pi->sched_lock); 4732 4733 for (i = 0; i < num_queues; i++) { 4734 struct ice_sched_node *node; 4735 4736 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4737 if (!node) 4738 continue; 4739 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4740 if (!q_ctx) { 4741 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4742 q_handles[i]); 4743 continue; 4744 } 4745 if (q_ctx->q_handle != q_handles[i]) { 4746 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4747 q_ctx->q_handle, q_handles[i]); 4748 continue; 4749 } 4750 qg_list->parent_teid = node->info.parent_teid; 4751 qg_list->num_qs = 1; 4752 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4753 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4754 vmvf_num, cd); 4755 4756 if (status) 4757 break; 4758 ice_free_sched_node(pi, node); 4759 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4760 q_ctx->q_teid = ICE_INVAL_TEID; 4761 } 4762 mutex_unlock(&pi->sched_lock); 4763 return status; 4764 } 4765 4766 /** 4767 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4768 * @pi: port information structure 4769 * @vsi_handle: software VSI handle 4770 * @tc_bitmap: TC bitmap 4771 * @maxqs: max queues array per TC 4772 * @owner: LAN or RDMA 4773 * 4774 * This function adds/updates the VSI queues per TC. 4775 */ 4776 static int 4777 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4778 u16 *maxqs, u8 owner) 4779 { 4780 int status = 0; 4781 u8 i; 4782 4783 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4784 return -EIO; 4785 4786 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4787 return -EINVAL; 4788 4789 mutex_lock(&pi->sched_lock); 4790 4791 ice_for_each_traffic_class(i) { 4792 /* configuration is possible only if TC node is present */ 4793 if (!ice_sched_get_tc_node(pi, i)) 4794 continue; 4795 4796 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4797 ice_is_tc_ena(tc_bitmap, i)); 4798 if (status) 4799 break; 4800 } 4801 4802 mutex_unlock(&pi->sched_lock); 4803 return status; 4804 } 4805 4806 /** 4807 * ice_cfg_vsi_lan - configure VSI LAN queues 4808 * @pi: port information structure 4809 * @vsi_handle: software VSI handle 4810 * @tc_bitmap: TC bitmap 4811 * @max_lanqs: max LAN queues array per TC 4812 * 4813 * This function adds/updates the VSI LAN queues per TC. 4814 */ 4815 int 4816 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4817 u16 *max_lanqs) 4818 { 4819 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4820 ICE_SCHED_NODE_OWNER_LAN); 4821 } 4822 4823 /** 4824 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4825 * @pi: port information structure 4826 * @vsi_handle: software VSI handle 4827 * @tc_bitmap: TC bitmap 4828 * @max_rdmaqs: max RDMA queues array per TC 4829 * 4830 * This function adds/updates the VSI RDMA queues per TC. 4831 */ 4832 int 4833 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4834 u16 *max_rdmaqs) 4835 { 4836 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4837 ICE_SCHED_NODE_OWNER_RDMA); 4838 } 4839 4840 /** 4841 * ice_ena_vsi_rdma_qset 4842 * @pi: port information structure 4843 * @vsi_handle: software VSI handle 4844 * @tc: TC number 4845 * @rdma_qset: pointer to RDMA Qset 4846 * @num_qsets: number of RDMA Qsets 4847 * @qset_teid: pointer to Qset node TEIDs 4848 * 4849 * This function adds RDMA Qset 4850 */ 4851 int 4852 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4853 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4854 { 4855 struct ice_aqc_txsched_elem_data node = { 0 }; 4856 struct ice_aqc_add_rdma_qset_data *buf; 4857 struct ice_sched_node *parent; 4858 struct ice_hw *hw; 4859 u16 i, buf_size; 4860 int ret; 4861 4862 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4863 return -EIO; 4864 hw = pi->hw; 4865 4866 if (!ice_is_vsi_valid(hw, vsi_handle)) 4867 return -EINVAL; 4868 4869 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4870 buf = kzalloc(buf_size, GFP_KERNEL); 4871 if (!buf) 4872 return -ENOMEM; 4873 mutex_lock(&pi->sched_lock); 4874 4875 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4876 ICE_SCHED_NODE_OWNER_RDMA); 4877 if (!parent) { 4878 ret = -EINVAL; 4879 goto rdma_error_exit; 4880 } 4881 buf->parent_teid = parent->info.node_teid; 4882 node.parent_teid = parent->info.node_teid; 4883 4884 buf->num_qsets = cpu_to_le16(num_qsets); 4885 for (i = 0; i < num_qsets; i++) { 4886 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4887 buf->rdma_qsets[i].info.valid_sections = 4888 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4889 ICE_AQC_ELEM_VALID_EIR; 4890 buf->rdma_qsets[i].info.generic = 0; 4891 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4892 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4893 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4894 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4895 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4896 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4897 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4898 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4899 } 4900 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4901 if (ret) { 4902 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4903 goto rdma_error_exit; 4904 } 4905 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4906 for (i = 0; i < num_qsets; i++) { 4907 node.node_teid = buf->rdma_qsets[i].qset_teid; 4908 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4909 &node, NULL); 4910 if (ret) 4911 break; 4912 qset_teid[i] = le32_to_cpu(node.node_teid); 4913 } 4914 rdma_error_exit: 4915 mutex_unlock(&pi->sched_lock); 4916 kfree(buf); 4917 return ret; 4918 } 4919 4920 /** 4921 * ice_dis_vsi_rdma_qset - free RDMA resources 4922 * @pi: port_info struct 4923 * @count: number of RDMA Qsets to free 4924 * @qset_teid: TEID of Qset node 4925 * @q_id: list of queue IDs being disabled 4926 */ 4927 int 4928 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4929 u16 *q_id) 4930 { 4931 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4932 u16 qg_size = __struct_size(qg_list); 4933 struct ice_hw *hw; 4934 int status = 0; 4935 int i; 4936 4937 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4938 return -EIO; 4939 4940 hw = pi->hw; 4941 4942 mutex_lock(&pi->sched_lock); 4943 4944 for (i = 0; i < count; i++) { 4945 struct ice_sched_node *node; 4946 4947 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4948 if (!node) 4949 continue; 4950 4951 qg_list->parent_teid = node->info.parent_teid; 4952 qg_list->num_qs = 1; 4953 qg_list->q_id[0] = 4954 cpu_to_le16(q_id[i] | 4955 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4956 4957 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4958 ICE_NO_RESET, 0, NULL); 4959 if (status) 4960 break; 4961 4962 ice_free_sched_node(pi, node); 4963 } 4964 4965 mutex_unlock(&pi->sched_lock); 4966 return status; 4967 } 4968 4969 /** 4970 * ice_aq_get_cgu_abilities - get cgu abilities 4971 * @hw: pointer to the HW struct 4972 * @abilities: CGU abilities 4973 * 4974 * Get CGU abilities (0x0C61) 4975 * Return: 0 on success or negative value on failure. 4976 */ 4977 int 4978 ice_aq_get_cgu_abilities(struct ice_hw *hw, 4979 struct ice_aqc_get_cgu_abilities *abilities) 4980 { 4981 struct ice_aq_desc desc; 4982 4983 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 4984 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 4985 } 4986 4987 /** 4988 * ice_aq_set_input_pin_cfg - set input pin config 4989 * @hw: pointer to the HW struct 4990 * @input_idx: Input index 4991 * @flags1: Input flags 4992 * @flags2: Input flags 4993 * @freq: Frequency in Hz 4994 * @phase_delay: Delay in ps 4995 * 4996 * Set CGU input config (0x0C62) 4997 * Return: 0 on success or negative value on failure. 4998 */ 4999 int 5000 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5001 u32 freq, s32 phase_delay) 5002 { 5003 struct ice_aqc_set_cgu_input_config *cmd; 5004 struct ice_aq_desc desc; 5005 5006 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5007 cmd = &desc.params.set_cgu_input_config; 5008 cmd->input_idx = input_idx; 5009 cmd->flags1 = flags1; 5010 cmd->flags2 = flags2; 5011 cmd->freq = cpu_to_le32(freq); 5012 cmd->phase_delay = cpu_to_le32(phase_delay); 5013 5014 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5015 } 5016 5017 /** 5018 * ice_aq_get_input_pin_cfg - get input pin config 5019 * @hw: pointer to the HW struct 5020 * @input_idx: Input index 5021 * @status: Pin status 5022 * @type: Pin type 5023 * @flags1: Input flags 5024 * @flags2: Input flags 5025 * @freq: Frequency in Hz 5026 * @phase_delay: Delay in ps 5027 * 5028 * Get CGU input config (0x0C63) 5029 * Return: 0 on success or negative value on failure. 5030 */ 5031 int 5032 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5033 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5034 { 5035 struct ice_aqc_get_cgu_input_config *cmd; 5036 struct ice_aq_desc desc; 5037 int ret; 5038 5039 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5040 cmd = &desc.params.get_cgu_input_config; 5041 cmd->input_idx = input_idx; 5042 5043 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5044 if (!ret) { 5045 if (status) 5046 *status = cmd->status; 5047 if (type) 5048 *type = cmd->type; 5049 if (flags1) 5050 *flags1 = cmd->flags1; 5051 if (flags2) 5052 *flags2 = cmd->flags2; 5053 if (freq) 5054 *freq = le32_to_cpu(cmd->freq); 5055 if (phase_delay) 5056 *phase_delay = le32_to_cpu(cmd->phase_delay); 5057 } 5058 5059 return ret; 5060 } 5061 5062 /** 5063 * ice_aq_set_output_pin_cfg - set output pin config 5064 * @hw: pointer to the HW struct 5065 * @output_idx: Output index 5066 * @flags: Output flags 5067 * @src_sel: Index of DPLL block 5068 * @freq: Output frequency 5069 * @phase_delay: Output phase compensation 5070 * 5071 * Set CGU output config (0x0C64) 5072 * Return: 0 on success or negative value on failure. 5073 */ 5074 int 5075 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5076 u8 src_sel, u32 freq, s32 phase_delay) 5077 { 5078 struct ice_aqc_set_cgu_output_config *cmd; 5079 struct ice_aq_desc desc; 5080 5081 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5082 cmd = &desc.params.set_cgu_output_config; 5083 cmd->output_idx = output_idx; 5084 cmd->flags = flags; 5085 cmd->src_sel = src_sel; 5086 cmd->freq = cpu_to_le32(freq); 5087 cmd->phase_delay = cpu_to_le32(phase_delay); 5088 5089 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5090 } 5091 5092 /** 5093 * ice_aq_get_output_pin_cfg - get output pin config 5094 * @hw: pointer to the HW struct 5095 * @output_idx: Output index 5096 * @flags: Output flags 5097 * @src_sel: Internal DPLL source 5098 * @freq: Output frequency 5099 * @src_freq: Source frequency 5100 * 5101 * Get CGU output config (0x0C65) 5102 * Return: 0 on success or negative value on failure. 5103 */ 5104 int 5105 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5106 u8 *src_sel, u32 *freq, u32 *src_freq) 5107 { 5108 struct ice_aqc_get_cgu_output_config *cmd; 5109 struct ice_aq_desc desc; 5110 int ret; 5111 5112 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5113 cmd = &desc.params.get_cgu_output_config; 5114 cmd->output_idx = output_idx; 5115 5116 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5117 if (!ret) { 5118 if (flags) 5119 *flags = cmd->flags; 5120 if (src_sel) 5121 *src_sel = cmd->src_sel; 5122 if (freq) 5123 *freq = le32_to_cpu(cmd->freq); 5124 if (src_freq) 5125 *src_freq = le32_to_cpu(cmd->src_freq); 5126 } 5127 5128 return ret; 5129 } 5130 5131 /** 5132 * ice_aq_get_cgu_dpll_status - get dpll status 5133 * @hw: pointer to the HW struct 5134 * @dpll_num: DPLL index 5135 * @ref_state: Reference clock state 5136 * @config: current DPLL config 5137 * @dpll_state: current DPLL state 5138 * @phase_offset: Phase offset in ns 5139 * @eec_mode: EEC_mode 5140 * 5141 * Get CGU DPLL status (0x0C66) 5142 * Return: 0 on success or negative value on failure. 5143 */ 5144 int 5145 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5146 u8 *dpll_state, u8 *config, s64 *phase_offset, 5147 u8 *eec_mode) 5148 { 5149 struct ice_aqc_get_cgu_dpll_status *cmd; 5150 struct ice_aq_desc desc; 5151 int status; 5152 5153 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5154 cmd = &desc.params.get_cgu_dpll_status; 5155 cmd->dpll_num = dpll_num; 5156 5157 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5158 if (!status) { 5159 *ref_state = cmd->ref_state; 5160 *dpll_state = cmd->dpll_state; 5161 *config = cmd->config; 5162 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5163 *phase_offset <<= 32; 5164 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5165 *phase_offset = sign_extend64(*phase_offset, 47); 5166 *eec_mode = cmd->eec_mode; 5167 } 5168 5169 return status; 5170 } 5171 5172 /** 5173 * ice_aq_set_cgu_dpll_config - set dpll config 5174 * @hw: pointer to the HW struct 5175 * @dpll_num: DPLL index 5176 * @ref_state: Reference clock state 5177 * @config: DPLL config 5178 * @eec_mode: EEC mode 5179 * 5180 * Set CGU DPLL config (0x0C67) 5181 * Return: 0 on success or negative value on failure. 5182 */ 5183 int 5184 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5185 u8 config, u8 eec_mode) 5186 { 5187 struct ice_aqc_set_cgu_dpll_config *cmd; 5188 struct ice_aq_desc desc; 5189 5190 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5191 cmd = &desc.params.set_cgu_dpll_config; 5192 cmd->dpll_num = dpll_num; 5193 cmd->ref_state = ref_state; 5194 cmd->config = config; 5195 cmd->eec_mode = eec_mode; 5196 5197 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5198 } 5199 5200 /** 5201 * ice_aq_set_cgu_ref_prio - set input reference priority 5202 * @hw: pointer to the HW struct 5203 * @dpll_num: DPLL index 5204 * @ref_idx: Reference pin index 5205 * @ref_priority: Reference input priority 5206 * 5207 * Set CGU reference priority (0x0C68) 5208 * Return: 0 on success or negative value on failure. 5209 */ 5210 int 5211 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5212 u8 ref_priority) 5213 { 5214 struct ice_aqc_set_cgu_ref_prio *cmd; 5215 struct ice_aq_desc desc; 5216 5217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5218 cmd = &desc.params.set_cgu_ref_prio; 5219 cmd->dpll_num = dpll_num; 5220 cmd->ref_idx = ref_idx; 5221 cmd->ref_priority = ref_priority; 5222 5223 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5224 } 5225 5226 /** 5227 * ice_aq_get_cgu_ref_prio - get input reference priority 5228 * @hw: pointer to the HW struct 5229 * @dpll_num: DPLL index 5230 * @ref_idx: Reference pin index 5231 * @ref_prio: Reference input priority 5232 * 5233 * Get CGU reference priority (0x0C69) 5234 * Return: 0 on success or negative value on failure. 5235 */ 5236 int 5237 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5238 u8 *ref_prio) 5239 { 5240 struct ice_aqc_get_cgu_ref_prio *cmd; 5241 struct ice_aq_desc desc; 5242 int status; 5243 5244 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5245 cmd = &desc.params.get_cgu_ref_prio; 5246 cmd->dpll_num = dpll_num; 5247 cmd->ref_idx = ref_idx; 5248 5249 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5250 if (!status) 5251 *ref_prio = cmd->ref_priority; 5252 5253 return status; 5254 } 5255 5256 /** 5257 * ice_aq_get_cgu_info - get cgu info 5258 * @hw: pointer to the HW struct 5259 * @cgu_id: CGU ID 5260 * @cgu_cfg_ver: CGU config version 5261 * @cgu_fw_ver: CGU firmware version 5262 * 5263 * Get CGU info (0x0C6A) 5264 * Return: 0 on success or negative value on failure. 5265 */ 5266 int 5267 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5268 u32 *cgu_fw_ver) 5269 { 5270 struct ice_aqc_get_cgu_info *cmd; 5271 struct ice_aq_desc desc; 5272 int status; 5273 5274 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5275 cmd = &desc.params.get_cgu_info; 5276 5277 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5278 if (!status) { 5279 *cgu_id = le32_to_cpu(cmd->cgu_id); 5280 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5281 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5282 } 5283 5284 return status; 5285 } 5286 5287 /** 5288 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5289 * @hw: pointer to the HW struct 5290 * @phy_output: PHY reference clock output pin 5291 * @enable: GPIO state to be applied 5292 * @freq: PHY output frequency 5293 * 5294 * Set phy recovered clock as reference (0x0630) 5295 * Return: 0 on success or negative value on failure. 5296 */ 5297 int 5298 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5299 u32 *freq) 5300 { 5301 struct ice_aqc_set_phy_rec_clk_out *cmd; 5302 struct ice_aq_desc desc; 5303 int status; 5304 5305 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5306 cmd = &desc.params.set_phy_rec_clk_out; 5307 cmd->phy_output = phy_output; 5308 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5309 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5310 cmd->freq = cpu_to_le32(*freq); 5311 5312 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5313 if (!status) 5314 *freq = le32_to_cpu(cmd->freq); 5315 5316 return status; 5317 } 5318 5319 /** 5320 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5321 * @hw: pointer to the HW struct 5322 * @phy_output: PHY reference clock output pin 5323 * @port_num: Port number 5324 * @flags: PHY flags 5325 * @node_handle: PHY output frequency 5326 * 5327 * Get PHY recovered clock output info (0x0631) 5328 * Return: 0 on success or negative value on failure. 5329 */ 5330 int 5331 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5332 u8 *flags, u16 *node_handle) 5333 { 5334 struct ice_aqc_get_phy_rec_clk_out *cmd; 5335 struct ice_aq_desc desc; 5336 int status; 5337 5338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5339 cmd = &desc.params.get_phy_rec_clk_out; 5340 cmd->phy_output = *phy_output; 5341 5342 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5343 if (!status) { 5344 *phy_output = cmd->phy_output; 5345 if (port_num) 5346 *port_num = cmd->port_num; 5347 if (flags) 5348 *flags = cmd->flags; 5349 if (node_handle) 5350 *node_handle = le16_to_cpu(cmd->node_handle); 5351 } 5352 5353 return status; 5354 } 5355 5356 /** 5357 * ice_aq_get_sensor_reading 5358 * @hw: pointer to the HW struct 5359 * @data: pointer to data to be read from the sensor 5360 * 5361 * Get sensor reading (0x0632) 5362 */ 5363 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5364 struct ice_aqc_get_sensor_reading_resp *data) 5365 { 5366 struct ice_aqc_get_sensor_reading *cmd; 5367 struct ice_aq_desc desc; 5368 int status; 5369 5370 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5371 cmd = &desc.params.get_sensor_reading; 5372 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5373 #define ICE_INTERNAL_TEMP_SENSOR 0 5374 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5375 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5376 5377 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5378 if (!status) 5379 memcpy(data, &desc.params.get_sensor_reading_resp, 5380 sizeof(*data)); 5381 5382 return status; 5383 } 5384 5385 /** 5386 * ice_replay_pre_init - replay pre initialization 5387 * @hw: pointer to the HW struct 5388 * 5389 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5390 */ 5391 static int ice_replay_pre_init(struct ice_hw *hw) 5392 { 5393 struct ice_switch_info *sw = hw->switch_info; 5394 u8 i; 5395 5396 /* Delete old entries from replay filter list head if there is any */ 5397 ice_rm_all_sw_replay_rule_info(hw); 5398 /* In start of replay, move entries into replay_rules list, it 5399 * will allow adding rules entries back to filt_rules list, 5400 * which is operational list. 5401 */ 5402 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5403 list_replace_init(&sw->recp_list[i].filt_rules, 5404 &sw->recp_list[i].filt_replay_rules); 5405 ice_sched_replay_agg_vsi_preinit(hw); 5406 5407 return 0; 5408 } 5409 5410 /** 5411 * ice_replay_vsi - replay VSI configuration 5412 * @hw: pointer to the HW struct 5413 * @vsi_handle: driver VSI handle 5414 * 5415 * Restore all VSI configuration after reset. It is required to call this 5416 * function with main VSI first. 5417 */ 5418 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5419 { 5420 int status; 5421 5422 if (!ice_is_vsi_valid(hw, vsi_handle)) 5423 return -EINVAL; 5424 5425 /* Replay pre-initialization if there is any */ 5426 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5427 status = ice_replay_pre_init(hw); 5428 if (status) 5429 return status; 5430 } 5431 /* Replay per VSI all RSS configurations */ 5432 status = ice_replay_rss_cfg(hw, vsi_handle); 5433 if (status) 5434 return status; 5435 /* Replay per VSI all filters */ 5436 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5437 if (!status) 5438 status = ice_replay_vsi_agg(hw, vsi_handle); 5439 return status; 5440 } 5441 5442 /** 5443 * ice_replay_post - post replay configuration cleanup 5444 * @hw: pointer to the HW struct 5445 * 5446 * Post replay cleanup. 5447 */ 5448 void ice_replay_post(struct ice_hw *hw) 5449 { 5450 /* Delete old entries from replay filter list head */ 5451 ice_rm_all_sw_replay_rule_info(hw); 5452 ice_sched_replay_agg(hw); 5453 } 5454 5455 /** 5456 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5457 * @hw: ptr to the hardware info 5458 * @reg: offset of 64 bit HW register to read from 5459 * @prev_stat_loaded: bool to specify if previous stats are loaded 5460 * @prev_stat: ptr to previous loaded stat value 5461 * @cur_stat: ptr to current stat value 5462 */ 5463 void 5464 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5465 u64 *prev_stat, u64 *cur_stat) 5466 { 5467 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5468 5469 /* device stats are not reset at PFR, they likely will not be zeroed 5470 * when the driver starts. Thus, save the value from the first read 5471 * without adding to the statistic value so that we report stats which 5472 * count up from zero. 5473 */ 5474 if (!prev_stat_loaded) { 5475 *prev_stat = new_data; 5476 return; 5477 } 5478 5479 /* Calculate the difference between the new and old values, and then 5480 * add it to the software stat value. 5481 */ 5482 if (new_data >= *prev_stat) 5483 *cur_stat += new_data - *prev_stat; 5484 else 5485 /* to manage the potential roll-over */ 5486 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5487 5488 /* Update the previously stored value to prepare for next read */ 5489 *prev_stat = new_data; 5490 } 5491 5492 /** 5493 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5494 * @hw: ptr to the hardware info 5495 * @reg: offset of HW register to read from 5496 * @prev_stat_loaded: bool to specify if previous stats are loaded 5497 * @prev_stat: ptr to previous loaded stat value 5498 * @cur_stat: ptr to current stat value 5499 */ 5500 void 5501 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5502 u64 *prev_stat, u64 *cur_stat) 5503 { 5504 u32 new_data; 5505 5506 new_data = rd32(hw, reg); 5507 5508 /* device stats are not reset at PFR, they likely will not be zeroed 5509 * when the driver starts. Thus, save the value from the first read 5510 * without adding to the statistic value so that we report stats which 5511 * count up from zero. 5512 */ 5513 if (!prev_stat_loaded) { 5514 *prev_stat = new_data; 5515 return; 5516 } 5517 5518 /* Calculate the difference between the new and old values, and then 5519 * add it to the software stat value. 5520 */ 5521 if (new_data >= *prev_stat) 5522 *cur_stat += new_data - *prev_stat; 5523 else 5524 /* to manage the potential roll-over */ 5525 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5526 5527 /* Update the previously stored value to prepare for next read */ 5528 *prev_stat = new_data; 5529 } 5530 5531 /** 5532 * ice_sched_query_elem - query element information from HW 5533 * @hw: pointer to the HW struct 5534 * @node_teid: node TEID to be queried 5535 * @buf: buffer to element information 5536 * 5537 * This function queries HW element information 5538 */ 5539 int 5540 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5541 struct ice_aqc_txsched_elem_data *buf) 5542 { 5543 u16 buf_size, num_elem_ret = 0; 5544 int status; 5545 5546 buf_size = sizeof(*buf); 5547 memset(buf, 0, buf_size); 5548 buf->node_teid = cpu_to_le32(node_teid); 5549 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5550 NULL); 5551 if (status || num_elem_ret != 1) 5552 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5553 return status; 5554 } 5555 5556 /** 5557 * ice_aq_read_i2c 5558 * @hw: pointer to the hw struct 5559 * @topo_addr: topology address for a device to communicate with 5560 * @bus_addr: 7-bit I2C bus address 5561 * @addr: I2C memory address (I2C offset) with up to 16 bits 5562 * @params: I2C parameters: bit [7] - Repeated start, 5563 * bits [6:5] data offset size, 5564 * bit [4] - I2C address type, 5565 * bits [3:0] - data size to read (0-16 bytes) 5566 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5567 * @cd: pointer to command details structure or NULL 5568 * 5569 * Read I2C (0x06E2) 5570 */ 5571 int 5572 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5573 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5574 struct ice_sq_cd *cd) 5575 { 5576 struct ice_aq_desc desc = { 0 }; 5577 struct ice_aqc_i2c *cmd; 5578 u8 data_size; 5579 int status; 5580 5581 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5582 cmd = &desc.params.read_write_i2c; 5583 5584 if (!data) 5585 return -EINVAL; 5586 5587 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5588 5589 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5590 cmd->topo_addr = topo_addr; 5591 cmd->i2c_params = params; 5592 cmd->i2c_addr = addr; 5593 5594 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5595 if (!status) { 5596 struct ice_aqc_read_i2c_resp *resp; 5597 u8 i; 5598 5599 resp = &desc.params.read_i2c_resp; 5600 for (i = 0; i < data_size; i++) { 5601 *data = resp->i2c_data[i]; 5602 data++; 5603 } 5604 } 5605 5606 return status; 5607 } 5608 5609 /** 5610 * ice_aq_write_i2c 5611 * @hw: pointer to the hw struct 5612 * @topo_addr: topology address for a device to communicate with 5613 * @bus_addr: 7-bit I2C bus address 5614 * @addr: I2C memory address (I2C offset) with up to 16 bits 5615 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5616 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5617 * @cd: pointer to command details structure or NULL 5618 * 5619 * Write I2C (0x06E3) 5620 * 5621 * * Return: 5622 * * 0 - Successful write to the i2c device 5623 * * -EINVAL - Data size greater than 4 bytes 5624 * * -EIO - FW error 5625 */ 5626 int 5627 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5628 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5629 struct ice_sq_cd *cd) 5630 { 5631 struct ice_aq_desc desc = { 0 }; 5632 struct ice_aqc_i2c *cmd; 5633 u8 data_size; 5634 5635 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5636 cmd = &desc.params.read_write_i2c; 5637 5638 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5639 5640 /* data_size limited to 4 */ 5641 if (data_size > 4) 5642 return -EINVAL; 5643 5644 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5645 cmd->topo_addr = topo_addr; 5646 cmd->i2c_params = params; 5647 cmd->i2c_addr = addr; 5648 5649 memcpy(cmd->i2c_data, data, data_size); 5650 5651 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5652 } 5653 5654 /** 5655 * ice_get_pca9575_handle - find and return the PCA9575 controller 5656 * @hw: pointer to the hw struct 5657 * @pca9575_handle: GPIO controller's handle 5658 * 5659 * Find and return the GPIO controller's handle in the netlist. 5660 * When found - the value will be cached in the hw structure and following calls 5661 * will return cached value. 5662 * 5663 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5664 */ 5665 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5666 { 5667 struct ice_aqc_get_link_topo *cmd; 5668 struct ice_aq_desc desc; 5669 int err; 5670 u8 idx; 5671 5672 /* If handle was read previously return cached value */ 5673 if (hw->io_expander_handle) { 5674 *pca9575_handle = hw->io_expander_handle; 5675 return 0; 5676 } 5677 5678 #define SW_PCA9575_SFP_TOPO_IDX 2 5679 #define SW_PCA9575_QSFP_TOPO_IDX 1 5680 5681 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5682 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5683 idx = SW_PCA9575_SFP_TOPO_IDX; 5684 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5685 idx = SW_PCA9575_QSFP_TOPO_IDX; 5686 else 5687 return -ENXIO; 5688 5689 /* If handle was not detected read it from the netlist */ 5690 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5691 cmd = &desc.params.get_link_topo; 5692 cmd->addr.topo_params.node_type_ctx = 5693 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5694 cmd->addr.topo_params.index = idx; 5695 5696 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5697 if (err) 5698 return -ENXIO; 5699 5700 /* Verify if we found the right IO expander type */ 5701 if (desc.params.get_link_topo.node_part_num != 5702 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5703 return -ENXIO; 5704 5705 /* If present save the handle and return it */ 5706 hw->io_expander_handle = 5707 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5708 *pca9575_handle = hw->io_expander_handle; 5709 5710 return 0; 5711 } 5712 5713 /** 5714 * ice_read_pca9575_reg - read the register from the PCA9575 controller 5715 * @hw: pointer to the hw struct 5716 * @offset: GPIO controller register offset 5717 * @data: pointer to data to be read from the GPIO controller 5718 * 5719 * Return: 0 on success, negative error code otherwise. 5720 */ 5721 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5722 { 5723 struct ice_aqc_link_topo_addr link_topo; 5724 __le16 addr; 5725 u16 handle; 5726 int err; 5727 5728 memset(&link_topo, 0, sizeof(link_topo)); 5729 5730 err = ice_get_pca9575_handle(hw, &handle); 5731 if (err) 5732 return err; 5733 5734 link_topo.handle = cpu_to_le16(handle); 5735 link_topo.topo_params.node_type_ctx = 5736 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 5737 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 5738 5739 addr = cpu_to_le16((u16)offset); 5740 5741 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 5742 } 5743 5744 /** 5745 * ice_aq_set_gpio 5746 * @hw: pointer to the hw struct 5747 * @gpio_ctrl_handle: GPIO controller node handle 5748 * @pin_idx: IO Number of the GPIO that needs to be set 5749 * @value: SW provide IO value to set in the LSB 5750 * @cd: pointer to command details structure or NULL 5751 * 5752 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5753 */ 5754 int 5755 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5756 struct ice_sq_cd *cd) 5757 { 5758 struct ice_aqc_gpio *cmd; 5759 struct ice_aq_desc desc; 5760 5761 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5762 cmd = &desc.params.read_write_gpio; 5763 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5764 cmd->gpio_num = pin_idx; 5765 cmd->gpio_val = value ? 1 : 0; 5766 5767 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5768 } 5769 5770 /** 5771 * ice_aq_get_gpio 5772 * @hw: pointer to the hw struct 5773 * @gpio_ctrl_handle: GPIO controller node handle 5774 * @pin_idx: IO Number of the GPIO that needs to be set 5775 * @value: IO value read 5776 * @cd: pointer to command details structure or NULL 5777 * 5778 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5779 * the topology 5780 */ 5781 int 5782 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5783 bool *value, struct ice_sq_cd *cd) 5784 { 5785 struct ice_aqc_gpio *cmd; 5786 struct ice_aq_desc desc; 5787 int status; 5788 5789 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5790 cmd = &desc.params.read_write_gpio; 5791 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5792 cmd->gpio_num = pin_idx; 5793 5794 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5795 if (status) 5796 return status; 5797 5798 *value = !!cmd->gpio_val; 5799 return 0; 5800 } 5801 5802 /** 5803 * ice_is_fw_api_min_ver 5804 * @hw: pointer to the hardware structure 5805 * @maj: major version 5806 * @min: minor version 5807 * @patch: patch version 5808 * 5809 * Checks if the firmware API is minimum version 5810 */ 5811 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5812 { 5813 if (hw->api_maj_ver == maj) { 5814 if (hw->api_min_ver > min) 5815 return true; 5816 if (hw->api_min_ver == min && hw->api_patch >= patch) 5817 return true; 5818 } else if (hw->api_maj_ver > maj) { 5819 return true; 5820 } 5821 5822 return false; 5823 } 5824 5825 /** 5826 * ice_fw_supports_link_override 5827 * @hw: pointer to the hardware structure 5828 * 5829 * Checks if the firmware supports link override 5830 */ 5831 bool ice_fw_supports_link_override(struct ice_hw *hw) 5832 { 5833 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5834 ICE_FW_API_LINK_OVERRIDE_MIN, 5835 ICE_FW_API_LINK_OVERRIDE_PATCH); 5836 } 5837 5838 /** 5839 * ice_get_link_default_override 5840 * @ldo: pointer to the link default override struct 5841 * @pi: pointer to the port info struct 5842 * 5843 * Gets the link default override for a port 5844 */ 5845 int 5846 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5847 struct ice_port_info *pi) 5848 { 5849 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5850 struct ice_hw *hw = pi->hw; 5851 int status; 5852 5853 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5854 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5855 if (status) { 5856 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5857 return status; 5858 } 5859 5860 /* Each port has its own config; calculate for our port */ 5861 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5862 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5863 5864 /* link options first */ 5865 status = ice_read_sr_word(hw, tlv_start, &buf); 5866 if (status) { 5867 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5868 return status; 5869 } 5870 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 5871 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5872 ICE_LINK_OVERRIDE_PHY_CFG_S; 5873 5874 /* link PHY config */ 5875 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5876 status = ice_read_sr_word(hw, offset, &buf); 5877 if (status) { 5878 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5879 return status; 5880 } 5881 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5882 5883 /* PHY types low */ 5884 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5885 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5886 status = ice_read_sr_word(hw, (offset + i), &buf); 5887 if (status) { 5888 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5889 return status; 5890 } 5891 /* shift 16 bits at a time to fill 64 bits */ 5892 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5893 } 5894 5895 /* PHY types high */ 5896 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5897 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5898 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5899 status = ice_read_sr_word(hw, (offset + i), &buf); 5900 if (status) { 5901 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5902 return status; 5903 } 5904 /* shift 16 bits at a time to fill 64 bits */ 5905 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5906 } 5907 5908 return status; 5909 } 5910 5911 /** 5912 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5913 * @caps: get PHY capability data 5914 */ 5915 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5916 { 5917 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5918 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5919 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5920 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5921 return true; 5922 5923 return false; 5924 } 5925 5926 /** 5927 * ice_is_fw_health_report_supported - checks if firmware supports health events 5928 * @hw: pointer to the hardware structure 5929 * 5930 * Return: true if firmware supports health status reports, 5931 * false otherwise 5932 */ 5933 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 5934 { 5935 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 5936 ICE_FW_API_HEALTH_REPORT_MIN, 5937 ICE_FW_API_HEALTH_REPORT_PATCH); 5938 } 5939 5940 /** 5941 * ice_aq_set_health_status_cfg - Configure FW health events 5942 * @hw: pointer to the HW struct 5943 * @event_source: type of diagnostic events to enable 5944 * 5945 * Configure the health status event types that the firmware will send to this 5946 * PF. The supported event types are: PF-specific, all PFs, and global. 5947 * 5948 * Return: 0 on success, negative error code otherwise. 5949 */ 5950 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 5951 { 5952 struct ice_aqc_set_health_status_cfg *cmd; 5953 struct ice_aq_desc desc; 5954 5955 cmd = &desc.params.set_health_status_cfg; 5956 5957 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 5958 5959 cmd->event_source = event_source; 5960 5961 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5962 } 5963 5964 /** 5965 * ice_aq_set_lldp_mib - Set the LLDP MIB 5966 * @hw: pointer to the HW struct 5967 * @mib_type: Local, Remote or both Local and Remote MIBs 5968 * @buf: pointer to the caller-supplied buffer to store the MIB block 5969 * @buf_size: size of the buffer (in bytes) 5970 * @cd: pointer to command details structure or NULL 5971 * 5972 * Set the LLDP MIB. (0x0A08) 5973 */ 5974 int 5975 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5976 struct ice_sq_cd *cd) 5977 { 5978 struct ice_aqc_lldp_set_local_mib *cmd; 5979 struct ice_aq_desc desc; 5980 5981 cmd = &desc.params.lldp_set_mib; 5982 5983 if (buf_size == 0 || !buf) 5984 return -EINVAL; 5985 5986 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5987 5988 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5989 desc.datalen = cpu_to_le16(buf_size); 5990 5991 cmd->type = mib_type; 5992 cmd->length = cpu_to_le16(buf_size); 5993 5994 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5995 } 5996 5997 /** 5998 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5999 * @hw: pointer to HW struct 6000 */ 6001 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6002 { 6003 if (hw->mac_type != ICE_MAC_E810) 6004 return false; 6005 6006 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6007 ICE_FW_API_LLDP_FLTR_MIN, 6008 ICE_FW_API_LLDP_FLTR_PATCH); 6009 } 6010 6011 /** 6012 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6013 * @hw: pointer to HW struct 6014 * @vsi_num: absolute HW index for VSI 6015 * @add: boolean for if adding or removing a filter 6016 */ 6017 int 6018 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 6019 { 6020 struct ice_aqc_lldp_filter_ctrl *cmd; 6021 struct ice_aq_desc desc; 6022 6023 cmd = &desc.params.lldp_filter_ctrl; 6024 6025 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6026 6027 if (add) 6028 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6029 else 6030 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6031 6032 cmd->vsi_num = cpu_to_le16(vsi_num); 6033 6034 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6035 } 6036 6037 /** 6038 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6039 * @hw: pointer to HW struct 6040 */ 6041 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6042 { 6043 struct ice_aq_desc desc; 6044 6045 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6046 6047 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6048 } 6049 6050 /** 6051 * ice_fw_supports_report_dflt_cfg 6052 * @hw: pointer to the hardware structure 6053 * 6054 * Checks if the firmware supports report default configuration 6055 */ 6056 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6057 { 6058 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6059 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6060 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6061 } 6062 6063 /* each of the indexes into the following array match the speed of a return 6064 * value from the list of AQ returned speeds like the range: 6065 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6066 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6067 * array. The array is defined as 15 elements long because the link_speed 6068 * returned by the firmware is a 16 bit * value, but is indexed 6069 * by [fls(speed) - 1] 6070 */ 6071 static const u32 ice_aq_to_link_speed[] = { 6072 SPEED_10, /* BIT(0) */ 6073 SPEED_100, 6074 SPEED_1000, 6075 SPEED_2500, 6076 SPEED_5000, 6077 SPEED_10000, 6078 SPEED_20000, 6079 SPEED_25000, 6080 SPEED_40000, 6081 SPEED_50000, 6082 SPEED_100000, /* BIT(10) */ 6083 SPEED_200000, 6084 }; 6085 6086 /** 6087 * ice_get_link_speed - get integer speed from table 6088 * @index: array index from fls(aq speed) - 1 6089 * 6090 * Returns: u32 value containing integer speed 6091 */ 6092 u32 ice_get_link_speed(u16 index) 6093 { 6094 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6095 return 0; 6096 6097 return ice_aq_to_link_speed[index]; 6098 } 6099