1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 10 #define ICE_PF_RESET_WAIT_COUNT 300 11 #define ICE_MAX_NETLIST_SIZE 10 12 13 static const char * const ice_link_mode_str_low[] = { 14 [0] = "100BASE_TX", 15 [1] = "100M_SGMII", 16 [2] = "1000BASE_T", 17 [3] = "1000BASE_SX", 18 [4] = "1000BASE_LX", 19 [5] = "1000BASE_KX", 20 [6] = "1G_SGMII", 21 [7] = "2500BASE_T", 22 [8] = "2500BASE_X", 23 [9] = "2500BASE_KX", 24 [10] = "5GBASE_T", 25 [11] = "5GBASE_KR", 26 [12] = "10GBASE_T", 27 [13] = "10G_SFI_DA", 28 [14] = "10GBASE_SR", 29 [15] = "10GBASE_LR", 30 [16] = "10GBASE_KR_CR1", 31 [17] = "10G_SFI_AOC_ACC", 32 [18] = "10G_SFI_C2C", 33 [19] = "25GBASE_T", 34 [20] = "25GBASE_CR", 35 [21] = "25GBASE_CR_S", 36 [22] = "25GBASE_CR1", 37 [23] = "25GBASE_SR", 38 [24] = "25GBASE_LR", 39 [25] = "25GBASE_KR", 40 [26] = "25GBASE_KR_S", 41 [27] = "25GBASE_KR1", 42 [28] = "25G_AUI_AOC_ACC", 43 [29] = "25G_AUI_C2C", 44 [30] = "40GBASE_CR4", 45 [31] = "40GBASE_SR4", 46 [32] = "40GBASE_LR4", 47 [33] = "40GBASE_KR4", 48 [34] = "40G_XLAUI_AOC_ACC", 49 [35] = "40G_XLAUI", 50 [36] = "50GBASE_CR2", 51 [37] = "50GBASE_SR2", 52 [38] = "50GBASE_LR2", 53 [39] = "50GBASE_KR2", 54 [40] = "50G_LAUI2_AOC_ACC", 55 [41] = "50G_LAUI2", 56 [42] = "50G_AUI2_AOC_ACC", 57 [43] = "50G_AUI2", 58 [44] = "50GBASE_CP", 59 [45] = "50GBASE_SR", 60 [46] = "50GBASE_FR", 61 [47] = "50GBASE_LR", 62 [48] = "50GBASE_KR_PAM4", 63 [49] = "50G_AUI1_AOC_ACC", 64 [50] = "50G_AUI1", 65 [51] = "100GBASE_CR4", 66 [52] = "100GBASE_SR4", 67 [53] = "100GBASE_LR4", 68 [54] = "100GBASE_KR4", 69 [55] = "100G_CAUI4_AOC_ACC", 70 [56] = "100G_CAUI4", 71 [57] = "100G_AUI4_AOC_ACC", 72 [58] = "100G_AUI4", 73 [59] = "100GBASE_CR_PAM4", 74 [60] = "100GBASE_KR_PAM4", 75 [61] = "100GBASE_CP2", 76 [62] = "100GBASE_SR2", 77 [63] = "100GBASE_DR", 78 }; 79 80 static const char * const ice_link_mode_str_high[] = { 81 [0] = "100GBASE_KR2_PAM4", 82 [1] = "100G_CAUI2_AOC_ACC", 83 [2] = "100G_CAUI2", 84 [3] = "100G_AUI2_AOC_ACC", 85 [4] = "100G_AUI2", 86 }; 87 88 /** 89 * ice_dump_phy_type - helper function to dump phy_type 90 * @hw: pointer to the HW structure 91 * @low: 64 bit value for phy_type_low 92 * @high: 64 bit value for phy_type_high 93 * @prefix: prefix string to differentiate multiple dumps 94 */ 95 static void 96 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 97 { 98 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 99 100 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 101 if (low & BIT_ULL(i)) 102 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 103 prefix, i, ice_link_mode_str_low[i]); 104 } 105 106 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 107 108 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 109 if (high & BIT_ULL(i)) 110 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 111 prefix, i, ice_link_mode_str_high[i]); 112 } 113 } 114 115 /** 116 * ice_set_mac_type - Sets MAC type 117 * @hw: pointer to the HW structure 118 * 119 * This function sets the MAC type of the adapter based on the 120 * vendor ID and device ID stored in the HW structure. 121 */ 122 static int ice_set_mac_type(struct ice_hw *hw) 123 { 124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 125 return -ENODEV; 126 127 switch (hw->device_id) { 128 case ICE_DEV_ID_E810C_BACKPLANE: 129 case ICE_DEV_ID_E810C_QSFP: 130 case ICE_DEV_ID_E810C_SFP: 131 case ICE_DEV_ID_E810_XXV_BACKPLANE: 132 case ICE_DEV_ID_E810_XXV_QSFP: 133 case ICE_DEV_ID_E810_XXV_SFP: 134 hw->mac_type = ICE_MAC_E810; 135 break; 136 case ICE_DEV_ID_E823C_10G_BASE_T: 137 case ICE_DEV_ID_E823C_BACKPLANE: 138 case ICE_DEV_ID_E823C_QSFP: 139 case ICE_DEV_ID_E823C_SFP: 140 case ICE_DEV_ID_E823C_SGMII: 141 case ICE_DEV_ID_E822C_10G_BASE_T: 142 case ICE_DEV_ID_E822C_BACKPLANE: 143 case ICE_DEV_ID_E822C_QSFP: 144 case ICE_DEV_ID_E822C_SFP: 145 case ICE_DEV_ID_E822C_SGMII: 146 case ICE_DEV_ID_E822L_10G_BASE_T: 147 case ICE_DEV_ID_E822L_BACKPLANE: 148 case ICE_DEV_ID_E822L_SFP: 149 case ICE_DEV_ID_E822L_SGMII: 150 case ICE_DEV_ID_E823L_10G_BASE_T: 151 case ICE_DEV_ID_E823L_1GBE: 152 case ICE_DEV_ID_E823L_BACKPLANE: 153 case ICE_DEV_ID_E823L_QSFP: 154 case ICE_DEV_ID_E823L_SFP: 155 hw->mac_type = ICE_MAC_GENERIC; 156 break; 157 case ICE_DEV_ID_E825C_BACKPLANE: 158 case ICE_DEV_ID_E825C_QSFP: 159 case ICE_DEV_ID_E825C_SFP: 160 case ICE_DEV_ID_E825C_SGMII: 161 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 162 break; 163 case ICE_DEV_ID_E830_BACKPLANE: 164 case ICE_DEV_ID_E830_QSFP56: 165 case ICE_DEV_ID_E830_SFP: 166 case ICE_DEV_ID_E830_SFP_DD: 167 hw->mac_type = ICE_MAC_E830; 168 break; 169 default: 170 hw->mac_type = ICE_MAC_UNKNOWN; 171 break; 172 } 173 174 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 175 return 0; 176 } 177 178 /** 179 * ice_is_generic_mac - check if device's mac_type is generic 180 * @hw: pointer to the hardware structure 181 * 182 * Return: true if mac_type is generic (with SBQ support), false if not 183 */ 184 bool ice_is_generic_mac(struct ice_hw *hw) 185 { 186 return (hw->mac_type == ICE_MAC_GENERIC || 187 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 188 } 189 190 /** 191 * ice_is_e810 192 * @hw: pointer to the hardware structure 193 * 194 * returns true if the device is E810 based, false if not. 195 */ 196 bool ice_is_e810(struct ice_hw *hw) 197 { 198 return hw->mac_type == ICE_MAC_E810; 199 } 200 201 /** 202 * ice_is_e810t 203 * @hw: pointer to the hardware structure 204 * 205 * returns true if the device is E810T based, false if not. 206 */ 207 bool ice_is_e810t(struct ice_hw *hw) 208 { 209 switch (hw->device_id) { 210 case ICE_DEV_ID_E810C_SFP: 211 switch (hw->subsystem_device_id) { 212 case ICE_SUBDEV_ID_E810T: 213 case ICE_SUBDEV_ID_E810T2: 214 case ICE_SUBDEV_ID_E810T3: 215 case ICE_SUBDEV_ID_E810T4: 216 case ICE_SUBDEV_ID_E810T6: 217 case ICE_SUBDEV_ID_E810T7: 218 return true; 219 } 220 break; 221 case ICE_DEV_ID_E810C_QSFP: 222 switch (hw->subsystem_device_id) { 223 case ICE_SUBDEV_ID_E810T2: 224 case ICE_SUBDEV_ID_E810T3: 225 case ICE_SUBDEV_ID_E810T5: 226 return true; 227 } 228 break; 229 default: 230 break; 231 } 232 233 return false; 234 } 235 236 /** 237 * ice_is_e823 238 * @hw: pointer to the hardware structure 239 * 240 * returns true if the device is E823-L or E823-C based, false if not. 241 */ 242 bool ice_is_e823(struct ice_hw *hw) 243 { 244 switch (hw->device_id) { 245 case ICE_DEV_ID_E823L_BACKPLANE: 246 case ICE_DEV_ID_E823L_SFP: 247 case ICE_DEV_ID_E823L_10G_BASE_T: 248 case ICE_DEV_ID_E823L_1GBE: 249 case ICE_DEV_ID_E823L_QSFP: 250 case ICE_DEV_ID_E823C_BACKPLANE: 251 case ICE_DEV_ID_E823C_QSFP: 252 case ICE_DEV_ID_E823C_SFP: 253 case ICE_DEV_ID_E823C_10G_BASE_T: 254 case ICE_DEV_ID_E823C_SGMII: 255 return true; 256 default: 257 return false; 258 } 259 } 260 261 /** 262 * ice_is_e825c - Check if a device is E825C family device 263 * @hw: pointer to the hardware structure 264 * 265 * Return: true if the device is E825-C based, false if not. 266 */ 267 bool ice_is_e825c(struct ice_hw *hw) 268 { 269 switch (hw->device_id) { 270 case ICE_DEV_ID_E825C_BACKPLANE: 271 case ICE_DEV_ID_E825C_QSFP: 272 case ICE_DEV_ID_E825C_SFP: 273 case ICE_DEV_ID_E825C_SGMII: 274 return true; 275 default: 276 return false; 277 } 278 } 279 280 /** 281 * ice_clear_pf_cfg - Clear PF configuration 282 * @hw: pointer to the hardware structure 283 * 284 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 285 * configuration, flow director filters, etc.). 286 */ 287 int ice_clear_pf_cfg(struct ice_hw *hw) 288 { 289 struct ice_aq_desc desc; 290 291 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 292 293 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 294 } 295 296 /** 297 * ice_aq_manage_mac_read - manage MAC address read command 298 * @hw: pointer to the HW struct 299 * @buf: a virtual buffer to hold the manage MAC read response 300 * @buf_size: Size of the virtual buffer 301 * @cd: pointer to command details structure or NULL 302 * 303 * This function is used to return per PF station MAC address (0x0107). 304 * NOTE: Upon successful completion of this command, MAC address information 305 * is returned in user specified buffer. Please interpret user specified 306 * buffer as "manage_mac_read" response. 307 * Response such as various MAC addresses are stored in HW struct (port.mac) 308 * ice_discover_dev_caps is expected to be called before this function is 309 * called. 310 */ 311 static int 312 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 313 struct ice_sq_cd *cd) 314 { 315 struct ice_aqc_manage_mac_read_resp *resp; 316 struct ice_aqc_manage_mac_read *cmd; 317 struct ice_aq_desc desc; 318 int status; 319 u16 flags; 320 u8 i; 321 322 cmd = &desc.params.mac_read; 323 324 if (buf_size < sizeof(*resp)) 325 return -EINVAL; 326 327 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 328 329 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 330 if (status) 331 return status; 332 333 resp = buf; 334 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 335 336 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 337 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 338 return -EIO; 339 } 340 341 /* A single port can report up to two (LAN and WoL) addresses */ 342 for (i = 0; i < cmd->num_addr; i++) 343 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 344 ether_addr_copy(hw->port_info->mac.lan_addr, 345 resp[i].mac_addr); 346 ether_addr_copy(hw->port_info->mac.perm_addr, 347 resp[i].mac_addr); 348 break; 349 } 350 351 return 0; 352 } 353 354 /** 355 * ice_aq_get_phy_caps - returns PHY capabilities 356 * @pi: port information structure 357 * @qual_mods: report qualified modules 358 * @report_mode: report mode capabilities 359 * @pcaps: structure for PHY capabilities to be filled 360 * @cd: pointer to command details structure or NULL 361 * 362 * Returns the various PHY capabilities supported on the Port (0x0600) 363 */ 364 int 365 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 366 struct ice_aqc_get_phy_caps_data *pcaps, 367 struct ice_sq_cd *cd) 368 { 369 struct ice_aqc_get_phy_caps *cmd; 370 u16 pcaps_size = sizeof(*pcaps); 371 struct ice_aq_desc desc; 372 const char *prefix; 373 struct ice_hw *hw; 374 int status; 375 376 cmd = &desc.params.get_phy; 377 378 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 379 return -EINVAL; 380 hw = pi->hw; 381 382 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 383 !ice_fw_supports_report_dflt_cfg(hw)) 384 return -EINVAL; 385 386 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 387 388 if (qual_mods) 389 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 390 391 cmd->param0 |= cpu_to_le16(report_mode); 392 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 393 394 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 395 396 switch (report_mode) { 397 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 398 prefix = "phy_caps_media"; 399 break; 400 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 401 prefix = "phy_caps_no_media"; 402 break; 403 case ICE_AQC_REPORT_ACTIVE_CFG: 404 prefix = "phy_caps_active"; 405 break; 406 case ICE_AQC_REPORT_DFLT_CFG: 407 prefix = "phy_caps_default"; 408 break; 409 default: 410 prefix = "phy_caps_invalid"; 411 } 412 413 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 414 le64_to_cpu(pcaps->phy_type_high), prefix); 415 416 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 417 prefix, report_mode); 418 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 419 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 420 pcaps->low_power_ctrl_an); 421 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 422 pcaps->eee_cap); 423 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 424 pcaps->eeer_value); 425 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 426 pcaps->link_fec_options); 427 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 428 prefix, pcaps->module_compliance_enforcement); 429 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 430 prefix, pcaps->extended_compliance_code); 431 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 432 pcaps->module_type[0]); 433 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 434 pcaps->module_type[1]); 435 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 436 pcaps->module_type[2]); 437 438 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 439 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 440 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 441 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 442 sizeof(pi->phy.link_info.module_type)); 443 } 444 445 return status; 446 } 447 448 /** 449 * ice_aq_get_link_topo_handle - get link topology node return status 450 * @pi: port information structure 451 * @node_type: requested node type 452 * @cd: pointer to command details structure or NULL 453 * 454 * Get link topology node return status for specified node type (0x06E0) 455 * 456 * Node type cage can be used to determine if cage is present. If AQC 457 * returns error (ENOENT), then no cage present. If no cage present, then 458 * connection type is backplane or BASE-T. 459 */ 460 static int 461 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 462 struct ice_sq_cd *cd) 463 { 464 struct ice_aqc_get_link_topo *cmd; 465 struct ice_aq_desc desc; 466 467 cmd = &desc.params.get_link_topo; 468 469 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 470 471 cmd->addr.topo_params.node_type_ctx = 472 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 473 ICE_AQC_LINK_TOPO_NODE_CTX_S); 474 475 /* set node type */ 476 cmd->addr.topo_params.node_type_ctx |= 477 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 478 479 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 480 } 481 482 /** 483 * ice_aq_get_netlist_node 484 * @hw: pointer to the hw struct 485 * @cmd: get_link_topo AQ structure 486 * @node_part_number: output node part number if node found 487 * @node_handle: output node handle parameter if node found 488 * 489 * Get netlist node handle. 490 */ 491 int 492 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 493 u8 *node_part_number, u16 *node_handle) 494 { 495 struct ice_aq_desc desc; 496 497 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 498 desc.params.get_link_topo = *cmd; 499 500 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 501 return -EINTR; 502 503 if (node_handle) 504 *node_handle = 505 le16_to_cpu(desc.params.get_link_topo.addr.handle); 506 if (node_part_number) 507 *node_part_number = desc.params.get_link_topo.node_part_num; 508 509 return 0; 510 } 511 512 /** 513 * ice_find_netlist_node 514 * @hw: pointer to the hw struct 515 * @node_type_ctx: type of netlist node to look for 516 * @node_part_number: node part number to look for 517 * @node_handle: output parameter if node found - optional 518 * 519 * Scan the netlist for a node handle of the given node type and part number. 520 * 521 * If node_handle is non-NULL it will be modified on function exit. It is only 522 * valid if the function returns zero, and should be ignored on any non-zero 523 * return value. 524 * 525 * Returns: 0 if the node is found, -ENOENT if no handle was found, and 526 * a negative error code on failure to access the AQ. 527 */ 528 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, 529 u8 node_part_number, u16 *node_handle) 530 { 531 u8 idx; 532 533 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 534 struct ice_aqc_get_link_topo cmd = {}; 535 u8 rec_node_part_number; 536 int status; 537 538 cmd.addr.topo_params.node_type_ctx = 539 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, 540 node_type_ctx); 541 cmd.addr.topo_params.index = idx; 542 543 status = ice_aq_get_netlist_node(hw, &cmd, 544 &rec_node_part_number, 545 node_handle); 546 if (status) 547 return status; 548 549 if (rec_node_part_number == node_part_number) 550 return 0; 551 } 552 553 return -ENOENT; 554 } 555 556 /** 557 * ice_is_media_cage_present 558 * @pi: port information structure 559 * 560 * Returns true if media cage is present, else false. If no cage, then 561 * media type is backplane or BASE-T. 562 */ 563 static bool ice_is_media_cage_present(struct ice_port_info *pi) 564 { 565 /* Node type cage can be used to determine if cage is present. If AQC 566 * returns error (ENOENT), then no cage present. If no cage present then 567 * connection type is backplane or BASE-T. 568 */ 569 return !ice_aq_get_link_topo_handle(pi, 570 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 571 NULL); 572 } 573 574 /** 575 * ice_get_media_type - Gets media type 576 * @pi: port information structure 577 */ 578 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 579 { 580 struct ice_link_status *hw_link_info; 581 582 if (!pi) 583 return ICE_MEDIA_UNKNOWN; 584 585 hw_link_info = &pi->phy.link_info; 586 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 587 /* If more than one media type is selected, report unknown */ 588 return ICE_MEDIA_UNKNOWN; 589 590 if (hw_link_info->phy_type_low) { 591 /* 1G SGMII is a special case where some DA cable PHYs 592 * may show this as an option when it really shouldn't 593 * be since SGMII is meant to be between a MAC and a PHY 594 * in a backplane. Try to detect this case and handle it 595 */ 596 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 597 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 598 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 599 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 600 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 601 return ICE_MEDIA_DA; 602 603 switch (hw_link_info->phy_type_low) { 604 case ICE_PHY_TYPE_LOW_1000BASE_SX: 605 case ICE_PHY_TYPE_LOW_1000BASE_LX: 606 case ICE_PHY_TYPE_LOW_10GBASE_SR: 607 case ICE_PHY_TYPE_LOW_10GBASE_LR: 608 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 609 case ICE_PHY_TYPE_LOW_25GBASE_SR: 610 case ICE_PHY_TYPE_LOW_25GBASE_LR: 611 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 612 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 613 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 614 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 615 case ICE_PHY_TYPE_LOW_50GBASE_SR: 616 case ICE_PHY_TYPE_LOW_50GBASE_FR: 617 case ICE_PHY_TYPE_LOW_50GBASE_LR: 618 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 619 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 620 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 621 case ICE_PHY_TYPE_LOW_100GBASE_DR: 622 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 623 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 624 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 625 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 626 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 627 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 628 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 629 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 630 return ICE_MEDIA_FIBER; 631 case ICE_PHY_TYPE_LOW_100BASE_TX: 632 case ICE_PHY_TYPE_LOW_1000BASE_T: 633 case ICE_PHY_TYPE_LOW_2500BASE_T: 634 case ICE_PHY_TYPE_LOW_5GBASE_T: 635 case ICE_PHY_TYPE_LOW_10GBASE_T: 636 case ICE_PHY_TYPE_LOW_25GBASE_T: 637 return ICE_MEDIA_BASET; 638 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 639 case ICE_PHY_TYPE_LOW_25GBASE_CR: 640 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 641 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 642 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 643 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 644 case ICE_PHY_TYPE_LOW_50GBASE_CP: 645 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 646 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 647 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 648 return ICE_MEDIA_DA; 649 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 650 case ICE_PHY_TYPE_LOW_40G_XLAUI: 651 case ICE_PHY_TYPE_LOW_50G_LAUI2: 652 case ICE_PHY_TYPE_LOW_50G_AUI2: 653 case ICE_PHY_TYPE_LOW_50G_AUI1: 654 case ICE_PHY_TYPE_LOW_100G_AUI4: 655 case ICE_PHY_TYPE_LOW_100G_CAUI4: 656 if (ice_is_media_cage_present(pi)) 657 return ICE_MEDIA_DA; 658 fallthrough; 659 case ICE_PHY_TYPE_LOW_1000BASE_KX: 660 case ICE_PHY_TYPE_LOW_2500BASE_KX: 661 case ICE_PHY_TYPE_LOW_2500BASE_X: 662 case ICE_PHY_TYPE_LOW_5GBASE_KR: 663 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 664 case ICE_PHY_TYPE_LOW_25GBASE_KR: 665 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 666 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 667 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 668 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 669 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 670 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 671 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 672 return ICE_MEDIA_BACKPLANE; 673 } 674 } else { 675 switch (hw_link_info->phy_type_high) { 676 case ICE_PHY_TYPE_HIGH_100G_AUI2: 677 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 678 if (ice_is_media_cage_present(pi)) 679 return ICE_MEDIA_DA; 680 fallthrough; 681 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 682 return ICE_MEDIA_BACKPLANE; 683 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 684 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 685 return ICE_MEDIA_FIBER; 686 } 687 } 688 return ICE_MEDIA_UNKNOWN; 689 } 690 691 /** 692 * ice_get_link_status_datalen 693 * @hw: pointer to the HW struct 694 * 695 * Returns datalength for the Get Link Status AQ command, which is bigger for 696 * newer adapter families handled by ice driver. 697 */ 698 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 699 { 700 switch (hw->mac_type) { 701 case ICE_MAC_E830: 702 return ICE_AQC_LS_DATA_SIZE_V2; 703 case ICE_MAC_E810: 704 default: 705 return ICE_AQC_LS_DATA_SIZE_V1; 706 } 707 } 708 709 /** 710 * ice_aq_get_link_info 711 * @pi: port information structure 712 * @ena_lse: enable/disable LinkStatusEvent reporting 713 * @link: pointer to link status structure - optional 714 * @cd: pointer to command details structure or NULL 715 * 716 * Get Link Status (0x607). Returns the link status of the adapter. 717 */ 718 int 719 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 720 struct ice_link_status *link, struct ice_sq_cd *cd) 721 { 722 struct ice_aqc_get_link_status_data link_data = { 0 }; 723 struct ice_aqc_get_link_status *resp; 724 struct ice_link_status *li_old, *li; 725 enum ice_media_type *hw_media_type; 726 struct ice_fc_info *hw_fc_info; 727 bool tx_pause, rx_pause; 728 struct ice_aq_desc desc; 729 struct ice_hw *hw; 730 u16 cmd_flags; 731 int status; 732 733 if (!pi) 734 return -EINVAL; 735 hw = pi->hw; 736 li_old = &pi->phy.link_info_old; 737 hw_media_type = &pi->phy.media_type; 738 li = &pi->phy.link_info; 739 hw_fc_info = &pi->fc; 740 741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 742 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 743 resp = &desc.params.get_link_status; 744 resp->cmd_flags = cpu_to_le16(cmd_flags); 745 resp->lport_num = pi->lport; 746 747 status = ice_aq_send_cmd(hw, &desc, &link_data, 748 ice_get_link_status_datalen(hw), cd); 749 if (status) 750 return status; 751 752 /* save off old link status information */ 753 *li_old = *li; 754 755 /* update current link status information */ 756 li->link_speed = le16_to_cpu(link_data.link_speed); 757 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 758 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 759 *hw_media_type = ice_get_media_type(pi); 760 li->link_info = link_data.link_info; 761 li->link_cfg_err = link_data.link_cfg_err; 762 li->an_info = link_data.an_info; 763 li->ext_info = link_data.ext_info; 764 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 765 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 766 li->topo_media_conflict = link_data.topo_media_conflict; 767 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 768 ICE_AQ_CFG_PACING_TYPE_M); 769 770 /* update fc info */ 771 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 772 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 773 if (tx_pause && rx_pause) 774 hw_fc_info->current_mode = ICE_FC_FULL; 775 else if (tx_pause) 776 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 777 else if (rx_pause) 778 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 779 else 780 hw_fc_info->current_mode = ICE_FC_NONE; 781 782 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 783 784 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 785 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 786 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 787 (unsigned long long)li->phy_type_low); 788 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 789 (unsigned long long)li->phy_type_high); 790 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 791 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 792 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 793 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 794 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 795 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 796 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 797 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 798 li->max_frame_size); 799 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 800 801 /* save link status information */ 802 if (link) 803 *link = *li; 804 805 /* flag cleared so calling functions don't call AQ again */ 806 pi->phy.get_link_info = false; 807 808 return 0; 809 } 810 811 /** 812 * ice_fill_tx_timer_and_fc_thresh 813 * @hw: pointer to the HW struct 814 * @cmd: pointer to MAC cfg structure 815 * 816 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 817 * descriptor 818 */ 819 static void 820 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 821 struct ice_aqc_set_mac_cfg *cmd) 822 { 823 u32 val, fc_thres_m; 824 825 /* We read back the transmit timer and FC threshold value of 826 * LFC. Thus, we will use index = 827 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 828 * 829 * Also, because we are operating on transmit timer and FC 830 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 831 */ 832 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 833 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 834 835 if (hw->mac_type == ICE_MAC_E830) { 836 /* Retrieve the transmit timer */ 837 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 838 cmd->tx_tmr_value = 839 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 840 841 /* Retrieve the fc threshold */ 842 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 843 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 844 } else { 845 /* Retrieve the transmit timer */ 846 val = rd32(hw, 847 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 848 cmd->tx_tmr_value = 849 le16_encode_bits(val, 850 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 851 852 /* Retrieve the fc threshold */ 853 val = rd32(hw, 854 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 855 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 856 } 857 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 858 } 859 860 /** 861 * ice_aq_set_mac_cfg 862 * @hw: pointer to the HW struct 863 * @max_frame_size: Maximum Frame Size to be supported 864 * @cd: pointer to command details structure or NULL 865 * 866 * Set MAC configuration (0x0603) 867 */ 868 int 869 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 870 { 871 struct ice_aqc_set_mac_cfg *cmd; 872 struct ice_aq_desc desc; 873 874 cmd = &desc.params.set_mac_cfg; 875 876 if (max_frame_size == 0) 877 return -EINVAL; 878 879 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 880 881 cmd->max_frame_size = cpu_to_le16(max_frame_size); 882 883 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 884 885 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 886 } 887 888 /** 889 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 890 * @hw: pointer to the HW struct 891 */ 892 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 893 { 894 struct ice_switch_info *sw; 895 int status; 896 897 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 898 sizeof(*hw->switch_info), GFP_KERNEL); 899 sw = hw->switch_info; 900 901 if (!sw) 902 return -ENOMEM; 903 904 INIT_LIST_HEAD(&sw->vsi_list_map_head); 905 sw->prof_res_bm_init = 0; 906 907 status = ice_init_def_sw_recp(hw); 908 if (status) { 909 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 910 return status; 911 } 912 return 0; 913 } 914 915 /** 916 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 917 * @hw: pointer to the HW struct 918 */ 919 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 920 { 921 struct ice_switch_info *sw = hw->switch_info; 922 struct ice_vsi_list_map_info *v_pos_map; 923 struct ice_vsi_list_map_info *v_tmp_map; 924 struct ice_sw_recipe *recps; 925 u8 i; 926 927 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 928 list_entry) { 929 list_del(&v_pos_map->list_entry); 930 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 931 } 932 recps = sw->recp_list; 933 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 934 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 935 936 recps[i].root_rid = i; 937 list_for_each_entry_safe(rg_entry, tmprg_entry, 938 &recps[i].rg_list, l_entry) { 939 list_del(&rg_entry->l_entry); 940 devm_kfree(ice_hw_to_dev(hw), rg_entry); 941 } 942 943 if (recps[i].adv_rule) { 944 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 945 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 946 947 mutex_destroy(&recps[i].filt_rule_lock); 948 list_for_each_entry_safe(lst_itr, tmp_entry, 949 &recps[i].filt_rules, 950 list_entry) { 951 list_del(&lst_itr->list_entry); 952 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 953 devm_kfree(ice_hw_to_dev(hw), lst_itr); 954 } 955 } else { 956 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 957 958 mutex_destroy(&recps[i].filt_rule_lock); 959 list_for_each_entry_safe(lst_itr, tmp_entry, 960 &recps[i].filt_rules, 961 list_entry) { 962 list_del(&lst_itr->list_entry); 963 devm_kfree(ice_hw_to_dev(hw), lst_itr); 964 } 965 } 966 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 967 } 968 ice_rm_all_sw_replay_rule_info(hw); 969 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 970 devm_kfree(ice_hw_to_dev(hw), sw); 971 } 972 973 /** 974 * ice_get_itr_intrl_gran 975 * @hw: pointer to the HW struct 976 * 977 * Determines the ITR/INTRL granularities based on the maximum aggregate 978 * bandwidth according to the device's configuration during power-on. 979 */ 980 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 981 { 982 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 983 rd32(hw, GL_PWR_MODE_CTL)); 984 985 switch (max_agg_bw) { 986 case ICE_MAX_AGG_BW_200G: 987 case ICE_MAX_AGG_BW_100G: 988 case ICE_MAX_AGG_BW_50G: 989 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 990 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 991 break; 992 case ICE_MAX_AGG_BW_25G: 993 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 994 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 995 break; 996 } 997 } 998 999 /** 1000 * ice_init_hw - main hardware initialization routine 1001 * @hw: pointer to the hardware structure 1002 */ 1003 int ice_init_hw(struct ice_hw *hw) 1004 { 1005 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1006 void *mac_buf __free(kfree) = NULL; 1007 u16 mac_buf_len; 1008 int status; 1009 1010 /* Set MAC type based on DeviceID */ 1011 status = ice_set_mac_type(hw); 1012 if (status) 1013 return status; 1014 1015 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1016 1017 status = ice_reset(hw, ICE_RESET_PFR); 1018 if (status) 1019 return status; 1020 1021 ice_get_itr_intrl_gran(hw); 1022 1023 status = ice_create_all_ctrlq(hw); 1024 if (status) 1025 goto err_unroll_cqinit; 1026 1027 status = ice_fwlog_init(hw); 1028 if (status) 1029 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1030 status); 1031 1032 status = ice_clear_pf_cfg(hw); 1033 if (status) 1034 goto err_unroll_cqinit; 1035 1036 /* Set bit to enable Flow Director filters */ 1037 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1038 INIT_LIST_HEAD(&hw->fdir_list_head); 1039 1040 ice_clear_pxe_mode(hw); 1041 1042 status = ice_init_nvm(hw); 1043 if (status) 1044 goto err_unroll_cqinit; 1045 1046 status = ice_get_caps(hw); 1047 if (status) 1048 goto err_unroll_cqinit; 1049 1050 if (!hw->port_info) 1051 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1052 sizeof(*hw->port_info), 1053 GFP_KERNEL); 1054 if (!hw->port_info) { 1055 status = -ENOMEM; 1056 goto err_unroll_cqinit; 1057 } 1058 1059 /* set the back pointer to HW */ 1060 hw->port_info->hw = hw; 1061 1062 /* Initialize port_info struct with switch configuration data */ 1063 status = ice_get_initial_sw_cfg(hw); 1064 if (status) 1065 goto err_unroll_alloc; 1066 1067 hw->evb_veb = true; 1068 1069 /* init xarray for identifying scheduling nodes uniquely */ 1070 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1071 1072 /* Query the allocated resources for Tx scheduler */ 1073 status = ice_sched_query_res_alloc(hw); 1074 if (status) { 1075 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1076 goto err_unroll_alloc; 1077 } 1078 ice_sched_get_psm_clk_freq(hw); 1079 1080 /* Initialize port_info struct with scheduler data */ 1081 status = ice_sched_init_port(hw->port_info); 1082 if (status) 1083 goto err_unroll_sched; 1084 1085 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1086 if (!pcaps) { 1087 status = -ENOMEM; 1088 goto err_unroll_sched; 1089 } 1090 1091 /* Initialize port_info struct with PHY capabilities */ 1092 status = ice_aq_get_phy_caps(hw->port_info, false, 1093 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1094 NULL); 1095 if (status) 1096 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1097 status); 1098 1099 /* Initialize port_info struct with link information */ 1100 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1101 if (status) 1102 goto err_unroll_sched; 1103 1104 /* need a valid SW entry point to build a Tx tree */ 1105 if (!hw->sw_entry_point_layer) { 1106 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1107 status = -EIO; 1108 goto err_unroll_sched; 1109 } 1110 INIT_LIST_HEAD(&hw->agg_list); 1111 /* Initialize max burst size */ 1112 if (!hw->max_burst_size) 1113 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1114 1115 status = ice_init_fltr_mgmt_struct(hw); 1116 if (status) 1117 goto err_unroll_sched; 1118 1119 /* Get MAC information */ 1120 /* A single port can report up to two (LAN and WoL) addresses */ 1121 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1122 GFP_KERNEL); 1123 if (!mac_buf) { 1124 status = -ENOMEM; 1125 goto err_unroll_fltr_mgmt_struct; 1126 } 1127 1128 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1129 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1130 1131 if (status) 1132 goto err_unroll_fltr_mgmt_struct; 1133 /* enable jumbo frame support at MAC level */ 1134 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1135 if (status) 1136 goto err_unroll_fltr_mgmt_struct; 1137 /* Obtain counter base index which would be used by flow director */ 1138 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1139 if (status) 1140 goto err_unroll_fltr_mgmt_struct; 1141 status = ice_init_hw_tbls(hw); 1142 if (status) 1143 goto err_unroll_fltr_mgmt_struct; 1144 mutex_init(&hw->tnl_lock); 1145 ice_init_chk_recipe_reuse_support(hw); 1146 1147 return 0; 1148 1149 err_unroll_fltr_mgmt_struct: 1150 ice_cleanup_fltr_mgmt_struct(hw); 1151 err_unroll_sched: 1152 ice_sched_cleanup_all(hw); 1153 err_unroll_alloc: 1154 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1155 err_unroll_cqinit: 1156 ice_destroy_all_ctrlq(hw); 1157 return status; 1158 } 1159 1160 /** 1161 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1162 * @hw: pointer to the hardware structure 1163 * 1164 * This should be called only during nominal operation, not as a result of 1165 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1166 * applicable initializations if it fails for any reason. 1167 */ 1168 void ice_deinit_hw(struct ice_hw *hw) 1169 { 1170 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1171 ice_cleanup_fltr_mgmt_struct(hw); 1172 1173 ice_sched_cleanup_all(hw); 1174 ice_sched_clear_agg(hw); 1175 ice_free_seg(hw); 1176 ice_free_hw_tbls(hw); 1177 mutex_destroy(&hw->tnl_lock); 1178 1179 ice_fwlog_deinit(hw); 1180 ice_destroy_all_ctrlq(hw); 1181 1182 /* Clear VSI contexts if not already cleared */ 1183 ice_clear_all_vsi_ctx(hw); 1184 } 1185 1186 /** 1187 * ice_check_reset - Check to see if a global reset is complete 1188 * @hw: pointer to the hardware structure 1189 */ 1190 int ice_check_reset(struct ice_hw *hw) 1191 { 1192 u32 cnt, reg = 0, grst_timeout, uld_mask; 1193 1194 /* Poll for Device Active state in case a recent CORER, GLOBR, 1195 * or EMPR has occurred. The grst delay value is in 100ms units. 1196 * Add 1sec for outstanding AQ commands that can take a long time. 1197 */ 1198 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1199 rd32(hw, GLGEN_RSTCTL)) + 10; 1200 1201 for (cnt = 0; cnt < grst_timeout; cnt++) { 1202 mdelay(100); 1203 reg = rd32(hw, GLGEN_RSTAT); 1204 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1205 break; 1206 } 1207 1208 if (cnt == grst_timeout) { 1209 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1210 return -EIO; 1211 } 1212 1213 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1214 GLNVM_ULD_PCIER_DONE_1_M |\ 1215 GLNVM_ULD_CORER_DONE_M |\ 1216 GLNVM_ULD_GLOBR_DONE_M |\ 1217 GLNVM_ULD_POR_DONE_M |\ 1218 GLNVM_ULD_POR_DONE_1_M |\ 1219 GLNVM_ULD_PCIER_DONE_2_M) 1220 1221 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1222 GLNVM_ULD_PE_DONE_M : 0); 1223 1224 /* Device is Active; check Global Reset processes are done */ 1225 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1226 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1227 if (reg == uld_mask) { 1228 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1229 break; 1230 } 1231 mdelay(10); 1232 } 1233 1234 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1235 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1236 reg); 1237 return -EIO; 1238 } 1239 1240 return 0; 1241 } 1242 1243 /** 1244 * ice_pf_reset - Reset the PF 1245 * @hw: pointer to the hardware structure 1246 * 1247 * If a global reset has been triggered, this function checks 1248 * for its completion and then issues the PF reset 1249 */ 1250 static int ice_pf_reset(struct ice_hw *hw) 1251 { 1252 u32 cnt, reg; 1253 1254 /* If at function entry a global reset was already in progress, i.e. 1255 * state is not 'device active' or any of the reset done bits are not 1256 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1257 * global reset is done. 1258 */ 1259 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1260 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1261 /* poll on global reset currently in progress until done */ 1262 if (ice_check_reset(hw)) 1263 return -EIO; 1264 1265 return 0; 1266 } 1267 1268 /* Reset the PF */ 1269 reg = rd32(hw, PFGEN_CTRL); 1270 1271 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1272 1273 /* Wait for the PFR to complete. The wait time is the global config lock 1274 * timeout plus the PFR timeout which will account for a possible reset 1275 * that is occurring during a download package operation. 1276 */ 1277 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1278 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1279 reg = rd32(hw, PFGEN_CTRL); 1280 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1281 break; 1282 1283 mdelay(1); 1284 } 1285 1286 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1287 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1288 return -EIO; 1289 } 1290 1291 return 0; 1292 } 1293 1294 /** 1295 * ice_reset - Perform different types of reset 1296 * @hw: pointer to the hardware structure 1297 * @req: reset request 1298 * 1299 * This function triggers a reset as specified by the req parameter. 1300 * 1301 * Note: 1302 * If anything other than a PF reset is triggered, PXE mode is restored. 1303 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1304 * interface has been restored in the rebuild flow. 1305 */ 1306 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1307 { 1308 u32 val = 0; 1309 1310 switch (req) { 1311 case ICE_RESET_PFR: 1312 return ice_pf_reset(hw); 1313 case ICE_RESET_CORER: 1314 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1315 val = GLGEN_RTRIG_CORER_M; 1316 break; 1317 case ICE_RESET_GLOBR: 1318 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1319 val = GLGEN_RTRIG_GLOBR_M; 1320 break; 1321 default: 1322 return -EINVAL; 1323 } 1324 1325 val |= rd32(hw, GLGEN_RTRIG); 1326 wr32(hw, GLGEN_RTRIG, val); 1327 ice_flush(hw); 1328 1329 /* wait for the FW to be ready */ 1330 return ice_check_reset(hw); 1331 } 1332 1333 /** 1334 * ice_copy_rxq_ctx_to_hw 1335 * @hw: pointer to the hardware structure 1336 * @ice_rxq_ctx: pointer to the rxq context 1337 * @rxq_index: the index of the Rx queue 1338 * 1339 * Copies rxq context from dense structure to HW register space 1340 */ 1341 static int 1342 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1343 { 1344 u8 i; 1345 1346 if (!ice_rxq_ctx) 1347 return -EINVAL; 1348 1349 if (rxq_index > QRX_CTRL_MAX_INDEX) 1350 return -EINVAL; 1351 1352 /* Copy each dword separately to HW */ 1353 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1354 wr32(hw, QRX_CONTEXT(i, rxq_index), 1355 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1356 1357 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1358 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1359 } 1360 1361 return 0; 1362 } 1363 1364 /* LAN Rx Queue Context */ 1365 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1366 /* Field Width LSB */ 1367 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1368 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1369 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1370 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1371 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1372 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1373 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1374 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1375 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1376 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1377 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1378 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1379 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1380 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1381 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1382 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1383 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1384 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1385 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1386 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1387 { 0 } 1388 }; 1389 1390 /** 1391 * ice_write_rxq_ctx 1392 * @hw: pointer to the hardware structure 1393 * @rlan_ctx: pointer to the rxq context 1394 * @rxq_index: the index of the Rx queue 1395 * 1396 * Converts rxq context from sparse to dense structure and then writes 1397 * it to HW register space and enables the hardware to prefetch descriptors 1398 * instead of only fetching them on demand 1399 */ 1400 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1401 u32 rxq_index) 1402 { 1403 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1404 1405 if (!rlan_ctx) 1406 return -EINVAL; 1407 1408 rlan_ctx->prefena = 1; 1409 1410 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1411 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1412 } 1413 1414 /* LAN Tx Queue Context */ 1415 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1416 /* Field Width LSB */ 1417 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1418 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1419 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1420 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1421 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1422 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1423 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1424 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1425 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1426 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1427 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1428 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1429 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1430 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1431 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1432 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1433 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1434 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1435 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1436 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1437 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1438 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1439 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1440 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1441 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1442 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1443 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1444 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1445 { 0 } 1446 }; 1447 1448 /* Sideband Queue command wrappers */ 1449 1450 /** 1451 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1452 * @hw: pointer to the HW struct 1453 * @desc: descriptor describing the command 1454 * @buf: buffer to use for indirect commands (NULL for direct commands) 1455 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1456 * @cd: pointer to command details structure 1457 */ 1458 static int 1459 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1460 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1461 { 1462 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1463 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1464 } 1465 1466 /** 1467 * ice_sbq_rw_reg - Fill Sideband Queue command 1468 * @hw: pointer to the HW struct 1469 * @in: message info to be filled in descriptor 1470 */ 1471 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1472 { 1473 struct ice_sbq_cmd_desc desc = {0}; 1474 struct ice_sbq_msg_req msg = {0}; 1475 u16 msg_len; 1476 int status; 1477 1478 msg_len = sizeof(msg); 1479 1480 msg.dest_dev = in->dest_dev; 1481 msg.opcode = in->opcode; 1482 msg.flags = ICE_SBQ_MSG_FLAGS; 1483 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1484 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1485 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1486 1487 if (in->opcode) 1488 msg.data = cpu_to_le32(in->data); 1489 else 1490 /* data read comes back in completion, so shorten the struct by 1491 * sizeof(msg.data) 1492 */ 1493 msg_len -= sizeof(msg.data); 1494 1495 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1496 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1497 desc.param0.cmd_len = cpu_to_le16(msg_len); 1498 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1499 if (!status && !in->opcode) 1500 in->data = le32_to_cpu 1501 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1502 return status; 1503 } 1504 1505 /* FW Admin Queue command wrappers */ 1506 1507 /* Software lock/mutex that is meant to be held while the Global Config Lock 1508 * in firmware is acquired by the software to prevent most (but not all) types 1509 * of AQ commands from being sent to FW 1510 */ 1511 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1512 1513 /** 1514 * ice_should_retry_sq_send_cmd 1515 * @opcode: AQ opcode 1516 * 1517 * Decide if we should retry the send command routine for the ATQ, depending 1518 * on the opcode. 1519 */ 1520 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1521 { 1522 switch (opcode) { 1523 case ice_aqc_opc_get_link_topo: 1524 case ice_aqc_opc_lldp_stop: 1525 case ice_aqc_opc_lldp_start: 1526 case ice_aqc_opc_lldp_filter_ctrl: 1527 return true; 1528 } 1529 1530 return false; 1531 } 1532 1533 /** 1534 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1535 * @hw: pointer to the HW struct 1536 * @cq: pointer to the specific Control queue 1537 * @desc: prefilled descriptor describing the command 1538 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1539 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1540 * @cd: pointer to command details structure 1541 * 1542 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1543 * Queue if the EBUSY AQ error is returned. 1544 */ 1545 static int 1546 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1547 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1548 struct ice_sq_cd *cd) 1549 { 1550 struct ice_aq_desc desc_cpy; 1551 bool is_cmd_for_retry; 1552 u8 idx = 0; 1553 u16 opcode; 1554 int status; 1555 1556 opcode = le16_to_cpu(desc->opcode); 1557 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1558 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1559 1560 if (is_cmd_for_retry) { 1561 /* All retryable cmds are direct, without buf. */ 1562 WARN_ON(buf); 1563 1564 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1565 } 1566 1567 do { 1568 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1569 1570 if (!is_cmd_for_retry || !status || 1571 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1572 break; 1573 1574 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1575 1576 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1577 1578 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1579 1580 return status; 1581 } 1582 1583 /** 1584 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1585 * @hw: pointer to the HW struct 1586 * @desc: descriptor describing the command 1587 * @buf: buffer to use for indirect commands (NULL for direct commands) 1588 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1589 * @cd: pointer to command details structure 1590 * 1591 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1592 */ 1593 int 1594 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1595 u16 buf_size, struct ice_sq_cd *cd) 1596 { 1597 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1598 bool lock_acquired = false; 1599 int status; 1600 1601 /* When a package download is in process (i.e. when the firmware's 1602 * Global Configuration Lock resource is held), only the Download 1603 * Package, Get Version, Get Package Info List, Upload Section, 1604 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1605 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1606 * Recipes to Profile Association, and Release Resource (with resource 1607 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1608 * must block until the package download completes and the Global Config 1609 * Lock is released. See also ice_acquire_global_cfg_lock(). 1610 */ 1611 switch (le16_to_cpu(desc->opcode)) { 1612 case ice_aqc_opc_download_pkg: 1613 case ice_aqc_opc_get_pkg_info_list: 1614 case ice_aqc_opc_get_ver: 1615 case ice_aqc_opc_upload_section: 1616 case ice_aqc_opc_update_pkg: 1617 case ice_aqc_opc_set_port_params: 1618 case ice_aqc_opc_get_vlan_mode_parameters: 1619 case ice_aqc_opc_set_vlan_mode_parameters: 1620 case ice_aqc_opc_set_tx_topo: 1621 case ice_aqc_opc_get_tx_topo: 1622 case ice_aqc_opc_add_recipe: 1623 case ice_aqc_opc_recipe_to_profile: 1624 case ice_aqc_opc_get_recipe: 1625 case ice_aqc_opc_get_recipe_to_profile: 1626 break; 1627 case ice_aqc_opc_release_res: 1628 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1629 break; 1630 fallthrough; 1631 default: 1632 mutex_lock(&ice_global_cfg_lock_sw); 1633 lock_acquired = true; 1634 break; 1635 } 1636 1637 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1638 if (lock_acquired) 1639 mutex_unlock(&ice_global_cfg_lock_sw); 1640 1641 return status; 1642 } 1643 1644 /** 1645 * ice_aq_get_fw_ver 1646 * @hw: pointer to the HW struct 1647 * @cd: pointer to command details structure or NULL 1648 * 1649 * Get the firmware version (0x0001) from the admin queue commands 1650 */ 1651 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1652 { 1653 struct ice_aqc_get_ver *resp; 1654 struct ice_aq_desc desc; 1655 int status; 1656 1657 resp = &desc.params.get_ver; 1658 1659 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1660 1661 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1662 1663 if (!status) { 1664 hw->fw_branch = resp->fw_branch; 1665 hw->fw_maj_ver = resp->fw_major; 1666 hw->fw_min_ver = resp->fw_minor; 1667 hw->fw_patch = resp->fw_patch; 1668 hw->fw_build = le32_to_cpu(resp->fw_build); 1669 hw->api_branch = resp->api_branch; 1670 hw->api_maj_ver = resp->api_major; 1671 hw->api_min_ver = resp->api_minor; 1672 hw->api_patch = resp->api_patch; 1673 } 1674 1675 return status; 1676 } 1677 1678 /** 1679 * ice_aq_send_driver_ver 1680 * @hw: pointer to the HW struct 1681 * @dv: driver's major, minor version 1682 * @cd: pointer to command details structure or NULL 1683 * 1684 * Send the driver version (0x0002) to the firmware 1685 */ 1686 int 1687 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1688 struct ice_sq_cd *cd) 1689 { 1690 struct ice_aqc_driver_ver *cmd; 1691 struct ice_aq_desc desc; 1692 u16 len; 1693 1694 cmd = &desc.params.driver_ver; 1695 1696 if (!dv) 1697 return -EINVAL; 1698 1699 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1700 1701 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1702 cmd->major_ver = dv->major_ver; 1703 cmd->minor_ver = dv->minor_ver; 1704 cmd->build_ver = dv->build_ver; 1705 cmd->subbuild_ver = dv->subbuild_ver; 1706 1707 len = 0; 1708 while (len < sizeof(dv->driver_string) && 1709 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1710 len++; 1711 1712 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1713 } 1714 1715 /** 1716 * ice_aq_q_shutdown 1717 * @hw: pointer to the HW struct 1718 * @unloading: is the driver unloading itself 1719 * 1720 * Tell the Firmware that we're shutting down the AdminQ and whether 1721 * or not the driver is unloading as well (0x0003). 1722 */ 1723 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1724 { 1725 struct ice_aqc_q_shutdown *cmd; 1726 struct ice_aq_desc desc; 1727 1728 cmd = &desc.params.q_shutdown; 1729 1730 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1731 1732 if (unloading) 1733 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1734 1735 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1736 } 1737 1738 /** 1739 * ice_aq_req_res 1740 * @hw: pointer to the HW struct 1741 * @res: resource ID 1742 * @access: access type 1743 * @sdp_number: resource number 1744 * @timeout: the maximum time in ms that the driver may hold the resource 1745 * @cd: pointer to command details structure or NULL 1746 * 1747 * Requests common resource using the admin queue commands (0x0008). 1748 * When attempting to acquire the Global Config Lock, the driver can 1749 * learn of three states: 1750 * 1) 0 - acquired lock, and can perform download package 1751 * 2) -EIO - did not get lock, driver should fail to load 1752 * 3) -EALREADY - did not get lock, but another driver has 1753 * successfully downloaded the package; the driver does 1754 * not have to download the package and can continue 1755 * loading 1756 * 1757 * Note that if the caller is in an acquire lock, perform action, release lock 1758 * phase of operation, it is possible that the FW may detect a timeout and issue 1759 * a CORER. In this case, the driver will receive a CORER interrupt and will 1760 * have to determine its cause. The calling thread that is handling this flow 1761 * will likely get an error propagated back to it indicating the Download 1762 * Package, Update Package or the Release Resource AQ commands timed out. 1763 */ 1764 static int 1765 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1766 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1767 struct ice_sq_cd *cd) 1768 { 1769 struct ice_aqc_req_res *cmd_resp; 1770 struct ice_aq_desc desc; 1771 int status; 1772 1773 cmd_resp = &desc.params.res_owner; 1774 1775 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1776 1777 cmd_resp->res_id = cpu_to_le16(res); 1778 cmd_resp->access_type = cpu_to_le16(access); 1779 cmd_resp->res_number = cpu_to_le32(sdp_number); 1780 cmd_resp->timeout = cpu_to_le32(*timeout); 1781 *timeout = 0; 1782 1783 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1784 1785 /* The completion specifies the maximum time in ms that the driver 1786 * may hold the resource in the Timeout field. 1787 */ 1788 1789 /* Global config lock response utilizes an additional status field. 1790 * 1791 * If the Global config lock resource is held by some other driver, the 1792 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1793 * and the timeout field indicates the maximum time the current owner 1794 * of the resource has to free it. 1795 */ 1796 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1797 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1798 *timeout = le32_to_cpu(cmd_resp->timeout); 1799 return 0; 1800 } else if (le16_to_cpu(cmd_resp->status) == 1801 ICE_AQ_RES_GLBL_IN_PROG) { 1802 *timeout = le32_to_cpu(cmd_resp->timeout); 1803 return -EIO; 1804 } else if (le16_to_cpu(cmd_resp->status) == 1805 ICE_AQ_RES_GLBL_DONE) { 1806 return -EALREADY; 1807 } 1808 1809 /* invalid FW response, force a timeout immediately */ 1810 *timeout = 0; 1811 return -EIO; 1812 } 1813 1814 /* If the resource is held by some other driver, the command completes 1815 * with a busy return value and the timeout field indicates the maximum 1816 * time the current owner of the resource has to free it. 1817 */ 1818 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1819 *timeout = le32_to_cpu(cmd_resp->timeout); 1820 1821 return status; 1822 } 1823 1824 /** 1825 * ice_aq_release_res 1826 * @hw: pointer to the HW struct 1827 * @res: resource ID 1828 * @sdp_number: resource number 1829 * @cd: pointer to command details structure or NULL 1830 * 1831 * release common resource using the admin queue commands (0x0009) 1832 */ 1833 static int 1834 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1835 struct ice_sq_cd *cd) 1836 { 1837 struct ice_aqc_req_res *cmd; 1838 struct ice_aq_desc desc; 1839 1840 cmd = &desc.params.res_owner; 1841 1842 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1843 1844 cmd->res_id = cpu_to_le16(res); 1845 cmd->res_number = cpu_to_le32(sdp_number); 1846 1847 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1848 } 1849 1850 /** 1851 * ice_acquire_res 1852 * @hw: pointer to the HW structure 1853 * @res: resource ID 1854 * @access: access type (read or write) 1855 * @timeout: timeout in milliseconds 1856 * 1857 * This function will attempt to acquire the ownership of a resource. 1858 */ 1859 int 1860 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1861 enum ice_aq_res_access_type access, u32 timeout) 1862 { 1863 #define ICE_RES_POLLING_DELAY_MS 10 1864 u32 delay = ICE_RES_POLLING_DELAY_MS; 1865 u32 time_left = timeout; 1866 int status; 1867 1868 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1869 1870 /* A return code of -EALREADY means that another driver has 1871 * previously acquired the resource and performed any necessary updates; 1872 * in this case the caller does not obtain the resource and has no 1873 * further work to do. 1874 */ 1875 if (status == -EALREADY) 1876 goto ice_acquire_res_exit; 1877 1878 if (status) 1879 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1880 1881 /* If necessary, poll until the current lock owner timeouts */ 1882 timeout = time_left; 1883 while (status && timeout && time_left) { 1884 mdelay(delay); 1885 timeout = (timeout > delay) ? timeout - delay : 0; 1886 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1887 1888 if (status == -EALREADY) 1889 /* lock free, but no work to do */ 1890 break; 1891 1892 if (!status) 1893 /* lock acquired */ 1894 break; 1895 } 1896 if (status && status != -EALREADY) 1897 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1898 1899 ice_acquire_res_exit: 1900 if (status == -EALREADY) { 1901 if (access == ICE_RES_WRITE) 1902 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1903 else 1904 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1905 } 1906 return status; 1907 } 1908 1909 /** 1910 * ice_release_res 1911 * @hw: pointer to the HW structure 1912 * @res: resource ID 1913 * 1914 * This function will release a resource using the proper Admin Command. 1915 */ 1916 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1917 { 1918 unsigned long timeout; 1919 int status; 1920 1921 /* there are some rare cases when trying to release the resource 1922 * results in an admin queue timeout, so handle them correctly 1923 */ 1924 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 1925 do { 1926 status = ice_aq_release_res(hw, res, 0, NULL); 1927 if (status != -EIO) 1928 break; 1929 usleep_range(1000, 2000); 1930 } while (time_before(jiffies, timeout)); 1931 } 1932 1933 /** 1934 * ice_aq_alloc_free_res - command to allocate/free resources 1935 * @hw: pointer to the HW struct 1936 * @buf: Indirect buffer to hold data parameters and response 1937 * @buf_size: size of buffer for indirect commands 1938 * @opc: pass in the command opcode 1939 * 1940 * Helper function to allocate/free resources using the admin queue commands 1941 */ 1942 int ice_aq_alloc_free_res(struct ice_hw *hw, 1943 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1944 enum ice_adminq_opc opc) 1945 { 1946 struct ice_aqc_alloc_free_res_cmd *cmd; 1947 struct ice_aq_desc desc; 1948 1949 cmd = &desc.params.sw_res_ctrl; 1950 1951 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 1952 return -EINVAL; 1953 1954 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1955 1956 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1957 1958 cmd->num_entries = cpu_to_le16(1); 1959 1960 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 1961 } 1962 1963 /** 1964 * ice_alloc_hw_res - allocate resource 1965 * @hw: pointer to the HW struct 1966 * @type: type of resource 1967 * @num: number of resources to allocate 1968 * @btm: allocate from bottom 1969 * @res: pointer to array that will receive the resources 1970 */ 1971 int 1972 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1973 { 1974 struct ice_aqc_alloc_free_res_elem *buf; 1975 u16 buf_len; 1976 int status; 1977 1978 buf_len = struct_size(buf, elem, num); 1979 buf = kzalloc(buf_len, GFP_KERNEL); 1980 if (!buf) 1981 return -ENOMEM; 1982 1983 /* Prepare buffer to allocate resource. */ 1984 buf->num_elems = cpu_to_le16(num); 1985 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1986 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1987 if (btm) 1988 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1989 1990 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 1991 if (status) 1992 goto ice_alloc_res_exit; 1993 1994 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1995 1996 ice_alloc_res_exit: 1997 kfree(buf); 1998 return status; 1999 } 2000 2001 /** 2002 * ice_free_hw_res - free allocated HW resource 2003 * @hw: pointer to the HW struct 2004 * @type: type of resource to free 2005 * @num: number of resources 2006 * @res: pointer to array that contains the resources to free 2007 */ 2008 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2009 { 2010 struct ice_aqc_alloc_free_res_elem *buf; 2011 u16 buf_len; 2012 int status; 2013 2014 buf_len = struct_size(buf, elem, num); 2015 buf = kzalloc(buf_len, GFP_KERNEL); 2016 if (!buf) 2017 return -ENOMEM; 2018 2019 /* Prepare buffer to free resource. */ 2020 buf->num_elems = cpu_to_le16(num); 2021 buf->res_type = cpu_to_le16(type); 2022 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2023 2024 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2025 if (status) 2026 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2027 2028 kfree(buf); 2029 return status; 2030 } 2031 2032 /** 2033 * ice_get_num_per_func - determine number of resources per PF 2034 * @hw: pointer to the HW structure 2035 * @max: value to be evenly split between each PF 2036 * 2037 * Determine the number of valid functions by going through the bitmap returned 2038 * from parsing capabilities and use this to calculate the number of resources 2039 * per PF based on the max value passed in. 2040 */ 2041 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2042 { 2043 u8 funcs; 2044 2045 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2046 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2047 ICE_CAPS_VALID_FUNCS_M); 2048 2049 if (!funcs) 2050 return 0; 2051 2052 return max / funcs; 2053 } 2054 2055 /** 2056 * ice_parse_common_caps - parse common device/function capabilities 2057 * @hw: pointer to the HW struct 2058 * @caps: pointer to common capabilities structure 2059 * @elem: the capability element to parse 2060 * @prefix: message prefix for tracing capabilities 2061 * 2062 * Given a capability element, extract relevant details into the common 2063 * capability structure. 2064 * 2065 * Returns: true if the capability matches one of the common capability ids, 2066 * false otherwise. 2067 */ 2068 static bool 2069 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2070 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2071 { 2072 u32 logical_id = le32_to_cpu(elem->logical_id); 2073 u32 phys_id = le32_to_cpu(elem->phys_id); 2074 u32 number = le32_to_cpu(elem->number); 2075 u16 cap = le16_to_cpu(elem->cap); 2076 bool found = true; 2077 2078 switch (cap) { 2079 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2080 caps->valid_functions = number; 2081 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2082 caps->valid_functions); 2083 break; 2084 case ICE_AQC_CAPS_SRIOV: 2085 caps->sr_iov_1_1 = (number == 1); 2086 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2087 caps->sr_iov_1_1); 2088 break; 2089 case ICE_AQC_CAPS_DCB: 2090 caps->dcb = (number == 1); 2091 caps->active_tc_bitmap = logical_id; 2092 caps->maxtc = phys_id; 2093 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2094 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2095 caps->active_tc_bitmap); 2096 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2097 break; 2098 case ICE_AQC_CAPS_RSS: 2099 caps->rss_table_size = number; 2100 caps->rss_table_entry_width = logical_id; 2101 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2102 caps->rss_table_size); 2103 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2104 caps->rss_table_entry_width); 2105 break; 2106 case ICE_AQC_CAPS_RXQS: 2107 caps->num_rxq = number; 2108 caps->rxq_first_id = phys_id; 2109 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2110 caps->num_rxq); 2111 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2112 caps->rxq_first_id); 2113 break; 2114 case ICE_AQC_CAPS_TXQS: 2115 caps->num_txq = number; 2116 caps->txq_first_id = phys_id; 2117 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2118 caps->num_txq); 2119 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2120 caps->txq_first_id); 2121 break; 2122 case ICE_AQC_CAPS_MSIX: 2123 caps->num_msix_vectors = number; 2124 caps->msix_vector_first_id = phys_id; 2125 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2126 caps->num_msix_vectors); 2127 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2128 caps->msix_vector_first_id); 2129 break; 2130 case ICE_AQC_CAPS_PENDING_NVM_VER: 2131 caps->nvm_update_pending_nvm = true; 2132 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2133 break; 2134 case ICE_AQC_CAPS_PENDING_OROM_VER: 2135 caps->nvm_update_pending_orom = true; 2136 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2137 break; 2138 case ICE_AQC_CAPS_PENDING_NET_VER: 2139 caps->nvm_update_pending_netlist = true; 2140 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2141 break; 2142 case ICE_AQC_CAPS_NVM_MGMT: 2143 caps->nvm_unified_update = 2144 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2145 true : false; 2146 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2147 caps->nvm_unified_update); 2148 break; 2149 case ICE_AQC_CAPS_RDMA: 2150 caps->rdma = (number == 1); 2151 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2152 break; 2153 case ICE_AQC_CAPS_MAX_MTU: 2154 caps->max_mtu = number; 2155 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2156 prefix, caps->max_mtu); 2157 break; 2158 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2159 caps->pcie_reset_avoidance = (number > 0); 2160 ice_debug(hw, ICE_DBG_INIT, 2161 "%s: pcie_reset_avoidance = %d\n", prefix, 2162 caps->pcie_reset_avoidance); 2163 break; 2164 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2165 caps->reset_restrict_support = (number == 1); 2166 ice_debug(hw, ICE_DBG_INIT, 2167 "%s: reset_restrict_support = %d\n", prefix, 2168 caps->reset_restrict_support); 2169 break; 2170 case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2171 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2172 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2173 prefix, caps->roce_lag); 2174 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2175 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2176 prefix, caps->sriov_lag); 2177 break; 2178 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2179 caps->tx_sched_topo_comp_mode_en = (number == 1); 2180 break; 2181 default: 2182 /* Not one of the recognized common capabilities */ 2183 found = false; 2184 } 2185 2186 return found; 2187 } 2188 2189 /** 2190 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2191 * @hw: pointer to the HW structure 2192 * @caps: pointer to capabilities structure to fix 2193 * 2194 * Re-calculate the capabilities that are dependent on the number of physical 2195 * ports; i.e. some features are not supported or function differently on 2196 * devices with more than 4 ports. 2197 */ 2198 static void 2199 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2200 { 2201 /* This assumes device capabilities are always scanned before function 2202 * capabilities during the initialization flow. 2203 */ 2204 if (hw->dev_caps.num_funcs > 4) { 2205 /* Max 4 TCs per port */ 2206 caps->maxtc = 4; 2207 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2208 caps->maxtc); 2209 if (caps->rdma) { 2210 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2211 caps->rdma = 0; 2212 } 2213 2214 /* print message only when processing device capabilities 2215 * during initialization. 2216 */ 2217 if (caps == &hw->dev_caps.common_cap) 2218 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2219 } 2220 } 2221 2222 /** 2223 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2224 * @hw: pointer to the HW struct 2225 * @func_p: pointer to function capabilities structure 2226 * @cap: pointer to the capability element to parse 2227 * 2228 * Extract function capabilities for ICE_AQC_CAPS_VF. 2229 */ 2230 static void 2231 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2232 struct ice_aqc_list_caps_elem *cap) 2233 { 2234 u32 logical_id = le32_to_cpu(cap->logical_id); 2235 u32 number = le32_to_cpu(cap->number); 2236 2237 func_p->num_allocd_vfs = number; 2238 func_p->vf_base_id = logical_id; 2239 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2240 func_p->num_allocd_vfs); 2241 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2242 func_p->vf_base_id); 2243 } 2244 2245 /** 2246 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2247 * @hw: pointer to the HW struct 2248 * @func_p: pointer to function capabilities structure 2249 * @cap: pointer to the capability element to parse 2250 * 2251 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2252 */ 2253 static void 2254 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2255 struct ice_aqc_list_caps_elem *cap) 2256 { 2257 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2258 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2259 le32_to_cpu(cap->number)); 2260 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2261 func_p->guar_num_vsi); 2262 } 2263 2264 /** 2265 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2266 * @hw: pointer to the HW struct 2267 * @func_p: pointer to function capabilities structure 2268 * @cap: pointer to the capability element to parse 2269 * 2270 * Extract function capabilities for ICE_AQC_CAPS_1588. 2271 */ 2272 static void 2273 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2274 struct ice_aqc_list_caps_elem *cap) 2275 { 2276 struct ice_ts_func_info *info = &func_p->ts_func_info; 2277 u32 number = le32_to_cpu(cap->number); 2278 2279 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2280 func_p->common_cap.ieee_1588 = info->ena; 2281 2282 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2283 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2284 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2285 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2286 2287 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2288 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2289 2290 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2291 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2292 } else { 2293 /* Unknown clock frequency, so assume a (probably incorrect) 2294 * default to avoid out-of-bounds look ups of frequency 2295 * related information. 2296 */ 2297 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2298 info->clk_freq); 2299 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2300 } 2301 2302 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2303 func_p->common_cap.ieee_1588); 2304 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2305 info->src_tmr_owned); 2306 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2307 info->tmr_ena); 2308 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2309 info->tmr_index_owned); 2310 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2311 info->tmr_index_assoc); 2312 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2313 info->clk_freq); 2314 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2315 info->clk_src); 2316 } 2317 2318 /** 2319 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2320 * @hw: pointer to the HW struct 2321 * @func_p: pointer to function capabilities structure 2322 * 2323 * Extract function capabilities for ICE_AQC_CAPS_FD. 2324 */ 2325 static void 2326 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2327 { 2328 u32 reg_val, gsize, bsize; 2329 2330 reg_val = rd32(hw, GLQF_FD_SIZE); 2331 switch (hw->mac_type) { 2332 case ICE_MAC_E830: 2333 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2334 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2335 break; 2336 case ICE_MAC_E810: 2337 default: 2338 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2339 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2340 } 2341 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2342 func_p->fd_fltr_best_effort = bsize; 2343 2344 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2345 func_p->fd_fltr_guar); 2346 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2347 func_p->fd_fltr_best_effort); 2348 } 2349 2350 /** 2351 * ice_parse_func_caps - Parse function capabilities 2352 * @hw: pointer to the HW struct 2353 * @func_p: pointer to function capabilities structure 2354 * @buf: buffer containing the function capability records 2355 * @cap_count: the number of capabilities 2356 * 2357 * Helper function to parse function (0x000A) capabilities list. For 2358 * capabilities shared between device and function, this relies on 2359 * ice_parse_common_caps. 2360 * 2361 * Loop through the list of provided capabilities and extract the relevant 2362 * data into the function capabilities structured. 2363 */ 2364 static void 2365 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2366 void *buf, u32 cap_count) 2367 { 2368 struct ice_aqc_list_caps_elem *cap_resp; 2369 u32 i; 2370 2371 cap_resp = buf; 2372 2373 memset(func_p, 0, sizeof(*func_p)); 2374 2375 for (i = 0; i < cap_count; i++) { 2376 u16 cap = le16_to_cpu(cap_resp[i].cap); 2377 bool found; 2378 2379 found = ice_parse_common_caps(hw, &func_p->common_cap, 2380 &cap_resp[i], "func caps"); 2381 2382 switch (cap) { 2383 case ICE_AQC_CAPS_VF: 2384 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2385 break; 2386 case ICE_AQC_CAPS_VSI: 2387 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2388 break; 2389 case ICE_AQC_CAPS_1588: 2390 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2391 break; 2392 case ICE_AQC_CAPS_FD: 2393 ice_parse_fdir_func_caps(hw, func_p); 2394 break; 2395 default: 2396 /* Don't list common capabilities as unknown */ 2397 if (!found) 2398 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2399 i, cap); 2400 break; 2401 } 2402 } 2403 2404 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2405 } 2406 2407 /** 2408 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2409 * @hw: pointer to the HW struct 2410 * @dev_p: pointer to device capabilities structure 2411 * @cap: capability element to parse 2412 * 2413 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2414 */ 2415 static void 2416 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2417 struct ice_aqc_list_caps_elem *cap) 2418 { 2419 u32 number = le32_to_cpu(cap->number); 2420 2421 dev_p->num_funcs = hweight32(number); 2422 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2423 dev_p->num_funcs); 2424 } 2425 2426 /** 2427 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2428 * @hw: pointer to the HW struct 2429 * @dev_p: pointer to device capabilities structure 2430 * @cap: capability element to parse 2431 * 2432 * Parse ICE_AQC_CAPS_VF for device capabilities. 2433 */ 2434 static void 2435 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2436 struct ice_aqc_list_caps_elem *cap) 2437 { 2438 u32 number = le32_to_cpu(cap->number); 2439 2440 dev_p->num_vfs_exposed = number; 2441 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2442 dev_p->num_vfs_exposed); 2443 } 2444 2445 /** 2446 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2447 * @hw: pointer to the HW struct 2448 * @dev_p: pointer to device capabilities structure 2449 * @cap: capability element to parse 2450 * 2451 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2452 */ 2453 static void 2454 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2455 struct ice_aqc_list_caps_elem *cap) 2456 { 2457 u32 number = le32_to_cpu(cap->number); 2458 2459 dev_p->num_vsi_allocd_to_host = number; 2460 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2461 dev_p->num_vsi_allocd_to_host); 2462 } 2463 2464 /** 2465 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2466 * @hw: pointer to the HW struct 2467 * @dev_p: pointer to device capabilities structure 2468 * @cap: capability element to parse 2469 * 2470 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2471 */ 2472 static void 2473 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2474 struct ice_aqc_list_caps_elem *cap) 2475 { 2476 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2477 u32 logical_id = le32_to_cpu(cap->logical_id); 2478 u32 phys_id = le32_to_cpu(cap->phys_id); 2479 u32 number = le32_to_cpu(cap->number); 2480 2481 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2482 dev_p->common_cap.ieee_1588 = info->ena; 2483 2484 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2485 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2486 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2487 2488 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2489 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2490 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2491 2492 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2493 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2494 2495 info->ena_ports = logical_id; 2496 info->tmr_own_map = phys_id; 2497 2498 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2499 dev_p->common_cap.ieee_1588); 2500 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2501 info->tmr0_owner); 2502 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2503 info->tmr0_owned); 2504 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2505 info->tmr0_ena); 2506 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2507 info->tmr1_owner); 2508 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2509 info->tmr1_owned); 2510 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2511 info->tmr1_ena); 2512 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2513 info->ts_ll_read); 2514 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2515 info->ts_ll_int_read); 2516 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2517 info->ena_ports); 2518 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2519 info->tmr_own_map); 2520 } 2521 2522 /** 2523 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2524 * @hw: pointer to the HW struct 2525 * @dev_p: pointer to device capabilities structure 2526 * @cap: capability element to parse 2527 * 2528 * Parse ICE_AQC_CAPS_FD for device capabilities. 2529 */ 2530 static void 2531 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2532 struct ice_aqc_list_caps_elem *cap) 2533 { 2534 u32 number = le32_to_cpu(cap->number); 2535 2536 dev_p->num_flow_director_fltr = number; 2537 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2538 dev_p->num_flow_director_fltr); 2539 } 2540 2541 /** 2542 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2543 * @hw: pointer to the HW struct 2544 * @dev_p: pointer to device capabilities structure 2545 * @cap: capability element to parse 2546 * 2547 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2548 * enabled sensors. 2549 */ 2550 static void 2551 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2552 struct ice_aqc_list_caps_elem *cap) 2553 { 2554 dev_p->supported_sensors = le32_to_cpu(cap->number); 2555 2556 ice_debug(hw, ICE_DBG_INIT, 2557 "dev caps: supported sensors (bitmap) = 0x%x\n", 2558 dev_p->supported_sensors); 2559 } 2560 2561 /** 2562 * ice_parse_dev_caps - Parse device capabilities 2563 * @hw: pointer to the HW struct 2564 * @dev_p: pointer to device capabilities structure 2565 * @buf: buffer containing the device capability records 2566 * @cap_count: the number of capabilities 2567 * 2568 * Helper device to parse device (0x000B) capabilities list. For 2569 * capabilities shared between device and function, this relies on 2570 * ice_parse_common_caps. 2571 * 2572 * Loop through the list of provided capabilities and extract the relevant 2573 * data into the device capabilities structured. 2574 */ 2575 static void 2576 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2577 void *buf, u32 cap_count) 2578 { 2579 struct ice_aqc_list_caps_elem *cap_resp; 2580 u32 i; 2581 2582 cap_resp = buf; 2583 2584 memset(dev_p, 0, sizeof(*dev_p)); 2585 2586 for (i = 0; i < cap_count; i++) { 2587 u16 cap = le16_to_cpu(cap_resp[i].cap); 2588 bool found; 2589 2590 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2591 &cap_resp[i], "dev caps"); 2592 2593 switch (cap) { 2594 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2595 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2596 break; 2597 case ICE_AQC_CAPS_VF: 2598 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2599 break; 2600 case ICE_AQC_CAPS_VSI: 2601 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2602 break; 2603 case ICE_AQC_CAPS_1588: 2604 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2605 break; 2606 case ICE_AQC_CAPS_FD: 2607 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2608 break; 2609 case ICE_AQC_CAPS_SENSOR_READING: 2610 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2611 break; 2612 default: 2613 /* Don't list common capabilities as unknown */ 2614 if (!found) 2615 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2616 i, cap); 2617 break; 2618 } 2619 } 2620 2621 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2622 } 2623 2624 /** 2625 * ice_is_pf_c827 - check if pf contains c827 phy 2626 * @hw: pointer to the hw struct 2627 */ 2628 bool ice_is_pf_c827(struct ice_hw *hw) 2629 { 2630 struct ice_aqc_get_link_topo cmd = {}; 2631 u8 node_part_number; 2632 u16 node_handle; 2633 int status; 2634 2635 if (hw->mac_type != ICE_MAC_E810) 2636 return false; 2637 2638 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 2639 return true; 2640 2641 cmd.addr.topo_params.node_type_ctx = 2642 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 2643 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 2644 cmd.addr.topo_params.index = 0; 2645 2646 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 2647 &node_handle); 2648 2649 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 2650 return false; 2651 2652 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 2653 return true; 2654 2655 return false; 2656 } 2657 2658 /** 2659 * ice_is_phy_rclk_in_netlist 2660 * @hw: pointer to the hw struct 2661 * 2662 * Check if the PHY Recovered Clock device is present in the netlist 2663 */ 2664 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2665 { 2666 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2667 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2668 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2669 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2670 return false; 2671 2672 return true; 2673 } 2674 2675 /** 2676 * ice_is_clock_mux_in_netlist 2677 * @hw: pointer to the hw struct 2678 * 2679 * Check if the Clock Multiplexer device is present in the netlist 2680 */ 2681 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2682 { 2683 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2684 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2685 NULL)) 2686 return false; 2687 2688 return true; 2689 } 2690 2691 /** 2692 * ice_is_cgu_in_netlist - check for CGU presence 2693 * @hw: pointer to the hw struct 2694 * 2695 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2696 * Save the CGU part number in the hw structure for later use. 2697 * Return: 2698 * * true - cgu is present 2699 * * false - cgu is not present 2700 */ 2701 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2702 { 2703 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2704 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2705 NULL)) { 2706 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2707 return true; 2708 } else if (!ice_find_netlist_node(hw, 2709 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2710 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2711 NULL)) { 2712 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2713 return true; 2714 } 2715 2716 return false; 2717 } 2718 2719 /** 2720 * ice_is_gps_in_netlist 2721 * @hw: pointer to the hw struct 2722 * 2723 * Check if the GPS generic device is present in the netlist 2724 */ 2725 bool ice_is_gps_in_netlist(struct ice_hw *hw) 2726 { 2727 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 2728 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 2729 return false; 2730 2731 return true; 2732 } 2733 2734 /** 2735 * ice_aq_list_caps - query function/device capabilities 2736 * @hw: pointer to the HW struct 2737 * @buf: a buffer to hold the capabilities 2738 * @buf_size: size of the buffer 2739 * @cap_count: if not NULL, set to the number of capabilities reported 2740 * @opc: capabilities type to discover, device or function 2741 * @cd: pointer to command details structure or NULL 2742 * 2743 * Get the function (0x000A) or device (0x000B) capabilities description from 2744 * firmware and store it in the buffer. 2745 * 2746 * If the cap_count pointer is not NULL, then it is set to the number of 2747 * capabilities firmware will report. Note that if the buffer size is too 2748 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2749 * cap_count will still be updated in this case. It is recommended that the 2750 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2751 * firmware could return) to avoid this. 2752 */ 2753 int 2754 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2755 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2756 { 2757 struct ice_aqc_list_caps *cmd; 2758 struct ice_aq_desc desc; 2759 int status; 2760 2761 cmd = &desc.params.get_cap; 2762 2763 if (opc != ice_aqc_opc_list_func_caps && 2764 opc != ice_aqc_opc_list_dev_caps) 2765 return -EINVAL; 2766 2767 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2768 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2769 2770 if (cap_count) 2771 *cap_count = le32_to_cpu(cmd->count); 2772 2773 return status; 2774 } 2775 2776 /** 2777 * ice_discover_dev_caps - Read and extract device capabilities 2778 * @hw: pointer to the hardware structure 2779 * @dev_caps: pointer to device capabilities structure 2780 * 2781 * Read the device capabilities and extract them into the dev_caps structure 2782 * for later use. 2783 */ 2784 int 2785 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2786 { 2787 u32 cap_count = 0; 2788 void *cbuf; 2789 int status; 2790 2791 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2792 if (!cbuf) 2793 return -ENOMEM; 2794 2795 /* Although the driver doesn't know the number of capabilities the 2796 * device will return, we can simply send a 4KB buffer, the maximum 2797 * possible size that firmware can return. 2798 */ 2799 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2800 2801 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2802 ice_aqc_opc_list_dev_caps, NULL); 2803 if (!status) 2804 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2805 kfree(cbuf); 2806 2807 return status; 2808 } 2809 2810 /** 2811 * ice_discover_func_caps - Read and extract function capabilities 2812 * @hw: pointer to the hardware structure 2813 * @func_caps: pointer to function capabilities structure 2814 * 2815 * Read the function capabilities and extract them into the func_caps structure 2816 * for later use. 2817 */ 2818 static int 2819 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2820 { 2821 u32 cap_count = 0; 2822 void *cbuf; 2823 int status; 2824 2825 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2826 if (!cbuf) 2827 return -ENOMEM; 2828 2829 /* Although the driver doesn't know the number of capabilities the 2830 * device will return, we can simply send a 4KB buffer, the maximum 2831 * possible size that firmware can return. 2832 */ 2833 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2834 2835 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2836 ice_aqc_opc_list_func_caps, NULL); 2837 if (!status) 2838 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2839 kfree(cbuf); 2840 2841 return status; 2842 } 2843 2844 /** 2845 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2846 * @hw: pointer to the hardware structure 2847 */ 2848 void ice_set_safe_mode_caps(struct ice_hw *hw) 2849 { 2850 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2851 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2852 struct ice_hw_common_caps cached_caps; 2853 u32 num_funcs; 2854 2855 /* cache some func_caps values that should be restored after memset */ 2856 cached_caps = func_caps->common_cap; 2857 2858 /* unset func capabilities */ 2859 memset(func_caps, 0, sizeof(*func_caps)); 2860 2861 #define ICE_RESTORE_FUNC_CAP(name) \ 2862 func_caps->common_cap.name = cached_caps.name 2863 2864 /* restore cached values */ 2865 ICE_RESTORE_FUNC_CAP(valid_functions); 2866 ICE_RESTORE_FUNC_CAP(txq_first_id); 2867 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2868 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2869 ICE_RESTORE_FUNC_CAP(max_mtu); 2870 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2871 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2872 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2873 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2874 2875 /* one Tx and one Rx queue in safe mode */ 2876 func_caps->common_cap.num_rxq = 1; 2877 func_caps->common_cap.num_txq = 1; 2878 2879 /* two MSIX vectors, one for traffic and one for misc causes */ 2880 func_caps->common_cap.num_msix_vectors = 2; 2881 func_caps->guar_num_vsi = 1; 2882 2883 /* cache some dev_caps values that should be restored after memset */ 2884 cached_caps = dev_caps->common_cap; 2885 num_funcs = dev_caps->num_funcs; 2886 2887 /* unset dev capabilities */ 2888 memset(dev_caps, 0, sizeof(*dev_caps)); 2889 2890 #define ICE_RESTORE_DEV_CAP(name) \ 2891 dev_caps->common_cap.name = cached_caps.name 2892 2893 /* restore cached values */ 2894 ICE_RESTORE_DEV_CAP(valid_functions); 2895 ICE_RESTORE_DEV_CAP(txq_first_id); 2896 ICE_RESTORE_DEV_CAP(rxq_first_id); 2897 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2898 ICE_RESTORE_DEV_CAP(max_mtu); 2899 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2900 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2901 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2902 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2903 dev_caps->num_funcs = num_funcs; 2904 2905 /* one Tx and one Rx queue per function in safe mode */ 2906 dev_caps->common_cap.num_rxq = num_funcs; 2907 dev_caps->common_cap.num_txq = num_funcs; 2908 2909 /* two MSIX vectors per function */ 2910 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2911 } 2912 2913 /** 2914 * ice_get_caps - get info about the HW 2915 * @hw: pointer to the hardware structure 2916 */ 2917 int ice_get_caps(struct ice_hw *hw) 2918 { 2919 int status; 2920 2921 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2922 if (status) 2923 return status; 2924 2925 return ice_discover_func_caps(hw, &hw->func_caps); 2926 } 2927 2928 /** 2929 * ice_aq_manage_mac_write - manage MAC address write command 2930 * @hw: pointer to the HW struct 2931 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2932 * @flags: flags to control write behavior 2933 * @cd: pointer to command details structure or NULL 2934 * 2935 * This function is used to write MAC address to the NVM (0x0108). 2936 */ 2937 int 2938 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2939 struct ice_sq_cd *cd) 2940 { 2941 struct ice_aqc_manage_mac_write *cmd; 2942 struct ice_aq_desc desc; 2943 2944 cmd = &desc.params.mac_write; 2945 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2946 2947 cmd->flags = flags; 2948 ether_addr_copy(cmd->mac_addr, mac_addr); 2949 2950 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2951 } 2952 2953 /** 2954 * ice_aq_clear_pxe_mode 2955 * @hw: pointer to the HW struct 2956 * 2957 * Tell the firmware that the driver is taking over from PXE (0x0110). 2958 */ 2959 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2960 { 2961 struct ice_aq_desc desc; 2962 2963 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2964 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2965 2966 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2967 } 2968 2969 /** 2970 * ice_clear_pxe_mode - clear pxe operations mode 2971 * @hw: pointer to the HW struct 2972 * 2973 * Make sure all PXE mode settings are cleared, including things 2974 * like descriptor fetch/write-back mode. 2975 */ 2976 void ice_clear_pxe_mode(struct ice_hw *hw) 2977 { 2978 if (ice_check_sq_alive(hw, &hw->adminq)) 2979 ice_aq_clear_pxe_mode(hw); 2980 } 2981 2982 /** 2983 * ice_aq_set_port_params - set physical port parameters. 2984 * @pi: pointer to the port info struct 2985 * @double_vlan: if set double VLAN is enabled 2986 * @cd: pointer to command details structure or NULL 2987 * 2988 * Set Physical port parameters (0x0203) 2989 */ 2990 int 2991 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2992 struct ice_sq_cd *cd) 2993 2994 { 2995 struct ice_aqc_set_port_params *cmd; 2996 struct ice_hw *hw = pi->hw; 2997 struct ice_aq_desc desc; 2998 u16 cmd_flags = 0; 2999 3000 cmd = &desc.params.set_port_params; 3001 3002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3003 if (double_vlan) 3004 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3005 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3006 3007 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3008 } 3009 3010 /** 3011 * ice_is_100m_speed_supported 3012 * @hw: pointer to the HW struct 3013 * 3014 * returns true if 100M speeds are supported by the device, 3015 * false otherwise. 3016 */ 3017 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3018 { 3019 switch (hw->device_id) { 3020 case ICE_DEV_ID_E822C_SGMII: 3021 case ICE_DEV_ID_E822L_SGMII: 3022 case ICE_DEV_ID_E823L_1GBE: 3023 case ICE_DEV_ID_E823C_SGMII: 3024 return true; 3025 default: 3026 return false; 3027 } 3028 } 3029 3030 /** 3031 * ice_get_link_speed_based_on_phy_type - returns link speed 3032 * @phy_type_low: lower part of phy_type 3033 * @phy_type_high: higher part of phy_type 3034 * 3035 * This helper function will convert an entry in PHY type structure 3036 * [phy_type_low, phy_type_high] to its corresponding link speed. 3037 * Note: In the structure of [phy_type_low, phy_type_high], there should 3038 * be one bit set, as this function will convert one PHY type to its 3039 * speed. 3040 * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3041 * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3042 */ 3043 static u16 3044 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3045 { 3046 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3047 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3048 3049 switch (phy_type_low) { 3050 case ICE_PHY_TYPE_LOW_100BASE_TX: 3051 case ICE_PHY_TYPE_LOW_100M_SGMII: 3052 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3053 break; 3054 case ICE_PHY_TYPE_LOW_1000BASE_T: 3055 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3056 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3057 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3058 case ICE_PHY_TYPE_LOW_1G_SGMII: 3059 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3060 break; 3061 case ICE_PHY_TYPE_LOW_2500BASE_T: 3062 case ICE_PHY_TYPE_LOW_2500BASE_X: 3063 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3064 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3065 break; 3066 case ICE_PHY_TYPE_LOW_5GBASE_T: 3067 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3068 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3069 break; 3070 case ICE_PHY_TYPE_LOW_10GBASE_T: 3071 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3072 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3073 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3074 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3075 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3076 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3077 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3078 break; 3079 case ICE_PHY_TYPE_LOW_25GBASE_T: 3080 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3081 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3082 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3083 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3084 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3085 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3086 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3087 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3088 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3089 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3090 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3091 break; 3092 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3093 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3094 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3095 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3096 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3097 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3098 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3099 break; 3100 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3101 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3102 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3103 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3104 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3105 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3106 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3107 case ICE_PHY_TYPE_LOW_50G_AUI2: 3108 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3109 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3110 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3111 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3112 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3113 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3114 case ICE_PHY_TYPE_LOW_50G_AUI1: 3115 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3116 break; 3117 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3118 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3119 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3120 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3121 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3122 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3123 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3124 case ICE_PHY_TYPE_LOW_100G_AUI4: 3125 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3126 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3127 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3128 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3129 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3130 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3131 break; 3132 default: 3133 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3134 break; 3135 } 3136 3137 switch (phy_type_high) { 3138 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3139 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3140 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3141 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3142 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3143 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3144 break; 3145 default: 3146 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3147 break; 3148 } 3149 3150 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3151 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3152 return ICE_AQ_LINK_SPEED_UNKNOWN; 3153 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3154 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3155 return ICE_AQ_LINK_SPEED_UNKNOWN; 3156 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3157 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3158 return speed_phy_type_low; 3159 else 3160 return speed_phy_type_high; 3161 } 3162 3163 /** 3164 * ice_update_phy_type 3165 * @phy_type_low: pointer to the lower part of phy_type 3166 * @phy_type_high: pointer to the higher part of phy_type 3167 * @link_speeds_bitmap: targeted link speeds bitmap 3168 * 3169 * Note: For the link_speeds_bitmap structure, you can check it at 3170 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3171 * link_speeds_bitmap include multiple speeds. 3172 * 3173 * Each entry in this [phy_type_low, phy_type_high] structure will 3174 * present a certain link speed. This helper function will turn on bits 3175 * in [phy_type_low, phy_type_high] structure based on the value of 3176 * link_speeds_bitmap input parameter. 3177 */ 3178 void 3179 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3180 u16 link_speeds_bitmap) 3181 { 3182 u64 pt_high; 3183 u64 pt_low; 3184 int index; 3185 u16 speed; 3186 3187 /* We first check with low part of phy_type */ 3188 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3189 pt_low = BIT_ULL(index); 3190 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3191 3192 if (link_speeds_bitmap & speed) 3193 *phy_type_low |= BIT_ULL(index); 3194 } 3195 3196 /* We then check with high part of phy_type */ 3197 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3198 pt_high = BIT_ULL(index); 3199 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3200 3201 if (link_speeds_bitmap & speed) 3202 *phy_type_high |= BIT_ULL(index); 3203 } 3204 } 3205 3206 /** 3207 * ice_aq_set_phy_cfg 3208 * @hw: pointer to the HW struct 3209 * @pi: port info structure of the interested logical port 3210 * @cfg: structure with PHY configuration data to be set 3211 * @cd: pointer to command details structure or NULL 3212 * 3213 * Set the various PHY configuration parameters supported on the Port. 3214 * One or more of the Set PHY config parameters may be ignored in an MFP 3215 * mode as the PF may not have the privilege to set some of the PHY Config 3216 * parameters. This status will be indicated by the command response (0x0601). 3217 */ 3218 int 3219 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3220 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3221 { 3222 struct ice_aq_desc desc; 3223 int status; 3224 3225 if (!cfg) 3226 return -EINVAL; 3227 3228 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3229 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3230 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3231 cfg->caps); 3232 3233 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3234 } 3235 3236 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3237 desc.params.set_phy.lport_num = pi->lport; 3238 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3239 3240 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3241 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3242 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3243 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3244 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3245 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3246 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3247 cfg->low_power_ctrl_an); 3248 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3249 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3250 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3251 cfg->link_fec_opt); 3252 3253 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3254 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3255 status = 0; 3256 3257 if (!status) 3258 pi->phy.curr_user_phy_cfg = *cfg; 3259 3260 return status; 3261 } 3262 3263 /** 3264 * ice_update_link_info - update status of the HW network link 3265 * @pi: port info structure of the interested logical port 3266 */ 3267 int ice_update_link_info(struct ice_port_info *pi) 3268 { 3269 struct ice_link_status *li; 3270 int status; 3271 3272 if (!pi) 3273 return -EINVAL; 3274 3275 li = &pi->phy.link_info; 3276 3277 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3278 if (status) 3279 return status; 3280 3281 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3282 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3283 3284 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3285 if (!pcaps) 3286 return -ENOMEM; 3287 3288 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3289 pcaps, NULL); 3290 } 3291 3292 return status; 3293 } 3294 3295 /** 3296 * ice_cache_phy_user_req 3297 * @pi: port information structure 3298 * @cache_data: PHY logging data 3299 * @cache_mode: PHY logging mode 3300 * 3301 * Log the user request on (FC, FEC, SPEED) for later use. 3302 */ 3303 static void 3304 ice_cache_phy_user_req(struct ice_port_info *pi, 3305 struct ice_phy_cache_mode_data cache_data, 3306 enum ice_phy_cache_mode cache_mode) 3307 { 3308 if (!pi) 3309 return; 3310 3311 switch (cache_mode) { 3312 case ICE_FC_MODE: 3313 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3314 break; 3315 case ICE_SPEED_MODE: 3316 pi->phy.curr_user_speed_req = 3317 cache_data.data.curr_user_speed_req; 3318 break; 3319 case ICE_FEC_MODE: 3320 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3321 break; 3322 default: 3323 break; 3324 } 3325 } 3326 3327 /** 3328 * ice_caps_to_fc_mode 3329 * @caps: PHY capabilities 3330 * 3331 * Convert PHY FC capabilities to ice FC mode 3332 */ 3333 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3334 { 3335 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3336 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3337 return ICE_FC_FULL; 3338 3339 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3340 return ICE_FC_TX_PAUSE; 3341 3342 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3343 return ICE_FC_RX_PAUSE; 3344 3345 return ICE_FC_NONE; 3346 } 3347 3348 /** 3349 * ice_caps_to_fec_mode 3350 * @caps: PHY capabilities 3351 * @fec_options: Link FEC options 3352 * 3353 * Convert PHY FEC capabilities to ice FEC mode 3354 */ 3355 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3356 { 3357 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3358 return ICE_FEC_AUTO; 3359 3360 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3361 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3362 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3363 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3364 return ICE_FEC_BASER; 3365 3366 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3367 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3368 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3369 return ICE_FEC_RS; 3370 3371 return ICE_FEC_NONE; 3372 } 3373 3374 /** 3375 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3376 * @pi: port information structure 3377 * @cfg: PHY configuration data to set FC mode 3378 * @req_mode: FC mode to configure 3379 */ 3380 int 3381 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3382 enum ice_fc_mode req_mode) 3383 { 3384 struct ice_phy_cache_mode_data cache_data; 3385 u8 pause_mask = 0x0; 3386 3387 if (!pi || !cfg) 3388 return -EINVAL; 3389 3390 switch (req_mode) { 3391 case ICE_FC_FULL: 3392 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3393 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3394 break; 3395 case ICE_FC_RX_PAUSE: 3396 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3397 break; 3398 case ICE_FC_TX_PAUSE: 3399 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3400 break; 3401 default: 3402 break; 3403 } 3404 3405 /* clear the old pause settings */ 3406 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3407 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3408 3409 /* set the new capabilities */ 3410 cfg->caps |= pause_mask; 3411 3412 /* Cache user FC request */ 3413 cache_data.data.curr_user_fc_req = req_mode; 3414 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3415 3416 return 0; 3417 } 3418 3419 /** 3420 * ice_set_fc 3421 * @pi: port information structure 3422 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3423 * @ena_auto_link_update: enable automatic link update 3424 * 3425 * Set the requested flow control mode. 3426 */ 3427 int 3428 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3429 { 3430 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3431 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3432 struct ice_hw *hw; 3433 int status; 3434 3435 if (!pi || !aq_failures) 3436 return -EINVAL; 3437 3438 *aq_failures = 0; 3439 hw = pi->hw; 3440 3441 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3442 if (!pcaps) 3443 return -ENOMEM; 3444 3445 /* Get the current PHY config */ 3446 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3447 pcaps, NULL); 3448 if (status) { 3449 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3450 goto out; 3451 } 3452 3453 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3454 3455 /* Configure the set PHY data */ 3456 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3457 if (status) 3458 goto out; 3459 3460 /* If the capabilities have changed, then set the new config */ 3461 if (cfg.caps != pcaps->caps) { 3462 int retry_count, retry_max = 10; 3463 3464 /* Auto restart link so settings take effect */ 3465 if (ena_auto_link_update) 3466 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3467 3468 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3469 if (status) { 3470 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3471 goto out; 3472 } 3473 3474 /* Update the link info 3475 * It sometimes takes a really long time for link to 3476 * come back from the atomic reset. Thus, we wait a 3477 * little bit. 3478 */ 3479 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3480 status = ice_update_link_info(pi); 3481 3482 if (!status) 3483 break; 3484 3485 mdelay(100); 3486 } 3487 3488 if (status) 3489 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3490 } 3491 3492 out: 3493 return status; 3494 } 3495 3496 /** 3497 * ice_phy_caps_equals_cfg 3498 * @phy_caps: PHY capabilities 3499 * @phy_cfg: PHY configuration 3500 * 3501 * Helper function to determine if PHY capabilities matches PHY 3502 * configuration 3503 */ 3504 bool 3505 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3506 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3507 { 3508 u8 caps_mask, cfg_mask; 3509 3510 if (!phy_caps || !phy_cfg) 3511 return false; 3512 3513 /* These bits are not common between capabilities and configuration. 3514 * Do not use them to determine equality. 3515 */ 3516 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3517 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3518 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3519 3520 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3521 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3522 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3523 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3524 phy_caps->eee_cap != phy_cfg->eee_cap || 3525 phy_caps->eeer_value != phy_cfg->eeer_value || 3526 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3527 return false; 3528 3529 return true; 3530 } 3531 3532 /** 3533 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3534 * @pi: port information structure 3535 * @caps: PHY ability structure to copy date from 3536 * @cfg: PHY configuration structure to copy data to 3537 * 3538 * Helper function to copy AQC PHY get ability data to PHY set configuration 3539 * data structure 3540 */ 3541 void 3542 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3543 struct ice_aqc_get_phy_caps_data *caps, 3544 struct ice_aqc_set_phy_cfg_data *cfg) 3545 { 3546 if (!pi || !caps || !cfg) 3547 return; 3548 3549 memset(cfg, 0, sizeof(*cfg)); 3550 cfg->phy_type_low = caps->phy_type_low; 3551 cfg->phy_type_high = caps->phy_type_high; 3552 cfg->caps = caps->caps; 3553 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3554 cfg->eee_cap = caps->eee_cap; 3555 cfg->eeer_value = caps->eeer_value; 3556 cfg->link_fec_opt = caps->link_fec_options; 3557 cfg->module_compliance_enforcement = 3558 caps->module_compliance_enforcement; 3559 } 3560 3561 /** 3562 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3563 * @pi: port information structure 3564 * @cfg: PHY configuration data to set FEC mode 3565 * @fec: FEC mode to configure 3566 */ 3567 int 3568 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3569 enum ice_fec_mode fec) 3570 { 3571 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3572 struct ice_hw *hw; 3573 int status; 3574 3575 if (!pi || !cfg) 3576 return -EINVAL; 3577 3578 hw = pi->hw; 3579 3580 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3581 if (!pcaps) 3582 return -ENOMEM; 3583 3584 status = ice_aq_get_phy_caps(pi, false, 3585 (ice_fw_supports_report_dflt_cfg(hw) ? 3586 ICE_AQC_REPORT_DFLT_CFG : 3587 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3588 if (status) 3589 goto out; 3590 3591 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3592 cfg->link_fec_opt = pcaps->link_fec_options; 3593 3594 switch (fec) { 3595 case ICE_FEC_BASER: 3596 /* Clear RS bits, and AND BASE-R ability 3597 * bits and OR request bits. 3598 */ 3599 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3600 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3601 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3602 ICE_AQC_PHY_FEC_25G_KR_REQ; 3603 break; 3604 case ICE_FEC_RS: 3605 /* Clear BASE-R bits, and AND RS ability 3606 * bits and OR request bits. 3607 */ 3608 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3609 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3610 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3611 break; 3612 case ICE_FEC_NONE: 3613 /* Clear all FEC option bits. */ 3614 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3615 break; 3616 case ICE_FEC_AUTO: 3617 /* AND auto FEC bit, and all caps bits. */ 3618 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3619 cfg->link_fec_opt |= pcaps->link_fec_options; 3620 break; 3621 default: 3622 status = -EINVAL; 3623 break; 3624 } 3625 3626 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3627 !ice_fw_supports_report_dflt_cfg(hw)) { 3628 struct ice_link_default_override_tlv tlv = { 0 }; 3629 3630 status = ice_get_link_default_override(&tlv, pi); 3631 if (status) 3632 goto out; 3633 3634 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3635 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3636 cfg->link_fec_opt = tlv.fec_options; 3637 } 3638 3639 out: 3640 return status; 3641 } 3642 3643 /** 3644 * ice_get_link_status - get status of the HW network link 3645 * @pi: port information structure 3646 * @link_up: pointer to bool (true/false = linkup/linkdown) 3647 * 3648 * Variable link_up is true if link is up, false if link is down. 3649 * The variable link_up is invalid if status is non zero. As a 3650 * result of this call, link status reporting becomes enabled 3651 */ 3652 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3653 { 3654 struct ice_phy_info *phy_info; 3655 int status = 0; 3656 3657 if (!pi || !link_up) 3658 return -EINVAL; 3659 3660 phy_info = &pi->phy; 3661 3662 if (phy_info->get_link_info) { 3663 status = ice_update_link_info(pi); 3664 3665 if (status) 3666 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3667 status); 3668 } 3669 3670 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3671 3672 return status; 3673 } 3674 3675 /** 3676 * ice_aq_set_link_restart_an 3677 * @pi: pointer to the port information structure 3678 * @ena_link: if true: enable link, if false: disable link 3679 * @cd: pointer to command details structure or NULL 3680 * 3681 * Sets up the link and restarts the Auto-Negotiation over the link. 3682 */ 3683 int 3684 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3685 struct ice_sq_cd *cd) 3686 { 3687 struct ice_aqc_restart_an *cmd; 3688 struct ice_aq_desc desc; 3689 3690 cmd = &desc.params.restart_an; 3691 3692 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3693 3694 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3695 cmd->lport_num = pi->lport; 3696 if (ena_link) 3697 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3698 else 3699 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3700 3701 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3702 } 3703 3704 /** 3705 * ice_aq_set_event_mask 3706 * @hw: pointer to the HW struct 3707 * @port_num: port number of the physical function 3708 * @mask: event mask to be set 3709 * @cd: pointer to command details structure or NULL 3710 * 3711 * Set event mask (0x0613) 3712 */ 3713 int 3714 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3715 struct ice_sq_cd *cd) 3716 { 3717 struct ice_aqc_set_event_mask *cmd; 3718 struct ice_aq_desc desc; 3719 3720 cmd = &desc.params.set_event_mask; 3721 3722 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3723 3724 cmd->lport_num = port_num; 3725 3726 cmd->event_mask = cpu_to_le16(mask); 3727 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3728 } 3729 3730 /** 3731 * ice_aq_set_mac_loopback 3732 * @hw: pointer to the HW struct 3733 * @ena_lpbk: Enable or Disable loopback 3734 * @cd: pointer to command details structure or NULL 3735 * 3736 * Enable/disable loopback on a given port 3737 */ 3738 int 3739 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3740 { 3741 struct ice_aqc_set_mac_lb *cmd; 3742 struct ice_aq_desc desc; 3743 3744 cmd = &desc.params.set_mac_lb; 3745 3746 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3747 if (ena_lpbk) 3748 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3749 3750 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3751 } 3752 3753 /** 3754 * ice_aq_set_port_id_led 3755 * @pi: pointer to the port information 3756 * @is_orig_mode: is this LED set to original mode (by the net-list) 3757 * @cd: pointer to command details structure or NULL 3758 * 3759 * Set LED value for the given port (0x06e9) 3760 */ 3761 int 3762 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3763 struct ice_sq_cd *cd) 3764 { 3765 struct ice_aqc_set_port_id_led *cmd; 3766 struct ice_hw *hw = pi->hw; 3767 struct ice_aq_desc desc; 3768 3769 cmd = &desc.params.set_port_id_led; 3770 3771 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3772 3773 if (is_orig_mode) 3774 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3775 else 3776 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3777 3778 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3779 } 3780 3781 /** 3782 * ice_aq_get_port_options 3783 * @hw: pointer to the HW struct 3784 * @options: buffer for the resultant port options 3785 * @option_count: input - size of the buffer in port options structures, 3786 * output - number of returned port options 3787 * @lport: logical port to call the command with (optional) 3788 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3789 * when PF owns more than 1 port it must be true 3790 * @active_option_idx: index of active port option in returned buffer 3791 * @active_option_valid: active option in returned buffer is valid 3792 * @pending_option_idx: index of pending port option in returned buffer 3793 * @pending_option_valid: pending option in returned buffer is valid 3794 * 3795 * Calls Get Port Options AQC (0x06ea) and verifies result. 3796 */ 3797 int 3798 ice_aq_get_port_options(struct ice_hw *hw, 3799 struct ice_aqc_get_port_options_elem *options, 3800 u8 *option_count, u8 lport, bool lport_valid, 3801 u8 *active_option_idx, bool *active_option_valid, 3802 u8 *pending_option_idx, bool *pending_option_valid) 3803 { 3804 struct ice_aqc_get_port_options *cmd; 3805 struct ice_aq_desc desc; 3806 int status; 3807 u8 i; 3808 3809 /* options buffer shall be able to hold max returned options */ 3810 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3811 return -EINVAL; 3812 3813 cmd = &desc.params.get_port_options; 3814 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3815 3816 if (lport_valid) 3817 cmd->lport_num = lport; 3818 cmd->lport_num_valid = lport_valid; 3819 3820 status = ice_aq_send_cmd(hw, &desc, options, 3821 *option_count * sizeof(*options), NULL); 3822 if (status) 3823 return status; 3824 3825 /* verify direct FW response & set output parameters */ 3826 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3827 cmd->port_options_count); 3828 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3829 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3830 cmd->port_options); 3831 if (*active_option_valid) { 3832 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3833 cmd->port_options); 3834 if (*active_option_idx > (*option_count - 1)) 3835 return -EIO; 3836 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3837 *active_option_idx); 3838 } 3839 3840 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3841 cmd->pending_port_option_status); 3842 if (*pending_option_valid) { 3843 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3844 cmd->pending_port_option_status); 3845 if (*pending_option_idx > (*option_count - 1)) 3846 return -EIO; 3847 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3848 *pending_option_idx); 3849 } 3850 3851 /* mask output options fields */ 3852 for (i = 0; i < *option_count; i++) { 3853 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3854 options[i].pmd); 3855 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3856 options[i].max_lane_speed); 3857 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3858 options[i].pmd, options[i].max_lane_speed); 3859 } 3860 3861 return 0; 3862 } 3863 3864 /** 3865 * ice_aq_set_port_option 3866 * @hw: pointer to the HW struct 3867 * @lport: logical port to call the command with 3868 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3869 * when PF owns more than 1 port it must be true 3870 * @new_option: new port option to be written 3871 * 3872 * Calls Set Port Options AQC (0x06eb). 3873 */ 3874 int 3875 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3876 u8 new_option) 3877 { 3878 struct ice_aqc_set_port_option *cmd; 3879 struct ice_aq_desc desc; 3880 3881 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3882 return -EINVAL; 3883 3884 cmd = &desc.params.set_port_option; 3885 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3886 3887 if (lport_valid) 3888 cmd->lport_num = lport; 3889 3890 cmd->lport_num_valid = lport_valid; 3891 cmd->selected_port_option = new_option; 3892 3893 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3894 } 3895 3896 /** 3897 * ice_aq_sff_eeprom 3898 * @hw: pointer to the HW struct 3899 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3900 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3901 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3902 * @page: QSFP page 3903 * @set_page: set or ignore the page 3904 * @data: pointer to data buffer to be read/written to the I2C device. 3905 * @length: 1-16 for read, 1 for write. 3906 * @write: 0 read, 1 for write. 3907 * @cd: pointer to command details structure or NULL 3908 * 3909 * Read/Write SFF EEPROM (0x06EE) 3910 */ 3911 int 3912 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3913 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3914 bool write, struct ice_sq_cd *cd) 3915 { 3916 struct ice_aqc_sff_eeprom *cmd; 3917 struct ice_aq_desc desc; 3918 u16 i2c_bus_addr; 3919 int status; 3920 3921 if (!data || (mem_addr & 0xff00)) 3922 return -EINVAL; 3923 3924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3925 cmd = &desc.params.read_write_sff_param; 3926 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3927 cmd->lport_num = (u8)(lport & 0xff); 3928 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3929 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 3930 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 3931 if (write) 3932 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 3933 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 3934 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3935 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 3936 3937 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3938 return status; 3939 } 3940 3941 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 3942 { 3943 switch (type) { 3944 case ICE_LUT_VSI: 3945 return ICE_LUT_VSI_SIZE; 3946 case ICE_LUT_GLOBAL: 3947 return ICE_LUT_GLOBAL_SIZE; 3948 case ICE_LUT_PF: 3949 return ICE_LUT_PF_SIZE; 3950 } 3951 WARN_ONCE(1, "incorrect type passed"); 3952 return ICE_LUT_VSI_SIZE; 3953 } 3954 3955 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 3956 { 3957 switch (size) { 3958 case ICE_LUT_VSI_SIZE: 3959 return ICE_AQC_LUT_SIZE_SMALL; 3960 case ICE_LUT_GLOBAL_SIZE: 3961 return ICE_AQC_LUT_SIZE_512; 3962 case ICE_LUT_PF_SIZE: 3963 return ICE_AQC_LUT_SIZE_2K; 3964 } 3965 WARN_ONCE(1, "incorrect size passed"); 3966 return 0; 3967 } 3968 3969 /** 3970 * __ice_aq_get_set_rss_lut 3971 * @hw: pointer to the hardware structure 3972 * @params: RSS LUT parameters 3973 * @set: set true to set the table, false to get the table 3974 * 3975 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3976 */ 3977 static int 3978 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 3979 struct ice_aq_get_set_rss_lut_params *params, bool set) 3980 { 3981 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 3982 enum ice_lut_type lut_type = params->lut_type; 3983 struct ice_aqc_get_set_rss_lut *desc_params; 3984 enum ice_aqc_lut_flags flags; 3985 enum ice_lut_size lut_size; 3986 struct ice_aq_desc desc; 3987 u8 *lut = params->lut; 3988 3989 3990 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 3991 return -EINVAL; 3992 3993 lut_size = ice_lut_type_to_size(lut_type); 3994 if (lut_size > params->lut_size) 3995 return -EINVAL; 3996 else if (set && lut_size != params->lut_size) 3997 return -EINVAL; 3998 3999 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4000 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4001 if (set) 4002 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4003 4004 desc_params = &desc.params.get_set_rss_lut; 4005 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4006 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4007 4008 if (lut_type == ICE_LUT_GLOBAL) 4009 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4010 params->global_lut_id); 4011 4012 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4013 desc_params->flags = cpu_to_le16(flags); 4014 4015 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4016 } 4017 4018 /** 4019 * ice_aq_get_rss_lut 4020 * @hw: pointer to the hardware structure 4021 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4022 * 4023 * get the RSS lookup table, PF or VSI type 4024 */ 4025 int 4026 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4027 { 4028 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4029 } 4030 4031 /** 4032 * ice_aq_set_rss_lut 4033 * @hw: pointer to the hardware structure 4034 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4035 * 4036 * set the RSS lookup table, PF or VSI type 4037 */ 4038 int 4039 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4040 { 4041 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4042 } 4043 4044 /** 4045 * __ice_aq_get_set_rss_key 4046 * @hw: pointer to the HW struct 4047 * @vsi_id: VSI FW index 4048 * @key: pointer to key info struct 4049 * @set: set true to set the key, false to get the key 4050 * 4051 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4052 */ 4053 static int 4054 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4055 struct ice_aqc_get_set_rss_keys *key, bool set) 4056 { 4057 struct ice_aqc_get_set_rss_key *desc_params; 4058 u16 key_size = sizeof(*key); 4059 struct ice_aq_desc desc; 4060 4061 if (set) { 4062 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4063 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4064 } else { 4065 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4066 } 4067 4068 desc_params = &desc.params.get_set_rss_key; 4069 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4070 4071 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4072 } 4073 4074 /** 4075 * ice_aq_get_rss_key 4076 * @hw: pointer to the HW struct 4077 * @vsi_handle: software VSI handle 4078 * @key: pointer to key info struct 4079 * 4080 * get the RSS key per VSI 4081 */ 4082 int 4083 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4084 struct ice_aqc_get_set_rss_keys *key) 4085 { 4086 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4087 return -EINVAL; 4088 4089 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4090 key, false); 4091 } 4092 4093 /** 4094 * ice_aq_set_rss_key 4095 * @hw: pointer to the HW struct 4096 * @vsi_handle: software VSI handle 4097 * @keys: pointer to key info struct 4098 * 4099 * set the RSS key per VSI 4100 */ 4101 int 4102 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4103 struct ice_aqc_get_set_rss_keys *keys) 4104 { 4105 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4106 return -EINVAL; 4107 4108 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4109 keys, true); 4110 } 4111 4112 /** 4113 * ice_aq_add_lan_txq 4114 * @hw: pointer to the hardware structure 4115 * @num_qgrps: Number of added queue groups 4116 * @qg_list: list of queue groups to be added 4117 * @buf_size: size of buffer for indirect command 4118 * @cd: pointer to command details structure or NULL 4119 * 4120 * Add Tx LAN queue (0x0C30) 4121 * 4122 * NOTE: 4123 * Prior to calling add Tx LAN queue: 4124 * Initialize the following as part of the Tx queue context: 4125 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4126 * Cache profile and Packet shaper profile. 4127 * 4128 * After add Tx LAN queue AQ command is completed: 4129 * Interrupts should be associated with specific queues, 4130 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4131 * flow. 4132 */ 4133 static int 4134 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4135 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4136 struct ice_sq_cd *cd) 4137 { 4138 struct ice_aqc_add_tx_qgrp *list; 4139 struct ice_aqc_add_txqs *cmd; 4140 struct ice_aq_desc desc; 4141 u16 i, sum_size = 0; 4142 4143 cmd = &desc.params.add_txqs; 4144 4145 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4146 4147 if (!qg_list) 4148 return -EINVAL; 4149 4150 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4151 return -EINVAL; 4152 4153 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4154 sum_size += struct_size(list, txqs, list->num_txqs); 4155 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4156 list->num_txqs); 4157 } 4158 4159 if (buf_size != sum_size) 4160 return -EINVAL; 4161 4162 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4163 4164 cmd->num_qgrps = num_qgrps; 4165 4166 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4167 } 4168 4169 /** 4170 * ice_aq_dis_lan_txq 4171 * @hw: pointer to the hardware structure 4172 * @num_qgrps: number of groups in the list 4173 * @qg_list: the list of groups to disable 4174 * @buf_size: the total size of the qg_list buffer in bytes 4175 * @rst_src: if called due to reset, specifies the reset source 4176 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4177 * @cd: pointer to command details structure or NULL 4178 * 4179 * Disable LAN Tx queue (0x0C31) 4180 */ 4181 static int 4182 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4183 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4184 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4185 struct ice_sq_cd *cd) 4186 { 4187 struct ice_aqc_dis_txq_item *item; 4188 struct ice_aqc_dis_txqs *cmd; 4189 struct ice_aq_desc desc; 4190 u16 vmvf_and_timeout; 4191 u16 i, sz = 0; 4192 int status; 4193 4194 cmd = &desc.params.dis_txqs; 4195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4196 4197 /* qg_list can be NULL only in VM/VF reset flow */ 4198 if (!qg_list && !rst_src) 4199 return -EINVAL; 4200 4201 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4202 return -EINVAL; 4203 4204 cmd->num_entries = num_qgrps; 4205 4206 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4207 4208 switch (rst_src) { 4209 case ICE_VM_RESET: 4210 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4211 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4212 break; 4213 case ICE_VF_RESET: 4214 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4215 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4216 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4217 ICE_AQC_Q_DIS_VMVF_NUM_M; 4218 break; 4219 case ICE_NO_RESET: 4220 default: 4221 break; 4222 } 4223 4224 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4225 4226 /* flush pipe on time out */ 4227 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4228 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4229 if (!qg_list) 4230 goto do_aq; 4231 4232 /* set RD bit to indicate that command buffer is provided by the driver 4233 * and it needs to be read by the firmware 4234 */ 4235 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4236 4237 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4238 u16 item_size = struct_size(item, q_id, item->num_qs); 4239 4240 /* If the num of queues is even, add 2 bytes of padding */ 4241 if ((item->num_qs % 2) == 0) 4242 item_size += 2; 4243 4244 sz += item_size; 4245 4246 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4247 } 4248 4249 if (buf_size != sz) 4250 return -EINVAL; 4251 4252 do_aq: 4253 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4254 if (status) { 4255 if (!qg_list) 4256 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4257 vmvf_num, hw->adminq.sq_last_status); 4258 else 4259 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4260 le16_to_cpu(qg_list[0].q_id[0]), 4261 hw->adminq.sq_last_status); 4262 } 4263 return status; 4264 } 4265 4266 /** 4267 * ice_aq_cfg_lan_txq 4268 * @hw: pointer to the hardware structure 4269 * @buf: buffer for command 4270 * @buf_size: size of buffer in bytes 4271 * @num_qs: number of queues being configured 4272 * @oldport: origination lport 4273 * @newport: destination lport 4274 * @cd: pointer to command details structure or NULL 4275 * 4276 * Move/Configure LAN Tx queue (0x0C32) 4277 * 4278 * There is a better AQ command to use for moving nodes, so only coding 4279 * this one for configuring the node. 4280 */ 4281 int 4282 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4283 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4284 struct ice_sq_cd *cd) 4285 { 4286 struct ice_aqc_cfg_txqs *cmd; 4287 struct ice_aq_desc desc; 4288 int status; 4289 4290 cmd = &desc.params.cfg_txqs; 4291 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4292 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4293 4294 if (!buf) 4295 return -EINVAL; 4296 4297 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4298 cmd->num_qs = num_qs; 4299 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4300 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4301 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4302 cmd->blocked_cgds = 0; 4303 4304 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4305 if (status) 4306 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4307 hw->adminq.sq_last_status); 4308 return status; 4309 } 4310 4311 /** 4312 * ice_aq_add_rdma_qsets 4313 * @hw: pointer to the hardware structure 4314 * @num_qset_grps: Number of RDMA Qset groups 4315 * @qset_list: list of Qset groups to be added 4316 * @buf_size: size of buffer for indirect command 4317 * @cd: pointer to command details structure or NULL 4318 * 4319 * Add Tx RDMA Qsets (0x0C33) 4320 */ 4321 static int 4322 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4323 struct ice_aqc_add_rdma_qset_data *qset_list, 4324 u16 buf_size, struct ice_sq_cd *cd) 4325 { 4326 struct ice_aqc_add_rdma_qset_data *list; 4327 struct ice_aqc_add_rdma_qset *cmd; 4328 struct ice_aq_desc desc; 4329 u16 i, sum_size = 0; 4330 4331 cmd = &desc.params.add_rdma_qset; 4332 4333 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4334 4335 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4336 return -EINVAL; 4337 4338 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4339 u16 num_qsets = le16_to_cpu(list->num_qsets); 4340 4341 sum_size += struct_size(list, rdma_qsets, num_qsets); 4342 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4343 num_qsets); 4344 } 4345 4346 if (buf_size != sum_size) 4347 return -EINVAL; 4348 4349 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4350 4351 cmd->num_qset_grps = num_qset_grps; 4352 4353 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4354 } 4355 4356 /* End of FW Admin Queue command wrappers */ 4357 4358 /** 4359 * ice_pack_ctx_byte - write a byte to a packed context structure 4360 * @src_ctx: unpacked source context structure 4361 * @dest_ctx: packed destination context data 4362 * @ce_info: context element description 4363 */ 4364 static void ice_pack_ctx_byte(u8 *src_ctx, u8 *dest_ctx, 4365 const struct ice_ctx_ele *ce_info) 4366 { 4367 u8 src_byte, dest_byte, mask; 4368 u8 *from, *dest; 4369 u16 shift_width; 4370 4371 /* copy from the next struct field */ 4372 from = src_ctx + ce_info->offset; 4373 4374 /* prepare the bits and mask */ 4375 shift_width = ce_info->lsb % 8; 4376 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4377 4378 src_byte = *from; 4379 src_byte <<= shift_width; 4380 src_byte &= mask; 4381 4382 /* get the current bits from the target bit string */ 4383 dest = dest_ctx + (ce_info->lsb / 8); 4384 4385 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4386 4387 dest_byte &= ~mask; /* get the bits not changing */ 4388 dest_byte |= src_byte; /* add in the new bits */ 4389 4390 /* put it all back */ 4391 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4392 } 4393 4394 /** 4395 * ice_pack_ctx_word - write a word to a packed context structure 4396 * @src_ctx: unpacked source context structure 4397 * @dest_ctx: packed destination context data 4398 * @ce_info: context element description 4399 */ 4400 static void ice_pack_ctx_word(u8 *src_ctx, u8 *dest_ctx, 4401 const struct ice_ctx_ele *ce_info) 4402 { 4403 u16 src_word, mask; 4404 __le16 dest_word; 4405 u8 *from, *dest; 4406 u16 shift_width; 4407 4408 /* copy from the next struct field */ 4409 from = src_ctx + ce_info->offset; 4410 4411 /* prepare the bits and mask */ 4412 shift_width = ce_info->lsb % 8; 4413 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4414 4415 /* don't swizzle the bits until after the mask because the mask bits 4416 * will be in a different bit position on big endian machines 4417 */ 4418 src_word = *(u16 *)from; 4419 src_word <<= shift_width; 4420 src_word &= mask; 4421 4422 /* get the current bits from the target bit string */ 4423 dest = dest_ctx + (ce_info->lsb / 8); 4424 4425 memcpy(&dest_word, dest, sizeof(dest_word)); 4426 4427 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4428 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4429 4430 /* put it all back */ 4431 memcpy(dest, &dest_word, sizeof(dest_word)); 4432 } 4433 4434 /** 4435 * ice_pack_ctx_dword - write a dword to a packed context structure 4436 * @src_ctx: unpacked source context structure 4437 * @dest_ctx: packed destination context data 4438 * @ce_info: context element description 4439 */ 4440 static void ice_pack_ctx_dword(u8 *src_ctx, u8 *dest_ctx, 4441 const struct ice_ctx_ele *ce_info) 4442 { 4443 u32 src_dword, mask; 4444 __le32 dest_dword; 4445 u8 *from, *dest; 4446 u16 shift_width; 4447 4448 /* copy from the next struct field */ 4449 from = src_ctx + ce_info->offset; 4450 4451 /* prepare the bits and mask */ 4452 shift_width = ce_info->lsb % 8; 4453 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width); 4454 4455 /* don't swizzle the bits until after the mask because the mask bits 4456 * will be in a different bit position on big endian machines 4457 */ 4458 src_dword = *(u32 *)from; 4459 src_dword <<= shift_width; 4460 src_dword &= mask; 4461 4462 /* get the current bits from the target bit string */ 4463 dest = dest_ctx + (ce_info->lsb / 8); 4464 4465 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4466 4467 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4468 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4469 4470 /* put it all back */ 4471 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4472 } 4473 4474 /** 4475 * ice_pack_ctx_qword - write a qword to a packed context structure 4476 * @src_ctx: unpacked source context structure 4477 * @dest_ctx: packed destination context data 4478 * @ce_info: context element description 4479 */ 4480 static void ice_pack_ctx_qword(u8 *src_ctx, u8 *dest_ctx, 4481 const struct ice_ctx_ele *ce_info) 4482 { 4483 u64 src_qword, mask; 4484 __le64 dest_qword; 4485 u8 *from, *dest; 4486 u16 shift_width; 4487 4488 /* copy from the next struct field */ 4489 from = src_ctx + ce_info->offset; 4490 4491 /* prepare the bits and mask */ 4492 shift_width = ce_info->lsb % 8; 4493 mask = GENMASK_ULL(ce_info->width - 1 + shift_width, shift_width); 4494 4495 /* don't swizzle the bits until after the mask because the mask bits 4496 * will be in a different bit position on big endian machines 4497 */ 4498 src_qword = *(u64 *)from; 4499 src_qword <<= shift_width; 4500 src_qword &= mask; 4501 4502 /* get the current bits from the target bit string */ 4503 dest = dest_ctx + (ce_info->lsb / 8); 4504 4505 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4506 4507 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4508 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4509 4510 /* put it all back */ 4511 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4512 } 4513 4514 /** 4515 * ice_set_ctx - set context bits in packed structure 4516 * @hw: pointer to the hardware structure 4517 * @src_ctx: pointer to a generic non-packed context structure 4518 * @dest_ctx: pointer to memory for the packed structure 4519 * @ce_info: List of Rx context elements 4520 */ 4521 int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4522 const struct ice_ctx_ele *ce_info) 4523 { 4524 int f; 4525 4526 for (f = 0; ce_info[f].width; f++) { 4527 /* We have to deal with each element of the FW response 4528 * using the correct size so that we are correct regardless 4529 * of the endianness of the machine. 4530 */ 4531 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4532 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4533 f, ce_info[f].width, ce_info[f].size_of); 4534 continue; 4535 } 4536 switch (ce_info[f].size_of) { 4537 case sizeof(u8): 4538 ice_pack_ctx_byte(src_ctx, dest_ctx, &ce_info[f]); 4539 break; 4540 case sizeof(u16): 4541 ice_pack_ctx_word(src_ctx, dest_ctx, &ce_info[f]); 4542 break; 4543 case sizeof(u32): 4544 ice_pack_ctx_dword(src_ctx, dest_ctx, &ce_info[f]); 4545 break; 4546 case sizeof(u64): 4547 ice_pack_ctx_qword(src_ctx, dest_ctx, &ce_info[f]); 4548 break; 4549 default: 4550 return -EINVAL; 4551 } 4552 } 4553 4554 return 0; 4555 } 4556 4557 /** 4558 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4559 * @hw: pointer to the HW struct 4560 * @vsi_handle: software VSI handle 4561 * @tc: TC number 4562 * @q_handle: software queue handle 4563 */ 4564 struct ice_q_ctx * 4565 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4566 { 4567 struct ice_vsi_ctx *vsi; 4568 struct ice_q_ctx *q_ctx; 4569 4570 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4571 if (!vsi) 4572 return NULL; 4573 if (q_handle >= vsi->num_lan_q_entries[tc]) 4574 return NULL; 4575 if (!vsi->lan_q_ctx[tc]) 4576 return NULL; 4577 q_ctx = vsi->lan_q_ctx[tc]; 4578 return &q_ctx[q_handle]; 4579 } 4580 4581 /** 4582 * ice_ena_vsi_txq 4583 * @pi: port information structure 4584 * @vsi_handle: software VSI handle 4585 * @tc: TC number 4586 * @q_handle: software queue handle 4587 * @num_qgrps: Number of added queue groups 4588 * @buf: list of queue groups to be added 4589 * @buf_size: size of buffer for indirect command 4590 * @cd: pointer to command details structure or NULL 4591 * 4592 * This function adds one LAN queue 4593 */ 4594 int 4595 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4596 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4597 struct ice_sq_cd *cd) 4598 { 4599 struct ice_aqc_txsched_elem_data node = { 0 }; 4600 struct ice_sched_node *parent; 4601 struct ice_q_ctx *q_ctx; 4602 struct ice_hw *hw; 4603 int status; 4604 4605 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4606 return -EIO; 4607 4608 if (num_qgrps > 1 || buf->num_txqs > 1) 4609 return -ENOSPC; 4610 4611 hw = pi->hw; 4612 4613 if (!ice_is_vsi_valid(hw, vsi_handle)) 4614 return -EINVAL; 4615 4616 mutex_lock(&pi->sched_lock); 4617 4618 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4619 if (!q_ctx) { 4620 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4621 q_handle); 4622 status = -EINVAL; 4623 goto ena_txq_exit; 4624 } 4625 4626 /* find a parent node */ 4627 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4628 ICE_SCHED_NODE_OWNER_LAN); 4629 if (!parent) { 4630 status = -EINVAL; 4631 goto ena_txq_exit; 4632 } 4633 4634 buf->parent_teid = parent->info.node_teid; 4635 node.parent_teid = parent->info.node_teid; 4636 /* Mark that the values in the "generic" section as valid. The default 4637 * value in the "generic" section is zero. This means that : 4638 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4639 * - 0 priority among siblings, indicated by Bit 1-3. 4640 * - WFQ, indicated by Bit 4. 4641 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4642 * Bit 5-6. 4643 * - Bit 7 is reserved. 4644 * Without setting the generic section as valid in valid_sections, the 4645 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4646 */ 4647 buf->txqs[0].info.valid_sections = 4648 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4649 ICE_AQC_ELEM_VALID_EIR; 4650 buf->txqs[0].info.generic = 0; 4651 buf->txqs[0].info.cir_bw.bw_profile_idx = 4652 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4653 buf->txqs[0].info.cir_bw.bw_alloc = 4654 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4655 buf->txqs[0].info.eir_bw.bw_profile_idx = 4656 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4657 buf->txqs[0].info.eir_bw.bw_alloc = 4658 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4659 4660 /* add the LAN queue */ 4661 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4662 if (status) { 4663 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4664 le16_to_cpu(buf->txqs[0].txq_id), 4665 hw->adminq.sq_last_status); 4666 goto ena_txq_exit; 4667 } 4668 4669 node.node_teid = buf->txqs[0].q_teid; 4670 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4671 q_ctx->q_handle = q_handle; 4672 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4673 4674 /* add a leaf node into scheduler tree queue layer */ 4675 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4676 if (!status) 4677 status = ice_sched_replay_q_bw(pi, q_ctx); 4678 4679 ena_txq_exit: 4680 mutex_unlock(&pi->sched_lock); 4681 return status; 4682 } 4683 4684 /** 4685 * ice_dis_vsi_txq 4686 * @pi: port information structure 4687 * @vsi_handle: software VSI handle 4688 * @tc: TC number 4689 * @num_queues: number of queues 4690 * @q_handles: pointer to software queue handle array 4691 * @q_ids: pointer to the q_id array 4692 * @q_teids: pointer to queue node teids 4693 * @rst_src: if called due to reset, specifies the reset source 4694 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4695 * @cd: pointer to command details structure or NULL 4696 * 4697 * This function removes queues and their corresponding nodes in SW DB 4698 */ 4699 int 4700 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4701 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4702 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4703 struct ice_sq_cd *cd) 4704 { 4705 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4706 u16 i, buf_size = __struct_size(qg_list); 4707 struct ice_q_ctx *q_ctx; 4708 int status = -ENOENT; 4709 struct ice_hw *hw; 4710 4711 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4712 return -EIO; 4713 4714 hw = pi->hw; 4715 4716 if (!num_queues) { 4717 /* if queue is disabled already yet the disable queue command 4718 * has to be sent to complete the VF reset, then call 4719 * ice_aq_dis_lan_txq without any queue information 4720 */ 4721 if (rst_src) 4722 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4723 vmvf_num, NULL); 4724 return -EIO; 4725 } 4726 4727 mutex_lock(&pi->sched_lock); 4728 4729 for (i = 0; i < num_queues; i++) { 4730 struct ice_sched_node *node; 4731 4732 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4733 if (!node) 4734 continue; 4735 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4736 if (!q_ctx) { 4737 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4738 q_handles[i]); 4739 continue; 4740 } 4741 if (q_ctx->q_handle != q_handles[i]) { 4742 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4743 q_ctx->q_handle, q_handles[i]); 4744 continue; 4745 } 4746 qg_list->parent_teid = node->info.parent_teid; 4747 qg_list->num_qs = 1; 4748 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4749 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4750 vmvf_num, cd); 4751 4752 if (status) 4753 break; 4754 ice_free_sched_node(pi, node); 4755 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4756 q_ctx->q_teid = ICE_INVAL_TEID; 4757 } 4758 mutex_unlock(&pi->sched_lock); 4759 return status; 4760 } 4761 4762 /** 4763 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4764 * @pi: port information structure 4765 * @vsi_handle: software VSI handle 4766 * @tc_bitmap: TC bitmap 4767 * @maxqs: max queues array per TC 4768 * @owner: LAN or RDMA 4769 * 4770 * This function adds/updates the VSI queues per TC. 4771 */ 4772 static int 4773 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4774 u16 *maxqs, u8 owner) 4775 { 4776 int status = 0; 4777 u8 i; 4778 4779 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4780 return -EIO; 4781 4782 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4783 return -EINVAL; 4784 4785 mutex_lock(&pi->sched_lock); 4786 4787 ice_for_each_traffic_class(i) { 4788 /* configuration is possible only if TC node is present */ 4789 if (!ice_sched_get_tc_node(pi, i)) 4790 continue; 4791 4792 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4793 ice_is_tc_ena(tc_bitmap, i)); 4794 if (status) 4795 break; 4796 } 4797 4798 mutex_unlock(&pi->sched_lock); 4799 return status; 4800 } 4801 4802 /** 4803 * ice_cfg_vsi_lan - configure VSI LAN queues 4804 * @pi: port information structure 4805 * @vsi_handle: software VSI handle 4806 * @tc_bitmap: TC bitmap 4807 * @max_lanqs: max LAN queues array per TC 4808 * 4809 * This function adds/updates the VSI LAN queues per TC. 4810 */ 4811 int 4812 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4813 u16 *max_lanqs) 4814 { 4815 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4816 ICE_SCHED_NODE_OWNER_LAN); 4817 } 4818 4819 /** 4820 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4821 * @pi: port information structure 4822 * @vsi_handle: software VSI handle 4823 * @tc_bitmap: TC bitmap 4824 * @max_rdmaqs: max RDMA queues array per TC 4825 * 4826 * This function adds/updates the VSI RDMA queues per TC. 4827 */ 4828 int 4829 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4830 u16 *max_rdmaqs) 4831 { 4832 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4833 ICE_SCHED_NODE_OWNER_RDMA); 4834 } 4835 4836 /** 4837 * ice_ena_vsi_rdma_qset 4838 * @pi: port information structure 4839 * @vsi_handle: software VSI handle 4840 * @tc: TC number 4841 * @rdma_qset: pointer to RDMA Qset 4842 * @num_qsets: number of RDMA Qsets 4843 * @qset_teid: pointer to Qset node TEIDs 4844 * 4845 * This function adds RDMA Qset 4846 */ 4847 int 4848 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4849 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4850 { 4851 struct ice_aqc_txsched_elem_data node = { 0 }; 4852 struct ice_aqc_add_rdma_qset_data *buf; 4853 struct ice_sched_node *parent; 4854 struct ice_hw *hw; 4855 u16 i, buf_size; 4856 int ret; 4857 4858 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4859 return -EIO; 4860 hw = pi->hw; 4861 4862 if (!ice_is_vsi_valid(hw, vsi_handle)) 4863 return -EINVAL; 4864 4865 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4866 buf = kzalloc(buf_size, GFP_KERNEL); 4867 if (!buf) 4868 return -ENOMEM; 4869 mutex_lock(&pi->sched_lock); 4870 4871 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4872 ICE_SCHED_NODE_OWNER_RDMA); 4873 if (!parent) { 4874 ret = -EINVAL; 4875 goto rdma_error_exit; 4876 } 4877 buf->parent_teid = parent->info.node_teid; 4878 node.parent_teid = parent->info.node_teid; 4879 4880 buf->num_qsets = cpu_to_le16(num_qsets); 4881 for (i = 0; i < num_qsets; i++) { 4882 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4883 buf->rdma_qsets[i].info.valid_sections = 4884 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4885 ICE_AQC_ELEM_VALID_EIR; 4886 buf->rdma_qsets[i].info.generic = 0; 4887 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4888 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4889 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4890 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4891 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4892 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4893 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4894 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4895 } 4896 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4897 if (ret) { 4898 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4899 goto rdma_error_exit; 4900 } 4901 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4902 for (i = 0; i < num_qsets; i++) { 4903 node.node_teid = buf->rdma_qsets[i].qset_teid; 4904 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4905 &node, NULL); 4906 if (ret) 4907 break; 4908 qset_teid[i] = le32_to_cpu(node.node_teid); 4909 } 4910 rdma_error_exit: 4911 mutex_unlock(&pi->sched_lock); 4912 kfree(buf); 4913 return ret; 4914 } 4915 4916 /** 4917 * ice_dis_vsi_rdma_qset - free RDMA resources 4918 * @pi: port_info struct 4919 * @count: number of RDMA Qsets to free 4920 * @qset_teid: TEID of Qset node 4921 * @q_id: list of queue IDs being disabled 4922 */ 4923 int 4924 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4925 u16 *q_id) 4926 { 4927 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4928 u16 qg_size = __struct_size(qg_list); 4929 struct ice_hw *hw; 4930 int status = 0; 4931 int i; 4932 4933 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4934 return -EIO; 4935 4936 hw = pi->hw; 4937 4938 mutex_lock(&pi->sched_lock); 4939 4940 for (i = 0; i < count; i++) { 4941 struct ice_sched_node *node; 4942 4943 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4944 if (!node) 4945 continue; 4946 4947 qg_list->parent_teid = node->info.parent_teid; 4948 qg_list->num_qs = 1; 4949 qg_list->q_id[0] = 4950 cpu_to_le16(q_id[i] | 4951 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4952 4953 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4954 ICE_NO_RESET, 0, NULL); 4955 if (status) 4956 break; 4957 4958 ice_free_sched_node(pi, node); 4959 } 4960 4961 mutex_unlock(&pi->sched_lock); 4962 return status; 4963 } 4964 4965 /** 4966 * ice_aq_get_cgu_abilities - get cgu abilities 4967 * @hw: pointer to the HW struct 4968 * @abilities: CGU abilities 4969 * 4970 * Get CGU abilities (0x0C61) 4971 * Return: 0 on success or negative value on failure. 4972 */ 4973 int 4974 ice_aq_get_cgu_abilities(struct ice_hw *hw, 4975 struct ice_aqc_get_cgu_abilities *abilities) 4976 { 4977 struct ice_aq_desc desc; 4978 4979 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 4980 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 4981 } 4982 4983 /** 4984 * ice_aq_set_input_pin_cfg - set input pin config 4985 * @hw: pointer to the HW struct 4986 * @input_idx: Input index 4987 * @flags1: Input flags 4988 * @flags2: Input flags 4989 * @freq: Frequency in Hz 4990 * @phase_delay: Delay in ps 4991 * 4992 * Set CGU input config (0x0C62) 4993 * Return: 0 on success or negative value on failure. 4994 */ 4995 int 4996 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 4997 u32 freq, s32 phase_delay) 4998 { 4999 struct ice_aqc_set_cgu_input_config *cmd; 5000 struct ice_aq_desc desc; 5001 5002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5003 cmd = &desc.params.set_cgu_input_config; 5004 cmd->input_idx = input_idx; 5005 cmd->flags1 = flags1; 5006 cmd->flags2 = flags2; 5007 cmd->freq = cpu_to_le32(freq); 5008 cmd->phase_delay = cpu_to_le32(phase_delay); 5009 5010 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5011 } 5012 5013 /** 5014 * ice_aq_get_input_pin_cfg - get input pin config 5015 * @hw: pointer to the HW struct 5016 * @input_idx: Input index 5017 * @status: Pin status 5018 * @type: Pin type 5019 * @flags1: Input flags 5020 * @flags2: Input flags 5021 * @freq: Frequency in Hz 5022 * @phase_delay: Delay in ps 5023 * 5024 * Get CGU input config (0x0C63) 5025 * Return: 0 on success or negative value on failure. 5026 */ 5027 int 5028 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5029 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5030 { 5031 struct ice_aqc_get_cgu_input_config *cmd; 5032 struct ice_aq_desc desc; 5033 int ret; 5034 5035 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5036 cmd = &desc.params.get_cgu_input_config; 5037 cmd->input_idx = input_idx; 5038 5039 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5040 if (!ret) { 5041 if (status) 5042 *status = cmd->status; 5043 if (type) 5044 *type = cmd->type; 5045 if (flags1) 5046 *flags1 = cmd->flags1; 5047 if (flags2) 5048 *flags2 = cmd->flags2; 5049 if (freq) 5050 *freq = le32_to_cpu(cmd->freq); 5051 if (phase_delay) 5052 *phase_delay = le32_to_cpu(cmd->phase_delay); 5053 } 5054 5055 return ret; 5056 } 5057 5058 /** 5059 * ice_aq_set_output_pin_cfg - set output pin config 5060 * @hw: pointer to the HW struct 5061 * @output_idx: Output index 5062 * @flags: Output flags 5063 * @src_sel: Index of DPLL block 5064 * @freq: Output frequency 5065 * @phase_delay: Output phase compensation 5066 * 5067 * Set CGU output config (0x0C64) 5068 * Return: 0 on success or negative value on failure. 5069 */ 5070 int 5071 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5072 u8 src_sel, u32 freq, s32 phase_delay) 5073 { 5074 struct ice_aqc_set_cgu_output_config *cmd; 5075 struct ice_aq_desc desc; 5076 5077 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5078 cmd = &desc.params.set_cgu_output_config; 5079 cmd->output_idx = output_idx; 5080 cmd->flags = flags; 5081 cmd->src_sel = src_sel; 5082 cmd->freq = cpu_to_le32(freq); 5083 cmd->phase_delay = cpu_to_le32(phase_delay); 5084 5085 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5086 } 5087 5088 /** 5089 * ice_aq_get_output_pin_cfg - get output pin config 5090 * @hw: pointer to the HW struct 5091 * @output_idx: Output index 5092 * @flags: Output flags 5093 * @src_sel: Internal DPLL source 5094 * @freq: Output frequency 5095 * @src_freq: Source frequency 5096 * 5097 * Get CGU output config (0x0C65) 5098 * Return: 0 on success or negative value on failure. 5099 */ 5100 int 5101 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5102 u8 *src_sel, u32 *freq, u32 *src_freq) 5103 { 5104 struct ice_aqc_get_cgu_output_config *cmd; 5105 struct ice_aq_desc desc; 5106 int ret; 5107 5108 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5109 cmd = &desc.params.get_cgu_output_config; 5110 cmd->output_idx = output_idx; 5111 5112 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5113 if (!ret) { 5114 if (flags) 5115 *flags = cmd->flags; 5116 if (src_sel) 5117 *src_sel = cmd->src_sel; 5118 if (freq) 5119 *freq = le32_to_cpu(cmd->freq); 5120 if (src_freq) 5121 *src_freq = le32_to_cpu(cmd->src_freq); 5122 } 5123 5124 return ret; 5125 } 5126 5127 /** 5128 * ice_aq_get_cgu_dpll_status - get dpll status 5129 * @hw: pointer to the HW struct 5130 * @dpll_num: DPLL index 5131 * @ref_state: Reference clock state 5132 * @config: current DPLL config 5133 * @dpll_state: current DPLL state 5134 * @phase_offset: Phase offset in ns 5135 * @eec_mode: EEC_mode 5136 * 5137 * Get CGU DPLL status (0x0C66) 5138 * Return: 0 on success or negative value on failure. 5139 */ 5140 int 5141 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5142 u8 *dpll_state, u8 *config, s64 *phase_offset, 5143 u8 *eec_mode) 5144 { 5145 struct ice_aqc_get_cgu_dpll_status *cmd; 5146 struct ice_aq_desc desc; 5147 int status; 5148 5149 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5150 cmd = &desc.params.get_cgu_dpll_status; 5151 cmd->dpll_num = dpll_num; 5152 5153 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5154 if (!status) { 5155 *ref_state = cmd->ref_state; 5156 *dpll_state = cmd->dpll_state; 5157 *config = cmd->config; 5158 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5159 *phase_offset <<= 32; 5160 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5161 *phase_offset = sign_extend64(*phase_offset, 47); 5162 *eec_mode = cmd->eec_mode; 5163 } 5164 5165 return status; 5166 } 5167 5168 /** 5169 * ice_aq_set_cgu_dpll_config - set dpll config 5170 * @hw: pointer to the HW struct 5171 * @dpll_num: DPLL index 5172 * @ref_state: Reference clock state 5173 * @config: DPLL config 5174 * @eec_mode: EEC mode 5175 * 5176 * Set CGU DPLL config (0x0C67) 5177 * Return: 0 on success or negative value on failure. 5178 */ 5179 int 5180 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5181 u8 config, u8 eec_mode) 5182 { 5183 struct ice_aqc_set_cgu_dpll_config *cmd; 5184 struct ice_aq_desc desc; 5185 5186 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5187 cmd = &desc.params.set_cgu_dpll_config; 5188 cmd->dpll_num = dpll_num; 5189 cmd->ref_state = ref_state; 5190 cmd->config = config; 5191 cmd->eec_mode = eec_mode; 5192 5193 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5194 } 5195 5196 /** 5197 * ice_aq_set_cgu_ref_prio - set input reference priority 5198 * @hw: pointer to the HW struct 5199 * @dpll_num: DPLL index 5200 * @ref_idx: Reference pin index 5201 * @ref_priority: Reference input priority 5202 * 5203 * Set CGU reference priority (0x0C68) 5204 * Return: 0 on success or negative value on failure. 5205 */ 5206 int 5207 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5208 u8 ref_priority) 5209 { 5210 struct ice_aqc_set_cgu_ref_prio *cmd; 5211 struct ice_aq_desc desc; 5212 5213 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5214 cmd = &desc.params.set_cgu_ref_prio; 5215 cmd->dpll_num = dpll_num; 5216 cmd->ref_idx = ref_idx; 5217 cmd->ref_priority = ref_priority; 5218 5219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5220 } 5221 5222 /** 5223 * ice_aq_get_cgu_ref_prio - get input reference priority 5224 * @hw: pointer to the HW struct 5225 * @dpll_num: DPLL index 5226 * @ref_idx: Reference pin index 5227 * @ref_prio: Reference input priority 5228 * 5229 * Get CGU reference priority (0x0C69) 5230 * Return: 0 on success or negative value on failure. 5231 */ 5232 int 5233 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5234 u8 *ref_prio) 5235 { 5236 struct ice_aqc_get_cgu_ref_prio *cmd; 5237 struct ice_aq_desc desc; 5238 int status; 5239 5240 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5241 cmd = &desc.params.get_cgu_ref_prio; 5242 cmd->dpll_num = dpll_num; 5243 cmd->ref_idx = ref_idx; 5244 5245 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5246 if (!status) 5247 *ref_prio = cmd->ref_priority; 5248 5249 return status; 5250 } 5251 5252 /** 5253 * ice_aq_get_cgu_info - get cgu info 5254 * @hw: pointer to the HW struct 5255 * @cgu_id: CGU ID 5256 * @cgu_cfg_ver: CGU config version 5257 * @cgu_fw_ver: CGU firmware version 5258 * 5259 * Get CGU info (0x0C6A) 5260 * Return: 0 on success or negative value on failure. 5261 */ 5262 int 5263 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5264 u32 *cgu_fw_ver) 5265 { 5266 struct ice_aqc_get_cgu_info *cmd; 5267 struct ice_aq_desc desc; 5268 int status; 5269 5270 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5271 cmd = &desc.params.get_cgu_info; 5272 5273 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5274 if (!status) { 5275 *cgu_id = le32_to_cpu(cmd->cgu_id); 5276 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5277 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5278 } 5279 5280 return status; 5281 } 5282 5283 /** 5284 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5285 * @hw: pointer to the HW struct 5286 * @phy_output: PHY reference clock output pin 5287 * @enable: GPIO state to be applied 5288 * @freq: PHY output frequency 5289 * 5290 * Set phy recovered clock as reference (0x0630) 5291 * Return: 0 on success or negative value on failure. 5292 */ 5293 int 5294 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5295 u32 *freq) 5296 { 5297 struct ice_aqc_set_phy_rec_clk_out *cmd; 5298 struct ice_aq_desc desc; 5299 int status; 5300 5301 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5302 cmd = &desc.params.set_phy_rec_clk_out; 5303 cmd->phy_output = phy_output; 5304 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5305 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5306 cmd->freq = cpu_to_le32(*freq); 5307 5308 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5309 if (!status) 5310 *freq = le32_to_cpu(cmd->freq); 5311 5312 return status; 5313 } 5314 5315 /** 5316 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5317 * @hw: pointer to the HW struct 5318 * @phy_output: PHY reference clock output pin 5319 * @port_num: Port number 5320 * @flags: PHY flags 5321 * @node_handle: PHY output frequency 5322 * 5323 * Get PHY recovered clock output info (0x0631) 5324 * Return: 0 on success or negative value on failure. 5325 */ 5326 int 5327 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5328 u8 *flags, u16 *node_handle) 5329 { 5330 struct ice_aqc_get_phy_rec_clk_out *cmd; 5331 struct ice_aq_desc desc; 5332 int status; 5333 5334 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5335 cmd = &desc.params.get_phy_rec_clk_out; 5336 cmd->phy_output = *phy_output; 5337 5338 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5339 if (!status) { 5340 *phy_output = cmd->phy_output; 5341 if (port_num) 5342 *port_num = cmd->port_num; 5343 if (flags) 5344 *flags = cmd->flags; 5345 if (node_handle) 5346 *node_handle = le16_to_cpu(cmd->node_handle); 5347 } 5348 5349 return status; 5350 } 5351 5352 /** 5353 * ice_aq_get_sensor_reading 5354 * @hw: pointer to the HW struct 5355 * @data: pointer to data to be read from the sensor 5356 * 5357 * Get sensor reading (0x0632) 5358 */ 5359 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5360 struct ice_aqc_get_sensor_reading_resp *data) 5361 { 5362 struct ice_aqc_get_sensor_reading *cmd; 5363 struct ice_aq_desc desc; 5364 int status; 5365 5366 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5367 cmd = &desc.params.get_sensor_reading; 5368 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5369 #define ICE_INTERNAL_TEMP_SENSOR 0 5370 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5371 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5372 5373 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5374 if (!status) 5375 memcpy(data, &desc.params.get_sensor_reading_resp, 5376 sizeof(*data)); 5377 5378 return status; 5379 } 5380 5381 /** 5382 * ice_replay_pre_init - replay pre initialization 5383 * @hw: pointer to the HW struct 5384 * 5385 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5386 */ 5387 static int ice_replay_pre_init(struct ice_hw *hw) 5388 { 5389 struct ice_switch_info *sw = hw->switch_info; 5390 u8 i; 5391 5392 /* Delete old entries from replay filter list head if there is any */ 5393 ice_rm_all_sw_replay_rule_info(hw); 5394 /* In start of replay, move entries into replay_rules list, it 5395 * will allow adding rules entries back to filt_rules list, 5396 * which is operational list. 5397 */ 5398 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5399 list_replace_init(&sw->recp_list[i].filt_rules, 5400 &sw->recp_list[i].filt_replay_rules); 5401 ice_sched_replay_agg_vsi_preinit(hw); 5402 5403 return 0; 5404 } 5405 5406 /** 5407 * ice_replay_vsi - replay VSI configuration 5408 * @hw: pointer to the HW struct 5409 * @vsi_handle: driver VSI handle 5410 * 5411 * Restore all VSI configuration after reset. It is required to call this 5412 * function with main VSI first. 5413 */ 5414 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5415 { 5416 int status; 5417 5418 if (!ice_is_vsi_valid(hw, vsi_handle)) 5419 return -EINVAL; 5420 5421 /* Replay pre-initialization if there is any */ 5422 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5423 status = ice_replay_pre_init(hw); 5424 if (status) 5425 return status; 5426 } 5427 /* Replay per VSI all RSS configurations */ 5428 status = ice_replay_rss_cfg(hw, vsi_handle); 5429 if (status) 5430 return status; 5431 /* Replay per VSI all filters */ 5432 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5433 if (!status) 5434 status = ice_replay_vsi_agg(hw, vsi_handle); 5435 return status; 5436 } 5437 5438 /** 5439 * ice_replay_post - post replay configuration cleanup 5440 * @hw: pointer to the HW struct 5441 * 5442 * Post replay cleanup. 5443 */ 5444 void ice_replay_post(struct ice_hw *hw) 5445 { 5446 /* Delete old entries from replay filter list head */ 5447 ice_rm_all_sw_replay_rule_info(hw); 5448 ice_sched_replay_agg(hw); 5449 } 5450 5451 /** 5452 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5453 * @hw: ptr to the hardware info 5454 * @reg: offset of 64 bit HW register to read from 5455 * @prev_stat_loaded: bool to specify if previous stats are loaded 5456 * @prev_stat: ptr to previous loaded stat value 5457 * @cur_stat: ptr to current stat value 5458 */ 5459 void 5460 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5461 u64 *prev_stat, u64 *cur_stat) 5462 { 5463 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5464 5465 /* device stats are not reset at PFR, they likely will not be zeroed 5466 * when the driver starts. Thus, save the value from the first read 5467 * without adding to the statistic value so that we report stats which 5468 * count up from zero. 5469 */ 5470 if (!prev_stat_loaded) { 5471 *prev_stat = new_data; 5472 return; 5473 } 5474 5475 /* Calculate the difference between the new and old values, and then 5476 * add it to the software stat value. 5477 */ 5478 if (new_data >= *prev_stat) 5479 *cur_stat += new_data - *prev_stat; 5480 else 5481 /* to manage the potential roll-over */ 5482 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5483 5484 /* Update the previously stored value to prepare for next read */ 5485 *prev_stat = new_data; 5486 } 5487 5488 /** 5489 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5490 * @hw: ptr to the hardware info 5491 * @reg: offset of HW register to read from 5492 * @prev_stat_loaded: bool to specify if previous stats are loaded 5493 * @prev_stat: ptr to previous loaded stat value 5494 * @cur_stat: ptr to current stat value 5495 */ 5496 void 5497 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5498 u64 *prev_stat, u64 *cur_stat) 5499 { 5500 u32 new_data; 5501 5502 new_data = rd32(hw, reg); 5503 5504 /* device stats are not reset at PFR, they likely will not be zeroed 5505 * when the driver starts. Thus, save the value from the first read 5506 * without adding to the statistic value so that we report stats which 5507 * count up from zero. 5508 */ 5509 if (!prev_stat_loaded) { 5510 *prev_stat = new_data; 5511 return; 5512 } 5513 5514 /* Calculate the difference between the new and old values, and then 5515 * add it to the software stat value. 5516 */ 5517 if (new_data >= *prev_stat) 5518 *cur_stat += new_data - *prev_stat; 5519 else 5520 /* to manage the potential roll-over */ 5521 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5522 5523 /* Update the previously stored value to prepare for next read */ 5524 *prev_stat = new_data; 5525 } 5526 5527 /** 5528 * ice_sched_query_elem - query element information from HW 5529 * @hw: pointer to the HW struct 5530 * @node_teid: node TEID to be queried 5531 * @buf: buffer to element information 5532 * 5533 * This function queries HW element information 5534 */ 5535 int 5536 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5537 struct ice_aqc_txsched_elem_data *buf) 5538 { 5539 u16 buf_size, num_elem_ret = 0; 5540 int status; 5541 5542 buf_size = sizeof(*buf); 5543 memset(buf, 0, buf_size); 5544 buf->node_teid = cpu_to_le32(node_teid); 5545 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5546 NULL); 5547 if (status || num_elem_ret != 1) 5548 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5549 return status; 5550 } 5551 5552 /** 5553 * ice_aq_read_i2c 5554 * @hw: pointer to the hw struct 5555 * @topo_addr: topology address for a device to communicate with 5556 * @bus_addr: 7-bit I2C bus address 5557 * @addr: I2C memory address (I2C offset) with up to 16 bits 5558 * @params: I2C parameters: bit [7] - Repeated start, 5559 * bits [6:5] data offset size, 5560 * bit [4] - I2C address type, 5561 * bits [3:0] - data size to read (0-16 bytes) 5562 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5563 * @cd: pointer to command details structure or NULL 5564 * 5565 * Read I2C (0x06E2) 5566 */ 5567 int 5568 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5569 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5570 struct ice_sq_cd *cd) 5571 { 5572 struct ice_aq_desc desc = { 0 }; 5573 struct ice_aqc_i2c *cmd; 5574 u8 data_size; 5575 int status; 5576 5577 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5578 cmd = &desc.params.read_write_i2c; 5579 5580 if (!data) 5581 return -EINVAL; 5582 5583 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5584 5585 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5586 cmd->topo_addr = topo_addr; 5587 cmd->i2c_params = params; 5588 cmd->i2c_addr = addr; 5589 5590 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5591 if (!status) { 5592 struct ice_aqc_read_i2c_resp *resp; 5593 u8 i; 5594 5595 resp = &desc.params.read_i2c_resp; 5596 for (i = 0; i < data_size; i++) { 5597 *data = resp->i2c_data[i]; 5598 data++; 5599 } 5600 } 5601 5602 return status; 5603 } 5604 5605 /** 5606 * ice_aq_write_i2c 5607 * @hw: pointer to the hw struct 5608 * @topo_addr: topology address for a device to communicate with 5609 * @bus_addr: 7-bit I2C bus address 5610 * @addr: I2C memory address (I2C offset) with up to 16 bits 5611 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5612 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5613 * @cd: pointer to command details structure or NULL 5614 * 5615 * Write I2C (0x06E3) 5616 * 5617 * * Return: 5618 * * 0 - Successful write to the i2c device 5619 * * -EINVAL - Data size greater than 4 bytes 5620 * * -EIO - FW error 5621 */ 5622 int 5623 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5624 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5625 struct ice_sq_cd *cd) 5626 { 5627 struct ice_aq_desc desc = { 0 }; 5628 struct ice_aqc_i2c *cmd; 5629 u8 data_size; 5630 5631 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5632 cmd = &desc.params.read_write_i2c; 5633 5634 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5635 5636 /* data_size limited to 4 */ 5637 if (data_size > 4) 5638 return -EINVAL; 5639 5640 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5641 cmd->topo_addr = topo_addr; 5642 cmd->i2c_params = params; 5643 cmd->i2c_addr = addr; 5644 5645 memcpy(cmd->i2c_data, data, data_size); 5646 5647 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5648 } 5649 5650 /** 5651 * ice_aq_set_gpio 5652 * @hw: pointer to the hw struct 5653 * @gpio_ctrl_handle: GPIO controller node handle 5654 * @pin_idx: IO Number of the GPIO that needs to be set 5655 * @value: SW provide IO value to set in the LSB 5656 * @cd: pointer to command details structure or NULL 5657 * 5658 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5659 */ 5660 int 5661 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5662 struct ice_sq_cd *cd) 5663 { 5664 struct ice_aqc_gpio *cmd; 5665 struct ice_aq_desc desc; 5666 5667 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5668 cmd = &desc.params.read_write_gpio; 5669 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5670 cmd->gpio_num = pin_idx; 5671 cmd->gpio_val = value ? 1 : 0; 5672 5673 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5674 } 5675 5676 /** 5677 * ice_aq_get_gpio 5678 * @hw: pointer to the hw struct 5679 * @gpio_ctrl_handle: GPIO controller node handle 5680 * @pin_idx: IO Number of the GPIO that needs to be set 5681 * @value: IO value read 5682 * @cd: pointer to command details structure or NULL 5683 * 5684 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5685 * the topology 5686 */ 5687 int 5688 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5689 bool *value, struct ice_sq_cd *cd) 5690 { 5691 struct ice_aqc_gpio *cmd; 5692 struct ice_aq_desc desc; 5693 int status; 5694 5695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5696 cmd = &desc.params.read_write_gpio; 5697 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5698 cmd->gpio_num = pin_idx; 5699 5700 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5701 if (status) 5702 return status; 5703 5704 *value = !!cmd->gpio_val; 5705 return 0; 5706 } 5707 5708 /** 5709 * ice_is_fw_api_min_ver 5710 * @hw: pointer to the hardware structure 5711 * @maj: major version 5712 * @min: minor version 5713 * @patch: patch version 5714 * 5715 * Checks if the firmware API is minimum version 5716 */ 5717 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5718 { 5719 if (hw->api_maj_ver == maj) { 5720 if (hw->api_min_ver > min) 5721 return true; 5722 if (hw->api_min_ver == min && hw->api_patch >= patch) 5723 return true; 5724 } else if (hw->api_maj_ver > maj) { 5725 return true; 5726 } 5727 5728 return false; 5729 } 5730 5731 /** 5732 * ice_fw_supports_link_override 5733 * @hw: pointer to the hardware structure 5734 * 5735 * Checks if the firmware supports link override 5736 */ 5737 bool ice_fw_supports_link_override(struct ice_hw *hw) 5738 { 5739 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5740 ICE_FW_API_LINK_OVERRIDE_MIN, 5741 ICE_FW_API_LINK_OVERRIDE_PATCH); 5742 } 5743 5744 /** 5745 * ice_get_link_default_override 5746 * @ldo: pointer to the link default override struct 5747 * @pi: pointer to the port info struct 5748 * 5749 * Gets the link default override for a port 5750 */ 5751 int 5752 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5753 struct ice_port_info *pi) 5754 { 5755 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5756 struct ice_hw *hw = pi->hw; 5757 int status; 5758 5759 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5760 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5761 if (status) { 5762 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5763 return status; 5764 } 5765 5766 /* Each port has its own config; calculate for our port */ 5767 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5768 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5769 5770 /* link options first */ 5771 status = ice_read_sr_word(hw, tlv_start, &buf); 5772 if (status) { 5773 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5774 return status; 5775 } 5776 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 5777 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5778 ICE_LINK_OVERRIDE_PHY_CFG_S; 5779 5780 /* link PHY config */ 5781 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5782 status = ice_read_sr_word(hw, offset, &buf); 5783 if (status) { 5784 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5785 return status; 5786 } 5787 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5788 5789 /* PHY types low */ 5790 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5791 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5792 status = ice_read_sr_word(hw, (offset + i), &buf); 5793 if (status) { 5794 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5795 return status; 5796 } 5797 /* shift 16 bits at a time to fill 64 bits */ 5798 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5799 } 5800 5801 /* PHY types high */ 5802 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5803 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5804 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5805 status = ice_read_sr_word(hw, (offset + i), &buf); 5806 if (status) { 5807 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5808 return status; 5809 } 5810 /* shift 16 bits at a time to fill 64 bits */ 5811 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5812 } 5813 5814 return status; 5815 } 5816 5817 /** 5818 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5819 * @caps: get PHY capability data 5820 */ 5821 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5822 { 5823 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5824 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5825 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5826 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5827 return true; 5828 5829 return false; 5830 } 5831 5832 /** 5833 * ice_aq_set_lldp_mib - Set the LLDP MIB 5834 * @hw: pointer to the HW struct 5835 * @mib_type: Local, Remote or both Local and Remote MIBs 5836 * @buf: pointer to the caller-supplied buffer to store the MIB block 5837 * @buf_size: size of the buffer (in bytes) 5838 * @cd: pointer to command details structure or NULL 5839 * 5840 * Set the LLDP MIB. (0x0A08) 5841 */ 5842 int 5843 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5844 struct ice_sq_cd *cd) 5845 { 5846 struct ice_aqc_lldp_set_local_mib *cmd; 5847 struct ice_aq_desc desc; 5848 5849 cmd = &desc.params.lldp_set_mib; 5850 5851 if (buf_size == 0 || !buf) 5852 return -EINVAL; 5853 5854 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5855 5856 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5857 desc.datalen = cpu_to_le16(buf_size); 5858 5859 cmd->type = mib_type; 5860 cmd->length = cpu_to_le16(buf_size); 5861 5862 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5863 } 5864 5865 /** 5866 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5867 * @hw: pointer to HW struct 5868 */ 5869 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5870 { 5871 if (hw->mac_type != ICE_MAC_E810) 5872 return false; 5873 5874 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5875 ICE_FW_API_LLDP_FLTR_MIN, 5876 ICE_FW_API_LLDP_FLTR_PATCH); 5877 } 5878 5879 /** 5880 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5881 * @hw: pointer to HW struct 5882 * @vsi_num: absolute HW index for VSI 5883 * @add: boolean for if adding or removing a filter 5884 */ 5885 int 5886 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5887 { 5888 struct ice_aqc_lldp_filter_ctrl *cmd; 5889 struct ice_aq_desc desc; 5890 5891 cmd = &desc.params.lldp_filter_ctrl; 5892 5893 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5894 5895 if (add) 5896 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5897 else 5898 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5899 5900 cmd->vsi_num = cpu_to_le16(vsi_num); 5901 5902 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5903 } 5904 5905 /** 5906 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 5907 * @hw: pointer to HW struct 5908 */ 5909 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 5910 { 5911 struct ice_aq_desc desc; 5912 5913 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 5914 5915 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5916 } 5917 5918 /** 5919 * ice_fw_supports_report_dflt_cfg 5920 * @hw: pointer to the hardware structure 5921 * 5922 * Checks if the firmware supports report default configuration 5923 */ 5924 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5925 { 5926 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 5927 ICE_FW_API_REPORT_DFLT_CFG_MIN, 5928 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 5929 } 5930 5931 /* each of the indexes into the following array match the speed of a return 5932 * value from the list of AQ returned speeds like the range: 5933 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 5934 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 5935 * array. The array is defined as 15 elements long because the link_speed 5936 * returned by the firmware is a 16 bit * value, but is indexed 5937 * by [fls(speed) - 1] 5938 */ 5939 static const u32 ice_aq_to_link_speed[] = { 5940 SPEED_10, /* BIT(0) */ 5941 SPEED_100, 5942 SPEED_1000, 5943 SPEED_2500, 5944 SPEED_5000, 5945 SPEED_10000, 5946 SPEED_20000, 5947 SPEED_25000, 5948 SPEED_40000, 5949 SPEED_50000, 5950 SPEED_100000, /* BIT(10) */ 5951 SPEED_200000, 5952 }; 5953 5954 /** 5955 * ice_get_link_speed - get integer speed from table 5956 * @index: array index from fls(aq speed) - 1 5957 * 5958 * Returns: u32 value containing integer speed 5959 */ 5960 u32 ice_get_link_speed(u16 index) 5961 { 5962 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 5963 return 0; 5964 5965 return ice_aq_to_link_speed[index]; 5966 } 5967