1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_clear_pf_cfg - Clear PF configuration 208 * @hw: pointer to the hardware structure 209 * 210 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 211 * configuration, flow director filters, etc.). 212 */ 213 int ice_clear_pf_cfg(struct ice_hw *hw) 214 { 215 struct libie_aq_desc desc; 216 217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 218 219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 220 } 221 222 /** 223 * ice_aq_manage_mac_read - manage MAC address read command 224 * @hw: pointer to the HW struct 225 * @buf: a virtual buffer to hold the manage MAC read response 226 * @buf_size: Size of the virtual buffer 227 * @cd: pointer to command details structure or NULL 228 * 229 * This function is used to return per PF station MAC address (0x0107). 230 * NOTE: Upon successful completion of this command, MAC address information 231 * is returned in user specified buffer. Please interpret user specified 232 * buffer as "manage_mac_read" response. 233 * Response such as various MAC addresses are stored in HW struct (port.mac) 234 * ice_discover_dev_caps is expected to be called before this function is 235 * called. 236 */ 237 static int 238 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 239 struct ice_sq_cd *cd) 240 { 241 struct ice_aqc_manage_mac_read_resp *resp; 242 struct ice_aqc_manage_mac_read *cmd; 243 struct libie_aq_desc desc; 244 int status; 245 u16 flags; 246 u8 i; 247 248 cmd = libie_aq_raw(&desc); 249 250 if (buf_size < sizeof(*resp)) 251 return -EINVAL; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 254 255 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 256 if (status) 257 return status; 258 259 resp = buf; 260 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 261 262 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 263 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 264 return -EIO; 265 } 266 267 /* A single port can report up to two (LAN and WoL) addresses */ 268 for (i = 0; i < cmd->num_addr; i++) 269 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 270 ether_addr_copy(hw->port_info->mac.lan_addr, 271 resp[i].mac_addr); 272 ether_addr_copy(hw->port_info->mac.perm_addr, 273 resp[i].mac_addr); 274 break; 275 } 276 277 return 0; 278 } 279 280 /** 281 * ice_aq_get_phy_caps - returns PHY capabilities 282 * @pi: port information structure 283 * @qual_mods: report qualified modules 284 * @report_mode: report mode capabilities 285 * @pcaps: structure for PHY capabilities to be filled 286 * @cd: pointer to command details structure or NULL 287 * 288 * Returns the various PHY capabilities supported on the Port (0x0600) 289 */ 290 int 291 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 292 struct ice_aqc_get_phy_caps_data *pcaps, 293 struct ice_sq_cd *cd) 294 { 295 struct ice_aqc_get_phy_caps *cmd; 296 u16 pcaps_size = sizeof(*pcaps); 297 struct libie_aq_desc desc; 298 const char *prefix; 299 struct ice_hw *hw; 300 int status; 301 302 cmd = libie_aq_raw(&desc); 303 304 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 305 return -EINVAL; 306 hw = pi->hw; 307 308 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 309 !ice_fw_supports_report_dflt_cfg(hw)) 310 return -EINVAL; 311 312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 313 314 if (qual_mods) 315 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 316 317 cmd->param0 |= cpu_to_le16(report_mode); 318 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 319 320 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 321 322 switch (report_mode) { 323 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 324 prefix = "phy_caps_media"; 325 break; 326 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 327 prefix = "phy_caps_no_media"; 328 break; 329 case ICE_AQC_REPORT_ACTIVE_CFG: 330 prefix = "phy_caps_active"; 331 break; 332 case ICE_AQC_REPORT_DFLT_CFG: 333 prefix = "phy_caps_default"; 334 break; 335 default: 336 prefix = "phy_caps_invalid"; 337 } 338 339 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 340 le64_to_cpu(pcaps->phy_type_high), prefix); 341 342 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 343 prefix, report_mode); 344 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 345 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 346 pcaps->low_power_ctrl_an); 347 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 348 pcaps->eee_cap); 349 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 350 pcaps->eeer_value); 351 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 352 pcaps->link_fec_options); 353 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 354 prefix, pcaps->module_compliance_enforcement); 355 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 356 prefix, pcaps->extended_compliance_code); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 358 pcaps->module_type[0]); 359 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 360 pcaps->module_type[1]); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 362 pcaps->module_type[2]); 363 364 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 365 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 366 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 367 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 368 sizeof(pi->phy.link_info.module_type)); 369 } 370 371 return status; 372 } 373 374 /** 375 * ice_aq_get_link_topo_handle - get link topology node return status 376 * @pi: port information structure 377 * @node_type: requested node type 378 * @cd: pointer to command details structure or NULL 379 * 380 * Get link topology node return status for specified node type (0x06E0) 381 * 382 * Node type cage can be used to determine if cage is present. If AQC 383 * returns error (ENOENT), then no cage present. If no cage present, then 384 * connection type is backplane or BASE-T. 385 */ 386 static int 387 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 388 struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_topo *cmd; 391 struct libie_aq_desc desc; 392 393 cmd = libie_aq_raw(&desc); 394 395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 396 397 cmd->addr.topo_params.node_type_ctx = 398 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 399 ICE_AQC_LINK_TOPO_NODE_CTX_S); 400 401 /* set node type */ 402 cmd->addr.topo_params.node_type_ctx |= 403 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 404 405 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 406 } 407 408 /** 409 * ice_aq_get_netlist_node 410 * @hw: pointer to the hw struct 411 * @cmd: get_link_topo AQ structure 412 * @node_part_number: output node part number if node found 413 * @node_handle: output node handle parameter if node found 414 * 415 * Get netlist node handle. 416 */ 417 int 418 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 419 u8 *node_part_number, u16 *node_handle) 420 { 421 struct ice_aqc_get_link_topo *resp; 422 struct libie_aq_desc desc; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 resp = libie_aq_raw(&desc); 426 *resp = *cmd; 427 428 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 429 return -EINTR; 430 431 if (node_handle) 432 *node_handle = le16_to_cpu(resp->addr.handle); 433 if (node_part_number) 434 *node_part_number = resp->node_part_num; 435 436 return 0; 437 } 438 439 /** 440 * ice_find_netlist_node 441 * @hw: pointer to the hw struct 442 * @node_type: type of netlist node to look for 443 * @ctx: context of the search 444 * @node_part_number: node part number to look for 445 * @node_handle: output parameter if node found - optional 446 * 447 * Scan the netlist for a node handle of the given node type and part number. 448 * 449 * If node_handle is non-NULL it will be modified on function exit. It is only 450 * valid if the function returns zero, and should be ignored on any non-zero 451 * return value. 452 * 453 * Return: 454 * * 0 if the node is found, 455 * * -ENOENT if no handle was found, 456 * * negative error code on failure to access the AQ. 457 */ 458 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 459 u8 node_part_number, u16 *node_handle) 460 { 461 u8 idx; 462 463 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 464 struct ice_aqc_get_link_topo cmd = {}; 465 u8 rec_node_part_number; 466 int status; 467 468 cmd.addr.topo_params.node_type_ctx = 469 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 470 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 471 cmd.addr.topo_params.index = idx; 472 473 status = ice_aq_get_netlist_node(hw, &cmd, 474 &rec_node_part_number, 475 node_handle); 476 if (status) 477 return status; 478 479 if (rec_node_part_number == node_part_number) 480 return 0; 481 } 482 483 return -ENOENT; 484 } 485 486 /** 487 * ice_is_media_cage_present 488 * @pi: port information structure 489 * 490 * Returns true if media cage is present, else false. If no cage, then 491 * media type is backplane or BASE-T. 492 */ 493 static bool ice_is_media_cage_present(struct ice_port_info *pi) 494 { 495 /* Node type cage can be used to determine if cage is present. If AQC 496 * returns error (ENOENT), then no cage present. If no cage present then 497 * connection type is backplane or BASE-T. 498 */ 499 return !ice_aq_get_link_topo_handle(pi, 500 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 501 NULL); 502 } 503 504 /** 505 * ice_get_media_type - Gets media type 506 * @pi: port information structure 507 */ 508 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 509 { 510 struct ice_link_status *hw_link_info; 511 512 if (!pi) 513 return ICE_MEDIA_UNKNOWN; 514 515 hw_link_info = &pi->phy.link_info; 516 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 517 /* If more than one media type is selected, report unknown */ 518 return ICE_MEDIA_UNKNOWN; 519 520 if (hw_link_info->phy_type_low) { 521 /* 1G SGMII is a special case where some DA cable PHYs 522 * may show this as an option when it really shouldn't 523 * be since SGMII is meant to be between a MAC and a PHY 524 * in a backplane. Try to detect this case and handle it 525 */ 526 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 527 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 528 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 529 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 530 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 531 return ICE_MEDIA_DA; 532 533 switch (hw_link_info->phy_type_low) { 534 case ICE_PHY_TYPE_LOW_1000BASE_SX: 535 case ICE_PHY_TYPE_LOW_1000BASE_LX: 536 case ICE_PHY_TYPE_LOW_10GBASE_SR: 537 case ICE_PHY_TYPE_LOW_10GBASE_LR: 538 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 539 case ICE_PHY_TYPE_LOW_25GBASE_SR: 540 case ICE_PHY_TYPE_LOW_25GBASE_LR: 541 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 542 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 543 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 544 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 545 case ICE_PHY_TYPE_LOW_50GBASE_SR: 546 case ICE_PHY_TYPE_LOW_50GBASE_FR: 547 case ICE_PHY_TYPE_LOW_50GBASE_LR: 548 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 549 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 550 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_DR: 552 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 553 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 554 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 555 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 556 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 557 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 558 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 559 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 560 return ICE_MEDIA_FIBER; 561 case ICE_PHY_TYPE_LOW_100BASE_TX: 562 case ICE_PHY_TYPE_LOW_1000BASE_T: 563 case ICE_PHY_TYPE_LOW_2500BASE_T: 564 case ICE_PHY_TYPE_LOW_5GBASE_T: 565 case ICE_PHY_TYPE_LOW_10GBASE_T: 566 case ICE_PHY_TYPE_LOW_25GBASE_T: 567 return ICE_MEDIA_BASET; 568 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 569 case ICE_PHY_TYPE_LOW_25GBASE_CR: 570 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 571 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 572 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 573 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 574 case ICE_PHY_TYPE_LOW_50GBASE_CP: 575 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 577 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 578 return ICE_MEDIA_DA; 579 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2: 582 case ICE_PHY_TYPE_LOW_50G_AUI2: 583 case ICE_PHY_TYPE_LOW_50G_AUI1: 584 case ICE_PHY_TYPE_LOW_100G_AUI4: 585 case ICE_PHY_TYPE_LOW_100G_CAUI4: 586 if (ice_is_media_cage_present(pi)) 587 return ICE_MEDIA_DA; 588 fallthrough; 589 case ICE_PHY_TYPE_LOW_1000BASE_KX: 590 case ICE_PHY_TYPE_LOW_2500BASE_KX: 591 case ICE_PHY_TYPE_LOW_2500BASE_X: 592 case ICE_PHY_TYPE_LOW_5GBASE_KR: 593 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 594 case ICE_PHY_TYPE_LOW_25GBASE_KR: 595 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 596 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 597 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 599 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 600 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 601 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 602 return ICE_MEDIA_BACKPLANE; 603 } 604 } else { 605 switch (hw_link_info->phy_type_high) { 606 case ICE_PHY_TYPE_HIGH_100G_AUI2: 607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 608 if (ice_is_media_cage_present(pi)) 609 return ICE_MEDIA_DA; 610 fallthrough; 611 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 612 return ICE_MEDIA_BACKPLANE; 613 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 614 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 615 return ICE_MEDIA_FIBER; 616 } 617 } 618 return ICE_MEDIA_UNKNOWN; 619 } 620 621 /** 622 * ice_get_link_status_datalen 623 * @hw: pointer to the HW struct 624 * 625 * Returns datalength for the Get Link Status AQ command, which is bigger for 626 * newer adapter families handled by ice driver. 627 */ 628 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 629 { 630 switch (hw->mac_type) { 631 case ICE_MAC_E830: 632 return ICE_AQC_LS_DATA_SIZE_V2; 633 case ICE_MAC_E810: 634 default: 635 return ICE_AQC_LS_DATA_SIZE_V1; 636 } 637 } 638 639 /** 640 * ice_aq_get_link_info 641 * @pi: port information structure 642 * @ena_lse: enable/disable LinkStatusEvent reporting 643 * @link: pointer to link status structure - optional 644 * @cd: pointer to command details structure or NULL 645 * 646 * Get Link Status (0x607). Returns the link status of the adapter. 647 */ 648 int 649 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 650 struct ice_link_status *link, struct ice_sq_cd *cd) 651 { 652 struct ice_aqc_get_link_status_data link_data = { 0 }; 653 struct ice_aqc_get_link_status *resp; 654 struct ice_link_status *li_old, *li; 655 enum ice_media_type *hw_media_type; 656 struct ice_fc_info *hw_fc_info; 657 struct libie_aq_desc desc; 658 bool tx_pause, rx_pause; 659 struct ice_hw *hw; 660 u16 cmd_flags; 661 int status; 662 663 if (!pi) 664 return -EINVAL; 665 hw = pi->hw; 666 li_old = &pi->phy.link_info_old; 667 hw_media_type = &pi->phy.media_type; 668 li = &pi->phy.link_info; 669 hw_fc_info = &pi->fc; 670 671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 672 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 673 resp = libie_aq_raw(&desc); 674 resp->cmd_flags = cpu_to_le16(cmd_flags); 675 resp->lport_num = pi->lport; 676 677 status = ice_aq_send_cmd(hw, &desc, &link_data, 678 ice_get_link_status_datalen(hw), cd); 679 if (status) 680 return status; 681 682 /* save off old link status information */ 683 *li_old = *li; 684 685 /* update current link status information */ 686 li->link_speed = le16_to_cpu(link_data.link_speed); 687 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 688 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 689 *hw_media_type = ice_get_media_type(pi); 690 li->link_info = link_data.link_info; 691 li->link_cfg_err = link_data.link_cfg_err; 692 li->an_info = link_data.an_info; 693 li->ext_info = link_data.ext_info; 694 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 695 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 696 li->topo_media_conflict = link_data.topo_media_conflict; 697 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 698 ICE_AQ_CFG_PACING_TYPE_M); 699 700 /* update fc info */ 701 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 702 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 703 if (tx_pause && rx_pause) 704 hw_fc_info->current_mode = ICE_FC_FULL; 705 else if (tx_pause) 706 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 707 else if (rx_pause) 708 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 709 else 710 hw_fc_info->current_mode = ICE_FC_NONE; 711 712 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 713 714 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 715 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 716 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 717 (unsigned long long)li->phy_type_low); 718 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 719 (unsigned long long)li->phy_type_high); 720 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 721 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 722 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 723 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 724 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 725 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 726 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 727 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 728 li->max_frame_size); 729 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 730 731 /* save link status information */ 732 if (link) 733 *link = *li; 734 735 /* flag cleared so calling functions don't call AQ again */ 736 pi->phy.get_link_info = false; 737 738 return 0; 739 } 740 741 /** 742 * ice_fill_tx_timer_and_fc_thresh 743 * @hw: pointer to the HW struct 744 * @cmd: pointer to MAC cfg structure 745 * 746 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 747 * descriptor 748 */ 749 static void 750 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 751 struct ice_aqc_set_mac_cfg *cmd) 752 { 753 u32 val, fc_thres_m; 754 755 /* We read back the transmit timer and FC threshold value of 756 * LFC. Thus, we will use index = 757 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 758 * 759 * Also, because we are operating on transmit timer and FC 760 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 761 */ 762 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 763 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 764 765 if (hw->mac_type == ICE_MAC_E830) { 766 /* Retrieve the transmit timer */ 767 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 768 cmd->tx_tmr_value = 769 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 770 771 /* Retrieve the fc threshold */ 772 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 773 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 774 } else { 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, 777 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 778 cmd->tx_tmr_value = 779 le16_encode_bits(val, 780 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 781 782 /* Retrieve the fc threshold */ 783 val = rd32(hw, 784 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 785 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 786 } 787 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 788 } 789 790 /** 791 * ice_aq_set_mac_cfg 792 * @hw: pointer to the HW struct 793 * @max_frame_size: Maximum Frame Size to be supported 794 * @cd: pointer to command details structure or NULL 795 * 796 * Set MAC configuration (0x0603) 797 */ 798 int 799 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 800 { 801 struct ice_aqc_set_mac_cfg *cmd; 802 struct libie_aq_desc desc; 803 804 cmd = libie_aq_raw(&desc); 805 806 if (max_frame_size == 0) 807 return -EINVAL; 808 809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 810 811 cmd->max_frame_size = cpu_to_le16(max_frame_size); 812 813 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 814 815 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 816 } 817 818 /** 819 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 820 * @hw: pointer to the HW struct 821 */ 822 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 823 { 824 struct ice_switch_info *sw; 825 int status; 826 827 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 828 sizeof(*hw->switch_info), GFP_KERNEL); 829 sw = hw->switch_info; 830 831 if (!sw) 832 return -ENOMEM; 833 834 INIT_LIST_HEAD(&sw->vsi_list_map_head); 835 sw->prof_res_bm_init = 0; 836 837 /* Initialize recipe count with default recipes read from NVM */ 838 sw->recp_cnt = ICE_SW_LKUP_LAST; 839 840 status = ice_init_def_sw_recp(hw); 841 if (status) { 842 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 843 return status; 844 } 845 return 0; 846 } 847 848 /** 849 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 850 * @hw: pointer to the HW struct 851 */ 852 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 853 { 854 struct ice_switch_info *sw = hw->switch_info; 855 struct ice_vsi_list_map_info *v_pos_map; 856 struct ice_vsi_list_map_info *v_tmp_map; 857 struct ice_sw_recipe *recps; 858 u8 i; 859 860 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 861 list_entry) { 862 list_del(&v_pos_map->list_entry); 863 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 864 } 865 recps = sw->recp_list; 866 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 867 recps[i].root_rid = i; 868 869 if (recps[i].adv_rule) { 870 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 871 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 872 873 mutex_destroy(&recps[i].filt_rule_lock); 874 list_for_each_entry_safe(lst_itr, tmp_entry, 875 &recps[i].filt_rules, 876 list_entry) { 877 list_del(&lst_itr->list_entry); 878 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 879 devm_kfree(ice_hw_to_dev(hw), lst_itr); 880 } 881 } else { 882 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 883 884 mutex_destroy(&recps[i].filt_rule_lock); 885 list_for_each_entry_safe(lst_itr, tmp_entry, 886 &recps[i].filt_rules, 887 list_entry) { 888 list_del(&lst_itr->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), lst_itr); 890 } 891 } 892 } 893 ice_rm_all_sw_replay_rule_info(hw); 894 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 895 devm_kfree(ice_hw_to_dev(hw), sw); 896 } 897 898 /** 899 * ice_get_itr_intrl_gran 900 * @hw: pointer to the HW struct 901 * 902 * Determines the ITR/INTRL granularities based on the maximum aggregate 903 * bandwidth according to the device's configuration during power-on. 904 */ 905 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 906 { 907 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 908 rd32(hw, GL_PWR_MODE_CTL)); 909 910 switch (max_agg_bw) { 911 case ICE_MAX_AGG_BW_200G: 912 case ICE_MAX_AGG_BW_100G: 913 case ICE_MAX_AGG_BW_50G: 914 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 915 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 916 break; 917 case ICE_MAX_AGG_BW_25G: 918 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 919 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 920 break; 921 } 922 } 923 924 /** 925 * ice_wait_fw_load - wait for PHY firmware loading to complete 926 * @hw: pointer to the hardware structure 927 * @timeout: milliseconds that can elapse before timing out, 0 to bypass waiting 928 * 929 * Return: 930 * * 0 on success 931 * * negative on timeout 932 */ 933 static int ice_wait_fw_load(struct ice_hw *hw, u32 timeout) 934 { 935 int fw_loading_reg; 936 937 if (!timeout) 938 return 0; 939 940 fw_loading_reg = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 941 /* notify the user only once if PHY FW is still loading */ 942 if (fw_loading_reg) 943 dev_info(ice_hw_to_dev(hw), "Link initialization is blocked by PHY FW initialization. Link initialization will continue after PHY FW initialization completes.\n"); 944 else 945 return 0; 946 947 return rd32_poll_timeout(hw, GL_MNG_FWSM, fw_loading_reg, 948 !(fw_loading_reg & GL_MNG_FWSM_FW_LOADING_M), 949 10000, timeout * 1000); 950 } 951 952 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 953 u16 size) 954 { 955 struct ice_hw *hw = priv; 956 957 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 958 } 959 960 static int __fwlog_init(struct ice_hw *hw) 961 { 962 struct ice_pf *pf = hw->back; 963 struct libie_fwlog_api api = { 964 .pdev = pf->pdev, 965 .send_cmd = __fwlog_send_cmd, 966 .priv = hw, 967 }; 968 int err; 969 970 /* only support fw log commands on PF 0 */ 971 if (hw->bus.func) 972 return -EINVAL; 973 974 err = ice_debugfs_pf_init(pf); 975 if (err) 976 return err; 977 978 api.debugfs_root = pf->ice_debugfs_pf; 979 980 return libie_fwlog_init(&hw->fwlog, &api); 981 } 982 983 /** 984 * ice_init_hw - main hardware initialization routine 985 * @hw: pointer to the hardware structure 986 */ 987 int ice_init_hw(struct ice_hw *hw) 988 { 989 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 990 void *mac_buf __free(kfree) = NULL; 991 u16 mac_buf_len; 992 int status; 993 994 /* Set MAC type based on DeviceID */ 995 status = ice_set_mac_type(hw); 996 if (status) 997 return status; 998 999 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1000 1001 status = ice_reset(hw, ICE_RESET_PFR); 1002 if (status) 1003 return status; 1004 1005 ice_get_itr_intrl_gran(hw); 1006 1007 status = ice_create_all_ctrlq(hw); 1008 if (status) 1009 goto err_unroll_cqinit; 1010 1011 status = __fwlog_init(hw); 1012 if (status) 1013 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1014 status); 1015 1016 status = ice_clear_pf_cfg(hw); 1017 if (status) 1018 goto err_unroll_cqinit; 1019 1020 /* Set bit to enable Flow Director filters */ 1021 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1022 INIT_LIST_HEAD(&hw->fdir_list_head); 1023 1024 ice_clear_pxe_mode(hw); 1025 1026 status = ice_init_nvm(hw); 1027 if (status) 1028 goto err_unroll_cqinit; 1029 1030 status = ice_get_caps(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 if (!hw->port_info) 1035 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1036 sizeof(*hw->port_info), 1037 GFP_KERNEL); 1038 if (!hw->port_info) { 1039 status = -ENOMEM; 1040 goto err_unroll_cqinit; 1041 } 1042 1043 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1044 /* set the back pointer to HW */ 1045 hw->port_info->hw = hw; 1046 1047 /* Initialize port_info struct with switch configuration data */ 1048 status = ice_get_initial_sw_cfg(hw); 1049 if (status) 1050 goto err_unroll_alloc; 1051 1052 hw->evb_veb = true; 1053 1054 /* init xarray for identifying scheduling nodes uniquely */ 1055 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1056 1057 /* Query the allocated resources for Tx scheduler */ 1058 status = ice_sched_query_res_alloc(hw); 1059 if (status) { 1060 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1061 goto err_unroll_alloc; 1062 } 1063 ice_sched_get_psm_clk_freq(hw); 1064 1065 /* Initialize port_info struct with scheduler data */ 1066 status = ice_sched_init_port(hw->port_info); 1067 if (status) 1068 goto err_unroll_sched; 1069 1070 pcaps = kzalloc_obj(*pcaps); 1071 if (!pcaps) { 1072 status = -ENOMEM; 1073 goto err_unroll_sched; 1074 } 1075 1076 /* Initialize port_info struct with PHY capabilities */ 1077 status = ice_aq_get_phy_caps(hw->port_info, false, 1078 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1079 NULL); 1080 if (status) 1081 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1082 status); 1083 1084 /* Initialize port_info struct with link information */ 1085 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1086 if (status) 1087 goto err_unroll_sched; 1088 1089 /* need a valid SW entry point to build a Tx tree */ 1090 if (!hw->sw_entry_point_layer) { 1091 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1092 status = -EIO; 1093 goto err_unroll_sched; 1094 } 1095 INIT_LIST_HEAD(&hw->agg_list); 1096 /* Initialize max burst size */ 1097 if (!hw->max_burst_size) 1098 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1099 1100 status = ice_init_fltr_mgmt_struct(hw); 1101 if (status) 1102 goto err_unroll_sched; 1103 1104 /* Get MAC information */ 1105 /* A single port can report up to two (LAN and WoL) addresses */ 1106 mac_buf = kzalloc_objs(struct ice_aqc_manage_mac_read_resp, 2); 1107 if (!mac_buf) { 1108 status = -ENOMEM; 1109 goto err_unroll_fltr_mgmt_struct; 1110 } 1111 1112 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1113 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1114 1115 if (status) 1116 goto err_unroll_fltr_mgmt_struct; 1117 /* enable jumbo frame support at MAC level */ 1118 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1119 if (status) 1120 goto err_unroll_fltr_mgmt_struct; 1121 /* Obtain counter base index which would be used by flow director */ 1122 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1123 if (status) 1124 goto err_unroll_fltr_mgmt_struct; 1125 status = ice_init_hw_tbls(hw); 1126 if (status) 1127 goto err_unroll_fltr_mgmt_struct; 1128 1129 ice_init_dev_hw(hw->back); 1130 1131 mutex_init(&hw->tnl_lock); 1132 ice_init_chk_recipe_reuse_support(hw); 1133 1134 /* Some cards require longer initialization times 1135 * due to necessity of loading FW from an external source. 1136 * This can take even half a minute. 1137 */ 1138 status = ice_wait_fw_load(hw, 30000); 1139 if (status) { 1140 dev_err(ice_hw_to_dev(hw), "ice_wait_fw_load timed out"); 1141 goto err_unroll_fltr_mgmt_struct; 1142 } 1143 1144 hw->lane_num = ice_get_phy_lane_number(hw); 1145 1146 return 0; 1147 err_unroll_fltr_mgmt_struct: 1148 ice_cleanup_fltr_mgmt_struct(hw); 1149 err_unroll_sched: 1150 ice_sched_cleanup_all(hw); 1151 err_unroll_alloc: 1152 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1153 err_unroll_cqinit: 1154 ice_destroy_all_ctrlq(hw); 1155 return status; 1156 } 1157 1158 static void __fwlog_deinit(struct ice_hw *hw) 1159 { 1160 /* only support fw log commands on PF 0 */ 1161 if (hw->bus.func) 1162 return; 1163 1164 ice_debugfs_pf_deinit(hw->back); 1165 libie_fwlog_deinit(&hw->fwlog); 1166 } 1167 1168 /** 1169 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1170 * @hw: pointer to the hardware structure 1171 * 1172 * This should be called only during nominal operation, not as a result of 1173 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1174 * applicable initializations if it fails for any reason. 1175 */ 1176 void ice_deinit_hw(struct ice_hw *hw) 1177 { 1178 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1179 ice_cleanup_fltr_mgmt_struct(hw); 1180 1181 ice_sched_cleanup_all(hw); 1182 ice_sched_clear_agg(hw); 1183 ice_free_seg(hw); 1184 ice_free_hw_tbls(hw); 1185 mutex_destroy(&hw->tnl_lock); 1186 __fwlog_deinit(hw); 1187 ice_destroy_all_ctrlq(hw); 1188 1189 /* Clear VSI contexts if not already cleared */ 1190 ice_clear_all_vsi_ctx(hw); 1191 } 1192 1193 /** 1194 * ice_check_reset - Check to see if a global reset is complete 1195 * @hw: pointer to the hardware structure 1196 */ 1197 int ice_check_reset(struct ice_hw *hw) 1198 { 1199 u32 cnt, reg = 0, grst_timeout, uld_mask; 1200 1201 /* Poll for Device Active state in case a recent CORER, GLOBR, 1202 * or EMPR has occurred. The grst delay value is in 100ms units. 1203 * Add 1sec for outstanding AQ commands that can take a long time. 1204 */ 1205 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1206 rd32(hw, GLGEN_RSTCTL)) + 10; 1207 1208 for (cnt = 0; cnt < grst_timeout; cnt++) { 1209 mdelay(100); 1210 reg = rd32(hw, GLGEN_RSTAT); 1211 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1212 break; 1213 } 1214 1215 if (cnt == grst_timeout) { 1216 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1217 return -EIO; 1218 } 1219 1220 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1221 GLNVM_ULD_PCIER_DONE_1_M |\ 1222 GLNVM_ULD_CORER_DONE_M |\ 1223 GLNVM_ULD_GLOBR_DONE_M |\ 1224 GLNVM_ULD_POR_DONE_M |\ 1225 GLNVM_ULD_POR_DONE_1_M |\ 1226 GLNVM_ULD_PCIER_DONE_2_M) 1227 1228 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1229 GLNVM_ULD_PE_DONE_M : 0); 1230 1231 /* Device is Active; check Global Reset processes are done */ 1232 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1233 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1234 if (reg == uld_mask) { 1235 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1236 break; 1237 } 1238 mdelay(10); 1239 } 1240 1241 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1242 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1243 reg); 1244 return -EIO; 1245 } 1246 1247 return 0; 1248 } 1249 1250 /** 1251 * ice_pf_reset - Reset the PF 1252 * @hw: pointer to the hardware structure 1253 * 1254 * If a global reset has been triggered, this function checks 1255 * for its completion and then issues the PF reset 1256 */ 1257 static int ice_pf_reset(struct ice_hw *hw) 1258 { 1259 u32 cnt, reg; 1260 1261 /* If at function entry a global reset was already in progress, i.e. 1262 * state is not 'device active' or any of the reset done bits are not 1263 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1264 * global reset is done. 1265 */ 1266 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1267 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1268 /* poll on global reset currently in progress until done */ 1269 if (ice_check_reset(hw)) 1270 return -EIO; 1271 1272 return 0; 1273 } 1274 1275 /* Reset the PF */ 1276 reg = rd32(hw, PFGEN_CTRL); 1277 1278 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1279 1280 /* Wait for the PFR to complete. The wait time is the global config lock 1281 * timeout plus the PFR timeout which will account for a possible reset 1282 * that is occurring during a download package operation. 1283 */ 1284 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1285 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1286 reg = rd32(hw, PFGEN_CTRL); 1287 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1288 break; 1289 1290 mdelay(1); 1291 } 1292 1293 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1294 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1295 return -EIO; 1296 } 1297 1298 return 0; 1299 } 1300 1301 /** 1302 * ice_reset - Perform different types of reset 1303 * @hw: pointer to the hardware structure 1304 * @req: reset request 1305 * 1306 * This function triggers a reset as specified by the req parameter. 1307 * 1308 * Note: 1309 * If anything other than a PF reset is triggered, PXE mode is restored. 1310 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1311 * interface has been restored in the rebuild flow. 1312 */ 1313 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1314 { 1315 u32 val = 0; 1316 1317 switch (req) { 1318 case ICE_RESET_PFR: 1319 return ice_pf_reset(hw); 1320 case ICE_RESET_CORER: 1321 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1322 val = GLGEN_RTRIG_CORER_M; 1323 break; 1324 case ICE_RESET_GLOBR: 1325 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1326 val = GLGEN_RTRIG_GLOBR_M; 1327 break; 1328 default: 1329 return -EINVAL; 1330 } 1331 1332 val |= rd32(hw, GLGEN_RTRIG); 1333 wr32(hw, GLGEN_RTRIG, val); 1334 ice_flush(hw); 1335 1336 /* wait for the FW to be ready */ 1337 return ice_check_reset(hw); 1338 } 1339 1340 /** 1341 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1342 * @hw: pointer to the hardware structure 1343 * @rxq_ctx: pointer to the packed Rx queue context 1344 * @rxq_index: the index of the Rx queue 1345 */ 1346 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1347 const ice_rxq_ctx_buf_t *rxq_ctx, 1348 u32 rxq_index) 1349 { 1350 /* Copy each dword separately to HW */ 1351 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1352 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1353 1354 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1355 1356 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1357 } 1358 } 1359 1360 /** 1361 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1362 * @hw: pointer to the hardware structure 1363 * @rxq_ctx: pointer to the packed Rx queue context 1364 * @rxq_index: the index of the Rx queue 1365 */ 1366 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1367 ice_rxq_ctx_buf_t *rxq_ctx, 1368 u32 rxq_index) 1369 { 1370 u32 *ctx = (u32 *)rxq_ctx; 1371 1372 /* Copy each dword separately from HW */ 1373 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1374 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1375 1376 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1377 } 1378 } 1379 1380 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1381 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1382 1383 /* LAN Rx Queue Context */ 1384 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1385 /* Field Width LSB */ 1386 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1387 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1388 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1389 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1390 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1391 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1392 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1393 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1394 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1395 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1396 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1397 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1398 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1399 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1400 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1401 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1402 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1403 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1404 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1405 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1406 }; 1407 1408 /** 1409 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1410 * @ctx: the Rx queue context to pack 1411 * @buf: the HW buffer to pack into 1412 * 1413 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1414 * bit-packed HW layout. 1415 */ 1416 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1417 ice_rxq_ctx_buf_t *buf) 1418 { 1419 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1420 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1421 } 1422 1423 /** 1424 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1425 * @buf: the HW buffer to unpack from 1426 * @ctx: the Rx queue context to unpack 1427 * 1428 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1429 * structure. 1430 */ 1431 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1432 struct ice_rlan_ctx *ctx) 1433 { 1434 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1435 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1436 } 1437 1438 /** 1439 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1440 * @hw: pointer to the hardware structure 1441 * @rlan_ctx: pointer to the unpacked Rx queue context 1442 * @rxq_index: the index of the Rx queue 1443 * 1444 * Pack the sparse Rx Queue context into dense hardware format and write it 1445 * into the HW register space. 1446 * 1447 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1448 */ 1449 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1450 u32 rxq_index) 1451 { 1452 ice_rxq_ctx_buf_t buf = {}; 1453 1454 if (rxq_index > QRX_CTRL_MAX_INDEX) 1455 return -EINVAL; 1456 1457 ice_pack_rxq_ctx(rlan_ctx, &buf); 1458 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1459 1460 return 0; 1461 } 1462 1463 /** 1464 * ice_read_rxq_ctx - Read Rx queue context from HW 1465 * @hw: pointer to the hardware structure 1466 * @rlan_ctx: pointer to the Rx queue context 1467 * @rxq_index: the index of the Rx queue 1468 * 1469 * Read the Rx queue context from the hardware registers, and unpack it into 1470 * the sparse Rx queue context structure. 1471 * 1472 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1473 */ 1474 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1475 u32 rxq_index) 1476 { 1477 ice_rxq_ctx_buf_t buf = {}; 1478 1479 if (rxq_index > QRX_CTRL_MAX_INDEX) 1480 return -EINVAL; 1481 1482 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1483 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1484 1485 return 0; 1486 } 1487 1488 /* LAN Tx Queue Context */ 1489 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1490 /* Field Width LSB */ 1491 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1492 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1493 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1494 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1495 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1496 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1497 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1498 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1499 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1500 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1501 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1502 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1503 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1504 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1505 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1506 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1507 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1508 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1509 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1510 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1511 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1512 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1513 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1514 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1515 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1516 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1517 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1518 }; 1519 1520 /** 1521 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1522 * @ctx: the Tx queue context to pack 1523 * @buf: the Admin Queue HW buffer to pack into 1524 * 1525 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1526 * bit-packed Admin Queue layout. 1527 */ 1528 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1529 { 1530 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1531 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1532 } 1533 1534 /** 1535 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1536 * @ctx: the Tx queue context to pack 1537 * @buf: the HW buffer to pack into 1538 * 1539 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1540 * bit-packed HW layout, including the internal data portion. 1541 */ 1542 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1543 ice_txq_ctx_buf_full_t *buf) 1544 { 1545 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1546 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1547 } 1548 1549 /** 1550 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1551 * @buf: the HW buffer to unpack from 1552 * @ctx: the Tx queue context to unpack 1553 * 1554 * Unpack the Tx queue context from the HW buffer (including the full internal 1555 * state) into the CPU-friendly structure. 1556 */ 1557 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1558 struct ice_tlan_ctx *ctx) 1559 { 1560 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1561 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1562 } 1563 1564 /** 1565 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1566 * @hw: pointer to the hardware structure 1567 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1568 * @txq_index: the index of the Tx queue 1569 * 1570 * Copy Tx Queue context from HW register space to dense structure 1571 */ 1572 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1573 ice_txq_ctx_buf_full_t *txq_ctx, 1574 u32 txq_index) 1575 { 1576 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1577 u32 *ctx = (u32 *)txq_ctx; 1578 u32 txq_base, reg; 1579 1580 /* Get Tx queue base within card space */ 1581 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1582 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1583 1584 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1585 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1586 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1587 txq_base + txq_index) | 1588 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1589 1590 /* Prevent other PFs on the same adapter from accessing the Tx queue 1591 * context interface concurrently. 1592 */ 1593 spin_lock(&pf->adapter->txq_ctx_lock); 1594 1595 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1596 ice_flush(hw); 1597 1598 /* Copy each dword separately from HW */ 1599 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1600 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1601 1602 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1603 } 1604 1605 spin_unlock(&pf->adapter->txq_ctx_lock); 1606 } 1607 1608 /** 1609 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1610 * @hw: pointer to the hardware structure 1611 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1612 * @txq_index: the index of the Tx queue 1613 */ 1614 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1615 const ice_txq_ctx_buf_full_t *txq_ctx, 1616 u32 txq_index) 1617 { 1618 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1619 u32 txq_base, reg; 1620 1621 /* Get Tx queue base within card space */ 1622 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1623 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1624 1625 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1626 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1627 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1628 txq_base + txq_index) | 1629 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1630 1631 /* Prevent other PFs on the same adapter from accessing the Tx queue 1632 * context interface concurrently. 1633 */ 1634 spin_lock(&pf->adapter->txq_ctx_lock); 1635 1636 /* Copy each dword separately to HW */ 1637 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1638 u32 ctx = ((const u32 *)txq_ctx)[i]; 1639 1640 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1641 1642 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1643 } 1644 1645 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1646 ice_flush(hw); 1647 1648 spin_unlock(&pf->adapter->txq_ctx_lock); 1649 } 1650 1651 /** 1652 * ice_read_txq_ctx - Read Tx queue context from HW 1653 * @hw: pointer to the hardware structure 1654 * @tlan_ctx: pointer to the Tx queue context 1655 * @txq_index: the index of the Tx queue 1656 * 1657 * Read the Tx queue context from the HW registers, then unpack it into the 1658 * ice_tlan_ctx structure for use. 1659 * 1660 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1661 */ 1662 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1663 u32 txq_index) 1664 { 1665 ice_txq_ctx_buf_full_t buf = {}; 1666 1667 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1668 return -EINVAL; 1669 1670 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1671 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1672 1673 return 0; 1674 } 1675 1676 /** 1677 * ice_write_txq_ctx - Write Tx queue context to HW 1678 * @hw: pointer to the hardware structure 1679 * @tlan_ctx: pointer to the Tx queue context 1680 * @txq_index: the index of the Tx queue 1681 * 1682 * Pack the Tx queue context into the dense HW layout, then write it into the 1683 * HW registers. 1684 * 1685 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1686 */ 1687 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1688 u32 txq_index) 1689 { 1690 ice_txq_ctx_buf_full_t buf = {}; 1691 1692 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1693 return -EINVAL; 1694 1695 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1696 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1697 1698 return 0; 1699 } 1700 1701 /* Tx time Queue Context */ 1702 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1703 /* Field Width LSB */ 1704 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1705 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1706 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1707 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1708 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1709 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1710 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1711 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1712 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1713 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1714 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1715 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1716 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1717 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1718 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1719 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1720 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1721 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1722 }; 1723 1724 /** 1725 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1726 * @ctx: the Tx time queue context to pack 1727 * @buf: the HW buffer to pack into 1728 * 1729 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1730 * its bit-packed HW layout. 1731 */ 1732 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1733 ice_txtime_ctx_buf_t *buf) 1734 { 1735 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1736 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1737 } 1738 1739 /* Sideband Queue command wrappers */ 1740 1741 /** 1742 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1743 * @hw: pointer to the HW struct 1744 * @desc: descriptor describing the command 1745 * @buf: buffer to use for indirect commands (NULL for direct commands) 1746 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1747 * @cd: pointer to command details structure 1748 */ 1749 static int 1750 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1751 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1752 { 1753 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1754 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1755 } 1756 1757 /** 1758 * ice_sbq_rw_reg - Fill Sideband Queue command 1759 * @hw: pointer to the HW struct 1760 * @in: message info to be filled in descriptor 1761 * @flags: control queue descriptor flags 1762 */ 1763 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1764 { 1765 struct ice_sbq_cmd_desc desc = {0}; 1766 struct ice_sbq_msg_req msg = {0}; 1767 u16 msg_len; 1768 int status; 1769 1770 msg_len = sizeof(msg); 1771 1772 msg.dest_dev = in->dest_dev; 1773 msg.opcode = in->opcode; 1774 msg.flags = ICE_SBQ_MSG_FLAGS; 1775 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1776 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1777 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1778 1779 if (in->opcode) 1780 msg.data = cpu_to_le32(in->data); 1781 else 1782 /* data read comes back in completion, so shorten the struct by 1783 * sizeof(msg.data) 1784 */ 1785 msg_len -= sizeof(msg.data); 1786 1787 desc.flags = cpu_to_le16(flags); 1788 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1789 desc.param0.cmd_len = cpu_to_le16(msg_len); 1790 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1791 if (!status && !in->opcode) 1792 in->data = le32_to_cpu 1793 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1794 return status; 1795 } 1796 1797 /* FW Admin Queue command wrappers */ 1798 1799 /* Software lock/mutex that is meant to be held while the Global Config Lock 1800 * in firmware is acquired by the software to prevent most (but not all) types 1801 * of AQ commands from being sent to FW 1802 */ 1803 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1804 1805 /** 1806 * ice_should_retry_sq_send_cmd 1807 * @opcode: AQ opcode 1808 * 1809 * Decide if we should retry the send command routine for the ATQ, depending 1810 * on the opcode. 1811 */ 1812 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1813 { 1814 switch (opcode) { 1815 case ice_aqc_opc_get_link_topo: 1816 case ice_aqc_opc_lldp_stop: 1817 case ice_aqc_opc_lldp_start: 1818 case ice_aqc_opc_lldp_filter_ctrl: 1819 case ice_aqc_opc_sff_eeprom: 1820 return true; 1821 } 1822 1823 return false; 1824 } 1825 1826 /** 1827 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1828 * @hw: pointer to the HW struct 1829 * @cq: pointer to the specific Control queue 1830 * @desc: prefilled descriptor describing the command 1831 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1832 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1833 * @cd: pointer to command details structure 1834 * 1835 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1836 * Queue if the EBUSY AQ error is returned. 1837 */ 1838 static int 1839 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1840 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1841 struct ice_sq_cd *cd) 1842 { 1843 struct libie_aq_desc desc_cpy; 1844 bool is_cmd_for_retry; 1845 u8 *buf_cpy = NULL; 1846 u8 idx = 0; 1847 u16 opcode; 1848 int status; 1849 1850 opcode = le16_to_cpu(desc->opcode); 1851 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1852 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1853 1854 if (is_cmd_for_retry) { 1855 if (buf) { 1856 buf_cpy = kmemdup(buf, buf_size, GFP_KERNEL); 1857 if (!buf_cpy) 1858 return -ENOMEM; 1859 } 1860 1861 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1862 } 1863 1864 do { 1865 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1866 1867 if (!is_cmd_for_retry || !status || 1868 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1869 break; 1870 1871 if (buf_cpy) 1872 memcpy(buf, buf_cpy, buf_size); 1873 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1874 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1875 1876 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1877 1878 kfree(buf_cpy); 1879 return status; 1880 } 1881 1882 /** 1883 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1884 * @hw: pointer to the HW struct 1885 * @desc: descriptor describing the command 1886 * @buf: buffer to use for indirect commands (NULL for direct commands) 1887 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1888 * @cd: pointer to command details structure 1889 * 1890 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1891 */ 1892 int 1893 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1894 u16 buf_size, struct ice_sq_cd *cd) 1895 { 1896 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1897 bool lock_acquired = false; 1898 int status; 1899 1900 /* When a package download is in process (i.e. when the firmware's 1901 * Global Configuration Lock resource is held), only the Download 1902 * Package, Get Version, Get Package Info List, Upload Section, 1903 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1904 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1905 * Recipes to Profile Association, and Release Resource (with resource 1906 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1907 * must block until the package download completes and the Global Config 1908 * Lock is released. See also ice_acquire_global_cfg_lock(). 1909 */ 1910 switch (le16_to_cpu(desc->opcode)) { 1911 case ice_aqc_opc_download_pkg: 1912 case ice_aqc_opc_get_pkg_info_list: 1913 case ice_aqc_opc_get_ver: 1914 case ice_aqc_opc_upload_section: 1915 case ice_aqc_opc_update_pkg: 1916 case ice_aqc_opc_set_port_params: 1917 case ice_aqc_opc_get_vlan_mode_parameters: 1918 case ice_aqc_opc_set_vlan_mode_parameters: 1919 case ice_aqc_opc_set_tx_topo: 1920 case ice_aqc_opc_get_tx_topo: 1921 case ice_aqc_opc_add_recipe: 1922 case ice_aqc_opc_recipe_to_profile: 1923 case ice_aqc_opc_get_recipe: 1924 case ice_aqc_opc_get_recipe_to_profile: 1925 break; 1926 case ice_aqc_opc_release_res: 1927 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1928 break; 1929 fallthrough; 1930 default: 1931 mutex_lock(&ice_global_cfg_lock_sw); 1932 lock_acquired = true; 1933 break; 1934 } 1935 1936 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1937 if (lock_acquired) 1938 mutex_unlock(&ice_global_cfg_lock_sw); 1939 1940 return status; 1941 } 1942 1943 /** 1944 * ice_aq_get_fw_ver 1945 * @hw: pointer to the HW struct 1946 * @cd: pointer to command details structure or NULL 1947 * 1948 * Get the firmware version (0x0001) from the admin queue commands 1949 */ 1950 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1951 { 1952 struct libie_aqc_get_ver *resp; 1953 struct libie_aq_desc desc; 1954 int status; 1955 1956 resp = &desc.params.get_ver; 1957 1958 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1959 1960 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1961 1962 if (!status) { 1963 hw->fw_branch = resp->fw_branch; 1964 hw->fw_maj_ver = resp->fw_major; 1965 hw->fw_min_ver = resp->fw_minor; 1966 hw->fw_patch = resp->fw_patch; 1967 hw->fw_build = le32_to_cpu(resp->fw_build); 1968 hw->api_branch = resp->api_branch; 1969 hw->api_maj_ver = resp->api_major; 1970 hw->api_min_ver = resp->api_minor; 1971 hw->api_patch = resp->api_patch; 1972 } 1973 1974 return status; 1975 } 1976 1977 /** 1978 * ice_aq_send_driver_ver 1979 * @hw: pointer to the HW struct 1980 * @dv: driver's major, minor version 1981 * @cd: pointer to command details structure or NULL 1982 * 1983 * Send the driver version (0x0002) to the firmware 1984 */ 1985 int 1986 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1987 struct ice_sq_cd *cd) 1988 { 1989 struct libie_aqc_driver_ver *cmd; 1990 struct libie_aq_desc desc; 1991 u16 len; 1992 1993 cmd = &desc.params.driver_ver; 1994 1995 if (!dv) 1996 return -EINVAL; 1997 1998 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1999 2000 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2001 cmd->major_ver = dv->major_ver; 2002 cmd->minor_ver = dv->minor_ver; 2003 cmd->build_ver = dv->build_ver; 2004 cmd->subbuild_ver = dv->subbuild_ver; 2005 2006 len = 0; 2007 while (len < sizeof(dv->driver_string) && 2008 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2009 len++; 2010 2011 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2012 } 2013 2014 /** 2015 * ice_aq_q_shutdown 2016 * @hw: pointer to the HW struct 2017 * @unloading: is the driver unloading itself 2018 * 2019 * Tell the Firmware that we're shutting down the AdminQ and whether 2020 * or not the driver is unloading as well (0x0003). 2021 */ 2022 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2023 { 2024 struct ice_aqc_q_shutdown *cmd; 2025 struct libie_aq_desc desc; 2026 2027 cmd = libie_aq_raw(&desc); 2028 2029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2030 2031 if (unloading) 2032 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2033 2034 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2035 } 2036 2037 /** 2038 * ice_aq_req_res 2039 * @hw: pointer to the HW struct 2040 * @res: resource ID 2041 * @access: access type 2042 * @sdp_number: resource number 2043 * @timeout: the maximum time in ms that the driver may hold the resource 2044 * @cd: pointer to command details structure or NULL 2045 * 2046 * Requests common resource using the admin queue commands (0x0008). 2047 * When attempting to acquire the Global Config Lock, the driver can 2048 * learn of three states: 2049 * 1) 0 - acquired lock, and can perform download package 2050 * 2) -EIO - did not get lock, driver should fail to load 2051 * 3) -EALREADY - did not get lock, but another driver has 2052 * successfully downloaded the package; the driver does 2053 * not have to download the package and can continue 2054 * loading 2055 * 2056 * Note that if the caller is in an acquire lock, perform action, release lock 2057 * phase of operation, it is possible that the FW may detect a timeout and issue 2058 * a CORER. In this case, the driver will receive a CORER interrupt and will 2059 * have to determine its cause. The calling thread that is handling this flow 2060 * will likely get an error propagated back to it indicating the Download 2061 * Package, Update Package or the Release Resource AQ commands timed out. 2062 */ 2063 static int 2064 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2065 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2066 struct ice_sq_cd *cd) 2067 { 2068 struct libie_aqc_req_res *cmd_resp; 2069 struct libie_aq_desc desc; 2070 int status; 2071 2072 cmd_resp = &desc.params.res_owner; 2073 2074 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2075 2076 cmd_resp->res_id = cpu_to_le16(res); 2077 cmd_resp->access_type = cpu_to_le16(access); 2078 cmd_resp->res_number = cpu_to_le32(sdp_number); 2079 cmd_resp->timeout = cpu_to_le32(*timeout); 2080 *timeout = 0; 2081 2082 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2083 2084 /* The completion specifies the maximum time in ms that the driver 2085 * may hold the resource in the Timeout field. 2086 */ 2087 2088 /* Global config lock response utilizes an additional status field. 2089 * 2090 * If the Global config lock resource is held by some other driver, the 2091 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2092 * and the timeout field indicates the maximum time the current owner 2093 * of the resource has to free it. 2094 */ 2095 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2096 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2097 *timeout = le32_to_cpu(cmd_resp->timeout); 2098 return 0; 2099 } else if (le16_to_cpu(cmd_resp->status) == 2100 LIBIE_AQ_RES_GLBL_IN_PROG) { 2101 *timeout = le32_to_cpu(cmd_resp->timeout); 2102 return -EIO; 2103 } else if (le16_to_cpu(cmd_resp->status) == 2104 LIBIE_AQ_RES_GLBL_DONE) { 2105 return -EALREADY; 2106 } 2107 2108 /* invalid FW response, force a timeout immediately */ 2109 *timeout = 0; 2110 return -EIO; 2111 } 2112 2113 /* If the resource is held by some other driver, the command completes 2114 * with a busy return value and the timeout field indicates the maximum 2115 * time the current owner of the resource has to free it. 2116 */ 2117 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2118 *timeout = le32_to_cpu(cmd_resp->timeout); 2119 2120 return status; 2121 } 2122 2123 /** 2124 * ice_aq_release_res 2125 * @hw: pointer to the HW struct 2126 * @res: resource ID 2127 * @sdp_number: resource number 2128 * @cd: pointer to command details structure or NULL 2129 * 2130 * release common resource using the admin queue commands (0x0009) 2131 */ 2132 static int 2133 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2134 struct ice_sq_cd *cd) 2135 { 2136 struct libie_aqc_req_res *cmd; 2137 struct libie_aq_desc desc; 2138 2139 cmd = &desc.params.res_owner; 2140 2141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2142 2143 cmd->res_id = cpu_to_le16(res); 2144 cmd->res_number = cpu_to_le32(sdp_number); 2145 2146 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2147 } 2148 2149 /** 2150 * ice_acquire_res 2151 * @hw: pointer to the HW structure 2152 * @res: resource ID 2153 * @access: access type (read or write) 2154 * @timeout: timeout in milliseconds 2155 * 2156 * This function will attempt to acquire the ownership of a resource. 2157 */ 2158 int 2159 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2160 enum ice_aq_res_access_type access, u32 timeout) 2161 { 2162 #define ICE_RES_POLLING_DELAY_MS 10 2163 u32 delay = ICE_RES_POLLING_DELAY_MS; 2164 u32 time_left = timeout; 2165 int status; 2166 2167 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2168 2169 /* A return code of -EALREADY means that another driver has 2170 * previously acquired the resource and performed any necessary updates; 2171 * in this case the caller does not obtain the resource and has no 2172 * further work to do. 2173 */ 2174 if (status == -EALREADY) 2175 goto ice_acquire_res_exit; 2176 2177 if (status) 2178 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2179 2180 /* If necessary, poll until the current lock owner timeouts */ 2181 timeout = time_left; 2182 while (status && timeout && time_left) { 2183 mdelay(delay); 2184 timeout = (timeout > delay) ? timeout - delay : 0; 2185 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2186 2187 if (status == -EALREADY) 2188 /* lock free, but no work to do */ 2189 break; 2190 2191 if (!status) 2192 /* lock acquired */ 2193 break; 2194 } 2195 if (status && status != -EALREADY) 2196 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2197 2198 ice_acquire_res_exit: 2199 if (status == -EALREADY) { 2200 if (access == ICE_RES_WRITE) 2201 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2202 else 2203 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2204 } 2205 return status; 2206 } 2207 2208 /** 2209 * ice_release_res 2210 * @hw: pointer to the HW structure 2211 * @res: resource ID 2212 * 2213 * This function will release a resource using the proper Admin Command. 2214 */ 2215 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2216 { 2217 unsigned long timeout; 2218 int status; 2219 2220 /* there are some rare cases when trying to release the resource 2221 * results in an admin queue timeout, so handle them correctly 2222 */ 2223 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2224 do { 2225 status = ice_aq_release_res(hw, res, 0, NULL); 2226 if (status != -EIO) 2227 break; 2228 usleep_range(1000, 2000); 2229 } while (time_before(jiffies, timeout)); 2230 } 2231 2232 /** 2233 * ice_aq_alloc_free_res - command to allocate/free resources 2234 * @hw: pointer to the HW struct 2235 * @buf: Indirect buffer to hold data parameters and response 2236 * @buf_size: size of buffer for indirect commands 2237 * @opc: pass in the command opcode 2238 * 2239 * Helper function to allocate/free resources using the admin queue commands 2240 */ 2241 int ice_aq_alloc_free_res(struct ice_hw *hw, 2242 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2243 enum ice_adminq_opc opc) 2244 { 2245 struct ice_aqc_alloc_free_res_cmd *cmd; 2246 struct libie_aq_desc desc; 2247 2248 cmd = libie_aq_raw(&desc); 2249 2250 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2251 return -EINVAL; 2252 2253 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2254 2255 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2256 2257 cmd->num_entries = cpu_to_le16(1); 2258 2259 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2260 } 2261 2262 /** 2263 * ice_alloc_hw_res - allocate resource 2264 * @hw: pointer to the HW struct 2265 * @type: type of resource 2266 * @num: number of resources to allocate 2267 * @btm: allocate from bottom 2268 * @res: pointer to array that will receive the resources 2269 */ 2270 int 2271 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2272 { 2273 struct ice_aqc_alloc_free_res_elem *buf; 2274 u16 buf_len; 2275 int status; 2276 2277 buf_len = struct_size(buf, elem, num); 2278 buf = kzalloc(buf_len, GFP_KERNEL); 2279 if (!buf) 2280 return -ENOMEM; 2281 2282 /* Prepare buffer to allocate resource. */ 2283 buf->num_elems = cpu_to_le16(num); 2284 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2285 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2286 if (btm) 2287 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2288 2289 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2290 if (status) 2291 goto ice_alloc_res_exit; 2292 2293 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2294 2295 ice_alloc_res_exit: 2296 kfree(buf); 2297 return status; 2298 } 2299 2300 /** 2301 * ice_free_hw_res - free allocated HW resource 2302 * @hw: pointer to the HW struct 2303 * @type: type of resource to free 2304 * @num: number of resources 2305 * @res: pointer to array that contains the resources to free 2306 */ 2307 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2308 { 2309 struct ice_aqc_alloc_free_res_elem *buf; 2310 u16 buf_len; 2311 int status; 2312 2313 buf_len = struct_size(buf, elem, num); 2314 buf = kzalloc(buf_len, GFP_KERNEL); 2315 if (!buf) 2316 return -ENOMEM; 2317 2318 /* Prepare buffer to free resource. */ 2319 buf->num_elems = cpu_to_le16(num); 2320 buf->res_type = cpu_to_le16(type); 2321 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2322 2323 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2324 if (status) 2325 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2326 2327 kfree(buf); 2328 return status; 2329 } 2330 2331 /** 2332 * ice_get_num_per_func - determine number of resources per PF 2333 * @hw: pointer to the HW structure 2334 * @max: value to be evenly split between each PF 2335 * 2336 * Determine the number of valid functions by going through the bitmap returned 2337 * from parsing capabilities and use this to calculate the number of resources 2338 * per PF based on the max value passed in. 2339 */ 2340 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2341 { 2342 u8 funcs; 2343 2344 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2345 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2346 ICE_CAPS_VALID_FUNCS_M); 2347 2348 if (!funcs) 2349 return 0; 2350 2351 return max / funcs; 2352 } 2353 2354 /** 2355 * ice_parse_common_caps - parse common device/function capabilities 2356 * @hw: pointer to the HW struct 2357 * @caps: pointer to common capabilities structure 2358 * @elem: the capability element to parse 2359 * @prefix: message prefix for tracing capabilities 2360 * 2361 * Given a capability element, extract relevant details into the common 2362 * capability structure. 2363 * 2364 * Returns: true if the capability matches one of the common capability ids, 2365 * false otherwise. 2366 */ 2367 static bool 2368 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2369 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2370 { 2371 u32 logical_id = le32_to_cpu(elem->logical_id); 2372 u32 phys_id = le32_to_cpu(elem->phys_id); 2373 u32 number = le32_to_cpu(elem->number); 2374 u16 cap = le16_to_cpu(elem->cap); 2375 bool found = true; 2376 2377 switch (cap) { 2378 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2379 caps->valid_functions = number; 2380 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2381 caps->valid_functions); 2382 break; 2383 case LIBIE_AQC_CAPS_SRIOV: 2384 caps->sr_iov_1_1 = (number == 1); 2385 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2386 caps->sr_iov_1_1); 2387 break; 2388 case LIBIE_AQC_CAPS_DCB: 2389 caps->dcb = (number == 1); 2390 caps->active_tc_bitmap = logical_id; 2391 caps->maxtc = phys_id; 2392 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2393 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2394 caps->active_tc_bitmap); 2395 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2396 break; 2397 case LIBIE_AQC_CAPS_RSS: 2398 caps->rss_table_size = number; 2399 caps->rss_table_entry_width = logical_id; 2400 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2401 caps->rss_table_size); 2402 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2403 caps->rss_table_entry_width); 2404 break; 2405 case LIBIE_AQC_CAPS_RXQS: 2406 caps->num_rxq = number; 2407 caps->rxq_first_id = phys_id; 2408 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2409 caps->num_rxq); 2410 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2411 caps->rxq_first_id); 2412 break; 2413 case LIBIE_AQC_CAPS_TXQS: 2414 caps->num_txq = number; 2415 caps->txq_first_id = phys_id; 2416 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2417 caps->num_txq); 2418 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2419 caps->txq_first_id); 2420 break; 2421 case LIBIE_AQC_CAPS_MSIX: 2422 caps->num_msix_vectors = number; 2423 caps->msix_vector_first_id = phys_id; 2424 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2425 caps->num_msix_vectors); 2426 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2427 caps->msix_vector_first_id); 2428 break; 2429 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2430 caps->nvm_update_pending_nvm = true; 2431 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2432 break; 2433 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2434 caps->nvm_update_pending_orom = true; 2435 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2436 break; 2437 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2438 caps->nvm_update_pending_netlist = true; 2439 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2440 break; 2441 case LIBIE_AQC_CAPS_NVM_MGMT: 2442 caps->nvm_unified_update = 2443 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2444 true : false; 2445 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2446 caps->nvm_unified_update); 2447 break; 2448 case LIBIE_AQC_CAPS_RDMA: 2449 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2450 caps->rdma = (number == 1); 2451 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2452 break; 2453 case LIBIE_AQC_CAPS_MAX_MTU: 2454 caps->max_mtu = number; 2455 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2456 prefix, caps->max_mtu); 2457 break; 2458 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2459 caps->pcie_reset_avoidance = (number > 0); 2460 ice_debug(hw, ICE_DBG_INIT, 2461 "%s: pcie_reset_avoidance = %d\n", prefix, 2462 caps->pcie_reset_avoidance); 2463 break; 2464 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2465 caps->reset_restrict_support = (number == 1); 2466 ice_debug(hw, ICE_DBG_INIT, 2467 "%s: reset_restrict_support = %d\n", prefix, 2468 caps->reset_restrict_support); 2469 break; 2470 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2471 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2472 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2473 prefix, caps->roce_lag); 2474 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2475 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2476 prefix, caps->sriov_lag); 2477 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2478 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2479 prefix, caps->sriov_aa_lag); 2480 break; 2481 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2482 caps->tx_sched_topo_comp_mode_en = (number == 1); 2483 break; 2484 default: 2485 /* Not one of the recognized common capabilities */ 2486 found = false; 2487 } 2488 2489 return found; 2490 } 2491 2492 /** 2493 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2494 * @hw: pointer to the HW structure 2495 * @caps: pointer to capabilities structure to fix 2496 * 2497 * Re-calculate the capabilities that are dependent on the number of physical 2498 * ports; i.e. some features are not supported or function differently on 2499 * devices with more than 4 ports. 2500 */ 2501 static void 2502 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2503 { 2504 /* This assumes device capabilities are always scanned before function 2505 * capabilities during the initialization flow. 2506 */ 2507 if (hw->dev_caps.num_funcs > 4) { 2508 /* Max 4 TCs per port */ 2509 caps->maxtc = 4; 2510 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2511 caps->maxtc); 2512 if (caps->rdma) { 2513 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2514 caps->rdma = 0; 2515 } 2516 2517 /* print message only when processing device capabilities 2518 * during initialization. 2519 */ 2520 if (caps == &hw->dev_caps.common_cap) 2521 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2522 } 2523 } 2524 2525 /** 2526 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2527 * @hw: pointer to the HW struct 2528 * @func_p: pointer to function capabilities structure 2529 * @cap: pointer to the capability element to parse 2530 * 2531 * Extract function capabilities for ICE_AQC_CAPS_VF. 2532 */ 2533 static void 2534 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2535 struct libie_aqc_list_caps_elem *cap) 2536 { 2537 u32 logical_id = le32_to_cpu(cap->logical_id); 2538 u32 number = le32_to_cpu(cap->number); 2539 2540 func_p->num_allocd_vfs = number; 2541 func_p->vf_base_id = logical_id; 2542 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2543 func_p->num_allocd_vfs); 2544 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2545 func_p->vf_base_id); 2546 } 2547 2548 /** 2549 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2550 * @hw: pointer to the HW struct 2551 * @func_p: pointer to function capabilities structure 2552 * @cap: pointer to the capability element to parse 2553 * 2554 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2555 */ 2556 static void 2557 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2558 struct libie_aqc_list_caps_elem *cap) 2559 { 2560 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2561 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2562 le32_to_cpu(cap->number)); 2563 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2564 func_p->guar_num_vsi); 2565 } 2566 2567 /** 2568 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2569 * @hw: pointer to the HW struct 2570 * @func_p: pointer to function capabilities structure 2571 * @cap: pointer to the capability element to parse 2572 * 2573 * Extract function capabilities for ICE_AQC_CAPS_1588. 2574 */ 2575 static void 2576 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2577 struct libie_aqc_list_caps_elem *cap) 2578 { 2579 struct ice_ts_func_info *info = &func_p->ts_func_info; 2580 u32 number = le32_to_cpu(cap->number); 2581 2582 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2583 func_p->common_cap.ieee_1588 = info->ena; 2584 2585 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2586 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2587 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2588 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2589 2590 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2591 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2592 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2593 } else { 2594 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2595 info->clk_src = ICE_CLK_SRC_TIME_REF; 2596 } 2597 2598 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2599 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2600 } else { 2601 /* Unknown clock frequency, so assume a (probably incorrect) 2602 * default to avoid out-of-bounds look ups of frequency 2603 * related information. 2604 */ 2605 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2606 info->clk_freq); 2607 info->time_ref = ICE_TSPLL_FREQ_25_000; 2608 } 2609 2610 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2611 func_p->common_cap.ieee_1588); 2612 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2613 info->src_tmr_owned); 2614 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2615 info->tmr_ena); 2616 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2617 info->tmr_index_owned); 2618 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2619 info->tmr_index_assoc); 2620 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2621 info->clk_freq); 2622 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2623 info->clk_src); 2624 } 2625 2626 /** 2627 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2628 * @hw: pointer to the HW struct 2629 * @func_p: pointer to function capabilities structure 2630 * 2631 * Extract function capabilities for ICE_AQC_CAPS_FD. 2632 */ 2633 static void 2634 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2635 { 2636 u32 reg_val, gsize, bsize; 2637 2638 reg_val = rd32(hw, GLQF_FD_SIZE); 2639 switch (hw->mac_type) { 2640 case ICE_MAC_E830: 2641 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2642 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2643 break; 2644 case ICE_MAC_E810: 2645 default: 2646 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2647 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2648 } 2649 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2650 func_p->fd_fltr_best_effort = bsize; 2651 2652 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2653 func_p->fd_fltr_guar); 2654 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2655 func_p->fd_fltr_best_effort); 2656 } 2657 2658 /** 2659 * ice_parse_func_caps - Parse function capabilities 2660 * @hw: pointer to the HW struct 2661 * @func_p: pointer to function capabilities structure 2662 * @buf: buffer containing the function capability records 2663 * @cap_count: the number of capabilities 2664 * 2665 * Helper function to parse function (0x000A) capabilities list. For 2666 * capabilities shared between device and function, this relies on 2667 * ice_parse_common_caps. 2668 * 2669 * Loop through the list of provided capabilities and extract the relevant 2670 * data into the function capabilities structured. 2671 */ 2672 static void 2673 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2674 void *buf, u32 cap_count) 2675 { 2676 struct libie_aqc_list_caps_elem *cap_resp; 2677 u32 i; 2678 2679 cap_resp = buf; 2680 2681 memset(func_p, 0, sizeof(*func_p)); 2682 2683 for (i = 0; i < cap_count; i++) { 2684 u16 cap = le16_to_cpu(cap_resp[i].cap); 2685 bool found; 2686 2687 found = ice_parse_common_caps(hw, &func_p->common_cap, 2688 &cap_resp[i], "func caps"); 2689 2690 switch (cap) { 2691 case LIBIE_AQC_CAPS_VF: 2692 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2693 break; 2694 case LIBIE_AQC_CAPS_VSI: 2695 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2696 break; 2697 case LIBIE_AQC_CAPS_1588: 2698 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2699 break; 2700 case LIBIE_AQC_CAPS_FD: 2701 ice_parse_fdir_func_caps(hw, func_p); 2702 break; 2703 default: 2704 /* Don't list common capabilities as unknown */ 2705 if (!found) 2706 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2707 i, cap); 2708 break; 2709 } 2710 } 2711 2712 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2713 } 2714 2715 /** 2716 * ice_func_id_to_logical_id - map from function id to logical pf id 2717 * @active_function_bitmap: active function bitmap 2718 * @pf_id: function number of device 2719 * 2720 * Return: logical PF ID. 2721 */ 2722 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2723 { 2724 u8 logical_id = 0; 2725 u8 i; 2726 2727 for (i = 0; i < pf_id; i++) 2728 if (active_function_bitmap & BIT(i)) 2729 logical_id++; 2730 2731 return logical_id; 2732 } 2733 2734 /** 2735 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2736 * @hw: pointer to the HW struct 2737 * @dev_p: pointer to device capabilities structure 2738 * @cap: capability element to parse 2739 * 2740 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2741 */ 2742 static void 2743 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2744 struct libie_aqc_list_caps_elem *cap) 2745 { 2746 u32 number = le32_to_cpu(cap->number); 2747 2748 dev_p->num_funcs = hweight32(number); 2749 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2750 dev_p->num_funcs); 2751 2752 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2753 } 2754 2755 /** 2756 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2757 * @hw: pointer to the HW struct 2758 * @dev_p: pointer to device capabilities structure 2759 * @cap: capability element to parse 2760 * 2761 * Parse ICE_AQC_CAPS_VF for device capabilities. 2762 */ 2763 static void 2764 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2765 struct libie_aqc_list_caps_elem *cap) 2766 { 2767 u32 number = le32_to_cpu(cap->number); 2768 2769 dev_p->num_vfs_exposed = number; 2770 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2771 dev_p->num_vfs_exposed); 2772 } 2773 2774 /** 2775 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2776 * @hw: pointer to the HW struct 2777 * @dev_p: pointer to device capabilities structure 2778 * @cap: capability element to parse 2779 * 2780 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2781 */ 2782 static void 2783 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2784 struct libie_aqc_list_caps_elem *cap) 2785 { 2786 u32 number = le32_to_cpu(cap->number); 2787 2788 dev_p->num_vsi_allocd_to_host = number; 2789 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2790 dev_p->num_vsi_allocd_to_host); 2791 } 2792 2793 /** 2794 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2795 * @hw: pointer to the HW struct 2796 * @dev_p: pointer to device capabilities structure 2797 * @cap: capability element to parse 2798 * 2799 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2800 */ 2801 static void 2802 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2803 struct libie_aqc_list_caps_elem *cap) 2804 { 2805 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2806 u32 logical_id = le32_to_cpu(cap->logical_id); 2807 u32 phys_id = le32_to_cpu(cap->phys_id); 2808 u32 number = le32_to_cpu(cap->number); 2809 2810 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2811 dev_p->common_cap.ieee_1588 = info->ena; 2812 2813 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2814 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2815 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2816 2817 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2818 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2819 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2820 2821 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2822 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2823 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2824 2825 info->ena_ports = logical_id; 2826 info->tmr_own_map = phys_id; 2827 2828 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2829 dev_p->common_cap.ieee_1588); 2830 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2831 info->tmr0_owner); 2832 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2833 info->tmr0_owned); 2834 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2835 info->tmr0_ena); 2836 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2837 info->tmr1_owner); 2838 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2839 info->tmr1_owned); 2840 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2841 info->tmr1_ena); 2842 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2843 info->ts_ll_read); 2844 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2845 info->ts_ll_int_read); 2846 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2847 info->ll_phy_tmr_update); 2848 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2849 info->ena_ports); 2850 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2851 info->tmr_own_map); 2852 } 2853 2854 /** 2855 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2856 * @hw: pointer to the HW struct 2857 * @dev_p: pointer to device capabilities structure 2858 * @cap: capability element to parse 2859 * 2860 * Parse ICE_AQC_CAPS_FD for device capabilities. 2861 */ 2862 static void 2863 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2864 struct libie_aqc_list_caps_elem *cap) 2865 { 2866 u32 number = le32_to_cpu(cap->number); 2867 2868 dev_p->num_flow_director_fltr = number; 2869 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2870 dev_p->num_flow_director_fltr); 2871 } 2872 2873 /** 2874 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2875 * @hw: pointer to the HW struct 2876 * @dev_p: pointer to device capabilities structure 2877 * @cap: capability element to parse 2878 * 2879 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2880 * enabled sensors. 2881 */ 2882 static void 2883 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2884 struct libie_aqc_list_caps_elem *cap) 2885 { 2886 dev_p->supported_sensors = le32_to_cpu(cap->number); 2887 2888 ice_debug(hw, ICE_DBG_INIT, 2889 "dev caps: supported sensors (bitmap) = 0x%x\n", 2890 dev_p->supported_sensors); 2891 } 2892 2893 /** 2894 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2895 * @hw: pointer to the HW struct 2896 * @dev_p: pointer to device capabilities structure 2897 * @cap: capability element to parse 2898 * 2899 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2900 */ 2901 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2902 struct ice_hw_dev_caps *dev_p, 2903 struct libie_aqc_list_caps_elem *cap) 2904 { 2905 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2906 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2907 2908 dev_info(ice_hw_to_dev(hw), 2909 "PF is configured in %s mode with IP instance ID %d\n", 2910 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2911 "primary" : "secondary", dev_p->nac_topo.id); 2912 2913 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2914 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2915 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2916 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2917 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2918 dev_p->nac_topo.id); 2919 } 2920 2921 /** 2922 * ice_parse_dev_caps - Parse device capabilities 2923 * @hw: pointer to the HW struct 2924 * @dev_p: pointer to device capabilities structure 2925 * @buf: buffer containing the device capability records 2926 * @cap_count: the number of capabilities 2927 * 2928 * Helper device to parse device (0x000B) capabilities list. For 2929 * capabilities shared between device and function, this relies on 2930 * ice_parse_common_caps. 2931 * 2932 * Loop through the list of provided capabilities and extract the relevant 2933 * data into the device capabilities structured. 2934 */ 2935 static void 2936 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2937 void *buf, u32 cap_count) 2938 { 2939 struct libie_aqc_list_caps_elem *cap_resp; 2940 u32 i; 2941 2942 cap_resp = buf; 2943 2944 memset(dev_p, 0, sizeof(*dev_p)); 2945 2946 for (i = 0; i < cap_count; i++) { 2947 u16 cap = le16_to_cpu(cap_resp[i].cap); 2948 bool found; 2949 2950 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2951 &cap_resp[i], "dev caps"); 2952 2953 switch (cap) { 2954 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2955 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2956 break; 2957 case LIBIE_AQC_CAPS_VF: 2958 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2959 break; 2960 case LIBIE_AQC_CAPS_VSI: 2961 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2962 break; 2963 case LIBIE_AQC_CAPS_1588: 2964 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2965 break; 2966 case LIBIE_AQC_CAPS_FD: 2967 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2968 break; 2969 case LIBIE_AQC_CAPS_SENSOR_READING: 2970 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2971 break; 2972 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2973 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2974 break; 2975 default: 2976 /* Don't list common capabilities as unknown */ 2977 if (!found) 2978 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2979 i, cap); 2980 break; 2981 } 2982 } 2983 2984 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2985 } 2986 2987 /** 2988 * ice_is_phy_rclk_in_netlist 2989 * @hw: pointer to the hw struct 2990 * 2991 * Check if the PHY Recovered Clock device is present in the netlist 2992 */ 2993 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2994 { 2995 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2996 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2997 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2998 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2999 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3000 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3001 return false; 3002 3003 return true; 3004 } 3005 3006 /** 3007 * ice_is_clock_mux_in_netlist 3008 * @hw: pointer to the hw struct 3009 * 3010 * Check if the Clock Multiplexer device is present in the netlist 3011 */ 3012 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3013 { 3014 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3015 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3016 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3017 NULL)) 3018 return false; 3019 3020 return true; 3021 } 3022 3023 /** 3024 * ice_is_cgu_in_netlist - check for CGU presence 3025 * @hw: pointer to the hw struct 3026 * 3027 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3028 * Save the CGU part number in the hw structure for later use. 3029 * Return: 3030 * * true - cgu is present 3031 * * false - cgu is not present 3032 */ 3033 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3034 { 3035 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3036 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3037 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3038 NULL)) { 3039 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3040 return true; 3041 } else if (!ice_find_netlist_node(hw, 3042 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3043 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3044 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3045 NULL)) { 3046 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3047 return true; 3048 } 3049 3050 return false; 3051 } 3052 3053 /** 3054 * ice_is_gps_in_netlist 3055 * @hw: pointer to the hw struct 3056 * 3057 * Check if the GPS generic device is present in the netlist 3058 */ 3059 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3060 { 3061 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3062 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3063 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3064 return false; 3065 3066 return true; 3067 } 3068 3069 /** 3070 * ice_aq_list_caps - query function/device capabilities 3071 * @hw: pointer to the HW struct 3072 * @buf: a buffer to hold the capabilities 3073 * @buf_size: size of the buffer 3074 * @cap_count: if not NULL, set to the number of capabilities reported 3075 * @opc: capabilities type to discover, device or function 3076 * @cd: pointer to command details structure or NULL 3077 * 3078 * Get the function (0x000A) or device (0x000B) capabilities description from 3079 * firmware and store it in the buffer. 3080 * 3081 * If the cap_count pointer is not NULL, then it is set to the number of 3082 * capabilities firmware will report. Note that if the buffer size is too 3083 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3084 * cap_count will still be updated in this case. It is recommended that the 3085 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3086 * firmware could return) to avoid this. 3087 */ 3088 int 3089 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3090 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3091 { 3092 struct libie_aqc_list_caps *cmd; 3093 struct libie_aq_desc desc; 3094 int status; 3095 3096 cmd = &desc.params.get_cap; 3097 3098 if (opc != ice_aqc_opc_list_func_caps && 3099 opc != ice_aqc_opc_list_dev_caps) 3100 return -EINVAL; 3101 3102 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3103 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3104 3105 if (cap_count) 3106 *cap_count = le32_to_cpu(cmd->count); 3107 3108 return status; 3109 } 3110 3111 /** 3112 * ice_discover_dev_caps - Read and extract device capabilities 3113 * @hw: pointer to the hardware structure 3114 * @dev_caps: pointer to device capabilities structure 3115 * 3116 * Read the device capabilities and extract them into the dev_caps structure 3117 * for later use. 3118 */ 3119 int 3120 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3121 { 3122 u32 cap_count = 0; 3123 void *cbuf; 3124 int status; 3125 3126 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3127 if (!cbuf) 3128 return -ENOMEM; 3129 3130 /* Although the driver doesn't know the number of capabilities the 3131 * device will return, we can simply send a 4KB buffer, the maximum 3132 * possible size that firmware can return. 3133 */ 3134 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3135 3136 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3137 ice_aqc_opc_list_dev_caps, NULL); 3138 if (!status) 3139 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3140 kfree(cbuf); 3141 3142 return status; 3143 } 3144 3145 /** 3146 * ice_discover_func_caps - Read and extract function capabilities 3147 * @hw: pointer to the hardware structure 3148 * @func_caps: pointer to function capabilities structure 3149 * 3150 * Read the function capabilities and extract them into the func_caps structure 3151 * for later use. 3152 */ 3153 static int 3154 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3155 { 3156 u32 cap_count = 0; 3157 void *cbuf; 3158 int status; 3159 3160 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3161 if (!cbuf) 3162 return -ENOMEM; 3163 3164 /* Although the driver doesn't know the number of capabilities the 3165 * device will return, we can simply send a 4KB buffer, the maximum 3166 * possible size that firmware can return. 3167 */ 3168 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3169 3170 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3171 ice_aqc_opc_list_func_caps, NULL); 3172 if (!status) 3173 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3174 kfree(cbuf); 3175 3176 return status; 3177 } 3178 3179 /** 3180 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3181 * @hw: pointer to the hardware structure 3182 */ 3183 void ice_set_safe_mode_caps(struct ice_hw *hw) 3184 { 3185 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3186 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3187 struct ice_hw_common_caps cached_caps; 3188 u32 num_funcs; 3189 3190 /* cache some func_caps values that should be restored after memset */ 3191 cached_caps = func_caps->common_cap; 3192 3193 /* unset func capabilities */ 3194 memset(func_caps, 0, sizeof(*func_caps)); 3195 3196 #define ICE_RESTORE_FUNC_CAP(name) \ 3197 func_caps->common_cap.name = cached_caps.name 3198 3199 /* restore cached values */ 3200 ICE_RESTORE_FUNC_CAP(valid_functions); 3201 ICE_RESTORE_FUNC_CAP(txq_first_id); 3202 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3203 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3204 ICE_RESTORE_FUNC_CAP(max_mtu); 3205 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3206 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3207 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3208 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3209 3210 /* one Tx and one Rx queue in safe mode */ 3211 func_caps->common_cap.num_rxq = 1; 3212 func_caps->common_cap.num_txq = 1; 3213 3214 /* two MSIX vectors, one for traffic and one for misc causes */ 3215 func_caps->common_cap.num_msix_vectors = 2; 3216 func_caps->guar_num_vsi = 1; 3217 3218 /* cache some dev_caps values that should be restored after memset */ 3219 cached_caps = dev_caps->common_cap; 3220 num_funcs = dev_caps->num_funcs; 3221 3222 /* unset dev capabilities */ 3223 memset(dev_caps, 0, sizeof(*dev_caps)); 3224 3225 #define ICE_RESTORE_DEV_CAP(name) \ 3226 dev_caps->common_cap.name = cached_caps.name 3227 3228 /* restore cached values */ 3229 ICE_RESTORE_DEV_CAP(valid_functions); 3230 ICE_RESTORE_DEV_CAP(txq_first_id); 3231 ICE_RESTORE_DEV_CAP(rxq_first_id); 3232 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3233 ICE_RESTORE_DEV_CAP(max_mtu); 3234 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3235 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3236 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3237 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3238 dev_caps->num_funcs = num_funcs; 3239 3240 /* one Tx and one Rx queue per function in safe mode */ 3241 dev_caps->common_cap.num_rxq = num_funcs; 3242 dev_caps->common_cap.num_txq = num_funcs; 3243 3244 /* two MSIX vectors per function */ 3245 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3246 } 3247 3248 /** 3249 * ice_get_caps - get info about the HW 3250 * @hw: pointer to the hardware structure 3251 */ 3252 int ice_get_caps(struct ice_hw *hw) 3253 { 3254 int status; 3255 3256 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3257 if (status) 3258 return status; 3259 3260 return ice_discover_func_caps(hw, &hw->func_caps); 3261 } 3262 3263 /** 3264 * ice_aq_manage_mac_write - manage MAC address write command 3265 * @hw: pointer to the HW struct 3266 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3267 * @flags: flags to control write behavior 3268 * @cd: pointer to command details structure or NULL 3269 * 3270 * This function is used to write MAC address to the NVM (0x0108). 3271 */ 3272 int 3273 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3274 struct ice_sq_cd *cd) 3275 { 3276 struct ice_aqc_manage_mac_write *cmd; 3277 struct libie_aq_desc desc; 3278 3279 cmd = libie_aq_raw(&desc); 3280 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3281 3282 cmd->flags = flags; 3283 ether_addr_copy(cmd->mac_addr, mac_addr); 3284 3285 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3286 } 3287 3288 /** 3289 * ice_aq_clear_pxe_mode 3290 * @hw: pointer to the HW struct 3291 * 3292 * Tell the firmware that the driver is taking over from PXE (0x0110). 3293 */ 3294 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3295 { 3296 struct ice_aqc_clear_pxe *cmd; 3297 struct libie_aq_desc desc; 3298 3299 cmd = libie_aq_raw(&desc); 3300 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3301 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3302 3303 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3304 } 3305 3306 /** 3307 * ice_clear_pxe_mode - clear pxe operations mode 3308 * @hw: pointer to the HW struct 3309 * 3310 * Make sure all PXE mode settings are cleared, including things 3311 * like descriptor fetch/write-back mode. 3312 */ 3313 void ice_clear_pxe_mode(struct ice_hw *hw) 3314 { 3315 if (ice_check_sq_alive(hw, &hw->adminq)) 3316 ice_aq_clear_pxe_mode(hw); 3317 } 3318 3319 /** 3320 * ice_aq_set_port_params - set physical port parameters. 3321 * @pi: pointer to the port info struct 3322 * @double_vlan: if set double VLAN is enabled 3323 * @cd: pointer to command details structure or NULL 3324 * 3325 * Set Physical port parameters (0x0203) 3326 */ 3327 int 3328 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3329 struct ice_sq_cd *cd) 3330 3331 { 3332 struct ice_aqc_set_port_params *cmd; 3333 struct ice_hw *hw = pi->hw; 3334 struct libie_aq_desc desc; 3335 u16 cmd_flags = 0; 3336 3337 cmd = libie_aq_raw(&desc); 3338 3339 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3340 if (double_vlan) 3341 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3342 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3343 3344 cmd->local_fwd_mode = pi->local_fwd_mode | 3345 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3346 3347 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3348 } 3349 3350 /** 3351 * ice_is_100m_speed_supported 3352 * @hw: pointer to the HW struct 3353 * 3354 * returns true if 100M speeds are supported by the device, 3355 * false otherwise. 3356 */ 3357 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3358 { 3359 switch (hw->device_id) { 3360 case ICE_DEV_ID_E822C_SGMII: 3361 case ICE_DEV_ID_E822L_SGMII: 3362 case ICE_DEV_ID_E823L_1GBE: 3363 case ICE_DEV_ID_E823C_SGMII: 3364 case ICE_DEV_ID_E825C_SGMII: 3365 return true; 3366 default: 3367 return false; 3368 } 3369 } 3370 3371 /** 3372 * ice_get_link_speed_based_on_phy_type - returns link speed 3373 * @phy_type_low: lower part of phy_type 3374 * @phy_type_high: higher part of phy_type 3375 * 3376 * This helper function will convert an entry in PHY type structure 3377 * [phy_type_low, phy_type_high] to its corresponding link speed. 3378 * Note: In the structure of [phy_type_low, phy_type_high], there should 3379 * be one bit set, as this function will convert one PHY type to its 3380 * speed. 3381 * 3382 * Return: 3383 * * PHY speed for recognized PHY type 3384 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3385 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3386 */ 3387 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3388 { 3389 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3390 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3391 3392 switch (phy_type_low) { 3393 case ICE_PHY_TYPE_LOW_100BASE_TX: 3394 case ICE_PHY_TYPE_LOW_100M_SGMII: 3395 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3396 break; 3397 case ICE_PHY_TYPE_LOW_1000BASE_T: 3398 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3399 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3400 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3401 case ICE_PHY_TYPE_LOW_1G_SGMII: 3402 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3403 break; 3404 case ICE_PHY_TYPE_LOW_2500BASE_T: 3405 case ICE_PHY_TYPE_LOW_2500BASE_X: 3406 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3407 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3408 break; 3409 case ICE_PHY_TYPE_LOW_5GBASE_T: 3410 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3411 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3412 break; 3413 case ICE_PHY_TYPE_LOW_10GBASE_T: 3414 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3415 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3416 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3417 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3418 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3419 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3420 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3421 break; 3422 case ICE_PHY_TYPE_LOW_25GBASE_T: 3423 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3424 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3425 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3426 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3427 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3428 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3429 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3430 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3431 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3432 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3433 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3434 break; 3435 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3436 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3437 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3438 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3439 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3440 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3441 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3442 break; 3443 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3444 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3445 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3446 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3447 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3448 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3449 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3450 case ICE_PHY_TYPE_LOW_50G_AUI2: 3451 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3452 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3453 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3454 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3455 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3456 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3457 case ICE_PHY_TYPE_LOW_50G_AUI1: 3458 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3459 break; 3460 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3461 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3462 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3463 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3464 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3465 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3466 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3467 case ICE_PHY_TYPE_LOW_100G_AUI4: 3468 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3469 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3470 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3471 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3472 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3473 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3474 break; 3475 default: 3476 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3477 break; 3478 } 3479 3480 switch (phy_type_high) { 3481 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3482 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3483 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3484 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3485 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3486 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3487 break; 3488 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3489 case ICE_PHY_TYPE_HIGH_200G_SR4: 3490 case ICE_PHY_TYPE_HIGH_200G_FR4: 3491 case ICE_PHY_TYPE_HIGH_200G_LR4: 3492 case ICE_PHY_TYPE_HIGH_200G_DR4: 3493 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3494 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3495 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3496 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3497 break; 3498 default: 3499 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3500 break; 3501 } 3502 3503 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3504 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3505 return ICE_AQ_LINK_SPEED_UNKNOWN; 3506 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3507 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3508 return ICE_AQ_LINK_SPEED_UNKNOWN; 3509 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3510 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3511 return speed_phy_type_low; 3512 else 3513 return speed_phy_type_high; 3514 } 3515 3516 /** 3517 * ice_update_phy_type 3518 * @phy_type_low: pointer to the lower part of phy_type 3519 * @phy_type_high: pointer to the higher part of phy_type 3520 * @link_speeds_bitmap: targeted link speeds bitmap 3521 * 3522 * Note: For the link_speeds_bitmap structure, you can check it at 3523 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3524 * link_speeds_bitmap include multiple speeds. 3525 * 3526 * Each entry in this [phy_type_low, phy_type_high] structure will 3527 * present a certain link speed. This helper function will turn on bits 3528 * in [phy_type_low, phy_type_high] structure based on the value of 3529 * link_speeds_bitmap input parameter. 3530 */ 3531 void 3532 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3533 u16 link_speeds_bitmap) 3534 { 3535 u64 pt_high; 3536 u64 pt_low; 3537 int index; 3538 u16 speed; 3539 3540 /* We first check with low part of phy_type */ 3541 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3542 pt_low = BIT_ULL(index); 3543 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3544 3545 if (link_speeds_bitmap & speed) 3546 *phy_type_low |= BIT_ULL(index); 3547 } 3548 3549 /* We then check with high part of phy_type */ 3550 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3551 pt_high = BIT_ULL(index); 3552 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3553 3554 if (link_speeds_bitmap & speed) 3555 *phy_type_high |= BIT_ULL(index); 3556 } 3557 } 3558 3559 /** 3560 * ice_aq_set_phy_cfg 3561 * @hw: pointer to the HW struct 3562 * @pi: port info structure of the interested logical port 3563 * @cfg: structure with PHY configuration data to be set 3564 * @cd: pointer to command details structure or NULL 3565 * 3566 * Set the various PHY configuration parameters supported on the Port. 3567 * One or more of the Set PHY config parameters may be ignored in an MFP 3568 * mode as the PF may not have the privilege to set some of the PHY Config 3569 * parameters. This status will be indicated by the command response (0x0601). 3570 */ 3571 int 3572 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3573 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3574 { 3575 struct ice_aqc_set_phy_cfg *cmd; 3576 struct libie_aq_desc desc; 3577 int status; 3578 3579 if (!cfg) 3580 return -EINVAL; 3581 3582 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3583 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3584 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3585 cfg->caps); 3586 3587 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3588 } 3589 3590 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3591 cmd = libie_aq_raw(&desc); 3592 cmd->lport_num = pi->lport; 3593 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3594 3595 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3596 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3597 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3598 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3599 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3600 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3601 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3602 cfg->low_power_ctrl_an); 3603 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3604 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3605 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3606 cfg->link_fec_opt); 3607 3608 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3609 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3610 status = 0; 3611 3612 if (!status) 3613 pi->phy.curr_user_phy_cfg = *cfg; 3614 3615 return status; 3616 } 3617 3618 /** 3619 * ice_update_link_info - update status of the HW network link 3620 * @pi: port info structure of the interested logical port 3621 */ 3622 int ice_update_link_info(struct ice_port_info *pi) 3623 { 3624 struct ice_link_status *li; 3625 int status; 3626 3627 if (!pi) 3628 return -EINVAL; 3629 3630 li = &pi->phy.link_info; 3631 3632 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3633 if (status) 3634 return status; 3635 3636 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3637 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3638 3639 pcaps = kzalloc_obj(*pcaps); 3640 if (!pcaps) 3641 return -ENOMEM; 3642 3643 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3644 pcaps, NULL); 3645 } 3646 3647 return status; 3648 } 3649 3650 /** 3651 * ice_aq_get_phy_equalization - function to read serdes equaliser 3652 * value from firmware using admin queue command. 3653 * @hw: pointer to the HW struct 3654 * @data_in: represents the serdes equalization parameter requested 3655 * @op_code: represents the serdes number and flag to represent tx or rx 3656 * @serdes_num: represents the serdes number 3657 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3658 * 3659 * Return: non-zero status on error and 0 on success. 3660 */ 3661 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3662 u8 serdes_num, int *output) 3663 { 3664 struct ice_aqc_dnl_call_command *cmd; 3665 struct ice_aqc_dnl_call buf = {}; 3666 struct libie_aq_desc desc; 3667 int err; 3668 3669 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3670 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3671 cpu_to_le16(op_code | (serdes_num & 0xF)); 3672 cmd = libie_aq_raw(&desc); 3673 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3674 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3675 LIBIE_AQ_FLAG_RD | 3676 LIBIE_AQ_FLAG_SI); 3677 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3678 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3679 3680 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3681 NULL); 3682 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3683 3684 return err; 3685 } 3686 3687 #define FEC_REG_PORT(port) { \ 3688 FEC_CORR_LOW_REG_PORT##port, \ 3689 FEC_CORR_HIGH_REG_PORT##port, \ 3690 FEC_UNCORR_LOW_REG_PORT##port, \ 3691 FEC_UNCORR_HIGH_REG_PORT##port, \ 3692 } 3693 3694 static const u32 fec_reg[][ICE_FEC_MAX] = { 3695 FEC_REG_PORT(0), 3696 FEC_REG_PORT(1), 3697 FEC_REG_PORT(2), 3698 FEC_REG_PORT(3) 3699 }; 3700 3701 /** 3702 * ice_aq_get_fec_stats - reads fec stats from phy 3703 * @hw: pointer to the HW struct 3704 * @pcs_quad: represents pcsquad of user input serdes 3705 * @pcs_port: represents the pcs port number part of above pcs quad 3706 * @fec_type: represents FEC stats type 3707 * @output: pointer to the caller-supplied buffer to return requested fec stats 3708 * 3709 * Return: non-zero status on error and 0 on success. 3710 */ 3711 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3712 enum ice_fec_stats_types fec_type, u32 *output) 3713 { 3714 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3715 struct ice_sbq_msg_input msg = {}; 3716 u32 receiver_id, reg_offset; 3717 int err; 3718 3719 if (pcs_port > 3) 3720 return -EINVAL; 3721 3722 reg_offset = fec_reg[pcs_port][fec_type]; 3723 3724 if (pcs_quad == 0) 3725 receiver_id = FEC_RECEIVER_ID_PCS0; 3726 else if (pcs_quad == 1) 3727 receiver_id = FEC_RECEIVER_ID_PCS1; 3728 else 3729 return -EINVAL; 3730 3731 msg.msg_addr_low = lower_16_bits(reg_offset); 3732 msg.msg_addr_high = receiver_id; 3733 msg.opcode = ice_sbq_msg_rd; 3734 msg.dest_dev = ice_sbq_dev_phy_0; 3735 3736 err = ice_sbq_rw_reg(hw, &msg, flag); 3737 if (err) 3738 return err; 3739 3740 *output = msg.data; 3741 return 0; 3742 } 3743 3744 /** 3745 * ice_cache_phy_user_req 3746 * @pi: port information structure 3747 * @cache_data: PHY logging data 3748 * @cache_mode: PHY logging mode 3749 * 3750 * Log the user request on (FC, FEC, SPEED) for later use. 3751 */ 3752 static void 3753 ice_cache_phy_user_req(struct ice_port_info *pi, 3754 struct ice_phy_cache_mode_data cache_data, 3755 enum ice_phy_cache_mode cache_mode) 3756 { 3757 if (!pi) 3758 return; 3759 3760 switch (cache_mode) { 3761 case ICE_FC_MODE: 3762 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3763 break; 3764 case ICE_SPEED_MODE: 3765 pi->phy.curr_user_speed_req = 3766 cache_data.data.curr_user_speed_req; 3767 break; 3768 case ICE_FEC_MODE: 3769 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3770 break; 3771 default: 3772 break; 3773 } 3774 } 3775 3776 /** 3777 * ice_caps_to_fc_mode 3778 * @caps: PHY capabilities 3779 * 3780 * Convert PHY FC capabilities to ice FC mode 3781 */ 3782 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3783 { 3784 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3785 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3786 return ICE_FC_FULL; 3787 3788 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3789 return ICE_FC_TX_PAUSE; 3790 3791 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3792 return ICE_FC_RX_PAUSE; 3793 3794 return ICE_FC_NONE; 3795 } 3796 3797 /** 3798 * ice_caps_to_fec_mode 3799 * @caps: PHY capabilities 3800 * @fec_options: Link FEC options 3801 * 3802 * Convert PHY FEC capabilities to ice FEC mode 3803 */ 3804 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3805 { 3806 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3807 return ICE_FEC_AUTO; 3808 3809 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3810 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3811 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3812 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3813 return ICE_FEC_BASER; 3814 3815 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3816 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3817 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3818 return ICE_FEC_RS; 3819 3820 return ICE_FEC_NONE; 3821 } 3822 3823 /** 3824 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3825 * @pi: port information structure 3826 * @cfg: PHY configuration data to set FC mode 3827 * @req_mode: FC mode to configure 3828 */ 3829 int 3830 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3831 enum ice_fc_mode req_mode) 3832 { 3833 struct ice_phy_cache_mode_data cache_data; 3834 u8 pause_mask = 0x0; 3835 3836 if (!pi || !cfg) 3837 return -EINVAL; 3838 3839 switch (req_mode) { 3840 case ICE_FC_FULL: 3841 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3842 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3843 break; 3844 case ICE_FC_RX_PAUSE: 3845 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3846 break; 3847 case ICE_FC_TX_PAUSE: 3848 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3849 break; 3850 default: 3851 break; 3852 } 3853 3854 /* clear the old pause settings */ 3855 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3856 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3857 3858 /* set the new capabilities */ 3859 cfg->caps |= pause_mask; 3860 3861 /* Cache user FC request */ 3862 cache_data.data.curr_user_fc_req = req_mode; 3863 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3864 3865 return 0; 3866 } 3867 3868 /** 3869 * ice_set_fc 3870 * @pi: port information structure 3871 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3872 * @ena_auto_link_update: enable automatic link update 3873 * 3874 * Set the requested flow control mode. 3875 */ 3876 int 3877 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3878 { 3879 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3880 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3881 struct ice_hw *hw; 3882 int status; 3883 3884 if (!pi || !aq_failures) 3885 return -EINVAL; 3886 3887 *aq_failures = 0; 3888 hw = pi->hw; 3889 3890 pcaps = kzalloc_obj(*pcaps); 3891 if (!pcaps) 3892 return -ENOMEM; 3893 3894 /* Get the current PHY config */ 3895 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3896 pcaps, NULL); 3897 if (status) { 3898 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3899 goto out; 3900 } 3901 3902 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3903 3904 /* Configure the set PHY data */ 3905 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3906 if (status) 3907 goto out; 3908 3909 /* If the capabilities have changed, then set the new config */ 3910 if (cfg.caps != pcaps->caps) { 3911 int retry_count, retry_max = 10; 3912 3913 /* Auto restart link so settings take effect */ 3914 if (ena_auto_link_update) 3915 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3916 3917 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3918 if (status) { 3919 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3920 goto out; 3921 } 3922 3923 /* Update the link info 3924 * It sometimes takes a really long time for link to 3925 * come back from the atomic reset. Thus, we wait a 3926 * little bit. 3927 */ 3928 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3929 status = ice_update_link_info(pi); 3930 3931 if (!status) 3932 break; 3933 3934 mdelay(100); 3935 } 3936 3937 if (status) 3938 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3939 } 3940 3941 out: 3942 return status; 3943 } 3944 3945 /** 3946 * ice_phy_caps_equals_cfg 3947 * @phy_caps: PHY capabilities 3948 * @phy_cfg: PHY configuration 3949 * 3950 * Helper function to determine if PHY capabilities matches PHY 3951 * configuration 3952 */ 3953 bool 3954 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3955 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3956 { 3957 u8 caps_mask, cfg_mask; 3958 3959 if (!phy_caps || !phy_cfg) 3960 return false; 3961 3962 /* These bits are not common between capabilities and configuration. 3963 * Do not use them to determine equality. 3964 */ 3965 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3966 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3967 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3968 3969 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3970 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3971 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3972 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3973 phy_caps->eee_cap != phy_cfg->eee_cap || 3974 phy_caps->eeer_value != phy_cfg->eeer_value || 3975 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3976 return false; 3977 3978 return true; 3979 } 3980 3981 /** 3982 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3983 * @pi: port information structure 3984 * @caps: PHY ability structure to copy date from 3985 * @cfg: PHY configuration structure to copy data to 3986 * 3987 * Helper function to copy AQC PHY get ability data to PHY set configuration 3988 * data structure 3989 */ 3990 void 3991 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3992 struct ice_aqc_get_phy_caps_data *caps, 3993 struct ice_aqc_set_phy_cfg_data *cfg) 3994 { 3995 if (!pi || !caps || !cfg) 3996 return; 3997 3998 memset(cfg, 0, sizeof(*cfg)); 3999 cfg->phy_type_low = caps->phy_type_low; 4000 cfg->phy_type_high = caps->phy_type_high; 4001 cfg->caps = caps->caps; 4002 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4003 cfg->eee_cap = caps->eee_cap; 4004 cfg->eeer_value = caps->eeer_value; 4005 cfg->link_fec_opt = caps->link_fec_options; 4006 cfg->module_compliance_enforcement = 4007 caps->module_compliance_enforcement; 4008 } 4009 4010 /** 4011 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4012 * @pi: port information structure 4013 * @cfg: PHY configuration data to set FEC mode 4014 * @fec: FEC mode to configure 4015 */ 4016 int 4017 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4018 enum ice_fec_mode fec) 4019 { 4020 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4021 struct ice_hw *hw; 4022 int status; 4023 4024 if (!pi || !cfg) 4025 return -EINVAL; 4026 4027 hw = pi->hw; 4028 4029 pcaps = kzalloc_obj(*pcaps); 4030 if (!pcaps) 4031 return -ENOMEM; 4032 4033 status = ice_aq_get_phy_caps(pi, false, 4034 (ice_fw_supports_report_dflt_cfg(hw) ? 4035 ICE_AQC_REPORT_DFLT_CFG : 4036 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4037 if (status) 4038 goto out; 4039 4040 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4041 cfg->link_fec_opt = pcaps->link_fec_options; 4042 4043 switch (fec) { 4044 case ICE_FEC_BASER: 4045 /* Clear RS bits, and AND BASE-R ability 4046 * bits and OR request bits. 4047 */ 4048 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4049 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4050 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4051 ICE_AQC_PHY_FEC_25G_KR_REQ; 4052 break; 4053 case ICE_FEC_RS: 4054 /* Clear BASE-R bits, and AND RS ability 4055 * bits and OR request bits. 4056 */ 4057 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4058 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4059 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4060 break; 4061 case ICE_FEC_NONE: 4062 /* Clear all FEC option bits. */ 4063 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4064 break; 4065 case ICE_FEC_AUTO: 4066 /* AND auto FEC bit, and all caps bits. */ 4067 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4068 cfg->link_fec_opt |= pcaps->link_fec_options; 4069 break; 4070 default: 4071 status = -EINVAL; 4072 break; 4073 } 4074 4075 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4076 !ice_fw_supports_report_dflt_cfg(hw)) { 4077 struct ice_link_default_override_tlv tlv = { 0 }; 4078 4079 status = ice_get_link_default_override(&tlv, pi); 4080 if (status) 4081 goto out; 4082 4083 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4084 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4085 cfg->link_fec_opt = tlv.fec_options; 4086 } 4087 4088 out: 4089 return status; 4090 } 4091 4092 /** 4093 * ice_get_link_status - get status of the HW network link 4094 * @pi: port information structure 4095 * @link_up: pointer to bool (true/false = linkup/linkdown) 4096 * 4097 * Variable link_up is true if link is up, false if link is down. 4098 * The variable link_up is invalid if status is non zero. As a 4099 * result of this call, link status reporting becomes enabled 4100 */ 4101 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4102 { 4103 struct ice_phy_info *phy_info; 4104 int status = 0; 4105 4106 if (!pi || !link_up) 4107 return -EINVAL; 4108 4109 phy_info = &pi->phy; 4110 4111 if (phy_info->get_link_info) { 4112 status = ice_update_link_info(pi); 4113 4114 if (status) 4115 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4116 status); 4117 } 4118 4119 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4120 4121 return status; 4122 } 4123 4124 /** 4125 * ice_aq_set_link_restart_an 4126 * @pi: pointer to the port information structure 4127 * @ena_link: if true: enable link, if false: disable link 4128 * @cd: pointer to command details structure or NULL 4129 * 4130 * Sets up the link and restarts the Auto-Negotiation over the link. 4131 */ 4132 int 4133 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4134 struct ice_sq_cd *cd) 4135 { 4136 struct ice_aqc_restart_an *cmd; 4137 struct libie_aq_desc desc; 4138 4139 cmd = libie_aq_raw(&desc); 4140 4141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4142 4143 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4144 cmd->lport_num = pi->lport; 4145 if (ena_link) 4146 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4147 else 4148 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4149 4150 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4151 } 4152 4153 /** 4154 * ice_aq_set_event_mask 4155 * @hw: pointer to the HW struct 4156 * @port_num: port number of the physical function 4157 * @mask: event mask to be set 4158 * @cd: pointer to command details structure or NULL 4159 * 4160 * Set event mask (0x0613) 4161 */ 4162 int 4163 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4164 struct ice_sq_cd *cd) 4165 { 4166 struct ice_aqc_set_event_mask *cmd; 4167 struct libie_aq_desc desc; 4168 4169 cmd = libie_aq_raw(&desc); 4170 4171 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4172 4173 cmd->lport_num = port_num; 4174 4175 cmd->event_mask = cpu_to_le16(mask); 4176 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4177 } 4178 4179 /** 4180 * ice_aq_set_mac_loopback 4181 * @hw: pointer to the HW struct 4182 * @ena_lpbk: Enable or Disable loopback 4183 * @cd: pointer to command details structure or NULL 4184 * 4185 * Enable/disable loopback on a given port 4186 */ 4187 int 4188 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4189 { 4190 struct ice_aqc_set_mac_lb *cmd; 4191 struct libie_aq_desc desc; 4192 4193 cmd = libie_aq_raw(&desc); 4194 4195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4196 if (ena_lpbk) 4197 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4198 4199 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4200 } 4201 4202 /** 4203 * ice_aq_set_port_id_led 4204 * @pi: pointer to the port information 4205 * @is_orig_mode: is this LED set to original mode (by the net-list) 4206 * @cd: pointer to command details structure or NULL 4207 * 4208 * Set LED value for the given port (0x06e9) 4209 */ 4210 int 4211 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4212 struct ice_sq_cd *cd) 4213 { 4214 struct ice_aqc_set_port_id_led *cmd; 4215 struct ice_hw *hw = pi->hw; 4216 struct libie_aq_desc desc; 4217 4218 cmd = libie_aq_raw(&desc); 4219 4220 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4221 4222 if (is_orig_mode) 4223 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4224 else 4225 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4226 4227 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4228 } 4229 4230 /** 4231 * ice_aq_get_port_options 4232 * @hw: pointer to the HW struct 4233 * @options: buffer for the resultant port options 4234 * @option_count: input - size of the buffer in port options structures, 4235 * output - number of returned port options 4236 * @lport: logical port to call the command with (optional) 4237 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4238 * when PF owns more than 1 port it must be true 4239 * @active_option_idx: index of active port option in returned buffer 4240 * @active_option_valid: active option in returned buffer is valid 4241 * @pending_option_idx: index of pending port option in returned buffer 4242 * @pending_option_valid: pending option in returned buffer is valid 4243 * 4244 * Calls Get Port Options AQC (0x06ea) and verifies result. 4245 */ 4246 int 4247 ice_aq_get_port_options(struct ice_hw *hw, 4248 struct ice_aqc_get_port_options_elem *options, 4249 u8 *option_count, u8 lport, bool lport_valid, 4250 u8 *active_option_idx, bool *active_option_valid, 4251 u8 *pending_option_idx, bool *pending_option_valid) 4252 { 4253 struct ice_aqc_get_port_options *cmd; 4254 struct libie_aq_desc desc; 4255 int status; 4256 u8 i; 4257 4258 /* options buffer shall be able to hold max returned options */ 4259 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4260 return -EINVAL; 4261 4262 cmd = libie_aq_raw(&desc); 4263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4264 4265 if (lport_valid) 4266 cmd->lport_num = lport; 4267 cmd->lport_num_valid = lport_valid; 4268 4269 status = ice_aq_send_cmd(hw, &desc, options, 4270 *option_count * sizeof(*options), NULL); 4271 if (status) 4272 return status; 4273 4274 /* verify direct FW response & set output parameters */ 4275 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4276 cmd->port_options_count); 4277 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4278 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4279 cmd->port_options); 4280 if (*active_option_valid) { 4281 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4282 cmd->port_options); 4283 if (*active_option_idx > (*option_count - 1)) 4284 return -EIO; 4285 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4286 *active_option_idx); 4287 } 4288 4289 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4290 cmd->pending_port_option_status); 4291 if (*pending_option_valid) { 4292 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4293 cmd->pending_port_option_status); 4294 if (*pending_option_idx > (*option_count - 1)) 4295 return -EIO; 4296 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4297 *pending_option_idx); 4298 } 4299 4300 /* mask output options fields */ 4301 for (i = 0; i < *option_count; i++) { 4302 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4303 options[i].pmd); 4304 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4305 options[i].max_lane_speed); 4306 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4307 options[i].pmd, options[i].max_lane_speed); 4308 } 4309 4310 return 0; 4311 } 4312 4313 /** 4314 * ice_aq_set_port_option 4315 * @hw: pointer to the HW struct 4316 * @lport: logical port to call the command with 4317 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4318 * when PF owns more than 1 port it must be true 4319 * @new_option: new port option to be written 4320 * 4321 * Calls Set Port Options AQC (0x06eb). 4322 */ 4323 int 4324 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4325 u8 new_option) 4326 { 4327 struct ice_aqc_set_port_option *cmd; 4328 struct libie_aq_desc desc; 4329 4330 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4331 return -EINVAL; 4332 4333 cmd = libie_aq_raw(&desc); 4334 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4335 4336 if (lport_valid) 4337 cmd->lport_num = lport; 4338 4339 cmd->lport_num_valid = lport_valid; 4340 cmd->selected_port_option = new_option; 4341 4342 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4343 } 4344 4345 /** 4346 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4347 * @hw: pointer to the hw struct 4348 * 4349 * Return: PHY lane number on success, negative error code otherwise. 4350 */ 4351 int ice_get_phy_lane_number(struct ice_hw *hw) 4352 { 4353 struct ice_aqc_get_port_options_elem *options; 4354 unsigned int lport = 0; 4355 unsigned int lane; 4356 int err; 4357 4358 /* E82X does not have sequential IDs, lane number is PF ID. 4359 * For E825 device, the exception is the variant with external 4360 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4361 * mapping. 4362 */ 4363 if (hw->mac_type == ICE_MAC_GENERIC || 4364 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4365 return hw->pf_id; 4366 4367 options = kzalloc_objs(*options, ICE_AQC_PORT_OPT_MAX); 4368 if (!options) 4369 return -ENOMEM; 4370 4371 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4372 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4373 u8 speed, active_idx, pending_idx; 4374 bool active_valid, pending_valid; 4375 4376 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4377 true, &active_idx, &active_valid, 4378 &pending_idx, &pending_valid); 4379 if (err) 4380 goto err; 4381 4382 if (!active_valid) 4383 continue; 4384 4385 speed = options[active_idx].max_lane_speed; 4386 /* If we don't get speed for this lane, it's unoccupied */ 4387 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4388 continue; 4389 4390 if (hw->pf_id == lport) { 4391 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4392 ice_is_dual(hw) && !ice_is_primary(hw)) 4393 lane += ICE_PORTS_PER_QUAD; 4394 kfree(options); 4395 return lane; 4396 } 4397 lport++; 4398 } 4399 4400 /* PHY lane not found */ 4401 err = -ENXIO; 4402 err: 4403 kfree(options); 4404 return err; 4405 } 4406 4407 /** 4408 * ice_aq_sff_eeprom 4409 * @hw: pointer to the HW struct 4410 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4411 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4412 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4413 * @page: QSFP page 4414 * @set_page: set or ignore the page 4415 * @data: pointer to data buffer to be read/written to the I2C device. 4416 * @length: 1-16 for read, 1 for write. 4417 * @write: 0 read, 1 for write. 4418 * @cd: pointer to command details structure or NULL 4419 * 4420 * Read/Write SFF EEPROM (0x06EE) 4421 */ 4422 int 4423 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4424 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4425 bool write, struct ice_sq_cd *cd) 4426 { 4427 struct ice_aqc_sff_eeprom *cmd; 4428 struct libie_aq_desc desc; 4429 u16 i2c_bus_addr; 4430 int status; 4431 4432 if (!data || (mem_addr & 0xff00)) 4433 return -EINVAL; 4434 4435 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4436 cmd = libie_aq_raw(&desc); 4437 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4438 cmd->lport_num = (u8)(lport & 0xff); 4439 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4440 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4441 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4442 if (write) 4443 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4444 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4445 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4446 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4447 4448 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4449 return status; 4450 } 4451 4452 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4453 { 4454 switch (type) { 4455 case ICE_LUT_VSI: 4456 return ICE_LUT_VSI_SIZE; 4457 case ICE_LUT_GLOBAL: 4458 return ICE_LUT_GLOBAL_SIZE; 4459 case ICE_LUT_PF: 4460 return ICE_LUT_PF_SIZE; 4461 } 4462 WARN_ONCE(1, "incorrect type passed"); 4463 return ICE_LUT_VSI_SIZE; 4464 } 4465 4466 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4467 { 4468 switch (size) { 4469 case ICE_LUT_VSI_SIZE: 4470 return ICE_AQC_LUT_SIZE_SMALL; 4471 case ICE_LUT_GLOBAL_SIZE: 4472 return ICE_AQC_LUT_SIZE_512; 4473 case ICE_LUT_PF_SIZE: 4474 return ICE_AQC_LUT_SIZE_2K; 4475 } 4476 WARN_ONCE(1, "incorrect size passed"); 4477 return 0; 4478 } 4479 4480 /** 4481 * __ice_aq_get_set_rss_lut 4482 * @hw: pointer to the hardware structure 4483 * @params: RSS LUT parameters 4484 * @set: set true to set the table, false to get the table 4485 * 4486 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4487 */ 4488 static int 4489 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4490 struct ice_aq_get_set_rss_lut_params *params, bool set) 4491 { 4492 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4493 enum ice_lut_type lut_type = params->lut_type; 4494 struct ice_aqc_get_set_rss_lut *desc_params; 4495 enum ice_aqc_lut_flags flags; 4496 enum ice_lut_size lut_size; 4497 struct libie_aq_desc desc; 4498 u8 *lut = params->lut; 4499 4500 4501 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4502 return -EINVAL; 4503 4504 lut_size = ice_lut_type_to_size(lut_type); 4505 if (lut_size > params->lut_size) 4506 return -EINVAL; 4507 else if (set && lut_size != params->lut_size) 4508 return -EINVAL; 4509 4510 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4511 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4512 if (set) 4513 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4514 4515 desc_params = libie_aq_raw(&desc); 4516 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4517 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4518 4519 if (lut_type == ICE_LUT_GLOBAL) 4520 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4521 params->global_lut_id); 4522 4523 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4524 desc_params->flags = cpu_to_le16(flags); 4525 4526 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4527 } 4528 4529 /** 4530 * ice_aq_get_rss_lut 4531 * @hw: pointer to the hardware structure 4532 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4533 * 4534 * get the RSS lookup table, PF or VSI type 4535 */ 4536 int 4537 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4538 { 4539 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4540 } 4541 4542 /** 4543 * ice_aq_set_rss_lut 4544 * @hw: pointer to the hardware structure 4545 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4546 * 4547 * set the RSS lookup table, PF or VSI type 4548 */ 4549 int 4550 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4551 { 4552 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4553 } 4554 4555 /** 4556 * __ice_aq_get_set_rss_key 4557 * @hw: pointer to the HW struct 4558 * @vsi_id: VSI FW index 4559 * @key: pointer to key info struct 4560 * @set: set true to set the key, false to get the key 4561 * 4562 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4563 */ 4564 static int 4565 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4566 struct ice_aqc_get_set_rss_keys *key, bool set) 4567 { 4568 struct ice_aqc_get_set_rss_key *desc_params; 4569 u16 key_size = sizeof(*key); 4570 struct libie_aq_desc desc; 4571 4572 if (set) { 4573 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4574 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4575 } else { 4576 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4577 } 4578 4579 desc_params = libie_aq_raw(&desc); 4580 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4581 4582 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4583 } 4584 4585 /** 4586 * ice_aq_get_rss_key 4587 * @hw: pointer to the HW struct 4588 * @vsi_handle: software VSI handle 4589 * @key: pointer to key info struct 4590 * 4591 * get the RSS key per VSI 4592 */ 4593 int 4594 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4595 struct ice_aqc_get_set_rss_keys *key) 4596 { 4597 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4598 return -EINVAL; 4599 4600 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4601 key, false); 4602 } 4603 4604 /** 4605 * ice_aq_set_rss_key 4606 * @hw: pointer to the HW struct 4607 * @vsi_handle: software VSI handle 4608 * @keys: pointer to key info struct 4609 * 4610 * set the RSS key per VSI 4611 */ 4612 int 4613 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4614 struct ice_aqc_get_set_rss_keys *keys) 4615 { 4616 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4617 return -EINVAL; 4618 4619 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4620 keys, true); 4621 } 4622 4623 /** 4624 * ice_aq_add_lan_txq 4625 * @hw: pointer to the hardware structure 4626 * @num_qgrps: Number of added queue groups 4627 * @qg_list: list of queue groups to be added 4628 * @buf_size: size of buffer for indirect command 4629 * @cd: pointer to command details structure or NULL 4630 * 4631 * Add Tx LAN queue (0x0C30) 4632 * 4633 * NOTE: 4634 * Prior to calling add Tx LAN queue: 4635 * Initialize the following as part of the Tx queue context: 4636 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4637 * Cache profile and Packet shaper profile. 4638 * 4639 * After add Tx LAN queue AQ command is completed: 4640 * Interrupts should be associated with specific queues, 4641 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4642 * flow. 4643 */ 4644 static int 4645 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4646 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4647 struct ice_sq_cd *cd) 4648 { 4649 struct ice_aqc_add_tx_qgrp *list; 4650 struct ice_aqc_add_txqs *cmd; 4651 struct libie_aq_desc desc; 4652 u16 i, sum_size = 0; 4653 4654 cmd = libie_aq_raw(&desc); 4655 4656 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4657 4658 if (!qg_list) 4659 return -EINVAL; 4660 4661 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4662 return -EINVAL; 4663 4664 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4665 sum_size += struct_size(list, txqs, list->num_txqs); 4666 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4667 list->num_txqs); 4668 } 4669 4670 if (buf_size != sum_size) 4671 return -EINVAL; 4672 4673 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4674 4675 cmd->num_qgrps = num_qgrps; 4676 4677 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4678 } 4679 4680 /** 4681 * ice_aq_dis_lan_txq 4682 * @hw: pointer to the hardware structure 4683 * @num_qgrps: number of groups in the list 4684 * @qg_list: the list of groups to disable 4685 * @buf_size: the total size of the qg_list buffer in bytes 4686 * @rst_src: if called due to reset, specifies the reset source 4687 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4688 * @cd: pointer to command details structure or NULL 4689 * 4690 * Disable LAN Tx queue (0x0C31) 4691 */ 4692 static int 4693 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4694 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4695 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4696 struct ice_sq_cd *cd) 4697 { 4698 struct ice_aqc_dis_txq_item *item; 4699 struct ice_aqc_dis_txqs *cmd; 4700 struct libie_aq_desc desc; 4701 u16 vmvf_and_timeout; 4702 u16 i, sz = 0; 4703 int status; 4704 4705 cmd = libie_aq_raw(&desc); 4706 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4707 4708 /* qg_list can be NULL only in VM/VF reset flow */ 4709 if (!qg_list && !rst_src) 4710 return -EINVAL; 4711 4712 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4713 return -EINVAL; 4714 4715 cmd->num_entries = num_qgrps; 4716 4717 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4718 4719 switch (rst_src) { 4720 case ICE_VM_RESET: 4721 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4722 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4723 break; 4724 case ICE_VF_RESET: 4725 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4726 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4727 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4728 ICE_AQC_Q_DIS_VMVF_NUM_M; 4729 break; 4730 case ICE_NO_RESET: 4731 default: 4732 break; 4733 } 4734 4735 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4736 4737 /* flush pipe on time out */ 4738 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4739 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4740 if (!qg_list) 4741 goto do_aq; 4742 4743 /* set RD bit to indicate that command buffer is provided by the driver 4744 * and it needs to be read by the firmware 4745 */ 4746 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4747 4748 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4749 u16 item_size = struct_size(item, q_id, item->num_qs); 4750 4751 /* If the num of queues is even, add 2 bytes of padding */ 4752 if ((item->num_qs % 2) == 0) 4753 item_size += 2; 4754 4755 sz += item_size; 4756 4757 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4758 } 4759 4760 if (buf_size != sz) 4761 return -EINVAL; 4762 4763 do_aq: 4764 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4765 if (status) { 4766 if (!qg_list) 4767 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4768 vmvf_num, hw->adminq.sq_last_status); 4769 else 4770 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4771 le16_to_cpu(qg_list[0].q_id[0]), 4772 hw->adminq.sq_last_status); 4773 } 4774 return status; 4775 } 4776 4777 /** 4778 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4779 * @hw: pointer to the hardware structure 4780 * @buf: buffer for command 4781 * @buf_size: size of buffer in bytes 4782 * @num_qs: number of queues being configured 4783 * @oldport: origination lport 4784 * @newport: destination lport 4785 * @mode: cmd_type for move to use 4786 * @cd: pointer to command details structure or NULL 4787 * 4788 * Move/Configure LAN Tx queue (0x0C32) 4789 * 4790 * Return: Zero on success, associated error code on failure. 4791 */ 4792 int 4793 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4794 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4795 u8 mode, struct ice_sq_cd *cd) 4796 { 4797 struct ice_aqc_cfg_txqs *cmd; 4798 struct libie_aq_desc desc; 4799 int status; 4800 4801 cmd = libie_aq_raw(&desc); 4802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4803 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4804 4805 if (!buf) 4806 return -EINVAL; 4807 4808 cmd->cmd_type = mode; 4809 cmd->num_qs = num_qs; 4810 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4811 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4812 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4813 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4814 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4815 cmd->blocked_cgds = 0; 4816 4817 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4818 if (status) 4819 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4820 hw->adminq.sq_last_status); 4821 return status; 4822 } 4823 4824 /** 4825 * ice_aq_add_rdma_qsets 4826 * @hw: pointer to the hardware structure 4827 * @num_qset_grps: Number of RDMA Qset groups 4828 * @qset_list: list of Qset groups to be added 4829 * @buf_size: size of buffer for indirect command 4830 * @cd: pointer to command details structure or NULL 4831 * 4832 * Add Tx RDMA Qsets (0x0C33) 4833 */ 4834 static int 4835 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4836 struct ice_aqc_add_rdma_qset_data *qset_list, 4837 u16 buf_size, struct ice_sq_cd *cd) 4838 { 4839 struct ice_aqc_add_rdma_qset_data *list; 4840 struct ice_aqc_add_rdma_qset *cmd; 4841 struct libie_aq_desc desc; 4842 u16 i, sum_size = 0; 4843 4844 cmd = libie_aq_raw(&desc); 4845 4846 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4847 4848 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4849 return -EINVAL; 4850 4851 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4852 u16 num_qsets = le16_to_cpu(list->num_qsets); 4853 4854 sum_size += struct_size(list, rdma_qsets, num_qsets); 4855 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4856 num_qsets); 4857 } 4858 4859 if (buf_size != sum_size) 4860 return -EINVAL; 4861 4862 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4863 4864 cmd->num_qset_grps = num_qset_grps; 4865 4866 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4867 } 4868 4869 /** 4870 * ice_aq_set_txtimeq - set Tx time queues 4871 * @hw: pointer to the hardware structure 4872 * @txtimeq: first Tx time queue id to configure 4873 * @q_count: number of queues to configure 4874 * @txtime_qg: queue group to be set 4875 * @buf_size: size of buffer for indirect command 4876 * @cd: pointer to command details structure or NULL 4877 * 4878 * Set Tx Time queue (0x0C35) 4879 * Return: 0 on success or negative value on failure. 4880 */ 4881 int 4882 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4883 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4884 struct ice_sq_cd *cd) 4885 { 4886 struct ice_aqc_set_txtimeqs *cmd; 4887 struct libie_aq_desc desc; 4888 u16 size; 4889 4890 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4891 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4892 return -EINVAL; 4893 4894 size = struct_size(txtime_qg, txtimeqs, q_count); 4895 if (buf_size != size) 4896 return -EINVAL; 4897 4898 cmd = libie_aq_raw(&desc); 4899 4900 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4901 4902 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4903 4904 cmd->q_id = cpu_to_le16(txtimeq); 4905 cmd->q_amount = cpu_to_le16(q_count); 4906 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4907 } 4908 4909 /* End of FW Admin Queue command wrappers */ 4910 4911 /** 4912 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4913 * @hw: pointer to the HW struct 4914 * @vsi_handle: software VSI handle 4915 * @tc: TC number 4916 * @q_handle: software queue handle 4917 */ 4918 struct ice_q_ctx * 4919 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4920 { 4921 struct ice_vsi_ctx *vsi; 4922 struct ice_q_ctx *q_ctx; 4923 4924 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4925 if (!vsi) 4926 return NULL; 4927 if (q_handle >= vsi->num_lan_q_entries[tc]) 4928 return NULL; 4929 if (!vsi->lan_q_ctx[tc]) 4930 return NULL; 4931 q_ctx = vsi->lan_q_ctx[tc]; 4932 return &q_ctx[q_handle]; 4933 } 4934 4935 /** 4936 * ice_ena_vsi_txq 4937 * @pi: port information structure 4938 * @vsi_handle: software VSI handle 4939 * @tc: TC number 4940 * @q_handle: software queue handle 4941 * @num_qgrps: Number of added queue groups 4942 * @buf: list of queue groups to be added 4943 * @buf_size: size of buffer for indirect command 4944 * @cd: pointer to command details structure or NULL 4945 * 4946 * This function adds one LAN queue 4947 */ 4948 int 4949 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4950 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4951 struct ice_sq_cd *cd) 4952 { 4953 struct ice_aqc_txsched_elem_data node = { 0 }; 4954 struct ice_sched_node *parent; 4955 struct ice_q_ctx *q_ctx; 4956 struct ice_hw *hw; 4957 int status; 4958 4959 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4960 return -EIO; 4961 4962 if (num_qgrps > 1 || buf->num_txqs > 1) 4963 return -ENOSPC; 4964 4965 hw = pi->hw; 4966 4967 if (!ice_is_vsi_valid(hw, vsi_handle)) 4968 return -EINVAL; 4969 4970 mutex_lock(&pi->sched_lock); 4971 4972 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4973 if (!q_ctx) { 4974 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4975 q_handle); 4976 status = -EINVAL; 4977 goto ena_txq_exit; 4978 } 4979 4980 /* find a parent node */ 4981 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4982 ICE_SCHED_NODE_OWNER_LAN); 4983 if (!parent) { 4984 status = -EINVAL; 4985 goto ena_txq_exit; 4986 } 4987 4988 buf->parent_teid = parent->info.node_teid; 4989 node.parent_teid = parent->info.node_teid; 4990 /* Mark that the values in the "generic" section as valid. The default 4991 * value in the "generic" section is zero. This means that : 4992 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4993 * - 0 priority among siblings, indicated by Bit 1-3. 4994 * - WFQ, indicated by Bit 4. 4995 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4996 * Bit 5-6. 4997 * - Bit 7 is reserved. 4998 * Without setting the generic section as valid in valid_sections, the 4999 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5000 */ 5001 buf->txqs[0].info.valid_sections = 5002 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5003 ICE_AQC_ELEM_VALID_EIR; 5004 buf->txqs[0].info.generic = 0; 5005 buf->txqs[0].info.cir_bw.bw_profile_idx = 5006 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5007 buf->txqs[0].info.cir_bw.bw_alloc = 5008 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5009 buf->txqs[0].info.eir_bw.bw_profile_idx = 5010 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5011 buf->txqs[0].info.eir_bw.bw_alloc = 5012 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5013 5014 /* add the LAN queue */ 5015 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5016 if (status) { 5017 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5018 le16_to_cpu(buf->txqs[0].txq_id), 5019 hw->adminq.sq_last_status); 5020 goto ena_txq_exit; 5021 } 5022 5023 node.node_teid = buf->txqs[0].q_teid; 5024 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5025 q_ctx->q_handle = q_handle; 5026 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5027 5028 /* add a leaf node into scheduler tree queue layer */ 5029 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5030 if (!status) 5031 status = ice_sched_replay_q_bw(pi, q_ctx); 5032 5033 ena_txq_exit: 5034 mutex_unlock(&pi->sched_lock); 5035 return status; 5036 } 5037 5038 /** 5039 * ice_dis_vsi_txq 5040 * @pi: port information structure 5041 * @vsi_handle: software VSI handle 5042 * @tc: TC number 5043 * @num_queues: number of queues 5044 * @q_handles: pointer to software queue handle array 5045 * @q_ids: pointer to the q_id array 5046 * @q_teids: pointer to queue node teids 5047 * @rst_src: if called due to reset, specifies the reset source 5048 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5049 * @cd: pointer to command details structure or NULL 5050 * 5051 * This function removes queues and their corresponding nodes in SW DB 5052 */ 5053 int 5054 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5055 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5056 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5057 struct ice_sq_cd *cd) 5058 { 5059 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5060 u16 i, buf_size = __struct_size(qg_list); 5061 struct ice_q_ctx *q_ctx; 5062 int status = -ENOENT; 5063 struct ice_hw *hw; 5064 5065 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5066 return -EIO; 5067 5068 hw = pi->hw; 5069 5070 if (!num_queues) { 5071 /* if queue is disabled already yet the disable queue command 5072 * has to be sent to complete the VF reset, then call 5073 * ice_aq_dis_lan_txq without any queue information 5074 */ 5075 if (rst_src) 5076 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5077 vmvf_num, NULL); 5078 return -EIO; 5079 } 5080 5081 mutex_lock(&pi->sched_lock); 5082 5083 for (i = 0; i < num_queues; i++) { 5084 struct ice_sched_node *node; 5085 5086 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5087 if (!node) 5088 continue; 5089 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5090 if (!q_ctx) { 5091 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5092 q_handles[i]); 5093 continue; 5094 } 5095 if (q_ctx->q_handle != q_handles[i]) { 5096 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5097 q_ctx->q_handle, q_handles[i]); 5098 continue; 5099 } 5100 qg_list->parent_teid = node->info.parent_teid; 5101 qg_list->num_qs = 1; 5102 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5103 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5104 vmvf_num, cd); 5105 5106 if (status) 5107 break; 5108 ice_free_sched_node(pi, node); 5109 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5110 q_ctx->q_teid = ICE_INVAL_TEID; 5111 } 5112 mutex_unlock(&pi->sched_lock); 5113 return status; 5114 } 5115 5116 /** 5117 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5118 * @pi: port information structure 5119 * @vsi_handle: software VSI handle 5120 * @tc_bitmap: TC bitmap 5121 * @maxqs: max queues array per TC 5122 * @owner: LAN or RDMA 5123 * 5124 * This function adds/updates the VSI queues per TC. 5125 */ 5126 static int 5127 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5128 u16 *maxqs, u8 owner) 5129 { 5130 int status = 0; 5131 u8 i; 5132 5133 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5134 return -EIO; 5135 5136 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5137 return -EINVAL; 5138 5139 mutex_lock(&pi->sched_lock); 5140 5141 ice_for_each_traffic_class(i) { 5142 /* configuration is possible only if TC node is present */ 5143 if (!ice_sched_get_tc_node(pi, i)) 5144 continue; 5145 5146 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5147 ice_is_tc_ena(tc_bitmap, i)); 5148 if (status) 5149 break; 5150 } 5151 5152 mutex_unlock(&pi->sched_lock); 5153 return status; 5154 } 5155 5156 /** 5157 * ice_cfg_vsi_lan - configure VSI LAN queues 5158 * @pi: port information structure 5159 * @vsi_handle: software VSI handle 5160 * @tc_bitmap: TC bitmap 5161 * @max_lanqs: max LAN queues array per TC 5162 * 5163 * This function adds/updates the VSI LAN queues per TC. 5164 */ 5165 int 5166 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5167 u16 *max_lanqs) 5168 { 5169 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5170 ICE_SCHED_NODE_OWNER_LAN); 5171 } 5172 5173 /** 5174 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5175 * @pi: port information structure 5176 * @vsi_handle: software VSI handle 5177 * @tc_bitmap: TC bitmap 5178 * @max_rdmaqs: max RDMA queues array per TC 5179 * 5180 * This function adds/updates the VSI RDMA queues per TC. 5181 */ 5182 int 5183 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5184 u16 *max_rdmaqs) 5185 { 5186 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5187 ICE_SCHED_NODE_OWNER_RDMA); 5188 } 5189 5190 /** 5191 * ice_ena_vsi_rdma_qset 5192 * @pi: port information structure 5193 * @vsi_handle: software VSI handle 5194 * @tc: TC number 5195 * @rdma_qset: pointer to RDMA Qset 5196 * @num_qsets: number of RDMA Qsets 5197 * @qset_teid: pointer to Qset node TEIDs 5198 * 5199 * This function adds RDMA Qset 5200 */ 5201 int 5202 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5203 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5204 { 5205 struct ice_aqc_txsched_elem_data node = { 0 }; 5206 struct ice_aqc_add_rdma_qset_data *buf; 5207 struct ice_sched_node *parent; 5208 struct ice_hw *hw; 5209 u16 i, buf_size; 5210 int ret; 5211 5212 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5213 return -EIO; 5214 hw = pi->hw; 5215 5216 if (!ice_is_vsi_valid(hw, vsi_handle)) 5217 return -EINVAL; 5218 5219 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5220 buf = kzalloc(buf_size, GFP_KERNEL); 5221 if (!buf) 5222 return -ENOMEM; 5223 mutex_lock(&pi->sched_lock); 5224 5225 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5226 ICE_SCHED_NODE_OWNER_RDMA); 5227 if (!parent) { 5228 ret = -EINVAL; 5229 goto rdma_error_exit; 5230 } 5231 buf->parent_teid = parent->info.node_teid; 5232 node.parent_teid = parent->info.node_teid; 5233 5234 buf->num_qsets = cpu_to_le16(num_qsets); 5235 for (i = 0; i < num_qsets; i++) { 5236 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5237 buf->rdma_qsets[i].info.valid_sections = 5238 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5239 ICE_AQC_ELEM_VALID_EIR; 5240 buf->rdma_qsets[i].info.generic = 0; 5241 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5242 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5243 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5244 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5245 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5246 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5247 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5248 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5249 } 5250 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5251 if (ret) { 5252 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5253 goto rdma_error_exit; 5254 } 5255 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5256 for (i = 0; i < num_qsets; i++) { 5257 node.node_teid = buf->rdma_qsets[i].qset_teid; 5258 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5259 &node, NULL); 5260 if (ret) 5261 break; 5262 qset_teid[i] = le32_to_cpu(node.node_teid); 5263 } 5264 rdma_error_exit: 5265 mutex_unlock(&pi->sched_lock); 5266 kfree(buf); 5267 return ret; 5268 } 5269 5270 /** 5271 * ice_dis_vsi_rdma_qset - free RDMA resources 5272 * @pi: port_info struct 5273 * @count: number of RDMA Qsets to free 5274 * @qset_teid: TEID of Qset node 5275 * @q_id: list of queue IDs being disabled 5276 */ 5277 int 5278 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5279 u16 *q_id) 5280 { 5281 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5282 u16 qg_size = __struct_size(qg_list); 5283 struct ice_hw *hw; 5284 int status = 0; 5285 int i; 5286 5287 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5288 return -EIO; 5289 5290 hw = pi->hw; 5291 5292 mutex_lock(&pi->sched_lock); 5293 5294 for (i = 0; i < count; i++) { 5295 struct ice_sched_node *node; 5296 5297 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5298 if (!node) 5299 continue; 5300 5301 qg_list->parent_teid = node->info.parent_teid; 5302 qg_list->num_qs = 1; 5303 qg_list->q_id[0] = 5304 cpu_to_le16(q_id[i] | 5305 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5306 5307 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5308 ICE_NO_RESET, 0, NULL); 5309 if (status) 5310 break; 5311 5312 ice_free_sched_node(pi, node); 5313 } 5314 5315 mutex_unlock(&pi->sched_lock); 5316 return status; 5317 } 5318 5319 /** 5320 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5321 * @hw: pointer to the HW struct 5322 * @dpll_idx: index of dpll to be measured 5323 * @meas: array to be filled with results 5324 * @meas_num: max number of results array can hold 5325 * 5326 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5327 * pins on given dpll. 5328 * 5329 * Return: 0 on success or negative value on failure. 5330 */ 5331 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5332 struct ice_cgu_input_measure *meas, 5333 u16 meas_num) 5334 { 5335 struct ice_aqc_get_cgu_input_measure *cmd; 5336 struct libie_aq_desc desc; 5337 5338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5339 cmd = libie_aq_raw(&desc); 5340 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5341 5342 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5343 } 5344 5345 /** 5346 * ice_aq_get_cgu_abilities - get cgu abilities 5347 * @hw: pointer to the HW struct 5348 * @abilities: CGU abilities 5349 * 5350 * Get CGU abilities (0x0C61) 5351 * Return: 0 on success or negative value on failure. 5352 */ 5353 int 5354 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5355 struct ice_aqc_get_cgu_abilities *abilities) 5356 { 5357 struct libie_aq_desc desc; 5358 5359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5360 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5361 } 5362 5363 /** 5364 * ice_aq_set_input_pin_cfg - set input pin config 5365 * @hw: pointer to the HW struct 5366 * @input_idx: Input index 5367 * @flags1: Input flags 5368 * @flags2: Input flags 5369 * @freq: Frequency in Hz 5370 * @phase_delay: Delay in ps 5371 * 5372 * Set CGU input config (0x0C62) 5373 * Return: 0 on success or negative value on failure. 5374 */ 5375 int 5376 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5377 u32 freq, s32 phase_delay) 5378 { 5379 struct ice_aqc_set_cgu_input_config *cmd; 5380 struct libie_aq_desc desc; 5381 5382 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5383 cmd = libie_aq_raw(&desc); 5384 cmd->input_idx = input_idx; 5385 cmd->flags1 = flags1; 5386 cmd->flags2 = flags2; 5387 cmd->freq = cpu_to_le32(freq); 5388 cmd->phase_delay = cpu_to_le32(phase_delay); 5389 5390 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5391 } 5392 5393 /** 5394 * ice_aq_get_input_pin_cfg - get input pin config 5395 * @hw: pointer to the HW struct 5396 * @input_idx: Input index 5397 * @status: Pin status 5398 * @type: Pin type 5399 * @flags1: Input flags 5400 * @flags2: Input flags 5401 * @freq: Frequency in Hz 5402 * @phase_delay: Delay in ps 5403 * 5404 * Get CGU input config (0x0C63) 5405 * Return: 0 on success or negative value on failure. 5406 */ 5407 int 5408 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5409 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5410 { 5411 struct ice_aqc_get_cgu_input_config *cmd; 5412 struct libie_aq_desc desc; 5413 int ret; 5414 5415 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5416 cmd = libie_aq_raw(&desc); 5417 cmd->input_idx = input_idx; 5418 5419 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5420 if (!ret) { 5421 if (status) 5422 *status = cmd->status; 5423 if (type) 5424 *type = cmd->type; 5425 if (flags1) 5426 *flags1 = cmd->flags1; 5427 if (flags2) 5428 *flags2 = cmd->flags2; 5429 if (freq) 5430 *freq = le32_to_cpu(cmd->freq); 5431 if (phase_delay) 5432 *phase_delay = le32_to_cpu(cmd->phase_delay); 5433 } 5434 5435 return ret; 5436 } 5437 5438 /** 5439 * ice_aq_set_output_pin_cfg - set output pin config 5440 * @hw: pointer to the HW struct 5441 * @output_idx: Output index 5442 * @flags: Output flags 5443 * @src_sel: Index of DPLL block 5444 * @freq: Output frequency 5445 * @phase_delay: Output phase compensation 5446 * 5447 * Set CGU output config (0x0C64) 5448 * Return: 0 on success or negative value on failure. 5449 */ 5450 int 5451 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5452 u8 src_sel, u32 freq, s32 phase_delay) 5453 { 5454 struct ice_aqc_set_cgu_output_config *cmd; 5455 struct libie_aq_desc desc; 5456 5457 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5458 cmd = libie_aq_raw(&desc); 5459 cmd->output_idx = output_idx; 5460 cmd->flags = flags; 5461 cmd->src_sel = src_sel; 5462 cmd->freq = cpu_to_le32(freq); 5463 cmd->phase_delay = cpu_to_le32(phase_delay); 5464 5465 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5466 } 5467 5468 /** 5469 * ice_aq_get_output_pin_cfg - get output pin config 5470 * @hw: pointer to the HW struct 5471 * @output_idx: Output index 5472 * @flags: Output flags 5473 * @src_sel: Internal DPLL source 5474 * @freq: Output frequency 5475 * @src_freq: Source frequency 5476 * 5477 * Get CGU output config (0x0C65) 5478 * Return: 0 on success or negative value on failure. 5479 */ 5480 int 5481 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5482 u8 *src_sel, u32 *freq, u32 *src_freq) 5483 { 5484 struct ice_aqc_get_cgu_output_config *cmd; 5485 struct libie_aq_desc desc; 5486 int ret; 5487 5488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5489 cmd = libie_aq_raw(&desc); 5490 cmd->output_idx = output_idx; 5491 5492 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5493 if (!ret) { 5494 if (flags) 5495 *flags = cmd->flags; 5496 if (src_sel) 5497 *src_sel = cmd->src_sel; 5498 if (freq) 5499 *freq = le32_to_cpu(cmd->freq); 5500 if (src_freq) 5501 *src_freq = le32_to_cpu(cmd->src_freq); 5502 } 5503 5504 return ret; 5505 } 5506 5507 /** 5508 * ice_aq_get_cgu_dpll_status - get dpll status 5509 * @hw: pointer to the HW struct 5510 * @dpll_num: DPLL index 5511 * @ref_state: Reference clock state 5512 * @config: current DPLL config 5513 * @dpll_state: current DPLL state 5514 * @phase_offset: Phase offset in ns 5515 * @eec_mode: EEC_mode 5516 * 5517 * Get CGU DPLL status (0x0C66) 5518 * Return: 0 on success or negative value on failure. 5519 */ 5520 int 5521 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5522 u8 *dpll_state, u8 *config, s64 *phase_offset, 5523 u8 *eec_mode) 5524 { 5525 struct ice_aqc_get_cgu_dpll_status *cmd; 5526 struct libie_aq_desc desc; 5527 int status; 5528 5529 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5530 cmd = libie_aq_raw(&desc); 5531 cmd->dpll_num = dpll_num; 5532 5533 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5534 if (!status) { 5535 *ref_state = cmd->ref_state; 5536 *dpll_state = cmd->dpll_state; 5537 *config = cmd->config; 5538 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5539 *phase_offset <<= 32; 5540 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5541 *phase_offset = sign_extend64(*phase_offset, 47); 5542 *eec_mode = cmd->eec_mode; 5543 } 5544 5545 return status; 5546 } 5547 5548 /** 5549 * ice_aq_set_cgu_dpll_config - set dpll config 5550 * @hw: pointer to the HW struct 5551 * @dpll_num: DPLL index 5552 * @ref_state: Reference clock state 5553 * @config: DPLL config 5554 * @eec_mode: EEC mode 5555 * 5556 * Set CGU DPLL config (0x0C67) 5557 * Return: 0 on success or negative value on failure. 5558 */ 5559 int 5560 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5561 u8 config, u8 eec_mode) 5562 { 5563 struct ice_aqc_set_cgu_dpll_config *cmd; 5564 struct libie_aq_desc desc; 5565 5566 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5567 cmd = libie_aq_raw(&desc); 5568 cmd->dpll_num = dpll_num; 5569 cmd->ref_state = ref_state; 5570 cmd->config = config; 5571 cmd->eec_mode = eec_mode; 5572 5573 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5574 } 5575 5576 /** 5577 * ice_aq_set_cgu_ref_prio - set input reference priority 5578 * @hw: pointer to the HW struct 5579 * @dpll_num: DPLL index 5580 * @ref_idx: Reference pin index 5581 * @ref_priority: Reference input priority 5582 * 5583 * Set CGU reference priority (0x0C68) 5584 * Return: 0 on success or negative value on failure. 5585 */ 5586 int 5587 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5588 u8 ref_priority) 5589 { 5590 struct ice_aqc_set_cgu_ref_prio *cmd; 5591 struct libie_aq_desc desc; 5592 5593 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5594 cmd = libie_aq_raw(&desc); 5595 cmd->dpll_num = dpll_num; 5596 cmd->ref_idx = ref_idx; 5597 cmd->ref_priority = ref_priority; 5598 5599 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5600 } 5601 5602 /** 5603 * ice_aq_get_cgu_ref_prio - get input reference priority 5604 * @hw: pointer to the HW struct 5605 * @dpll_num: DPLL index 5606 * @ref_idx: Reference pin index 5607 * @ref_prio: Reference input priority 5608 * 5609 * Get CGU reference priority (0x0C69) 5610 * Return: 0 on success or negative value on failure. 5611 */ 5612 int 5613 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5614 u8 *ref_prio) 5615 { 5616 struct ice_aqc_get_cgu_ref_prio *cmd; 5617 struct libie_aq_desc desc; 5618 int status; 5619 5620 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5621 cmd = libie_aq_raw(&desc); 5622 cmd->dpll_num = dpll_num; 5623 cmd->ref_idx = ref_idx; 5624 5625 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5626 if (!status) 5627 *ref_prio = cmd->ref_priority; 5628 5629 return status; 5630 } 5631 5632 /** 5633 * ice_aq_get_cgu_info - get cgu info 5634 * @hw: pointer to the HW struct 5635 * @cgu_id: CGU ID 5636 * @cgu_cfg_ver: CGU config version 5637 * @cgu_fw_ver: CGU firmware version 5638 * 5639 * Get CGU info (0x0C6A) 5640 * Return: 0 on success or negative value on failure. 5641 */ 5642 int 5643 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5644 u32 *cgu_fw_ver) 5645 { 5646 struct ice_aqc_get_cgu_info *cmd; 5647 struct libie_aq_desc desc; 5648 int status; 5649 5650 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5651 cmd = libie_aq_raw(&desc); 5652 5653 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5654 if (!status) { 5655 *cgu_id = le32_to_cpu(cmd->cgu_id); 5656 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5657 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5658 } 5659 5660 return status; 5661 } 5662 5663 /** 5664 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5665 * @hw: pointer to the HW struct 5666 * @phy_output: PHY reference clock output pin 5667 * @enable: GPIO state to be applied 5668 * @freq: PHY output frequency 5669 * 5670 * Set phy recovered clock as reference (0x0630) 5671 * Return: 0 on success or negative value on failure. 5672 */ 5673 int 5674 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5675 u32 *freq) 5676 { 5677 struct ice_aqc_set_phy_rec_clk_out *cmd; 5678 struct libie_aq_desc desc; 5679 int status; 5680 5681 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5682 cmd = libie_aq_raw(&desc); 5683 cmd->phy_output = phy_output; 5684 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5685 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5686 cmd->freq = cpu_to_le32(*freq); 5687 5688 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5689 if (!status) 5690 *freq = le32_to_cpu(cmd->freq); 5691 5692 return status; 5693 } 5694 5695 /** 5696 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5697 * @hw: pointer to the HW struct 5698 * @phy_output: PHY reference clock output pin 5699 * @port_num: Port number 5700 * @flags: PHY flags 5701 * @node_handle: PHY output frequency 5702 * 5703 * Get PHY recovered clock output info (0x0631) 5704 * Return: 0 on success or negative value on failure. 5705 */ 5706 int 5707 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5708 u8 *flags, u16 *node_handle) 5709 { 5710 struct ice_aqc_get_phy_rec_clk_out *cmd; 5711 struct libie_aq_desc desc; 5712 int status; 5713 5714 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5715 cmd = libie_aq_raw(&desc); 5716 cmd->phy_output = *phy_output; 5717 5718 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5719 if (!status) { 5720 *phy_output = cmd->phy_output; 5721 if (port_num) 5722 *port_num = cmd->port_num; 5723 if (flags) 5724 *flags = cmd->flags; 5725 if (node_handle) 5726 *node_handle = le16_to_cpu(cmd->node_handle); 5727 } 5728 5729 return status; 5730 } 5731 5732 /** 5733 * ice_aq_get_sensor_reading 5734 * @hw: pointer to the HW struct 5735 * @data: pointer to data to be read from the sensor 5736 * 5737 * Get sensor reading (0x0632) 5738 */ 5739 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5740 struct ice_aqc_get_sensor_reading_resp *data) 5741 { 5742 struct ice_aqc_get_sensor_reading *cmd; 5743 struct libie_aq_desc desc; 5744 int status; 5745 5746 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5747 cmd = libie_aq_raw(&desc); 5748 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5749 #define ICE_INTERNAL_TEMP_SENSOR 0 5750 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5751 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5752 5753 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5754 if (!status) 5755 memcpy(data, &desc.params.raw, 5756 sizeof(*data)); 5757 5758 return status; 5759 } 5760 5761 /** 5762 * ice_replay_pre_init - replay pre initialization 5763 * @hw: pointer to the HW struct 5764 * 5765 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5766 */ 5767 static int ice_replay_pre_init(struct ice_hw *hw) 5768 { 5769 struct ice_switch_info *sw = hw->switch_info; 5770 u8 i; 5771 5772 /* Delete old entries from replay filter list head if there is any */ 5773 ice_rm_all_sw_replay_rule_info(hw); 5774 /* In start of replay, move entries into replay_rules list, it 5775 * will allow adding rules entries back to filt_rules list, 5776 * which is operational list. 5777 */ 5778 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5779 list_replace_init(&sw->recp_list[i].filt_rules, 5780 &sw->recp_list[i].filt_replay_rules); 5781 ice_sched_replay_agg_vsi_preinit(hw); 5782 5783 return 0; 5784 } 5785 5786 /** 5787 * ice_replay_vsi - replay VSI configuration 5788 * @hw: pointer to the HW struct 5789 * @vsi_handle: driver VSI handle 5790 * 5791 * Restore all VSI configuration after reset. It is required to call this 5792 * function with main VSI first. 5793 */ 5794 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5795 { 5796 int status; 5797 5798 if (!ice_is_vsi_valid(hw, vsi_handle)) 5799 return -EINVAL; 5800 5801 /* Replay pre-initialization if there is any */ 5802 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5803 status = ice_replay_pre_init(hw); 5804 if (status) 5805 return status; 5806 } 5807 /* Replay per VSI all RSS configurations */ 5808 status = ice_replay_rss_cfg(hw, vsi_handle); 5809 if (status) 5810 return status; 5811 /* Replay per VSI all filters */ 5812 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5813 if (!status) 5814 status = ice_replay_vsi_agg(hw, vsi_handle); 5815 return status; 5816 } 5817 5818 /** 5819 * ice_replay_post - post replay configuration cleanup 5820 * @hw: pointer to the HW struct 5821 * 5822 * Post replay cleanup. 5823 */ 5824 void ice_replay_post(struct ice_hw *hw) 5825 { 5826 /* Delete old entries from replay filter list head */ 5827 ice_rm_all_sw_replay_rule_info(hw); 5828 ice_sched_replay_agg(hw); 5829 } 5830 5831 /** 5832 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5833 * @hw: ptr to the hardware info 5834 * @reg: offset of 64 bit HW register to read from 5835 * @prev_stat_loaded: bool to specify if previous stats are loaded 5836 * @prev_stat: ptr to previous loaded stat value 5837 * @cur_stat: ptr to current stat value 5838 */ 5839 void 5840 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5841 u64 *prev_stat, u64 *cur_stat) 5842 { 5843 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5844 5845 /* device stats are not reset at PFR, they likely will not be zeroed 5846 * when the driver starts. Thus, save the value from the first read 5847 * without adding to the statistic value so that we report stats which 5848 * count up from zero. 5849 */ 5850 if (!prev_stat_loaded) { 5851 *prev_stat = new_data; 5852 return; 5853 } 5854 5855 /* Calculate the difference between the new and old values, and then 5856 * add it to the software stat value. 5857 */ 5858 if (new_data >= *prev_stat) 5859 *cur_stat += new_data - *prev_stat; 5860 else 5861 /* to manage the potential roll-over */ 5862 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5863 5864 /* Update the previously stored value to prepare for next read */ 5865 *prev_stat = new_data; 5866 } 5867 5868 /** 5869 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5870 * @hw: ptr to the hardware info 5871 * @reg: offset of HW register to read from 5872 * @prev_stat_loaded: bool to specify if previous stats are loaded 5873 * @prev_stat: ptr to previous loaded stat value 5874 * @cur_stat: ptr to current stat value 5875 */ 5876 void 5877 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5878 u64 *prev_stat, u64 *cur_stat) 5879 { 5880 u32 new_data; 5881 5882 new_data = rd32(hw, reg); 5883 5884 /* device stats are not reset at PFR, they likely will not be zeroed 5885 * when the driver starts. Thus, save the value from the first read 5886 * without adding to the statistic value so that we report stats which 5887 * count up from zero. 5888 */ 5889 if (!prev_stat_loaded) { 5890 *prev_stat = new_data; 5891 return; 5892 } 5893 5894 /* Calculate the difference between the new and old values, and then 5895 * add it to the software stat value. 5896 */ 5897 if (new_data >= *prev_stat) 5898 *cur_stat += new_data - *prev_stat; 5899 else 5900 /* to manage the potential roll-over */ 5901 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5902 5903 /* Update the previously stored value to prepare for next read */ 5904 *prev_stat = new_data; 5905 } 5906 5907 /** 5908 * ice_sched_query_elem - query element information from HW 5909 * @hw: pointer to the HW struct 5910 * @node_teid: node TEID to be queried 5911 * @buf: buffer to element information 5912 * 5913 * This function queries HW element information 5914 */ 5915 int 5916 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5917 struct ice_aqc_txsched_elem_data *buf) 5918 { 5919 u16 buf_size, num_elem_ret = 0; 5920 int status; 5921 5922 buf_size = sizeof(*buf); 5923 memset(buf, 0, buf_size); 5924 buf->node_teid = cpu_to_le32(node_teid); 5925 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5926 NULL); 5927 if (status || num_elem_ret != 1) 5928 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5929 return status; 5930 } 5931 5932 /** 5933 * ice_aq_read_i2c 5934 * @hw: pointer to the hw struct 5935 * @topo_addr: topology address for a device to communicate with 5936 * @bus_addr: 7-bit I2C bus address 5937 * @addr: I2C memory address (I2C offset) with up to 16 bits 5938 * @params: I2C parameters: bit [7] - Repeated start, 5939 * bits [6:5] data offset size, 5940 * bit [4] - I2C address type, 5941 * bits [3:0] - data size to read (0-16 bytes) 5942 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5943 * @cd: pointer to command details structure or NULL 5944 * 5945 * Read I2C (0x06E2) 5946 */ 5947 int 5948 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5949 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5950 struct ice_sq_cd *cd) 5951 { 5952 struct libie_aq_desc desc = { 0 }; 5953 struct ice_aqc_i2c *cmd; 5954 u8 data_size; 5955 int status; 5956 5957 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5958 cmd = libie_aq_raw(&desc); 5959 5960 if (!data) 5961 return -EINVAL; 5962 5963 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5964 5965 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5966 cmd->topo_addr = topo_addr; 5967 cmd->i2c_params = params; 5968 cmd->i2c_addr = addr; 5969 5970 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5971 if (!status) { 5972 struct ice_aqc_read_i2c_resp *resp; 5973 u8 i; 5974 5975 resp = libie_aq_raw(&desc); 5976 for (i = 0; i < data_size; i++) { 5977 *data = resp->i2c_data[i]; 5978 data++; 5979 } 5980 } 5981 5982 return status; 5983 } 5984 5985 /** 5986 * ice_aq_write_i2c 5987 * @hw: pointer to the hw struct 5988 * @topo_addr: topology address for a device to communicate with 5989 * @bus_addr: 7-bit I2C bus address 5990 * @addr: I2C memory address (I2C offset) with up to 16 bits 5991 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5992 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5993 * @cd: pointer to command details structure or NULL 5994 * 5995 * Write I2C (0x06E3) 5996 * 5997 * * Return: 5998 * * 0 - Successful write to the i2c device 5999 * * -EINVAL - Data size greater than 4 bytes 6000 * * -EIO - FW error 6001 */ 6002 int 6003 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6004 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6005 struct ice_sq_cd *cd) 6006 { 6007 struct libie_aq_desc desc = { 0 }; 6008 struct ice_aqc_i2c *cmd; 6009 u8 data_size; 6010 6011 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6012 cmd = libie_aq_raw(&desc); 6013 6014 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6015 6016 /* data_size limited to 4 */ 6017 if (data_size > 4) 6018 return -EINVAL; 6019 6020 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6021 cmd->topo_addr = topo_addr; 6022 cmd->i2c_params = params; 6023 cmd->i2c_addr = addr; 6024 6025 memcpy(cmd->i2c_data, data, data_size); 6026 6027 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6028 } 6029 6030 /** 6031 * ice_get_pca9575_handle - find and return the PCA9575 controller 6032 * @hw: pointer to the hw struct 6033 * @pca9575_handle: GPIO controller's handle 6034 * 6035 * Find and return the GPIO controller's handle in the netlist. 6036 * When found - the value will be cached in the hw structure and following calls 6037 * will return cached value. 6038 * 6039 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6040 */ 6041 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6042 { 6043 struct ice_aqc_get_link_topo *cmd; 6044 struct libie_aq_desc desc; 6045 int err; 6046 u8 idx; 6047 6048 /* If handle was read previously return cached value */ 6049 if (hw->io_expander_handle) { 6050 *pca9575_handle = hw->io_expander_handle; 6051 return 0; 6052 } 6053 6054 #define SW_PCA9575_SFP_TOPO_IDX 2 6055 #define SW_PCA9575_QSFP_TOPO_IDX 1 6056 6057 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6058 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6059 idx = SW_PCA9575_SFP_TOPO_IDX; 6060 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6061 idx = SW_PCA9575_QSFP_TOPO_IDX; 6062 else 6063 return -ENXIO; 6064 6065 /* If handle was not detected read it from the netlist */ 6066 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6067 cmd = libie_aq_raw(&desc); 6068 cmd->addr.topo_params.node_type_ctx = 6069 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6070 cmd->addr.topo_params.index = idx; 6071 6072 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6073 if (err) 6074 return -ENXIO; 6075 6076 /* Verify if we found the right IO expander type */ 6077 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6078 return -ENXIO; 6079 6080 /* If present save the handle and return it */ 6081 hw->io_expander_handle = 6082 le16_to_cpu(cmd->addr.handle); 6083 *pca9575_handle = hw->io_expander_handle; 6084 6085 return 0; 6086 } 6087 6088 /** 6089 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6090 * @hw: pointer to the hw struct 6091 * @offset: GPIO controller register offset 6092 * @data: pointer to data to be read from the GPIO controller 6093 * 6094 * Return: 0 on success, negative error code otherwise. 6095 */ 6096 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6097 { 6098 struct ice_aqc_link_topo_addr link_topo; 6099 __le16 addr; 6100 u16 handle; 6101 int err; 6102 6103 memset(&link_topo, 0, sizeof(link_topo)); 6104 6105 err = ice_get_pca9575_handle(hw, &handle); 6106 if (err) 6107 return err; 6108 6109 link_topo.handle = cpu_to_le16(handle); 6110 link_topo.topo_params.node_type_ctx = 6111 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6112 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6113 6114 addr = cpu_to_le16((u16)offset); 6115 6116 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6117 } 6118 6119 /** 6120 * ice_aq_set_gpio 6121 * @hw: pointer to the hw struct 6122 * @gpio_ctrl_handle: GPIO controller node handle 6123 * @pin_idx: IO Number of the GPIO that needs to be set 6124 * @value: SW provide IO value to set in the LSB 6125 * @cd: pointer to command details structure or NULL 6126 * 6127 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6128 */ 6129 int 6130 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6131 struct ice_sq_cd *cd) 6132 { 6133 struct libie_aq_desc desc; 6134 struct ice_aqc_gpio *cmd; 6135 6136 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6137 cmd = libie_aq_raw(&desc); 6138 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6139 cmd->gpio_num = pin_idx; 6140 cmd->gpio_val = value ? 1 : 0; 6141 6142 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6143 } 6144 6145 /** 6146 * ice_aq_get_gpio 6147 * @hw: pointer to the hw struct 6148 * @gpio_ctrl_handle: GPIO controller node handle 6149 * @pin_idx: IO Number of the GPIO that needs to be set 6150 * @value: IO value read 6151 * @cd: pointer to command details structure or NULL 6152 * 6153 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6154 * the topology 6155 */ 6156 int 6157 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6158 bool *value, struct ice_sq_cd *cd) 6159 { 6160 struct libie_aq_desc desc; 6161 struct ice_aqc_gpio *cmd; 6162 int status; 6163 6164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6165 cmd = libie_aq_raw(&desc); 6166 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6167 cmd->gpio_num = pin_idx; 6168 6169 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6170 if (status) 6171 return status; 6172 6173 *value = !!cmd->gpio_val; 6174 return 0; 6175 } 6176 6177 /** 6178 * ice_is_fw_api_min_ver 6179 * @hw: pointer to the hardware structure 6180 * @maj: major version 6181 * @min: minor version 6182 * @patch: patch version 6183 * 6184 * Checks if the firmware API is minimum version 6185 */ 6186 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6187 { 6188 if (hw->api_maj_ver == maj) { 6189 if (hw->api_min_ver > min) 6190 return true; 6191 if (hw->api_min_ver == min && hw->api_patch >= patch) 6192 return true; 6193 } else if (hw->api_maj_ver > maj) { 6194 return true; 6195 } 6196 6197 return false; 6198 } 6199 6200 /** 6201 * ice_fw_supports_link_override 6202 * @hw: pointer to the hardware structure 6203 * 6204 * Checks if the firmware supports link override 6205 */ 6206 bool ice_fw_supports_link_override(struct ice_hw *hw) 6207 { 6208 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6209 ICE_FW_API_LINK_OVERRIDE_MIN, 6210 ICE_FW_API_LINK_OVERRIDE_PATCH); 6211 } 6212 6213 /** 6214 * ice_get_link_default_override 6215 * @ldo: pointer to the link default override struct 6216 * @pi: pointer to the port info struct 6217 * 6218 * Gets the link default override for a port 6219 */ 6220 int 6221 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6222 struct ice_port_info *pi) 6223 { 6224 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6225 struct ice_hw *hw = pi->hw; 6226 int status; 6227 6228 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6229 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6230 if (status) { 6231 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6232 return status; 6233 } 6234 6235 /* Each port has its own config; calculate for our port */ 6236 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6237 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6238 6239 /* link options first */ 6240 status = ice_read_sr_word(hw, tlv_start, &buf); 6241 if (status) { 6242 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6243 return status; 6244 } 6245 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6246 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6247 ICE_LINK_OVERRIDE_PHY_CFG_S; 6248 6249 /* link PHY config */ 6250 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6251 status = ice_read_sr_word(hw, offset, &buf); 6252 if (status) { 6253 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6254 return status; 6255 } 6256 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6257 6258 /* PHY types low */ 6259 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6260 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6261 status = ice_read_sr_word(hw, (offset + i), &buf); 6262 if (status) { 6263 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6264 return status; 6265 } 6266 /* shift 16 bits at a time to fill 64 bits */ 6267 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6268 } 6269 6270 /* PHY types high */ 6271 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6272 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6273 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6274 status = ice_read_sr_word(hw, (offset + i), &buf); 6275 if (status) { 6276 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6277 return status; 6278 } 6279 /* shift 16 bits at a time to fill 64 bits */ 6280 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6281 } 6282 6283 return status; 6284 } 6285 6286 /** 6287 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6288 * @caps: get PHY capability data 6289 */ 6290 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6291 { 6292 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6293 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6294 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6295 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6296 return true; 6297 6298 return false; 6299 } 6300 6301 /** 6302 * ice_is_fw_health_report_supported - checks if firmware supports health events 6303 * @hw: pointer to the hardware structure 6304 * 6305 * Return: true if firmware supports health status reports, 6306 * false otherwise 6307 */ 6308 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6309 { 6310 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6311 ICE_FW_API_HEALTH_REPORT_MIN, 6312 ICE_FW_API_HEALTH_REPORT_PATCH); 6313 } 6314 6315 /** 6316 * ice_aq_set_health_status_cfg - Configure FW health events 6317 * @hw: pointer to the HW struct 6318 * @event_source: type of diagnostic events to enable 6319 * 6320 * Configure the health status event types that the firmware will send to this 6321 * PF. The supported event types are: PF-specific, all PFs, and global. 6322 * 6323 * Return: 0 on success, negative error code otherwise. 6324 */ 6325 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6326 { 6327 struct ice_aqc_set_health_status_cfg *cmd; 6328 struct libie_aq_desc desc; 6329 6330 cmd = libie_aq_raw(&desc); 6331 6332 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6333 6334 cmd->event_source = event_source; 6335 6336 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6337 } 6338 6339 /** 6340 * ice_aq_set_lldp_mib - Set the LLDP MIB 6341 * @hw: pointer to the HW struct 6342 * @mib_type: Local, Remote or both Local and Remote MIBs 6343 * @buf: pointer to the caller-supplied buffer to store the MIB block 6344 * @buf_size: size of the buffer (in bytes) 6345 * @cd: pointer to command details structure or NULL 6346 * 6347 * Set the LLDP MIB. (0x0A08) 6348 */ 6349 int 6350 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6351 struct ice_sq_cd *cd) 6352 { 6353 struct ice_aqc_lldp_set_local_mib *cmd; 6354 struct libie_aq_desc desc; 6355 6356 cmd = libie_aq_raw(&desc); 6357 6358 if (buf_size == 0 || !buf) 6359 return -EINVAL; 6360 6361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6362 6363 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6364 desc.datalen = cpu_to_le16(buf_size); 6365 6366 cmd->type = mib_type; 6367 cmd->length = cpu_to_le16(buf_size); 6368 6369 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6370 } 6371 6372 /** 6373 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6374 * @hw: pointer to HW struct 6375 */ 6376 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6377 { 6378 if (hw->mac_type != ICE_MAC_E810) 6379 return false; 6380 6381 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6382 ICE_FW_API_LLDP_FLTR_MIN, 6383 ICE_FW_API_LLDP_FLTR_PATCH); 6384 } 6385 6386 /** 6387 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6388 * @hw: pointer to HW struct 6389 * @vsi: VSI to add the filter to 6390 * @add: boolean for if adding or removing a filter 6391 * 6392 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6393 * with this HW or VSI, otherwise an error corresponding to 6394 * the AQ transaction result. 6395 */ 6396 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6397 { 6398 struct ice_aqc_lldp_filter_ctrl *cmd; 6399 struct libie_aq_desc desc; 6400 6401 if (!ice_fw_supports_lldp_fltr_ctrl(hw)) 6402 return -EOPNOTSUPP; 6403 6404 cmd = libie_aq_raw(&desc); 6405 6406 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6407 6408 if (add) 6409 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6410 else 6411 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6412 6413 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6414 6415 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6416 } 6417 6418 /** 6419 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6420 * @hw: pointer to HW struct 6421 */ 6422 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6423 { 6424 struct libie_aq_desc desc; 6425 6426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6427 6428 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6429 } 6430 6431 /** 6432 * ice_fw_supports_report_dflt_cfg 6433 * @hw: pointer to the hardware structure 6434 * 6435 * Checks if the firmware supports report default configuration 6436 */ 6437 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6438 { 6439 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6440 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6441 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6442 } 6443 6444 /* each of the indexes into the following array match the speed of a return 6445 * value from the list of AQ returned speeds like the range: 6446 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6447 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6448 * array. The array is defined as 15 elements long because the link_speed 6449 * returned by the firmware is a 16 bit * value, but is indexed 6450 * by [fls(speed) - 1] 6451 */ 6452 static const u32 ice_aq_to_link_speed[] = { 6453 SPEED_10, /* BIT(0) */ 6454 SPEED_100, 6455 SPEED_1000, 6456 SPEED_2500, 6457 SPEED_5000, 6458 SPEED_10000, 6459 SPEED_20000, 6460 SPEED_25000, 6461 SPEED_40000, 6462 SPEED_50000, 6463 SPEED_100000, /* BIT(10) */ 6464 SPEED_200000, 6465 }; 6466 6467 /** 6468 * ice_get_link_speed - get integer speed from table 6469 * @index: array index from fls(aq speed) - 1 6470 * 6471 * Returns: u32 value containing integer speed 6472 */ 6473 u32 ice_get_link_speed(u16 index) 6474 { 6475 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6476 return 0; 6477 6478 return ice_aq_to_link_speed[index]; 6479 } 6480 6481 /** 6482 * ice_get_dest_cgu - get destination CGU dev for given HW 6483 * @hw: pointer to the HW struct 6484 * 6485 * Get CGU client id for CGU register read/write operations. 6486 * 6487 * Return: CGU device id to use in SBQ transactions. 6488 */ 6489 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6490 { 6491 /* On dual complex E825 only complex 0 has functional CGU powering all 6492 * the PHYs. 6493 * SBQ destination device cgu points to CGU on a current complex and to 6494 * access primary CGU from the secondary complex, the driver should use 6495 * cgu_peer as a destination device. 6496 */ 6497 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6498 !ice_is_primary(hw)) 6499 return ice_sbq_dev_cgu_peer; 6500 return ice_sbq_dev_cgu; 6501 } 6502 6503 /** 6504 * ice_read_cgu_reg - Read a CGU register 6505 * @hw: Pointer to the HW struct 6506 * @addr: Register address to read 6507 * @val: Storage for register value read 6508 * 6509 * Read the contents of a register of the Clock Generation Unit. Only 6510 * applicable to E82X devices. 6511 * 6512 * Return: 0 on success, other error codes when failed to read from CGU. 6513 */ 6514 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6515 { 6516 struct ice_sbq_msg_input cgu_msg = { 6517 .dest_dev = ice_get_dest_cgu(hw), 6518 .opcode = ice_sbq_msg_rd, 6519 .msg_addr_low = addr 6520 }; 6521 int err; 6522 6523 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6524 if (err) { 6525 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6526 addr, err); 6527 return err; 6528 } 6529 6530 *val = cgu_msg.data; 6531 6532 return 0; 6533 } 6534 6535 /** 6536 * ice_write_cgu_reg - Write a CGU register 6537 * @hw: Pointer to the HW struct 6538 * @addr: Register address to write 6539 * @val: Value to write into the register 6540 * 6541 * Write the specified value to a register of the Clock Generation Unit. Only 6542 * applicable to E82X devices. 6543 * 6544 * Return: 0 on success, other error codes when failed to write to CGU. 6545 */ 6546 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6547 { 6548 struct ice_sbq_msg_input cgu_msg = { 6549 .dest_dev = ice_get_dest_cgu(hw), 6550 .opcode = ice_sbq_msg_wr, 6551 .msg_addr_low = addr, 6552 .data = val 6553 }; 6554 int err; 6555 6556 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6557 if (err) 6558 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6559 addr, err); 6560 6561 return err; 6562 } 6563