1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473 } 474 475 /** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496 { 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520 } 521 522 /** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529 static bool ice_is_media_cage_present(struct ice_port_info *pi) 530 { 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538 } 539 540 /** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545 { 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655 } 656 657 /** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665 { 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673 } 674 675 /** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684 int 685 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687 { 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775 } 776 777 /** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785 static void 786 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788 { 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824 } 825 826 /** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834 int 835 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 { 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852 } 853 854 /** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859 { 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882 } 883 884 /** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889 { 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932 } 933 934 /** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942 { 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958 } 959 960 /** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968 { 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985 } 986 987 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 988 u16 size) 989 { 990 struct ice_hw *hw = priv; 991 992 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 993 } 994 995 static int __fwlog_init(struct ice_hw *hw) 996 { 997 struct ice_pf *pf = hw->back; 998 struct libie_fwlog_api api = { 999 .pdev = pf->pdev, 1000 .send_cmd = __fwlog_send_cmd, 1001 .priv = hw, 1002 }; 1003 int err; 1004 1005 /* only support fw log commands on PF 0 */ 1006 if (hw->bus.func) 1007 return -EINVAL; 1008 1009 err = ice_debugfs_pf_init(pf); 1010 if (err) 1011 return err; 1012 1013 api.debugfs_root = pf->ice_debugfs_pf; 1014 1015 return libie_fwlog_init(&hw->fwlog, &api); 1016 } 1017 1018 /** 1019 * ice_init_hw - main hardware initialization routine 1020 * @hw: pointer to the hardware structure 1021 */ 1022 int ice_init_hw(struct ice_hw *hw) 1023 { 1024 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1025 void *mac_buf __free(kfree) = NULL; 1026 u16 mac_buf_len; 1027 int status; 1028 1029 /* Set MAC type based on DeviceID */ 1030 status = ice_set_mac_type(hw); 1031 if (status) 1032 return status; 1033 1034 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1035 1036 status = ice_reset(hw, ICE_RESET_PFR); 1037 if (status) 1038 return status; 1039 1040 ice_get_itr_intrl_gran(hw); 1041 1042 status = ice_create_all_ctrlq(hw); 1043 if (status) 1044 goto err_unroll_cqinit; 1045 1046 status = __fwlog_init(hw); 1047 if (status) 1048 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1049 status); 1050 1051 status = ice_clear_pf_cfg(hw); 1052 if (status) 1053 goto err_unroll_cqinit; 1054 1055 /* Set bit to enable Flow Director filters */ 1056 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1057 INIT_LIST_HEAD(&hw->fdir_list_head); 1058 1059 ice_clear_pxe_mode(hw); 1060 1061 status = ice_init_nvm(hw); 1062 if (status) 1063 goto err_unroll_cqinit; 1064 1065 status = ice_get_caps(hw); 1066 if (status) 1067 goto err_unroll_cqinit; 1068 1069 if (!hw->port_info) 1070 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1071 sizeof(*hw->port_info), 1072 GFP_KERNEL); 1073 if (!hw->port_info) { 1074 status = -ENOMEM; 1075 goto err_unroll_cqinit; 1076 } 1077 1078 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1079 /* set the back pointer to HW */ 1080 hw->port_info->hw = hw; 1081 1082 /* Initialize port_info struct with switch configuration data */ 1083 status = ice_get_initial_sw_cfg(hw); 1084 if (status) 1085 goto err_unroll_alloc; 1086 1087 hw->evb_veb = true; 1088 1089 /* init xarray for identifying scheduling nodes uniquely */ 1090 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1091 1092 /* Query the allocated resources for Tx scheduler */ 1093 status = ice_sched_query_res_alloc(hw); 1094 if (status) { 1095 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1096 goto err_unroll_alloc; 1097 } 1098 ice_sched_get_psm_clk_freq(hw); 1099 1100 /* Initialize port_info struct with scheduler data */ 1101 status = ice_sched_init_port(hw->port_info); 1102 if (status) 1103 goto err_unroll_sched; 1104 1105 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1106 if (!pcaps) { 1107 status = -ENOMEM; 1108 goto err_unroll_sched; 1109 } 1110 1111 /* Initialize port_info struct with PHY capabilities */ 1112 status = ice_aq_get_phy_caps(hw->port_info, false, 1113 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1114 NULL); 1115 if (status) 1116 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1117 status); 1118 1119 /* Initialize port_info struct with link information */ 1120 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1121 if (status) 1122 goto err_unroll_sched; 1123 1124 /* need a valid SW entry point to build a Tx tree */ 1125 if (!hw->sw_entry_point_layer) { 1126 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1127 status = -EIO; 1128 goto err_unroll_sched; 1129 } 1130 INIT_LIST_HEAD(&hw->agg_list); 1131 /* Initialize max burst size */ 1132 if (!hw->max_burst_size) 1133 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1134 1135 status = ice_init_fltr_mgmt_struct(hw); 1136 if (status) 1137 goto err_unroll_sched; 1138 1139 /* Get MAC information */ 1140 /* A single port can report up to two (LAN and WoL) addresses */ 1141 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1142 GFP_KERNEL); 1143 if (!mac_buf) { 1144 status = -ENOMEM; 1145 goto err_unroll_fltr_mgmt_struct; 1146 } 1147 1148 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1149 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1150 1151 if (status) 1152 goto err_unroll_fltr_mgmt_struct; 1153 /* enable jumbo frame support at MAC level */ 1154 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1155 if (status) 1156 goto err_unroll_fltr_mgmt_struct; 1157 /* Obtain counter base index which would be used by flow director */ 1158 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1159 if (status) 1160 goto err_unroll_fltr_mgmt_struct; 1161 status = ice_init_hw_tbls(hw); 1162 if (status) 1163 goto err_unroll_fltr_mgmt_struct; 1164 mutex_init(&hw->tnl_lock); 1165 ice_init_chk_recipe_reuse_support(hw); 1166 1167 /* Some cards require longer initialization times 1168 * due to necessity of loading FW from an external source. 1169 * This can take even half a minute. 1170 */ 1171 if (ice_is_pf_c827(hw)) { 1172 status = ice_wait_for_fw(hw, 30000); 1173 if (status) { 1174 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1175 goto err_unroll_fltr_mgmt_struct; 1176 } 1177 } 1178 1179 hw->lane_num = ice_get_phy_lane_number(hw); 1180 1181 return 0; 1182 err_unroll_fltr_mgmt_struct: 1183 ice_cleanup_fltr_mgmt_struct(hw); 1184 err_unroll_sched: 1185 ice_sched_cleanup_all(hw); 1186 err_unroll_alloc: 1187 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1188 err_unroll_cqinit: 1189 ice_destroy_all_ctrlq(hw); 1190 return status; 1191 } 1192 1193 static void __fwlog_deinit(struct ice_hw *hw) 1194 { 1195 /* only support fw log commands on PF 0 */ 1196 if (hw->bus.func) 1197 return; 1198 1199 ice_debugfs_pf_deinit(hw->back); 1200 libie_fwlog_deinit(&hw->fwlog); 1201 } 1202 1203 /** 1204 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1205 * @hw: pointer to the hardware structure 1206 * 1207 * This should be called only during nominal operation, not as a result of 1208 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1209 * applicable initializations if it fails for any reason. 1210 */ 1211 void ice_deinit_hw(struct ice_hw *hw) 1212 { 1213 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1214 ice_cleanup_fltr_mgmt_struct(hw); 1215 1216 ice_sched_cleanup_all(hw); 1217 ice_sched_clear_agg(hw); 1218 ice_free_seg(hw); 1219 ice_free_hw_tbls(hw); 1220 mutex_destroy(&hw->tnl_lock); 1221 __fwlog_deinit(hw); 1222 ice_destroy_all_ctrlq(hw); 1223 1224 /* Clear VSI contexts if not already cleared */ 1225 ice_clear_all_vsi_ctx(hw); 1226 } 1227 1228 /** 1229 * ice_check_reset - Check to see if a global reset is complete 1230 * @hw: pointer to the hardware structure 1231 */ 1232 int ice_check_reset(struct ice_hw *hw) 1233 { 1234 u32 cnt, reg = 0, grst_timeout, uld_mask; 1235 1236 /* Poll for Device Active state in case a recent CORER, GLOBR, 1237 * or EMPR has occurred. The grst delay value is in 100ms units. 1238 * Add 1sec for outstanding AQ commands that can take a long time. 1239 */ 1240 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1241 rd32(hw, GLGEN_RSTCTL)) + 10; 1242 1243 for (cnt = 0; cnt < grst_timeout; cnt++) { 1244 mdelay(100); 1245 reg = rd32(hw, GLGEN_RSTAT); 1246 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1247 break; 1248 } 1249 1250 if (cnt == grst_timeout) { 1251 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1252 return -EIO; 1253 } 1254 1255 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1256 GLNVM_ULD_PCIER_DONE_1_M |\ 1257 GLNVM_ULD_CORER_DONE_M |\ 1258 GLNVM_ULD_GLOBR_DONE_M |\ 1259 GLNVM_ULD_POR_DONE_M |\ 1260 GLNVM_ULD_POR_DONE_1_M |\ 1261 GLNVM_ULD_PCIER_DONE_2_M) 1262 1263 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1264 GLNVM_ULD_PE_DONE_M : 0); 1265 1266 /* Device is Active; check Global Reset processes are done */ 1267 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1268 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1269 if (reg == uld_mask) { 1270 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1271 break; 1272 } 1273 mdelay(10); 1274 } 1275 1276 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1277 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1278 reg); 1279 return -EIO; 1280 } 1281 1282 return 0; 1283 } 1284 1285 /** 1286 * ice_pf_reset - Reset the PF 1287 * @hw: pointer to the hardware structure 1288 * 1289 * If a global reset has been triggered, this function checks 1290 * for its completion and then issues the PF reset 1291 */ 1292 static int ice_pf_reset(struct ice_hw *hw) 1293 { 1294 u32 cnt, reg; 1295 1296 /* If at function entry a global reset was already in progress, i.e. 1297 * state is not 'device active' or any of the reset done bits are not 1298 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1299 * global reset is done. 1300 */ 1301 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1302 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1303 /* poll on global reset currently in progress until done */ 1304 if (ice_check_reset(hw)) 1305 return -EIO; 1306 1307 return 0; 1308 } 1309 1310 /* Reset the PF */ 1311 reg = rd32(hw, PFGEN_CTRL); 1312 1313 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1314 1315 /* Wait for the PFR to complete. The wait time is the global config lock 1316 * timeout plus the PFR timeout which will account for a possible reset 1317 * that is occurring during a download package operation. 1318 */ 1319 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1320 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1321 reg = rd32(hw, PFGEN_CTRL); 1322 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1323 break; 1324 1325 mdelay(1); 1326 } 1327 1328 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1329 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1330 return -EIO; 1331 } 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * ice_reset - Perform different types of reset 1338 * @hw: pointer to the hardware structure 1339 * @req: reset request 1340 * 1341 * This function triggers a reset as specified by the req parameter. 1342 * 1343 * Note: 1344 * If anything other than a PF reset is triggered, PXE mode is restored. 1345 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1346 * interface has been restored in the rebuild flow. 1347 */ 1348 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1349 { 1350 u32 val = 0; 1351 1352 switch (req) { 1353 case ICE_RESET_PFR: 1354 return ice_pf_reset(hw); 1355 case ICE_RESET_CORER: 1356 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1357 val = GLGEN_RTRIG_CORER_M; 1358 break; 1359 case ICE_RESET_GLOBR: 1360 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1361 val = GLGEN_RTRIG_GLOBR_M; 1362 break; 1363 default: 1364 return -EINVAL; 1365 } 1366 1367 val |= rd32(hw, GLGEN_RTRIG); 1368 wr32(hw, GLGEN_RTRIG, val); 1369 ice_flush(hw); 1370 1371 /* wait for the FW to be ready */ 1372 return ice_check_reset(hw); 1373 } 1374 1375 /** 1376 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1377 * @hw: pointer to the hardware structure 1378 * @rxq_ctx: pointer to the packed Rx queue context 1379 * @rxq_index: the index of the Rx queue 1380 */ 1381 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1382 const ice_rxq_ctx_buf_t *rxq_ctx, 1383 u32 rxq_index) 1384 { 1385 /* Copy each dword separately to HW */ 1386 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1387 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1388 1389 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1390 1391 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1392 } 1393 } 1394 1395 /** 1396 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1397 * @hw: pointer to the hardware structure 1398 * @rxq_ctx: pointer to the packed Rx queue context 1399 * @rxq_index: the index of the Rx queue 1400 */ 1401 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1402 ice_rxq_ctx_buf_t *rxq_ctx, 1403 u32 rxq_index) 1404 { 1405 u32 *ctx = (u32 *)rxq_ctx; 1406 1407 /* Copy each dword separately from HW */ 1408 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1409 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1410 1411 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1412 } 1413 } 1414 1415 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1416 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1417 1418 /* LAN Rx Queue Context */ 1419 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1420 /* Field Width LSB */ 1421 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1422 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1423 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1424 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1425 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1426 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1427 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1428 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1429 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1430 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1431 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1432 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1433 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1434 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1435 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1436 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1437 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1438 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1439 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1440 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1441 }; 1442 1443 /** 1444 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1445 * @ctx: the Rx queue context to pack 1446 * @buf: the HW buffer to pack into 1447 * 1448 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1449 * bit-packed HW layout. 1450 */ 1451 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1452 ice_rxq_ctx_buf_t *buf) 1453 { 1454 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1455 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1456 } 1457 1458 /** 1459 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1460 * @buf: the HW buffer to unpack from 1461 * @ctx: the Rx queue context to unpack 1462 * 1463 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1464 * structure. 1465 */ 1466 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1467 struct ice_rlan_ctx *ctx) 1468 { 1469 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1470 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1471 } 1472 1473 /** 1474 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1475 * @hw: pointer to the hardware structure 1476 * @rlan_ctx: pointer to the unpacked Rx queue context 1477 * @rxq_index: the index of the Rx queue 1478 * 1479 * Pack the sparse Rx Queue context into dense hardware format and write it 1480 * into the HW register space. 1481 * 1482 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1483 */ 1484 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1485 u32 rxq_index) 1486 { 1487 ice_rxq_ctx_buf_t buf = {}; 1488 1489 if (rxq_index > QRX_CTRL_MAX_INDEX) 1490 return -EINVAL; 1491 1492 ice_pack_rxq_ctx(rlan_ctx, &buf); 1493 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1494 1495 return 0; 1496 } 1497 1498 /** 1499 * ice_read_rxq_ctx - Read Rx queue context from HW 1500 * @hw: pointer to the hardware structure 1501 * @rlan_ctx: pointer to the Rx queue context 1502 * @rxq_index: the index of the Rx queue 1503 * 1504 * Read the Rx queue context from the hardware registers, and unpack it into 1505 * the sparse Rx queue context structure. 1506 * 1507 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1508 */ 1509 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1510 u32 rxq_index) 1511 { 1512 ice_rxq_ctx_buf_t buf = {}; 1513 1514 if (rxq_index > QRX_CTRL_MAX_INDEX) 1515 return -EINVAL; 1516 1517 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1518 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1519 1520 return 0; 1521 } 1522 1523 /* LAN Tx Queue Context */ 1524 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1525 /* Field Width LSB */ 1526 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1527 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1528 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1529 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1530 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1531 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1532 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1533 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1534 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1535 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1536 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1537 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1538 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1539 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1540 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1541 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1542 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1543 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1544 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1545 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1546 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1547 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1548 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1549 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1550 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1551 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1552 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1553 }; 1554 1555 /** 1556 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1557 * @ctx: the Tx queue context to pack 1558 * @buf: the Admin Queue HW buffer to pack into 1559 * 1560 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1561 * bit-packed Admin Queue layout. 1562 */ 1563 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1564 { 1565 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1566 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1567 } 1568 1569 /** 1570 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1571 * @ctx: the Tx queue context to pack 1572 * @buf: the HW buffer to pack into 1573 * 1574 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1575 * bit-packed HW layout, including the internal data portion. 1576 */ 1577 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1578 ice_txq_ctx_buf_full_t *buf) 1579 { 1580 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1581 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1582 } 1583 1584 /** 1585 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1586 * @buf: the HW buffer to unpack from 1587 * @ctx: the Tx queue context to unpack 1588 * 1589 * Unpack the Tx queue context from the HW buffer (including the full internal 1590 * state) into the CPU-friendly structure. 1591 */ 1592 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1593 struct ice_tlan_ctx *ctx) 1594 { 1595 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1596 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1597 } 1598 1599 /** 1600 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1601 * @hw: pointer to the hardware structure 1602 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1603 * @txq_index: the index of the Tx queue 1604 * 1605 * Copy Tx Queue context from HW register space to dense structure 1606 */ 1607 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1608 ice_txq_ctx_buf_full_t *txq_ctx, 1609 u32 txq_index) 1610 { 1611 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1612 u32 *ctx = (u32 *)txq_ctx; 1613 u32 txq_base, reg; 1614 1615 /* Get Tx queue base within card space */ 1616 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1617 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1618 1619 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1620 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1621 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1622 txq_base + txq_index) | 1623 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1624 1625 /* Prevent other PFs on the same adapter from accessing the Tx queue 1626 * context interface concurrently. 1627 */ 1628 spin_lock(&pf->adapter->txq_ctx_lock); 1629 1630 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1631 ice_flush(hw); 1632 1633 /* Copy each dword separately from HW */ 1634 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1635 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1636 1637 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1638 } 1639 1640 spin_unlock(&pf->adapter->txq_ctx_lock); 1641 } 1642 1643 /** 1644 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1645 * @hw: pointer to the hardware structure 1646 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1647 * @txq_index: the index of the Tx queue 1648 */ 1649 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1650 const ice_txq_ctx_buf_full_t *txq_ctx, 1651 u32 txq_index) 1652 { 1653 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1654 u32 txq_base, reg; 1655 1656 /* Get Tx queue base within card space */ 1657 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1658 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1659 1660 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1661 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1662 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1663 txq_base + txq_index) | 1664 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1665 1666 /* Prevent other PFs on the same adapter from accessing the Tx queue 1667 * context interface concurrently. 1668 */ 1669 spin_lock(&pf->adapter->txq_ctx_lock); 1670 1671 /* Copy each dword separately to HW */ 1672 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1673 u32 ctx = ((const u32 *)txq_ctx)[i]; 1674 1675 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1676 1677 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1678 } 1679 1680 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1681 ice_flush(hw); 1682 1683 spin_unlock(&pf->adapter->txq_ctx_lock); 1684 } 1685 1686 /** 1687 * ice_read_txq_ctx - Read Tx queue context from HW 1688 * @hw: pointer to the hardware structure 1689 * @tlan_ctx: pointer to the Tx queue context 1690 * @txq_index: the index of the Tx queue 1691 * 1692 * Read the Tx queue context from the HW registers, then unpack it into the 1693 * ice_tlan_ctx structure for use. 1694 * 1695 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1696 */ 1697 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1698 u32 txq_index) 1699 { 1700 ice_txq_ctx_buf_full_t buf = {}; 1701 1702 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1703 return -EINVAL; 1704 1705 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1706 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1707 1708 return 0; 1709 } 1710 1711 /** 1712 * ice_write_txq_ctx - Write Tx queue context to HW 1713 * @hw: pointer to the hardware structure 1714 * @tlan_ctx: pointer to the Tx queue context 1715 * @txq_index: the index of the Tx queue 1716 * 1717 * Pack the Tx queue context into the dense HW layout, then write it into the 1718 * HW registers. 1719 * 1720 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1721 */ 1722 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1723 u32 txq_index) 1724 { 1725 ice_txq_ctx_buf_full_t buf = {}; 1726 1727 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1728 return -EINVAL; 1729 1730 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1731 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1732 1733 return 0; 1734 } 1735 1736 /* Sideband Queue command wrappers */ 1737 1738 /** 1739 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1740 * @hw: pointer to the HW struct 1741 * @desc: descriptor describing the command 1742 * @buf: buffer to use for indirect commands (NULL for direct commands) 1743 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1744 * @cd: pointer to command details structure 1745 */ 1746 static int 1747 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1748 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1749 { 1750 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1751 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1752 } 1753 1754 /** 1755 * ice_sbq_rw_reg - Fill Sideband Queue command 1756 * @hw: pointer to the HW struct 1757 * @in: message info to be filled in descriptor 1758 * @flags: control queue descriptor flags 1759 */ 1760 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1761 { 1762 struct ice_sbq_cmd_desc desc = {0}; 1763 struct ice_sbq_msg_req msg = {0}; 1764 u16 msg_len; 1765 int status; 1766 1767 msg_len = sizeof(msg); 1768 1769 msg.dest_dev = in->dest_dev; 1770 msg.opcode = in->opcode; 1771 msg.flags = ICE_SBQ_MSG_FLAGS; 1772 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1773 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1774 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1775 1776 if (in->opcode) 1777 msg.data = cpu_to_le32(in->data); 1778 else 1779 /* data read comes back in completion, so shorten the struct by 1780 * sizeof(msg.data) 1781 */ 1782 msg_len -= sizeof(msg.data); 1783 1784 desc.flags = cpu_to_le16(flags); 1785 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1786 desc.param0.cmd_len = cpu_to_le16(msg_len); 1787 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1788 if (!status && !in->opcode) 1789 in->data = le32_to_cpu 1790 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1791 return status; 1792 } 1793 1794 /* FW Admin Queue command wrappers */ 1795 1796 /* Software lock/mutex that is meant to be held while the Global Config Lock 1797 * in firmware is acquired by the software to prevent most (but not all) types 1798 * of AQ commands from being sent to FW 1799 */ 1800 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1801 1802 /** 1803 * ice_should_retry_sq_send_cmd 1804 * @opcode: AQ opcode 1805 * 1806 * Decide if we should retry the send command routine for the ATQ, depending 1807 * on the opcode. 1808 */ 1809 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1810 { 1811 switch (opcode) { 1812 case ice_aqc_opc_get_link_topo: 1813 case ice_aqc_opc_lldp_stop: 1814 case ice_aqc_opc_lldp_start: 1815 case ice_aqc_opc_lldp_filter_ctrl: 1816 return true; 1817 } 1818 1819 return false; 1820 } 1821 1822 /** 1823 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1824 * @hw: pointer to the HW struct 1825 * @cq: pointer to the specific Control queue 1826 * @desc: prefilled descriptor describing the command 1827 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1828 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1829 * @cd: pointer to command details structure 1830 * 1831 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1832 * Queue if the EBUSY AQ error is returned. 1833 */ 1834 static int 1835 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1836 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1837 struct ice_sq_cd *cd) 1838 { 1839 struct libie_aq_desc desc_cpy; 1840 bool is_cmd_for_retry; 1841 u8 idx = 0; 1842 u16 opcode; 1843 int status; 1844 1845 opcode = le16_to_cpu(desc->opcode); 1846 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1847 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1848 1849 if (is_cmd_for_retry) { 1850 /* All retryable cmds are direct, without buf. */ 1851 WARN_ON(buf); 1852 1853 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1854 } 1855 1856 do { 1857 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1858 1859 if (!is_cmd_for_retry || !status || 1860 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1861 break; 1862 1863 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1864 1865 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1866 1867 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1868 1869 return status; 1870 } 1871 1872 /** 1873 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1874 * @hw: pointer to the HW struct 1875 * @desc: descriptor describing the command 1876 * @buf: buffer to use for indirect commands (NULL for direct commands) 1877 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1878 * @cd: pointer to command details structure 1879 * 1880 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1881 */ 1882 int 1883 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1884 u16 buf_size, struct ice_sq_cd *cd) 1885 { 1886 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1887 bool lock_acquired = false; 1888 int status; 1889 1890 /* When a package download is in process (i.e. when the firmware's 1891 * Global Configuration Lock resource is held), only the Download 1892 * Package, Get Version, Get Package Info List, Upload Section, 1893 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1894 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1895 * Recipes to Profile Association, and Release Resource (with resource 1896 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1897 * must block until the package download completes and the Global Config 1898 * Lock is released. See also ice_acquire_global_cfg_lock(). 1899 */ 1900 switch (le16_to_cpu(desc->opcode)) { 1901 case ice_aqc_opc_download_pkg: 1902 case ice_aqc_opc_get_pkg_info_list: 1903 case ice_aqc_opc_get_ver: 1904 case ice_aqc_opc_upload_section: 1905 case ice_aqc_opc_update_pkg: 1906 case ice_aqc_opc_set_port_params: 1907 case ice_aqc_opc_get_vlan_mode_parameters: 1908 case ice_aqc_opc_set_vlan_mode_parameters: 1909 case ice_aqc_opc_set_tx_topo: 1910 case ice_aqc_opc_get_tx_topo: 1911 case ice_aqc_opc_add_recipe: 1912 case ice_aqc_opc_recipe_to_profile: 1913 case ice_aqc_opc_get_recipe: 1914 case ice_aqc_opc_get_recipe_to_profile: 1915 break; 1916 case ice_aqc_opc_release_res: 1917 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1918 break; 1919 fallthrough; 1920 default: 1921 mutex_lock(&ice_global_cfg_lock_sw); 1922 lock_acquired = true; 1923 break; 1924 } 1925 1926 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1927 if (lock_acquired) 1928 mutex_unlock(&ice_global_cfg_lock_sw); 1929 1930 return status; 1931 } 1932 1933 /** 1934 * ice_aq_get_fw_ver 1935 * @hw: pointer to the HW struct 1936 * @cd: pointer to command details structure or NULL 1937 * 1938 * Get the firmware version (0x0001) from the admin queue commands 1939 */ 1940 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1941 { 1942 struct libie_aqc_get_ver *resp; 1943 struct libie_aq_desc desc; 1944 int status; 1945 1946 resp = &desc.params.get_ver; 1947 1948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1949 1950 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1951 1952 if (!status) { 1953 hw->fw_branch = resp->fw_branch; 1954 hw->fw_maj_ver = resp->fw_major; 1955 hw->fw_min_ver = resp->fw_minor; 1956 hw->fw_patch = resp->fw_patch; 1957 hw->fw_build = le32_to_cpu(resp->fw_build); 1958 hw->api_branch = resp->api_branch; 1959 hw->api_maj_ver = resp->api_major; 1960 hw->api_min_ver = resp->api_minor; 1961 hw->api_patch = resp->api_patch; 1962 } 1963 1964 return status; 1965 } 1966 1967 /** 1968 * ice_aq_send_driver_ver 1969 * @hw: pointer to the HW struct 1970 * @dv: driver's major, minor version 1971 * @cd: pointer to command details structure or NULL 1972 * 1973 * Send the driver version (0x0002) to the firmware 1974 */ 1975 int 1976 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1977 struct ice_sq_cd *cd) 1978 { 1979 struct libie_aqc_driver_ver *cmd; 1980 struct libie_aq_desc desc; 1981 u16 len; 1982 1983 cmd = &desc.params.driver_ver; 1984 1985 if (!dv) 1986 return -EINVAL; 1987 1988 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1989 1990 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1991 cmd->major_ver = dv->major_ver; 1992 cmd->minor_ver = dv->minor_ver; 1993 cmd->build_ver = dv->build_ver; 1994 cmd->subbuild_ver = dv->subbuild_ver; 1995 1996 len = 0; 1997 while (len < sizeof(dv->driver_string) && 1998 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1999 len++; 2000 2001 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2002 } 2003 2004 /** 2005 * ice_aq_q_shutdown 2006 * @hw: pointer to the HW struct 2007 * @unloading: is the driver unloading itself 2008 * 2009 * Tell the Firmware that we're shutting down the AdminQ and whether 2010 * or not the driver is unloading as well (0x0003). 2011 */ 2012 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2013 { 2014 struct ice_aqc_q_shutdown *cmd; 2015 struct libie_aq_desc desc; 2016 2017 cmd = libie_aq_raw(&desc); 2018 2019 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2020 2021 if (unloading) 2022 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2023 2024 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2025 } 2026 2027 /** 2028 * ice_aq_req_res 2029 * @hw: pointer to the HW struct 2030 * @res: resource ID 2031 * @access: access type 2032 * @sdp_number: resource number 2033 * @timeout: the maximum time in ms that the driver may hold the resource 2034 * @cd: pointer to command details structure or NULL 2035 * 2036 * Requests common resource using the admin queue commands (0x0008). 2037 * When attempting to acquire the Global Config Lock, the driver can 2038 * learn of three states: 2039 * 1) 0 - acquired lock, and can perform download package 2040 * 2) -EIO - did not get lock, driver should fail to load 2041 * 3) -EALREADY - did not get lock, but another driver has 2042 * successfully downloaded the package; the driver does 2043 * not have to download the package and can continue 2044 * loading 2045 * 2046 * Note that if the caller is in an acquire lock, perform action, release lock 2047 * phase of operation, it is possible that the FW may detect a timeout and issue 2048 * a CORER. In this case, the driver will receive a CORER interrupt and will 2049 * have to determine its cause. The calling thread that is handling this flow 2050 * will likely get an error propagated back to it indicating the Download 2051 * Package, Update Package or the Release Resource AQ commands timed out. 2052 */ 2053 static int 2054 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2055 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2056 struct ice_sq_cd *cd) 2057 { 2058 struct libie_aqc_req_res *cmd_resp; 2059 struct libie_aq_desc desc; 2060 int status; 2061 2062 cmd_resp = &desc.params.res_owner; 2063 2064 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2065 2066 cmd_resp->res_id = cpu_to_le16(res); 2067 cmd_resp->access_type = cpu_to_le16(access); 2068 cmd_resp->res_number = cpu_to_le32(sdp_number); 2069 cmd_resp->timeout = cpu_to_le32(*timeout); 2070 *timeout = 0; 2071 2072 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2073 2074 /* The completion specifies the maximum time in ms that the driver 2075 * may hold the resource in the Timeout field. 2076 */ 2077 2078 /* Global config lock response utilizes an additional status field. 2079 * 2080 * If the Global config lock resource is held by some other driver, the 2081 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2082 * and the timeout field indicates the maximum time the current owner 2083 * of the resource has to free it. 2084 */ 2085 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2086 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2087 *timeout = le32_to_cpu(cmd_resp->timeout); 2088 return 0; 2089 } else if (le16_to_cpu(cmd_resp->status) == 2090 LIBIE_AQ_RES_GLBL_IN_PROG) { 2091 *timeout = le32_to_cpu(cmd_resp->timeout); 2092 return -EIO; 2093 } else if (le16_to_cpu(cmd_resp->status) == 2094 LIBIE_AQ_RES_GLBL_DONE) { 2095 return -EALREADY; 2096 } 2097 2098 /* invalid FW response, force a timeout immediately */ 2099 *timeout = 0; 2100 return -EIO; 2101 } 2102 2103 /* If the resource is held by some other driver, the command completes 2104 * with a busy return value and the timeout field indicates the maximum 2105 * time the current owner of the resource has to free it. 2106 */ 2107 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2108 *timeout = le32_to_cpu(cmd_resp->timeout); 2109 2110 return status; 2111 } 2112 2113 /** 2114 * ice_aq_release_res 2115 * @hw: pointer to the HW struct 2116 * @res: resource ID 2117 * @sdp_number: resource number 2118 * @cd: pointer to command details structure or NULL 2119 * 2120 * release common resource using the admin queue commands (0x0009) 2121 */ 2122 static int 2123 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2124 struct ice_sq_cd *cd) 2125 { 2126 struct libie_aqc_req_res *cmd; 2127 struct libie_aq_desc desc; 2128 2129 cmd = &desc.params.res_owner; 2130 2131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2132 2133 cmd->res_id = cpu_to_le16(res); 2134 cmd->res_number = cpu_to_le32(sdp_number); 2135 2136 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2137 } 2138 2139 /** 2140 * ice_acquire_res 2141 * @hw: pointer to the HW structure 2142 * @res: resource ID 2143 * @access: access type (read or write) 2144 * @timeout: timeout in milliseconds 2145 * 2146 * This function will attempt to acquire the ownership of a resource. 2147 */ 2148 int 2149 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2150 enum ice_aq_res_access_type access, u32 timeout) 2151 { 2152 #define ICE_RES_POLLING_DELAY_MS 10 2153 u32 delay = ICE_RES_POLLING_DELAY_MS; 2154 u32 time_left = timeout; 2155 int status; 2156 2157 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2158 2159 /* A return code of -EALREADY means that another driver has 2160 * previously acquired the resource and performed any necessary updates; 2161 * in this case the caller does not obtain the resource and has no 2162 * further work to do. 2163 */ 2164 if (status == -EALREADY) 2165 goto ice_acquire_res_exit; 2166 2167 if (status) 2168 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2169 2170 /* If necessary, poll until the current lock owner timeouts */ 2171 timeout = time_left; 2172 while (status && timeout && time_left) { 2173 mdelay(delay); 2174 timeout = (timeout > delay) ? timeout - delay : 0; 2175 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2176 2177 if (status == -EALREADY) 2178 /* lock free, but no work to do */ 2179 break; 2180 2181 if (!status) 2182 /* lock acquired */ 2183 break; 2184 } 2185 if (status && status != -EALREADY) 2186 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2187 2188 ice_acquire_res_exit: 2189 if (status == -EALREADY) { 2190 if (access == ICE_RES_WRITE) 2191 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2192 else 2193 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2194 } 2195 return status; 2196 } 2197 2198 /** 2199 * ice_release_res 2200 * @hw: pointer to the HW structure 2201 * @res: resource ID 2202 * 2203 * This function will release a resource using the proper Admin Command. 2204 */ 2205 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2206 { 2207 unsigned long timeout; 2208 int status; 2209 2210 /* there are some rare cases when trying to release the resource 2211 * results in an admin queue timeout, so handle them correctly 2212 */ 2213 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2214 do { 2215 status = ice_aq_release_res(hw, res, 0, NULL); 2216 if (status != -EIO) 2217 break; 2218 usleep_range(1000, 2000); 2219 } while (time_before(jiffies, timeout)); 2220 } 2221 2222 /** 2223 * ice_aq_alloc_free_res - command to allocate/free resources 2224 * @hw: pointer to the HW struct 2225 * @buf: Indirect buffer to hold data parameters and response 2226 * @buf_size: size of buffer for indirect commands 2227 * @opc: pass in the command opcode 2228 * 2229 * Helper function to allocate/free resources using the admin queue commands 2230 */ 2231 int ice_aq_alloc_free_res(struct ice_hw *hw, 2232 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2233 enum ice_adminq_opc opc) 2234 { 2235 struct ice_aqc_alloc_free_res_cmd *cmd; 2236 struct libie_aq_desc desc; 2237 2238 cmd = libie_aq_raw(&desc); 2239 2240 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2241 return -EINVAL; 2242 2243 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2244 2245 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2246 2247 cmd->num_entries = cpu_to_le16(1); 2248 2249 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2250 } 2251 2252 /** 2253 * ice_alloc_hw_res - allocate resource 2254 * @hw: pointer to the HW struct 2255 * @type: type of resource 2256 * @num: number of resources to allocate 2257 * @btm: allocate from bottom 2258 * @res: pointer to array that will receive the resources 2259 */ 2260 int 2261 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2262 { 2263 struct ice_aqc_alloc_free_res_elem *buf; 2264 u16 buf_len; 2265 int status; 2266 2267 buf_len = struct_size(buf, elem, num); 2268 buf = kzalloc(buf_len, GFP_KERNEL); 2269 if (!buf) 2270 return -ENOMEM; 2271 2272 /* Prepare buffer to allocate resource. */ 2273 buf->num_elems = cpu_to_le16(num); 2274 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2275 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2276 if (btm) 2277 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2278 2279 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2280 if (status) 2281 goto ice_alloc_res_exit; 2282 2283 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2284 2285 ice_alloc_res_exit: 2286 kfree(buf); 2287 return status; 2288 } 2289 2290 /** 2291 * ice_free_hw_res - free allocated HW resource 2292 * @hw: pointer to the HW struct 2293 * @type: type of resource to free 2294 * @num: number of resources 2295 * @res: pointer to array that contains the resources to free 2296 */ 2297 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2298 { 2299 struct ice_aqc_alloc_free_res_elem *buf; 2300 u16 buf_len; 2301 int status; 2302 2303 buf_len = struct_size(buf, elem, num); 2304 buf = kzalloc(buf_len, GFP_KERNEL); 2305 if (!buf) 2306 return -ENOMEM; 2307 2308 /* Prepare buffer to free resource. */ 2309 buf->num_elems = cpu_to_le16(num); 2310 buf->res_type = cpu_to_le16(type); 2311 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2312 2313 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2314 if (status) 2315 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2316 2317 kfree(buf); 2318 return status; 2319 } 2320 2321 /** 2322 * ice_get_num_per_func - determine number of resources per PF 2323 * @hw: pointer to the HW structure 2324 * @max: value to be evenly split between each PF 2325 * 2326 * Determine the number of valid functions by going through the bitmap returned 2327 * from parsing capabilities and use this to calculate the number of resources 2328 * per PF based on the max value passed in. 2329 */ 2330 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2331 { 2332 u8 funcs; 2333 2334 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2335 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2336 ICE_CAPS_VALID_FUNCS_M); 2337 2338 if (!funcs) 2339 return 0; 2340 2341 return max / funcs; 2342 } 2343 2344 /** 2345 * ice_parse_common_caps - parse common device/function capabilities 2346 * @hw: pointer to the HW struct 2347 * @caps: pointer to common capabilities structure 2348 * @elem: the capability element to parse 2349 * @prefix: message prefix for tracing capabilities 2350 * 2351 * Given a capability element, extract relevant details into the common 2352 * capability structure. 2353 * 2354 * Returns: true if the capability matches one of the common capability ids, 2355 * false otherwise. 2356 */ 2357 static bool 2358 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2359 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2360 { 2361 u32 logical_id = le32_to_cpu(elem->logical_id); 2362 u32 phys_id = le32_to_cpu(elem->phys_id); 2363 u32 number = le32_to_cpu(elem->number); 2364 u16 cap = le16_to_cpu(elem->cap); 2365 bool found = true; 2366 2367 switch (cap) { 2368 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2369 caps->valid_functions = number; 2370 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2371 caps->valid_functions); 2372 break; 2373 case LIBIE_AQC_CAPS_SRIOV: 2374 caps->sr_iov_1_1 = (number == 1); 2375 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2376 caps->sr_iov_1_1); 2377 break; 2378 case LIBIE_AQC_CAPS_DCB: 2379 caps->dcb = (number == 1); 2380 caps->active_tc_bitmap = logical_id; 2381 caps->maxtc = phys_id; 2382 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2383 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2384 caps->active_tc_bitmap); 2385 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2386 break; 2387 case LIBIE_AQC_CAPS_RSS: 2388 caps->rss_table_size = number; 2389 caps->rss_table_entry_width = logical_id; 2390 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2391 caps->rss_table_size); 2392 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2393 caps->rss_table_entry_width); 2394 break; 2395 case LIBIE_AQC_CAPS_RXQS: 2396 caps->num_rxq = number; 2397 caps->rxq_first_id = phys_id; 2398 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2399 caps->num_rxq); 2400 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2401 caps->rxq_first_id); 2402 break; 2403 case LIBIE_AQC_CAPS_TXQS: 2404 caps->num_txq = number; 2405 caps->txq_first_id = phys_id; 2406 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2407 caps->num_txq); 2408 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2409 caps->txq_first_id); 2410 break; 2411 case LIBIE_AQC_CAPS_MSIX: 2412 caps->num_msix_vectors = number; 2413 caps->msix_vector_first_id = phys_id; 2414 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2415 caps->num_msix_vectors); 2416 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2417 caps->msix_vector_first_id); 2418 break; 2419 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2420 caps->nvm_update_pending_nvm = true; 2421 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2422 break; 2423 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2424 caps->nvm_update_pending_orom = true; 2425 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2426 break; 2427 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2428 caps->nvm_update_pending_netlist = true; 2429 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2430 break; 2431 case LIBIE_AQC_CAPS_NVM_MGMT: 2432 caps->nvm_unified_update = 2433 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2434 true : false; 2435 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2436 caps->nvm_unified_update); 2437 break; 2438 case LIBIE_AQC_CAPS_RDMA: 2439 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2440 caps->rdma = (number == 1); 2441 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2442 break; 2443 case LIBIE_AQC_CAPS_MAX_MTU: 2444 caps->max_mtu = number; 2445 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2446 prefix, caps->max_mtu); 2447 break; 2448 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2449 caps->pcie_reset_avoidance = (number > 0); 2450 ice_debug(hw, ICE_DBG_INIT, 2451 "%s: pcie_reset_avoidance = %d\n", prefix, 2452 caps->pcie_reset_avoidance); 2453 break; 2454 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2455 caps->reset_restrict_support = (number == 1); 2456 ice_debug(hw, ICE_DBG_INIT, 2457 "%s: reset_restrict_support = %d\n", prefix, 2458 caps->reset_restrict_support); 2459 break; 2460 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2461 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2462 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2463 prefix, caps->roce_lag); 2464 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2465 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2466 prefix, caps->sriov_lag); 2467 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2468 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2469 prefix, caps->sriov_aa_lag); 2470 break; 2471 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2472 caps->tx_sched_topo_comp_mode_en = (number == 1); 2473 break; 2474 default: 2475 /* Not one of the recognized common capabilities */ 2476 found = false; 2477 } 2478 2479 return found; 2480 } 2481 2482 /** 2483 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2484 * @hw: pointer to the HW structure 2485 * @caps: pointer to capabilities structure to fix 2486 * 2487 * Re-calculate the capabilities that are dependent on the number of physical 2488 * ports; i.e. some features are not supported or function differently on 2489 * devices with more than 4 ports. 2490 */ 2491 static void 2492 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2493 { 2494 /* This assumes device capabilities are always scanned before function 2495 * capabilities during the initialization flow. 2496 */ 2497 if (hw->dev_caps.num_funcs > 4) { 2498 /* Max 4 TCs per port */ 2499 caps->maxtc = 4; 2500 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2501 caps->maxtc); 2502 if (caps->rdma) { 2503 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2504 caps->rdma = 0; 2505 } 2506 2507 /* print message only when processing device capabilities 2508 * during initialization. 2509 */ 2510 if (caps == &hw->dev_caps.common_cap) 2511 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2512 } 2513 } 2514 2515 /** 2516 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2517 * @hw: pointer to the HW struct 2518 * @func_p: pointer to function capabilities structure 2519 * @cap: pointer to the capability element to parse 2520 * 2521 * Extract function capabilities for ICE_AQC_CAPS_VF. 2522 */ 2523 static void 2524 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2525 struct libie_aqc_list_caps_elem *cap) 2526 { 2527 u32 logical_id = le32_to_cpu(cap->logical_id); 2528 u32 number = le32_to_cpu(cap->number); 2529 2530 func_p->num_allocd_vfs = number; 2531 func_p->vf_base_id = logical_id; 2532 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2533 func_p->num_allocd_vfs); 2534 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2535 func_p->vf_base_id); 2536 } 2537 2538 /** 2539 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2540 * @hw: pointer to the HW struct 2541 * @func_p: pointer to function capabilities structure 2542 * @cap: pointer to the capability element to parse 2543 * 2544 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2545 */ 2546 static void 2547 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2548 struct libie_aqc_list_caps_elem *cap) 2549 { 2550 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2551 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2552 le32_to_cpu(cap->number)); 2553 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2554 func_p->guar_num_vsi); 2555 } 2556 2557 /** 2558 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2559 * @hw: pointer to the HW struct 2560 * @func_p: pointer to function capabilities structure 2561 * @cap: pointer to the capability element to parse 2562 * 2563 * Extract function capabilities for ICE_AQC_CAPS_1588. 2564 */ 2565 static void 2566 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2567 struct libie_aqc_list_caps_elem *cap) 2568 { 2569 struct ice_ts_func_info *info = &func_p->ts_func_info; 2570 u32 number = le32_to_cpu(cap->number); 2571 2572 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2573 func_p->common_cap.ieee_1588 = info->ena; 2574 2575 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2576 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2577 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2578 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2579 2580 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2581 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2582 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2583 } else { 2584 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2585 info->clk_src = ICE_CLK_SRC_TIME_REF; 2586 } 2587 2588 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2589 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2590 } else { 2591 /* Unknown clock frequency, so assume a (probably incorrect) 2592 * default to avoid out-of-bounds look ups of frequency 2593 * related information. 2594 */ 2595 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2596 info->clk_freq); 2597 info->time_ref = ICE_TSPLL_FREQ_25_000; 2598 } 2599 2600 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2601 func_p->common_cap.ieee_1588); 2602 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2603 info->src_tmr_owned); 2604 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2605 info->tmr_ena); 2606 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2607 info->tmr_index_owned); 2608 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2609 info->tmr_index_assoc); 2610 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2611 info->clk_freq); 2612 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2613 info->clk_src); 2614 } 2615 2616 /** 2617 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2618 * @hw: pointer to the HW struct 2619 * @func_p: pointer to function capabilities structure 2620 * 2621 * Extract function capabilities for ICE_AQC_CAPS_FD. 2622 */ 2623 static void 2624 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2625 { 2626 u32 reg_val, gsize, bsize; 2627 2628 reg_val = rd32(hw, GLQF_FD_SIZE); 2629 switch (hw->mac_type) { 2630 case ICE_MAC_E830: 2631 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2632 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2633 break; 2634 case ICE_MAC_E810: 2635 default: 2636 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2637 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2638 } 2639 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2640 func_p->fd_fltr_best_effort = bsize; 2641 2642 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2643 func_p->fd_fltr_guar); 2644 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2645 func_p->fd_fltr_best_effort); 2646 } 2647 2648 /** 2649 * ice_parse_func_caps - Parse function capabilities 2650 * @hw: pointer to the HW struct 2651 * @func_p: pointer to function capabilities structure 2652 * @buf: buffer containing the function capability records 2653 * @cap_count: the number of capabilities 2654 * 2655 * Helper function to parse function (0x000A) capabilities list. For 2656 * capabilities shared between device and function, this relies on 2657 * ice_parse_common_caps. 2658 * 2659 * Loop through the list of provided capabilities and extract the relevant 2660 * data into the function capabilities structured. 2661 */ 2662 static void 2663 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2664 void *buf, u32 cap_count) 2665 { 2666 struct libie_aqc_list_caps_elem *cap_resp; 2667 u32 i; 2668 2669 cap_resp = buf; 2670 2671 memset(func_p, 0, sizeof(*func_p)); 2672 2673 for (i = 0; i < cap_count; i++) { 2674 u16 cap = le16_to_cpu(cap_resp[i].cap); 2675 bool found; 2676 2677 found = ice_parse_common_caps(hw, &func_p->common_cap, 2678 &cap_resp[i], "func caps"); 2679 2680 switch (cap) { 2681 case LIBIE_AQC_CAPS_VF: 2682 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2683 break; 2684 case LIBIE_AQC_CAPS_VSI: 2685 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2686 break; 2687 case LIBIE_AQC_CAPS_1588: 2688 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2689 break; 2690 case LIBIE_AQC_CAPS_FD: 2691 ice_parse_fdir_func_caps(hw, func_p); 2692 break; 2693 default: 2694 /* Don't list common capabilities as unknown */ 2695 if (!found) 2696 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2697 i, cap); 2698 break; 2699 } 2700 } 2701 2702 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2703 } 2704 2705 /** 2706 * ice_func_id_to_logical_id - map from function id to logical pf id 2707 * @active_function_bitmap: active function bitmap 2708 * @pf_id: function number of device 2709 * 2710 * Return: logical PF ID. 2711 */ 2712 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2713 { 2714 u8 logical_id = 0; 2715 u8 i; 2716 2717 for (i = 0; i < pf_id; i++) 2718 if (active_function_bitmap & BIT(i)) 2719 logical_id++; 2720 2721 return logical_id; 2722 } 2723 2724 /** 2725 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2726 * @hw: pointer to the HW struct 2727 * @dev_p: pointer to device capabilities structure 2728 * @cap: capability element to parse 2729 * 2730 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2731 */ 2732 static void 2733 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2734 struct libie_aqc_list_caps_elem *cap) 2735 { 2736 u32 number = le32_to_cpu(cap->number); 2737 2738 dev_p->num_funcs = hweight32(number); 2739 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2740 dev_p->num_funcs); 2741 2742 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2743 } 2744 2745 /** 2746 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2747 * @hw: pointer to the HW struct 2748 * @dev_p: pointer to device capabilities structure 2749 * @cap: capability element to parse 2750 * 2751 * Parse ICE_AQC_CAPS_VF for device capabilities. 2752 */ 2753 static void 2754 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2755 struct libie_aqc_list_caps_elem *cap) 2756 { 2757 u32 number = le32_to_cpu(cap->number); 2758 2759 dev_p->num_vfs_exposed = number; 2760 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2761 dev_p->num_vfs_exposed); 2762 } 2763 2764 /** 2765 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2766 * @hw: pointer to the HW struct 2767 * @dev_p: pointer to device capabilities structure 2768 * @cap: capability element to parse 2769 * 2770 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2771 */ 2772 static void 2773 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2774 struct libie_aqc_list_caps_elem *cap) 2775 { 2776 u32 number = le32_to_cpu(cap->number); 2777 2778 dev_p->num_vsi_allocd_to_host = number; 2779 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2780 dev_p->num_vsi_allocd_to_host); 2781 } 2782 2783 /** 2784 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2785 * @hw: pointer to the HW struct 2786 * @dev_p: pointer to device capabilities structure 2787 * @cap: capability element to parse 2788 * 2789 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2790 */ 2791 static void 2792 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2793 struct libie_aqc_list_caps_elem *cap) 2794 { 2795 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2796 u32 logical_id = le32_to_cpu(cap->logical_id); 2797 u32 phys_id = le32_to_cpu(cap->phys_id); 2798 u32 number = le32_to_cpu(cap->number); 2799 2800 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2801 dev_p->common_cap.ieee_1588 = info->ena; 2802 2803 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2804 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2805 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2806 2807 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2808 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2809 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2810 2811 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2812 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2813 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2814 2815 info->ena_ports = logical_id; 2816 info->tmr_own_map = phys_id; 2817 2818 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2819 dev_p->common_cap.ieee_1588); 2820 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2821 info->tmr0_owner); 2822 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2823 info->tmr0_owned); 2824 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2825 info->tmr0_ena); 2826 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2827 info->tmr1_owner); 2828 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2829 info->tmr1_owned); 2830 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2831 info->tmr1_ena); 2832 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2833 info->ts_ll_read); 2834 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2835 info->ts_ll_int_read); 2836 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2837 info->ll_phy_tmr_update); 2838 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2839 info->ena_ports); 2840 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2841 info->tmr_own_map); 2842 } 2843 2844 /** 2845 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2846 * @hw: pointer to the HW struct 2847 * @dev_p: pointer to device capabilities structure 2848 * @cap: capability element to parse 2849 * 2850 * Parse ICE_AQC_CAPS_FD for device capabilities. 2851 */ 2852 static void 2853 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2854 struct libie_aqc_list_caps_elem *cap) 2855 { 2856 u32 number = le32_to_cpu(cap->number); 2857 2858 dev_p->num_flow_director_fltr = number; 2859 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2860 dev_p->num_flow_director_fltr); 2861 } 2862 2863 /** 2864 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2865 * @hw: pointer to the HW struct 2866 * @dev_p: pointer to device capabilities structure 2867 * @cap: capability element to parse 2868 * 2869 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2870 * enabled sensors. 2871 */ 2872 static void 2873 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2874 struct libie_aqc_list_caps_elem *cap) 2875 { 2876 dev_p->supported_sensors = le32_to_cpu(cap->number); 2877 2878 ice_debug(hw, ICE_DBG_INIT, 2879 "dev caps: supported sensors (bitmap) = 0x%x\n", 2880 dev_p->supported_sensors); 2881 } 2882 2883 /** 2884 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2885 * @hw: pointer to the HW struct 2886 * @dev_p: pointer to device capabilities structure 2887 * @cap: capability element to parse 2888 * 2889 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2890 */ 2891 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2892 struct ice_hw_dev_caps *dev_p, 2893 struct libie_aqc_list_caps_elem *cap) 2894 { 2895 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2896 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2897 2898 dev_info(ice_hw_to_dev(hw), 2899 "PF is configured in %s mode with IP instance ID %d\n", 2900 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2901 "primary" : "secondary", dev_p->nac_topo.id); 2902 2903 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2904 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2905 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2906 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2907 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2908 dev_p->nac_topo.id); 2909 } 2910 2911 /** 2912 * ice_parse_dev_caps - Parse device capabilities 2913 * @hw: pointer to the HW struct 2914 * @dev_p: pointer to device capabilities structure 2915 * @buf: buffer containing the device capability records 2916 * @cap_count: the number of capabilities 2917 * 2918 * Helper device to parse device (0x000B) capabilities list. For 2919 * capabilities shared between device and function, this relies on 2920 * ice_parse_common_caps. 2921 * 2922 * Loop through the list of provided capabilities and extract the relevant 2923 * data into the device capabilities structured. 2924 */ 2925 static void 2926 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2927 void *buf, u32 cap_count) 2928 { 2929 struct libie_aqc_list_caps_elem *cap_resp; 2930 u32 i; 2931 2932 cap_resp = buf; 2933 2934 memset(dev_p, 0, sizeof(*dev_p)); 2935 2936 for (i = 0; i < cap_count; i++) { 2937 u16 cap = le16_to_cpu(cap_resp[i].cap); 2938 bool found; 2939 2940 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2941 &cap_resp[i], "dev caps"); 2942 2943 switch (cap) { 2944 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2945 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2946 break; 2947 case LIBIE_AQC_CAPS_VF: 2948 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2949 break; 2950 case LIBIE_AQC_CAPS_VSI: 2951 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2952 break; 2953 case LIBIE_AQC_CAPS_1588: 2954 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2955 break; 2956 case LIBIE_AQC_CAPS_FD: 2957 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2958 break; 2959 case LIBIE_AQC_CAPS_SENSOR_READING: 2960 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2961 break; 2962 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2963 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2964 break; 2965 default: 2966 /* Don't list common capabilities as unknown */ 2967 if (!found) 2968 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2969 i, cap); 2970 break; 2971 } 2972 } 2973 2974 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2975 } 2976 2977 /** 2978 * ice_is_phy_rclk_in_netlist 2979 * @hw: pointer to the hw struct 2980 * 2981 * Check if the PHY Recovered Clock device is present in the netlist 2982 */ 2983 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2984 { 2985 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2986 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2987 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2988 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2989 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2990 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2991 return false; 2992 2993 return true; 2994 } 2995 2996 /** 2997 * ice_is_clock_mux_in_netlist 2998 * @hw: pointer to the hw struct 2999 * 3000 * Check if the Clock Multiplexer device is present in the netlist 3001 */ 3002 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3003 { 3004 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3005 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3006 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3007 NULL)) 3008 return false; 3009 3010 return true; 3011 } 3012 3013 /** 3014 * ice_is_cgu_in_netlist - check for CGU presence 3015 * @hw: pointer to the hw struct 3016 * 3017 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3018 * Save the CGU part number in the hw structure for later use. 3019 * Return: 3020 * * true - cgu is present 3021 * * false - cgu is not present 3022 */ 3023 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3024 { 3025 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3026 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3027 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3028 NULL)) { 3029 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3030 return true; 3031 } else if (!ice_find_netlist_node(hw, 3032 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3033 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3034 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3035 NULL)) { 3036 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3037 return true; 3038 } 3039 3040 return false; 3041 } 3042 3043 /** 3044 * ice_is_gps_in_netlist 3045 * @hw: pointer to the hw struct 3046 * 3047 * Check if the GPS generic device is present in the netlist 3048 */ 3049 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3050 { 3051 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3052 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3053 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3054 return false; 3055 3056 return true; 3057 } 3058 3059 /** 3060 * ice_aq_list_caps - query function/device capabilities 3061 * @hw: pointer to the HW struct 3062 * @buf: a buffer to hold the capabilities 3063 * @buf_size: size of the buffer 3064 * @cap_count: if not NULL, set to the number of capabilities reported 3065 * @opc: capabilities type to discover, device or function 3066 * @cd: pointer to command details structure or NULL 3067 * 3068 * Get the function (0x000A) or device (0x000B) capabilities description from 3069 * firmware and store it in the buffer. 3070 * 3071 * If the cap_count pointer is not NULL, then it is set to the number of 3072 * capabilities firmware will report. Note that if the buffer size is too 3073 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3074 * cap_count will still be updated in this case. It is recommended that the 3075 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3076 * firmware could return) to avoid this. 3077 */ 3078 int 3079 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3080 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3081 { 3082 struct libie_aqc_list_caps *cmd; 3083 struct libie_aq_desc desc; 3084 int status; 3085 3086 cmd = &desc.params.get_cap; 3087 3088 if (opc != ice_aqc_opc_list_func_caps && 3089 opc != ice_aqc_opc_list_dev_caps) 3090 return -EINVAL; 3091 3092 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3093 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3094 3095 if (cap_count) 3096 *cap_count = le32_to_cpu(cmd->count); 3097 3098 return status; 3099 } 3100 3101 /** 3102 * ice_discover_dev_caps - Read and extract device capabilities 3103 * @hw: pointer to the hardware structure 3104 * @dev_caps: pointer to device capabilities structure 3105 * 3106 * Read the device capabilities and extract them into the dev_caps structure 3107 * for later use. 3108 */ 3109 int 3110 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3111 { 3112 u32 cap_count = 0; 3113 void *cbuf; 3114 int status; 3115 3116 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3117 if (!cbuf) 3118 return -ENOMEM; 3119 3120 /* Although the driver doesn't know the number of capabilities the 3121 * device will return, we can simply send a 4KB buffer, the maximum 3122 * possible size that firmware can return. 3123 */ 3124 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3125 3126 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3127 ice_aqc_opc_list_dev_caps, NULL); 3128 if (!status) 3129 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3130 kfree(cbuf); 3131 3132 return status; 3133 } 3134 3135 /** 3136 * ice_discover_func_caps - Read and extract function capabilities 3137 * @hw: pointer to the hardware structure 3138 * @func_caps: pointer to function capabilities structure 3139 * 3140 * Read the function capabilities and extract them into the func_caps structure 3141 * for later use. 3142 */ 3143 static int 3144 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3145 { 3146 u32 cap_count = 0; 3147 void *cbuf; 3148 int status; 3149 3150 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3151 if (!cbuf) 3152 return -ENOMEM; 3153 3154 /* Although the driver doesn't know the number of capabilities the 3155 * device will return, we can simply send a 4KB buffer, the maximum 3156 * possible size that firmware can return. 3157 */ 3158 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3159 3160 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3161 ice_aqc_opc_list_func_caps, NULL); 3162 if (!status) 3163 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3164 kfree(cbuf); 3165 3166 return status; 3167 } 3168 3169 /** 3170 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3171 * @hw: pointer to the hardware structure 3172 */ 3173 void ice_set_safe_mode_caps(struct ice_hw *hw) 3174 { 3175 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3176 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3177 struct ice_hw_common_caps cached_caps; 3178 u32 num_funcs; 3179 3180 /* cache some func_caps values that should be restored after memset */ 3181 cached_caps = func_caps->common_cap; 3182 3183 /* unset func capabilities */ 3184 memset(func_caps, 0, sizeof(*func_caps)); 3185 3186 #define ICE_RESTORE_FUNC_CAP(name) \ 3187 func_caps->common_cap.name = cached_caps.name 3188 3189 /* restore cached values */ 3190 ICE_RESTORE_FUNC_CAP(valid_functions); 3191 ICE_RESTORE_FUNC_CAP(txq_first_id); 3192 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3193 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3194 ICE_RESTORE_FUNC_CAP(max_mtu); 3195 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3196 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3197 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3198 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3199 3200 /* one Tx and one Rx queue in safe mode */ 3201 func_caps->common_cap.num_rxq = 1; 3202 func_caps->common_cap.num_txq = 1; 3203 3204 /* two MSIX vectors, one for traffic and one for misc causes */ 3205 func_caps->common_cap.num_msix_vectors = 2; 3206 func_caps->guar_num_vsi = 1; 3207 3208 /* cache some dev_caps values that should be restored after memset */ 3209 cached_caps = dev_caps->common_cap; 3210 num_funcs = dev_caps->num_funcs; 3211 3212 /* unset dev capabilities */ 3213 memset(dev_caps, 0, sizeof(*dev_caps)); 3214 3215 #define ICE_RESTORE_DEV_CAP(name) \ 3216 dev_caps->common_cap.name = cached_caps.name 3217 3218 /* restore cached values */ 3219 ICE_RESTORE_DEV_CAP(valid_functions); 3220 ICE_RESTORE_DEV_CAP(txq_first_id); 3221 ICE_RESTORE_DEV_CAP(rxq_first_id); 3222 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3223 ICE_RESTORE_DEV_CAP(max_mtu); 3224 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3225 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3226 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3227 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3228 dev_caps->num_funcs = num_funcs; 3229 3230 /* one Tx and one Rx queue per function in safe mode */ 3231 dev_caps->common_cap.num_rxq = num_funcs; 3232 dev_caps->common_cap.num_txq = num_funcs; 3233 3234 /* two MSIX vectors per function */ 3235 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3236 } 3237 3238 /** 3239 * ice_get_caps - get info about the HW 3240 * @hw: pointer to the hardware structure 3241 */ 3242 int ice_get_caps(struct ice_hw *hw) 3243 { 3244 int status; 3245 3246 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3247 if (status) 3248 return status; 3249 3250 return ice_discover_func_caps(hw, &hw->func_caps); 3251 } 3252 3253 /** 3254 * ice_aq_manage_mac_write - manage MAC address write command 3255 * @hw: pointer to the HW struct 3256 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3257 * @flags: flags to control write behavior 3258 * @cd: pointer to command details structure or NULL 3259 * 3260 * This function is used to write MAC address to the NVM (0x0108). 3261 */ 3262 int 3263 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3264 struct ice_sq_cd *cd) 3265 { 3266 struct ice_aqc_manage_mac_write *cmd; 3267 struct libie_aq_desc desc; 3268 3269 cmd = libie_aq_raw(&desc); 3270 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3271 3272 cmd->flags = flags; 3273 ether_addr_copy(cmd->mac_addr, mac_addr); 3274 3275 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3276 } 3277 3278 /** 3279 * ice_aq_clear_pxe_mode 3280 * @hw: pointer to the HW struct 3281 * 3282 * Tell the firmware that the driver is taking over from PXE (0x0110). 3283 */ 3284 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3285 { 3286 struct ice_aqc_clear_pxe *cmd; 3287 struct libie_aq_desc desc; 3288 3289 cmd = libie_aq_raw(&desc); 3290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3291 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3292 3293 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3294 } 3295 3296 /** 3297 * ice_clear_pxe_mode - clear pxe operations mode 3298 * @hw: pointer to the HW struct 3299 * 3300 * Make sure all PXE mode settings are cleared, including things 3301 * like descriptor fetch/write-back mode. 3302 */ 3303 void ice_clear_pxe_mode(struct ice_hw *hw) 3304 { 3305 if (ice_check_sq_alive(hw, &hw->adminq)) 3306 ice_aq_clear_pxe_mode(hw); 3307 } 3308 3309 /** 3310 * ice_aq_set_port_params - set physical port parameters. 3311 * @pi: pointer to the port info struct 3312 * @double_vlan: if set double VLAN is enabled 3313 * @cd: pointer to command details structure or NULL 3314 * 3315 * Set Physical port parameters (0x0203) 3316 */ 3317 int 3318 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3319 struct ice_sq_cd *cd) 3320 3321 { 3322 struct ice_aqc_set_port_params *cmd; 3323 struct ice_hw *hw = pi->hw; 3324 struct libie_aq_desc desc; 3325 u16 cmd_flags = 0; 3326 3327 cmd = libie_aq_raw(&desc); 3328 3329 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3330 if (double_vlan) 3331 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3332 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3333 3334 cmd->local_fwd_mode = pi->local_fwd_mode | 3335 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3336 3337 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3338 } 3339 3340 /** 3341 * ice_is_100m_speed_supported 3342 * @hw: pointer to the HW struct 3343 * 3344 * returns true if 100M speeds are supported by the device, 3345 * false otherwise. 3346 */ 3347 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3348 { 3349 switch (hw->device_id) { 3350 case ICE_DEV_ID_E822C_SGMII: 3351 case ICE_DEV_ID_E822L_SGMII: 3352 case ICE_DEV_ID_E823L_1GBE: 3353 case ICE_DEV_ID_E823C_SGMII: 3354 return true; 3355 default: 3356 return false; 3357 } 3358 } 3359 3360 /** 3361 * ice_get_link_speed_based_on_phy_type - returns link speed 3362 * @phy_type_low: lower part of phy_type 3363 * @phy_type_high: higher part of phy_type 3364 * 3365 * This helper function will convert an entry in PHY type structure 3366 * [phy_type_low, phy_type_high] to its corresponding link speed. 3367 * Note: In the structure of [phy_type_low, phy_type_high], there should 3368 * be one bit set, as this function will convert one PHY type to its 3369 * speed. 3370 * 3371 * Return: 3372 * * PHY speed for recognized PHY type 3373 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3374 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3375 */ 3376 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3377 { 3378 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3379 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3380 3381 switch (phy_type_low) { 3382 case ICE_PHY_TYPE_LOW_100BASE_TX: 3383 case ICE_PHY_TYPE_LOW_100M_SGMII: 3384 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3385 break; 3386 case ICE_PHY_TYPE_LOW_1000BASE_T: 3387 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3388 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3389 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3390 case ICE_PHY_TYPE_LOW_1G_SGMII: 3391 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3392 break; 3393 case ICE_PHY_TYPE_LOW_2500BASE_T: 3394 case ICE_PHY_TYPE_LOW_2500BASE_X: 3395 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3396 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3397 break; 3398 case ICE_PHY_TYPE_LOW_5GBASE_T: 3399 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3400 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3401 break; 3402 case ICE_PHY_TYPE_LOW_10GBASE_T: 3403 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3404 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3405 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3406 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3407 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3408 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3409 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3410 break; 3411 case ICE_PHY_TYPE_LOW_25GBASE_T: 3412 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3413 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3414 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3415 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3416 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3417 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3418 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3419 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3420 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3421 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3422 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3423 break; 3424 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3425 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3426 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3427 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3428 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3429 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3430 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3431 break; 3432 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3433 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3434 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3435 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3436 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3437 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3438 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3439 case ICE_PHY_TYPE_LOW_50G_AUI2: 3440 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3441 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3442 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3443 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3444 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3445 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3446 case ICE_PHY_TYPE_LOW_50G_AUI1: 3447 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3448 break; 3449 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3450 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3451 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3452 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3453 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3454 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3455 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3456 case ICE_PHY_TYPE_LOW_100G_AUI4: 3457 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3458 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3459 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3460 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3461 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3462 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3463 break; 3464 default: 3465 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3466 break; 3467 } 3468 3469 switch (phy_type_high) { 3470 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3471 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3472 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3473 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3474 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3475 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3476 break; 3477 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3478 case ICE_PHY_TYPE_HIGH_200G_SR4: 3479 case ICE_PHY_TYPE_HIGH_200G_FR4: 3480 case ICE_PHY_TYPE_HIGH_200G_LR4: 3481 case ICE_PHY_TYPE_HIGH_200G_DR4: 3482 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3483 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3484 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3485 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3486 break; 3487 default: 3488 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3489 break; 3490 } 3491 3492 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3493 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3494 return ICE_AQ_LINK_SPEED_UNKNOWN; 3495 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3496 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3497 return ICE_AQ_LINK_SPEED_UNKNOWN; 3498 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3499 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3500 return speed_phy_type_low; 3501 else 3502 return speed_phy_type_high; 3503 } 3504 3505 /** 3506 * ice_update_phy_type 3507 * @phy_type_low: pointer to the lower part of phy_type 3508 * @phy_type_high: pointer to the higher part of phy_type 3509 * @link_speeds_bitmap: targeted link speeds bitmap 3510 * 3511 * Note: For the link_speeds_bitmap structure, you can check it at 3512 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3513 * link_speeds_bitmap include multiple speeds. 3514 * 3515 * Each entry in this [phy_type_low, phy_type_high] structure will 3516 * present a certain link speed. This helper function will turn on bits 3517 * in [phy_type_low, phy_type_high] structure based on the value of 3518 * link_speeds_bitmap input parameter. 3519 */ 3520 void 3521 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3522 u16 link_speeds_bitmap) 3523 { 3524 u64 pt_high; 3525 u64 pt_low; 3526 int index; 3527 u16 speed; 3528 3529 /* We first check with low part of phy_type */ 3530 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3531 pt_low = BIT_ULL(index); 3532 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3533 3534 if (link_speeds_bitmap & speed) 3535 *phy_type_low |= BIT_ULL(index); 3536 } 3537 3538 /* We then check with high part of phy_type */ 3539 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3540 pt_high = BIT_ULL(index); 3541 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3542 3543 if (link_speeds_bitmap & speed) 3544 *phy_type_high |= BIT_ULL(index); 3545 } 3546 } 3547 3548 /** 3549 * ice_aq_set_phy_cfg 3550 * @hw: pointer to the HW struct 3551 * @pi: port info structure of the interested logical port 3552 * @cfg: structure with PHY configuration data to be set 3553 * @cd: pointer to command details structure or NULL 3554 * 3555 * Set the various PHY configuration parameters supported on the Port. 3556 * One or more of the Set PHY config parameters may be ignored in an MFP 3557 * mode as the PF may not have the privilege to set some of the PHY Config 3558 * parameters. This status will be indicated by the command response (0x0601). 3559 */ 3560 int 3561 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3562 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3563 { 3564 struct ice_aqc_set_phy_cfg *cmd; 3565 struct libie_aq_desc desc; 3566 int status; 3567 3568 if (!cfg) 3569 return -EINVAL; 3570 3571 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3572 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3573 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3574 cfg->caps); 3575 3576 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3577 } 3578 3579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3580 cmd = libie_aq_raw(&desc); 3581 cmd->lport_num = pi->lport; 3582 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3583 3584 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3585 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3586 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3587 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3588 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3589 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3590 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3591 cfg->low_power_ctrl_an); 3592 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3593 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3594 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3595 cfg->link_fec_opt); 3596 3597 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3598 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3599 status = 0; 3600 3601 if (!status) 3602 pi->phy.curr_user_phy_cfg = *cfg; 3603 3604 return status; 3605 } 3606 3607 /** 3608 * ice_update_link_info - update status of the HW network link 3609 * @pi: port info structure of the interested logical port 3610 */ 3611 int ice_update_link_info(struct ice_port_info *pi) 3612 { 3613 struct ice_link_status *li; 3614 int status; 3615 3616 if (!pi) 3617 return -EINVAL; 3618 3619 li = &pi->phy.link_info; 3620 3621 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3622 if (status) 3623 return status; 3624 3625 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3626 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3627 3628 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3629 if (!pcaps) 3630 return -ENOMEM; 3631 3632 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3633 pcaps, NULL); 3634 } 3635 3636 return status; 3637 } 3638 3639 /** 3640 * ice_aq_get_phy_equalization - function to read serdes equaliser 3641 * value from firmware using admin queue command. 3642 * @hw: pointer to the HW struct 3643 * @data_in: represents the serdes equalization parameter requested 3644 * @op_code: represents the serdes number and flag to represent tx or rx 3645 * @serdes_num: represents the serdes number 3646 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3647 * 3648 * Return: non-zero status on error and 0 on success. 3649 */ 3650 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3651 u8 serdes_num, int *output) 3652 { 3653 struct ice_aqc_dnl_call_command *cmd; 3654 struct ice_aqc_dnl_call buf = {}; 3655 struct libie_aq_desc desc; 3656 int err; 3657 3658 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3659 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3660 cpu_to_le16(op_code | (serdes_num & 0xF)); 3661 cmd = libie_aq_raw(&desc); 3662 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3663 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3664 LIBIE_AQ_FLAG_RD | 3665 LIBIE_AQ_FLAG_SI); 3666 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3667 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3668 3669 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3670 NULL); 3671 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3672 3673 return err; 3674 } 3675 3676 #define FEC_REG_PORT(port) { \ 3677 FEC_CORR_LOW_REG_PORT##port, \ 3678 FEC_CORR_HIGH_REG_PORT##port, \ 3679 FEC_UNCORR_LOW_REG_PORT##port, \ 3680 FEC_UNCORR_HIGH_REG_PORT##port, \ 3681 } 3682 3683 static const u32 fec_reg[][ICE_FEC_MAX] = { 3684 FEC_REG_PORT(0), 3685 FEC_REG_PORT(1), 3686 FEC_REG_PORT(2), 3687 FEC_REG_PORT(3) 3688 }; 3689 3690 /** 3691 * ice_aq_get_fec_stats - reads fec stats from phy 3692 * @hw: pointer to the HW struct 3693 * @pcs_quad: represents pcsquad of user input serdes 3694 * @pcs_port: represents the pcs port number part of above pcs quad 3695 * @fec_type: represents FEC stats type 3696 * @output: pointer to the caller-supplied buffer to return requested fec stats 3697 * 3698 * Return: non-zero status on error and 0 on success. 3699 */ 3700 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3701 enum ice_fec_stats_types fec_type, u32 *output) 3702 { 3703 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3704 struct ice_sbq_msg_input msg = {}; 3705 u32 receiver_id, reg_offset; 3706 int err; 3707 3708 if (pcs_port > 3) 3709 return -EINVAL; 3710 3711 reg_offset = fec_reg[pcs_port][fec_type]; 3712 3713 if (pcs_quad == 0) 3714 receiver_id = FEC_RECEIVER_ID_PCS0; 3715 else if (pcs_quad == 1) 3716 receiver_id = FEC_RECEIVER_ID_PCS1; 3717 else 3718 return -EINVAL; 3719 3720 msg.msg_addr_low = lower_16_bits(reg_offset); 3721 msg.msg_addr_high = receiver_id; 3722 msg.opcode = ice_sbq_msg_rd; 3723 msg.dest_dev = ice_sbq_dev_phy_0; 3724 3725 err = ice_sbq_rw_reg(hw, &msg, flag); 3726 if (err) 3727 return err; 3728 3729 *output = msg.data; 3730 return 0; 3731 } 3732 3733 /** 3734 * ice_cache_phy_user_req 3735 * @pi: port information structure 3736 * @cache_data: PHY logging data 3737 * @cache_mode: PHY logging mode 3738 * 3739 * Log the user request on (FC, FEC, SPEED) for later use. 3740 */ 3741 static void 3742 ice_cache_phy_user_req(struct ice_port_info *pi, 3743 struct ice_phy_cache_mode_data cache_data, 3744 enum ice_phy_cache_mode cache_mode) 3745 { 3746 if (!pi) 3747 return; 3748 3749 switch (cache_mode) { 3750 case ICE_FC_MODE: 3751 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3752 break; 3753 case ICE_SPEED_MODE: 3754 pi->phy.curr_user_speed_req = 3755 cache_data.data.curr_user_speed_req; 3756 break; 3757 case ICE_FEC_MODE: 3758 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3759 break; 3760 default: 3761 break; 3762 } 3763 } 3764 3765 /** 3766 * ice_caps_to_fc_mode 3767 * @caps: PHY capabilities 3768 * 3769 * Convert PHY FC capabilities to ice FC mode 3770 */ 3771 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3772 { 3773 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3774 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3775 return ICE_FC_FULL; 3776 3777 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3778 return ICE_FC_TX_PAUSE; 3779 3780 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3781 return ICE_FC_RX_PAUSE; 3782 3783 return ICE_FC_NONE; 3784 } 3785 3786 /** 3787 * ice_caps_to_fec_mode 3788 * @caps: PHY capabilities 3789 * @fec_options: Link FEC options 3790 * 3791 * Convert PHY FEC capabilities to ice FEC mode 3792 */ 3793 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3794 { 3795 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3796 return ICE_FEC_AUTO; 3797 3798 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3799 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3800 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3801 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3802 return ICE_FEC_BASER; 3803 3804 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3805 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3806 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3807 return ICE_FEC_RS; 3808 3809 return ICE_FEC_NONE; 3810 } 3811 3812 /** 3813 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3814 * @pi: port information structure 3815 * @cfg: PHY configuration data to set FC mode 3816 * @req_mode: FC mode to configure 3817 */ 3818 int 3819 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3820 enum ice_fc_mode req_mode) 3821 { 3822 struct ice_phy_cache_mode_data cache_data; 3823 u8 pause_mask = 0x0; 3824 3825 if (!pi || !cfg) 3826 return -EINVAL; 3827 3828 switch (req_mode) { 3829 case ICE_FC_FULL: 3830 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3831 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3832 break; 3833 case ICE_FC_RX_PAUSE: 3834 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3835 break; 3836 case ICE_FC_TX_PAUSE: 3837 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3838 break; 3839 default: 3840 break; 3841 } 3842 3843 /* clear the old pause settings */ 3844 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3845 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3846 3847 /* set the new capabilities */ 3848 cfg->caps |= pause_mask; 3849 3850 /* Cache user FC request */ 3851 cache_data.data.curr_user_fc_req = req_mode; 3852 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3853 3854 return 0; 3855 } 3856 3857 /** 3858 * ice_set_fc 3859 * @pi: port information structure 3860 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3861 * @ena_auto_link_update: enable automatic link update 3862 * 3863 * Set the requested flow control mode. 3864 */ 3865 int 3866 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3867 { 3868 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3869 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3870 struct ice_hw *hw; 3871 int status; 3872 3873 if (!pi || !aq_failures) 3874 return -EINVAL; 3875 3876 *aq_failures = 0; 3877 hw = pi->hw; 3878 3879 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3880 if (!pcaps) 3881 return -ENOMEM; 3882 3883 /* Get the current PHY config */ 3884 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3885 pcaps, NULL); 3886 if (status) { 3887 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3888 goto out; 3889 } 3890 3891 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3892 3893 /* Configure the set PHY data */ 3894 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3895 if (status) 3896 goto out; 3897 3898 /* If the capabilities have changed, then set the new config */ 3899 if (cfg.caps != pcaps->caps) { 3900 int retry_count, retry_max = 10; 3901 3902 /* Auto restart link so settings take effect */ 3903 if (ena_auto_link_update) 3904 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3905 3906 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3907 if (status) { 3908 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3909 goto out; 3910 } 3911 3912 /* Update the link info 3913 * It sometimes takes a really long time for link to 3914 * come back from the atomic reset. Thus, we wait a 3915 * little bit. 3916 */ 3917 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3918 status = ice_update_link_info(pi); 3919 3920 if (!status) 3921 break; 3922 3923 mdelay(100); 3924 } 3925 3926 if (status) 3927 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3928 } 3929 3930 out: 3931 return status; 3932 } 3933 3934 /** 3935 * ice_phy_caps_equals_cfg 3936 * @phy_caps: PHY capabilities 3937 * @phy_cfg: PHY configuration 3938 * 3939 * Helper function to determine if PHY capabilities matches PHY 3940 * configuration 3941 */ 3942 bool 3943 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3944 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3945 { 3946 u8 caps_mask, cfg_mask; 3947 3948 if (!phy_caps || !phy_cfg) 3949 return false; 3950 3951 /* These bits are not common between capabilities and configuration. 3952 * Do not use them to determine equality. 3953 */ 3954 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3955 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3956 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3957 3958 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3959 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3960 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3961 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3962 phy_caps->eee_cap != phy_cfg->eee_cap || 3963 phy_caps->eeer_value != phy_cfg->eeer_value || 3964 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3965 return false; 3966 3967 return true; 3968 } 3969 3970 /** 3971 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3972 * @pi: port information structure 3973 * @caps: PHY ability structure to copy date from 3974 * @cfg: PHY configuration structure to copy data to 3975 * 3976 * Helper function to copy AQC PHY get ability data to PHY set configuration 3977 * data structure 3978 */ 3979 void 3980 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3981 struct ice_aqc_get_phy_caps_data *caps, 3982 struct ice_aqc_set_phy_cfg_data *cfg) 3983 { 3984 if (!pi || !caps || !cfg) 3985 return; 3986 3987 memset(cfg, 0, sizeof(*cfg)); 3988 cfg->phy_type_low = caps->phy_type_low; 3989 cfg->phy_type_high = caps->phy_type_high; 3990 cfg->caps = caps->caps; 3991 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3992 cfg->eee_cap = caps->eee_cap; 3993 cfg->eeer_value = caps->eeer_value; 3994 cfg->link_fec_opt = caps->link_fec_options; 3995 cfg->module_compliance_enforcement = 3996 caps->module_compliance_enforcement; 3997 } 3998 3999 /** 4000 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4001 * @pi: port information structure 4002 * @cfg: PHY configuration data to set FEC mode 4003 * @fec: FEC mode to configure 4004 */ 4005 int 4006 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4007 enum ice_fec_mode fec) 4008 { 4009 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4010 struct ice_hw *hw; 4011 int status; 4012 4013 if (!pi || !cfg) 4014 return -EINVAL; 4015 4016 hw = pi->hw; 4017 4018 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 4019 if (!pcaps) 4020 return -ENOMEM; 4021 4022 status = ice_aq_get_phy_caps(pi, false, 4023 (ice_fw_supports_report_dflt_cfg(hw) ? 4024 ICE_AQC_REPORT_DFLT_CFG : 4025 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4026 if (status) 4027 goto out; 4028 4029 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4030 cfg->link_fec_opt = pcaps->link_fec_options; 4031 4032 switch (fec) { 4033 case ICE_FEC_BASER: 4034 /* Clear RS bits, and AND BASE-R ability 4035 * bits and OR request bits. 4036 */ 4037 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4038 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4039 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4040 ICE_AQC_PHY_FEC_25G_KR_REQ; 4041 break; 4042 case ICE_FEC_RS: 4043 /* Clear BASE-R bits, and AND RS ability 4044 * bits and OR request bits. 4045 */ 4046 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4047 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4048 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4049 break; 4050 case ICE_FEC_NONE: 4051 /* Clear all FEC option bits. */ 4052 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4053 break; 4054 case ICE_FEC_AUTO: 4055 /* AND auto FEC bit, and all caps bits. */ 4056 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4057 cfg->link_fec_opt |= pcaps->link_fec_options; 4058 break; 4059 default: 4060 status = -EINVAL; 4061 break; 4062 } 4063 4064 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4065 !ice_fw_supports_report_dflt_cfg(hw)) { 4066 struct ice_link_default_override_tlv tlv = { 0 }; 4067 4068 status = ice_get_link_default_override(&tlv, pi); 4069 if (status) 4070 goto out; 4071 4072 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4073 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4074 cfg->link_fec_opt = tlv.fec_options; 4075 } 4076 4077 out: 4078 return status; 4079 } 4080 4081 /** 4082 * ice_get_link_status - get status of the HW network link 4083 * @pi: port information structure 4084 * @link_up: pointer to bool (true/false = linkup/linkdown) 4085 * 4086 * Variable link_up is true if link is up, false if link is down. 4087 * The variable link_up is invalid if status is non zero. As a 4088 * result of this call, link status reporting becomes enabled 4089 */ 4090 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4091 { 4092 struct ice_phy_info *phy_info; 4093 int status = 0; 4094 4095 if (!pi || !link_up) 4096 return -EINVAL; 4097 4098 phy_info = &pi->phy; 4099 4100 if (phy_info->get_link_info) { 4101 status = ice_update_link_info(pi); 4102 4103 if (status) 4104 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4105 status); 4106 } 4107 4108 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4109 4110 return status; 4111 } 4112 4113 /** 4114 * ice_aq_set_link_restart_an 4115 * @pi: pointer to the port information structure 4116 * @ena_link: if true: enable link, if false: disable link 4117 * @cd: pointer to command details structure or NULL 4118 * 4119 * Sets up the link and restarts the Auto-Negotiation over the link. 4120 */ 4121 int 4122 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4123 struct ice_sq_cd *cd) 4124 { 4125 struct ice_aqc_restart_an *cmd; 4126 struct libie_aq_desc desc; 4127 4128 cmd = libie_aq_raw(&desc); 4129 4130 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4131 4132 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4133 cmd->lport_num = pi->lport; 4134 if (ena_link) 4135 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4136 else 4137 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4138 4139 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4140 } 4141 4142 /** 4143 * ice_aq_set_event_mask 4144 * @hw: pointer to the HW struct 4145 * @port_num: port number of the physical function 4146 * @mask: event mask to be set 4147 * @cd: pointer to command details structure or NULL 4148 * 4149 * Set event mask (0x0613) 4150 */ 4151 int 4152 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4153 struct ice_sq_cd *cd) 4154 { 4155 struct ice_aqc_set_event_mask *cmd; 4156 struct libie_aq_desc desc; 4157 4158 cmd = libie_aq_raw(&desc); 4159 4160 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4161 4162 cmd->lport_num = port_num; 4163 4164 cmd->event_mask = cpu_to_le16(mask); 4165 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4166 } 4167 4168 /** 4169 * ice_aq_set_mac_loopback 4170 * @hw: pointer to the HW struct 4171 * @ena_lpbk: Enable or Disable loopback 4172 * @cd: pointer to command details structure or NULL 4173 * 4174 * Enable/disable loopback on a given port 4175 */ 4176 int 4177 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4178 { 4179 struct ice_aqc_set_mac_lb *cmd; 4180 struct libie_aq_desc desc; 4181 4182 cmd = libie_aq_raw(&desc); 4183 4184 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4185 if (ena_lpbk) 4186 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4187 4188 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4189 } 4190 4191 /** 4192 * ice_aq_set_port_id_led 4193 * @pi: pointer to the port information 4194 * @is_orig_mode: is this LED set to original mode (by the net-list) 4195 * @cd: pointer to command details structure or NULL 4196 * 4197 * Set LED value for the given port (0x06e9) 4198 */ 4199 int 4200 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4201 struct ice_sq_cd *cd) 4202 { 4203 struct ice_aqc_set_port_id_led *cmd; 4204 struct ice_hw *hw = pi->hw; 4205 struct libie_aq_desc desc; 4206 4207 cmd = libie_aq_raw(&desc); 4208 4209 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4210 4211 if (is_orig_mode) 4212 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4213 else 4214 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4215 4216 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4217 } 4218 4219 /** 4220 * ice_aq_get_port_options 4221 * @hw: pointer to the HW struct 4222 * @options: buffer for the resultant port options 4223 * @option_count: input - size of the buffer in port options structures, 4224 * output - number of returned port options 4225 * @lport: logical port to call the command with (optional) 4226 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4227 * when PF owns more than 1 port it must be true 4228 * @active_option_idx: index of active port option in returned buffer 4229 * @active_option_valid: active option in returned buffer is valid 4230 * @pending_option_idx: index of pending port option in returned buffer 4231 * @pending_option_valid: pending option in returned buffer is valid 4232 * 4233 * Calls Get Port Options AQC (0x06ea) and verifies result. 4234 */ 4235 int 4236 ice_aq_get_port_options(struct ice_hw *hw, 4237 struct ice_aqc_get_port_options_elem *options, 4238 u8 *option_count, u8 lport, bool lport_valid, 4239 u8 *active_option_idx, bool *active_option_valid, 4240 u8 *pending_option_idx, bool *pending_option_valid) 4241 { 4242 struct ice_aqc_get_port_options *cmd; 4243 struct libie_aq_desc desc; 4244 int status; 4245 u8 i; 4246 4247 /* options buffer shall be able to hold max returned options */ 4248 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4249 return -EINVAL; 4250 4251 cmd = libie_aq_raw(&desc); 4252 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4253 4254 if (lport_valid) 4255 cmd->lport_num = lport; 4256 cmd->lport_num_valid = lport_valid; 4257 4258 status = ice_aq_send_cmd(hw, &desc, options, 4259 *option_count * sizeof(*options), NULL); 4260 if (status) 4261 return status; 4262 4263 /* verify direct FW response & set output parameters */ 4264 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4265 cmd->port_options_count); 4266 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4267 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4268 cmd->port_options); 4269 if (*active_option_valid) { 4270 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4271 cmd->port_options); 4272 if (*active_option_idx > (*option_count - 1)) 4273 return -EIO; 4274 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4275 *active_option_idx); 4276 } 4277 4278 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4279 cmd->pending_port_option_status); 4280 if (*pending_option_valid) { 4281 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4282 cmd->pending_port_option_status); 4283 if (*pending_option_idx > (*option_count - 1)) 4284 return -EIO; 4285 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4286 *pending_option_idx); 4287 } 4288 4289 /* mask output options fields */ 4290 for (i = 0; i < *option_count; i++) { 4291 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4292 options[i].pmd); 4293 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4294 options[i].max_lane_speed); 4295 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4296 options[i].pmd, options[i].max_lane_speed); 4297 } 4298 4299 return 0; 4300 } 4301 4302 /** 4303 * ice_aq_set_port_option 4304 * @hw: pointer to the HW struct 4305 * @lport: logical port to call the command with 4306 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4307 * when PF owns more than 1 port it must be true 4308 * @new_option: new port option to be written 4309 * 4310 * Calls Set Port Options AQC (0x06eb). 4311 */ 4312 int 4313 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4314 u8 new_option) 4315 { 4316 struct ice_aqc_set_port_option *cmd; 4317 struct libie_aq_desc desc; 4318 4319 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4320 return -EINVAL; 4321 4322 cmd = libie_aq_raw(&desc); 4323 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4324 4325 if (lport_valid) 4326 cmd->lport_num = lport; 4327 4328 cmd->lport_num_valid = lport_valid; 4329 cmd->selected_port_option = new_option; 4330 4331 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4332 } 4333 4334 /** 4335 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4336 * @hw: pointer to the hw struct 4337 * 4338 * Return: PHY lane number on success, negative error code otherwise. 4339 */ 4340 int ice_get_phy_lane_number(struct ice_hw *hw) 4341 { 4342 struct ice_aqc_get_port_options_elem *options; 4343 unsigned int lport = 0; 4344 unsigned int lane; 4345 int err; 4346 4347 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4348 if (!options) 4349 return -ENOMEM; 4350 4351 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4352 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4353 u8 speed, active_idx, pending_idx; 4354 bool active_valid, pending_valid; 4355 4356 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4357 true, &active_idx, &active_valid, 4358 &pending_idx, &pending_valid); 4359 if (err) 4360 goto err; 4361 4362 if (!active_valid) 4363 continue; 4364 4365 speed = options[active_idx].max_lane_speed; 4366 /* If we don't get speed for this lane, it's unoccupied */ 4367 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4368 continue; 4369 4370 if (hw->pf_id == lport) { 4371 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4372 ice_is_dual(hw) && !ice_is_primary(hw)) 4373 lane += ICE_PORTS_PER_QUAD; 4374 kfree(options); 4375 return lane; 4376 } 4377 lport++; 4378 } 4379 4380 /* PHY lane not found */ 4381 err = -ENXIO; 4382 err: 4383 kfree(options); 4384 return err; 4385 } 4386 4387 /** 4388 * ice_aq_sff_eeprom 4389 * @hw: pointer to the HW struct 4390 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4391 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4392 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4393 * @page: QSFP page 4394 * @set_page: set or ignore the page 4395 * @data: pointer to data buffer to be read/written to the I2C device. 4396 * @length: 1-16 for read, 1 for write. 4397 * @write: 0 read, 1 for write. 4398 * @cd: pointer to command details structure or NULL 4399 * 4400 * Read/Write SFF EEPROM (0x06EE) 4401 */ 4402 int 4403 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4404 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4405 bool write, struct ice_sq_cd *cd) 4406 { 4407 struct ice_aqc_sff_eeprom *cmd; 4408 struct libie_aq_desc desc; 4409 u16 i2c_bus_addr; 4410 int status; 4411 4412 if (!data || (mem_addr & 0xff00)) 4413 return -EINVAL; 4414 4415 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4416 cmd = libie_aq_raw(&desc); 4417 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4418 cmd->lport_num = (u8)(lport & 0xff); 4419 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4420 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4421 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4422 if (write) 4423 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4424 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4425 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4426 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4427 4428 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4429 return status; 4430 } 4431 4432 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4433 { 4434 switch (type) { 4435 case ICE_LUT_VSI: 4436 return ICE_LUT_VSI_SIZE; 4437 case ICE_LUT_GLOBAL: 4438 return ICE_LUT_GLOBAL_SIZE; 4439 case ICE_LUT_PF: 4440 return ICE_LUT_PF_SIZE; 4441 } 4442 WARN_ONCE(1, "incorrect type passed"); 4443 return ICE_LUT_VSI_SIZE; 4444 } 4445 4446 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4447 { 4448 switch (size) { 4449 case ICE_LUT_VSI_SIZE: 4450 return ICE_AQC_LUT_SIZE_SMALL; 4451 case ICE_LUT_GLOBAL_SIZE: 4452 return ICE_AQC_LUT_SIZE_512; 4453 case ICE_LUT_PF_SIZE: 4454 return ICE_AQC_LUT_SIZE_2K; 4455 } 4456 WARN_ONCE(1, "incorrect size passed"); 4457 return 0; 4458 } 4459 4460 /** 4461 * __ice_aq_get_set_rss_lut 4462 * @hw: pointer to the hardware structure 4463 * @params: RSS LUT parameters 4464 * @set: set true to set the table, false to get the table 4465 * 4466 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4467 */ 4468 static int 4469 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4470 struct ice_aq_get_set_rss_lut_params *params, bool set) 4471 { 4472 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4473 enum ice_lut_type lut_type = params->lut_type; 4474 struct ice_aqc_get_set_rss_lut *desc_params; 4475 enum ice_aqc_lut_flags flags; 4476 enum ice_lut_size lut_size; 4477 struct libie_aq_desc desc; 4478 u8 *lut = params->lut; 4479 4480 4481 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4482 return -EINVAL; 4483 4484 lut_size = ice_lut_type_to_size(lut_type); 4485 if (lut_size > params->lut_size) 4486 return -EINVAL; 4487 else if (set && lut_size != params->lut_size) 4488 return -EINVAL; 4489 4490 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4491 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4492 if (set) 4493 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4494 4495 desc_params = libie_aq_raw(&desc); 4496 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4497 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4498 4499 if (lut_type == ICE_LUT_GLOBAL) 4500 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4501 params->global_lut_id); 4502 4503 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4504 desc_params->flags = cpu_to_le16(flags); 4505 4506 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4507 } 4508 4509 /** 4510 * ice_aq_get_rss_lut 4511 * @hw: pointer to the hardware structure 4512 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4513 * 4514 * get the RSS lookup table, PF or VSI type 4515 */ 4516 int 4517 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4518 { 4519 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4520 } 4521 4522 /** 4523 * ice_aq_set_rss_lut 4524 * @hw: pointer to the hardware structure 4525 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4526 * 4527 * set the RSS lookup table, PF or VSI type 4528 */ 4529 int 4530 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4531 { 4532 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4533 } 4534 4535 /** 4536 * __ice_aq_get_set_rss_key 4537 * @hw: pointer to the HW struct 4538 * @vsi_id: VSI FW index 4539 * @key: pointer to key info struct 4540 * @set: set true to set the key, false to get the key 4541 * 4542 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4543 */ 4544 static int 4545 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4546 struct ice_aqc_get_set_rss_keys *key, bool set) 4547 { 4548 struct ice_aqc_get_set_rss_key *desc_params; 4549 u16 key_size = sizeof(*key); 4550 struct libie_aq_desc desc; 4551 4552 if (set) { 4553 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4554 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4555 } else { 4556 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4557 } 4558 4559 desc_params = libie_aq_raw(&desc); 4560 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4561 4562 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4563 } 4564 4565 /** 4566 * ice_aq_get_rss_key 4567 * @hw: pointer to the HW struct 4568 * @vsi_handle: software VSI handle 4569 * @key: pointer to key info struct 4570 * 4571 * get the RSS key per VSI 4572 */ 4573 int 4574 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4575 struct ice_aqc_get_set_rss_keys *key) 4576 { 4577 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4578 return -EINVAL; 4579 4580 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4581 key, false); 4582 } 4583 4584 /** 4585 * ice_aq_set_rss_key 4586 * @hw: pointer to the HW struct 4587 * @vsi_handle: software VSI handle 4588 * @keys: pointer to key info struct 4589 * 4590 * set the RSS key per VSI 4591 */ 4592 int 4593 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4594 struct ice_aqc_get_set_rss_keys *keys) 4595 { 4596 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4597 return -EINVAL; 4598 4599 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4600 keys, true); 4601 } 4602 4603 /** 4604 * ice_aq_add_lan_txq 4605 * @hw: pointer to the hardware structure 4606 * @num_qgrps: Number of added queue groups 4607 * @qg_list: list of queue groups to be added 4608 * @buf_size: size of buffer for indirect command 4609 * @cd: pointer to command details structure or NULL 4610 * 4611 * Add Tx LAN queue (0x0C30) 4612 * 4613 * NOTE: 4614 * Prior to calling add Tx LAN queue: 4615 * Initialize the following as part of the Tx queue context: 4616 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4617 * Cache profile and Packet shaper profile. 4618 * 4619 * After add Tx LAN queue AQ command is completed: 4620 * Interrupts should be associated with specific queues, 4621 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4622 * flow. 4623 */ 4624 static int 4625 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4626 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4627 struct ice_sq_cd *cd) 4628 { 4629 struct ice_aqc_add_tx_qgrp *list; 4630 struct ice_aqc_add_txqs *cmd; 4631 struct libie_aq_desc desc; 4632 u16 i, sum_size = 0; 4633 4634 cmd = libie_aq_raw(&desc); 4635 4636 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4637 4638 if (!qg_list) 4639 return -EINVAL; 4640 4641 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4642 return -EINVAL; 4643 4644 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4645 sum_size += struct_size(list, txqs, list->num_txqs); 4646 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4647 list->num_txqs); 4648 } 4649 4650 if (buf_size != sum_size) 4651 return -EINVAL; 4652 4653 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4654 4655 cmd->num_qgrps = num_qgrps; 4656 4657 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4658 } 4659 4660 /** 4661 * ice_aq_dis_lan_txq 4662 * @hw: pointer to the hardware structure 4663 * @num_qgrps: number of groups in the list 4664 * @qg_list: the list of groups to disable 4665 * @buf_size: the total size of the qg_list buffer in bytes 4666 * @rst_src: if called due to reset, specifies the reset source 4667 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4668 * @cd: pointer to command details structure or NULL 4669 * 4670 * Disable LAN Tx queue (0x0C31) 4671 */ 4672 static int 4673 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4674 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4675 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4676 struct ice_sq_cd *cd) 4677 { 4678 struct ice_aqc_dis_txq_item *item; 4679 struct ice_aqc_dis_txqs *cmd; 4680 struct libie_aq_desc desc; 4681 u16 vmvf_and_timeout; 4682 u16 i, sz = 0; 4683 int status; 4684 4685 cmd = libie_aq_raw(&desc); 4686 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4687 4688 /* qg_list can be NULL only in VM/VF reset flow */ 4689 if (!qg_list && !rst_src) 4690 return -EINVAL; 4691 4692 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4693 return -EINVAL; 4694 4695 cmd->num_entries = num_qgrps; 4696 4697 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4698 4699 switch (rst_src) { 4700 case ICE_VM_RESET: 4701 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4702 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4703 break; 4704 case ICE_VF_RESET: 4705 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4706 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4707 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4708 ICE_AQC_Q_DIS_VMVF_NUM_M; 4709 break; 4710 case ICE_NO_RESET: 4711 default: 4712 break; 4713 } 4714 4715 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4716 4717 /* flush pipe on time out */ 4718 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4719 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4720 if (!qg_list) 4721 goto do_aq; 4722 4723 /* set RD bit to indicate that command buffer is provided by the driver 4724 * and it needs to be read by the firmware 4725 */ 4726 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4727 4728 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4729 u16 item_size = struct_size(item, q_id, item->num_qs); 4730 4731 /* If the num of queues is even, add 2 bytes of padding */ 4732 if ((item->num_qs % 2) == 0) 4733 item_size += 2; 4734 4735 sz += item_size; 4736 4737 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4738 } 4739 4740 if (buf_size != sz) 4741 return -EINVAL; 4742 4743 do_aq: 4744 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4745 if (status) { 4746 if (!qg_list) 4747 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4748 vmvf_num, hw->adminq.sq_last_status); 4749 else 4750 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4751 le16_to_cpu(qg_list[0].q_id[0]), 4752 hw->adminq.sq_last_status); 4753 } 4754 return status; 4755 } 4756 4757 /** 4758 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4759 * @hw: pointer to the hardware structure 4760 * @buf: buffer for command 4761 * @buf_size: size of buffer in bytes 4762 * @num_qs: number of queues being configured 4763 * @oldport: origination lport 4764 * @newport: destination lport 4765 * @mode: cmd_type for move to use 4766 * @cd: pointer to command details structure or NULL 4767 * 4768 * Move/Configure LAN Tx queue (0x0C32) 4769 * 4770 * Return: Zero on success, associated error code on failure. 4771 */ 4772 int 4773 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4774 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4775 u8 mode, struct ice_sq_cd *cd) 4776 { 4777 struct ice_aqc_cfg_txqs *cmd; 4778 struct libie_aq_desc desc; 4779 int status; 4780 4781 cmd = libie_aq_raw(&desc); 4782 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4783 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4784 4785 if (!buf) 4786 return -EINVAL; 4787 4788 cmd->cmd_type = mode; 4789 cmd->num_qs = num_qs; 4790 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4791 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4792 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4793 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4794 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4795 cmd->blocked_cgds = 0; 4796 4797 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4798 if (status) 4799 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4800 hw->adminq.sq_last_status); 4801 return status; 4802 } 4803 4804 /** 4805 * ice_aq_add_rdma_qsets 4806 * @hw: pointer to the hardware structure 4807 * @num_qset_grps: Number of RDMA Qset groups 4808 * @qset_list: list of Qset groups to be added 4809 * @buf_size: size of buffer for indirect command 4810 * @cd: pointer to command details structure or NULL 4811 * 4812 * Add Tx RDMA Qsets (0x0C33) 4813 */ 4814 static int 4815 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4816 struct ice_aqc_add_rdma_qset_data *qset_list, 4817 u16 buf_size, struct ice_sq_cd *cd) 4818 { 4819 struct ice_aqc_add_rdma_qset_data *list; 4820 struct ice_aqc_add_rdma_qset *cmd; 4821 struct libie_aq_desc desc; 4822 u16 i, sum_size = 0; 4823 4824 cmd = libie_aq_raw(&desc); 4825 4826 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4827 4828 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4829 return -EINVAL; 4830 4831 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4832 u16 num_qsets = le16_to_cpu(list->num_qsets); 4833 4834 sum_size += struct_size(list, rdma_qsets, num_qsets); 4835 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4836 num_qsets); 4837 } 4838 4839 if (buf_size != sum_size) 4840 return -EINVAL; 4841 4842 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4843 4844 cmd->num_qset_grps = num_qset_grps; 4845 4846 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4847 } 4848 4849 /* End of FW Admin Queue command wrappers */ 4850 4851 /** 4852 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4853 * @hw: pointer to the HW struct 4854 * @vsi_handle: software VSI handle 4855 * @tc: TC number 4856 * @q_handle: software queue handle 4857 */ 4858 struct ice_q_ctx * 4859 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4860 { 4861 struct ice_vsi_ctx *vsi; 4862 struct ice_q_ctx *q_ctx; 4863 4864 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4865 if (!vsi) 4866 return NULL; 4867 if (q_handle >= vsi->num_lan_q_entries[tc]) 4868 return NULL; 4869 if (!vsi->lan_q_ctx[tc]) 4870 return NULL; 4871 q_ctx = vsi->lan_q_ctx[tc]; 4872 return &q_ctx[q_handle]; 4873 } 4874 4875 /** 4876 * ice_ena_vsi_txq 4877 * @pi: port information structure 4878 * @vsi_handle: software VSI handle 4879 * @tc: TC number 4880 * @q_handle: software queue handle 4881 * @num_qgrps: Number of added queue groups 4882 * @buf: list of queue groups to be added 4883 * @buf_size: size of buffer for indirect command 4884 * @cd: pointer to command details structure or NULL 4885 * 4886 * This function adds one LAN queue 4887 */ 4888 int 4889 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4890 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4891 struct ice_sq_cd *cd) 4892 { 4893 struct ice_aqc_txsched_elem_data node = { 0 }; 4894 struct ice_sched_node *parent; 4895 struct ice_q_ctx *q_ctx; 4896 struct ice_hw *hw; 4897 int status; 4898 4899 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4900 return -EIO; 4901 4902 if (num_qgrps > 1 || buf->num_txqs > 1) 4903 return -ENOSPC; 4904 4905 hw = pi->hw; 4906 4907 if (!ice_is_vsi_valid(hw, vsi_handle)) 4908 return -EINVAL; 4909 4910 mutex_lock(&pi->sched_lock); 4911 4912 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4913 if (!q_ctx) { 4914 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4915 q_handle); 4916 status = -EINVAL; 4917 goto ena_txq_exit; 4918 } 4919 4920 /* find a parent node */ 4921 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4922 ICE_SCHED_NODE_OWNER_LAN); 4923 if (!parent) { 4924 status = -EINVAL; 4925 goto ena_txq_exit; 4926 } 4927 4928 buf->parent_teid = parent->info.node_teid; 4929 node.parent_teid = parent->info.node_teid; 4930 /* Mark that the values in the "generic" section as valid. The default 4931 * value in the "generic" section is zero. This means that : 4932 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4933 * - 0 priority among siblings, indicated by Bit 1-3. 4934 * - WFQ, indicated by Bit 4. 4935 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4936 * Bit 5-6. 4937 * - Bit 7 is reserved. 4938 * Without setting the generic section as valid in valid_sections, the 4939 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4940 */ 4941 buf->txqs[0].info.valid_sections = 4942 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4943 ICE_AQC_ELEM_VALID_EIR; 4944 buf->txqs[0].info.generic = 0; 4945 buf->txqs[0].info.cir_bw.bw_profile_idx = 4946 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4947 buf->txqs[0].info.cir_bw.bw_alloc = 4948 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4949 buf->txqs[0].info.eir_bw.bw_profile_idx = 4950 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4951 buf->txqs[0].info.eir_bw.bw_alloc = 4952 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4953 4954 /* add the LAN queue */ 4955 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4956 if (status) { 4957 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4958 le16_to_cpu(buf->txqs[0].txq_id), 4959 hw->adminq.sq_last_status); 4960 goto ena_txq_exit; 4961 } 4962 4963 node.node_teid = buf->txqs[0].q_teid; 4964 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4965 q_ctx->q_handle = q_handle; 4966 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4967 4968 /* add a leaf node into scheduler tree queue layer */ 4969 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4970 if (!status) 4971 status = ice_sched_replay_q_bw(pi, q_ctx); 4972 4973 ena_txq_exit: 4974 mutex_unlock(&pi->sched_lock); 4975 return status; 4976 } 4977 4978 /** 4979 * ice_dis_vsi_txq 4980 * @pi: port information structure 4981 * @vsi_handle: software VSI handle 4982 * @tc: TC number 4983 * @num_queues: number of queues 4984 * @q_handles: pointer to software queue handle array 4985 * @q_ids: pointer to the q_id array 4986 * @q_teids: pointer to queue node teids 4987 * @rst_src: if called due to reset, specifies the reset source 4988 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4989 * @cd: pointer to command details structure or NULL 4990 * 4991 * This function removes queues and their corresponding nodes in SW DB 4992 */ 4993 int 4994 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4995 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4996 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4997 struct ice_sq_cd *cd) 4998 { 4999 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5000 u16 i, buf_size = __struct_size(qg_list); 5001 struct ice_q_ctx *q_ctx; 5002 int status = -ENOENT; 5003 struct ice_hw *hw; 5004 5005 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5006 return -EIO; 5007 5008 hw = pi->hw; 5009 5010 if (!num_queues) { 5011 /* if queue is disabled already yet the disable queue command 5012 * has to be sent to complete the VF reset, then call 5013 * ice_aq_dis_lan_txq without any queue information 5014 */ 5015 if (rst_src) 5016 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5017 vmvf_num, NULL); 5018 return -EIO; 5019 } 5020 5021 mutex_lock(&pi->sched_lock); 5022 5023 for (i = 0; i < num_queues; i++) { 5024 struct ice_sched_node *node; 5025 5026 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5027 if (!node) 5028 continue; 5029 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5030 if (!q_ctx) { 5031 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5032 q_handles[i]); 5033 continue; 5034 } 5035 if (q_ctx->q_handle != q_handles[i]) { 5036 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5037 q_ctx->q_handle, q_handles[i]); 5038 continue; 5039 } 5040 qg_list->parent_teid = node->info.parent_teid; 5041 qg_list->num_qs = 1; 5042 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5043 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5044 vmvf_num, cd); 5045 5046 if (status) 5047 break; 5048 ice_free_sched_node(pi, node); 5049 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5050 q_ctx->q_teid = ICE_INVAL_TEID; 5051 } 5052 mutex_unlock(&pi->sched_lock); 5053 return status; 5054 } 5055 5056 /** 5057 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5058 * @pi: port information structure 5059 * @vsi_handle: software VSI handle 5060 * @tc_bitmap: TC bitmap 5061 * @maxqs: max queues array per TC 5062 * @owner: LAN or RDMA 5063 * 5064 * This function adds/updates the VSI queues per TC. 5065 */ 5066 static int 5067 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5068 u16 *maxqs, u8 owner) 5069 { 5070 int status = 0; 5071 u8 i; 5072 5073 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5074 return -EIO; 5075 5076 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5077 return -EINVAL; 5078 5079 mutex_lock(&pi->sched_lock); 5080 5081 ice_for_each_traffic_class(i) { 5082 /* configuration is possible only if TC node is present */ 5083 if (!ice_sched_get_tc_node(pi, i)) 5084 continue; 5085 5086 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5087 ice_is_tc_ena(tc_bitmap, i)); 5088 if (status) 5089 break; 5090 } 5091 5092 mutex_unlock(&pi->sched_lock); 5093 return status; 5094 } 5095 5096 /** 5097 * ice_cfg_vsi_lan - configure VSI LAN queues 5098 * @pi: port information structure 5099 * @vsi_handle: software VSI handle 5100 * @tc_bitmap: TC bitmap 5101 * @max_lanqs: max LAN queues array per TC 5102 * 5103 * This function adds/updates the VSI LAN queues per TC. 5104 */ 5105 int 5106 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5107 u16 *max_lanqs) 5108 { 5109 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5110 ICE_SCHED_NODE_OWNER_LAN); 5111 } 5112 5113 /** 5114 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5115 * @pi: port information structure 5116 * @vsi_handle: software VSI handle 5117 * @tc_bitmap: TC bitmap 5118 * @max_rdmaqs: max RDMA queues array per TC 5119 * 5120 * This function adds/updates the VSI RDMA queues per TC. 5121 */ 5122 int 5123 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5124 u16 *max_rdmaqs) 5125 { 5126 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5127 ICE_SCHED_NODE_OWNER_RDMA); 5128 } 5129 5130 /** 5131 * ice_ena_vsi_rdma_qset 5132 * @pi: port information structure 5133 * @vsi_handle: software VSI handle 5134 * @tc: TC number 5135 * @rdma_qset: pointer to RDMA Qset 5136 * @num_qsets: number of RDMA Qsets 5137 * @qset_teid: pointer to Qset node TEIDs 5138 * 5139 * This function adds RDMA Qset 5140 */ 5141 int 5142 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5143 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5144 { 5145 struct ice_aqc_txsched_elem_data node = { 0 }; 5146 struct ice_aqc_add_rdma_qset_data *buf; 5147 struct ice_sched_node *parent; 5148 struct ice_hw *hw; 5149 u16 i, buf_size; 5150 int ret; 5151 5152 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5153 return -EIO; 5154 hw = pi->hw; 5155 5156 if (!ice_is_vsi_valid(hw, vsi_handle)) 5157 return -EINVAL; 5158 5159 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5160 buf = kzalloc(buf_size, GFP_KERNEL); 5161 if (!buf) 5162 return -ENOMEM; 5163 mutex_lock(&pi->sched_lock); 5164 5165 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5166 ICE_SCHED_NODE_OWNER_RDMA); 5167 if (!parent) { 5168 ret = -EINVAL; 5169 goto rdma_error_exit; 5170 } 5171 buf->parent_teid = parent->info.node_teid; 5172 node.parent_teid = parent->info.node_teid; 5173 5174 buf->num_qsets = cpu_to_le16(num_qsets); 5175 for (i = 0; i < num_qsets; i++) { 5176 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5177 buf->rdma_qsets[i].info.valid_sections = 5178 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5179 ICE_AQC_ELEM_VALID_EIR; 5180 buf->rdma_qsets[i].info.generic = 0; 5181 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5182 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5183 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5184 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5185 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5186 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5187 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5188 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5189 } 5190 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5191 if (ret) { 5192 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5193 goto rdma_error_exit; 5194 } 5195 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5196 for (i = 0; i < num_qsets; i++) { 5197 node.node_teid = buf->rdma_qsets[i].qset_teid; 5198 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5199 &node, NULL); 5200 if (ret) 5201 break; 5202 qset_teid[i] = le32_to_cpu(node.node_teid); 5203 } 5204 rdma_error_exit: 5205 mutex_unlock(&pi->sched_lock); 5206 kfree(buf); 5207 return ret; 5208 } 5209 5210 /** 5211 * ice_dis_vsi_rdma_qset - free RDMA resources 5212 * @pi: port_info struct 5213 * @count: number of RDMA Qsets to free 5214 * @qset_teid: TEID of Qset node 5215 * @q_id: list of queue IDs being disabled 5216 */ 5217 int 5218 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5219 u16 *q_id) 5220 { 5221 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5222 u16 qg_size = __struct_size(qg_list); 5223 struct ice_hw *hw; 5224 int status = 0; 5225 int i; 5226 5227 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5228 return -EIO; 5229 5230 hw = pi->hw; 5231 5232 mutex_lock(&pi->sched_lock); 5233 5234 for (i = 0; i < count; i++) { 5235 struct ice_sched_node *node; 5236 5237 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5238 if (!node) 5239 continue; 5240 5241 qg_list->parent_teid = node->info.parent_teid; 5242 qg_list->num_qs = 1; 5243 qg_list->q_id[0] = 5244 cpu_to_le16(q_id[i] | 5245 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5246 5247 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5248 ICE_NO_RESET, 0, NULL); 5249 if (status) 5250 break; 5251 5252 ice_free_sched_node(pi, node); 5253 } 5254 5255 mutex_unlock(&pi->sched_lock); 5256 return status; 5257 } 5258 5259 /** 5260 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5261 * @hw: pointer to the HW struct 5262 * @dpll_idx: index of dpll to be measured 5263 * @meas: array to be filled with results 5264 * @meas_num: max number of results array can hold 5265 * 5266 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5267 * pins on given dpll. 5268 * 5269 * Return: 0 on success or negative value on failure. 5270 */ 5271 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5272 struct ice_cgu_input_measure *meas, 5273 u16 meas_num) 5274 { 5275 struct ice_aqc_get_cgu_input_measure *cmd; 5276 struct libie_aq_desc desc; 5277 5278 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5279 cmd = libie_aq_raw(&desc); 5280 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5281 5282 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5283 } 5284 5285 /** 5286 * ice_aq_get_cgu_abilities - get cgu abilities 5287 * @hw: pointer to the HW struct 5288 * @abilities: CGU abilities 5289 * 5290 * Get CGU abilities (0x0C61) 5291 * Return: 0 on success or negative value on failure. 5292 */ 5293 int 5294 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5295 struct ice_aqc_get_cgu_abilities *abilities) 5296 { 5297 struct libie_aq_desc desc; 5298 5299 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5300 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5301 } 5302 5303 /** 5304 * ice_aq_set_input_pin_cfg - set input pin config 5305 * @hw: pointer to the HW struct 5306 * @input_idx: Input index 5307 * @flags1: Input flags 5308 * @flags2: Input flags 5309 * @freq: Frequency in Hz 5310 * @phase_delay: Delay in ps 5311 * 5312 * Set CGU input config (0x0C62) 5313 * Return: 0 on success or negative value on failure. 5314 */ 5315 int 5316 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5317 u32 freq, s32 phase_delay) 5318 { 5319 struct ice_aqc_set_cgu_input_config *cmd; 5320 struct libie_aq_desc desc; 5321 5322 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5323 cmd = libie_aq_raw(&desc); 5324 cmd->input_idx = input_idx; 5325 cmd->flags1 = flags1; 5326 cmd->flags2 = flags2; 5327 cmd->freq = cpu_to_le32(freq); 5328 cmd->phase_delay = cpu_to_le32(phase_delay); 5329 5330 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5331 } 5332 5333 /** 5334 * ice_aq_get_input_pin_cfg - get input pin config 5335 * @hw: pointer to the HW struct 5336 * @input_idx: Input index 5337 * @status: Pin status 5338 * @type: Pin type 5339 * @flags1: Input flags 5340 * @flags2: Input flags 5341 * @freq: Frequency in Hz 5342 * @phase_delay: Delay in ps 5343 * 5344 * Get CGU input config (0x0C63) 5345 * Return: 0 on success or negative value on failure. 5346 */ 5347 int 5348 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5349 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5350 { 5351 struct ice_aqc_get_cgu_input_config *cmd; 5352 struct libie_aq_desc desc; 5353 int ret; 5354 5355 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5356 cmd = libie_aq_raw(&desc); 5357 cmd->input_idx = input_idx; 5358 5359 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5360 if (!ret) { 5361 if (status) 5362 *status = cmd->status; 5363 if (type) 5364 *type = cmd->type; 5365 if (flags1) 5366 *flags1 = cmd->flags1; 5367 if (flags2) 5368 *flags2 = cmd->flags2; 5369 if (freq) 5370 *freq = le32_to_cpu(cmd->freq); 5371 if (phase_delay) 5372 *phase_delay = le32_to_cpu(cmd->phase_delay); 5373 } 5374 5375 return ret; 5376 } 5377 5378 /** 5379 * ice_aq_set_output_pin_cfg - set output pin config 5380 * @hw: pointer to the HW struct 5381 * @output_idx: Output index 5382 * @flags: Output flags 5383 * @src_sel: Index of DPLL block 5384 * @freq: Output frequency 5385 * @phase_delay: Output phase compensation 5386 * 5387 * Set CGU output config (0x0C64) 5388 * Return: 0 on success or negative value on failure. 5389 */ 5390 int 5391 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5392 u8 src_sel, u32 freq, s32 phase_delay) 5393 { 5394 struct ice_aqc_set_cgu_output_config *cmd; 5395 struct libie_aq_desc desc; 5396 5397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5398 cmd = libie_aq_raw(&desc); 5399 cmd->output_idx = output_idx; 5400 cmd->flags = flags; 5401 cmd->src_sel = src_sel; 5402 cmd->freq = cpu_to_le32(freq); 5403 cmd->phase_delay = cpu_to_le32(phase_delay); 5404 5405 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5406 } 5407 5408 /** 5409 * ice_aq_get_output_pin_cfg - get output pin config 5410 * @hw: pointer to the HW struct 5411 * @output_idx: Output index 5412 * @flags: Output flags 5413 * @src_sel: Internal DPLL source 5414 * @freq: Output frequency 5415 * @src_freq: Source frequency 5416 * 5417 * Get CGU output config (0x0C65) 5418 * Return: 0 on success or negative value on failure. 5419 */ 5420 int 5421 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5422 u8 *src_sel, u32 *freq, u32 *src_freq) 5423 { 5424 struct ice_aqc_get_cgu_output_config *cmd; 5425 struct libie_aq_desc desc; 5426 int ret; 5427 5428 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5429 cmd = libie_aq_raw(&desc); 5430 cmd->output_idx = output_idx; 5431 5432 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5433 if (!ret) { 5434 if (flags) 5435 *flags = cmd->flags; 5436 if (src_sel) 5437 *src_sel = cmd->src_sel; 5438 if (freq) 5439 *freq = le32_to_cpu(cmd->freq); 5440 if (src_freq) 5441 *src_freq = le32_to_cpu(cmd->src_freq); 5442 } 5443 5444 return ret; 5445 } 5446 5447 /** 5448 * ice_aq_get_cgu_dpll_status - get dpll status 5449 * @hw: pointer to the HW struct 5450 * @dpll_num: DPLL index 5451 * @ref_state: Reference clock state 5452 * @config: current DPLL config 5453 * @dpll_state: current DPLL state 5454 * @phase_offset: Phase offset in ns 5455 * @eec_mode: EEC_mode 5456 * 5457 * Get CGU DPLL status (0x0C66) 5458 * Return: 0 on success or negative value on failure. 5459 */ 5460 int 5461 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5462 u8 *dpll_state, u8 *config, s64 *phase_offset, 5463 u8 *eec_mode) 5464 { 5465 struct ice_aqc_get_cgu_dpll_status *cmd; 5466 struct libie_aq_desc desc; 5467 int status; 5468 5469 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5470 cmd = libie_aq_raw(&desc); 5471 cmd->dpll_num = dpll_num; 5472 5473 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5474 if (!status) { 5475 *ref_state = cmd->ref_state; 5476 *dpll_state = cmd->dpll_state; 5477 *config = cmd->config; 5478 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5479 *phase_offset <<= 32; 5480 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5481 *phase_offset = sign_extend64(*phase_offset, 47); 5482 *eec_mode = cmd->eec_mode; 5483 } 5484 5485 return status; 5486 } 5487 5488 /** 5489 * ice_aq_set_cgu_dpll_config - set dpll config 5490 * @hw: pointer to the HW struct 5491 * @dpll_num: DPLL index 5492 * @ref_state: Reference clock state 5493 * @config: DPLL config 5494 * @eec_mode: EEC mode 5495 * 5496 * Set CGU DPLL config (0x0C67) 5497 * Return: 0 on success or negative value on failure. 5498 */ 5499 int 5500 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5501 u8 config, u8 eec_mode) 5502 { 5503 struct ice_aqc_set_cgu_dpll_config *cmd; 5504 struct libie_aq_desc desc; 5505 5506 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5507 cmd = libie_aq_raw(&desc); 5508 cmd->dpll_num = dpll_num; 5509 cmd->ref_state = ref_state; 5510 cmd->config = config; 5511 cmd->eec_mode = eec_mode; 5512 5513 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5514 } 5515 5516 /** 5517 * ice_aq_set_cgu_ref_prio - set input reference priority 5518 * @hw: pointer to the HW struct 5519 * @dpll_num: DPLL index 5520 * @ref_idx: Reference pin index 5521 * @ref_priority: Reference input priority 5522 * 5523 * Set CGU reference priority (0x0C68) 5524 * Return: 0 on success or negative value on failure. 5525 */ 5526 int 5527 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5528 u8 ref_priority) 5529 { 5530 struct ice_aqc_set_cgu_ref_prio *cmd; 5531 struct libie_aq_desc desc; 5532 5533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5534 cmd = libie_aq_raw(&desc); 5535 cmd->dpll_num = dpll_num; 5536 cmd->ref_idx = ref_idx; 5537 cmd->ref_priority = ref_priority; 5538 5539 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5540 } 5541 5542 /** 5543 * ice_aq_get_cgu_ref_prio - get input reference priority 5544 * @hw: pointer to the HW struct 5545 * @dpll_num: DPLL index 5546 * @ref_idx: Reference pin index 5547 * @ref_prio: Reference input priority 5548 * 5549 * Get CGU reference priority (0x0C69) 5550 * Return: 0 on success or negative value on failure. 5551 */ 5552 int 5553 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5554 u8 *ref_prio) 5555 { 5556 struct ice_aqc_get_cgu_ref_prio *cmd; 5557 struct libie_aq_desc desc; 5558 int status; 5559 5560 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5561 cmd = libie_aq_raw(&desc); 5562 cmd->dpll_num = dpll_num; 5563 cmd->ref_idx = ref_idx; 5564 5565 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5566 if (!status) 5567 *ref_prio = cmd->ref_priority; 5568 5569 return status; 5570 } 5571 5572 /** 5573 * ice_aq_get_cgu_info - get cgu info 5574 * @hw: pointer to the HW struct 5575 * @cgu_id: CGU ID 5576 * @cgu_cfg_ver: CGU config version 5577 * @cgu_fw_ver: CGU firmware version 5578 * 5579 * Get CGU info (0x0C6A) 5580 * Return: 0 on success or negative value on failure. 5581 */ 5582 int 5583 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5584 u32 *cgu_fw_ver) 5585 { 5586 struct ice_aqc_get_cgu_info *cmd; 5587 struct libie_aq_desc desc; 5588 int status; 5589 5590 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5591 cmd = libie_aq_raw(&desc); 5592 5593 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5594 if (!status) { 5595 *cgu_id = le32_to_cpu(cmd->cgu_id); 5596 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5597 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5598 } 5599 5600 return status; 5601 } 5602 5603 /** 5604 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5605 * @hw: pointer to the HW struct 5606 * @phy_output: PHY reference clock output pin 5607 * @enable: GPIO state to be applied 5608 * @freq: PHY output frequency 5609 * 5610 * Set phy recovered clock as reference (0x0630) 5611 * Return: 0 on success or negative value on failure. 5612 */ 5613 int 5614 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5615 u32 *freq) 5616 { 5617 struct ice_aqc_set_phy_rec_clk_out *cmd; 5618 struct libie_aq_desc desc; 5619 int status; 5620 5621 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5622 cmd = libie_aq_raw(&desc); 5623 cmd->phy_output = phy_output; 5624 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5625 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5626 cmd->freq = cpu_to_le32(*freq); 5627 5628 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5629 if (!status) 5630 *freq = le32_to_cpu(cmd->freq); 5631 5632 return status; 5633 } 5634 5635 /** 5636 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5637 * @hw: pointer to the HW struct 5638 * @phy_output: PHY reference clock output pin 5639 * @port_num: Port number 5640 * @flags: PHY flags 5641 * @node_handle: PHY output frequency 5642 * 5643 * Get PHY recovered clock output info (0x0631) 5644 * Return: 0 on success or negative value on failure. 5645 */ 5646 int 5647 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5648 u8 *flags, u16 *node_handle) 5649 { 5650 struct ice_aqc_get_phy_rec_clk_out *cmd; 5651 struct libie_aq_desc desc; 5652 int status; 5653 5654 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5655 cmd = libie_aq_raw(&desc); 5656 cmd->phy_output = *phy_output; 5657 5658 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5659 if (!status) { 5660 *phy_output = cmd->phy_output; 5661 if (port_num) 5662 *port_num = cmd->port_num; 5663 if (flags) 5664 *flags = cmd->flags; 5665 if (node_handle) 5666 *node_handle = le16_to_cpu(cmd->node_handle); 5667 } 5668 5669 return status; 5670 } 5671 5672 /** 5673 * ice_aq_get_sensor_reading 5674 * @hw: pointer to the HW struct 5675 * @data: pointer to data to be read from the sensor 5676 * 5677 * Get sensor reading (0x0632) 5678 */ 5679 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5680 struct ice_aqc_get_sensor_reading_resp *data) 5681 { 5682 struct ice_aqc_get_sensor_reading *cmd; 5683 struct libie_aq_desc desc; 5684 int status; 5685 5686 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5687 cmd = libie_aq_raw(&desc); 5688 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5689 #define ICE_INTERNAL_TEMP_SENSOR 0 5690 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5691 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5692 5693 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5694 if (!status) 5695 memcpy(data, &desc.params.raw, 5696 sizeof(*data)); 5697 5698 return status; 5699 } 5700 5701 /** 5702 * ice_replay_pre_init - replay pre initialization 5703 * @hw: pointer to the HW struct 5704 * 5705 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5706 */ 5707 static int ice_replay_pre_init(struct ice_hw *hw) 5708 { 5709 struct ice_switch_info *sw = hw->switch_info; 5710 u8 i; 5711 5712 /* Delete old entries from replay filter list head if there is any */ 5713 ice_rm_all_sw_replay_rule_info(hw); 5714 /* In start of replay, move entries into replay_rules list, it 5715 * will allow adding rules entries back to filt_rules list, 5716 * which is operational list. 5717 */ 5718 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5719 list_replace_init(&sw->recp_list[i].filt_rules, 5720 &sw->recp_list[i].filt_replay_rules); 5721 ice_sched_replay_agg_vsi_preinit(hw); 5722 5723 return 0; 5724 } 5725 5726 /** 5727 * ice_replay_vsi - replay VSI configuration 5728 * @hw: pointer to the HW struct 5729 * @vsi_handle: driver VSI handle 5730 * 5731 * Restore all VSI configuration after reset. It is required to call this 5732 * function with main VSI first. 5733 */ 5734 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5735 { 5736 int status; 5737 5738 if (!ice_is_vsi_valid(hw, vsi_handle)) 5739 return -EINVAL; 5740 5741 /* Replay pre-initialization if there is any */ 5742 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5743 status = ice_replay_pre_init(hw); 5744 if (status) 5745 return status; 5746 } 5747 /* Replay per VSI all RSS configurations */ 5748 status = ice_replay_rss_cfg(hw, vsi_handle); 5749 if (status) 5750 return status; 5751 /* Replay per VSI all filters */ 5752 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5753 if (!status) 5754 status = ice_replay_vsi_agg(hw, vsi_handle); 5755 return status; 5756 } 5757 5758 /** 5759 * ice_replay_post - post replay configuration cleanup 5760 * @hw: pointer to the HW struct 5761 * 5762 * Post replay cleanup. 5763 */ 5764 void ice_replay_post(struct ice_hw *hw) 5765 { 5766 /* Delete old entries from replay filter list head */ 5767 ice_rm_all_sw_replay_rule_info(hw); 5768 ice_sched_replay_agg(hw); 5769 } 5770 5771 /** 5772 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5773 * @hw: ptr to the hardware info 5774 * @reg: offset of 64 bit HW register to read from 5775 * @prev_stat_loaded: bool to specify if previous stats are loaded 5776 * @prev_stat: ptr to previous loaded stat value 5777 * @cur_stat: ptr to current stat value 5778 */ 5779 void 5780 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5781 u64 *prev_stat, u64 *cur_stat) 5782 { 5783 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5784 5785 /* device stats are not reset at PFR, they likely will not be zeroed 5786 * when the driver starts. Thus, save the value from the first read 5787 * without adding to the statistic value so that we report stats which 5788 * count up from zero. 5789 */ 5790 if (!prev_stat_loaded) { 5791 *prev_stat = new_data; 5792 return; 5793 } 5794 5795 /* Calculate the difference between the new and old values, and then 5796 * add it to the software stat value. 5797 */ 5798 if (new_data >= *prev_stat) 5799 *cur_stat += new_data - *prev_stat; 5800 else 5801 /* to manage the potential roll-over */ 5802 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5803 5804 /* Update the previously stored value to prepare for next read */ 5805 *prev_stat = new_data; 5806 } 5807 5808 /** 5809 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5810 * @hw: ptr to the hardware info 5811 * @reg: offset of HW register to read from 5812 * @prev_stat_loaded: bool to specify if previous stats are loaded 5813 * @prev_stat: ptr to previous loaded stat value 5814 * @cur_stat: ptr to current stat value 5815 */ 5816 void 5817 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5818 u64 *prev_stat, u64 *cur_stat) 5819 { 5820 u32 new_data; 5821 5822 new_data = rd32(hw, reg); 5823 5824 /* device stats are not reset at PFR, they likely will not be zeroed 5825 * when the driver starts. Thus, save the value from the first read 5826 * without adding to the statistic value so that we report stats which 5827 * count up from zero. 5828 */ 5829 if (!prev_stat_loaded) { 5830 *prev_stat = new_data; 5831 return; 5832 } 5833 5834 /* Calculate the difference between the new and old values, and then 5835 * add it to the software stat value. 5836 */ 5837 if (new_data >= *prev_stat) 5838 *cur_stat += new_data - *prev_stat; 5839 else 5840 /* to manage the potential roll-over */ 5841 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5842 5843 /* Update the previously stored value to prepare for next read */ 5844 *prev_stat = new_data; 5845 } 5846 5847 /** 5848 * ice_sched_query_elem - query element information from HW 5849 * @hw: pointer to the HW struct 5850 * @node_teid: node TEID to be queried 5851 * @buf: buffer to element information 5852 * 5853 * This function queries HW element information 5854 */ 5855 int 5856 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5857 struct ice_aqc_txsched_elem_data *buf) 5858 { 5859 u16 buf_size, num_elem_ret = 0; 5860 int status; 5861 5862 buf_size = sizeof(*buf); 5863 memset(buf, 0, buf_size); 5864 buf->node_teid = cpu_to_le32(node_teid); 5865 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5866 NULL); 5867 if (status || num_elem_ret != 1) 5868 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5869 return status; 5870 } 5871 5872 /** 5873 * ice_aq_read_i2c 5874 * @hw: pointer to the hw struct 5875 * @topo_addr: topology address for a device to communicate with 5876 * @bus_addr: 7-bit I2C bus address 5877 * @addr: I2C memory address (I2C offset) with up to 16 bits 5878 * @params: I2C parameters: bit [7] - Repeated start, 5879 * bits [6:5] data offset size, 5880 * bit [4] - I2C address type, 5881 * bits [3:0] - data size to read (0-16 bytes) 5882 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5883 * @cd: pointer to command details structure or NULL 5884 * 5885 * Read I2C (0x06E2) 5886 */ 5887 int 5888 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5889 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5890 struct ice_sq_cd *cd) 5891 { 5892 struct libie_aq_desc desc = { 0 }; 5893 struct ice_aqc_i2c *cmd; 5894 u8 data_size; 5895 int status; 5896 5897 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5898 cmd = libie_aq_raw(&desc); 5899 5900 if (!data) 5901 return -EINVAL; 5902 5903 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5904 5905 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5906 cmd->topo_addr = topo_addr; 5907 cmd->i2c_params = params; 5908 cmd->i2c_addr = addr; 5909 5910 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5911 if (!status) { 5912 struct ice_aqc_read_i2c_resp *resp; 5913 u8 i; 5914 5915 resp = libie_aq_raw(&desc); 5916 for (i = 0; i < data_size; i++) { 5917 *data = resp->i2c_data[i]; 5918 data++; 5919 } 5920 } 5921 5922 return status; 5923 } 5924 5925 /** 5926 * ice_aq_write_i2c 5927 * @hw: pointer to the hw struct 5928 * @topo_addr: topology address for a device to communicate with 5929 * @bus_addr: 7-bit I2C bus address 5930 * @addr: I2C memory address (I2C offset) with up to 16 bits 5931 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5932 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5933 * @cd: pointer to command details structure or NULL 5934 * 5935 * Write I2C (0x06E3) 5936 * 5937 * * Return: 5938 * * 0 - Successful write to the i2c device 5939 * * -EINVAL - Data size greater than 4 bytes 5940 * * -EIO - FW error 5941 */ 5942 int 5943 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5944 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5945 struct ice_sq_cd *cd) 5946 { 5947 struct libie_aq_desc desc = { 0 }; 5948 struct ice_aqc_i2c *cmd; 5949 u8 data_size; 5950 5951 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5952 cmd = libie_aq_raw(&desc); 5953 5954 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5955 5956 /* data_size limited to 4 */ 5957 if (data_size > 4) 5958 return -EINVAL; 5959 5960 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5961 cmd->topo_addr = topo_addr; 5962 cmd->i2c_params = params; 5963 cmd->i2c_addr = addr; 5964 5965 memcpy(cmd->i2c_data, data, data_size); 5966 5967 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5968 } 5969 5970 /** 5971 * ice_get_pca9575_handle - find and return the PCA9575 controller 5972 * @hw: pointer to the hw struct 5973 * @pca9575_handle: GPIO controller's handle 5974 * 5975 * Find and return the GPIO controller's handle in the netlist. 5976 * When found - the value will be cached in the hw structure and following calls 5977 * will return cached value. 5978 * 5979 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5980 */ 5981 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5982 { 5983 struct ice_aqc_get_link_topo *cmd; 5984 struct libie_aq_desc desc; 5985 int err; 5986 u8 idx; 5987 5988 /* If handle was read previously return cached value */ 5989 if (hw->io_expander_handle) { 5990 *pca9575_handle = hw->io_expander_handle; 5991 return 0; 5992 } 5993 5994 #define SW_PCA9575_SFP_TOPO_IDX 2 5995 #define SW_PCA9575_QSFP_TOPO_IDX 1 5996 5997 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5998 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5999 idx = SW_PCA9575_SFP_TOPO_IDX; 6000 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6001 idx = SW_PCA9575_QSFP_TOPO_IDX; 6002 else 6003 return -ENXIO; 6004 6005 /* If handle was not detected read it from the netlist */ 6006 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6007 cmd = libie_aq_raw(&desc); 6008 cmd->addr.topo_params.node_type_ctx = 6009 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6010 cmd->addr.topo_params.index = idx; 6011 6012 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6013 if (err) 6014 return -ENXIO; 6015 6016 /* Verify if we found the right IO expander type */ 6017 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6018 return -ENXIO; 6019 6020 /* If present save the handle and return it */ 6021 hw->io_expander_handle = 6022 le16_to_cpu(cmd->addr.handle); 6023 *pca9575_handle = hw->io_expander_handle; 6024 6025 return 0; 6026 } 6027 6028 /** 6029 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6030 * @hw: pointer to the hw struct 6031 * @offset: GPIO controller register offset 6032 * @data: pointer to data to be read from the GPIO controller 6033 * 6034 * Return: 0 on success, negative error code otherwise. 6035 */ 6036 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6037 { 6038 struct ice_aqc_link_topo_addr link_topo; 6039 __le16 addr; 6040 u16 handle; 6041 int err; 6042 6043 memset(&link_topo, 0, sizeof(link_topo)); 6044 6045 err = ice_get_pca9575_handle(hw, &handle); 6046 if (err) 6047 return err; 6048 6049 link_topo.handle = cpu_to_le16(handle); 6050 link_topo.topo_params.node_type_ctx = 6051 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6052 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6053 6054 addr = cpu_to_le16((u16)offset); 6055 6056 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6057 } 6058 6059 /** 6060 * ice_aq_set_gpio 6061 * @hw: pointer to the hw struct 6062 * @gpio_ctrl_handle: GPIO controller node handle 6063 * @pin_idx: IO Number of the GPIO that needs to be set 6064 * @value: SW provide IO value to set in the LSB 6065 * @cd: pointer to command details structure or NULL 6066 * 6067 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6068 */ 6069 int 6070 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6071 struct ice_sq_cd *cd) 6072 { 6073 struct libie_aq_desc desc; 6074 struct ice_aqc_gpio *cmd; 6075 6076 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6077 cmd = libie_aq_raw(&desc); 6078 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6079 cmd->gpio_num = pin_idx; 6080 cmd->gpio_val = value ? 1 : 0; 6081 6082 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6083 } 6084 6085 /** 6086 * ice_aq_get_gpio 6087 * @hw: pointer to the hw struct 6088 * @gpio_ctrl_handle: GPIO controller node handle 6089 * @pin_idx: IO Number of the GPIO that needs to be set 6090 * @value: IO value read 6091 * @cd: pointer to command details structure or NULL 6092 * 6093 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6094 * the topology 6095 */ 6096 int 6097 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6098 bool *value, struct ice_sq_cd *cd) 6099 { 6100 struct libie_aq_desc desc; 6101 struct ice_aqc_gpio *cmd; 6102 int status; 6103 6104 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6105 cmd = libie_aq_raw(&desc); 6106 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6107 cmd->gpio_num = pin_idx; 6108 6109 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6110 if (status) 6111 return status; 6112 6113 *value = !!cmd->gpio_val; 6114 return 0; 6115 } 6116 6117 /** 6118 * ice_is_fw_api_min_ver 6119 * @hw: pointer to the hardware structure 6120 * @maj: major version 6121 * @min: minor version 6122 * @patch: patch version 6123 * 6124 * Checks if the firmware API is minimum version 6125 */ 6126 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6127 { 6128 if (hw->api_maj_ver == maj) { 6129 if (hw->api_min_ver > min) 6130 return true; 6131 if (hw->api_min_ver == min && hw->api_patch >= patch) 6132 return true; 6133 } else if (hw->api_maj_ver > maj) { 6134 return true; 6135 } 6136 6137 return false; 6138 } 6139 6140 /** 6141 * ice_fw_supports_link_override 6142 * @hw: pointer to the hardware structure 6143 * 6144 * Checks if the firmware supports link override 6145 */ 6146 bool ice_fw_supports_link_override(struct ice_hw *hw) 6147 { 6148 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6149 ICE_FW_API_LINK_OVERRIDE_MIN, 6150 ICE_FW_API_LINK_OVERRIDE_PATCH); 6151 } 6152 6153 /** 6154 * ice_get_link_default_override 6155 * @ldo: pointer to the link default override struct 6156 * @pi: pointer to the port info struct 6157 * 6158 * Gets the link default override for a port 6159 */ 6160 int 6161 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6162 struct ice_port_info *pi) 6163 { 6164 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6165 struct ice_hw *hw = pi->hw; 6166 int status; 6167 6168 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6169 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6170 if (status) { 6171 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6172 return status; 6173 } 6174 6175 /* Each port has its own config; calculate for our port */ 6176 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6177 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6178 6179 /* link options first */ 6180 status = ice_read_sr_word(hw, tlv_start, &buf); 6181 if (status) { 6182 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6183 return status; 6184 } 6185 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6186 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6187 ICE_LINK_OVERRIDE_PHY_CFG_S; 6188 6189 /* link PHY config */ 6190 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6191 status = ice_read_sr_word(hw, offset, &buf); 6192 if (status) { 6193 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6194 return status; 6195 } 6196 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6197 6198 /* PHY types low */ 6199 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6200 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6201 status = ice_read_sr_word(hw, (offset + i), &buf); 6202 if (status) { 6203 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6204 return status; 6205 } 6206 /* shift 16 bits at a time to fill 64 bits */ 6207 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6208 } 6209 6210 /* PHY types high */ 6211 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6212 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6213 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6214 status = ice_read_sr_word(hw, (offset + i), &buf); 6215 if (status) { 6216 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6217 return status; 6218 } 6219 /* shift 16 bits at a time to fill 64 bits */ 6220 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6221 } 6222 6223 return status; 6224 } 6225 6226 /** 6227 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6228 * @caps: get PHY capability data 6229 */ 6230 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6231 { 6232 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6233 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6234 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6235 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6236 return true; 6237 6238 return false; 6239 } 6240 6241 /** 6242 * ice_is_fw_health_report_supported - checks if firmware supports health events 6243 * @hw: pointer to the hardware structure 6244 * 6245 * Return: true if firmware supports health status reports, 6246 * false otherwise 6247 */ 6248 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6249 { 6250 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6251 ICE_FW_API_HEALTH_REPORT_MIN, 6252 ICE_FW_API_HEALTH_REPORT_PATCH); 6253 } 6254 6255 /** 6256 * ice_aq_set_health_status_cfg - Configure FW health events 6257 * @hw: pointer to the HW struct 6258 * @event_source: type of diagnostic events to enable 6259 * 6260 * Configure the health status event types that the firmware will send to this 6261 * PF. The supported event types are: PF-specific, all PFs, and global. 6262 * 6263 * Return: 0 on success, negative error code otherwise. 6264 */ 6265 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6266 { 6267 struct ice_aqc_set_health_status_cfg *cmd; 6268 struct libie_aq_desc desc; 6269 6270 cmd = libie_aq_raw(&desc); 6271 6272 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6273 6274 cmd->event_source = event_source; 6275 6276 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6277 } 6278 6279 /** 6280 * ice_aq_set_lldp_mib - Set the LLDP MIB 6281 * @hw: pointer to the HW struct 6282 * @mib_type: Local, Remote or both Local and Remote MIBs 6283 * @buf: pointer to the caller-supplied buffer to store the MIB block 6284 * @buf_size: size of the buffer (in bytes) 6285 * @cd: pointer to command details structure or NULL 6286 * 6287 * Set the LLDP MIB. (0x0A08) 6288 */ 6289 int 6290 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6291 struct ice_sq_cd *cd) 6292 { 6293 struct ice_aqc_lldp_set_local_mib *cmd; 6294 struct libie_aq_desc desc; 6295 6296 cmd = libie_aq_raw(&desc); 6297 6298 if (buf_size == 0 || !buf) 6299 return -EINVAL; 6300 6301 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6302 6303 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6304 desc.datalen = cpu_to_le16(buf_size); 6305 6306 cmd->type = mib_type; 6307 cmd->length = cpu_to_le16(buf_size); 6308 6309 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6310 } 6311 6312 /** 6313 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6314 * @hw: pointer to HW struct 6315 */ 6316 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6317 { 6318 if (hw->mac_type != ICE_MAC_E810) 6319 return false; 6320 6321 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6322 ICE_FW_API_LLDP_FLTR_MIN, 6323 ICE_FW_API_LLDP_FLTR_PATCH); 6324 } 6325 6326 /** 6327 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6328 * @hw: pointer to HW struct 6329 * @vsi: VSI to add the filter to 6330 * @add: boolean for if adding or removing a filter 6331 * 6332 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6333 * with this HW or VSI, otherwise an error corresponding to 6334 * the AQ transaction result. 6335 */ 6336 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6337 { 6338 struct ice_aqc_lldp_filter_ctrl *cmd; 6339 struct libie_aq_desc desc; 6340 6341 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6342 return -EOPNOTSUPP; 6343 6344 cmd = libie_aq_raw(&desc); 6345 6346 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6347 6348 if (add) 6349 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6350 else 6351 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6352 6353 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6354 6355 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6356 } 6357 6358 /** 6359 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6360 * @hw: pointer to HW struct 6361 */ 6362 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6363 { 6364 struct libie_aq_desc desc; 6365 6366 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6367 6368 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6369 } 6370 6371 /** 6372 * ice_fw_supports_report_dflt_cfg 6373 * @hw: pointer to the hardware structure 6374 * 6375 * Checks if the firmware supports report default configuration 6376 */ 6377 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6378 { 6379 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6380 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6381 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6382 } 6383 6384 /* each of the indexes into the following array match the speed of a return 6385 * value from the list of AQ returned speeds like the range: 6386 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6387 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6388 * array. The array is defined as 15 elements long because the link_speed 6389 * returned by the firmware is a 16 bit * value, but is indexed 6390 * by [fls(speed) - 1] 6391 */ 6392 static const u32 ice_aq_to_link_speed[] = { 6393 SPEED_10, /* BIT(0) */ 6394 SPEED_100, 6395 SPEED_1000, 6396 SPEED_2500, 6397 SPEED_5000, 6398 SPEED_10000, 6399 SPEED_20000, 6400 SPEED_25000, 6401 SPEED_40000, 6402 SPEED_50000, 6403 SPEED_100000, /* BIT(10) */ 6404 SPEED_200000, 6405 }; 6406 6407 /** 6408 * ice_get_link_speed - get integer speed from table 6409 * @index: array index from fls(aq speed) - 1 6410 * 6411 * Returns: u32 value containing integer speed 6412 */ 6413 u32 ice_get_link_speed(u16 index) 6414 { 6415 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6416 return 0; 6417 6418 return ice_aq_to_link_speed[index]; 6419 } 6420 6421 /** 6422 * ice_read_cgu_reg - Read a CGU register 6423 * @hw: Pointer to the HW struct 6424 * @addr: Register address to read 6425 * @val: Storage for register value read 6426 * 6427 * Read the contents of a register of the Clock Generation Unit. Only 6428 * applicable to E82X devices. 6429 * 6430 * Return: 0 on success, other error codes when failed to read from CGU. 6431 */ 6432 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6433 { 6434 struct ice_sbq_msg_input cgu_msg = { 6435 .opcode = ice_sbq_msg_rd, 6436 .dest_dev = ice_sbq_dev_cgu, 6437 .msg_addr_low = addr 6438 }; 6439 int err; 6440 6441 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6442 if (err) { 6443 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6444 addr, err); 6445 return err; 6446 } 6447 6448 *val = cgu_msg.data; 6449 6450 return 0; 6451 } 6452 6453 /** 6454 * ice_write_cgu_reg - Write a CGU register 6455 * @hw: Pointer to the HW struct 6456 * @addr: Register address to write 6457 * @val: Value to write into the register 6458 * 6459 * Write the specified value to a register of the Clock Generation Unit. Only 6460 * applicable to E82X devices. 6461 * 6462 * Return: 0 on success, other error codes when failed to write to CGU. 6463 */ 6464 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6465 { 6466 struct ice_sbq_msg_input cgu_msg = { 6467 .opcode = ice_sbq_msg_wr, 6468 .dest_dev = ice_sbq_dev_cgu, 6469 .msg_addr_low = addr, 6470 .data = val 6471 }; 6472 int err; 6473 6474 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6475 if (err) 6476 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6477 addr, err); 6478 6479 return err; 6480 } 6481