1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_lib.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 #include "ice_flow.h" 9 10 #define ICE_PF_RESET_WAIT_COUNT 300 11 12 /** 13 * ice_set_mac_type - Sets MAC type 14 * @hw: pointer to the HW structure 15 * 16 * This function sets the MAC type of the adapter based on the 17 * vendor ID and device ID stored in the HW structure. 18 */ 19 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 20 { 21 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 22 return ICE_ERR_DEVICE_NOT_SUPPORTED; 23 24 switch (hw->device_id) { 25 case ICE_DEV_ID_E810C_BACKPLANE: 26 case ICE_DEV_ID_E810C_QSFP: 27 case ICE_DEV_ID_E810C_SFP: 28 case ICE_DEV_ID_E810_XXV_SFP: 29 hw->mac_type = ICE_MAC_E810; 30 break; 31 case ICE_DEV_ID_E823C_10G_BASE_T: 32 case ICE_DEV_ID_E823C_BACKPLANE: 33 case ICE_DEV_ID_E823C_QSFP: 34 case ICE_DEV_ID_E823C_SFP: 35 case ICE_DEV_ID_E823C_SGMII: 36 case ICE_DEV_ID_E822C_10G_BASE_T: 37 case ICE_DEV_ID_E822C_BACKPLANE: 38 case ICE_DEV_ID_E822C_QSFP: 39 case ICE_DEV_ID_E822C_SFP: 40 case ICE_DEV_ID_E822C_SGMII: 41 case ICE_DEV_ID_E822L_10G_BASE_T: 42 case ICE_DEV_ID_E822L_BACKPLANE: 43 case ICE_DEV_ID_E822L_SFP: 44 case ICE_DEV_ID_E822L_SGMII: 45 case ICE_DEV_ID_E823L_10G_BASE_T: 46 case ICE_DEV_ID_E823L_1GBE: 47 case ICE_DEV_ID_E823L_BACKPLANE: 48 case ICE_DEV_ID_E823L_QSFP: 49 case ICE_DEV_ID_E823L_SFP: 50 hw->mac_type = ICE_MAC_GENERIC; 51 break; 52 default: 53 hw->mac_type = ICE_MAC_UNKNOWN; 54 break; 55 } 56 57 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 58 return 0; 59 } 60 61 /** 62 * ice_is_e810 63 * @hw: pointer to the hardware structure 64 * 65 * returns true if the device is E810 based, false if not. 66 */ 67 bool ice_is_e810(struct ice_hw *hw) 68 { 69 return hw->mac_type == ICE_MAC_E810; 70 } 71 72 /** 73 * ice_is_e810t 74 * @hw: pointer to the hardware structure 75 * 76 * returns true if the device is E810T based, false if not. 77 */ 78 bool ice_is_e810t(struct ice_hw *hw) 79 { 80 switch (hw->device_id) { 81 case ICE_DEV_ID_E810C_SFP: 82 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || 83 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 84 return true; 85 break; 86 default: 87 break; 88 } 89 90 return false; 91 } 92 93 /** 94 * ice_clear_pf_cfg - Clear PF configuration 95 * @hw: pointer to the hardware structure 96 * 97 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 98 * configuration, flow director filters, etc.). 99 */ 100 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 101 { 102 struct ice_aq_desc desc; 103 104 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 105 106 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 107 } 108 109 /** 110 * ice_aq_manage_mac_read - manage MAC address read command 111 * @hw: pointer to the HW struct 112 * @buf: a virtual buffer to hold the manage MAC read response 113 * @buf_size: Size of the virtual buffer 114 * @cd: pointer to command details structure or NULL 115 * 116 * This function is used to return per PF station MAC address (0x0107). 117 * NOTE: Upon successful completion of this command, MAC address information 118 * is returned in user specified buffer. Please interpret user specified 119 * buffer as "manage_mac_read" response. 120 * Response such as various MAC addresses are stored in HW struct (port.mac) 121 * ice_discover_dev_caps is expected to be called before this function is 122 * called. 123 */ 124 static enum ice_status 125 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 126 struct ice_sq_cd *cd) 127 { 128 struct ice_aqc_manage_mac_read_resp *resp; 129 struct ice_aqc_manage_mac_read *cmd; 130 struct ice_aq_desc desc; 131 enum ice_status status; 132 u16 flags; 133 u8 i; 134 135 cmd = &desc.params.mac_read; 136 137 if (buf_size < sizeof(*resp)) 138 return ICE_ERR_BUF_TOO_SHORT; 139 140 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 141 142 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 143 if (status) 144 return status; 145 146 resp = buf; 147 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 148 149 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 150 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 151 return ICE_ERR_CFG; 152 } 153 154 /* A single port can report up to two (LAN and WoL) addresses */ 155 for (i = 0; i < cmd->num_addr; i++) 156 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 157 ether_addr_copy(hw->port_info->mac.lan_addr, 158 resp[i].mac_addr); 159 ether_addr_copy(hw->port_info->mac.perm_addr, 160 resp[i].mac_addr); 161 break; 162 } 163 164 return 0; 165 } 166 167 /** 168 * ice_aq_get_phy_caps - returns PHY capabilities 169 * @pi: port information structure 170 * @qual_mods: report qualified modules 171 * @report_mode: report mode capabilities 172 * @pcaps: structure for PHY capabilities to be filled 173 * @cd: pointer to command details structure or NULL 174 * 175 * Returns the various PHY capabilities supported on the Port (0x0600) 176 */ 177 enum ice_status 178 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 179 struct ice_aqc_get_phy_caps_data *pcaps, 180 struct ice_sq_cd *cd) 181 { 182 struct ice_aqc_get_phy_caps *cmd; 183 u16 pcaps_size = sizeof(*pcaps); 184 struct ice_aq_desc desc; 185 enum ice_status status; 186 struct ice_hw *hw; 187 188 cmd = &desc.params.get_phy; 189 190 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 191 return ICE_ERR_PARAM; 192 hw = pi->hw; 193 194 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 195 !ice_fw_supports_report_dflt_cfg(hw)) 196 return ICE_ERR_PARAM; 197 198 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 199 200 if (qual_mods) 201 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 202 203 cmd->param0 |= cpu_to_le16(report_mode); 204 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 205 206 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 207 report_mode); 208 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 209 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 210 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 211 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 212 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 213 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 214 pcaps->low_power_ctrl_an); 215 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 216 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 217 pcaps->eeer_value); 218 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 219 pcaps->link_fec_options); 220 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 221 pcaps->module_compliance_enforcement); 222 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 223 pcaps->extended_compliance_code); 224 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 225 pcaps->module_type[0]); 226 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 227 pcaps->module_type[1]); 228 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 229 pcaps->module_type[2]); 230 231 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 232 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 233 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 234 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 235 sizeof(pi->phy.link_info.module_type)); 236 } 237 238 return status; 239 } 240 241 /** 242 * ice_aq_get_link_topo_handle - get link topology node return status 243 * @pi: port information structure 244 * @node_type: requested node type 245 * @cd: pointer to command details structure or NULL 246 * 247 * Get link topology node return status for specified node type (0x06E0) 248 * 249 * Node type cage can be used to determine if cage is present. If AQC 250 * returns error (ENOENT), then no cage present. If no cage present, then 251 * connection type is backplane or BASE-T. 252 */ 253 static enum ice_status 254 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 255 struct ice_sq_cd *cd) 256 { 257 struct ice_aqc_get_link_topo *cmd; 258 struct ice_aq_desc desc; 259 260 cmd = &desc.params.get_link_topo; 261 262 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 263 264 cmd->addr.topo_params.node_type_ctx = 265 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 266 ICE_AQC_LINK_TOPO_NODE_CTX_S); 267 268 /* set node type */ 269 cmd->addr.topo_params.node_type_ctx |= 270 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 271 272 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 273 } 274 275 /** 276 * ice_is_media_cage_present 277 * @pi: port information structure 278 * 279 * Returns true if media cage is present, else false. If no cage, then 280 * media type is backplane or BASE-T. 281 */ 282 static bool ice_is_media_cage_present(struct ice_port_info *pi) 283 { 284 /* Node type cage can be used to determine if cage is present. If AQC 285 * returns error (ENOENT), then no cage present. If no cage present then 286 * connection type is backplane or BASE-T. 287 */ 288 return !ice_aq_get_link_topo_handle(pi, 289 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 290 NULL); 291 } 292 293 /** 294 * ice_get_media_type - Gets media type 295 * @pi: port information structure 296 */ 297 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 298 { 299 struct ice_link_status *hw_link_info; 300 301 if (!pi) 302 return ICE_MEDIA_UNKNOWN; 303 304 hw_link_info = &pi->phy.link_info; 305 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 306 /* If more than one media type is selected, report unknown */ 307 return ICE_MEDIA_UNKNOWN; 308 309 if (hw_link_info->phy_type_low) { 310 /* 1G SGMII is a special case where some DA cable PHYs 311 * may show this as an option when it really shouldn't 312 * be since SGMII is meant to be between a MAC and a PHY 313 * in a backplane. Try to detect this case and handle it 314 */ 315 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 316 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 317 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 318 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 319 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 320 return ICE_MEDIA_DA; 321 322 switch (hw_link_info->phy_type_low) { 323 case ICE_PHY_TYPE_LOW_1000BASE_SX: 324 case ICE_PHY_TYPE_LOW_1000BASE_LX: 325 case ICE_PHY_TYPE_LOW_10GBASE_SR: 326 case ICE_PHY_TYPE_LOW_10GBASE_LR: 327 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 328 case ICE_PHY_TYPE_LOW_25GBASE_SR: 329 case ICE_PHY_TYPE_LOW_25GBASE_LR: 330 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 331 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 332 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 333 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 334 case ICE_PHY_TYPE_LOW_50GBASE_SR: 335 case ICE_PHY_TYPE_LOW_50GBASE_FR: 336 case ICE_PHY_TYPE_LOW_50GBASE_LR: 337 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 338 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 339 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 340 case ICE_PHY_TYPE_LOW_100GBASE_DR: 341 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 342 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 343 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 344 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 345 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 346 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 347 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 348 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 349 return ICE_MEDIA_FIBER; 350 case ICE_PHY_TYPE_LOW_100BASE_TX: 351 case ICE_PHY_TYPE_LOW_1000BASE_T: 352 case ICE_PHY_TYPE_LOW_2500BASE_T: 353 case ICE_PHY_TYPE_LOW_5GBASE_T: 354 case ICE_PHY_TYPE_LOW_10GBASE_T: 355 case ICE_PHY_TYPE_LOW_25GBASE_T: 356 return ICE_MEDIA_BASET; 357 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 358 case ICE_PHY_TYPE_LOW_25GBASE_CR: 359 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 360 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 361 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 362 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 363 case ICE_PHY_TYPE_LOW_50GBASE_CP: 364 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 365 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 366 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 367 return ICE_MEDIA_DA; 368 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 369 case ICE_PHY_TYPE_LOW_40G_XLAUI: 370 case ICE_PHY_TYPE_LOW_50G_LAUI2: 371 case ICE_PHY_TYPE_LOW_50G_AUI2: 372 case ICE_PHY_TYPE_LOW_50G_AUI1: 373 case ICE_PHY_TYPE_LOW_100G_AUI4: 374 case ICE_PHY_TYPE_LOW_100G_CAUI4: 375 if (ice_is_media_cage_present(pi)) 376 return ICE_MEDIA_DA; 377 fallthrough; 378 case ICE_PHY_TYPE_LOW_1000BASE_KX: 379 case ICE_PHY_TYPE_LOW_2500BASE_KX: 380 case ICE_PHY_TYPE_LOW_2500BASE_X: 381 case ICE_PHY_TYPE_LOW_5GBASE_KR: 382 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 383 case ICE_PHY_TYPE_LOW_25GBASE_KR: 384 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 385 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 386 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 387 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 388 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 389 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 390 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 391 return ICE_MEDIA_BACKPLANE; 392 } 393 } else { 394 switch (hw_link_info->phy_type_high) { 395 case ICE_PHY_TYPE_HIGH_100G_AUI2: 396 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 397 if (ice_is_media_cage_present(pi)) 398 return ICE_MEDIA_DA; 399 fallthrough; 400 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 401 return ICE_MEDIA_BACKPLANE; 402 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 403 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 404 return ICE_MEDIA_FIBER; 405 } 406 } 407 return ICE_MEDIA_UNKNOWN; 408 } 409 410 /** 411 * ice_aq_get_link_info 412 * @pi: port information structure 413 * @ena_lse: enable/disable LinkStatusEvent reporting 414 * @link: pointer to link status structure - optional 415 * @cd: pointer to command details structure or NULL 416 * 417 * Get Link Status (0x607). Returns the link status of the adapter. 418 */ 419 enum ice_status 420 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 421 struct ice_link_status *link, struct ice_sq_cd *cd) 422 { 423 struct ice_aqc_get_link_status_data link_data = { 0 }; 424 struct ice_aqc_get_link_status *resp; 425 struct ice_link_status *li_old, *li; 426 enum ice_media_type *hw_media_type; 427 struct ice_fc_info *hw_fc_info; 428 bool tx_pause, rx_pause; 429 struct ice_aq_desc desc; 430 enum ice_status status; 431 struct ice_hw *hw; 432 u16 cmd_flags; 433 434 if (!pi) 435 return ICE_ERR_PARAM; 436 hw = pi->hw; 437 li_old = &pi->phy.link_info_old; 438 hw_media_type = &pi->phy.media_type; 439 li = &pi->phy.link_info; 440 hw_fc_info = &pi->fc; 441 442 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 443 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 444 resp = &desc.params.get_link_status; 445 resp->cmd_flags = cpu_to_le16(cmd_flags); 446 resp->lport_num = pi->lport; 447 448 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 449 450 if (status) 451 return status; 452 453 /* save off old link status information */ 454 *li_old = *li; 455 456 /* update current link status information */ 457 li->link_speed = le16_to_cpu(link_data.link_speed); 458 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 459 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 460 *hw_media_type = ice_get_media_type(pi); 461 li->link_info = link_data.link_info; 462 li->link_cfg_err = link_data.link_cfg_err; 463 li->an_info = link_data.an_info; 464 li->ext_info = link_data.ext_info; 465 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 466 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 467 li->topo_media_conflict = link_data.topo_media_conflict; 468 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 469 ICE_AQ_CFG_PACING_TYPE_M); 470 471 /* update fc info */ 472 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 473 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 474 if (tx_pause && rx_pause) 475 hw_fc_info->current_mode = ICE_FC_FULL; 476 else if (tx_pause) 477 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 478 else if (rx_pause) 479 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 480 else 481 hw_fc_info->current_mode = ICE_FC_NONE; 482 483 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 484 485 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 486 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 487 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 488 (unsigned long long)li->phy_type_low); 489 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 490 (unsigned long long)li->phy_type_high); 491 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 492 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 493 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 494 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 495 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 496 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 497 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 498 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 499 li->max_frame_size); 500 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 501 502 /* save link status information */ 503 if (link) 504 *link = *li; 505 506 /* flag cleared so calling functions don't call AQ again */ 507 pi->phy.get_link_info = false; 508 509 return 0; 510 } 511 512 /** 513 * ice_fill_tx_timer_and_fc_thresh 514 * @hw: pointer to the HW struct 515 * @cmd: pointer to MAC cfg structure 516 * 517 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 518 * descriptor 519 */ 520 static void 521 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 522 struct ice_aqc_set_mac_cfg *cmd) 523 { 524 u16 fc_thres_val, tx_timer_val; 525 u32 val; 526 527 /* We read back the transmit timer and FC threshold value of 528 * LFC. Thus, we will use index = 529 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 530 * 531 * Also, because we are operating on transmit timer and FC 532 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 533 */ 534 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 535 536 /* Retrieve the transmit timer */ 537 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 538 tx_timer_val = val & 539 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 540 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 541 542 /* Retrieve the FC threshold */ 543 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 544 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 545 546 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 547 } 548 549 /** 550 * ice_aq_set_mac_cfg 551 * @hw: pointer to the HW struct 552 * @max_frame_size: Maximum Frame Size to be supported 553 * @cd: pointer to command details structure or NULL 554 * 555 * Set MAC configuration (0x0603) 556 */ 557 enum ice_status 558 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 559 { 560 struct ice_aqc_set_mac_cfg *cmd; 561 struct ice_aq_desc desc; 562 563 cmd = &desc.params.set_mac_cfg; 564 565 if (max_frame_size == 0) 566 return ICE_ERR_PARAM; 567 568 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 569 570 cmd->max_frame_size = cpu_to_le16(max_frame_size); 571 572 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 573 574 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 575 } 576 577 /** 578 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 579 * @hw: pointer to the HW struct 580 */ 581 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 582 { 583 struct ice_switch_info *sw; 584 enum ice_status status; 585 586 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 587 sizeof(*hw->switch_info), GFP_KERNEL); 588 sw = hw->switch_info; 589 590 if (!sw) 591 return ICE_ERR_NO_MEMORY; 592 593 INIT_LIST_HEAD(&sw->vsi_list_map_head); 594 sw->prof_res_bm_init = 0; 595 596 status = ice_init_def_sw_recp(hw); 597 if (status) { 598 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 599 return status; 600 } 601 return 0; 602 } 603 604 /** 605 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 606 * @hw: pointer to the HW struct 607 */ 608 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 609 { 610 struct ice_switch_info *sw = hw->switch_info; 611 struct ice_vsi_list_map_info *v_pos_map; 612 struct ice_vsi_list_map_info *v_tmp_map; 613 struct ice_sw_recipe *recps; 614 u8 i; 615 616 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 617 list_entry) { 618 list_del(&v_pos_map->list_entry); 619 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 620 } 621 recps = sw->recp_list; 622 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 623 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 624 625 recps[i].root_rid = i; 626 list_for_each_entry_safe(rg_entry, tmprg_entry, 627 &recps[i].rg_list, l_entry) { 628 list_del(&rg_entry->l_entry); 629 devm_kfree(ice_hw_to_dev(hw), rg_entry); 630 } 631 632 if (recps[i].adv_rule) { 633 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 634 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 635 636 mutex_destroy(&recps[i].filt_rule_lock); 637 list_for_each_entry_safe(lst_itr, tmp_entry, 638 &recps[i].filt_rules, 639 list_entry) { 640 list_del(&lst_itr->list_entry); 641 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 642 devm_kfree(ice_hw_to_dev(hw), lst_itr); 643 } 644 } else { 645 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 646 647 mutex_destroy(&recps[i].filt_rule_lock); 648 list_for_each_entry_safe(lst_itr, tmp_entry, 649 &recps[i].filt_rules, 650 list_entry) { 651 list_del(&lst_itr->list_entry); 652 devm_kfree(ice_hw_to_dev(hw), lst_itr); 653 } 654 } 655 if (recps[i].root_buf) 656 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 657 } 658 ice_rm_all_sw_replay_rule_info(hw); 659 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 660 devm_kfree(ice_hw_to_dev(hw), sw); 661 } 662 663 /** 664 * ice_get_fw_log_cfg - get FW logging configuration 665 * @hw: pointer to the HW struct 666 */ 667 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 668 { 669 struct ice_aq_desc desc; 670 enum ice_status status; 671 __le16 *config; 672 u16 size; 673 674 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 675 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 676 if (!config) 677 return ICE_ERR_NO_MEMORY; 678 679 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 680 681 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 682 if (!status) { 683 u16 i; 684 685 /* Save FW logging information into the HW structure */ 686 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 687 u16 v, m, flgs; 688 689 v = le16_to_cpu(config[i]); 690 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 691 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 692 693 if (m < ICE_AQC_FW_LOG_ID_MAX) 694 hw->fw_log.evnts[m].cur = flgs; 695 } 696 } 697 698 devm_kfree(ice_hw_to_dev(hw), config); 699 700 return status; 701 } 702 703 /** 704 * ice_cfg_fw_log - configure FW logging 705 * @hw: pointer to the HW struct 706 * @enable: enable certain FW logging events if true, disable all if false 707 * 708 * This function enables/disables the FW logging via Rx CQ events and a UART 709 * port based on predetermined configurations. FW logging via the Rx CQ can be 710 * enabled/disabled for individual PF's. However, FW logging via the UART can 711 * only be enabled/disabled for all PFs on the same device. 712 * 713 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 714 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 715 * before initializing the device. 716 * 717 * When re/configuring FW logging, callers need to update the "cfg" elements of 718 * the hw->fw_log.evnts array with the desired logging event configurations for 719 * modules of interest. When disabling FW logging completely, the callers can 720 * just pass false in the "enable" parameter. On completion, the function will 721 * update the "cur" element of the hw->fw_log.evnts array with the resulting 722 * logging event configurations of the modules that are being re/configured. FW 723 * logging modules that are not part of a reconfiguration operation retain their 724 * previous states. 725 * 726 * Before resetting the device, it is recommended that the driver disables FW 727 * logging before shutting down the control queue. When disabling FW logging 728 * ("enable" = false), the latest configurations of FW logging events stored in 729 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 730 * a device reset. 731 * 732 * When enabling FW logging to emit log messages via the Rx CQ during the 733 * device's initialization phase, a mechanism alternative to interrupt handlers 734 * needs to be used to extract FW log messages from the Rx CQ periodically and 735 * to prevent the Rx CQ from being full and stalling other types of control 736 * messages from FW to SW. Interrupts are typically disabled during the device's 737 * initialization phase. 738 */ 739 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 740 { 741 struct ice_aqc_fw_logging *cmd; 742 enum ice_status status = 0; 743 u16 i, chgs = 0, len = 0; 744 struct ice_aq_desc desc; 745 __le16 *data = NULL; 746 u8 actv_evnts = 0; 747 void *buf = NULL; 748 749 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 750 return 0; 751 752 /* Disable FW logging only when the control queue is still responsive */ 753 if (!enable && 754 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 755 return 0; 756 757 /* Get current FW log settings */ 758 status = ice_get_fw_log_cfg(hw); 759 if (status) 760 return status; 761 762 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 763 cmd = &desc.params.fw_logging; 764 765 /* Indicate which controls are valid */ 766 if (hw->fw_log.cq_en) 767 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 768 769 if (hw->fw_log.uart_en) 770 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 771 772 if (enable) { 773 /* Fill in an array of entries with FW logging modules and 774 * logging events being reconfigured. 775 */ 776 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 777 u16 val; 778 779 /* Keep track of enabled event types */ 780 actv_evnts |= hw->fw_log.evnts[i].cfg; 781 782 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 783 continue; 784 785 if (!data) { 786 data = devm_kcalloc(ice_hw_to_dev(hw), 787 ICE_AQC_FW_LOG_ID_MAX, 788 sizeof(*data), 789 GFP_KERNEL); 790 if (!data) 791 return ICE_ERR_NO_MEMORY; 792 } 793 794 val = i << ICE_AQC_FW_LOG_ID_S; 795 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 796 data[chgs++] = cpu_to_le16(val); 797 } 798 799 /* Only enable FW logging if at least one module is specified. 800 * If FW logging is currently enabled but all modules are not 801 * enabled to emit log messages, disable FW logging altogether. 802 */ 803 if (actv_evnts) { 804 /* Leave if there is effectively no change */ 805 if (!chgs) 806 goto out; 807 808 if (hw->fw_log.cq_en) 809 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 810 811 if (hw->fw_log.uart_en) 812 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 813 814 buf = data; 815 len = sizeof(*data) * chgs; 816 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 817 } 818 } 819 820 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 821 if (!status) { 822 /* Update the current configuration to reflect events enabled. 823 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 824 * logging mode is enabled for the device. They do not reflect 825 * actual modules being enabled to emit log messages. So, their 826 * values remain unchanged even when all modules are disabled. 827 */ 828 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 829 830 hw->fw_log.actv_evnts = actv_evnts; 831 for (i = 0; i < cnt; i++) { 832 u16 v, m; 833 834 if (!enable) { 835 /* When disabling all FW logging events as part 836 * of device's de-initialization, the original 837 * configurations are retained, and can be used 838 * to reconfigure FW logging later if the device 839 * is re-initialized. 840 */ 841 hw->fw_log.evnts[i].cur = 0; 842 continue; 843 } 844 845 v = le16_to_cpu(data[i]); 846 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 847 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 848 } 849 } 850 851 out: 852 if (data) 853 devm_kfree(ice_hw_to_dev(hw), data); 854 855 return status; 856 } 857 858 /** 859 * ice_output_fw_log 860 * @hw: pointer to the HW struct 861 * @desc: pointer to the AQ message descriptor 862 * @buf: pointer to the buffer accompanying the AQ message 863 * 864 * Formats a FW Log message and outputs it via the standard driver logs. 865 */ 866 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 867 { 868 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 869 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 870 le16_to_cpu(desc->datalen)); 871 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 872 } 873 874 /** 875 * ice_get_itr_intrl_gran 876 * @hw: pointer to the HW struct 877 * 878 * Determines the ITR/INTRL granularities based on the maximum aggregate 879 * bandwidth according to the device's configuration during power-on. 880 */ 881 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 882 { 883 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 884 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 885 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 886 887 switch (max_agg_bw) { 888 case ICE_MAX_AGG_BW_200G: 889 case ICE_MAX_AGG_BW_100G: 890 case ICE_MAX_AGG_BW_50G: 891 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 892 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 893 break; 894 case ICE_MAX_AGG_BW_25G: 895 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 896 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 897 break; 898 } 899 } 900 901 /** 902 * ice_init_hw - main hardware initialization routine 903 * @hw: pointer to the hardware structure 904 */ 905 enum ice_status ice_init_hw(struct ice_hw *hw) 906 { 907 struct ice_aqc_get_phy_caps_data *pcaps; 908 enum ice_status status; 909 u16 mac_buf_len; 910 void *mac_buf; 911 912 /* Set MAC type based on DeviceID */ 913 status = ice_set_mac_type(hw); 914 if (status) 915 return status; 916 917 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 918 PF_FUNC_RID_FUNC_NUM_M) >> 919 PF_FUNC_RID_FUNC_NUM_S; 920 921 status = ice_reset(hw, ICE_RESET_PFR); 922 if (status) 923 return status; 924 925 ice_get_itr_intrl_gran(hw); 926 927 status = ice_create_all_ctrlq(hw); 928 if (status) 929 goto err_unroll_cqinit; 930 931 /* Enable FW logging. Not fatal if this fails. */ 932 status = ice_cfg_fw_log(hw, true); 933 if (status) 934 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 935 936 status = ice_clear_pf_cfg(hw); 937 if (status) 938 goto err_unroll_cqinit; 939 940 /* Set bit to enable Flow Director filters */ 941 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 942 INIT_LIST_HEAD(&hw->fdir_list_head); 943 944 ice_clear_pxe_mode(hw); 945 946 status = ice_init_nvm(hw); 947 if (status) 948 goto err_unroll_cqinit; 949 950 status = ice_get_caps(hw); 951 if (status) 952 goto err_unroll_cqinit; 953 954 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 955 sizeof(*hw->port_info), GFP_KERNEL); 956 if (!hw->port_info) { 957 status = ICE_ERR_NO_MEMORY; 958 goto err_unroll_cqinit; 959 } 960 961 /* set the back pointer to HW */ 962 hw->port_info->hw = hw; 963 964 /* Initialize port_info struct with switch configuration data */ 965 status = ice_get_initial_sw_cfg(hw); 966 if (status) 967 goto err_unroll_alloc; 968 969 hw->evb_veb = true; 970 971 /* Query the allocated resources for Tx scheduler */ 972 status = ice_sched_query_res_alloc(hw); 973 if (status) { 974 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 975 goto err_unroll_alloc; 976 } 977 ice_sched_get_psm_clk_freq(hw); 978 979 /* Initialize port_info struct with scheduler data */ 980 status = ice_sched_init_port(hw->port_info); 981 if (status) 982 goto err_unroll_sched; 983 984 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 985 if (!pcaps) { 986 status = ICE_ERR_NO_MEMORY; 987 goto err_unroll_sched; 988 } 989 990 /* Initialize port_info struct with PHY capabilities */ 991 status = ice_aq_get_phy_caps(hw->port_info, false, 992 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 993 NULL); 994 devm_kfree(ice_hw_to_dev(hw), pcaps); 995 if (status) 996 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 997 status); 998 999 /* Initialize port_info struct with link information */ 1000 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1001 if (status) 1002 goto err_unroll_sched; 1003 1004 /* need a valid SW entry point to build a Tx tree */ 1005 if (!hw->sw_entry_point_layer) { 1006 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1007 status = ICE_ERR_CFG; 1008 goto err_unroll_sched; 1009 } 1010 INIT_LIST_HEAD(&hw->agg_list); 1011 /* Initialize max burst size */ 1012 if (!hw->max_burst_size) 1013 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1014 1015 status = ice_init_fltr_mgmt_struct(hw); 1016 if (status) 1017 goto err_unroll_sched; 1018 1019 /* Get MAC information */ 1020 /* A single port can report up to two (LAN and WoL) addresses */ 1021 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1022 sizeof(struct ice_aqc_manage_mac_read_resp), 1023 GFP_KERNEL); 1024 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1025 1026 if (!mac_buf) { 1027 status = ICE_ERR_NO_MEMORY; 1028 goto err_unroll_fltr_mgmt_struct; 1029 } 1030 1031 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1032 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1033 1034 if (status) 1035 goto err_unroll_fltr_mgmt_struct; 1036 /* enable jumbo frame support at MAC level */ 1037 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1038 if (status) 1039 goto err_unroll_fltr_mgmt_struct; 1040 /* Obtain counter base index which would be used by flow director */ 1041 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1042 if (status) 1043 goto err_unroll_fltr_mgmt_struct; 1044 status = ice_init_hw_tbls(hw); 1045 if (status) 1046 goto err_unroll_fltr_mgmt_struct; 1047 mutex_init(&hw->tnl_lock); 1048 return 0; 1049 1050 err_unroll_fltr_mgmt_struct: 1051 ice_cleanup_fltr_mgmt_struct(hw); 1052 err_unroll_sched: 1053 ice_sched_cleanup_all(hw); 1054 err_unroll_alloc: 1055 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1056 err_unroll_cqinit: 1057 ice_destroy_all_ctrlq(hw); 1058 return status; 1059 } 1060 1061 /** 1062 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1063 * @hw: pointer to the hardware structure 1064 * 1065 * This should be called only during nominal operation, not as a result of 1066 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1067 * applicable initializations if it fails for any reason. 1068 */ 1069 void ice_deinit_hw(struct ice_hw *hw) 1070 { 1071 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1072 ice_cleanup_fltr_mgmt_struct(hw); 1073 1074 ice_sched_cleanup_all(hw); 1075 ice_sched_clear_agg(hw); 1076 ice_free_seg(hw); 1077 ice_free_hw_tbls(hw); 1078 mutex_destroy(&hw->tnl_lock); 1079 1080 if (hw->port_info) { 1081 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1082 hw->port_info = NULL; 1083 } 1084 1085 /* Attempt to disable FW logging before shutting down control queues */ 1086 ice_cfg_fw_log(hw, false); 1087 ice_destroy_all_ctrlq(hw); 1088 1089 /* Clear VSI contexts if not already cleared */ 1090 ice_clear_all_vsi_ctx(hw); 1091 } 1092 1093 /** 1094 * ice_check_reset - Check to see if a global reset is complete 1095 * @hw: pointer to the hardware structure 1096 */ 1097 enum ice_status ice_check_reset(struct ice_hw *hw) 1098 { 1099 u32 cnt, reg = 0, grst_timeout, uld_mask; 1100 1101 /* Poll for Device Active state in case a recent CORER, GLOBR, 1102 * or EMPR has occurred. The grst delay value is in 100ms units. 1103 * Add 1sec for outstanding AQ commands that can take a long time. 1104 */ 1105 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1106 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1107 1108 for (cnt = 0; cnt < grst_timeout; cnt++) { 1109 mdelay(100); 1110 reg = rd32(hw, GLGEN_RSTAT); 1111 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1112 break; 1113 } 1114 1115 if (cnt == grst_timeout) { 1116 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1117 return ICE_ERR_RESET_FAILED; 1118 } 1119 1120 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1121 GLNVM_ULD_PCIER_DONE_1_M |\ 1122 GLNVM_ULD_CORER_DONE_M |\ 1123 GLNVM_ULD_GLOBR_DONE_M |\ 1124 GLNVM_ULD_POR_DONE_M |\ 1125 GLNVM_ULD_POR_DONE_1_M |\ 1126 GLNVM_ULD_PCIER_DONE_2_M) 1127 1128 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1129 GLNVM_ULD_PE_DONE_M : 0); 1130 1131 /* Device is Active; check Global Reset processes are done */ 1132 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1133 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1134 if (reg == uld_mask) { 1135 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1136 break; 1137 } 1138 mdelay(10); 1139 } 1140 1141 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1142 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1143 reg); 1144 return ICE_ERR_RESET_FAILED; 1145 } 1146 1147 return 0; 1148 } 1149 1150 /** 1151 * ice_pf_reset - Reset the PF 1152 * @hw: pointer to the hardware structure 1153 * 1154 * If a global reset has been triggered, this function checks 1155 * for its completion and then issues the PF reset 1156 */ 1157 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1158 { 1159 u32 cnt, reg; 1160 1161 /* If at function entry a global reset was already in progress, i.e. 1162 * state is not 'device active' or any of the reset done bits are not 1163 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1164 * global reset is done. 1165 */ 1166 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1167 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1168 /* poll on global reset currently in progress until done */ 1169 if (ice_check_reset(hw)) 1170 return ICE_ERR_RESET_FAILED; 1171 1172 return 0; 1173 } 1174 1175 /* Reset the PF */ 1176 reg = rd32(hw, PFGEN_CTRL); 1177 1178 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1179 1180 /* Wait for the PFR to complete. The wait time is the global config lock 1181 * timeout plus the PFR timeout which will account for a possible reset 1182 * that is occurring during a download package operation. 1183 */ 1184 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1185 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1186 reg = rd32(hw, PFGEN_CTRL); 1187 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1188 break; 1189 1190 mdelay(1); 1191 } 1192 1193 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1194 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1195 return ICE_ERR_RESET_FAILED; 1196 } 1197 1198 return 0; 1199 } 1200 1201 /** 1202 * ice_reset - Perform different types of reset 1203 * @hw: pointer to the hardware structure 1204 * @req: reset request 1205 * 1206 * This function triggers a reset as specified by the req parameter. 1207 * 1208 * Note: 1209 * If anything other than a PF reset is triggered, PXE mode is restored. 1210 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1211 * interface has been restored in the rebuild flow. 1212 */ 1213 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1214 { 1215 u32 val = 0; 1216 1217 switch (req) { 1218 case ICE_RESET_PFR: 1219 return ice_pf_reset(hw); 1220 case ICE_RESET_CORER: 1221 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1222 val = GLGEN_RTRIG_CORER_M; 1223 break; 1224 case ICE_RESET_GLOBR: 1225 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1226 val = GLGEN_RTRIG_GLOBR_M; 1227 break; 1228 default: 1229 return ICE_ERR_PARAM; 1230 } 1231 1232 val |= rd32(hw, GLGEN_RTRIG); 1233 wr32(hw, GLGEN_RTRIG, val); 1234 ice_flush(hw); 1235 1236 /* wait for the FW to be ready */ 1237 return ice_check_reset(hw); 1238 } 1239 1240 /** 1241 * ice_copy_rxq_ctx_to_hw 1242 * @hw: pointer to the hardware structure 1243 * @ice_rxq_ctx: pointer to the rxq context 1244 * @rxq_index: the index of the Rx queue 1245 * 1246 * Copies rxq context from dense structure to HW register space 1247 */ 1248 static enum ice_status 1249 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1250 { 1251 u8 i; 1252 1253 if (!ice_rxq_ctx) 1254 return ICE_ERR_BAD_PTR; 1255 1256 if (rxq_index > QRX_CTRL_MAX_INDEX) 1257 return ICE_ERR_PARAM; 1258 1259 /* Copy each dword separately to HW */ 1260 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1261 wr32(hw, QRX_CONTEXT(i, rxq_index), 1262 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1263 1264 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1265 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1266 } 1267 1268 return 0; 1269 } 1270 1271 /* LAN Rx Queue Context */ 1272 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1273 /* Field Width LSB */ 1274 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1275 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1276 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1277 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1278 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1279 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1280 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1281 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1282 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1283 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1284 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1285 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1286 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1287 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1288 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1289 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1290 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1291 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1292 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1293 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1294 { 0 } 1295 }; 1296 1297 /** 1298 * ice_write_rxq_ctx 1299 * @hw: pointer to the hardware structure 1300 * @rlan_ctx: pointer to the rxq context 1301 * @rxq_index: the index of the Rx queue 1302 * 1303 * Converts rxq context from sparse to dense structure and then writes 1304 * it to HW register space and enables the hardware to prefetch descriptors 1305 * instead of only fetching them on demand 1306 */ 1307 enum ice_status 1308 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1309 u32 rxq_index) 1310 { 1311 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1312 1313 if (!rlan_ctx) 1314 return ICE_ERR_BAD_PTR; 1315 1316 rlan_ctx->prefena = 1; 1317 1318 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1319 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1320 } 1321 1322 /* LAN Tx Queue Context */ 1323 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1324 /* Field Width LSB */ 1325 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1326 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1327 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1328 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1329 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1330 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1331 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1332 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1333 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1334 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1335 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1336 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1337 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1338 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1339 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1340 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1341 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1342 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1343 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1344 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1345 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1346 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1347 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1348 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1349 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1350 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1351 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1352 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1353 { 0 } 1354 }; 1355 1356 /* Sideband Queue command wrappers */ 1357 1358 /** 1359 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1360 * @hw: pointer to the HW struct 1361 * @desc: descriptor describing the command 1362 * @buf: buffer to use for indirect commands (NULL for direct commands) 1363 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1364 * @cd: pointer to command details structure 1365 */ 1366 static int 1367 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1368 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1369 { 1370 return ice_status_to_errno(ice_sq_send_cmd(hw, ice_get_sbq(hw), 1371 (struct ice_aq_desc *)desc, 1372 buf, buf_size, cd)); 1373 } 1374 1375 /** 1376 * ice_sbq_rw_reg - Fill Sideband Queue command 1377 * @hw: pointer to the HW struct 1378 * @in: message info to be filled in descriptor 1379 */ 1380 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1381 { 1382 struct ice_sbq_cmd_desc desc = {0}; 1383 struct ice_sbq_msg_req msg = {0}; 1384 u16 msg_len; 1385 int status; 1386 1387 msg_len = sizeof(msg); 1388 1389 msg.dest_dev = in->dest_dev; 1390 msg.opcode = in->opcode; 1391 msg.flags = ICE_SBQ_MSG_FLAGS; 1392 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1393 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1394 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1395 1396 if (in->opcode) 1397 msg.data = cpu_to_le32(in->data); 1398 else 1399 /* data read comes back in completion, so shorten the struct by 1400 * sizeof(msg.data) 1401 */ 1402 msg_len -= sizeof(msg.data); 1403 1404 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1405 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1406 desc.param0.cmd_len = cpu_to_le16(msg_len); 1407 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1408 if (!status && !in->opcode) 1409 in->data = le32_to_cpu 1410 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1411 return status; 1412 } 1413 1414 /* FW Admin Queue command wrappers */ 1415 1416 /* Software lock/mutex that is meant to be held while the Global Config Lock 1417 * in firmware is acquired by the software to prevent most (but not all) types 1418 * of AQ commands from being sent to FW 1419 */ 1420 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1421 1422 /** 1423 * ice_should_retry_sq_send_cmd 1424 * @opcode: AQ opcode 1425 * 1426 * Decide if we should retry the send command routine for the ATQ, depending 1427 * on the opcode. 1428 */ 1429 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1430 { 1431 switch (opcode) { 1432 case ice_aqc_opc_get_link_topo: 1433 case ice_aqc_opc_lldp_stop: 1434 case ice_aqc_opc_lldp_start: 1435 case ice_aqc_opc_lldp_filter_ctrl: 1436 return true; 1437 } 1438 1439 return false; 1440 } 1441 1442 /** 1443 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1444 * @hw: pointer to the HW struct 1445 * @cq: pointer to the specific Control queue 1446 * @desc: prefilled descriptor describing the command 1447 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1448 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1449 * @cd: pointer to command details structure 1450 * 1451 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1452 * Queue if the EBUSY AQ error is returned. 1453 */ 1454 static enum ice_status 1455 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1456 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1457 struct ice_sq_cd *cd) 1458 { 1459 struct ice_aq_desc desc_cpy; 1460 enum ice_status status; 1461 bool is_cmd_for_retry; 1462 u8 *buf_cpy = NULL; 1463 u8 idx = 0; 1464 u16 opcode; 1465 1466 opcode = le16_to_cpu(desc->opcode); 1467 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1468 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1469 1470 if (is_cmd_for_retry) { 1471 if (buf) { 1472 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1473 if (!buf_cpy) 1474 return ICE_ERR_NO_MEMORY; 1475 } 1476 1477 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1478 } 1479 1480 do { 1481 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1482 1483 if (!is_cmd_for_retry || !status || 1484 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1485 break; 1486 1487 if (buf_cpy) 1488 memcpy(buf, buf_cpy, buf_size); 1489 1490 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1491 1492 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1493 1494 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1495 1496 kfree(buf_cpy); 1497 1498 return status; 1499 } 1500 1501 /** 1502 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1503 * @hw: pointer to the HW struct 1504 * @desc: descriptor describing the command 1505 * @buf: buffer to use for indirect commands (NULL for direct commands) 1506 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1507 * @cd: pointer to command details structure 1508 * 1509 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1510 */ 1511 enum ice_status 1512 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1513 u16 buf_size, struct ice_sq_cd *cd) 1514 { 1515 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1516 bool lock_acquired = false; 1517 enum ice_status status; 1518 1519 /* When a package download is in process (i.e. when the firmware's 1520 * Global Configuration Lock resource is held), only the Download 1521 * Package, Get Version, Get Package Info List and Release Resource 1522 * (with resource ID set to Global Config Lock) AdminQ commands are 1523 * allowed; all others must block until the package download completes 1524 * and the Global Config Lock is released. See also 1525 * ice_acquire_global_cfg_lock(). 1526 */ 1527 switch (le16_to_cpu(desc->opcode)) { 1528 case ice_aqc_opc_download_pkg: 1529 case ice_aqc_opc_get_pkg_info_list: 1530 case ice_aqc_opc_get_ver: 1531 break; 1532 case ice_aqc_opc_release_res: 1533 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1534 break; 1535 fallthrough; 1536 default: 1537 mutex_lock(&ice_global_cfg_lock_sw); 1538 lock_acquired = true; 1539 break; 1540 } 1541 1542 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1543 if (lock_acquired) 1544 mutex_unlock(&ice_global_cfg_lock_sw); 1545 1546 return status; 1547 } 1548 1549 /** 1550 * ice_aq_get_fw_ver 1551 * @hw: pointer to the HW struct 1552 * @cd: pointer to command details structure or NULL 1553 * 1554 * Get the firmware version (0x0001) from the admin queue commands 1555 */ 1556 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1557 { 1558 struct ice_aqc_get_ver *resp; 1559 struct ice_aq_desc desc; 1560 enum ice_status status; 1561 1562 resp = &desc.params.get_ver; 1563 1564 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1565 1566 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1567 1568 if (!status) { 1569 hw->fw_branch = resp->fw_branch; 1570 hw->fw_maj_ver = resp->fw_major; 1571 hw->fw_min_ver = resp->fw_minor; 1572 hw->fw_patch = resp->fw_patch; 1573 hw->fw_build = le32_to_cpu(resp->fw_build); 1574 hw->api_branch = resp->api_branch; 1575 hw->api_maj_ver = resp->api_major; 1576 hw->api_min_ver = resp->api_minor; 1577 hw->api_patch = resp->api_patch; 1578 } 1579 1580 return status; 1581 } 1582 1583 /** 1584 * ice_aq_send_driver_ver 1585 * @hw: pointer to the HW struct 1586 * @dv: driver's major, minor version 1587 * @cd: pointer to command details structure or NULL 1588 * 1589 * Send the driver version (0x0002) to the firmware 1590 */ 1591 enum ice_status 1592 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1593 struct ice_sq_cd *cd) 1594 { 1595 struct ice_aqc_driver_ver *cmd; 1596 struct ice_aq_desc desc; 1597 u16 len; 1598 1599 cmd = &desc.params.driver_ver; 1600 1601 if (!dv) 1602 return ICE_ERR_PARAM; 1603 1604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1605 1606 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1607 cmd->major_ver = dv->major_ver; 1608 cmd->minor_ver = dv->minor_ver; 1609 cmd->build_ver = dv->build_ver; 1610 cmd->subbuild_ver = dv->subbuild_ver; 1611 1612 len = 0; 1613 while (len < sizeof(dv->driver_string) && 1614 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1615 len++; 1616 1617 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1618 } 1619 1620 /** 1621 * ice_aq_q_shutdown 1622 * @hw: pointer to the HW struct 1623 * @unloading: is the driver unloading itself 1624 * 1625 * Tell the Firmware that we're shutting down the AdminQ and whether 1626 * or not the driver is unloading as well (0x0003). 1627 */ 1628 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1629 { 1630 struct ice_aqc_q_shutdown *cmd; 1631 struct ice_aq_desc desc; 1632 1633 cmd = &desc.params.q_shutdown; 1634 1635 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1636 1637 if (unloading) 1638 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1639 1640 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1641 } 1642 1643 /** 1644 * ice_aq_req_res 1645 * @hw: pointer to the HW struct 1646 * @res: resource ID 1647 * @access: access type 1648 * @sdp_number: resource number 1649 * @timeout: the maximum time in ms that the driver may hold the resource 1650 * @cd: pointer to command details structure or NULL 1651 * 1652 * Requests common resource using the admin queue commands (0x0008). 1653 * When attempting to acquire the Global Config Lock, the driver can 1654 * learn of three states: 1655 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1656 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1657 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1658 * successfully downloaded the package; the driver does 1659 * not have to download the package and can continue 1660 * loading 1661 * 1662 * Note that if the caller is in an acquire lock, perform action, release lock 1663 * phase of operation, it is possible that the FW may detect a timeout and issue 1664 * a CORER. In this case, the driver will receive a CORER interrupt and will 1665 * have to determine its cause. The calling thread that is handling this flow 1666 * will likely get an error propagated back to it indicating the Download 1667 * Package, Update Package or the Release Resource AQ commands timed out. 1668 */ 1669 static enum ice_status 1670 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1671 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1672 struct ice_sq_cd *cd) 1673 { 1674 struct ice_aqc_req_res *cmd_resp; 1675 struct ice_aq_desc desc; 1676 enum ice_status status; 1677 1678 cmd_resp = &desc.params.res_owner; 1679 1680 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1681 1682 cmd_resp->res_id = cpu_to_le16(res); 1683 cmd_resp->access_type = cpu_to_le16(access); 1684 cmd_resp->res_number = cpu_to_le32(sdp_number); 1685 cmd_resp->timeout = cpu_to_le32(*timeout); 1686 *timeout = 0; 1687 1688 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1689 1690 /* The completion specifies the maximum time in ms that the driver 1691 * may hold the resource in the Timeout field. 1692 */ 1693 1694 /* Global config lock response utilizes an additional status field. 1695 * 1696 * If the Global config lock resource is held by some other driver, the 1697 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1698 * and the timeout field indicates the maximum time the current owner 1699 * of the resource has to free it. 1700 */ 1701 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1702 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1703 *timeout = le32_to_cpu(cmd_resp->timeout); 1704 return 0; 1705 } else if (le16_to_cpu(cmd_resp->status) == 1706 ICE_AQ_RES_GLBL_IN_PROG) { 1707 *timeout = le32_to_cpu(cmd_resp->timeout); 1708 return ICE_ERR_AQ_ERROR; 1709 } else if (le16_to_cpu(cmd_resp->status) == 1710 ICE_AQ_RES_GLBL_DONE) { 1711 return ICE_ERR_AQ_NO_WORK; 1712 } 1713 1714 /* invalid FW response, force a timeout immediately */ 1715 *timeout = 0; 1716 return ICE_ERR_AQ_ERROR; 1717 } 1718 1719 /* If the resource is held by some other driver, the command completes 1720 * with a busy return value and the timeout field indicates the maximum 1721 * time the current owner of the resource has to free it. 1722 */ 1723 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1724 *timeout = le32_to_cpu(cmd_resp->timeout); 1725 1726 return status; 1727 } 1728 1729 /** 1730 * ice_aq_release_res 1731 * @hw: pointer to the HW struct 1732 * @res: resource ID 1733 * @sdp_number: resource number 1734 * @cd: pointer to command details structure or NULL 1735 * 1736 * release common resource using the admin queue commands (0x0009) 1737 */ 1738 static enum ice_status 1739 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1740 struct ice_sq_cd *cd) 1741 { 1742 struct ice_aqc_req_res *cmd; 1743 struct ice_aq_desc desc; 1744 1745 cmd = &desc.params.res_owner; 1746 1747 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1748 1749 cmd->res_id = cpu_to_le16(res); 1750 cmd->res_number = cpu_to_le32(sdp_number); 1751 1752 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1753 } 1754 1755 /** 1756 * ice_acquire_res 1757 * @hw: pointer to the HW structure 1758 * @res: resource ID 1759 * @access: access type (read or write) 1760 * @timeout: timeout in milliseconds 1761 * 1762 * This function will attempt to acquire the ownership of a resource. 1763 */ 1764 enum ice_status 1765 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1766 enum ice_aq_res_access_type access, u32 timeout) 1767 { 1768 #define ICE_RES_POLLING_DELAY_MS 10 1769 u32 delay = ICE_RES_POLLING_DELAY_MS; 1770 u32 time_left = timeout; 1771 enum ice_status status; 1772 1773 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1774 1775 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1776 * previously acquired the resource and performed any necessary updates; 1777 * in this case the caller does not obtain the resource and has no 1778 * further work to do. 1779 */ 1780 if (status == ICE_ERR_AQ_NO_WORK) 1781 goto ice_acquire_res_exit; 1782 1783 if (status) 1784 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1785 1786 /* If necessary, poll until the current lock owner timeouts */ 1787 timeout = time_left; 1788 while (status && timeout && time_left) { 1789 mdelay(delay); 1790 timeout = (timeout > delay) ? timeout - delay : 0; 1791 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1792 1793 if (status == ICE_ERR_AQ_NO_WORK) 1794 /* lock free, but no work to do */ 1795 break; 1796 1797 if (!status) 1798 /* lock acquired */ 1799 break; 1800 } 1801 if (status && status != ICE_ERR_AQ_NO_WORK) 1802 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1803 1804 ice_acquire_res_exit: 1805 if (status == ICE_ERR_AQ_NO_WORK) { 1806 if (access == ICE_RES_WRITE) 1807 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1808 else 1809 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1810 } 1811 return status; 1812 } 1813 1814 /** 1815 * ice_release_res 1816 * @hw: pointer to the HW structure 1817 * @res: resource ID 1818 * 1819 * This function will release a resource using the proper Admin Command. 1820 */ 1821 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1822 { 1823 enum ice_status status; 1824 u32 total_delay = 0; 1825 1826 status = ice_aq_release_res(hw, res, 0, NULL); 1827 1828 /* there are some rare cases when trying to release the resource 1829 * results in an admin queue timeout, so handle them correctly 1830 */ 1831 while ((status == ICE_ERR_AQ_TIMEOUT) && 1832 (total_delay < hw->adminq.sq_cmd_timeout)) { 1833 mdelay(1); 1834 status = ice_aq_release_res(hw, res, 0, NULL); 1835 total_delay++; 1836 } 1837 } 1838 1839 /** 1840 * ice_aq_alloc_free_res - command to allocate/free resources 1841 * @hw: pointer to the HW struct 1842 * @num_entries: number of resource entries in buffer 1843 * @buf: Indirect buffer to hold data parameters and response 1844 * @buf_size: size of buffer for indirect commands 1845 * @opc: pass in the command opcode 1846 * @cd: pointer to command details structure or NULL 1847 * 1848 * Helper function to allocate/free resources using the admin queue commands 1849 */ 1850 enum ice_status 1851 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1852 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1853 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1854 { 1855 struct ice_aqc_alloc_free_res_cmd *cmd; 1856 struct ice_aq_desc desc; 1857 1858 cmd = &desc.params.sw_res_ctrl; 1859 1860 if (!buf) 1861 return ICE_ERR_PARAM; 1862 1863 if (buf_size < flex_array_size(buf, elem, num_entries)) 1864 return ICE_ERR_PARAM; 1865 1866 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1867 1868 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1869 1870 cmd->num_entries = cpu_to_le16(num_entries); 1871 1872 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1873 } 1874 1875 /** 1876 * ice_alloc_hw_res - allocate resource 1877 * @hw: pointer to the HW struct 1878 * @type: type of resource 1879 * @num: number of resources to allocate 1880 * @btm: allocate from bottom 1881 * @res: pointer to array that will receive the resources 1882 */ 1883 enum ice_status 1884 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1885 { 1886 struct ice_aqc_alloc_free_res_elem *buf; 1887 enum ice_status status; 1888 u16 buf_len; 1889 1890 buf_len = struct_size(buf, elem, num); 1891 buf = kzalloc(buf_len, GFP_KERNEL); 1892 if (!buf) 1893 return ICE_ERR_NO_MEMORY; 1894 1895 /* Prepare buffer to allocate resource. */ 1896 buf->num_elems = cpu_to_le16(num); 1897 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1898 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1899 if (btm) 1900 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1901 1902 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1903 ice_aqc_opc_alloc_res, NULL); 1904 if (status) 1905 goto ice_alloc_res_exit; 1906 1907 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1908 1909 ice_alloc_res_exit: 1910 kfree(buf); 1911 return status; 1912 } 1913 1914 /** 1915 * ice_free_hw_res - free allocated HW resource 1916 * @hw: pointer to the HW struct 1917 * @type: type of resource to free 1918 * @num: number of resources 1919 * @res: pointer to array that contains the resources to free 1920 */ 1921 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1922 { 1923 struct ice_aqc_alloc_free_res_elem *buf; 1924 enum ice_status status; 1925 u16 buf_len; 1926 1927 buf_len = struct_size(buf, elem, num); 1928 buf = kzalloc(buf_len, GFP_KERNEL); 1929 if (!buf) 1930 return ICE_ERR_NO_MEMORY; 1931 1932 /* Prepare buffer to free resource. */ 1933 buf->num_elems = cpu_to_le16(num); 1934 buf->res_type = cpu_to_le16(type); 1935 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1936 1937 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1938 ice_aqc_opc_free_res, NULL); 1939 if (status) 1940 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1941 1942 kfree(buf); 1943 return status; 1944 } 1945 1946 /** 1947 * ice_get_num_per_func - determine number of resources per PF 1948 * @hw: pointer to the HW structure 1949 * @max: value to be evenly split between each PF 1950 * 1951 * Determine the number of valid functions by going through the bitmap returned 1952 * from parsing capabilities and use this to calculate the number of resources 1953 * per PF based on the max value passed in. 1954 */ 1955 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1956 { 1957 u8 funcs; 1958 1959 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1960 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1961 ICE_CAPS_VALID_FUNCS_M); 1962 1963 if (!funcs) 1964 return 0; 1965 1966 return max / funcs; 1967 } 1968 1969 /** 1970 * ice_parse_common_caps - parse common device/function capabilities 1971 * @hw: pointer to the HW struct 1972 * @caps: pointer to common capabilities structure 1973 * @elem: the capability element to parse 1974 * @prefix: message prefix for tracing capabilities 1975 * 1976 * Given a capability element, extract relevant details into the common 1977 * capability structure. 1978 * 1979 * Returns: true if the capability matches one of the common capability ids, 1980 * false otherwise. 1981 */ 1982 static bool 1983 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1984 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1985 { 1986 u32 logical_id = le32_to_cpu(elem->logical_id); 1987 u32 phys_id = le32_to_cpu(elem->phys_id); 1988 u32 number = le32_to_cpu(elem->number); 1989 u16 cap = le16_to_cpu(elem->cap); 1990 bool found = true; 1991 1992 switch (cap) { 1993 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1994 caps->valid_functions = number; 1995 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1996 caps->valid_functions); 1997 break; 1998 case ICE_AQC_CAPS_SRIOV: 1999 caps->sr_iov_1_1 = (number == 1); 2000 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2001 caps->sr_iov_1_1); 2002 break; 2003 case ICE_AQC_CAPS_DCB: 2004 caps->dcb = (number == 1); 2005 caps->active_tc_bitmap = logical_id; 2006 caps->maxtc = phys_id; 2007 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2008 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2009 caps->active_tc_bitmap); 2010 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2011 break; 2012 case ICE_AQC_CAPS_RSS: 2013 caps->rss_table_size = number; 2014 caps->rss_table_entry_width = logical_id; 2015 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2016 caps->rss_table_size); 2017 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2018 caps->rss_table_entry_width); 2019 break; 2020 case ICE_AQC_CAPS_RXQS: 2021 caps->num_rxq = number; 2022 caps->rxq_first_id = phys_id; 2023 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2024 caps->num_rxq); 2025 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2026 caps->rxq_first_id); 2027 break; 2028 case ICE_AQC_CAPS_TXQS: 2029 caps->num_txq = number; 2030 caps->txq_first_id = phys_id; 2031 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2032 caps->num_txq); 2033 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2034 caps->txq_first_id); 2035 break; 2036 case ICE_AQC_CAPS_MSIX: 2037 caps->num_msix_vectors = number; 2038 caps->msix_vector_first_id = phys_id; 2039 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2040 caps->num_msix_vectors); 2041 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2042 caps->msix_vector_first_id); 2043 break; 2044 case ICE_AQC_CAPS_PENDING_NVM_VER: 2045 caps->nvm_update_pending_nvm = true; 2046 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2047 break; 2048 case ICE_AQC_CAPS_PENDING_OROM_VER: 2049 caps->nvm_update_pending_orom = true; 2050 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2051 break; 2052 case ICE_AQC_CAPS_PENDING_NET_VER: 2053 caps->nvm_update_pending_netlist = true; 2054 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2055 break; 2056 case ICE_AQC_CAPS_NVM_MGMT: 2057 caps->nvm_unified_update = 2058 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2059 true : false; 2060 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2061 caps->nvm_unified_update); 2062 break; 2063 case ICE_AQC_CAPS_RDMA: 2064 caps->rdma = (number == 1); 2065 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2066 break; 2067 case ICE_AQC_CAPS_MAX_MTU: 2068 caps->max_mtu = number; 2069 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2070 prefix, caps->max_mtu); 2071 break; 2072 default: 2073 /* Not one of the recognized common capabilities */ 2074 found = false; 2075 } 2076 2077 return found; 2078 } 2079 2080 /** 2081 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2082 * @hw: pointer to the HW structure 2083 * @caps: pointer to capabilities structure to fix 2084 * 2085 * Re-calculate the capabilities that are dependent on the number of physical 2086 * ports; i.e. some features are not supported or function differently on 2087 * devices with more than 4 ports. 2088 */ 2089 static void 2090 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2091 { 2092 /* This assumes device capabilities are always scanned before function 2093 * capabilities during the initialization flow. 2094 */ 2095 if (hw->dev_caps.num_funcs > 4) { 2096 /* Max 4 TCs per port */ 2097 caps->maxtc = 4; 2098 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2099 caps->maxtc); 2100 if (caps->rdma) { 2101 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2102 caps->rdma = 0; 2103 } 2104 2105 /* print message only when processing device capabilities 2106 * during initialization. 2107 */ 2108 if (caps == &hw->dev_caps.common_cap) 2109 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2110 } 2111 } 2112 2113 /** 2114 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2115 * @hw: pointer to the HW struct 2116 * @func_p: pointer to function capabilities structure 2117 * @cap: pointer to the capability element to parse 2118 * 2119 * Extract function capabilities for ICE_AQC_CAPS_VF. 2120 */ 2121 static void 2122 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2123 struct ice_aqc_list_caps_elem *cap) 2124 { 2125 u32 logical_id = le32_to_cpu(cap->logical_id); 2126 u32 number = le32_to_cpu(cap->number); 2127 2128 func_p->num_allocd_vfs = number; 2129 func_p->vf_base_id = logical_id; 2130 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2131 func_p->num_allocd_vfs); 2132 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2133 func_p->vf_base_id); 2134 } 2135 2136 /** 2137 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2138 * @hw: pointer to the HW struct 2139 * @func_p: pointer to function capabilities structure 2140 * @cap: pointer to the capability element to parse 2141 * 2142 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2143 */ 2144 static void 2145 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2146 struct ice_aqc_list_caps_elem *cap) 2147 { 2148 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2149 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2150 le32_to_cpu(cap->number)); 2151 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2152 func_p->guar_num_vsi); 2153 } 2154 2155 /** 2156 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2157 * @hw: pointer to the HW struct 2158 * @func_p: pointer to function capabilities structure 2159 * @cap: pointer to the capability element to parse 2160 * 2161 * Extract function capabilities for ICE_AQC_CAPS_1588. 2162 */ 2163 static void 2164 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2165 struct ice_aqc_list_caps_elem *cap) 2166 { 2167 struct ice_ts_func_info *info = &func_p->ts_func_info; 2168 u32 number = le32_to_cpu(cap->number); 2169 2170 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2171 func_p->common_cap.ieee_1588 = info->ena; 2172 2173 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2174 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2175 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2176 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2177 2178 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2179 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2180 2181 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2182 func_p->common_cap.ieee_1588); 2183 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2184 info->src_tmr_owned); 2185 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2186 info->tmr_ena); 2187 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2188 info->tmr_index_owned); 2189 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2190 info->tmr_index_assoc); 2191 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2192 info->clk_freq); 2193 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2194 info->clk_src); 2195 } 2196 2197 /** 2198 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2199 * @hw: pointer to the HW struct 2200 * @func_p: pointer to function capabilities structure 2201 * 2202 * Extract function capabilities for ICE_AQC_CAPS_FD. 2203 */ 2204 static void 2205 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2206 { 2207 u32 reg_val, val; 2208 2209 reg_val = rd32(hw, GLQF_FD_SIZE); 2210 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2211 GLQF_FD_SIZE_FD_GSIZE_S; 2212 func_p->fd_fltr_guar = 2213 ice_get_num_per_func(hw, val); 2214 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2215 GLQF_FD_SIZE_FD_BSIZE_S; 2216 func_p->fd_fltr_best_effort = val; 2217 2218 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2219 func_p->fd_fltr_guar); 2220 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2221 func_p->fd_fltr_best_effort); 2222 } 2223 2224 /** 2225 * ice_parse_func_caps - Parse function capabilities 2226 * @hw: pointer to the HW struct 2227 * @func_p: pointer to function capabilities structure 2228 * @buf: buffer containing the function capability records 2229 * @cap_count: the number of capabilities 2230 * 2231 * Helper function to parse function (0x000A) capabilities list. For 2232 * capabilities shared between device and function, this relies on 2233 * ice_parse_common_caps. 2234 * 2235 * Loop through the list of provided capabilities and extract the relevant 2236 * data into the function capabilities structured. 2237 */ 2238 static void 2239 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2240 void *buf, u32 cap_count) 2241 { 2242 struct ice_aqc_list_caps_elem *cap_resp; 2243 u32 i; 2244 2245 cap_resp = buf; 2246 2247 memset(func_p, 0, sizeof(*func_p)); 2248 2249 for (i = 0; i < cap_count; i++) { 2250 u16 cap = le16_to_cpu(cap_resp[i].cap); 2251 bool found; 2252 2253 found = ice_parse_common_caps(hw, &func_p->common_cap, 2254 &cap_resp[i], "func caps"); 2255 2256 switch (cap) { 2257 case ICE_AQC_CAPS_VF: 2258 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2259 break; 2260 case ICE_AQC_CAPS_VSI: 2261 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2262 break; 2263 case ICE_AQC_CAPS_1588: 2264 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2265 break; 2266 case ICE_AQC_CAPS_FD: 2267 ice_parse_fdir_func_caps(hw, func_p); 2268 break; 2269 default: 2270 /* Don't list common capabilities as unknown */ 2271 if (!found) 2272 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2273 i, cap); 2274 break; 2275 } 2276 } 2277 2278 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2279 } 2280 2281 /** 2282 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2283 * @hw: pointer to the HW struct 2284 * @dev_p: pointer to device capabilities structure 2285 * @cap: capability element to parse 2286 * 2287 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2288 */ 2289 static void 2290 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2291 struct ice_aqc_list_caps_elem *cap) 2292 { 2293 u32 number = le32_to_cpu(cap->number); 2294 2295 dev_p->num_funcs = hweight32(number); 2296 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2297 dev_p->num_funcs); 2298 } 2299 2300 /** 2301 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2302 * @hw: pointer to the HW struct 2303 * @dev_p: pointer to device capabilities structure 2304 * @cap: capability element to parse 2305 * 2306 * Parse ICE_AQC_CAPS_VF for device capabilities. 2307 */ 2308 static void 2309 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2310 struct ice_aqc_list_caps_elem *cap) 2311 { 2312 u32 number = le32_to_cpu(cap->number); 2313 2314 dev_p->num_vfs_exposed = number; 2315 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2316 dev_p->num_vfs_exposed); 2317 } 2318 2319 /** 2320 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2321 * @hw: pointer to the HW struct 2322 * @dev_p: pointer to device capabilities structure 2323 * @cap: capability element to parse 2324 * 2325 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2326 */ 2327 static void 2328 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2329 struct ice_aqc_list_caps_elem *cap) 2330 { 2331 u32 number = le32_to_cpu(cap->number); 2332 2333 dev_p->num_vsi_allocd_to_host = number; 2334 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2335 dev_p->num_vsi_allocd_to_host); 2336 } 2337 2338 /** 2339 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2340 * @hw: pointer to the HW struct 2341 * @dev_p: pointer to device capabilities structure 2342 * @cap: capability element to parse 2343 * 2344 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2345 */ 2346 static void 2347 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2348 struct ice_aqc_list_caps_elem *cap) 2349 { 2350 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2351 u32 logical_id = le32_to_cpu(cap->logical_id); 2352 u32 phys_id = le32_to_cpu(cap->phys_id); 2353 u32 number = le32_to_cpu(cap->number); 2354 2355 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2356 dev_p->common_cap.ieee_1588 = info->ena; 2357 2358 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2359 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2360 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2361 2362 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2363 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2364 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2365 2366 info->ena_ports = logical_id; 2367 info->tmr_own_map = phys_id; 2368 2369 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2370 dev_p->common_cap.ieee_1588); 2371 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2372 info->tmr0_owner); 2373 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2374 info->tmr0_owned); 2375 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2376 info->tmr0_ena); 2377 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2378 info->tmr1_owner); 2379 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2380 info->tmr1_owned); 2381 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2382 info->tmr1_ena); 2383 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2384 info->ena_ports); 2385 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2386 info->tmr_own_map); 2387 } 2388 2389 /** 2390 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2391 * @hw: pointer to the HW struct 2392 * @dev_p: pointer to device capabilities structure 2393 * @cap: capability element to parse 2394 * 2395 * Parse ICE_AQC_CAPS_FD for device capabilities. 2396 */ 2397 static void 2398 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2399 struct ice_aqc_list_caps_elem *cap) 2400 { 2401 u32 number = le32_to_cpu(cap->number); 2402 2403 dev_p->num_flow_director_fltr = number; 2404 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2405 dev_p->num_flow_director_fltr); 2406 } 2407 2408 /** 2409 * ice_parse_dev_caps - Parse device capabilities 2410 * @hw: pointer to the HW struct 2411 * @dev_p: pointer to device capabilities structure 2412 * @buf: buffer containing the device capability records 2413 * @cap_count: the number of capabilities 2414 * 2415 * Helper device to parse device (0x000B) capabilities list. For 2416 * capabilities shared between device and function, this relies on 2417 * ice_parse_common_caps. 2418 * 2419 * Loop through the list of provided capabilities and extract the relevant 2420 * data into the device capabilities structured. 2421 */ 2422 static void 2423 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2424 void *buf, u32 cap_count) 2425 { 2426 struct ice_aqc_list_caps_elem *cap_resp; 2427 u32 i; 2428 2429 cap_resp = buf; 2430 2431 memset(dev_p, 0, sizeof(*dev_p)); 2432 2433 for (i = 0; i < cap_count; i++) { 2434 u16 cap = le16_to_cpu(cap_resp[i].cap); 2435 bool found; 2436 2437 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2438 &cap_resp[i], "dev caps"); 2439 2440 switch (cap) { 2441 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2442 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2443 break; 2444 case ICE_AQC_CAPS_VF: 2445 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2446 break; 2447 case ICE_AQC_CAPS_VSI: 2448 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2449 break; 2450 case ICE_AQC_CAPS_1588: 2451 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2452 break; 2453 case ICE_AQC_CAPS_FD: 2454 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2455 break; 2456 default: 2457 /* Don't list common capabilities as unknown */ 2458 if (!found) 2459 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2460 i, cap); 2461 break; 2462 } 2463 } 2464 2465 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2466 } 2467 2468 /** 2469 * ice_aq_list_caps - query function/device capabilities 2470 * @hw: pointer to the HW struct 2471 * @buf: a buffer to hold the capabilities 2472 * @buf_size: size of the buffer 2473 * @cap_count: if not NULL, set to the number of capabilities reported 2474 * @opc: capabilities type to discover, device or function 2475 * @cd: pointer to command details structure or NULL 2476 * 2477 * Get the function (0x000A) or device (0x000B) capabilities description from 2478 * firmware and store it in the buffer. 2479 * 2480 * If the cap_count pointer is not NULL, then it is set to the number of 2481 * capabilities firmware will report. Note that if the buffer size is too 2482 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2483 * cap_count will still be updated in this case. It is recommended that the 2484 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2485 * firmware could return) to avoid this. 2486 */ 2487 enum ice_status 2488 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2489 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2490 { 2491 struct ice_aqc_list_caps *cmd; 2492 struct ice_aq_desc desc; 2493 enum ice_status status; 2494 2495 cmd = &desc.params.get_cap; 2496 2497 if (opc != ice_aqc_opc_list_func_caps && 2498 opc != ice_aqc_opc_list_dev_caps) 2499 return ICE_ERR_PARAM; 2500 2501 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2502 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2503 2504 if (cap_count) 2505 *cap_count = le32_to_cpu(cmd->count); 2506 2507 return status; 2508 } 2509 2510 /** 2511 * ice_discover_dev_caps - Read and extract device capabilities 2512 * @hw: pointer to the hardware structure 2513 * @dev_caps: pointer to device capabilities structure 2514 * 2515 * Read the device capabilities and extract them into the dev_caps structure 2516 * for later use. 2517 */ 2518 enum ice_status 2519 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2520 { 2521 enum ice_status status; 2522 u32 cap_count = 0; 2523 void *cbuf; 2524 2525 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2526 if (!cbuf) 2527 return ICE_ERR_NO_MEMORY; 2528 2529 /* Although the driver doesn't know the number of capabilities the 2530 * device will return, we can simply send a 4KB buffer, the maximum 2531 * possible size that firmware can return. 2532 */ 2533 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2534 2535 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2536 ice_aqc_opc_list_dev_caps, NULL); 2537 if (!status) 2538 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2539 kfree(cbuf); 2540 2541 return status; 2542 } 2543 2544 /** 2545 * ice_discover_func_caps - Read and extract function capabilities 2546 * @hw: pointer to the hardware structure 2547 * @func_caps: pointer to function capabilities structure 2548 * 2549 * Read the function capabilities and extract them into the func_caps structure 2550 * for later use. 2551 */ 2552 static enum ice_status 2553 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2554 { 2555 enum ice_status status; 2556 u32 cap_count = 0; 2557 void *cbuf; 2558 2559 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2560 if (!cbuf) 2561 return ICE_ERR_NO_MEMORY; 2562 2563 /* Although the driver doesn't know the number of capabilities the 2564 * device will return, we can simply send a 4KB buffer, the maximum 2565 * possible size that firmware can return. 2566 */ 2567 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2568 2569 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2570 ice_aqc_opc_list_func_caps, NULL); 2571 if (!status) 2572 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2573 kfree(cbuf); 2574 2575 return status; 2576 } 2577 2578 /** 2579 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2580 * @hw: pointer to the hardware structure 2581 */ 2582 void ice_set_safe_mode_caps(struct ice_hw *hw) 2583 { 2584 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2585 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2586 struct ice_hw_common_caps cached_caps; 2587 u32 num_funcs; 2588 2589 /* cache some func_caps values that should be restored after memset */ 2590 cached_caps = func_caps->common_cap; 2591 2592 /* unset func capabilities */ 2593 memset(func_caps, 0, sizeof(*func_caps)); 2594 2595 #define ICE_RESTORE_FUNC_CAP(name) \ 2596 func_caps->common_cap.name = cached_caps.name 2597 2598 /* restore cached values */ 2599 ICE_RESTORE_FUNC_CAP(valid_functions); 2600 ICE_RESTORE_FUNC_CAP(txq_first_id); 2601 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2602 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2603 ICE_RESTORE_FUNC_CAP(max_mtu); 2604 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2605 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2606 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2607 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2608 2609 /* one Tx and one Rx queue in safe mode */ 2610 func_caps->common_cap.num_rxq = 1; 2611 func_caps->common_cap.num_txq = 1; 2612 2613 /* two MSIX vectors, one for traffic and one for misc causes */ 2614 func_caps->common_cap.num_msix_vectors = 2; 2615 func_caps->guar_num_vsi = 1; 2616 2617 /* cache some dev_caps values that should be restored after memset */ 2618 cached_caps = dev_caps->common_cap; 2619 num_funcs = dev_caps->num_funcs; 2620 2621 /* unset dev capabilities */ 2622 memset(dev_caps, 0, sizeof(*dev_caps)); 2623 2624 #define ICE_RESTORE_DEV_CAP(name) \ 2625 dev_caps->common_cap.name = cached_caps.name 2626 2627 /* restore cached values */ 2628 ICE_RESTORE_DEV_CAP(valid_functions); 2629 ICE_RESTORE_DEV_CAP(txq_first_id); 2630 ICE_RESTORE_DEV_CAP(rxq_first_id); 2631 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2632 ICE_RESTORE_DEV_CAP(max_mtu); 2633 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2634 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2635 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2636 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2637 dev_caps->num_funcs = num_funcs; 2638 2639 /* one Tx and one Rx queue per function in safe mode */ 2640 dev_caps->common_cap.num_rxq = num_funcs; 2641 dev_caps->common_cap.num_txq = num_funcs; 2642 2643 /* two MSIX vectors per function */ 2644 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2645 } 2646 2647 /** 2648 * ice_get_caps - get info about the HW 2649 * @hw: pointer to the hardware structure 2650 */ 2651 enum ice_status ice_get_caps(struct ice_hw *hw) 2652 { 2653 enum ice_status status; 2654 2655 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2656 if (status) 2657 return status; 2658 2659 return ice_discover_func_caps(hw, &hw->func_caps); 2660 } 2661 2662 /** 2663 * ice_aq_manage_mac_write - manage MAC address write command 2664 * @hw: pointer to the HW struct 2665 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2666 * @flags: flags to control write behavior 2667 * @cd: pointer to command details structure or NULL 2668 * 2669 * This function is used to write MAC address to the NVM (0x0108). 2670 */ 2671 enum ice_status 2672 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2673 struct ice_sq_cd *cd) 2674 { 2675 struct ice_aqc_manage_mac_write *cmd; 2676 struct ice_aq_desc desc; 2677 2678 cmd = &desc.params.mac_write; 2679 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2680 2681 cmd->flags = flags; 2682 ether_addr_copy(cmd->mac_addr, mac_addr); 2683 2684 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2685 } 2686 2687 /** 2688 * ice_aq_clear_pxe_mode 2689 * @hw: pointer to the HW struct 2690 * 2691 * Tell the firmware that the driver is taking over from PXE (0x0110). 2692 */ 2693 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2694 { 2695 struct ice_aq_desc desc; 2696 2697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2698 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2699 2700 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2701 } 2702 2703 /** 2704 * ice_clear_pxe_mode - clear pxe operations mode 2705 * @hw: pointer to the HW struct 2706 * 2707 * Make sure all PXE mode settings are cleared, including things 2708 * like descriptor fetch/write-back mode. 2709 */ 2710 void ice_clear_pxe_mode(struct ice_hw *hw) 2711 { 2712 if (ice_check_sq_alive(hw, &hw->adminq)) 2713 ice_aq_clear_pxe_mode(hw); 2714 } 2715 2716 /** 2717 * ice_get_link_speed_based_on_phy_type - returns link speed 2718 * @phy_type_low: lower part of phy_type 2719 * @phy_type_high: higher part of phy_type 2720 * 2721 * This helper function will convert an entry in PHY type structure 2722 * [phy_type_low, phy_type_high] to its corresponding link speed. 2723 * Note: In the structure of [phy_type_low, phy_type_high], there should 2724 * be one bit set, as this function will convert one PHY type to its 2725 * speed. 2726 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2727 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2728 */ 2729 static u16 2730 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2731 { 2732 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2733 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2734 2735 switch (phy_type_low) { 2736 case ICE_PHY_TYPE_LOW_100BASE_TX: 2737 case ICE_PHY_TYPE_LOW_100M_SGMII: 2738 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2739 break; 2740 case ICE_PHY_TYPE_LOW_1000BASE_T: 2741 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2742 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2743 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2744 case ICE_PHY_TYPE_LOW_1G_SGMII: 2745 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2746 break; 2747 case ICE_PHY_TYPE_LOW_2500BASE_T: 2748 case ICE_PHY_TYPE_LOW_2500BASE_X: 2749 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2750 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2751 break; 2752 case ICE_PHY_TYPE_LOW_5GBASE_T: 2753 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2754 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2755 break; 2756 case ICE_PHY_TYPE_LOW_10GBASE_T: 2757 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2758 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2759 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2760 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2761 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2762 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2763 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2764 break; 2765 case ICE_PHY_TYPE_LOW_25GBASE_T: 2766 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2767 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2768 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2769 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2770 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2771 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2772 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2773 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2774 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2775 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2776 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2777 break; 2778 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2779 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2780 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2781 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2782 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2783 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2784 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2785 break; 2786 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2787 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2788 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2789 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2790 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2791 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2792 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2793 case ICE_PHY_TYPE_LOW_50G_AUI2: 2794 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2795 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2796 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2797 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2798 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2799 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2800 case ICE_PHY_TYPE_LOW_50G_AUI1: 2801 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2802 break; 2803 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2804 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2805 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2806 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2807 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2808 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2809 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2810 case ICE_PHY_TYPE_LOW_100G_AUI4: 2811 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2812 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2813 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2814 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2815 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2816 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2817 break; 2818 default: 2819 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2820 break; 2821 } 2822 2823 switch (phy_type_high) { 2824 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2825 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2826 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2827 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2828 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2829 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2830 break; 2831 default: 2832 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2833 break; 2834 } 2835 2836 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2837 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2838 return ICE_AQ_LINK_SPEED_UNKNOWN; 2839 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2840 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2841 return ICE_AQ_LINK_SPEED_UNKNOWN; 2842 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2843 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2844 return speed_phy_type_low; 2845 else 2846 return speed_phy_type_high; 2847 } 2848 2849 /** 2850 * ice_update_phy_type 2851 * @phy_type_low: pointer to the lower part of phy_type 2852 * @phy_type_high: pointer to the higher part of phy_type 2853 * @link_speeds_bitmap: targeted link speeds bitmap 2854 * 2855 * Note: For the link_speeds_bitmap structure, you can check it at 2856 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2857 * link_speeds_bitmap include multiple speeds. 2858 * 2859 * Each entry in this [phy_type_low, phy_type_high] structure will 2860 * present a certain link speed. This helper function will turn on bits 2861 * in [phy_type_low, phy_type_high] structure based on the value of 2862 * link_speeds_bitmap input parameter. 2863 */ 2864 void 2865 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2866 u16 link_speeds_bitmap) 2867 { 2868 u64 pt_high; 2869 u64 pt_low; 2870 int index; 2871 u16 speed; 2872 2873 /* We first check with low part of phy_type */ 2874 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2875 pt_low = BIT_ULL(index); 2876 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2877 2878 if (link_speeds_bitmap & speed) 2879 *phy_type_low |= BIT_ULL(index); 2880 } 2881 2882 /* We then check with high part of phy_type */ 2883 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2884 pt_high = BIT_ULL(index); 2885 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2886 2887 if (link_speeds_bitmap & speed) 2888 *phy_type_high |= BIT_ULL(index); 2889 } 2890 } 2891 2892 /** 2893 * ice_aq_set_phy_cfg 2894 * @hw: pointer to the HW struct 2895 * @pi: port info structure of the interested logical port 2896 * @cfg: structure with PHY configuration data to be set 2897 * @cd: pointer to command details structure or NULL 2898 * 2899 * Set the various PHY configuration parameters supported on the Port. 2900 * One or more of the Set PHY config parameters may be ignored in an MFP 2901 * mode as the PF may not have the privilege to set some of the PHY Config 2902 * parameters. This status will be indicated by the command response (0x0601). 2903 */ 2904 enum ice_status 2905 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2906 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2907 { 2908 struct ice_aq_desc desc; 2909 enum ice_status status; 2910 2911 if (!cfg) 2912 return ICE_ERR_PARAM; 2913 2914 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2915 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2916 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2917 cfg->caps); 2918 2919 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2920 } 2921 2922 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2923 desc.params.set_phy.lport_num = pi->lport; 2924 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2925 2926 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2927 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2928 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2929 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2930 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2931 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2932 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2933 cfg->low_power_ctrl_an); 2934 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2935 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2936 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2937 cfg->link_fec_opt); 2938 2939 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2940 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2941 status = 0; 2942 2943 if (!status) 2944 pi->phy.curr_user_phy_cfg = *cfg; 2945 2946 return status; 2947 } 2948 2949 /** 2950 * ice_update_link_info - update status of the HW network link 2951 * @pi: port info structure of the interested logical port 2952 */ 2953 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2954 { 2955 struct ice_link_status *li; 2956 enum ice_status status; 2957 2958 if (!pi) 2959 return ICE_ERR_PARAM; 2960 2961 li = &pi->phy.link_info; 2962 2963 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2964 if (status) 2965 return status; 2966 2967 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2968 struct ice_aqc_get_phy_caps_data *pcaps; 2969 struct ice_hw *hw; 2970 2971 hw = pi->hw; 2972 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2973 GFP_KERNEL); 2974 if (!pcaps) 2975 return ICE_ERR_NO_MEMORY; 2976 2977 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2978 pcaps, NULL); 2979 2980 devm_kfree(ice_hw_to_dev(hw), pcaps); 2981 } 2982 2983 return status; 2984 } 2985 2986 /** 2987 * ice_cache_phy_user_req 2988 * @pi: port information structure 2989 * @cache_data: PHY logging data 2990 * @cache_mode: PHY logging mode 2991 * 2992 * Log the user request on (FC, FEC, SPEED) for later use. 2993 */ 2994 static void 2995 ice_cache_phy_user_req(struct ice_port_info *pi, 2996 struct ice_phy_cache_mode_data cache_data, 2997 enum ice_phy_cache_mode cache_mode) 2998 { 2999 if (!pi) 3000 return; 3001 3002 switch (cache_mode) { 3003 case ICE_FC_MODE: 3004 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3005 break; 3006 case ICE_SPEED_MODE: 3007 pi->phy.curr_user_speed_req = 3008 cache_data.data.curr_user_speed_req; 3009 break; 3010 case ICE_FEC_MODE: 3011 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3012 break; 3013 default: 3014 break; 3015 } 3016 } 3017 3018 /** 3019 * ice_caps_to_fc_mode 3020 * @caps: PHY capabilities 3021 * 3022 * Convert PHY FC capabilities to ice FC mode 3023 */ 3024 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3025 { 3026 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3027 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3028 return ICE_FC_FULL; 3029 3030 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3031 return ICE_FC_TX_PAUSE; 3032 3033 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3034 return ICE_FC_RX_PAUSE; 3035 3036 return ICE_FC_NONE; 3037 } 3038 3039 /** 3040 * ice_caps_to_fec_mode 3041 * @caps: PHY capabilities 3042 * @fec_options: Link FEC options 3043 * 3044 * Convert PHY FEC capabilities to ice FEC mode 3045 */ 3046 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3047 { 3048 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3049 return ICE_FEC_AUTO; 3050 3051 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3052 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3053 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3054 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3055 return ICE_FEC_BASER; 3056 3057 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3058 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3059 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3060 return ICE_FEC_RS; 3061 3062 return ICE_FEC_NONE; 3063 } 3064 3065 /** 3066 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3067 * @pi: port information structure 3068 * @cfg: PHY configuration data to set FC mode 3069 * @req_mode: FC mode to configure 3070 */ 3071 enum ice_status 3072 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3073 enum ice_fc_mode req_mode) 3074 { 3075 struct ice_phy_cache_mode_data cache_data; 3076 u8 pause_mask = 0x0; 3077 3078 if (!pi || !cfg) 3079 return ICE_ERR_BAD_PTR; 3080 3081 switch (req_mode) { 3082 case ICE_FC_FULL: 3083 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3084 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3085 break; 3086 case ICE_FC_RX_PAUSE: 3087 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3088 break; 3089 case ICE_FC_TX_PAUSE: 3090 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3091 break; 3092 default: 3093 break; 3094 } 3095 3096 /* clear the old pause settings */ 3097 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3098 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3099 3100 /* set the new capabilities */ 3101 cfg->caps |= pause_mask; 3102 3103 /* Cache user FC request */ 3104 cache_data.data.curr_user_fc_req = req_mode; 3105 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3106 3107 return 0; 3108 } 3109 3110 /** 3111 * ice_set_fc 3112 * @pi: port information structure 3113 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3114 * @ena_auto_link_update: enable automatic link update 3115 * 3116 * Set the requested flow control mode. 3117 */ 3118 enum ice_status 3119 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3120 { 3121 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3122 struct ice_aqc_get_phy_caps_data *pcaps; 3123 enum ice_status status; 3124 struct ice_hw *hw; 3125 3126 if (!pi || !aq_failures) 3127 return ICE_ERR_BAD_PTR; 3128 3129 *aq_failures = 0; 3130 hw = pi->hw; 3131 3132 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3133 if (!pcaps) 3134 return ICE_ERR_NO_MEMORY; 3135 3136 /* Get the current PHY config */ 3137 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3138 pcaps, NULL); 3139 if (status) { 3140 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3141 goto out; 3142 } 3143 3144 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3145 3146 /* Configure the set PHY data */ 3147 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3148 if (status) 3149 goto out; 3150 3151 /* If the capabilities have changed, then set the new config */ 3152 if (cfg.caps != pcaps->caps) { 3153 int retry_count, retry_max = 10; 3154 3155 /* Auto restart link so settings take effect */ 3156 if (ena_auto_link_update) 3157 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3158 3159 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3160 if (status) { 3161 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3162 goto out; 3163 } 3164 3165 /* Update the link info 3166 * It sometimes takes a really long time for link to 3167 * come back from the atomic reset. Thus, we wait a 3168 * little bit. 3169 */ 3170 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3171 status = ice_update_link_info(pi); 3172 3173 if (!status) 3174 break; 3175 3176 mdelay(100); 3177 } 3178 3179 if (status) 3180 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3181 } 3182 3183 out: 3184 devm_kfree(ice_hw_to_dev(hw), pcaps); 3185 return status; 3186 } 3187 3188 /** 3189 * ice_phy_caps_equals_cfg 3190 * @phy_caps: PHY capabilities 3191 * @phy_cfg: PHY configuration 3192 * 3193 * Helper function to determine if PHY capabilities matches PHY 3194 * configuration 3195 */ 3196 bool 3197 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3198 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3199 { 3200 u8 caps_mask, cfg_mask; 3201 3202 if (!phy_caps || !phy_cfg) 3203 return false; 3204 3205 /* These bits are not common between capabilities and configuration. 3206 * Do not use them to determine equality. 3207 */ 3208 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3209 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3210 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3211 3212 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3213 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3214 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3215 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3216 phy_caps->eee_cap != phy_cfg->eee_cap || 3217 phy_caps->eeer_value != phy_cfg->eeer_value || 3218 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3219 return false; 3220 3221 return true; 3222 } 3223 3224 /** 3225 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3226 * @pi: port information structure 3227 * @caps: PHY ability structure to copy date from 3228 * @cfg: PHY configuration structure to copy data to 3229 * 3230 * Helper function to copy AQC PHY get ability data to PHY set configuration 3231 * data structure 3232 */ 3233 void 3234 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3235 struct ice_aqc_get_phy_caps_data *caps, 3236 struct ice_aqc_set_phy_cfg_data *cfg) 3237 { 3238 if (!pi || !caps || !cfg) 3239 return; 3240 3241 memset(cfg, 0, sizeof(*cfg)); 3242 cfg->phy_type_low = caps->phy_type_low; 3243 cfg->phy_type_high = caps->phy_type_high; 3244 cfg->caps = caps->caps; 3245 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3246 cfg->eee_cap = caps->eee_cap; 3247 cfg->eeer_value = caps->eeer_value; 3248 cfg->link_fec_opt = caps->link_fec_options; 3249 cfg->module_compliance_enforcement = 3250 caps->module_compliance_enforcement; 3251 } 3252 3253 /** 3254 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3255 * @pi: port information structure 3256 * @cfg: PHY configuration data to set FEC mode 3257 * @fec: FEC mode to configure 3258 */ 3259 enum ice_status 3260 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3261 enum ice_fec_mode fec) 3262 { 3263 struct ice_aqc_get_phy_caps_data *pcaps; 3264 enum ice_status status; 3265 struct ice_hw *hw; 3266 3267 if (!pi || !cfg) 3268 return ICE_ERR_BAD_PTR; 3269 3270 hw = pi->hw; 3271 3272 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3273 if (!pcaps) 3274 return ICE_ERR_NO_MEMORY; 3275 3276 status = ice_aq_get_phy_caps(pi, false, 3277 (ice_fw_supports_report_dflt_cfg(hw) ? 3278 ICE_AQC_REPORT_DFLT_CFG : 3279 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3280 if (status) 3281 goto out; 3282 3283 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3284 cfg->link_fec_opt = pcaps->link_fec_options; 3285 3286 switch (fec) { 3287 case ICE_FEC_BASER: 3288 /* Clear RS bits, and AND BASE-R ability 3289 * bits and OR request bits. 3290 */ 3291 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3292 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3293 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3294 ICE_AQC_PHY_FEC_25G_KR_REQ; 3295 break; 3296 case ICE_FEC_RS: 3297 /* Clear BASE-R bits, and AND RS ability 3298 * bits and OR request bits. 3299 */ 3300 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3301 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3302 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3303 break; 3304 case ICE_FEC_NONE: 3305 /* Clear all FEC option bits. */ 3306 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3307 break; 3308 case ICE_FEC_AUTO: 3309 /* AND auto FEC bit, and all caps bits. */ 3310 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3311 cfg->link_fec_opt |= pcaps->link_fec_options; 3312 break; 3313 default: 3314 status = ICE_ERR_PARAM; 3315 break; 3316 } 3317 3318 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3319 !ice_fw_supports_report_dflt_cfg(hw)) { 3320 struct ice_link_default_override_tlv tlv; 3321 3322 if (ice_get_link_default_override(&tlv, pi)) 3323 goto out; 3324 3325 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3326 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3327 cfg->link_fec_opt = tlv.fec_options; 3328 } 3329 3330 out: 3331 kfree(pcaps); 3332 3333 return status; 3334 } 3335 3336 /** 3337 * ice_get_link_status - get status of the HW network link 3338 * @pi: port information structure 3339 * @link_up: pointer to bool (true/false = linkup/linkdown) 3340 * 3341 * Variable link_up is true if link is up, false if link is down. 3342 * The variable link_up is invalid if status is non zero. As a 3343 * result of this call, link status reporting becomes enabled 3344 */ 3345 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3346 { 3347 struct ice_phy_info *phy_info; 3348 enum ice_status status = 0; 3349 3350 if (!pi || !link_up) 3351 return ICE_ERR_PARAM; 3352 3353 phy_info = &pi->phy; 3354 3355 if (phy_info->get_link_info) { 3356 status = ice_update_link_info(pi); 3357 3358 if (status) 3359 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3360 status); 3361 } 3362 3363 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3364 3365 return status; 3366 } 3367 3368 /** 3369 * ice_aq_set_link_restart_an 3370 * @pi: pointer to the port information structure 3371 * @ena_link: if true: enable link, if false: disable link 3372 * @cd: pointer to command details structure or NULL 3373 * 3374 * Sets up the link and restarts the Auto-Negotiation over the link. 3375 */ 3376 enum ice_status 3377 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3378 struct ice_sq_cd *cd) 3379 { 3380 struct ice_aqc_restart_an *cmd; 3381 struct ice_aq_desc desc; 3382 3383 cmd = &desc.params.restart_an; 3384 3385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3386 3387 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3388 cmd->lport_num = pi->lport; 3389 if (ena_link) 3390 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3391 else 3392 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3393 3394 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3395 } 3396 3397 /** 3398 * ice_aq_set_event_mask 3399 * @hw: pointer to the HW struct 3400 * @port_num: port number of the physical function 3401 * @mask: event mask to be set 3402 * @cd: pointer to command details structure or NULL 3403 * 3404 * Set event mask (0x0613) 3405 */ 3406 enum ice_status 3407 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3408 struct ice_sq_cd *cd) 3409 { 3410 struct ice_aqc_set_event_mask *cmd; 3411 struct ice_aq_desc desc; 3412 3413 cmd = &desc.params.set_event_mask; 3414 3415 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3416 3417 cmd->lport_num = port_num; 3418 3419 cmd->event_mask = cpu_to_le16(mask); 3420 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3421 } 3422 3423 /** 3424 * ice_aq_set_mac_loopback 3425 * @hw: pointer to the HW struct 3426 * @ena_lpbk: Enable or Disable loopback 3427 * @cd: pointer to command details structure or NULL 3428 * 3429 * Enable/disable loopback on a given port 3430 */ 3431 enum ice_status 3432 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3433 { 3434 struct ice_aqc_set_mac_lb *cmd; 3435 struct ice_aq_desc desc; 3436 3437 cmd = &desc.params.set_mac_lb; 3438 3439 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3440 if (ena_lpbk) 3441 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3442 3443 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3444 } 3445 3446 /** 3447 * ice_aq_set_port_id_led 3448 * @pi: pointer to the port information 3449 * @is_orig_mode: is this LED set to original mode (by the net-list) 3450 * @cd: pointer to command details structure or NULL 3451 * 3452 * Set LED value for the given port (0x06e9) 3453 */ 3454 enum ice_status 3455 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3456 struct ice_sq_cd *cd) 3457 { 3458 struct ice_aqc_set_port_id_led *cmd; 3459 struct ice_hw *hw = pi->hw; 3460 struct ice_aq_desc desc; 3461 3462 cmd = &desc.params.set_port_id_led; 3463 3464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3465 3466 if (is_orig_mode) 3467 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3468 else 3469 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3470 3471 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3472 } 3473 3474 /** 3475 * ice_aq_sff_eeprom 3476 * @hw: pointer to the HW struct 3477 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3478 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3479 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3480 * @page: QSFP page 3481 * @set_page: set or ignore the page 3482 * @data: pointer to data buffer to be read/written to the I2C device. 3483 * @length: 1-16 for read, 1 for write. 3484 * @write: 0 read, 1 for write. 3485 * @cd: pointer to command details structure or NULL 3486 * 3487 * Read/Write SFF EEPROM (0x06EE) 3488 */ 3489 enum ice_status 3490 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3491 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3492 bool write, struct ice_sq_cd *cd) 3493 { 3494 struct ice_aqc_sff_eeprom *cmd; 3495 struct ice_aq_desc desc; 3496 enum ice_status status; 3497 3498 if (!data || (mem_addr & 0xff00)) 3499 return ICE_ERR_PARAM; 3500 3501 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3502 cmd = &desc.params.read_write_sff_param; 3503 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3504 cmd->lport_num = (u8)(lport & 0xff); 3505 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3506 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3507 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3508 ((set_page << 3509 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3510 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3511 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3512 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3513 if (write) 3514 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3515 3516 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3517 return status; 3518 } 3519 3520 /** 3521 * __ice_aq_get_set_rss_lut 3522 * @hw: pointer to the hardware structure 3523 * @params: RSS LUT parameters 3524 * @set: set true to set the table, false to get the table 3525 * 3526 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3527 */ 3528 static enum ice_status 3529 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3530 { 3531 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3532 struct ice_aqc_get_set_rss_lut *cmd_resp; 3533 struct ice_aq_desc desc; 3534 enum ice_status status; 3535 u8 *lut; 3536 3537 if (!params) 3538 return ICE_ERR_PARAM; 3539 3540 vsi_handle = params->vsi_handle; 3541 lut = params->lut; 3542 3543 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3544 return ICE_ERR_PARAM; 3545 3546 lut_size = params->lut_size; 3547 lut_type = params->lut_type; 3548 glob_lut_idx = params->global_lut_id; 3549 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3550 3551 cmd_resp = &desc.params.get_set_rss_lut; 3552 3553 if (set) { 3554 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3555 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3556 } else { 3557 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3558 } 3559 3560 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3561 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3562 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3563 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3564 3565 switch (lut_type) { 3566 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3567 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3568 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3569 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3570 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3571 break; 3572 default: 3573 status = ICE_ERR_PARAM; 3574 goto ice_aq_get_set_rss_lut_exit; 3575 } 3576 3577 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3578 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3579 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3580 3581 if (!set) 3582 goto ice_aq_get_set_rss_lut_send; 3583 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3584 if (!set) 3585 goto ice_aq_get_set_rss_lut_send; 3586 } else { 3587 goto ice_aq_get_set_rss_lut_send; 3588 } 3589 3590 /* LUT size is only valid for Global and PF table types */ 3591 switch (lut_size) { 3592 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3593 break; 3594 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3595 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3596 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3597 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3598 break; 3599 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3600 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3601 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3602 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3603 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3604 break; 3605 } 3606 fallthrough; 3607 default: 3608 status = ICE_ERR_PARAM; 3609 goto ice_aq_get_set_rss_lut_exit; 3610 } 3611 3612 ice_aq_get_set_rss_lut_send: 3613 cmd_resp->flags = cpu_to_le16(flags); 3614 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3615 3616 ice_aq_get_set_rss_lut_exit: 3617 return status; 3618 } 3619 3620 /** 3621 * ice_aq_get_rss_lut 3622 * @hw: pointer to the hardware structure 3623 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3624 * 3625 * get the RSS lookup table, PF or VSI type 3626 */ 3627 enum ice_status 3628 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3629 { 3630 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3631 } 3632 3633 /** 3634 * ice_aq_set_rss_lut 3635 * @hw: pointer to the hardware structure 3636 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3637 * 3638 * set the RSS lookup table, PF or VSI type 3639 */ 3640 enum ice_status 3641 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3642 { 3643 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3644 } 3645 3646 /** 3647 * __ice_aq_get_set_rss_key 3648 * @hw: pointer to the HW struct 3649 * @vsi_id: VSI FW index 3650 * @key: pointer to key info struct 3651 * @set: set true to set the key, false to get the key 3652 * 3653 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3654 */ 3655 static enum 3656 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3657 struct ice_aqc_get_set_rss_keys *key, 3658 bool set) 3659 { 3660 struct ice_aqc_get_set_rss_key *cmd_resp; 3661 u16 key_size = sizeof(*key); 3662 struct ice_aq_desc desc; 3663 3664 cmd_resp = &desc.params.get_set_rss_key; 3665 3666 if (set) { 3667 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3668 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3669 } else { 3670 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3671 } 3672 3673 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3674 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3675 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3676 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3677 3678 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3679 } 3680 3681 /** 3682 * ice_aq_get_rss_key 3683 * @hw: pointer to the HW struct 3684 * @vsi_handle: software VSI handle 3685 * @key: pointer to key info struct 3686 * 3687 * get the RSS key per VSI 3688 */ 3689 enum ice_status 3690 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3691 struct ice_aqc_get_set_rss_keys *key) 3692 { 3693 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3694 return ICE_ERR_PARAM; 3695 3696 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3697 key, false); 3698 } 3699 3700 /** 3701 * ice_aq_set_rss_key 3702 * @hw: pointer to the HW struct 3703 * @vsi_handle: software VSI handle 3704 * @keys: pointer to key info struct 3705 * 3706 * set the RSS key per VSI 3707 */ 3708 enum ice_status 3709 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3710 struct ice_aqc_get_set_rss_keys *keys) 3711 { 3712 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3713 return ICE_ERR_PARAM; 3714 3715 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3716 keys, true); 3717 } 3718 3719 /** 3720 * ice_aq_add_lan_txq 3721 * @hw: pointer to the hardware structure 3722 * @num_qgrps: Number of added queue groups 3723 * @qg_list: list of queue groups to be added 3724 * @buf_size: size of buffer for indirect command 3725 * @cd: pointer to command details structure or NULL 3726 * 3727 * Add Tx LAN queue (0x0C30) 3728 * 3729 * NOTE: 3730 * Prior to calling add Tx LAN queue: 3731 * Initialize the following as part of the Tx queue context: 3732 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3733 * Cache profile and Packet shaper profile. 3734 * 3735 * After add Tx LAN queue AQ command is completed: 3736 * Interrupts should be associated with specific queues, 3737 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3738 * flow. 3739 */ 3740 static enum ice_status 3741 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3742 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3743 struct ice_sq_cd *cd) 3744 { 3745 struct ice_aqc_add_tx_qgrp *list; 3746 struct ice_aqc_add_txqs *cmd; 3747 struct ice_aq_desc desc; 3748 u16 i, sum_size = 0; 3749 3750 cmd = &desc.params.add_txqs; 3751 3752 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3753 3754 if (!qg_list) 3755 return ICE_ERR_PARAM; 3756 3757 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3758 return ICE_ERR_PARAM; 3759 3760 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3761 sum_size += struct_size(list, txqs, list->num_txqs); 3762 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3763 list->num_txqs); 3764 } 3765 3766 if (buf_size != sum_size) 3767 return ICE_ERR_PARAM; 3768 3769 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3770 3771 cmd->num_qgrps = num_qgrps; 3772 3773 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3774 } 3775 3776 /** 3777 * ice_aq_dis_lan_txq 3778 * @hw: pointer to the hardware structure 3779 * @num_qgrps: number of groups in the list 3780 * @qg_list: the list of groups to disable 3781 * @buf_size: the total size of the qg_list buffer in bytes 3782 * @rst_src: if called due to reset, specifies the reset source 3783 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3784 * @cd: pointer to command details structure or NULL 3785 * 3786 * Disable LAN Tx queue (0x0C31) 3787 */ 3788 static enum ice_status 3789 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3790 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3791 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3792 struct ice_sq_cd *cd) 3793 { 3794 struct ice_aqc_dis_txq_item *item; 3795 struct ice_aqc_dis_txqs *cmd; 3796 struct ice_aq_desc desc; 3797 enum ice_status status; 3798 u16 i, sz = 0; 3799 3800 cmd = &desc.params.dis_txqs; 3801 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3802 3803 /* qg_list can be NULL only in VM/VF reset flow */ 3804 if (!qg_list && !rst_src) 3805 return ICE_ERR_PARAM; 3806 3807 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3808 return ICE_ERR_PARAM; 3809 3810 cmd->num_entries = num_qgrps; 3811 3812 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3813 ICE_AQC_Q_DIS_TIMEOUT_M); 3814 3815 switch (rst_src) { 3816 case ICE_VM_RESET: 3817 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3818 cmd->vmvf_and_timeout |= 3819 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3820 break; 3821 case ICE_VF_RESET: 3822 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3823 /* In this case, FW expects vmvf_num to be absolute VF ID */ 3824 cmd->vmvf_and_timeout |= 3825 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3826 ICE_AQC_Q_DIS_VMVF_NUM_M); 3827 break; 3828 case ICE_NO_RESET: 3829 default: 3830 break; 3831 } 3832 3833 /* flush pipe on time out */ 3834 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3835 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3836 if (!qg_list) 3837 goto do_aq; 3838 3839 /* set RD bit to indicate that command buffer is provided by the driver 3840 * and it needs to be read by the firmware 3841 */ 3842 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3843 3844 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3845 u16 item_size = struct_size(item, q_id, item->num_qs); 3846 3847 /* If the num of queues is even, add 2 bytes of padding */ 3848 if ((item->num_qs % 2) == 0) 3849 item_size += 2; 3850 3851 sz += item_size; 3852 3853 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3854 } 3855 3856 if (buf_size != sz) 3857 return ICE_ERR_PARAM; 3858 3859 do_aq: 3860 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3861 if (status) { 3862 if (!qg_list) 3863 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3864 vmvf_num, hw->adminq.sq_last_status); 3865 else 3866 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3867 le16_to_cpu(qg_list[0].q_id[0]), 3868 hw->adminq.sq_last_status); 3869 } 3870 return status; 3871 } 3872 3873 /** 3874 * ice_aq_add_rdma_qsets 3875 * @hw: pointer to the hardware structure 3876 * @num_qset_grps: Number of RDMA Qset groups 3877 * @qset_list: list of Qset groups to be added 3878 * @buf_size: size of buffer for indirect command 3879 * @cd: pointer to command details structure or NULL 3880 * 3881 * Add Tx RDMA Qsets (0x0C33) 3882 */ 3883 static int 3884 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 3885 struct ice_aqc_add_rdma_qset_data *qset_list, 3886 u16 buf_size, struct ice_sq_cd *cd) 3887 { 3888 struct ice_aqc_add_rdma_qset_data *list; 3889 struct ice_aqc_add_rdma_qset *cmd; 3890 struct ice_aq_desc desc; 3891 u16 i, sum_size = 0; 3892 3893 cmd = &desc.params.add_rdma_qset; 3894 3895 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 3896 3897 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 3898 return -EINVAL; 3899 3900 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 3901 u16 num_qsets = le16_to_cpu(list->num_qsets); 3902 3903 sum_size += struct_size(list, rdma_qsets, num_qsets); 3904 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 3905 num_qsets); 3906 } 3907 3908 if (buf_size != sum_size) 3909 return -EINVAL; 3910 3911 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3912 3913 cmd->num_qset_grps = num_qset_grps; 3914 3915 return ice_status_to_errno(ice_aq_send_cmd(hw, &desc, qset_list, 3916 buf_size, cd)); 3917 } 3918 3919 /* End of FW Admin Queue command wrappers */ 3920 3921 /** 3922 * ice_write_byte - write a byte to a packed context structure 3923 * @src_ctx: the context structure to read from 3924 * @dest_ctx: the context to be written to 3925 * @ce_info: a description of the struct to be filled 3926 */ 3927 static void 3928 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3929 { 3930 u8 src_byte, dest_byte, mask; 3931 u8 *from, *dest; 3932 u16 shift_width; 3933 3934 /* copy from the next struct field */ 3935 from = src_ctx + ce_info->offset; 3936 3937 /* prepare the bits and mask */ 3938 shift_width = ce_info->lsb % 8; 3939 mask = (u8)(BIT(ce_info->width) - 1); 3940 3941 src_byte = *from; 3942 src_byte &= mask; 3943 3944 /* shift to correct alignment */ 3945 mask <<= shift_width; 3946 src_byte <<= shift_width; 3947 3948 /* get the current bits from the target bit string */ 3949 dest = dest_ctx + (ce_info->lsb / 8); 3950 3951 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3952 3953 dest_byte &= ~mask; /* get the bits not changing */ 3954 dest_byte |= src_byte; /* add in the new bits */ 3955 3956 /* put it all back */ 3957 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3958 } 3959 3960 /** 3961 * ice_write_word - write a word to a packed context structure 3962 * @src_ctx: the context structure to read from 3963 * @dest_ctx: the context to be written to 3964 * @ce_info: a description of the struct to be filled 3965 */ 3966 static void 3967 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3968 { 3969 u16 src_word, mask; 3970 __le16 dest_word; 3971 u8 *from, *dest; 3972 u16 shift_width; 3973 3974 /* copy from the next struct field */ 3975 from = src_ctx + ce_info->offset; 3976 3977 /* prepare the bits and mask */ 3978 shift_width = ce_info->lsb % 8; 3979 mask = BIT(ce_info->width) - 1; 3980 3981 /* don't swizzle the bits until after the mask because the mask bits 3982 * will be in a different bit position on big endian machines 3983 */ 3984 src_word = *(u16 *)from; 3985 src_word &= mask; 3986 3987 /* shift to correct alignment */ 3988 mask <<= shift_width; 3989 src_word <<= shift_width; 3990 3991 /* get the current bits from the target bit string */ 3992 dest = dest_ctx + (ce_info->lsb / 8); 3993 3994 memcpy(&dest_word, dest, sizeof(dest_word)); 3995 3996 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3997 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3998 3999 /* put it all back */ 4000 memcpy(dest, &dest_word, sizeof(dest_word)); 4001 } 4002 4003 /** 4004 * ice_write_dword - write a dword to a packed context structure 4005 * @src_ctx: the context structure to read from 4006 * @dest_ctx: the context to be written to 4007 * @ce_info: a description of the struct to be filled 4008 */ 4009 static void 4010 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4011 { 4012 u32 src_dword, mask; 4013 __le32 dest_dword; 4014 u8 *from, *dest; 4015 u16 shift_width; 4016 4017 /* copy from the next struct field */ 4018 from = src_ctx + ce_info->offset; 4019 4020 /* prepare the bits and mask */ 4021 shift_width = ce_info->lsb % 8; 4022 4023 /* if the field width is exactly 32 on an x86 machine, then the shift 4024 * operation will not work because the SHL instructions count is masked 4025 * to 5 bits so the shift will do nothing 4026 */ 4027 if (ce_info->width < 32) 4028 mask = BIT(ce_info->width) - 1; 4029 else 4030 mask = (u32)~0; 4031 4032 /* don't swizzle the bits until after the mask because the mask bits 4033 * will be in a different bit position on big endian machines 4034 */ 4035 src_dword = *(u32 *)from; 4036 src_dword &= mask; 4037 4038 /* shift to correct alignment */ 4039 mask <<= shift_width; 4040 src_dword <<= shift_width; 4041 4042 /* get the current bits from the target bit string */ 4043 dest = dest_ctx + (ce_info->lsb / 8); 4044 4045 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4046 4047 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4048 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4049 4050 /* put it all back */ 4051 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4052 } 4053 4054 /** 4055 * ice_write_qword - write a qword to a packed context structure 4056 * @src_ctx: the context structure to read from 4057 * @dest_ctx: the context to be written to 4058 * @ce_info: a description of the struct to be filled 4059 */ 4060 static void 4061 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4062 { 4063 u64 src_qword, mask; 4064 __le64 dest_qword; 4065 u8 *from, *dest; 4066 u16 shift_width; 4067 4068 /* copy from the next struct field */ 4069 from = src_ctx + ce_info->offset; 4070 4071 /* prepare the bits and mask */ 4072 shift_width = ce_info->lsb % 8; 4073 4074 /* if the field width is exactly 64 on an x86 machine, then the shift 4075 * operation will not work because the SHL instructions count is masked 4076 * to 6 bits so the shift will do nothing 4077 */ 4078 if (ce_info->width < 64) 4079 mask = BIT_ULL(ce_info->width) - 1; 4080 else 4081 mask = (u64)~0; 4082 4083 /* don't swizzle the bits until after the mask because the mask bits 4084 * will be in a different bit position on big endian machines 4085 */ 4086 src_qword = *(u64 *)from; 4087 src_qword &= mask; 4088 4089 /* shift to correct alignment */ 4090 mask <<= shift_width; 4091 src_qword <<= shift_width; 4092 4093 /* get the current bits from the target bit string */ 4094 dest = dest_ctx + (ce_info->lsb / 8); 4095 4096 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4097 4098 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4099 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4100 4101 /* put it all back */ 4102 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4103 } 4104 4105 /** 4106 * ice_set_ctx - set context bits in packed structure 4107 * @hw: pointer to the hardware structure 4108 * @src_ctx: pointer to a generic non-packed context structure 4109 * @dest_ctx: pointer to memory for the packed structure 4110 * @ce_info: a description of the structure to be transformed 4111 */ 4112 enum ice_status 4113 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4114 const struct ice_ctx_ele *ce_info) 4115 { 4116 int f; 4117 4118 for (f = 0; ce_info[f].width; f++) { 4119 /* We have to deal with each element of the FW response 4120 * using the correct size so that we are correct regardless 4121 * of the endianness of the machine. 4122 */ 4123 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4124 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4125 f, ce_info[f].width, ce_info[f].size_of); 4126 continue; 4127 } 4128 switch (ce_info[f].size_of) { 4129 case sizeof(u8): 4130 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4131 break; 4132 case sizeof(u16): 4133 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4134 break; 4135 case sizeof(u32): 4136 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4137 break; 4138 case sizeof(u64): 4139 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4140 break; 4141 default: 4142 return ICE_ERR_INVAL_SIZE; 4143 } 4144 } 4145 4146 return 0; 4147 } 4148 4149 /** 4150 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4151 * @hw: pointer to the HW struct 4152 * @vsi_handle: software VSI handle 4153 * @tc: TC number 4154 * @q_handle: software queue handle 4155 */ 4156 struct ice_q_ctx * 4157 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4158 { 4159 struct ice_vsi_ctx *vsi; 4160 struct ice_q_ctx *q_ctx; 4161 4162 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4163 if (!vsi) 4164 return NULL; 4165 if (q_handle >= vsi->num_lan_q_entries[tc]) 4166 return NULL; 4167 if (!vsi->lan_q_ctx[tc]) 4168 return NULL; 4169 q_ctx = vsi->lan_q_ctx[tc]; 4170 return &q_ctx[q_handle]; 4171 } 4172 4173 /** 4174 * ice_ena_vsi_txq 4175 * @pi: port information structure 4176 * @vsi_handle: software VSI handle 4177 * @tc: TC number 4178 * @q_handle: software queue handle 4179 * @num_qgrps: Number of added queue groups 4180 * @buf: list of queue groups to be added 4181 * @buf_size: size of buffer for indirect command 4182 * @cd: pointer to command details structure or NULL 4183 * 4184 * This function adds one LAN queue 4185 */ 4186 enum ice_status 4187 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4188 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4189 struct ice_sq_cd *cd) 4190 { 4191 struct ice_aqc_txsched_elem_data node = { 0 }; 4192 struct ice_sched_node *parent; 4193 struct ice_q_ctx *q_ctx; 4194 enum ice_status status; 4195 struct ice_hw *hw; 4196 4197 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4198 return ICE_ERR_CFG; 4199 4200 if (num_qgrps > 1 || buf->num_txqs > 1) 4201 return ICE_ERR_MAX_LIMIT; 4202 4203 hw = pi->hw; 4204 4205 if (!ice_is_vsi_valid(hw, vsi_handle)) 4206 return ICE_ERR_PARAM; 4207 4208 mutex_lock(&pi->sched_lock); 4209 4210 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4211 if (!q_ctx) { 4212 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4213 q_handle); 4214 status = ICE_ERR_PARAM; 4215 goto ena_txq_exit; 4216 } 4217 4218 /* find a parent node */ 4219 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4220 ICE_SCHED_NODE_OWNER_LAN); 4221 if (!parent) { 4222 status = ICE_ERR_PARAM; 4223 goto ena_txq_exit; 4224 } 4225 4226 buf->parent_teid = parent->info.node_teid; 4227 node.parent_teid = parent->info.node_teid; 4228 /* Mark that the values in the "generic" section as valid. The default 4229 * value in the "generic" section is zero. This means that : 4230 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4231 * - 0 priority among siblings, indicated by Bit 1-3. 4232 * - WFQ, indicated by Bit 4. 4233 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4234 * Bit 5-6. 4235 * - Bit 7 is reserved. 4236 * Without setting the generic section as valid in valid_sections, the 4237 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4238 */ 4239 buf->txqs[0].info.valid_sections = 4240 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4241 ICE_AQC_ELEM_VALID_EIR; 4242 buf->txqs[0].info.generic = 0; 4243 buf->txqs[0].info.cir_bw.bw_profile_idx = 4244 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4245 buf->txqs[0].info.cir_bw.bw_alloc = 4246 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4247 buf->txqs[0].info.eir_bw.bw_profile_idx = 4248 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4249 buf->txqs[0].info.eir_bw.bw_alloc = 4250 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4251 4252 /* add the LAN queue */ 4253 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4254 if (status) { 4255 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4256 le16_to_cpu(buf->txqs[0].txq_id), 4257 hw->adminq.sq_last_status); 4258 goto ena_txq_exit; 4259 } 4260 4261 node.node_teid = buf->txqs[0].q_teid; 4262 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4263 q_ctx->q_handle = q_handle; 4264 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4265 4266 /* add a leaf node into scheduler tree queue layer */ 4267 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4268 if (!status) 4269 status = ice_sched_replay_q_bw(pi, q_ctx); 4270 4271 ena_txq_exit: 4272 mutex_unlock(&pi->sched_lock); 4273 return status; 4274 } 4275 4276 /** 4277 * ice_dis_vsi_txq 4278 * @pi: port information structure 4279 * @vsi_handle: software VSI handle 4280 * @tc: TC number 4281 * @num_queues: number of queues 4282 * @q_handles: pointer to software queue handle array 4283 * @q_ids: pointer to the q_id array 4284 * @q_teids: pointer to queue node teids 4285 * @rst_src: if called due to reset, specifies the reset source 4286 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4287 * @cd: pointer to command details structure or NULL 4288 * 4289 * This function removes queues and their corresponding nodes in SW DB 4290 */ 4291 enum ice_status 4292 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4293 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4294 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4295 struct ice_sq_cd *cd) 4296 { 4297 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4298 struct ice_aqc_dis_txq_item *qg_list; 4299 struct ice_q_ctx *q_ctx; 4300 struct ice_hw *hw; 4301 u16 i, buf_size; 4302 4303 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4304 return ICE_ERR_CFG; 4305 4306 hw = pi->hw; 4307 4308 if (!num_queues) { 4309 /* if queue is disabled already yet the disable queue command 4310 * has to be sent to complete the VF reset, then call 4311 * ice_aq_dis_lan_txq without any queue information 4312 */ 4313 if (rst_src) 4314 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4315 vmvf_num, NULL); 4316 return ICE_ERR_CFG; 4317 } 4318 4319 buf_size = struct_size(qg_list, q_id, 1); 4320 qg_list = kzalloc(buf_size, GFP_KERNEL); 4321 if (!qg_list) 4322 return ICE_ERR_NO_MEMORY; 4323 4324 mutex_lock(&pi->sched_lock); 4325 4326 for (i = 0; i < num_queues; i++) { 4327 struct ice_sched_node *node; 4328 4329 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4330 if (!node) 4331 continue; 4332 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4333 if (!q_ctx) { 4334 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4335 q_handles[i]); 4336 continue; 4337 } 4338 if (q_ctx->q_handle != q_handles[i]) { 4339 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4340 q_ctx->q_handle, q_handles[i]); 4341 continue; 4342 } 4343 qg_list->parent_teid = node->info.parent_teid; 4344 qg_list->num_qs = 1; 4345 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4346 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4347 vmvf_num, cd); 4348 4349 if (status) 4350 break; 4351 ice_free_sched_node(pi, node); 4352 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4353 } 4354 mutex_unlock(&pi->sched_lock); 4355 kfree(qg_list); 4356 return status; 4357 } 4358 4359 /** 4360 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4361 * @pi: port information structure 4362 * @vsi_handle: software VSI handle 4363 * @tc_bitmap: TC bitmap 4364 * @maxqs: max queues array per TC 4365 * @owner: LAN or RDMA 4366 * 4367 * This function adds/updates the VSI queues per TC. 4368 */ 4369 static enum ice_status 4370 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4371 u16 *maxqs, u8 owner) 4372 { 4373 enum ice_status status = 0; 4374 u8 i; 4375 4376 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4377 return ICE_ERR_CFG; 4378 4379 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4380 return ICE_ERR_PARAM; 4381 4382 mutex_lock(&pi->sched_lock); 4383 4384 ice_for_each_traffic_class(i) { 4385 /* configuration is possible only if TC node is present */ 4386 if (!ice_sched_get_tc_node(pi, i)) 4387 continue; 4388 4389 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4390 ice_is_tc_ena(tc_bitmap, i)); 4391 if (status) 4392 break; 4393 } 4394 4395 mutex_unlock(&pi->sched_lock); 4396 return status; 4397 } 4398 4399 /** 4400 * ice_cfg_vsi_lan - configure VSI LAN queues 4401 * @pi: port information structure 4402 * @vsi_handle: software VSI handle 4403 * @tc_bitmap: TC bitmap 4404 * @max_lanqs: max LAN queues array per TC 4405 * 4406 * This function adds/updates the VSI LAN queues per TC. 4407 */ 4408 enum ice_status 4409 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4410 u16 *max_lanqs) 4411 { 4412 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4413 ICE_SCHED_NODE_OWNER_LAN); 4414 } 4415 4416 /** 4417 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4418 * @pi: port information structure 4419 * @vsi_handle: software VSI handle 4420 * @tc_bitmap: TC bitmap 4421 * @max_rdmaqs: max RDMA queues array per TC 4422 * 4423 * This function adds/updates the VSI RDMA queues per TC. 4424 */ 4425 int 4426 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4427 u16 *max_rdmaqs) 4428 { 4429 return ice_status_to_errno(ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, 4430 max_rdmaqs, 4431 ICE_SCHED_NODE_OWNER_RDMA)); 4432 } 4433 4434 /** 4435 * ice_ena_vsi_rdma_qset 4436 * @pi: port information structure 4437 * @vsi_handle: software VSI handle 4438 * @tc: TC number 4439 * @rdma_qset: pointer to RDMA Qset 4440 * @num_qsets: number of RDMA Qsets 4441 * @qset_teid: pointer to Qset node TEIDs 4442 * 4443 * This function adds RDMA Qset 4444 */ 4445 int 4446 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4447 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4448 { 4449 struct ice_aqc_txsched_elem_data node = { 0 }; 4450 struct ice_aqc_add_rdma_qset_data *buf; 4451 struct ice_sched_node *parent; 4452 enum ice_status status; 4453 struct ice_hw *hw; 4454 u16 i, buf_size; 4455 int ret; 4456 4457 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4458 return -EIO; 4459 hw = pi->hw; 4460 4461 if (!ice_is_vsi_valid(hw, vsi_handle)) 4462 return -EINVAL; 4463 4464 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4465 buf = kzalloc(buf_size, GFP_KERNEL); 4466 if (!buf) 4467 return -ENOMEM; 4468 mutex_lock(&pi->sched_lock); 4469 4470 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4471 ICE_SCHED_NODE_OWNER_RDMA); 4472 if (!parent) { 4473 ret = -EINVAL; 4474 goto rdma_error_exit; 4475 } 4476 buf->parent_teid = parent->info.node_teid; 4477 node.parent_teid = parent->info.node_teid; 4478 4479 buf->num_qsets = cpu_to_le16(num_qsets); 4480 for (i = 0; i < num_qsets; i++) { 4481 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4482 buf->rdma_qsets[i].info.valid_sections = 4483 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4484 ICE_AQC_ELEM_VALID_EIR; 4485 buf->rdma_qsets[i].info.generic = 0; 4486 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4487 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4488 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4489 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4490 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4491 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4492 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4493 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4494 } 4495 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4496 if (ret) { 4497 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4498 goto rdma_error_exit; 4499 } 4500 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4501 for (i = 0; i < num_qsets; i++) { 4502 node.node_teid = buf->rdma_qsets[i].qset_teid; 4503 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4504 &node); 4505 if (status) { 4506 ret = ice_status_to_errno(status); 4507 break; 4508 } 4509 qset_teid[i] = le32_to_cpu(node.node_teid); 4510 } 4511 rdma_error_exit: 4512 mutex_unlock(&pi->sched_lock); 4513 kfree(buf); 4514 return ret; 4515 } 4516 4517 /** 4518 * ice_dis_vsi_rdma_qset - free RDMA resources 4519 * @pi: port_info struct 4520 * @count: number of RDMA Qsets to free 4521 * @qset_teid: TEID of Qset node 4522 * @q_id: list of queue IDs being disabled 4523 */ 4524 int 4525 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4526 u16 *q_id) 4527 { 4528 struct ice_aqc_dis_txq_item *qg_list; 4529 enum ice_status status = 0; 4530 struct ice_hw *hw; 4531 u16 qg_size; 4532 int i; 4533 4534 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4535 return -EIO; 4536 4537 hw = pi->hw; 4538 4539 qg_size = struct_size(qg_list, q_id, 1); 4540 qg_list = kzalloc(qg_size, GFP_KERNEL); 4541 if (!qg_list) 4542 return -ENOMEM; 4543 4544 mutex_lock(&pi->sched_lock); 4545 4546 for (i = 0; i < count; i++) { 4547 struct ice_sched_node *node; 4548 4549 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4550 if (!node) 4551 continue; 4552 4553 qg_list->parent_teid = node->info.parent_teid; 4554 qg_list->num_qs = 1; 4555 qg_list->q_id[0] = 4556 cpu_to_le16(q_id[i] | 4557 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4558 4559 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4560 ICE_NO_RESET, 0, NULL); 4561 if (status) 4562 break; 4563 4564 ice_free_sched_node(pi, node); 4565 } 4566 4567 mutex_unlock(&pi->sched_lock); 4568 kfree(qg_list); 4569 return ice_status_to_errno(status); 4570 } 4571 4572 /** 4573 * ice_replay_pre_init - replay pre initialization 4574 * @hw: pointer to the HW struct 4575 * 4576 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4577 */ 4578 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4579 { 4580 struct ice_switch_info *sw = hw->switch_info; 4581 u8 i; 4582 4583 /* Delete old entries from replay filter list head if there is any */ 4584 ice_rm_all_sw_replay_rule_info(hw); 4585 /* In start of replay, move entries into replay_rules list, it 4586 * will allow adding rules entries back to filt_rules list, 4587 * which is operational list. 4588 */ 4589 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4590 list_replace_init(&sw->recp_list[i].filt_rules, 4591 &sw->recp_list[i].filt_replay_rules); 4592 ice_sched_replay_agg_vsi_preinit(hw); 4593 4594 return 0; 4595 } 4596 4597 /** 4598 * ice_replay_vsi - replay VSI configuration 4599 * @hw: pointer to the HW struct 4600 * @vsi_handle: driver VSI handle 4601 * 4602 * Restore all VSI configuration after reset. It is required to call this 4603 * function with main VSI first. 4604 */ 4605 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4606 { 4607 enum ice_status status; 4608 4609 if (!ice_is_vsi_valid(hw, vsi_handle)) 4610 return ICE_ERR_PARAM; 4611 4612 /* Replay pre-initialization if there is any */ 4613 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4614 status = ice_replay_pre_init(hw); 4615 if (status) 4616 return status; 4617 } 4618 /* Replay per VSI all RSS configurations */ 4619 status = ice_replay_rss_cfg(hw, vsi_handle); 4620 if (status) 4621 return status; 4622 /* Replay per VSI all filters */ 4623 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4624 if (!status) 4625 status = ice_replay_vsi_agg(hw, vsi_handle); 4626 return status; 4627 } 4628 4629 /** 4630 * ice_replay_post - post replay configuration cleanup 4631 * @hw: pointer to the HW struct 4632 * 4633 * Post replay cleanup. 4634 */ 4635 void ice_replay_post(struct ice_hw *hw) 4636 { 4637 /* Delete old entries from replay filter list head */ 4638 ice_rm_all_sw_replay_rule_info(hw); 4639 ice_sched_replay_agg(hw); 4640 } 4641 4642 /** 4643 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4644 * @hw: ptr to the hardware info 4645 * @reg: offset of 64 bit HW register to read from 4646 * @prev_stat_loaded: bool to specify if previous stats are loaded 4647 * @prev_stat: ptr to previous loaded stat value 4648 * @cur_stat: ptr to current stat value 4649 */ 4650 void 4651 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4652 u64 *prev_stat, u64 *cur_stat) 4653 { 4654 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4655 4656 /* device stats are not reset at PFR, they likely will not be zeroed 4657 * when the driver starts. Thus, save the value from the first read 4658 * without adding to the statistic value so that we report stats which 4659 * count up from zero. 4660 */ 4661 if (!prev_stat_loaded) { 4662 *prev_stat = new_data; 4663 return; 4664 } 4665 4666 /* Calculate the difference between the new and old values, and then 4667 * add it to the software stat value. 4668 */ 4669 if (new_data >= *prev_stat) 4670 *cur_stat += new_data - *prev_stat; 4671 else 4672 /* to manage the potential roll-over */ 4673 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4674 4675 /* Update the previously stored value to prepare for next read */ 4676 *prev_stat = new_data; 4677 } 4678 4679 /** 4680 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4681 * @hw: ptr to the hardware info 4682 * @reg: offset of HW register to read from 4683 * @prev_stat_loaded: bool to specify if previous stats are loaded 4684 * @prev_stat: ptr to previous loaded stat value 4685 * @cur_stat: ptr to current stat value 4686 */ 4687 void 4688 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4689 u64 *prev_stat, u64 *cur_stat) 4690 { 4691 u32 new_data; 4692 4693 new_data = rd32(hw, reg); 4694 4695 /* device stats are not reset at PFR, they likely will not be zeroed 4696 * when the driver starts. Thus, save the value from the first read 4697 * without adding to the statistic value so that we report stats which 4698 * count up from zero. 4699 */ 4700 if (!prev_stat_loaded) { 4701 *prev_stat = new_data; 4702 return; 4703 } 4704 4705 /* Calculate the difference between the new and old values, and then 4706 * add it to the software stat value. 4707 */ 4708 if (new_data >= *prev_stat) 4709 *cur_stat += new_data - *prev_stat; 4710 else 4711 /* to manage the potential roll-over */ 4712 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4713 4714 /* Update the previously stored value to prepare for next read */ 4715 *prev_stat = new_data; 4716 } 4717 4718 /** 4719 * ice_sched_query_elem - query element information from HW 4720 * @hw: pointer to the HW struct 4721 * @node_teid: node TEID to be queried 4722 * @buf: buffer to element information 4723 * 4724 * This function queries HW element information 4725 */ 4726 enum ice_status 4727 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4728 struct ice_aqc_txsched_elem_data *buf) 4729 { 4730 u16 buf_size, num_elem_ret = 0; 4731 enum ice_status status; 4732 4733 buf_size = sizeof(*buf); 4734 memset(buf, 0, buf_size); 4735 buf->node_teid = cpu_to_le32(node_teid); 4736 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4737 NULL); 4738 if (status || num_elem_ret != 1) 4739 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4740 return status; 4741 } 4742 4743 /** 4744 * ice_aq_set_driver_param - Set driver parameter to share via firmware 4745 * @hw: pointer to the HW struct 4746 * @idx: parameter index to set 4747 * @value: the value to set the parameter to 4748 * @cd: pointer to command details structure or NULL 4749 * 4750 * Set the value of one of the software defined parameters. All PFs connected 4751 * to this device can read the value using ice_aq_get_driver_param. 4752 * 4753 * Note that firmware provides no synchronization or locking, and will not 4754 * save the parameter value during a device reset. It is expected that 4755 * a single PF will write the parameter value, while all other PFs will only 4756 * read it. 4757 */ 4758 int 4759 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 4760 u32 value, struct ice_sq_cd *cd) 4761 { 4762 struct ice_aqc_driver_shared_params *cmd; 4763 struct ice_aq_desc desc; 4764 4765 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 4766 return -EIO; 4767 4768 cmd = &desc.params.drv_shared_params; 4769 4770 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 4771 4772 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 4773 cmd->param_indx = idx; 4774 cmd->param_val = cpu_to_le32(value); 4775 4776 return ice_status_to_errno(ice_aq_send_cmd(hw, &desc, NULL, 0, cd)); 4777 } 4778 4779 /** 4780 * ice_aq_get_driver_param - Get driver parameter shared via firmware 4781 * @hw: pointer to the HW struct 4782 * @idx: parameter index to set 4783 * @value: storage to return the shared parameter 4784 * @cd: pointer to command details structure or NULL 4785 * 4786 * Get the value of one of the software defined parameters. 4787 * 4788 * Note that firmware provides no synchronization or locking. It is expected 4789 * that only a single PF will write a given parameter. 4790 */ 4791 int 4792 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 4793 u32 *value, struct ice_sq_cd *cd) 4794 { 4795 struct ice_aqc_driver_shared_params *cmd; 4796 struct ice_aq_desc desc; 4797 enum ice_status status; 4798 4799 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 4800 return -EIO; 4801 4802 cmd = &desc.params.drv_shared_params; 4803 4804 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 4805 4806 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 4807 cmd->param_indx = idx; 4808 4809 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4810 if (status) 4811 return ice_status_to_errno(status); 4812 4813 *value = le32_to_cpu(cmd->param_val); 4814 4815 return 0; 4816 } 4817 4818 /** 4819 * ice_aq_set_gpio 4820 * @hw: pointer to the hw struct 4821 * @gpio_ctrl_handle: GPIO controller node handle 4822 * @pin_idx: IO Number of the GPIO that needs to be set 4823 * @value: SW provide IO value to set in the LSB 4824 * @cd: pointer to command details structure or NULL 4825 * 4826 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 4827 */ 4828 int 4829 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 4830 struct ice_sq_cd *cd) 4831 { 4832 struct ice_aqc_gpio *cmd; 4833 struct ice_aq_desc desc; 4834 4835 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 4836 cmd = &desc.params.read_write_gpio; 4837 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 4838 cmd->gpio_num = pin_idx; 4839 cmd->gpio_val = value ? 1 : 0; 4840 4841 return ice_status_to_errno(ice_aq_send_cmd(hw, &desc, NULL, 0, cd)); 4842 } 4843 4844 /** 4845 * ice_aq_get_gpio 4846 * @hw: pointer to the hw struct 4847 * @gpio_ctrl_handle: GPIO controller node handle 4848 * @pin_idx: IO Number of the GPIO that needs to be set 4849 * @value: IO value read 4850 * @cd: pointer to command details structure or NULL 4851 * 4852 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 4853 * the topology 4854 */ 4855 int 4856 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 4857 bool *value, struct ice_sq_cd *cd) 4858 { 4859 struct ice_aqc_gpio *cmd; 4860 struct ice_aq_desc desc; 4861 enum ice_status status; 4862 4863 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 4864 cmd = &desc.params.read_write_gpio; 4865 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 4866 cmd->gpio_num = pin_idx; 4867 4868 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4869 if (status) 4870 return ice_status_to_errno(status); 4871 4872 *value = !!cmd->gpio_val; 4873 return 0; 4874 } 4875 4876 /** 4877 * ice_fw_supports_link_override 4878 * @hw: pointer to the hardware structure 4879 * 4880 * Checks if the firmware supports link override 4881 */ 4882 bool ice_fw_supports_link_override(struct ice_hw *hw) 4883 { 4884 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4885 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4886 return true; 4887 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4888 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4889 return true; 4890 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4891 return true; 4892 } 4893 4894 return false; 4895 } 4896 4897 /** 4898 * ice_get_link_default_override 4899 * @ldo: pointer to the link default override struct 4900 * @pi: pointer to the port info struct 4901 * 4902 * Gets the link default override for a port 4903 */ 4904 enum ice_status 4905 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4906 struct ice_port_info *pi) 4907 { 4908 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4909 struct ice_hw *hw = pi->hw; 4910 enum ice_status status; 4911 4912 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4913 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4914 if (status) { 4915 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4916 return status; 4917 } 4918 4919 /* Each port has its own config; calculate for our port */ 4920 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4921 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4922 4923 /* link options first */ 4924 status = ice_read_sr_word(hw, tlv_start, &buf); 4925 if (status) { 4926 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4927 return status; 4928 } 4929 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4930 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4931 ICE_LINK_OVERRIDE_PHY_CFG_S; 4932 4933 /* link PHY config */ 4934 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4935 status = ice_read_sr_word(hw, offset, &buf); 4936 if (status) { 4937 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4938 return status; 4939 } 4940 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4941 4942 /* PHY types low */ 4943 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4944 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4945 status = ice_read_sr_word(hw, (offset + i), &buf); 4946 if (status) { 4947 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4948 return status; 4949 } 4950 /* shift 16 bits at a time to fill 64 bits */ 4951 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4952 } 4953 4954 /* PHY types high */ 4955 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4956 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4957 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4958 status = ice_read_sr_word(hw, (offset + i), &buf); 4959 if (status) { 4960 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4961 return status; 4962 } 4963 /* shift 16 bits at a time to fill 64 bits */ 4964 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4965 } 4966 4967 return status; 4968 } 4969 4970 /** 4971 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4972 * @caps: get PHY capability data 4973 */ 4974 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4975 { 4976 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4977 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4978 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4979 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4980 return true; 4981 4982 return false; 4983 } 4984 4985 /** 4986 * ice_aq_set_lldp_mib - Set the LLDP MIB 4987 * @hw: pointer to the HW struct 4988 * @mib_type: Local, Remote or both Local and Remote MIBs 4989 * @buf: pointer to the caller-supplied buffer to store the MIB block 4990 * @buf_size: size of the buffer (in bytes) 4991 * @cd: pointer to command details structure or NULL 4992 * 4993 * Set the LLDP MIB. (0x0A08) 4994 */ 4995 enum ice_status 4996 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4997 struct ice_sq_cd *cd) 4998 { 4999 struct ice_aqc_lldp_set_local_mib *cmd; 5000 struct ice_aq_desc desc; 5001 5002 cmd = &desc.params.lldp_set_mib; 5003 5004 if (buf_size == 0 || !buf) 5005 return ICE_ERR_PARAM; 5006 5007 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5008 5009 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5010 desc.datalen = cpu_to_le16(buf_size); 5011 5012 cmd->type = mib_type; 5013 cmd->length = cpu_to_le16(buf_size); 5014 5015 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5016 } 5017 5018 /** 5019 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5020 * @hw: pointer to HW struct 5021 */ 5022 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5023 { 5024 if (hw->mac_type != ICE_MAC_E810) 5025 return false; 5026 5027 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5028 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5029 return true; 5030 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5031 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5032 return true; 5033 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5034 return true; 5035 } 5036 return false; 5037 } 5038 5039 /** 5040 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5041 * @hw: pointer to HW struct 5042 * @vsi_num: absolute HW index for VSI 5043 * @add: boolean for if adding or removing a filter 5044 */ 5045 enum ice_status 5046 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5047 { 5048 struct ice_aqc_lldp_filter_ctrl *cmd; 5049 struct ice_aq_desc desc; 5050 5051 cmd = &desc.params.lldp_filter_ctrl; 5052 5053 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5054 5055 if (add) 5056 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5057 else 5058 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5059 5060 cmd->vsi_num = cpu_to_le16(vsi_num); 5061 5062 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5063 } 5064 5065 /** 5066 * ice_fw_supports_report_dflt_cfg 5067 * @hw: pointer to the hardware structure 5068 * 5069 * Checks if the firmware supports report default configuration 5070 */ 5071 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5072 { 5073 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5074 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5075 return true; 5076 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5077 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5078 return true; 5079 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5080 return true; 5081 } 5082 return false; 5083 } 5084