1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 static const char * const ice_link_mode_str_low[] = { 12 [0] = "100BASE_TX", 13 [1] = "100M_SGMII", 14 [2] = "1000BASE_T", 15 [3] = "1000BASE_SX", 16 [4] = "1000BASE_LX", 17 [5] = "1000BASE_KX", 18 [6] = "1G_SGMII", 19 [7] = "2500BASE_T", 20 [8] = "2500BASE_X", 21 [9] = "2500BASE_KX", 22 [10] = "5GBASE_T", 23 [11] = "5GBASE_KR", 24 [12] = "10GBASE_T", 25 [13] = "10G_SFI_DA", 26 [14] = "10GBASE_SR", 27 [15] = "10GBASE_LR", 28 [16] = "10GBASE_KR_CR1", 29 [17] = "10G_SFI_AOC_ACC", 30 [18] = "10G_SFI_C2C", 31 [19] = "25GBASE_T", 32 [20] = "25GBASE_CR", 33 [21] = "25GBASE_CR_S", 34 [22] = "25GBASE_CR1", 35 [23] = "25GBASE_SR", 36 [24] = "25GBASE_LR", 37 [25] = "25GBASE_KR", 38 [26] = "25GBASE_KR_S", 39 [27] = "25GBASE_KR1", 40 [28] = "25G_AUI_AOC_ACC", 41 [29] = "25G_AUI_C2C", 42 [30] = "40GBASE_CR4", 43 [31] = "40GBASE_SR4", 44 [32] = "40GBASE_LR4", 45 [33] = "40GBASE_KR4", 46 [34] = "40G_XLAUI_AOC_ACC", 47 [35] = "40G_XLAUI", 48 [36] = "50GBASE_CR2", 49 [37] = "50GBASE_SR2", 50 [38] = "50GBASE_LR2", 51 [39] = "50GBASE_KR2", 52 [40] = "50G_LAUI2_AOC_ACC", 53 [41] = "50G_LAUI2", 54 [42] = "50G_AUI2_AOC_ACC", 55 [43] = "50G_AUI2", 56 [44] = "50GBASE_CP", 57 [45] = "50GBASE_SR", 58 [46] = "50GBASE_FR", 59 [47] = "50GBASE_LR", 60 [48] = "50GBASE_KR_PAM4", 61 [49] = "50G_AUI1_AOC_ACC", 62 [50] = "50G_AUI1", 63 [51] = "100GBASE_CR4", 64 [52] = "100GBASE_SR4", 65 [53] = "100GBASE_LR4", 66 [54] = "100GBASE_KR4", 67 [55] = "100G_CAUI4_AOC_ACC", 68 [56] = "100G_CAUI4", 69 [57] = "100G_AUI4_AOC_ACC", 70 [58] = "100G_AUI4", 71 [59] = "100GBASE_CR_PAM4", 72 [60] = "100GBASE_KR_PAM4", 73 [61] = "100GBASE_CP2", 74 [62] = "100GBASE_SR2", 75 [63] = "100GBASE_DR", 76 }; 77 78 static const char * const ice_link_mode_str_high[] = { 79 [0] = "100GBASE_KR2_PAM4", 80 [1] = "100G_CAUI2_AOC_ACC", 81 [2] = "100G_CAUI2", 82 [3] = "100G_AUI2_AOC_ACC", 83 [4] = "100G_AUI2", 84 }; 85 86 /** 87 * ice_dump_phy_type - helper function to dump phy_type 88 * @hw: pointer to the HW structure 89 * @low: 64 bit value for phy_type_low 90 * @high: 64 bit value for phy_type_high 91 * @prefix: prefix string to differentiate multiple dumps 92 */ 93 static void 94 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 95 { 96 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 97 98 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 99 if (low & BIT_ULL(i)) 100 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 101 prefix, i, ice_link_mode_str_low[i]); 102 } 103 104 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 105 106 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 107 if (high & BIT_ULL(i)) 108 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 109 prefix, i, ice_link_mode_str_high[i]); 110 } 111 } 112 113 /** 114 * ice_set_mac_type - Sets MAC type 115 * @hw: pointer to the HW structure 116 * 117 * This function sets the MAC type of the adapter based on the 118 * vendor ID and device ID stored in the HW structure. 119 */ 120 static int ice_set_mac_type(struct ice_hw *hw) 121 { 122 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 123 return -ENODEV; 124 125 switch (hw->device_id) { 126 case ICE_DEV_ID_E810C_BACKPLANE: 127 case ICE_DEV_ID_E810C_QSFP: 128 case ICE_DEV_ID_E810C_SFP: 129 case ICE_DEV_ID_E810_XXV_BACKPLANE: 130 case ICE_DEV_ID_E810_XXV_QSFP: 131 case ICE_DEV_ID_E810_XXV_SFP: 132 hw->mac_type = ICE_MAC_E810; 133 break; 134 case ICE_DEV_ID_E823C_10G_BASE_T: 135 case ICE_DEV_ID_E823C_BACKPLANE: 136 case ICE_DEV_ID_E823C_QSFP: 137 case ICE_DEV_ID_E823C_SFP: 138 case ICE_DEV_ID_E823C_SGMII: 139 case ICE_DEV_ID_E822C_10G_BASE_T: 140 case ICE_DEV_ID_E822C_BACKPLANE: 141 case ICE_DEV_ID_E822C_QSFP: 142 case ICE_DEV_ID_E822C_SFP: 143 case ICE_DEV_ID_E822C_SGMII: 144 case ICE_DEV_ID_E822L_10G_BASE_T: 145 case ICE_DEV_ID_E822L_BACKPLANE: 146 case ICE_DEV_ID_E822L_SFP: 147 case ICE_DEV_ID_E822L_SGMII: 148 case ICE_DEV_ID_E823L_10G_BASE_T: 149 case ICE_DEV_ID_E823L_1GBE: 150 case ICE_DEV_ID_E823L_BACKPLANE: 151 case ICE_DEV_ID_E823L_QSFP: 152 case ICE_DEV_ID_E823L_SFP: 153 hw->mac_type = ICE_MAC_GENERIC; 154 break; 155 default: 156 hw->mac_type = ICE_MAC_UNKNOWN; 157 break; 158 } 159 160 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 161 return 0; 162 } 163 164 /** 165 * ice_is_e810 166 * @hw: pointer to the hardware structure 167 * 168 * returns true if the device is E810 based, false if not. 169 */ 170 bool ice_is_e810(struct ice_hw *hw) 171 { 172 return hw->mac_type == ICE_MAC_E810; 173 } 174 175 /** 176 * ice_is_e810t 177 * @hw: pointer to the hardware structure 178 * 179 * returns true if the device is E810T based, false if not. 180 */ 181 bool ice_is_e810t(struct ice_hw *hw) 182 { 183 switch (hw->device_id) { 184 case ICE_DEV_ID_E810C_SFP: 185 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || 186 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 187 return true; 188 break; 189 default: 190 break; 191 } 192 193 return false; 194 } 195 196 /** 197 * ice_clear_pf_cfg - Clear PF configuration 198 * @hw: pointer to the hardware structure 199 * 200 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 201 * configuration, flow director filters, etc.). 202 */ 203 int ice_clear_pf_cfg(struct ice_hw *hw) 204 { 205 struct ice_aq_desc desc; 206 207 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 208 209 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 210 } 211 212 /** 213 * ice_aq_manage_mac_read - manage MAC address read command 214 * @hw: pointer to the HW struct 215 * @buf: a virtual buffer to hold the manage MAC read response 216 * @buf_size: Size of the virtual buffer 217 * @cd: pointer to command details structure or NULL 218 * 219 * This function is used to return per PF station MAC address (0x0107). 220 * NOTE: Upon successful completion of this command, MAC address information 221 * is returned in user specified buffer. Please interpret user specified 222 * buffer as "manage_mac_read" response. 223 * Response such as various MAC addresses are stored in HW struct (port.mac) 224 * ice_discover_dev_caps is expected to be called before this function is 225 * called. 226 */ 227 static int 228 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 229 struct ice_sq_cd *cd) 230 { 231 struct ice_aqc_manage_mac_read_resp *resp; 232 struct ice_aqc_manage_mac_read *cmd; 233 struct ice_aq_desc desc; 234 int status; 235 u16 flags; 236 u8 i; 237 238 cmd = &desc.params.mac_read; 239 240 if (buf_size < sizeof(*resp)) 241 return -EINVAL; 242 243 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 244 245 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 246 if (status) 247 return status; 248 249 resp = buf; 250 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 251 252 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 253 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 254 return -EIO; 255 } 256 257 /* A single port can report up to two (LAN and WoL) addresses */ 258 for (i = 0; i < cmd->num_addr; i++) 259 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 260 ether_addr_copy(hw->port_info->mac.lan_addr, 261 resp[i].mac_addr); 262 ether_addr_copy(hw->port_info->mac.perm_addr, 263 resp[i].mac_addr); 264 break; 265 } 266 267 return 0; 268 } 269 270 /** 271 * ice_aq_get_phy_caps - returns PHY capabilities 272 * @pi: port information structure 273 * @qual_mods: report qualified modules 274 * @report_mode: report mode capabilities 275 * @pcaps: structure for PHY capabilities to be filled 276 * @cd: pointer to command details structure or NULL 277 * 278 * Returns the various PHY capabilities supported on the Port (0x0600) 279 */ 280 int 281 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 282 struct ice_aqc_get_phy_caps_data *pcaps, 283 struct ice_sq_cd *cd) 284 { 285 struct ice_aqc_get_phy_caps *cmd; 286 u16 pcaps_size = sizeof(*pcaps); 287 struct ice_aq_desc desc; 288 const char *prefix; 289 struct ice_hw *hw; 290 int status; 291 292 cmd = &desc.params.get_phy; 293 294 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 295 return -EINVAL; 296 hw = pi->hw; 297 298 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 299 !ice_fw_supports_report_dflt_cfg(hw)) 300 return -EINVAL; 301 302 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 303 304 if (qual_mods) 305 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 306 307 cmd->param0 |= cpu_to_le16(report_mode); 308 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 309 310 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 311 312 switch (report_mode) { 313 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 314 prefix = "phy_caps_media"; 315 break; 316 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 317 prefix = "phy_caps_no_media"; 318 break; 319 case ICE_AQC_REPORT_ACTIVE_CFG: 320 prefix = "phy_caps_active"; 321 break; 322 case ICE_AQC_REPORT_DFLT_CFG: 323 prefix = "phy_caps_default"; 324 break; 325 default: 326 prefix = "phy_caps_invalid"; 327 } 328 329 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 330 le64_to_cpu(pcaps->phy_type_high), prefix); 331 332 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 333 prefix, report_mode); 334 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 335 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 336 pcaps->low_power_ctrl_an); 337 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 338 pcaps->eee_cap); 339 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 340 pcaps->eeer_value); 341 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 342 pcaps->link_fec_options); 343 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 344 prefix, pcaps->module_compliance_enforcement); 345 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 346 prefix, pcaps->extended_compliance_code); 347 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 348 pcaps->module_type[0]); 349 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 350 pcaps->module_type[1]); 351 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 352 pcaps->module_type[2]); 353 354 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 355 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 356 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 357 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 358 sizeof(pi->phy.link_info.module_type)); 359 } 360 361 return status; 362 } 363 364 /** 365 * ice_aq_get_link_topo_handle - get link topology node return status 366 * @pi: port information structure 367 * @node_type: requested node type 368 * @cd: pointer to command details structure or NULL 369 * 370 * Get link topology node return status for specified node type (0x06E0) 371 * 372 * Node type cage can be used to determine if cage is present. If AQC 373 * returns error (ENOENT), then no cage present. If no cage present, then 374 * connection type is backplane or BASE-T. 375 */ 376 static int 377 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 378 struct ice_sq_cd *cd) 379 { 380 struct ice_aqc_get_link_topo *cmd; 381 struct ice_aq_desc desc; 382 383 cmd = &desc.params.get_link_topo; 384 385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 386 387 cmd->addr.topo_params.node_type_ctx = 388 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 389 ICE_AQC_LINK_TOPO_NODE_CTX_S); 390 391 /* set node type */ 392 cmd->addr.topo_params.node_type_ctx |= 393 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 394 395 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 396 } 397 398 /** 399 * ice_is_media_cage_present 400 * @pi: port information structure 401 * 402 * Returns true if media cage is present, else false. If no cage, then 403 * media type is backplane or BASE-T. 404 */ 405 static bool ice_is_media_cage_present(struct ice_port_info *pi) 406 { 407 /* Node type cage can be used to determine if cage is present. If AQC 408 * returns error (ENOENT), then no cage present. If no cage present then 409 * connection type is backplane or BASE-T. 410 */ 411 return !ice_aq_get_link_topo_handle(pi, 412 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 413 NULL); 414 } 415 416 /** 417 * ice_get_media_type - Gets media type 418 * @pi: port information structure 419 */ 420 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 421 { 422 struct ice_link_status *hw_link_info; 423 424 if (!pi) 425 return ICE_MEDIA_UNKNOWN; 426 427 hw_link_info = &pi->phy.link_info; 428 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 429 /* If more than one media type is selected, report unknown */ 430 return ICE_MEDIA_UNKNOWN; 431 432 if (hw_link_info->phy_type_low) { 433 /* 1G SGMII is a special case where some DA cable PHYs 434 * may show this as an option when it really shouldn't 435 * be since SGMII is meant to be between a MAC and a PHY 436 * in a backplane. Try to detect this case and handle it 437 */ 438 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 439 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 440 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 441 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 442 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 443 return ICE_MEDIA_DA; 444 445 switch (hw_link_info->phy_type_low) { 446 case ICE_PHY_TYPE_LOW_1000BASE_SX: 447 case ICE_PHY_TYPE_LOW_1000BASE_LX: 448 case ICE_PHY_TYPE_LOW_10GBASE_SR: 449 case ICE_PHY_TYPE_LOW_10GBASE_LR: 450 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 451 case ICE_PHY_TYPE_LOW_25GBASE_SR: 452 case ICE_PHY_TYPE_LOW_25GBASE_LR: 453 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 454 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 455 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 456 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 457 case ICE_PHY_TYPE_LOW_50GBASE_SR: 458 case ICE_PHY_TYPE_LOW_50GBASE_FR: 459 case ICE_PHY_TYPE_LOW_50GBASE_LR: 460 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 461 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 462 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 463 case ICE_PHY_TYPE_LOW_100GBASE_DR: 464 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 465 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 466 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 467 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 468 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 469 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 470 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 471 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 472 return ICE_MEDIA_FIBER; 473 case ICE_PHY_TYPE_LOW_100BASE_TX: 474 case ICE_PHY_TYPE_LOW_1000BASE_T: 475 case ICE_PHY_TYPE_LOW_2500BASE_T: 476 case ICE_PHY_TYPE_LOW_5GBASE_T: 477 case ICE_PHY_TYPE_LOW_10GBASE_T: 478 case ICE_PHY_TYPE_LOW_25GBASE_T: 479 return ICE_MEDIA_BASET; 480 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 481 case ICE_PHY_TYPE_LOW_25GBASE_CR: 482 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 483 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 484 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 485 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 486 case ICE_PHY_TYPE_LOW_50GBASE_CP: 487 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 488 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 489 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 490 return ICE_MEDIA_DA; 491 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 492 case ICE_PHY_TYPE_LOW_40G_XLAUI: 493 case ICE_PHY_TYPE_LOW_50G_LAUI2: 494 case ICE_PHY_TYPE_LOW_50G_AUI2: 495 case ICE_PHY_TYPE_LOW_50G_AUI1: 496 case ICE_PHY_TYPE_LOW_100G_AUI4: 497 case ICE_PHY_TYPE_LOW_100G_CAUI4: 498 if (ice_is_media_cage_present(pi)) 499 return ICE_MEDIA_DA; 500 fallthrough; 501 case ICE_PHY_TYPE_LOW_1000BASE_KX: 502 case ICE_PHY_TYPE_LOW_2500BASE_KX: 503 case ICE_PHY_TYPE_LOW_2500BASE_X: 504 case ICE_PHY_TYPE_LOW_5GBASE_KR: 505 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 506 case ICE_PHY_TYPE_LOW_25GBASE_KR: 507 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 508 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 509 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 510 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 511 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 512 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 513 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 514 return ICE_MEDIA_BACKPLANE; 515 } 516 } else { 517 switch (hw_link_info->phy_type_high) { 518 case ICE_PHY_TYPE_HIGH_100G_AUI2: 519 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 520 if (ice_is_media_cage_present(pi)) 521 return ICE_MEDIA_DA; 522 fallthrough; 523 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 524 return ICE_MEDIA_BACKPLANE; 525 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 526 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 527 return ICE_MEDIA_FIBER; 528 } 529 } 530 return ICE_MEDIA_UNKNOWN; 531 } 532 533 /** 534 * ice_aq_get_link_info 535 * @pi: port information structure 536 * @ena_lse: enable/disable LinkStatusEvent reporting 537 * @link: pointer to link status structure - optional 538 * @cd: pointer to command details structure or NULL 539 * 540 * Get Link Status (0x607). Returns the link status of the adapter. 541 */ 542 int 543 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 544 struct ice_link_status *link, struct ice_sq_cd *cd) 545 { 546 struct ice_aqc_get_link_status_data link_data = { 0 }; 547 struct ice_aqc_get_link_status *resp; 548 struct ice_link_status *li_old, *li; 549 enum ice_media_type *hw_media_type; 550 struct ice_fc_info *hw_fc_info; 551 bool tx_pause, rx_pause; 552 struct ice_aq_desc desc; 553 struct ice_hw *hw; 554 u16 cmd_flags; 555 int status; 556 557 if (!pi) 558 return -EINVAL; 559 hw = pi->hw; 560 li_old = &pi->phy.link_info_old; 561 hw_media_type = &pi->phy.media_type; 562 li = &pi->phy.link_info; 563 hw_fc_info = &pi->fc; 564 565 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 566 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 567 resp = &desc.params.get_link_status; 568 resp->cmd_flags = cpu_to_le16(cmd_flags); 569 resp->lport_num = pi->lport; 570 571 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 572 573 if (status) 574 return status; 575 576 /* save off old link status information */ 577 *li_old = *li; 578 579 /* update current link status information */ 580 li->link_speed = le16_to_cpu(link_data.link_speed); 581 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 582 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 583 *hw_media_type = ice_get_media_type(pi); 584 li->link_info = link_data.link_info; 585 li->link_cfg_err = link_data.link_cfg_err; 586 li->an_info = link_data.an_info; 587 li->ext_info = link_data.ext_info; 588 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 589 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 590 li->topo_media_conflict = link_data.topo_media_conflict; 591 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 592 ICE_AQ_CFG_PACING_TYPE_M); 593 594 /* update fc info */ 595 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 596 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 597 if (tx_pause && rx_pause) 598 hw_fc_info->current_mode = ICE_FC_FULL; 599 else if (tx_pause) 600 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 601 else if (rx_pause) 602 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 603 else 604 hw_fc_info->current_mode = ICE_FC_NONE; 605 606 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 607 608 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 609 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 610 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 611 (unsigned long long)li->phy_type_low); 612 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 613 (unsigned long long)li->phy_type_high); 614 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 615 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 616 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 617 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 618 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 619 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 620 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 621 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 622 li->max_frame_size); 623 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 624 625 /* save link status information */ 626 if (link) 627 *link = *li; 628 629 /* flag cleared so calling functions don't call AQ again */ 630 pi->phy.get_link_info = false; 631 632 return 0; 633 } 634 635 /** 636 * ice_fill_tx_timer_and_fc_thresh 637 * @hw: pointer to the HW struct 638 * @cmd: pointer to MAC cfg structure 639 * 640 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 641 * descriptor 642 */ 643 static void 644 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 645 struct ice_aqc_set_mac_cfg *cmd) 646 { 647 u16 fc_thres_val, tx_timer_val; 648 u32 val; 649 650 /* We read back the transmit timer and FC threshold value of 651 * LFC. Thus, we will use index = 652 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 653 * 654 * Also, because we are operating on transmit timer and FC 655 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 656 */ 657 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 658 659 /* Retrieve the transmit timer */ 660 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 661 tx_timer_val = val & 662 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 663 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 664 665 /* Retrieve the FC threshold */ 666 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 667 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 668 669 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 670 } 671 672 /** 673 * ice_aq_set_mac_cfg 674 * @hw: pointer to the HW struct 675 * @max_frame_size: Maximum Frame Size to be supported 676 * @cd: pointer to command details structure or NULL 677 * 678 * Set MAC configuration (0x0603) 679 */ 680 int 681 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 682 { 683 struct ice_aqc_set_mac_cfg *cmd; 684 struct ice_aq_desc desc; 685 686 cmd = &desc.params.set_mac_cfg; 687 688 if (max_frame_size == 0) 689 return -EINVAL; 690 691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 692 693 cmd->max_frame_size = cpu_to_le16(max_frame_size); 694 695 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 696 697 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 698 } 699 700 /** 701 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 702 * @hw: pointer to the HW struct 703 */ 704 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 705 { 706 struct ice_switch_info *sw; 707 int status; 708 709 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 710 sizeof(*hw->switch_info), GFP_KERNEL); 711 sw = hw->switch_info; 712 713 if (!sw) 714 return -ENOMEM; 715 716 INIT_LIST_HEAD(&sw->vsi_list_map_head); 717 sw->prof_res_bm_init = 0; 718 719 status = ice_init_def_sw_recp(hw); 720 if (status) { 721 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 722 return status; 723 } 724 return 0; 725 } 726 727 /** 728 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 729 * @hw: pointer to the HW struct 730 */ 731 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 732 { 733 struct ice_switch_info *sw = hw->switch_info; 734 struct ice_vsi_list_map_info *v_pos_map; 735 struct ice_vsi_list_map_info *v_tmp_map; 736 struct ice_sw_recipe *recps; 737 u8 i; 738 739 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 740 list_entry) { 741 list_del(&v_pos_map->list_entry); 742 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 743 } 744 recps = sw->recp_list; 745 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 746 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 747 748 recps[i].root_rid = i; 749 list_for_each_entry_safe(rg_entry, tmprg_entry, 750 &recps[i].rg_list, l_entry) { 751 list_del(&rg_entry->l_entry); 752 devm_kfree(ice_hw_to_dev(hw), rg_entry); 753 } 754 755 if (recps[i].adv_rule) { 756 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 757 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 758 759 mutex_destroy(&recps[i].filt_rule_lock); 760 list_for_each_entry_safe(lst_itr, tmp_entry, 761 &recps[i].filt_rules, 762 list_entry) { 763 list_del(&lst_itr->list_entry); 764 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 765 devm_kfree(ice_hw_to_dev(hw), lst_itr); 766 } 767 } else { 768 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 769 770 mutex_destroy(&recps[i].filt_rule_lock); 771 list_for_each_entry_safe(lst_itr, tmp_entry, 772 &recps[i].filt_rules, 773 list_entry) { 774 list_del(&lst_itr->list_entry); 775 devm_kfree(ice_hw_to_dev(hw), lst_itr); 776 } 777 } 778 if (recps[i].root_buf) 779 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 780 } 781 ice_rm_all_sw_replay_rule_info(hw); 782 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 783 devm_kfree(ice_hw_to_dev(hw), sw); 784 } 785 786 /** 787 * ice_get_fw_log_cfg - get FW logging configuration 788 * @hw: pointer to the HW struct 789 */ 790 static int ice_get_fw_log_cfg(struct ice_hw *hw) 791 { 792 struct ice_aq_desc desc; 793 __le16 *config; 794 int status; 795 u16 size; 796 797 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 798 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 799 if (!config) 800 return -ENOMEM; 801 802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 803 804 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 805 if (!status) { 806 u16 i; 807 808 /* Save FW logging information into the HW structure */ 809 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 810 u16 v, m, flgs; 811 812 v = le16_to_cpu(config[i]); 813 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 814 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 815 816 if (m < ICE_AQC_FW_LOG_ID_MAX) 817 hw->fw_log.evnts[m].cur = flgs; 818 } 819 } 820 821 devm_kfree(ice_hw_to_dev(hw), config); 822 823 return status; 824 } 825 826 /** 827 * ice_cfg_fw_log - configure FW logging 828 * @hw: pointer to the HW struct 829 * @enable: enable certain FW logging events if true, disable all if false 830 * 831 * This function enables/disables the FW logging via Rx CQ events and a UART 832 * port based on predetermined configurations. FW logging via the Rx CQ can be 833 * enabled/disabled for individual PF's. However, FW logging via the UART can 834 * only be enabled/disabled for all PFs on the same device. 835 * 836 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 837 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 838 * before initializing the device. 839 * 840 * When re/configuring FW logging, callers need to update the "cfg" elements of 841 * the hw->fw_log.evnts array with the desired logging event configurations for 842 * modules of interest. When disabling FW logging completely, the callers can 843 * just pass false in the "enable" parameter. On completion, the function will 844 * update the "cur" element of the hw->fw_log.evnts array with the resulting 845 * logging event configurations of the modules that are being re/configured. FW 846 * logging modules that are not part of a reconfiguration operation retain their 847 * previous states. 848 * 849 * Before resetting the device, it is recommended that the driver disables FW 850 * logging before shutting down the control queue. When disabling FW logging 851 * ("enable" = false), the latest configurations of FW logging events stored in 852 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 853 * a device reset. 854 * 855 * When enabling FW logging to emit log messages via the Rx CQ during the 856 * device's initialization phase, a mechanism alternative to interrupt handlers 857 * needs to be used to extract FW log messages from the Rx CQ periodically and 858 * to prevent the Rx CQ from being full and stalling other types of control 859 * messages from FW to SW. Interrupts are typically disabled during the device's 860 * initialization phase. 861 */ 862 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 863 { 864 struct ice_aqc_fw_logging *cmd; 865 u16 i, chgs = 0, len = 0; 866 struct ice_aq_desc desc; 867 __le16 *data = NULL; 868 u8 actv_evnts = 0; 869 void *buf = NULL; 870 int status = 0; 871 872 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 873 return 0; 874 875 /* Disable FW logging only when the control queue is still responsive */ 876 if (!enable && 877 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 878 return 0; 879 880 /* Get current FW log settings */ 881 status = ice_get_fw_log_cfg(hw); 882 if (status) 883 return status; 884 885 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 886 cmd = &desc.params.fw_logging; 887 888 /* Indicate which controls are valid */ 889 if (hw->fw_log.cq_en) 890 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 891 892 if (hw->fw_log.uart_en) 893 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 894 895 if (enable) { 896 /* Fill in an array of entries with FW logging modules and 897 * logging events being reconfigured. 898 */ 899 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 900 u16 val; 901 902 /* Keep track of enabled event types */ 903 actv_evnts |= hw->fw_log.evnts[i].cfg; 904 905 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 906 continue; 907 908 if (!data) { 909 data = devm_kcalloc(ice_hw_to_dev(hw), 910 ICE_AQC_FW_LOG_ID_MAX, 911 sizeof(*data), 912 GFP_KERNEL); 913 if (!data) 914 return -ENOMEM; 915 } 916 917 val = i << ICE_AQC_FW_LOG_ID_S; 918 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 919 data[chgs++] = cpu_to_le16(val); 920 } 921 922 /* Only enable FW logging if at least one module is specified. 923 * If FW logging is currently enabled but all modules are not 924 * enabled to emit log messages, disable FW logging altogether. 925 */ 926 if (actv_evnts) { 927 /* Leave if there is effectively no change */ 928 if (!chgs) 929 goto out; 930 931 if (hw->fw_log.cq_en) 932 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 933 934 if (hw->fw_log.uart_en) 935 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 936 937 buf = data; 938 len = sizeof(*data) * chgs; 939 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 940 } 941 } 942 943 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 944 if (!status) { 945 /* Update the current configuration to reflect events enabled. 946 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 947 * logging mode is enabled for the device. They do not reflect 948 * actual modules being enabled to emit log messages. So, their 949 * values remain unchanged even when all modules are disabled. 950 */ 951 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 952 953 hw->fw_log.actv_evnts = actv_evnts; 954 for (i = 0; i < cnt; i++) { 955 u16 v, m; 956 957 if (!enable) { 958 /* When disabling all FW logging events as part 959 * of device's de-initialization, the original 960 * configurations are retained, and can be used 961 * to reconfigure FW logging later if the device 962 * is re-initialized. 963 */ 964 hw->fw_log.evnts[i].cur = 0; 965 continue; 966 } 967 968 v = le16_to_cpu(data[i]); 969 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 970 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 971 } 972 } 973 974 out: 975 if (data) 976 devm_kfree(ice_hw_to_dev(hw), data); 977 978 return status; 979 } 980 981 /** 982 * ice_output_fw_log 983 * @hw: pointer to the HW struct 984 * @desc: pointer to the AQ message descriptor 985 * @buf: pointer to the buffer accompanying the AQ message 986 * 987 * Formats a FW Log message and outputs it via the standard driver logs. 988 */ 989 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 990 { 991 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 992 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 993 le16_to_cpu(desc->datalen)); 994 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 995 } 996 997 /** 998 * ice_get_itr_intrl_gran 999 * @hw: pointer to the HW struct 1000 * 1001 * Determines the ITR/INTRL granularities based on the maximum aggregate 1002 * bandwidth according to the device's configuration during power-on. 1003 */ 1004 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1005 { 1006 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 1007 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 1008 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 1009 1010 switch (max_agg_bw) { 1011 case ICE_MAX_AGG_BW_200G: 1012 case ICE_MAX_AGG_BW_100G: 1013 case ICE_MAX_AGG_BW_50G: 1014 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1015 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1016 break; 1017 case ICE_MAX_AGG_BW_25G: 1018 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1019 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1020 break; 1021 } 1022 } 1023 1024 /** 1025 * ice_init_hw - main hardware initialization routine 1026 * @hw: pointer to the hardware structure 1027 */ 1028 int ice_init_hw(struct ice_hw *hw) 1029 { 1030 struct ice_aqc_get_phy_caps_data *pcaps; 1031 u16 mac_buf_len; 1032 void *mac_buf; 1033 int status; 1034 1035 /* Set MAC type based on DeviceID */ 1036 status = ice_set_mac_type(hw); 1037 if (status) 1038 return status; 1039 1040 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 1041 PF_FUNC_RID_FUNC_NUM_M) >> 1042 PF_FUNC_RID_FUNC_NUM_S; 1043 1044 status = ice_reset(hw, ICE_RESET_PFR); 1045 if (status) 1046 return status; 1047 1048 ice_get_itr_intrl_gran(hw); 1049 1050 status = ice_create_all_ctrlq(hw); 1051 if (status) 1052 goto err_unroll_cqinit; 1053 1054 /* Enable FW logging. Not fatal if this fails. */ 1055 status = ice_cfg_fw_log(hw, true); 1056 if (status) 1057 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 1058 1059 status = ice_clear_pf_cfg(hw); 1060 if (status) 1061 goto err_unroll_cqinit; 1062 1063 /* Set bit to enable Flow Director filters */ 1064 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1065 INIT_LIST_HEAD(&hw->fdir_list_head); 1066 1067 ice_clear_pxe_mode(hw); 1068 1069 status = ice_init_nvm(hw); 1070 if (status) 1071 goto err_unroll_cqinit; 1072 1073 status = ice_get_caps(hw); 1074 if (status) 1075 goto err_unroll_cqinit; 1076 1077 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1078 sizeof(*hw->port_info), GFP_KERNEL); 1079 if (!hw->port_info) { 1080 status = -ENOMEM; 1081 goto err_unroll_cqinit; 1082 } 1083 1084 /* set the back pointer to HW */ 1085 hw->port_info->hw = hw; 1086 1087 /* Initialize port_info struct with switch configuration data */ 1088 status = ice_get_initial_sw_cfg(hw); 1089 if (status) 1090 goto err_unroll_alloc; 1091 1092 hw->evb_veb = true; 1093 1094 /* Query the allocated resources for Tx scheduler */ 1095 status = ice_sched_query_res_alloc(hw); 1096 if (status) { 1097 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1098 goto err_unroll_alloc; 1099 } 1100 ice_sched_get_psm_clk_freq(hw); 1101 1102 /* Initialize port_info struct with scheduler data */ 1103 status = ice_sched_init_port(hw->port_info); 1104 if (status) 1105 goto err_unroll_sched; 1106 1107 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1108 if (!pcaps) { 1109 status = -ENOMEM; 1110 goto err_unroll_sched; 1111 } 1112 1113 /* Initialize port_info struct with PHY capabilities */ 1114 status = ice_aq_get_phy_caps(hw->port_info, false, 1115 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1116 NULL); 1117 devm_kfree(ice_hw_to_dev(hw), pcaps); 1118 if (status) 1119 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1120 status); 1121 1122 /* Initialize port_info struct with link information */ 1123 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1124 if (status) 1125 goto err_unroll_sched; 1126 1127 /* need a valid SW entry point to build a Tx tree */ 1128 if (!hw->sw_entry_point_layer) { 1129 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1130 status = -EIO; 1131 goto err_unroll_sched; 1132 } 1133 INIT_LIST_HEAD(&hw->agg_list); 1134 /* Initialize max burst size */ 1135 if (!hw->max_burst_size) 1136 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1137 1138 status = ice_init_fltr_mgmt_struct(hw); 1139 if (status) 1140 goto err_unroll_sched; 1141 1142 /* Get MAC information */ 1143 /* A single port can report up to two (LAN and WoL) addresses */ 1144 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1145 sizeof(struct ice_aqc_manage_mac_read_resp), 1146 GFP_KERNEL); 1147 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1148 1149 if (!mac_buf) { 1150 status = -ENOMEM; 1151 goto err_unroll_fltr_mgmt_struct; 1152 } 1153 1154 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1155 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1156 1157 if (status) 1158 goto err_unroll_fltr_mgmt_struct; 1159 /* enable jumbo frame support at MAC level */ 1160 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1161 if (status) 1162 goto err_unroll_fltr_mgmt_struct; 1163 /* Obtain counter base index which would be used by flow director */ 1164 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1165 if (status) 1166 goto err_unroll_fltr_mgmt_struct; 1167 status = ice_init_hw_tbls(hw); 1168 if (status) 1169 goto err_unroll_fltr_mgmt_struct; 1170 mutex_init(&hw->tnl_lock); 1171 return 0; 1172 1173 err_unroll_fltr_mgmt_struct: 1174 ice_cleanup_fltr_mgmt_struct(hw); 1175 err_unroll_sched: 1176 ice_sched_cleanup_all(hw); 1177 err_unroll_alloc: 1178 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1179 err_unroll_cqinit: 1180 ice_destroy_all_ctrlq(hw); 1181 return status; 1182 } 1183 1184 /** 1185 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1186 * @hw: pointer to the hardware structure 1187 * 1188 * This should be called only during nominal operation, not as a result of 1189 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1190 * applicable initializations if it fails for any reason. 1191 */ 1192 void ice_deinit_hw(struct ice_hw *hw) 1193 { 1194 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1195 ice_cleanup_fltr_mgmt_struct(hw); 1196 1197 ice_sched_cleanup_all(hw); 1198 ice_sched_clear_agg(hw); 1199 ice_free_seg(hw); 1200 ice_free_hw_tbls(hw); 1201 mutex_destroy(&hw->tnl_lock); 1202 1203 if (hw->port_info) { 1204 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1205 hw->port_info = NULL; 1206 } 1207 1208 /* Attempt to disable FW logging before shutting down control queues */ 1209 ice_cfg_fw_log(hw, false); 1210 ice_destroy_all_ctrlq(hw); 1211 1212 /* Clear VSI contexts if not already cleared */ 1213 ice_clear_all_vsi_ctx(hw); 1214 } 1215 1216 /** 1217 * ice_check_reset - Check to see if a global reset is complete 1218 * @hw: pointer to the hardware structure 1219 */ 1220 int ice_check_reset(struct ice_hw *hw) 1221 { 1222 u32 cnt, reg = 0, grst_timeout, uld_mask; 1223 1224 /* Poll for Device Active state in case a recent CORER, GLOBR, 1225 * or EMPR has occurred. The grst delay value is in 100ms units. 1226 * Add 1sec for outstanding AQ commands that can take a long time. 1227 */ 1228 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1229 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1230 1231 for (cnt = 0; cnt < grst_timeout; cnt++) { 1232 mdelay(100); 1233 reg = rd32(hw, GLGEN_RSTAT); 1234 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1235 break; 1236 } 1237 1238 if (cnt == grst_timeout) { 1239 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1240 return -EIO; 1241 } 1242 1243 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1244 GLNVM_ULD_PCIER_DONE_1_M |\ 1245 GLNVM_ULD_CORER_DONE_M |\ 1246 GLNVM_ULD_GLOBR_DONE_M |\ 1247 GLNVM_ULD_POR_DONE_M |\ 1248 GLNVM_ULD_POR_DONE_1_M |\ 1249 GLNVM_ULD_PCIER_DONE_2_M) 1250 1251 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1252 GLNVM_ULD_PE_DONE_M : 0); 1253 1254 /* Device is Active; check Global Reset processes are done */ 1255 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1256 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1257 if (reg == uld_mask) { 1258 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1259 break; 1260 } 1261 mdelay(10); 1262 } 1263 1264 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1265 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1266 reg); 1267 return -EIO; 1268 } 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * ice_pf_reset - Reset the PF 1275 * @hw: pointer to the hardware structure 1276 * 1277 * If a global reset has been triggered, this function checks 1278 * for its completion and then issues the PF reset 1279 */ 1280 static int ice_pf_reset(struct ice_hw *hw) 1281 { 1282 u32 cnt, reg; 1283 1284 /* If at function entry a global reset was already in progress, i.e. 1285 * state is not 'device active' or any of the reset done bits are not 1286 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1287 * global reset is done. 1288 */ 1289 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1290 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1291 /* poll on global reset currently in progress until done */ 1292 if (ice_check_reset(hw)) 1293 return -EIO; 1294 1295 return 0; 1296 } 1297 1298 /* Reset the PF */ 1299 reg = rd32(hw, PFGEN_CTRL); 1300 1301 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1302 1303 /* Wait for the PFR to complete. The wait time is the global config lock 1304 * timeout plus the PFR timeout which will account for a possible reset 1305 * that is occurring during a download package operation. 1306 */ 1307 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1308 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1309 reg = rd32(hw, PFGEN_CTRL); 1310 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1311 break; 1312 1313 mdelay(1); 1314 } 1315 1316 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1317 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1318 return -EIO; 1319 } 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * ice_reset - Perform different types of reset 1326 * @hw: pointer to the hardware structure 1327 * @req: reset request 1328 * 1329 * This function triggers a reset as specified by the req parameter. 1330 * 1331 * Note: 1332 * If anything other than a PF reset is triggered, PXE mode is restored. 1333 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1334 * interface has been restored in the rebuild flow. 1335 */ 1336 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1337 { 1338 u32 val = 0; 1339 1340 switch (req) { 1341 case ICE_RESET_PFR: 1342 return ice_pf_reset(hw); 1343 case ICE_RESET_CORER: 1344 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1345 val = GLGEN_RTRIG_CORER_M; 1346 break; 1347 case ICE_RESET_GLOBR: 1348 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1349 val = GLGEN_RTRIG_GLOBR_M; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 val |= rd32(hw, GLGEN_RTRIG); 1356 wr32(hw, GLGEN_RTRIG, val); 1357 ice_flush(hw); 1358 1359 /* wait for the FW to be ready */ 1360 return ice_check_reset(hw); 1361 } 1362 1363 /** 1364 * ice_copy_rxq_ctx_to_hw 1365 * @hw: pointer to the hardware structure 1366 * @ice_rxq_ctx: pointer to the rxq context 1367 * @rxq_index: the index of the Rx queue 1368 * 1369 * Copies rxq context from dense structure to HW register space 1370 */ 1371 static int 1372 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1373 { 1374 u8 i; 1375 1376 if (!ice_rxq_ctx) 1377 return -EINVAL; 1378 1379 if (rxq_index > QRX_CTRL_MAX_INDEX) 1380 return -EINVAL; 1381 1382 /* Copy each dword separately to HW */ 1383 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1384 wr32(hw, QRX_CONTEXT(i, rxq_index), 1385 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1386 1387 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1388 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1389 } 1390 1391 return 0; 1392 } 1393 1394 /* LAN Rx Queue Context */ 1395 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1396 /* Field Width LSB */ 1397 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1398 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1399 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1400 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1401 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1402 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1403 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1404 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1405 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1406 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1407 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1408 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1409 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1410 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1411 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1412 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1413 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1414 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1415 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1416 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1417 { 0 } 1418 }; 1419 1420 /** 1421 * ice_write_rxq_ctx 1422 * @hw: pointer to the hardware structure 1423 * @rlan_ctx: pointer to the rxq context 1424 * @rxq_index: the index of the Rx queue 1425 * 1426 * Converts rxq context from sparse to dense structure and then writes 1427 * it to HW register space and enables the hardware to prefetch descriptors 1428 * instead of only fetching them on demand 1429 */ 1430 int 1431 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1432 u32 rxq_index) 1433 { 1434 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1435 1436 if (!rlan_ctx) 1437 return -EINVAL; 1438 1439 rlan_ctx->prefena = 1; 1440 1441 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1442 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1443 } 1444 1445 /* LAN Tx Queue Context */ 1446 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1447 /* Field Width LSB */ 1448 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1449 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1450 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1451 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1452 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1453 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1454 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1455 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1456 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1457 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1458 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1459 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1460 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1461 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1462 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1463 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1464 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1465 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1466 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1467 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1468 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1469 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1470 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1471 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1472 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1473 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1474 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1475 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1476 { 0 } 1477 }; 1478 1479 /* Sideband Queue command wrappers */ 1480 1481 /** 1482 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1483 * @hw: pointer to the HW struct 1484 * @desc: descriptor describing the command 1485 * @buf: buffer to use for indirect commands (NULL for direct commands) 1486 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1487 * @cd: pointer to command details structure 1488 */ 1489 static int 1490 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1491 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1492 { 1493 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1494 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1495 } 1496 1497 /** 1498 * ice_sbq_rw_reg - Fill Sideband Queue command 1499 * @hw: pointer to the HW struct 1500 * @in: message info to be filled in descriptor 1501 */ 1502 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1503 { 1504 struct ice_sbq_cmd_desc desc = {0}; 1505 struct ice_sbq_msg_req msg = {0}; 1506 u16 msg_len; 1507 int status; 1508 1509 msg_len = sizeof(msg); 1510 1511 msg.dest_dev = in->dest_dev; 1512 msg.opcode = in->opcode; 1513 msg.flags = ICE_SBQ_MSG_FLAGS; 1514 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1515 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1516 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1517 1518 if (in->opcode) 1519 msg.data = cpu_to_le32(in->data); 1520 else 1521 /* data read comes back in completion, so shorten the struct by 1522 * sizeof(msg.data) 1523 */ 1524 msg_len -= sizeof(msg.data); 1525 1526 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1527 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1528 desc.param0.cmd_len = cpu_to_le16(msg_len); 1529 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1530 if (!status && !in->opcode) 1531 in->data = le32_to_cpu 1532 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1533 return status; 1534 } 1535 1536 /* FW Admin Queue command wrappers */ 1537 1538 /* Software lock/mutex that is meant to be held while the Global Config Lock 1539 * in firmware is acquired by the software to prevent most (but not all) types 1540 * of AQ commands from being sent to FW 1541 */ 1542 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1543 1544 /** 1545 * ice_should_retry_sq_send_cmd 1546 * @opcode: AQ opcode 1547 * 1548 * Decide if we should retry the send command routine for the ATQ, depending 1549 * on the opcode. 1550 */ 1551 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1552 { 1553 switch (opcode) { 1554 case ice_aqc_opc_get_link_topo: 1555 case ice_aqc_opc_lldp_stop: 1556 case ice_aqc_opc_lldp_start: 1557 case ice_aqc_opc_lldp_filter_ctrl: 1558 return true; 1559 } 1560 1561 return false; 1562 } 1563 1564 /** 1565 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1566 * @hw: pointer to the HW struct 1567 * @cq: pointer to the specific Control queue 1568 * @desc: prefilled descriptor describing the command 1569 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1570 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1571 * @cd: pointer to command details structure 1572 * 1573 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1574 * Queue if the EBUSY AQ error is returned. 1575 */ 1576 static int 1577 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1578 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1579 struct ice_sq_cd *cd) 1580 { 1581 struct ice_aq_desc desc_cpy; 1582 bool is_cmd_for_retry; 1583 u8 *buf_cpy = NULL; 1584 u8 idx = 0; 1585 u16 opcode; 1586 int status; 1587 1588 opcode = le16_to_cpu(desc->opcode); 1589 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1590 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1591 1592 if (is_cmd_for_retry) { 1593 if (buf) { 1594 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1595 if (!buf_cpy) 1596 return -ENOMEM; 1597 } 1598 1599 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1600 } 1601 1602 do { 1603 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1604 1605 if (!is_cmd_for_retry || !status || 1606 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1607 break; 1608 1609 if (buf_cpy) 1610 memcpy(buf, buf_cpy, buf_size); 1611 1612 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1613 1614 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1615 1616 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1617 1618 kfree(buf_cpy); 1619 1620 return status; 1621 } 1622 1623 /** 1624 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1625 * @hw: pointer to the HW struct 1626 * @desc: descriptor describing the command 1627 * @buf: buffer to use for indirect commands (NULL for direct commands) 1628 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1629 * @cd: pointer to command details structure 1630 * 1631 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1632 */ 1633 int 1634 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1635 u16 buf_size, struct ice_sq_cd *cd) 1636 { 1637 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1638 bool lock_acquired = false; 1639 int status; 1640 1641 /* When a package download is in process (i.e. when the firmware's 1642 * Global Configuration Lock resource is held), only the Download 1643 * Package, Get Version, Get Package Info List, Upload Section, 1644 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1645 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1646 * Recipes to Profile Association, and Release Resource (with resource 1647 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1648 * must block until the package download completes and the Global Config 1649 * Lock is released. See also ice_acquire_global_cfg_lock(). 1650 */ 1651 switch (le16_to_cpu(desc->opcode)) { 1652 case ice_aqc_opc_download_pkg: 1653 case ice_aqc_opc_get_pkg_info_list: 1654 case ice_aqc_opc_get_ver: 1655 case ice_aqc_opc_upload_section: 1656 case ice_aqc_opc_update_pkg: 1657 case ice_aqc_opc_set_port_params: 1658 case ice_aqc_opc_get_vlan_mode_parameters: 1659 case ice_aqc_opc_set_vlan_mode_parameters: 1660 case ice_aqc_opc_add_recipe: 1661 case ice_aqc_opc_recipe_to_profile: 1662 case ice_aqc_opc_get_recipe: 1663 case ice_aqc_opc_get_recipe_to_profile: 1664 break; 1665 case ice_aqc_opc_release_res: 1666 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1667 break; 1668 fallthrough; 1669 default: 1670 mutex_lock(&ice_global_cfg_lock_sw); 1671 lock_acquired = true; 1672 break; 1673 } 1674 1675 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1676 if (lock_acquired) 1677 mutex_unlock(&ice_global_cfg_lock_sw); 1678 1679 return status; 1680 } 1681 1682 /** 1683 * ice_aq_get_fw_ver 1684 * @hw: pointer to the HW struct 1685 * @cd: pointer to command details structure or NULL 1686 * 1687 * Get the firmware version (0x0001) from the admin queue commands 1688 */ 1689 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1690 { 1691 struct ice_aqc_get_ver *resp; 1692 struct ice_aq_desc desc; 1693 int status; 1694 1695 resp = &desc.params.get_ver; 1696 1697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1698 1699 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1700 1701 if (!status) { 1702 hw->fw_branch = resp->fw_branch; 1703 hw->fw_maj_ver = resp->fw_major; 1704 hw->fw_min_ver = resp->fw_minor; 1705 hw->fw_patch = resp->fw_patch; 1706 hw->fw_build = le32_to_cpu(resp->fw_build); 1707 hw->api_branch = resp->api_branch; 1708 hw->api_maj_ver = resp->api_major; 1709 hw->api_min_ver = resp->api_minor; 1710 hw->api_patch = resp->api_patch; 1711 } 1712 1713 return status; 1714 } 1715 1716 /** 1717 * ice_aq_send_driver_ver 1718 * @hw: pointer to the HW struct 1719 * @dv: driver's major, minor version 1720 * @cd: pointer to command details structure or NULL 1721 * 1722 * Send the driver version (0x0002) to the firmware 1723 */ 1724 int 1725 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1726 struct ice_sq_cd *cd) 1727 { 1728 struct ice_aqc_driver_ver *cmd; 1729 struct ice_aq_desc desc; 1730 u16 len; 1731 1732 cmd = &desc.params.driver_ver; 1733 1734 if (!dv) 1735 return -EINVAL; 1736 1737 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1738 1739 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1740 cmd->major_ver = dv->major_ver; 1741 cmd->minor_ver = dv->minor_ver; 1742 cmd->build_ver = dv->build_ver; 1743 cmd->subbuild_ver = dv->subbuild_ver; 1744 1745 len = 0; 1746 while (len < sizeof(dv->driver_string) && 1747 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1748 len++; 1749 1750 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1751 } 1752 1753 /** 1754 * ice_aq_q_shutdown 1755 * @hw: pointer to the HW struct 1756 * @unloading: is the driver unloading itself 1757 * 1758 * Tell the Firmware that we're shutting down the AdminQ and whether 1759 * or not the driver is unloading as well (0x0003). 1760 */ 1761 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1762 { 1763 struct ice_aqc_q_shutdown *cmd; 1764 struct ice_aq_desc desc; 1765 1766 cmd = &desc.params.q_shutdown; 1767 1768 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1769 1770 if (unloading) 1771 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1772 1773 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1774 } 1775 1776 /** 1777 * ice_aq_req_res 1778 * @hw: pointer to the HW struct 1779 * @res: resource ID 1780 * @access: access type 1781 * @sdp_number: resource number 1782 * @timeout: the maximum time in ms that the driver may hold the resource 1783 * @cd: pointer to command details structure or NULL 1784 * 1785 * Requests common resource using the admin queue commands (0x0008). 1786 * When attempting to acquire the Global Config Lock, the driver can 1787 * learn of three states: 1788 * 1) 0 - acquired lock, and can perform download package 1789 * 2) -EIO - did not get lock, driver should fail to load 1790 * 3) -EALREADY - did not get lock, but another driver has 1791 * successfully downloaded the package; the driver does 1792 * not have to download the package and can continue 1793 * loading 1794 * 1795 * Note that if the caller is in an acquire lock, perform action, release lock 1796 * phase of operation, it is possible that the FW may detect a timeout and issue 1797 * a CORER. In this case, the driver will receive a CORER interrupt and will 1798 * have to determine its cause. The calling thread that is handling this flow 1799 * will likely get an error propagated back to it indicating the Download 1800 * Package, Update Package or the Release Resource AQ commands timed out. 1801 */ 1802 static int 1803 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1804 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1805 struct ice_sq_cd *cd) 1806 { 1807 struct ice_aqc_req_res *cmd_resp; 1808 struct ice_aq_desc desc; 1809 int status; 1810 1811 cmd_resp = &desc.params.res_owner; 1812 1813 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1814 1815 cmd_resp->res_id = cpu_to_le16(res); 1816 cmd_resp->access_type = cpu_to_le16(access); 1817 cmd_resp->res_number = cpu_to_le32(sdp_number); 1818 cmd_resp->timeout = cpu_to_le32(*timeout); 1819 *timeout = 0; 1820 1821 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1822 1823 /* The completion specifies the maximum time in ms that the driver 1824 * may hold the resource in the Timeout field. 1825 */ 1826 1827 /* Global config lock response utilizes an additional status field. 1828 * 1829 * If the Global config lock resource is held by some other driver, the 1830 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1831 * and the timeout field indicates the maximum time the current owner 1832 * of the resource has to free it. 1833 */ 1834 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1835 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1836 *timeout = le32_to_cpu(cmd_resp->timeout); 1837 return 0; 1838 } else if (le16_to_cpu(cmd_resp->status) == 1839 ICE_AQ_RES_GLBL_IN_PROG) { 1840 *timeout = le32_to_cpu(cmd_resp->timeout); 1841 return -EIO; 1842 } else if (le16_to_cpu(cmd_resp->status) == 1843 ICE_AQ_RES_GLBL_DONE) { 1844 return -EALREADY; 1845 } 1846 1847 /* invalid FW response, force a timeout immediately */ 1848 *timeout = 0; 1849 return -EIO; 1850 } 1851 1852 /* If the resource is held by some other driver, the command completes 1853 * with a busy return value and the timeout field indicates the maximum 1854 * time the current owner of the resource has to free it. 1855 */ 1856 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1857 *timeout = le32_to_cpu(cmd_resp->timeout); 1858 1859 return status; 1860 } 1861 1862 /** 1863 * ice_aq_release_res 1864 * @hw: pointer to the HW struct 1865 * @res: resource ID 1866 * @sdp_number: resource number 1867 * @cd: pointer to command details structure or NULL 1868 * 1869 * release common resource using the admin queue commands (0x0009) 1870 */ 1871 static int 1872 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1873 struct ice_sq_cd *cd) 1874 { 1875 struct ice_aqc_req_res *cmd; 1876 struct ice_aq_desc desc; 1877 1878 cmd = &desc.params.res_owner; 1879 1880 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1881 1882 cmd->res_id = cpu_to_le16(res); 1883 cmd->res_number = cpu_to_le32(sdp_number); 1884 1885 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1886 } 1887 1888 /** 1889 * ice_acquire_res 1890 * @hw: pointer to the HW structure 1891 * @res: resource ID 1892 * @access: access type (read or write) 1893 * @timeout: timeout in milliseconds 1894 * 1895 * This function will attempt to acquire the ownership of a resource. 1896 */ 1897 int 1898 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1899 enum ice_aq_res_access_type access, u32 timeout) 1900 { 1901 #define ICE_RES_POLLING_DELAY_MS 10 1902 u32 delay = ICE_RES_POLLING_DELAY_MS; 1903 u32 time_left = timeout; 1904 int status; 1905 1906 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1907 1908 /* A return code of -EALREADY means that another driver has 1909 * previously acquired the resource and performed any necessary updates; 1910 * in this case the caller does not obtain the resource and has no 1911 * further work to do. 1912 */ 1913 if (status == -EALREADY) 1914 goto ice_acquire_res_exit; 1915 1916 if (status) 1917 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1918 1919 /* If necessary, poll until the current lock owner timeouts */ 1920 timeout = time_left; 1921 while (status && timeout && time_left) { 1922 mdelay(delay); 1923 timeout = (timeout > delay) ? timeout - delay : 0; 1924 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1925 1926 if (status == -EALREADY) 1927 /* lock free, but no work to do */ 1928 break; 1929 1930 if (!status) 1931 /* lock acquired */ 1932 break; 1933 } 1934 if (status && status != -EALREADY) 1935 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1936 1937 ice_acquire_res_exit: 1938 if (status == -EALREADY) { 1939 if (access == ICE_RES_WRITE) 1940 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1941 else 1942 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1943 } 1944 return status; 1945 } 1946 1947 /** 1948 * ice_release_res 1949 * @hw: pointer to the HW structure 1950 * @res: resource ID 1951 * 1952 * This function will release a resource using the proper Admin Command. 1953 */ 1954 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1955 { 1956 u32 total_delay = 0; 1957 int status; 1958 1959 status = ice_aq_release_res(hw, res, 0, NULL); 1960 1961 /* there are some rare cases when trying to release the resource 1962 * results in an admin queue timeout, so handle them correctly 1963 */ 1964 while ((status == -EIO) && (total_delay < hw->adminq.sq_cmd_timeout)) { 1965 mdelay(1); 1966 status = ice_aq_release_res(hw, res, 0, NULL); 1967 total_delay++; 1968 } 1969 } 1970 1971 /** 1972 * ice_aq_alloc_free_res - command to allocate/free resources 1973 * @hw: pointer to the HW struct 1974 * @num_entries: number of resource entries in buffer 1975 * @buf: Indirect buffer to hold data parameters and response 1976 * @buf_size: size of buffer for indirect commands 1977 * @opc: pass in the command opcode 1978 * @cd: pointer to command details structure or NULL 1979 * 1980 * Helper function to allocate/free resources using the admin queue commands 1981 */ 1982 int 1983 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1984 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1985 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1986 { 1987 struct ice_aqc_alloc_free_res_cmd *cmd; 1988 struct ice_aq_desc desc; 1989 1990 cmd = &desc.params.sw_res_ctrl; 1991 1992 if (!buf) 1993 return -EINVAL; 1994 1995 if (buf_size < flex_array_size(buf, elem, num_entries)) 1996 return -EINVAL; 1997 1998 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1999 2000 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2001 2002 cmd->num_entries = cpu_to_le16(num_entries); 2003 2004 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2005 } 2006 2007 /** 2008 * ice_alloc_hw_res - allocate resource 2009 * @hw: pointer to the HW struct 2010 * @type: type of resource 2011 * @num: number of resources to allocate 2012 * @btm: allocate from bottom 2013 * @res: pointer to array that will receive the resources 2014 */ 2015 int 2016 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2017 { 2018 struct ice_aqc_alloc_free_res_elem *buf; 2019 u16 buf_len; 2020 int status; 2021 2022 buf_len = struct_size(buf, elem, num); 2023 buf = kzalloc(buf_len, GFP_KERNEL); 2024 if (!buf) 2025 return -ENOMEM; 2026 2027 /* Prepare buffer to allocate resource. */ 2028 buf->num_elems = cpu_to_le16(num); 2029 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2030 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2031 if (btm) 2032 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2033 2034 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2035 ice_aqc_opc_alloc_res, NULL); 2036 if (status) 2037 goto ice_alloc_res_exit; 2038 2039 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2040 2041 ice_alloc_res_exit: 2042 kfree(buf); 2043 return status; 2044 } 2045 2046 /** 2047 * ice_free_hw_res - free allocated HW resource 2048 * @hw: pointer to the HW struct 2049 * @type: type of resource to free 2050 * @num: number of resources 2051 * @res: pointer to array that contains the resources to free 2052 */ 2053 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2054 { 2055 struct ice_aqc_alloc_free_res_elem *buf; 2056 u16 buf_len; 2057 int status; 2058 2059 buf_len = struct_size(buf, elem, num); 2060 buf = kzalloc(buf_len, GFP_KERNEL); 2061 if (!buf) 2062 return -ENOMEM; 2063 2064 /* Prepare buffer to free resource. */ 2065 buf->num_elems = cpu_to_le16(num); 2066 buf->res_type = cpu_to_le16(type); 2067 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2068 2069 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2070 ice_aqc_opc_free_res, NULL); 2071 if (status) 2072 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2073 2074 kfree(buf); 2075 return status; 2076 } 2077 2078 /** 2079 * ice_get_num_per_func - determine number of resources per PF 2080 * @hw: pointer to the HW structure 2081 * @max: value to be evenly split between each PF 2082 * 2083 * Determine the number of valid functions by going through the bitmap returned 2084 * from parsing capabilities and use this to calculate the number of resources 2085 * per PF based on the max value passed in. 2086 */ 2087 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2088 { 2089 u8 funcs; 2090 2091 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2092 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2093 ICE_CAPS_VALID_FUNCS_M); 2094 2095 if (!funcs) 2096 return 0; 2097 2098 return max / funcs; 2099 } 2100 2101 /** 2102 * ice_parse_common_caps - parse common device/function capabilities 2103 * @hw: pointer to the HW struct 2104 * @caps: pointer to common capabilities structure 2105 * @elem: the capability element to parse 2106 * @prefix: message prefix for tracing capabilities 2107 * 2108 * Given a capability element, extract relevant details into the common 2109 * capability structure. 2110 * 2111 * Returns: true if the capability matches one of the common capability ids, 2112 * false otherwise. 2113 */ 2114 static bool 2115 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2116 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2117 { 2118 u32 logical_id = le32_to_cpu(elem->logical_id); 2119 u32 phys_id = le32_to_cpu(elem->phys_id); 2120 u32 number = le32_to_cpu(elem->number); 2121 u16 cap = le16_to_cpu(elem->cap); 2122 bool found = true; 2123 2124 switch (cap) { 2125 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2126 caps->valid_functions = number; 2127 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2128 caps->valid_functions); 2129 break; 2130 case ICE_AQC_CAPS_SRIOV: 2131 caps->sr_iov_1_1 = (number == 1); 2132 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2133 caps->sr_iov_1_1); 2134 break; 2135 case ICE_AQC_CAPS_DCB: 2136 caps->dcb = (number == 1); 2137 caps->active_tc_bitmap = logical_id; 2138 caps->maxtc = phys_id; 2139 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2140 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2141 caps->active_tc_bitmap); 2142 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2143 break; 2144 case ICE_AQC_CAPS_RSS: 2145 caps->rss_table_size = number; 2146 caps->rss_table_entry_width = logical_id; 2147 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2148 caps->rss_table_size); 2149 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2150 caps->rss_table_entry_width); 2151 break; 2152 case ICE_AQC_CAPS_RXQS: 2153 caps->num_rxq = number; 2154 caps->rxq_first_id = phys_id; 2155 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2156 caps->num_rxq); 2157 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2158 caps->rxq_first_id); 2159 break; 2160 case ICE_AQC_CAPS_TXQS: 2161 caps->num_txq = number; 2162 caps->txq_first_id = phys_id; 2163 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2164 caps->num_txq); 2165 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2166 caps->txq_first_id); 2167 break; 2168 case ICE_AQC_CAPS_MSIX: 2169 caps->num_msix_vectors = number; 2170 caps->msix_vector_first_id = phys_id; 2171 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2172 caps->num_msix_vectors); 2173 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2174 caps->msix_vector_first_id); 2175 break; 2176 case ICE_AQC_CAPS_PENDING_NVM_VER: 2177 caps->nvm_update_pending_nvm = true; 2178 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2179 break; 2180 case ICE_AQC_CAPS_PENDING_OROM_VER: 2181 caps->nvm_update_pending_orom = true; 2182 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2183 break; 2184 case ICE_AQC_CAPS_PENDING_NET_VER: 2185 caps->nvm_update_pending_netlist = true; 2186 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2187 break; 2188 case ICE_AQC_CAPS_NVM_MGMT: 2189 caps->nvm_unified_update = 2190 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2191 true : false; 2192 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2193 caps->nvm_unified_update); 2194 break; 2195 case ICE_AQC_CAPS_RDMA: 2196 caps->rdma = (number == 1); 2197 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2198 break; 2199 case ICE_AQC_CAPS_MAX_MTU: 2200 caps->max_mtu = number; 2201 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2202 prefix, caps->max_mtu); 2203 break; 2204 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2205 caps->pcie_reset_avoidance = (number > 0); 2206 ice_debug(hw, ICE_DBG_INIT, 2207 "%s: pcie_reset_avoidance = %d\n", prefix, 2208 caps->pcie_reset_avoidance); 2209 break; 2210 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2211 caps->reset_restrict_support = (number == 1); 2212 ice_debug(hw, ICE_DBG_INIT, 2213 "%s: reset_restrict_support = %d\n", prefix, 2214 caps->reset_restrict_support); 2215 break; 2216 default: 2217 /* Not one of the recognized common capabilities */ 2218 found = false; 2219 } 2220 2221 return found; 2222 } 2223 2224 /** 2225 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2226 * @hw: pointer to the HW structure 2227 * @caps: pointer to capabilities structure to fix 2228 * 2229 * Re-calculate the capabilities that are dependent on the number of physical 2230 * ports; i.e. some features are not supported or function differently on 2231 * devices with more than 4 ports. 2232 */ 2233 static void 2234 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2235 { 2236 /* This assumes device capabilities are always scanned before function 2237 * capabilities during the initialization flow. 2238 */ 2239 if (hw->dev_caps.num_funcs > 4) { 2240 /* Max 4 TCs per port */ 2241 caps->maxtc = 4; 2242 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2243 caps->maxtc); 2244 if (caps->rdma) { 2245 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2246 caps->rdma = 0; 2247 } 2248 2249 /* print message only when processing device capabilities 2250 * during initialization. 2251 */ 2252 if (caps == &hw->dev_caps.common_cap) 2253 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2254 } 2255 } 2256 2257 /** 2258 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2259 * @hw: pointer to the HW struct 2260 * @func_p: pointer to function capabilities structure 2261 * @cap: pointer to the capability element to parse 2262 * 2263 * Extract function capabilities for ICE_AQC_CAPS_VF. 2264 */ 2265 static void 2266 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2267 struct ice_aqc_list_caps_elem *cap) 2268 { 2269 u32 logical_id = le32_to_cpu(cap->logical_id); 2270 u32 number = le32_to_cpu(cap->number); 2271 2272 func_p->num_allocd_vfs = number; 2273 func_p->vf_base_id = logical_id; 2274 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2275 func_p->num_allocd_vfs); 2276 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2277 func_p->vf_base_id); 2278 } 2279 2280 /** 2281 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2282 * @hw: pointer to the HW struct 2283 * @func_p: pointer to function capabilities structure 2284 * @cap: pointer to the capability element to parse 2285 * 2286 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2287 */ 2288 static void 2289 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2290 struct ice_aqc_list_caps_elem *cap) 2291 { 2292 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2293 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2294 le32_to_cpu(cap->number)); 2295 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2296 func_p->guar_num_vsi); 2297 } 2298 2299 /** 2300 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2301 * @hw: pointer to the HW struct 2302 * @func_p: pointer to function capabilities structure 2303 * @cap: pointer to the capability element to parse 2304 * 2305 * Extract function capabilities for ICE_AQC_CAPS_1588. 2306 */ 2307 static void 2308 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2309 struct ice_aqc_list_caps_elem *cap) 2310 { 2311 struct ice_ts_func_info *info = &func_p->ts_func_info; 2312 u32 number = le32_to_cpu(cap->number); 2313 2314 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2315 func_p->common_cap.ieee_1588 = info->ena; 2316 2317 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2318 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2319 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2320 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2321 2322 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2323 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2324 2325 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2326 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2327 } else { 2328 /* Unknown clock frequency, so assume a (probably incorrect) 2329 * default to avoid out-of-bounds look ups of frequency 2330 * related information. 2331 */ 2332 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2333 info->clk_freq); 2334 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2335 } 2336 2337 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2338 func_p->common_cap.ieee_1588); 2339 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2340 info->src_tmr_owned); 2341 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2342 info->tmr_ena); 2343 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2344 info->tmr_index_owned); 2345 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2346 info->tmr_index_assoc); 2347 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2348 info->clk_freq); 2349 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2350 info->clk_src); 2351 } 2352 2353 /** 2354 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2355 * @hw: pointer to the HW struct 2356 * @func_p: pointer to function capabilities structure 2357 * 2358 * Extract function capabilities for ICE_AQC_CAPS_FD. 2359 */ 2360 static void 2361 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2362 { 2363 u32 reg_val, val; 2364 2365 reg_val = rd32(hw, GLQF_FD_SIZE); 2366 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2367 GLQF_FD_SIZE_FD_GSIZE_S; 2368 func_p->fd_fltr_guar = 2369 ice_get_num_per_func(hw, val); 2370 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2371 GLQF_FD_SIZE_FD_BSIZE_S; 2372 func_p->fd_fltr_best_effort = val; 2373 2374 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2375 func_p->fd_fltr_guar); 2376 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2377 func_p->fd_fltr_best_effort); 2378 } 2379 2380 /** 2381 * ice_parse_func_caps - Parse function capabilities 2382 * @hw: pointer to the HW struct 2383 * @func_p: pointer to function capabilities structure 2384 * @buf: buffer containing the function capability records 2385 * @cap_count: the number of capabilities 2386 * 2387 * Helper function to parse function (0x000A) capabilities list. For 2388 * capabilities shared between device and function, this relies on 2389 * ice_parse_common_caps. 2390 * 2391 * Loop through the list of provided capabilities and extract the relevant 2392 * data into the function capabilities structured. 2393 */ 2394 static void 2395 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2396 void *buf, u32 cap_count) 2397 { 2398 struct ice_aqc_list_caps_elem *cap_resp; 2399 u32 i; 2400 2401 cap_resp = buf; 2402 2403 memset(func_p, 0, sizeof(*func_p)); 2404 2405 for (i = 0; i < cap_count; i++) { 2406 u16 cap = le16_to_cpu(cap_resp[i].cap); 2407 bool found; 2408 2409 found = ice_parse_common_caps(hw, &func_p->common_cap, 2410 &cap_resp[i], "func caps"); 2411 2412 switch (cap) { 2413 case ICE_AQC_CAPS_VF: 2414 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2415 break; 2416 case ICE_AQC_CAPS_VSI: 2417 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2418 break; 2419 case ICE_AQC_CAPS_1588: 2420 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2421 break; 2422 case ICE_AQC_CAPS_FD: 2423 ice_parse_fdir_func_caps(hw, func_p); 2424 break; 2425 default: 2426 /* Don't list common capabilities as unknown */ 2427 if (!found) 2428 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2429 i, cap); 2430 break; 2431 } 2432 } 2433 2434 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2435 } 2436 2437 /** 2438 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2439 * @hw: pointer to the HW struct 2440 * @dev_p: pointer to device capabilities structure 2441 * @cap: capability element to parse 2442 * 2443 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2444 */ 2445 static void 2446 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2447 struct ice_aqc_list_caps_elem *cap) 2448 { 2449 u32 number = le32_to_cpu(cap->number); 2450 2451 dev_p->num_funcs = hweight32(number); 2452 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2453 dev_p->num_funcs); 2454 } 2455 2456 /** 2457 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2458 * @hw: pointer to the HW struct 2459 * @dev_p: pointer to device capabilities structure 2460 * @cap: capability element to parse 2461 * 2462 * Parse ICE_AQC_CAPS_VF for device capabilities. 2463 */ 2464 static void 2465 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2466 struct ice_aqc_list_caps_elem *cap) 2467 { 2468 u32 number = le32_to_cpu(cap->number); 2469 2470 dev_p->num_vfs_exposed = number; 2471 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2472 dev_p->num_vfs_exposed); 2473 } 2474 2475 /** 2476 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2477 * @hw: pointer to the HW struct 2478 * @dev_p: pointer to device capabilities structure 2479 * @cap: capability element to parse 2480 * 2481 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2482 */ 2483 static void 2484 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2485 struct ice_aqc_list_caps_elem *cap) 2486 { 2487 u32 number = le32_to_cpu(cap->number); 2488 2489 dev_p->num_vsi_allocd_to_host = number; 2490 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2491 dev_p->num_vsi_allocd_to_host); 2492 } 2493 2494 /** 2495 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2496 * @hw: pointer to the HW struct 2497 * @dev_p: pointer to device capabilities structure 2498 * @cap: capability element to parse 2499 * 2500 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2501 */ 2502 static void 2503 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2504 struct ice_aqc_list_caps_elem *cap) 2505 { 2506 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2507 u32 logical_id = le32_to_cpu(cap->logical_id); 2508 u32 phys_id = le32_to_cpu(cap->phys_id); 2509 u32 number = le32_to_cpu(cap->number); 2510 2511 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2512 dev_p->common_cap.ieee_1588 = info->ena; 2513 2514 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2515 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2516 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2517 2518 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2519 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2520 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2521 2522 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2523 2524 info->ena_ports = logical_id; 2525 info->tmr_own_map = phys_id; 2526 2527 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2528 dev_p->common_cap.ieee_1588); 2529 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2530 info->tmr0_owner); 2531 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2532 info->tmr0_owned); 2533 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2534 info->tmr0_ena); 2535 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2536 info->tmr1_owner); 2537 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2538 info->tmr1_owned); 2539 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2540 info->tmr1_ena); 2541 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2542 info->ts_ll_read); 2543 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2544 info->ena_ports); 2545 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2546 info->tmr_own_map); 2547 } 2548 2549 /** 2550 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2551 * @hw: pointer to the HW struct 2552 * @dev_p: pointer to device capabilities structure 2553 * @cap: capability element to parse 2554 * 2555 * Parse ICE_AQC_CAPS_FD for device capabilities. 2556 */ 2557 static void 2558 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2559 struct ice_aqc_list_caps_elem *cap) 2560 { 2561 u32 number = le32_to_cpu(cap->number); 2562 2563 dev_p->num_flow_director_fltr = number; 2564 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2565 dev_p->num_flow_director_fltr); 2566 } 2567 2568 /** 2569 * ice_parse_dev_caps - Parse device capabilities 2570 * @hw: pointer to the HW struct 2571 * @dev_p: pointer to device capabilities structure 2572 * @buf: buffer containing the device capability records 2573 * @cap_count: the number of capabilities 2574 * 2575 * Helper device to parse device (0x000B) capabilities list. For 2576 * capabilities shared between device and function, this relies on 2577 * ice_parse_common_caps. 2578 * 2579 * Loop through the list of provided capabilities and extract the relevant 2580 * data into the device capabilities structured. 2581 */ 2582 static void 2583 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2584 void *buf, u32 cap_count) 2585 { 2586 struct ice_aqc_list_caps_elem *cap_resp; 2587 u32 i; 2588 2589 cap_resp = buf; 2590 2591 memset(dev_p, 0, sizeof(*dev_p)); 2592 2593 for (i = 0; i < cap_count; i++) { 2594 u16 cap = le16_to_cpu(cap_resp[i].cap); 2595 bool found; 2596 2597 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2598 &cap_resp[i], "dev caps"); 2599 2600 switch (cap) { 2601 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2602 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2603 break; 2604 case ICE_AQC_CAPS_VF: 2605 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2606 break; 2607 case ICE_AQC_CAPS_VSI: 2608 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2609 break; 2610 case ICE_AQC_CAPS_1588: 2611 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2612 break; 2613 case ICE_AQC_CAPS_FD: 2614 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2615 break; 2616 default: 2617 /* Don't list common capabilities as unknown */ 2618 if (!found) 2619 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2620 i, cap); 2621 break; 2622 } 2623 } 2624 2625 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2626 } 2627 2628 /** 2629 * ice_aq_list_caps - query function/device capabilities 2630 * @hw: pointer to the HW struct 2631 * @buf: a buffer to hold the capabilities 2632 * @buf_size: size of the buffer 2633 * @cap_count: if not NULL, set to the number of capabilities reported 2634 * @opc: capabilities type to discover, device or function 2635 * @cd: pointer to command details structure or NULL 2636 * 2637 * Get the function (0x000A) or device (0x000B) capabilities description from 2638 * firmware and store it in the buffer. 2639 * 2640 * If the cap_count pointer is not NULL, then it is set to the number of 2641 * capabilities firmware will report. Note that if the buffer size is too 2642 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2643 * cap_count will still be updated in this case. It is recommended that the 2644 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2645 * firmware could return) to avoid this. 2646 */ 2647 int 2648 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2649 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2650 { 2651 struct ice_aqc_list_caps *cmd; 2652 struct ice_aq_desc desc; 2653 int status; 2654 2655 cmd = &desc.params.get_cap; 2656 2657 if (opc != ice_aqc_opc_list_func_caps && 2658 opc != ice_aqc_opc_list_dev_caps) 2659 return -EINVAL; 2660 2661 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2662 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2663 2664 if (cap_count) 2665 *cap_count = le32_to_cpu(cmd->count); 2666 2667 return status; 2668 } 2669 2670 /** 2671 * ice_discover_dev_caps - Read and extract device capabilities 2672 * @hw: pointer to the hardware structure 2673 * @dev_caps: pointer to device capabilities structure 2674 * 2675 * Read the device capabilities and extract them into the dev_caps structure 2676 * for later use. 2677 */ 2678 int 2679 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2680 { 2681 u32 cap_count = 0; 2682 void *cbuf; 2683 int status; 2684 2685 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2686 if (!cbuf) 2687 return -ENOMEM; 2688 2689 /* Although the driver doesn't know the number of capabilities the 2690 * device will return, we can simply send a 4KB buffer, the maximum 2691 * possible size that firmware can return. 2692 */ 2693 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2694 2695 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2696 ice_aqc_opc_list_dev_caps, NULL); 2697 if (!status) 2698 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2699 kfree(cbuf); 2700 2701 return status; 2702 } 2703 2704 /** 2705 * ice_discover_func_caps - Read and extract function capabilities 2706 * @hw: pointer to the hardware structure 2707 * @func_caps: pointer to function capabilities structure 2708 * 2709 * Read the function capabilities and extract them into the func_caps structure 2710 * for later use. 2711 */ 2712 static int 2713 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2714 { 2715 u32 cap_count = 0; 2716 void *cbuf; 2717 int status; 2718 2719 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2720 if (!cbuf) 2721 return -ENOMEM; 2722 2723 /* Although the driver doesn't know the number of capabilities the 2724 * device will return, we can simply send a 4KB buffer, the maximum 2725 * possible size that firmware can return. 2726 */ 2727 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2728 2729 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2730 ice_aqc_opc_list_func_caps, NULL); 2731 if (!status) 2732 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2733 kfree(cbuf); 2734 2735 return status; 2736 } 2737 2738 /** 2739 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2740 * @hw: pointer to the hardware structure 2741 */ 2742 void ice_set_safe_mode_caps(struct ice_hw *hw) 2743 { 2744 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2745 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2746 struct ice_hw_common_caps cached_caps; 2747 u32 num_funcs; 2748 2749 /* cache some func_caps values that should be restored after memset */ 2750 cached_caps = func_caps->common_cap; 2751 2752 /* unset func capabilities */ 2753 memset(func_caps, 0, sizeof(*func_caps)); 2754 2755 #define ICE_RESTORE_FUNC_CAP(name) \ 2756 func_caps->common_cap.name = cached_caps.name 2757 2758 /* restore cached values */ 2759 ICE_RESTORE_FUNC_CAP(valid_functions); 2760 ICE_RESTORE_FUNC_CAP(txq_first_id); 2761 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2762 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2763 ICE_RESTORE_FUNC_CAP(max_mtu); 2764 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2765 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2766 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2767 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2768 2769 /* one Tx and one Rx queue in safe mode */ 2770 func_caps->common_cap.num_rxq = 1; 2771 func_caps->common_cap.num_txq = 1; 2772 2773 /* two MSIX vectors, one for traffic and one for misc causes */ 2774 func_caps->common_cap.num_msix_vectors = 2; 2775 func_caps->guar_num_vsi = 1; 2776 2777 /* cache some dev_caps values that should be restored after memset */ 2778 cached_caps = dev_caps->common_cap; 2779 num_funcs = dev_caps->num_funcs; 2780 2781 /* unset dev capabilities */ 2782 memset(dev_caps, 0, sizeof(*dev_caps)); 2783 2784 #define ICE_RESTORE_DEV_CAP(name) \ 2785 dev_caps->common_cap.name = cached_caps.name 2786 2787 /* restore cached values */ 2788 ICE_RESTORE_DEV_CAP(valid_functions); 2789 ICE_RESTORE_DEV_CAP(txq_first_id); 2790 ICE_RESTORE_DEV_CAP(rxq_first_id); 2791 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2792 ICE_RESTORE_DEV_CAP(max_mtu); 2793 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2794 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2795 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2796 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2797 dev_caps->num_funcs = num_funcs; 2798 2799 /* one Tx and one Rx queue per function in safe mode */ 2800 dev_caps->common_cap.num_rxq = num_funcs; 2801 dev_caps->common_cap.num_txq = num_funcs; 2802 2803 /* two MSIX vectors per function */ 2804 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2805 } 2806 2807 /** 2808 * ice_get_caps - get info about the HW 2809 * @hw: pointer to the hardware structure 2810 */ 2811 int ice_get_caps(struct ice_hw *hw) 2812 { 2813 int status; 2814 2815 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2816 if (status) 2817 return status; 2818 2819 return ice_discover_func_caps(hw, &hw->func_caps); 2820 } 2821 2822 /** 2823 * ice_aq_manage_mac_write - manage MAC address write command 2824 * @hw: pointer to the HW struct 2825 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2826 * @flags: flags to control write behavior 2827 * @cd: pointer to command details structure or NULL 2828 * 2829 * This function is used to write MAC address to the NVM (0x0108). 2830 */ 2831 int 2832 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2833 struct ice_sq_cd *cd) 2834 { 2835 struct ice_aqc_manage_mac_write *cmd; 2836 struct ice_aq_desc desc; 2837 2838 cmd = &desc.params.mac_write; 2839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2840 2841 cmd->flags = flags; 2842 ether_addr_copy(cmd->mac_addr, mac_addr); 2843 2844 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2845 } 2846 2847 /** 2848 * ice_aq_clear_pxe_mode 2849 * @hw: pointer to the HW struct 2850 * 2851 * Tell the firmware that the driver is taking over from PXE (0x0110). 2852 */ 2853 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2854 { 2855 struct ice_aq_desc desc; 2856 2857 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2858 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2859 2860 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2861 } 2862 2863 /** 2864 * ice_clear_pxe_mode - clear pxe operations mode 2865 * @hw: pointer to the HW struct 2866 * 2867 * Make sure all PXE mode settings are cleared, including things 2868 * like descriptor fetch/write-back mode. 2869 */ 2870 void ice_clear_pxe_mode(struct ice_hw *hw) 2871 { 2872 if (ice_check_sq_alive(hw, &hw->adminq)) 2873 ice_aq_clear_pxe_mode(hw); 2874 } 2875 2876 /** 2877 * ice_aq_set_port_params - set physical port parameters. 2878 * @pi: pointer to the port info struct 2879 * @double_vlan: if set double VLAN is enabled 2880 * @cd: pointer to command details structure or NULL 2881 * 2882 * Set Physical port parameters (0x0203) 2883 */ 2884 int 2885 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2886 struct ice_sq_cd *cd) 2887 2888 { 2889 struct ice_aqc_set_port_params *cmd; 2890 struct ice_hw *hw = pi->hw; 2891 struct ice_aq_desc desc; 2892 u16 cmd_flags = 0; 2893 2894 cmd = &desc.params.set_port_params; 2895 2896 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2897 if (double_vlan) 2898 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2899 cmd->cmd_flags = cpu_to_le16(cmd_flags); 2900 2901 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2902 } 2903 2904 /** 2905 * ice_is_100m_speed_supported 2906 * @hw: pointer to the HW struct 2907 * 2908 * returns true if 100M speeds are supported by the device, 2909 * false otherwise. 2910 */ 2911 bool ice_is_100m_speed_supported(struct ice_hw *hw) 2912 { 2913 switch (hw->device_id) { 2914 case ICE_DEV_ID_E822C_SGMII: 2915 case ICE_DEV_ID_E822L_SGMII: 2916 case ICE_DEV_ID_E823L_1GBE: 2917 case ICE_DEV_ID_E823C_SGMII: 2918 return true; 2919 default: 2920 return false; 2921 } 2922 } 2923 2924 /** 2925 * ice_get_link_speed_based_on_phy_type - returns link speed 2926 * @phy_type_low: lower part of phy_type 2927 * @phy_type_high: higher part of phy_type 2928 * 2929 * This helper function will convert an entry in PHY type structure 2930 * [phy_type_low, phy_type_high] to its corresponding link speed. 2931 * Note: In the structure of [phy_type_low, phy_type_high], there should 2932 * be one bit set, as this function will convert one PHY type to its 2933 * speed. 2934 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2935 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2936 */ 2937 static u16 2938 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2939 { 2940 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2941 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2942 2943 switch (phy_type_low) { 2944 case ICE_PHY_TYPE_LOW_100BASE_TX: 2945 case ICE_PHY_TYPE_LOW_100M_SGMII: 2946 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2947 break; 2948 case ICE_PHY_TYPE_LOW_1000BASE_T: 2949 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2950 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2951 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2952 case ICE_PHY_TYPE_LOW_1G_SGMII: 2953 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2954 break; 2955 case ICE_PHY_TYPE_LOW_2500BASE_T: 2956 case ICE_PHY_TYPE_LOW_2500BASE_X: 2957 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2958 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2959 break; 2960 case ICE_PHY_TYPE_LOW_5GBASE_T: 2961 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2962 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2963 break; 2964 case ICE_PHY_TYPE_LOW_10GBASE_T: 2965 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2966 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2967 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2968 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2969 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2970 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2971 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2972 break; 2973 case ICE_PHY_TYPE_LOW_25GBASE_T: 2974 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2975 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2976 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2977 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2978 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2979 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2980 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2981 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2982 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2983 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2984 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2985 break; 2986 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2987 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2988 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2989 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2990 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2991 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2992 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2993 break; 2994 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2995 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2996 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2997 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2998 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2999 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3000 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3001 case ICE_PHY_TYPE_LOW_50G_AUI2: 3002 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3003 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3004 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3005 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3006 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3007 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3008 case ICE_PHY_TYPE_LOW_50G_AUI1: 3009 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3010 break; 3011 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3012 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3013 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3014 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3015 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3016 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3017 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3018 case ICE_PHY_TYPE_LOW_100G_AUI4: 3019 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3020 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3021 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3022 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3023 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3024 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3025 break; 3026 default: 3027 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3028 break; 3029 } 3030 3031 switch (phy_type_high) { 3032 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3033 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3034 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3035 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3036 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3037 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3038 break; 3039 default: 3040 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3041 break; 3042 } 3043 3044 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3045 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3046 return ICE_AQ_LINK_SPEED_UNKNOWN; 3047 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3048 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3049 return ICE_AQ_LINK_SPEED_UNKNOWN; 3050 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3051 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3052 return speed_phy_type_low; 3053 else 3054 return speed_phy_type_high; 3055 } 3056 3057 /** 3058 * ice_update_phy_type 3059 * @phy_type_low: pointer to the lower part of phy_type 3060 * @phy_type_high: pointer to the higher part of phy_type 3061 * @link_speeds_bitmap: targeted link speeds bitmap 3062 * 3063 * Note: For the link_speeds_bitmap structure, you can check it at 3064 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3065 * link_speeds_bitmap include multiple speeds. 3066 * 3067 * Each entry in this [phy_type_low, phy_type_high] structure will 3068 * present a certain link speed. This helper function will turn on bits 3069 * in [phy_type_low, phy_type_high] structure based on the value of 3070 * link_speeds_bitmap input parameter. 3071 */ 3072 void 3073 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3074 u16 link_speeds_bitmap) 3075 { 3076 u64 pt_high; 3077 u64 pt_low; 3078 int index; 3079 u16 speed; 3080 3081 /* We first check with low part of phy_type */ 3082 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3083 pt_low = BIT_ULL(index); 3084 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3085 3086 if (link_speeds_bitmap & speed) 3087 *phy_type_low |= BIT_ULL(index); 3088 } 3089 3090 /* We then check with high part of phy_type */ 3091 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3092 pt_high = BIT_ULL(index); 3093 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3094 3095 if (link_speeds_bitmap & speed) 3096 *phy_type_high |= BIT_ULL(index); 3097 } 3098 } 3099 3100 /** 3101 * ice_aq_set_phy_cfg 3102 * @hw: pointer to the HW struct 3103 * @pi: port info structure of the interested logical port 3104 * @cfg: structure with PHY configuration data to be set 3105 * @cd: pointer to command details structure or NULL 3106 * 3107 * Set the various PHY configuration parameters supported on the Port. 3108 * One or more of the Set PHY config parameters may be ignored in an MFP 3109 * mode as the PF may not have the privilege to set some of the PHY Config 3110 * parameters. This status will be indicated by the command response (0x0601). 3111 */ 3112 int 3113 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3114 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3115 { 3116 struct ice_aq_desc desc; 3117 int status; 3118 3119 if (!cfg) 3120 return -EINVAL; 3121 3122 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3123 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3124 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3125 cfg->caps); 3126 3127 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3128 } 3129 3130 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3131 desc.params.set_phy.lport_num = pi->lport; 3132 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3133 3134 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3135 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3136 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3137 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3138 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3139 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3140 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3141 cfg->low_power_ctrl_an); 3142 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3143 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3144 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3145 cfg->link_fec_opt); 3146 3147 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3148 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3149 status = 0; 3150 3151 if (!status) 3152 pi->phy.curr_user_phy_cfg = *cfg; 3153 3154 return status; 3155 } 3156 3157 /** 3158 * ice_update_link_info - update status of the HW network link 3159 * @pi: port info structure of the interested logical port 3160 */ 3161 int ice_update_link_info(struct ice_port_info *pi) 3162 { 3163 struct ice_link_status *li; 3164 int status; 3165 3166 if (!pi) 3167 return -EINVAL; 3168 3169 li = &pi->phy.link_info; 3170 3171 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3172 if (status) 3173 return status; 3174 3175 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3176 struct ice_aqc_get_phy_caps_data *pcaps; 3177 struct ice_hw *hw; 3178 3179 hw = pi->hw; 3180 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3181 GFP_KERNEL); 3182 if (!pcaps) 3183 return -ENOMEM; 3184 3185 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3186 pcaps, NULL); 3187 3188 devm_kfree(ice_hw_to_dev(hw), pcaps); 3189 } 3190 3191 return status; 3192 } 3193 3194 /** 3195 * ice_cache_phy_user_req 3196 * @pi: port information structure 3197 * @cache_data: PHY logging data 3198 * @cache_mode: PHY logging mode 3199 * 3200 * Log the user request on (FC, FEC, SPEED) for later use. 3201 */ 3202 static void 3203 ice_cache_phy_user_req(struct ice_port_info *pi, 3204 struct ice_phy_cache_mode_data cache_data, 3205 enum ice_phy_cache_mode cache_mode) 3206 { 3207 if (!pi) 3208 return; 3209 3210 switch (cache_mode) { 3211 case ICE_FC_MODE: 3212 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3213 break; 3214 case ICE_SPEED_MODE: 3215 pi->phy.curr_user_speed_req = 3216 cache_data.data.curr_user_speed_req; 3217 break; 3218 case ICE_FEC_MODE: 3219 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3220 break; 3221 default: 3222 break; 3223 } 3224 } 3225 3226 /** 3227 * ice_caps_to_fc_mode 3228 * @caps: PHY capabilities 3229 * 3230 * Convert PHY FC capabilities to ice FC mode 3231 */ 3232 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3233 { 3234 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3235 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3236 return ICE_FC_FULL; 3237 3238 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3239 return ICE_FC_TX_PAUSE; 3240 3241 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3242 return ICE_FC_RX_PAUSE; 3243 3244 return ICE_FC_NONE; 3245 } 3246 3247 /** 3248 * ice_caps_to_fec_mode 3249 * @caps: PHY capabilities 3250 * @fec_options: Link FEC options 3251 * 3252 * Convert PHY FEC capabilities to ice FEC mode 3253 */ 3254 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3255 { 3256 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3257 return ICE_FEC_AUTO; 3258 3259 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3260 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3261 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3262 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3263 return ICE_FEC_BASER; 3264 3265 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3266 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3267 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3268 return ICE_FEC_RS; 3269 3270 return ICE_FEC_NONE; 3271 } 3272 3273 /** 3274 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3275 * @pi: port information structure 3276 * @cfg: PHY configuration data to set FC mode 3277 * @req_mode: FC mode to configure 3278 */ 3279 int 3280 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3281 enum ice_fc_mode req_mode) 3282 { 3283 struct ice_phy_cache_mode_data cache_data; 3284 u8 pause_mask = 0x0; 3285 3286 if (!pi || !cfg) 3287 return -EINVAL; 3288 3289 switch (req_mode) { 3290 case ICE_FC_FULL: 3291 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3292 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3293 break; 3294 case ICE_FC_RX_PAUSE: 3295 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3296 break; 3297 case ICE_FC_TX_PAUSE: 3298 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3299 break; 3300 default: 3301 break; 3302 } 3303 3304 /* clear the old pause settings */ 3305 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3306 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3307 3308 /* set the new capabilities */ 3309 cfg->caps |= pause_mask; 3310 3311 /* Cache user FC request */ 3312 cache_data.data.curr_user_fc_req = req_mode; 3313 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3314 3315 return 0; 3316 } 3317 3318 /** 3319 * ice_set_fc 3320 * @pi: port information structure 3321 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3322 * @ena_auto_link_update: enable automatic link update 3323 * 3324 * Set the requested flow control mode. 3325 */ 3326 int 3327 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3328 { 3329 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3330 struct ice_aqc_get_phy_caps_data *pcaps; 3331 struct ice_hw *hw; 3332 int status; 3333 3334 if (!pi || !aq_failures) 3335 return -EINVAL; 3336 3337 *aq_failures = 0; 3338 hw = pi->hw; 3339 3340 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3341 if (!pcaps) 3342 return -ENOMEM; 3343 3344 /* Get the current PHY config */ 3345 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3346 pcaps, NULL); 3347 if (status) { 3348 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3349 goto out; 3350 } 3351 3352 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3353 3354 /* Configure the set PHY data */ 3355 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3356 if (status) 3357 goto out; 3358 3359 /* If the capabilities have changed, then set the new config */ 3360 if (cfg.caps != pcaps->caps) { 3361 int retry_count, retry_max = 10; 3362 3363 /* Auto restart link so settings take effect */ 3364 if (ena_auto_link_update) 3365 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3366 3367 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3368 if (status) { 3369 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3370 goto out; 3371 } 3372 3373 /* Update the link info 3374 * It sometimes takes a really long time for link to 3375 * come back from the atomic reset. Thus, we wait a 3376 * little bit. 3377 */ 3378 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3379 status = ice_update_link_info(pi); 3380 3381 if (!status) 3382 break; 3383 3384 mdelay(100); 3385 } 3386 3387 if (status) 3388 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3389 } 3390 3391 out: 3392 devm_kfree(ice_hw_to_dev(hw), pcaps); 3393 return status; 3394 } 3395 3396 /** 3397 * ice_phy_caps_equals_cfg 3398 * @phy_caps: PHY capabilities 3399 * @phy_cfg: PHY configuration 3400 * 3401 * Helper function to determine if PHY capabilities matches PHY 3402 * configuration 3403 */ 3404 bool 3405 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3406 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3407 { 3408 u8 caps_mask, cfg_mask; 3409 3410 if (!phy_caps || !phy_cfg) 3411 return false; 3412 3413 /* These bits are not common between capabilities and configuration. 3414 * Do not use them to determine equality. 3415 */ 3416 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3417 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3418 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3419 3420 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3421 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3422 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3423 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3424 phy_caps->eee_cap != phy_cfg->eee_cap || 3425 phy_caps->eeer_value != phy_cfg->eeer_value || 3426 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3427 return false; 3428 3429 return true; 3430 } 3431 3432 /** 3433 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3434 * @pi: port information structure 3435 * @caps: PHY ability structure to copy date from 3436 * @cfg: PHY configuration structure to copy data to 3437 * 3438 * Helper function to copy AQC PHY get ability data to PHY set configuration 3439 * data structure 3440 */ 3441 void 3442 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3443 struct ice_aqc_get_phy_caps_data *caps, 3444 struct ice_aqc_set_phy_cfg_data *cfg) 3445 { 3446 if (!pi || !caps || !cfg) 3447 return; 3448 3449 memset(cfg, 0, sizeof(*cfg)); 3450 cfg->phy_type_low = caps->phy_type_low; 3451 cfg->phy_type_high = caps->phy_type_high; 3452 cfg->caps = caps->caps; 3453 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3454 cfg->eee_cap = caps->eee_cap; 3455 cfg->eeer_value = caps->eeer_value; 3456 cfg->link_fec_opt = caps->link_fec_options; 3457 cfg->module_compliance_enforcement = 3458 caps->module_compliance_enforcement; 3459 } 3460 3461 /** 3462 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3463 * @pi: port information structure 3464 * @cfg: PHY configuration data to set FEC mode 3465 * @fec: FEC mode to configure 3466 */ 3467 int 3468 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3469 enum ice_fec_mode fec) 3470 { 3471 struct ice_aqc_get_phy_caps_data *pcaps; 3472 struct ice_hw *hw; 3473 int status; 3474 3475 if (!pi || !cfg) 3476 return -EINVAL; 3477 3478 hw = pi->hw; 3479 3480 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3481 if (!pcaps) 3482 return -ENOMEM; 3483 3484 status = ice_aq_get_phy_caps(pi, false, 3485 (ice_fw_supports_report_dflt_cfg(hw) ? 3486 ICE_AQC_REPORT_DFLT_CFG : 3487 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3488 if (status) 3489 goto out; 3490 3491 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3492 cfg->link_fec_opt = pcaps->link_fec_options; 3493 3494 switch (fec) { 3495 case ICE_FEC_BASER: 3496 /* Clear RS bits, and AND BASE-R ability 3497 * bits and OR request bits. 3498 */ 3499 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3500 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3501 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3502 ICE_AQC_PHY_FEC_25G_KR_REQ; 3503 break; 3504 case ICE_FEC_RS: 3505 /* Clear BASE-R bits, and AND RS ability 3506 * bits and OR request bits. 3507 */ 3508 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3509 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3510 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3511 break; 3512 case ICE_FEC_NONE: 3513 /* Clear all FEC option bits. */ 3514 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3515 break; 3516 case ICE_FEC_AUTO: 3517 /* AND auto FEC bit, and all caps bits. */ 3518 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3519 cfg->link_fec_opt |= pcaps->link_fec_options; 3520 break; 3521 default: 3522 status = -EINVAL; 3523 break; 3524 } 3525 3526 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3527 !ice_fw_supports_report_dflt_cfg(hw)) { 3528 struct ice_link_default_override_tlv tlv = { 0 }; 3529 3530 status = ice_get_link_default_override(&tlv, pi); 3531 if (status) 3532 goto out; 3533 3534 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3535 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3536 cfg->link_fec_opt = tlv.fec_options; 3537 } 3538 3539 out: 3540 kfree(pcaps); 3541 3542 return status; 3543 } 3544 3545 /** 3546 * ice_get_link_status - get status of the HW network link 3547 * @pi: port information structure 3548 * @link_up: pointer to bool (true/false = linkup/linkdown) 3549 * 3550 * Variable link_up is true if link is up, false if link is down. 3551 * The variable link_up is invalid if status is non zero. As a 3552 * result of this call, link status reporting becomes enabled 3553 */ 3554 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3555 { 3556 struct ice_phy_info *phy_info; 3557 int status = 0; 3558 3559 if (!pi || !link_up) 3560 return -EINVAL; 3561 3562 phy_info = &pi->phy; 3563 3564 if (phy_info->get_link_info) { 3565 status = ice_update_link_info(pi); 3566 3567 if (status) 3568 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3569 status); 3570 } 3571 3572 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3573 3574 return status; 3575 } 3576 3577 /** 3578 * ice_aq_set_link_restart_an 3579 * @pi: pointer to the port information structure 3580 * @ena_link: if true: enable link, if false: disable link 3581 * @cd: pointer to command details structure or NULL 3582 * 3583 * Sets up the link and restarts the Auto-Negotiation over the link. 3584 */ 3585 int 3586 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3587 struct ice_sq_cd *cd) 3588 { 3589 struct ice_aqc_restart_an *cmd; 3590 struct ice_aq_desc desc; 3591 3592 cmd = &desc.params.restart_an; 3593 3594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3595 3596 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3597 cmd->lport_num = pi->lport; 3598 if (ena_link) 3599 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3600 else 3601 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3602 3603 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3604 } 3605 3606 /** 3607 * ice_aq_set_event_mask 3608 * @hw: pointer to the HW struct 3609 * @port_num: port number of the physical function 3610 * @mask: event mask to be set 3611 * @cd: pointer to command details structure or NULL 3612 * 3613 * Set event mask (0x0613) 3614 */ 3615 int 3616 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3617 struct ice_sq_cd *cd) 3618 { 3619 struct ice_aqc_set_event_mask *cmd; 3620 struct ice_aq_desc desc; 3621 3622 cmd = &desc.params.set_event_mask; 3623 3624 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3625 3626 cmd->lport_num = port_num; 3627 3628 cmd->event_mask = cpu_to_le16(mask); 3629 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3630 } 3631 3632 /** 3633 * ice_aq_set_mac_loopback 3634 * @hw: pointer to the HW struct 3635 * @ena_lpbk: Enable or Disable loopback 3636 * @cd: pointer to command details structure or NULL 3637 * 3638 * Enable/disable loopback on a given port 3639 */ 3640 int 3641 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3642 { 3643 struct ice_aqc_set_mac_lb *cmd; 3644 struct ice_aq_desc desc; 3645 3646 cmd = &desc.params.set_mac_lb; 3647 3648 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3649 if (ena_lpbk) 3650 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3651 3652 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3653 } 3654 3655 /** 3656 * ice_aq_set_port_id_led 3657 * @pi: pointer to the port information 3658 * @is_orig_mode: is this LED set to original mode (by the net-list) 3659 * @cd: pointer to command details structure or NULL 3660 * 3661 * Set LED value for the given port (0x06e9) 3662 */ 3663 int 3664 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3665 struct ice_sq_cd *cd) 3666 { 3667 struct ice_aqc_set_port_id_led *cmd; 3668 struct ice_hw *hw = pi->hw; 3669 struct ice_aq_desc desc; 3670 3671 cmd = &desc.params.set_port_id_led; 3672 3673 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3674 3675 if (is_orig_mode) 3676 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3677 else 3678 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3679 3680 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3681 } 3682 3683 /** 3684 * ice_aq_get_port_options 3685 * @hw: pointer to the HW struct 3686 * @options: buffer for the resultant port options 3687 * @option_count: input - size of the buffer in port options structures, 3688 * output - number of returned port options 3689 * @lport: logical port to call the command with (optional) 3690 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3691 * when PF owns more than 1 port it must be true 3692 * @active_option_idx: index of active port option in returned buffer 3693 * @active_option_valid: active option in returned buffer is valid 3694 * @pending_option_idx: index of pending port option in returned buffer 3695 * @pending_option_valid: pending option in returned buffer is valid 3696 * 3697 * Calls Get Port Options AQC (0x06ea) and verifies result. 3698 */ 3699 int 3700 ice_aq_get_port_options(struct ice_hw *hw, 3701 struct ice_aqc_get_port_options_elem *options, 3702 u8 *option_count, u8 lport, bool lport_valid, 3703 u8 *active_option_idx, bool *active_option_valid, 3704 u8 *pending_option_idx, bool *pending_option_valid) 3705 { 3706 struct ice_aqc_get_port_options *cmd; 3707 struct ice_aq_desc desc; 3708 int status; 3709 u8 i; 3710 3711 /* options buffer shall be able to hold max returned options */ 3712 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3713 return -EINVAL; 3714 3715 cmd = &desc.params.get_port_options; 3716 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3717 3718 if (lport_valid) 3719 cmd->lport_num = lport; 3720 cmd->lport_num_valid = lport_valid; 3721 3722 status = ice_aq_send_cmd(hw, &desc, options, 3723 *option_count * sizeof(*options), NULL); 3724 if (status) 3725 return status; 3726 3727 /* verify direct FW response & set output parameters */ 3728 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3729 cmd->port_options_count); 3730 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3731 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3732 cmd->port_options); 3733 if (*active_option_valid) { 3734 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3735 cmd->port_options); 3736 if (*active_option_idx > (*option_count - 1)) 3737 return -EIO; 3738 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3739 *active_option_idx); 3740 } 3741 3742 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3743 cmd->pending_port_option_status); 3744 if (*pending_option_valid) { 3745 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3746 cmd->pending_port_option_status); 3747 if (*pending_option_idx > (*option_count - 1)) 3748 return -EIO; 3749 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3750 *pending_option_idx); 3751 } 3752 3753 /* mask output options fields */ 3754 for (i = 0; i < *option_count; i++) { 3755 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3756 options[i].pmd); 3757 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3758 options[i].max_lane_speed); 3759 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3760 options[i].pmd, options[i].max_lane_speed); 3761 } 3762 3763 return 0; 3764 } 3765 3766 /** 3767 * ice_aq_set_port_option 3768 * @hw: pointer to the HW struct 3769 * @lport: logical port to call the command with 3770 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3771 * when PF owns more than 1 port it must be true 3772 * @new_option: new port option to be written 3773 * 3774 * Calls Set Port Options AQC (0x06eb). 3775 */ 3776 int 3777 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3778 u8 new_option) 3779 { 3780 struct ice_aqc_set_port_option *cmd; 3781 struct ice_aq_desc desc; 3782 3783 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3784 return -EINVAL; 3785 3786 cmd = &desc.params.set_port_option; 3787 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3788 3789 if (lport_valid) 3790 cmd->lport_num = lport; 3791 3792 cmd->lport_num_valid = lport_valid; 3793 cmd->selected_port_option = new_option; 3794 3795 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3796 } 3797 3798 /** 3799 * ice_aq_sff_eeprom 3800 * @hw: pointer to the HW struct 3801 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3802 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3803 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3804 * @page: QSFP page 3805 * @set_page: set or ignore the page 3806 * @data: pointer to data buffer to be read/written to the I2C device. 3807 * @length: 1-16 for read, 1 for write. 3808 * @write: 0 read, 1 for write. 3809 * @cd: pointer to command details structure or NULL 3810 * 3811 * Read/Write SFF EEPROM (0x06EE) 3812 */ 3813 int 3814 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3815 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3816 bool write, struct ice_sq_cd *cd) 3817 { 3818 struct ice_aqc_sff_eeprom *cmd; 3819 struct ice_aq_desc desc; 3820 int status; 3821 3822 if (!data || (mem_addr & 0xff00)) 3823 return -EINVAL; 3824 3825 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3826 cmd = &desc.params.read_write_sff_param; 3827 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3828 cmd->lport_num = (u8)(lport & 0xff); 3829 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3830 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3831 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3832 ((set_page << 3833 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3834 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3835 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3836 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3837 if (write) 3838 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3839 3840 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3841 return status; 3842 } 3843 3844 /** 3845 * __ice_aq_get_set_rss_lut 3846 * @hw: pointer to the hardware structure 3847 * @params: RSS LUT parameters 3848 * @set: set true to set the table, false to get the table 3849 * 3850 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3851 */ 3852 static int 3853 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3854 { 3855 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3856 struct ice_aqc_get_set_rss_lut *cmd_resp; 3857 struct ice_aq_desc desc; 3858 int status; 3859 u8 *lut; 3860 3861 if (!params) 3862 return -EINVAL; 3863 3864 vsi_handle = params->vsi_handle; 3865 lut = params->lut; 3866 3867 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3868 return -EINVAL; 3869 3870 lut_size = params->lut_size; 3871 lut_type = params->lut_type; 3872 glob_lut_idx = params->global_lut_id; 3873 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3874 3875 cmd_resp = &desc.params.get_set_rss_lut; 3876 3877 if (set) { 3878 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3879 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3880 } else { 3881 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3882 } 3883 3884 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3885 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3886 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3887 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3888 3889 switch (lut_type) { 3890 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3891 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3892 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3893 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3894 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3895 break; 3896 default: 3897 status = -EINVAL; 3898 goto ice_aq_get_set_rss_lut_exit; 3899 } 3900 3901 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3902 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3903 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3904 3905 if (!set) 3906 goto ice_aq_get_set_rss_lut_send; 3907 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3908 if (!set) 3909 goto ice_aq_get_set_rss_lut_send; 3910 } else { 3911 goto ice_aq_get_set_rss_lut_send; 3912 } 3913 3914 /* LUT size is only valid for Global and PF table types */ 3915 switch (lut_size) { 3916 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3917 break; 3918 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3919 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3920 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3921 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3922 break; 3923 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3924 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3925 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3926 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3927 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3928 break; 3929 } 3930 fallthrough; 3931 default: 3932 status = -EINVAL; 3933 goto ice_aq_get_set_rss_lut_exit; 3934 } 3935 3936 ice_aq_get_set_rss_lut_send: 3937 cmd_resp->flags = cpu_to_le16(flags); 3938 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3939 3940 ice_aq_get_set_rss_lut_exit: 3941 return status; 3942 } 3943 3944 /** 3945 * ice_aq_get_rss_lut 3946 * @hw: pointer to the hardware structure 3947 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3948 * 3949 * get the RSS lookup table, PF or VSI type 3950 */ 3951 int 3952 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3953 { 3954 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3955 } 3956 3957 /** 3958 * ice_aq_set_rss_lut 3959 * @hw: pointer to the hardware structure 3960 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3961 * 3962 * set the RSS lookup table, PF or VSI type 3963 */ 3964 int 3965 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3966 { 3967 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3968 } 3969 3970 /** 3971 * __ice_aq_get_set_rss_key 3972 * @hw: pointer to the HW struct 3973 * @vsi_id: VSI FW index 3974 * @key: pointer to key info struct 3975 * @set: set true to set the key, false to get the key 3976 * 3977 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3978 */ 3979 static int 3980 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3981 struct ice_aqc_get_set_rss_keys *key, bool set) 3982 { 3983 struct ice_aqc_get_set_rss_key *cmd_resp; 3984 u16 key_size = sizeof(*key); 3985 struct ice_aq_desc desc; 3986 3987 cmd_resp = &desc.params.get_set_rss_key; 3988 3989 if (set) { 3990 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3991 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3992 } else { 3993 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3994 } 3995 3996 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3997 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3998 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3999 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 4000 4001 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4002 } 4003 4004 /** 4005 * ice_aq_get_rss_key 4006 * @hw: pointer to the HW struct 4007 * @vsi_handle: software VSI handle 4008 * @key: pointer to key info struct 4009 * 4010 * get the RSS key per VSI 4011 */ 4012 int 4013 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4014 struct ice_aqc_get_set_rss_keys *key) 4015 { 4016 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4017 return -EINVAL; 4018 4019 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4020 key, false); 4021 } 4022 4023 /** 4024 * ice_aq_set_rss_key 4025 * @hw: pointer to the HW struct 4026 * @vsi_handle: software VSI handle 4027 * @keys: pointer to key info struct 4028 * 4029 * set the RSS key per VSI 4030 */ 4031 int 4032 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4033 struct ice_aqc_get_set_rss_keys *keys) 4034 { 4035 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4036 return -EINVAL; 4037 4038 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4039 keys, true); 4040 } 4041 4042 /** 4043 * ice_aq_add_lan_txq 4044 * @hw: pointer to the hardware structure 4045 * @num_qgrps: Number of added queue groups 4046 * @qg_list: list of queue groups to be added 4047 * @buf_size: size of buffer for indirect command 4048 * @cd: pointer to command details structure or NULL 4049 * 4050 * Add Tx LAN queue (0x0C30) 4051 * 4052 * NOTE: 4053 * Prior to calling add Tx LAN queue: 4054 * Initialize the following as part of the Tx queue context: 4055 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4056 * Cache profile and Packet shaper profile. 4057 * 4058 * After add Tx LAN queue AQ command is completed: 4059 * Interrupts should be associated with specific queues, 4060 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4061 * flow. 4062 */ 4063 static int 4064 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4065 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4066 struct ice_sq_cd *cd) 4067 { 4068 struct ice_aqc_add_tx_qgrp *list; 4069 struct ice_aqc_add_txqs *cmd; 4070 struct ice_aq_desc desc; 4071 u16 i, sum_size = 0; 4072 4073 cmd = &desc.params.add_txqs; 4074 4075 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4076 4077 if (!qg_list) 4078 return -EINVAL; 4079 4080 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4081 return -EINVAL; 4082 4083 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4084 sum_size += struct_size(list, txqs, list->num_txqs); 4085 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4086 list->num_txqs); 4087 } 4088 4089 if (buf_size != sum_size) 4090 return -EINVAL; 4091 4092 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4093 4094 cmd->num_qgrps = num_qgrps; 4095 4096 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4097 } 4098 4099 /** 4100 * ice_aq_dis_lan_txq 4101 * @hw: pointer to the hardware structure 4102 * @num_qgrps: number of groups in the list 4103 * @qg_list: the list of groups to disable 4104 * @buf_size: the total size of the qg_list buffer in bytes 4105 * @rst_src: if called due to reset, specifies the reset source 4106 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4107 * @cd: pointer to command details structure or NULL 4108 * 4109 * Disable LAN Tx queue (0x0C31) 4110 */ 4111 static int 4112 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4113 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4114 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4115 struct ice_sq_cd *cd) 4116 { 4117 struct ice_aqc_dis_txq_item *item; 4118 struct ice_aqc_dis_txqs *cmd; 4119 struct ice_aq_desc desc; 4120 u16 i, sz = 0; 4121 int status; 4122 4123 cmd = &desc.params.dis_txqs; 4124 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4125 4126 /* qg_list can be NULL only in VM/VF reset flow */ 4127 if (!qg_list && !rst_src) 4128 return -EINVAL; 4129 4130 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4131 return -EINVAL; 4132 4133 cmd->num_entries = num_qgrps; 4134 4135 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4136 ICE_AQC_Q_DIS_TIMEOUT_M); 4137 4138 switch (rst_src) { 4139 case ICE_VM_RESET: 4140 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4141 cmd->vmvf_and_timeout |= 4142 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4143 break; 4144 case ICE_VF_RESET: 4145 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4146 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4147 cmd->vmvf_and_timeout |= 4148 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4149 ICE_AQC_Q_DIS_VMVF_NUM_M); 4150 break; 4151 case ICE_NO_RESET: 4152 default: 4153 break; 4154 } 4155 4156 /* flush pipe on time out */ 4157 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4158 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4159 if (!qg_list) 4160 goto do_aq; 4161 4162 /* set RD bit to indicate that command buffer is provided by the driver 4163 * and it needs to be read by the firmware 4164 */ 4165 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4166 4167 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4168 u16 item_size = struct_size(item, q_id, item->num_qs); 4169 4170 /* If the num of queues is even, add 2 bytes of padding */ 4171 if ((item->num_qs % 2) == 0) 4172 item_size += 2; 4173 4174 sz += item_size; 4175 4176 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4177 } 4178 4179 if (buf_size != sz) 4180 return -EINVAL; 4181 4182 do_aq: 4183 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4184 if (status) { 4185 if (!qg_list) 4186 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4187 vmvf_num, hw->adminq.sq_last_status); 4188 else 4189 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4190 le16_to_cpu(qg_list[0].q_id[0]), 4191 hw->adminq.sq_last_status); 4192 } 4193 return status; 4194 } 4195 4196 /** 4197 * ice_aq_add_rdma_qsets 4198 * @hw: pointer to the hardware structure 4199 * @num_qset_grps: Number of RDMA Qset groups 4200 * @qset_list: list of Qset groups to be added 4201 * @buf_size: size of buffer for indirect command 4202 * @cd: pointer to command details structure or NULL 4203 * 4204 * Add Tx RDMA Qsets (0x0C33) 4205 */ 4206 static int 4207 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4208 struct ice_aqc_add_rdma_qset_data *qset_list, 4209 u16 buf_size, struct ice_sq_cd *cd) 4210 { 4211 struct ice_aqc_add_rdma_qset_data *list; 4212 struct ice_aqc_add_rdma_qset *cmd; 4213 struct ice_aq_desc desc; 4214 u16 i, sum_size = 0; 4215 4216 cmd = &desc.params.add_rdma_qset; 4217 4218 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4219 4220 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4221 return -EINVAL; 4222 4223 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4224 u16 num_qsets = le16_to_cpu(list->num_qsets); 4225 4226 sum_size += struct_size(list, rdma_qsets, num_qsets); 4227 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4228 num_qsets); 4229 } 4230 4231 if (buf_size != sum_size) 4232 return -EINVAL; 4233 4234 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4235 4236 cmd->num_qset_grps = num_qset_grps; 4237 4238 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4239 } 4240 4241 /* End of FW Admin Queue command wrappers */ 4242 4243 /** 4244 * ice_write_byte - write a byte to a packed context structure 4245 * @src_ctx: the context structure to read from 4246 * @dest_ctx: the context to be written to 4247 * @ce_info: a description of the struct to be filled 4248 */ 4249 static void 4250 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4251 { 4252 u8 src_byte, dest_byte, mask; 4253 u8 *from, *dest; 4254 u16 shift_width; 4255 4256 /* copy from the next struct field */ 4257 from = src_ctx + ce_info->offset; 4258 4259 /* prepare the bits and mask */ 4260 shift_width = ce_info->lsb % 8; 4261 mask = (u8)(BIT(ce_info->width) - 1); 4262 4263 src_byte = *from; 4264 src_byte &= mask; 4265 4266 /* shift to correct alignment */ 4267 mask <<= shift_width; 4268 src_byte <<= shift_width; 4269 4270 /* get the current bits from the target bit string */ 4271 dest = dest_ctx + (ce_info->lsb / 8); 4272 4273 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4274 4275 dest_byte &= ~mask; /* get the bits not changing */ 4276 dest_byte |= src_byte; /* add in the new bits */ 4277 4278 /* put it all back */ 4279 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4280 } 4281 4282 /** 4283 * ice_write_word - write a word to a packed context structure 4284 * @src_ctx: the context structure to read from 4285 * @dest_ctx: the context to be written to 4286 * @ce_info: a description of the struct to be filled 4287 */ 4288 static void 4289 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4290 { 4291 u16 src_word, mask; 4292 __le16 dest_word; 4293 u8 *from, *dest; 4294 u16 shift_width; 4295 4296 /* copy from the next struct field */ 4297 from = src_ctx + ce_info->offset; 4298 4299 /* prepare the bits and mask */ 4300 shift_width = ce_info->lsb % 8; 4301 mask = BIT(ce_info->width) - 1; 4302 4303 /* don't swizzle the bits until after the mask because the mask bits 4304 * will be in a different bit position on big endian machines 4305 */ 4306 src_word = *(u16 *)from; 4307 src_word &= mask; 4308 4309 /* shift to correct alignment */ 4310 mask <<= shift_width; 4311 src_word <<= shift_width; 4312 4313 /* get the current bits from the target bit string */ 4314 dest = dest_ctx + (ce_info->lsb / 8); 4315 4316 memcpy(&dest_word, dest, sizeof(dest_word)); 4317 4318 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4319 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4320 4321 /* put it all back */ 4322 memcpy(dest, &dest_word, sizeof(dest_word)); 4323 } 4324 4325 /** 4326 * ice_write_dword - write a dword to a packed context structure 4327 * @src_ctx: the context structure to read from 4328 * @dest_ctx: the context to be written to 4329 * @ce_info: a description of the struct to be filled 4330 */ 4331 static void 4332 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4333 { 4334 u32 src_dword, mask; 4335 __le32 dest_dword; 4336 u8 *from, *dest; 4337 u16 shift_width; 4338 4339 /* copy from the next struct field */ 4340 from = src_ctx + ce_info->offset; 4341 4342 /* prepare the bits and mask */ 4343 shift_width = ce_info->lsb % 8; 4344 4345 /* if the field width is exactly 32 on an x86 machine, then the shift 4346 * operation will not work because the SHL instructions count is masked 4347 * to 5 bits so the shift will do nothing 4348 */ 4349 if (ce_info->width < 32) 4350 mask = BIT(ce_info->width) - 1; 4351 else 4352 mask = (u32)~0; 4353 4354 /* don't swizzle the bits until after the mask because the mask bits 4355 * will be in a different bit position on big endian machines 4356 */ 4357 src_dword = *(u32 *)from; 4358 src_dword &= mask; 4359 4360 /* shift to correct alignment */ 4361 mask <<= shift_width; 4362 src_dword <<= shift_width; 4363 4364 /* get the current bits from the target bit string */ 4365 dest = dest_ctx + (ce_info->lsb / 8); 4366 4367 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4368 4369 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4370 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4371 4372 /* put it all back */ 4373 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4374 } 4375 4376 /** 4377 * ice_write_qword - write a qword to a packed context structure 4378 * @src_ctx: the context structure to read from 4379 * @dest_ctx: the context to be written to 4380 * @ce_info: a description of the struct to be filled 4381 */ 4382 static void 4383 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4384 { 4385 u64 src_qword, mask; 4386 __le64 dest_qword; 4387 u8 *from, *dest; 4388 u16 shift_width; 4389 4390 /* copy from the next struct field */ 4391 from = src_ctx + ce_info->offset; 4392 4393 /* prepare the bits and mask */ 4394 shift_width = ce_info->lsb % 8; 4395 4396 /* if the field width is exactly 64 on an x86 machine, then the shift 4397 * operation will not work because the SHL instructions count is masked 4398 * to 6 bits so the shift will do nothing 4399 */ 4400 if (ce_info->width < 64) 4401 mask = BIT_ULL(ce_info->width) - 1; 4402 else 4403 mask = (u64)~0; 4404 4405 /* don't swizzle the bits until after the mask because the mask bits 4406 * will be in a different bit position on big endian machines 4407 */ 4408 src_qword = *(u64 *)from; 4409 src_qword &= mask; 4410 4411 /* shift to correct alignment */ 4412 mask <<= shift_width; 4413 src_qword <<= shift_width; 4414 4415 /* get the current bits from the target bit string */ 4416 dest = dest_ctx + (ce_info->lsb / 8); 4417 4418 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4419 4420 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4421 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4422 4423 /* put it all back */ 4424 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4425 } 4426 4427 /** 4428 * ice_set_ctx - set context bits in packed structure 4429 * @hw: pointer to the hardware structure 4430 * @src_ctx: pointer to a generic non-packed context structure 4431 * @dest_ctx: pointer to memory for the packed structure 4432 * @ce_info: a description of the structure to be transformed 4433 */ 4434 int 4435 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4436 const struct ice_ctx_ele *ce_info) 4437 { 4438 int f; 4439 4440 for (f = 0; ce_info[f].width; f++) { 4441 /* We have to deal with each element of the FW response 4442 * using the correct size so that we are correct regardless 4443 * of the endianness of the machine. 4444 */ 4445 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4446 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4447 f, ce_info[f].width, ce_info[f].size_of); 4448 continue; 4449 } 4450 switch (ce_info[f].size_of) { 4451 case sizeof(u8): 4452 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4453 break; 4454 case sizeof(u16): 4455 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4456 break; 4457 case sizeof(u32): 4458 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4459 break; 4460 case sizeof(u64): 4461 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4462 break; 4463 default: 4464 return -EINVAL; 4465 } 4466 } 4467 4468 return 0; 4469 } 4470 4471 /** 4472 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4473 * @hw: pointer to the HW struct 4474 * @vsi_handle: software VSI handle 4475 * @tc: TC number 4476 * @q_handle: software queue handle 4477 */ 4478 struct ice_q_ctx * 4479 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4480 { 4481 struct ice_vsi_ctx *vsi; 4482 struct ice_q_ctx *q_ctx; 4483 4484 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4485 if (!vsi) 4486 return NULL; 4487 if (q_handle >= vsi->num_lan_q_entries[tc]) 4488 return NULL; 4489 if (!vsi->lan_q_ctx[tc]) 4490 return NULL; 4491 q_ctx = vsi->lan_q_ctx[tc]; 4492 return &q_ctx[q_handle]; 4493 } 4494 4495 /** 4496 * ice_ena_vsi_txq 4497 * @pi: port information structure 4498 * @vsi_handle: software VSI handle 4499 * @tc: TC number 4500 * @q_handle: software queue handle 4501 * @num_qgrps: Number of added queue groups 4502 * @buf: list of queue groups to be added 4503 * @buf_size: size of buffer for indirect command 4504 * @cd: pointer to command details structure or NULL 4505 * 4506 * This function adds one LAN queue 4507 */ 4508 int 4509 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4510 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4511 struct ice_sq_cd *cd) 4512 { 4513 struct ice_aqc_txsched_elem_data node = { 0 }; 4514 struct ice_sched_node *parent; 4515 struct ice_q_ctx *q_ctx; 4516 struct ice_hw *hw; 4517 int status; 4518 4519 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4520 return -EIO; 4521 4522 if (num_qgrps > 1 || buf->num_txqs > 1) 4523 return -ENOSPC; 4524 4525 hw = pi->hw; 4526 4527 if (!ice_is_vsi_valid(hw, vsi_handle)) 4528 return -EINVAL; 4529 4530 mutex_lock(&pi->sched_lock); 4531 4532 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4533 if (!q_ctx) { 4534 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4535 q_handle); 4536 status = -EINVAL; 4537 goto ena_txq_exit; 4538 } 4539 4540 /* find a parent node */ 4541 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4542 ICE_SCHED_NODE_OWNER_LAN); 4543 if (!parent) { 4544 status = -EINVAL; 4545 goto ena_txq_exit; 4546 } 4547 4548 buf->parent_teid = parent->info.node_teid; 4549 node.parent_teid = parent->info.node_teid; 4550 /* Mark that the values in the "generic" section as valid. The default 4551 * value in the "generic" section is zero. This means that : 4552 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4553 * - 0 priority among siblings, indicated by Bit 1-3. 4554 * - WFQ, indicated by Bit 4. 4555 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4556 * Bit 5-6. 4557 * - Bit 7 is reserved. 4558 * Without setting the generic section as valid in valid_sections, the 4559 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4560 */ 4561 buf->txqs[0].info.valid_sections = 4562 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4563 ICE_AQC_ELEM_VALID_EIR; 4564 buf->txqs[0].info.generic = 0; 4565 buf->txqs[0].info.cir_bw.bw_profile_idx = 4566 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4567 buf->txqs[0].info.cir_bw.bw_alloc = 4568 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4569 buf->txqs[0].info.eir_bw.bw_profile_idx = 4570 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4571 buf->txqs[0].info.eir_bw.bw_alloc = 4572 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4573 4574 /* add the LAN queue */ 4575 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4576 if (status) { 4577 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4578 le16_to_cpu(buf->txqs[0].txq_id), 4579 hw->adminq.sq_last_status); 4580 goto ena_txq_exit; 4581 } 4582 4583 node.node_teid = buf->txqs[0].q_teid; 4584 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4585 q_ctx->q_handle = q_handle; 4586 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4587 4588 /* add a leaf node into scheduler tree queue layer */ 4589 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4590 if (!status) 4591 status = ice_sched_replay_q_bw(pi, q_ctx); 4592 4593 ena_txq_exit: 4594 mutex_unlock(&pi->sched_lock); 4595 return status; 4596 } 4597 4598 /** 4599 * ice_dis_vsi_txq 4600 * @pi: port information structure 4601 * @vsi_handle: software VSI handle 4602 * @tc: TC number 4603 * @num_queues: number of queues 4604 * @q_handles: pointer to software queue handle array 4605 * @q_ids: pointer to the q_id array 4606 * @q_teids: pointer to queue node teids 4607 * @rst_src: if called due to reset, specifies the reset source 4608 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4609 * @cd: pointer to command details structure or NULL 4610 * 4611 * This function removes queues and their corresponding nodes in SW DB 4612 */ 4613 int 4614 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4615 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4616 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4617 struct ice_sq_cd *cd) 4618 { 4619 struct ice_aqc_dis_txq_item *qg_list; 4620 struct ice_q_ctx *q_ctx; 4621 int status = -ENOENT; 4622 struct ice_hw *hw; 4623 u16 i, buf_size; 4624 4625 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4626 return -EIO; 4627 4628 hw = pi->hw; 4629 4630 if (!num_queues) { 4631 /* if queue is disabled already yet the disable queue command 4632 * has to be sent to complete the VF reset, then call 4633 * ice_aq_dis_lan_txq without any queue information 4634 */ 4635 if (rst_src) 4636 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4637 vmvf_num, NULL); 4638 return -EIO; 4639 } 4640 4641 buf_size = struct_size(qg_list, q_id, 1); 4642 qg_list = kzalloc(buf_size, GFP_KERNEL); 4643 if (!qg_list) 4644 return -ENOMEM; 4645 4646 mutex_lock(&pi->sched_lock); 4647 4648 for (i = 0; i < num_queues; i++) { 4649 struct ice_sched_node *node; 4650 4651 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4652 if (!node) 4653 continue; 4654 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4655 if (!q_ctx) { 4656 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4657 q_handles[i]); 4658 continue; 4659 } 4660 if (q_ctx->q_handle != q_handles[i]) { 4661 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4662 q_ctx->q_handle, q_handles[i]); 4663 continue; 4664 } 4665 qg_list->parent_teid = node->info.parent_teid; 4666 qg_list->num_qs = 1; 4667 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4668 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4669 vmvf_num, cd); 4670 4671 if (status) 4672 break; 4673 ice_free_sched_node(pi, node); 4674 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4675 } 4676 mutex_unlock(&pi->sched_lock); 4677 kfree(qg_list); 4678 return status; 4679 } 4680 4681 /** 4682 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4683 * @pi: port information structure 4684 * @vsi_handle: software VSI handle 4685 * @tc_bitmap: TC bitmap 4686 * @maxqs: max queues array per TC 4687 * @owner: LAN or RDMA 4688 * 4689 * This function adds/updates the VSI queues per TC. 4690 */ 4691 static int 4692 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4693 u16 *maxqs, u8 owner) 4694 { 4695 int status = 0; 4696 u8 i; 4697 4698 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4699 return -EIO; 4700 4701 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4702 return -EINVAL; 4703 4704 mutex_lock(&pi->sched_lock); 4705 4706 ice_for_each_traffic_class(i) { 4707 /* configuration is possible only if TC node is present */ 4708 if (!ice_sched_get_tc_node(pi, i)) 4709 continue; 4710 4711 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4712 ice_is_tc_ena(tc_bitmap, i)); 4713 if (status) 4714 break; 4715 } 4716 4717 mutex_unlock(&pi->sched_lock); 4718 return status; 4719 } 4720 4721 /** 4722 * ice_cfg_vsi_lan - configure VSI LAN queues 4723 * @pi: port information structure 4724 * @vsi_handle: software VSI handle 4725 * @tc_bitmap: TC bitmap 4726 * @max_lanqs: max LAN queues array per TC 4727 * 4728 * This function adds/updates the VSI LAN queues per TC. 4729 */ 4730 int 4731 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4732 u16 *max_lanqs) 4733 { 4734 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4735 ICE_SCHED_NODE_OWNER_LAN); 4736 } 4737 4738 /** 4739 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4740 * @pi: port information structure 4741 * @vsi_handle: software VSI handle 4742 * @tc_bitmap: TC bitmap 4743 * @max_rdmaqs: max RDMA queues array per TC 4744 * 4745 * This function adds/updates the VSI RDMA queues per TC. 4746 */ 4747 int 4748 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4749 u16 *max_rdmaqs) 4750 { 4751 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4752 ICE_SCHED_NODE_OWNER_RDMA); 4753 } 4754 4755 /** 4756 * ice_ena_vsi_rdma_qset 4757 * @pi: port information structure 4758 * @vsi_handle: software VSI handle 4759 * @tc: TC number 4760 * @rdma_qset: pointer to RDMA Qset 4761 * @num_qsets: number of RDMA Qsets 4762 * @qset_teid: pointer to Qset node TEIDs 4763 * 4764 * This function adds RDMA Qset 4765 */ 4766 int 4767 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4768 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4769 { 4770 struct ice_aqc_txsched_elem_data node = { 0 }; 4771 struct ice_aqc_add_rdma_qset_data *buf; 4772 struct ice_sched_node *parent; 4773 struct ice_hw *hw; 4774 u16 i, buf_size; 4775 int ret; 4776 4777 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4778 return -EIO; 4779 hw = pi->hw; 4780 4781 if (!ice_is_vsi_valid(hw, vsi_handle)) 4782 return -EINVAL; 4783 4784 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4785 buf = kzalloc(buf_size, GFP_KERNEL); 4786 if (!buf) 4787 return -ENOMEM; 4788 mutex_lock(&pi->sched_lock); 4789 4790 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4791 ICE_SCHED_NODE_OWNER_RDMA); 4792 if (!parent) { 4793 ret = -EINVAL; 4794 goto rdma_error_exit; 4795 } 4796 buf->parent_teid = parent->info.node_teid; 4797 node.parent_teid = parent->info.node_teid; 4798 4799 buf->num_qsets = cpu_to_le16(num_qsets); 4800 for (i = 0; i < num_qsets; i++) { 4801 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4802 buf->rdma_qsets[i].info.valid_sections = 4803 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4804 ICE_AQC_ELEM_VALID_EIR; 4805 buf->rdma_qsets[i].info.generic = 0; 4806 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4807 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4808 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4809 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4810 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4811 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4812 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4813 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4814 } 4815 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4816 if (ret) { 4817 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4818 goto rdma_error_exit; 4819 } 4820 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4821 for (i = 0; i < num_qsets; i++) { 4822 node.node_teid = buf->rdma_qsets[i].qset_teid; 4823 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4824 &node); 4825 if (ret) 4826 break; 4827 qset_teid[i] = le32_to_cpu(node.node_teid); 4828 } 4829 rdma_error_exit: 4830 mutex_unlock(&pi->sched_lock); 4831 kfree(buf); 4832 return ret; 4833 } 4834 4835 /** 4836 * ice_dis_vsi_rdma_qset - free RDMA resources 4837 * @pi: port_info struct 4838 * @count: number of RDMA Qsets to free 4839 * @qset_teid: TEID of Qset node 4840 * @q_id: list of queue IDs being disabled 4841 */ 4842 int 4843 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4844 u16 *q_id) 4845 { 4846 struct ice_aqc_dis_txq_item *qg_list; 4847 struct ice_hw *hw; 4848 int status = 0; 4849 u16 qg_size; 4850 int i; 4851 4852 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4853 return -EIO; 4854 4855 hw = pi->hw; 4856 4857 qg_size = struct_size(qg_list, q_id, 1); 4858 qg_list = kzalloc(qg_size, GFP_KERNEL); 4859 if (!qg_list) 4860 return -ENOMEM; 4861 4862 mutex_lock(&pi->sched_lock); 4863 4864 for (i = 0; i < count; i++) { 4865 struct ice_sched_node *node; 4866 4867 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4868 if (!node) 4869 continue; 4870 4871 qg_list->parent_teid = node->info.parent_teid; 4872 qg_list->num_qs = 1; 4873 qg_list->q_id[0] = 4874 cpu_to_le16(q_id[i] | 4875 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4876 4877 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4878 ICE_NO_RESET, 0, NULL); 4879 if (status) 4880 break; 4881 4882 ice_free_sched_node(pi, node); 4883 } 4884 4885 mutex_unlock(&pi->sched_lock); 4886 kfree(qg_list); 4887 return status; 4888 } 4889 4890 /** 4891 * ice_replay_pre_init - replay pre initialization 4892 * @hw: pointer to the HW struct 4893 * 4894 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4895 */ 4896 static int ice_replay_pre_init(struct ice_hw *hw) 4897 { 4898 struct ice_switch_info *sw = hw->switch_info; 4899 u8 i; 4900 4901 /* Delete old entries from replay filter list head if there is any */ 4902 ice_rm_all_sw_replay_rule_info(hw); 4903 /* In start of replay, move entries into replay_rules list, it 4904 * will allow adding rules entries back to filt_rules list, 4905 * which is operational list. 4906 */ 4907 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4908 list_replace_init(&sw->recp_list[i].filt_rules, 4909 &sw->recp_list[i].filt_replay_rules); 4910 ice_sched_replay_agg_vsi_preinit(hw); 4911 4912 return 0; 4913 } 4914 4915 /** 4916 * ice_replay_vsi - replay VSI configuration 4917 * @hw: pointer to the HW struct 4918 * @vsi_handle: driver VSI handle 4919 * 4920 * Restore all VSI configuration after reset. It is required to call this 4921 * function with main VSI first. 4922 */ 4923 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4924 { 4925 int status; 4926 4927 if (!ice_is_vsi_valid(hw, vsi_handle)) 4928 return -EINVAL; 4929 4930 /* Replay pre-initialization if there is any */ 4931 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4932 status = ice_replay_pre_init(hw); 4933 if (status) 4934 return status; 4935 } 4936 /* Replay per VSI all RSS configurations */ 4937 status = ice_replay_rss_cfg(hw, vsi_handle); 4938 if (status) 4939 return status; 4940 /* Replay per VSI all filters */ 4941 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4942 if (!status) 4943 status = ice_replay_vsi_agg(hw, vsi_handle); 4944 return status; 4945 } 4946 4947 /** 4948 * ice_replay_post - post replay configuration cleanup 4949 * @hw: pointer to the HW struct 4950 * 4951 * Post replay cleanup. 4952 */ 4953 void ice_replay_post(struct ice_hw *hw) 4954 { 4955 /* Delete old entries from replay filter list head */ 4956 ice_rm_all_sw_replay_rule_info(hw); 4957 ice_sched_replay_agg(hw); 4958 } 4959 4960 /** 4961 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4962 * @hw: ptr to the hardware info 4963 * @reg: offset of 64 bit HW register to read from 4964 * @prev_stat_loaded: bool to specify if previous stats are loaded 4965 * @prev_stat: ptr to previous loaded stat value 4966 * @cur_stat: ptr to current stat value 4967 */ 4968 void 4969 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4970 u64 *prev_stat, u64 *cur_stat) 4971 { 4972 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4973 4974 /* device stats are not reset at PFR, they likely will not be zeroed 4975 * when the driver starts. Thus, save the value from the first read 4976 * without adding to the statistic value so that we report stats which 4977 * count up from zero. 4978 */ 4979 if (!prev_stat_loaded) { 4980 *prev_stat = new_data; 4981 return; 4982 } 4983 4984 /* Calculate the difference between the new and old values, and then 4985 * add it to the software stat value. 4986 */ 4987 if (new_data >= *prev_stat) 4988 *cur_stat += new_data - *prev_stat; 4989 else 4990 /* to manage the potential roll-over */ 4991 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4992 4993 /* Update the previously stored value to prepare for next read */ 4994 *prev_stat = new_data; 4995 } 4996 4997 /** 4998 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4999 * @hw: ptr to the hardware info 5000 * @reg: offset of HW register to read from 5001 * @prev_stat_loaded: bool to specify if previous stats are loaded 5002 * @prev_stat: ptr to previous loaded stat value 5003 * @cur_stat: ptr to current stat value 5004 */ 5005 void 5006 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5007 u64 *prev_stat, u64 *cur_stat) 5008 { 5009 u32 new_data; 5010 5011 new_data = rd32(hw, reg); 5012 5013 /* device stats are not reset at PFR, they likely will not be zeroed 5014 * when the driver starts. Thus, save the value from the first read 5015 * without adding to the statistic value so that we report stats which 5016 * count up from zero. 5017 */ 5018 if (!prev_stat_loaded) { 5019 *prev_stat = new_data; 5020 return; 5021 } 5022 5023 /* Calculate the difference between the new and old values, and then 5024 * add it to the software stat value. 5025 */ 5026 if (new_data >= *prev_stat) 5027 *cur_stat += new_data - *prev_stat; 5028 else 5029 /* to manage the potential roll-over */ 5030 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5031 5032 /* Update the previously stored value to prepare for next read */ 5033 *prev_stat = new_data; 5034 } 5035 5036 /** 5037 * ice_sched_query_elem - query element information from HW 5038 * @hw: pointer to the HW struct 5039 * @node_teid: node TEID to be queried 5040 * @buf: buffer to element information 5041 * 5042 * This function queries HW element information 5043 */ 5044 int 5045 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5046 struct ice_aqc_txsched_elem_data *buf) 5047 { 5048 u16 buf_size, num_elem_ret = 0; 5049 int status; 5050 5051 buf_size = sizeof(*buf); 5052 memset(buf, 0, buf_size); 5053 buf->node_teid = cpu_to_le32(node_teid); 5054 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5055 NULL); 5056 if (status || num_elem_ret != 1) 5057 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5058 return status; 5059 } 5060 5061 /** 5062 * ice_aq_read_i2c 5063 * @hw: pointer to the hw struct 5064 * @topo_addr: topology address for a device to communicate with 5065 * @bus_addr: 7-bit I2C bus address 5066 * @addr: I2C memory address (I2C offset) with up to 16 bits 5067 * @params: I2C parameters: bit [7] - Repeated start, 5068 * bits [6:5] data offset size, 5069 * bit [4] - I2C address type, 5070 * bits [3:0] - data size to read (0-16 bytes) 5071 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5072 * @cd: pointer to command details structure or NULL 5073 * 5074 * Read I2C (0x06E2) 5075 */ 5076 int 5077 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5078 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5079 struct ice_sq_cd *cd) 5080 { 5081 struct ice_aq_desc desc = { 0 }; 5082 struct ice_aqc_i2c *cmd; 5083 u8 data_size; 5084 int status; 5085 5086 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5087 cmd = &desc.params.read_write_i2c; 5088 5089 if (!data) 5090 return -EINVAL; 5091 5092 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5093 5094 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5095 cmd->topo_addr = topo_addr; 5096 cmd->i2c_params = params; 5097 cmd->i2c_addr = addr; 5098 5099 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5100 if (!status) { 5101 struct ice_aqc_read_i2c_resp *resp; 5102 u8 i; 5103 5104 resp = &desc.params.read_i2c_resp; 5105 for (i = 0; i < data_size; i++) { 5106 *data = resp->i2c_data[i]; 5107 data++; 5108 } 5109 } 5110 5111 return status; 5112 } 5113 5114 /** 5115 * ice_aq_write_i2c 5116 * @hw: pointer to the hw struct 5117 * @topo_addr: topology address for a device to communicate with 5118 * @bus_addr: 7-bit I2C bus address 5119 * @addr: I2C memory address (I2C offset) with up to 16 bits 5120 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5121 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5122 * @cd: pointer to command details structure or NULL 5123 * 5124 * Write I2C (0x06E3) 5125 * 5126 * * Return: 5127 * * 0 - Successful write to the i2c device 5128 * * -EINVAL - Data size greater than 4 bytes 5129 * * -EIO - FW error 5130 */ 5131 int 5132 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5133 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5134 struct ice_sq_cd *cd) 5135 { 5136 struct ice_aq_desc desc = { 0 }; 5137 struct ice_aqc_i2c *cmd; 5138 u8 data_size; 5139 5140 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5141 cmd = &desc.params.read_write_i2c; 5142 5143 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5144 5145 /* data_size limited to 4 */ 5146 if (data_size > 4) 5147 return -EINVAL; 5148 5149 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5150 cmd->topo_addr = topo_addr; 5151 cmd->i2c_params = params; 5152 cmd->i2c_addr = addr; 5153 5154 memcpy(cmd->i2c_data, data, data_size); 5155 5156 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5157 } 5158 5159 /** 5160 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5161 * @hw: pointer to the HW struct 5162 * @idx: parameter index to set 5163 * @value: the value to set the parameter to 5164 * @cd: pointer to command details structure or NULL 5165 * 5166 * Set the value of one of the software defined parameters. All PFs connected 5167 * to this device can read the value using ice_aq_get_driver_param. 5168 * 5169 * Note that firmware provides no synchronization or locking, and will not 5170 * save the parameter value during a device reset. It is expected that 5171 * a single PF will write the parameter value, while all other PFs will only 5172 * read it. 5173 */ 5174 int 5175 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5176 u32 value, struct ice_sq_cd *cd) 5177 { 5178 struct ice_aqc_driver_shared_params *cmd; 5179 struct ice_aq_desc desc; 5180 5181 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5182 return -EIO; 5183 5184 cmd = &desc.params.drv_shared_params; 5185 5186 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5187 5188 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5189 cmd->param_indx = idx; 5190 cmd->param_val = cpu_to_le32(value); 5191 5192 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5193 } 5194 5195 /** 5196 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5197 * @hw: pointer to the HW struct 5198 * @idx: parameter index to set 5199 * @value: storage to return the shared parameter 5200 * @cd: pointer to command details structure or NULL 5201 * 5202 * Get the value of one of the software defined parameters. 5203 * 5204 * Note that firmware provides no synchronization or locking. It is expected 5205 * that only a single PF will write a given parameter. 5206 */ 5207 int 5208 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5209 u32 *value, struct ice_sq_cd *cd) 5210 { 5211 struct ice_aqc_driver_shared_params *cmd; 5212 struct ice_aq_desc desc; 5213 int status; 5214 5215 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5216 return -EIO; 5217 5218 cmd = &desc.params.drv_shared_params; 5219 5220 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5221 5222 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5223 cmd->param_indx = idx; 5224 5225 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5226 if (status) 5227 return status; 5228 5229 *value = le32_to_cpu(cmd->param_val); 5230 5231 return 0; 5232 } 5233 5234 /** 5235 * ice_aq_set_gpio 5236 * @hw: pointer to the hw struct 5237 * @gpio_ctrl_handle: GPIO controller node handle 5238 * @pin_idx: IO Number of the GPIO that needs to be set 5239 * @value: SW provide IO value to set in the LSB 5240 * @cd: pointer to command details structure or NULL 5241 * 5242 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5243 */ 5244 int 5245 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5246 struct ice_sq_cd *cd) 5247 { 5248 struct ice_aqc_gpio *cmd; 5249 struct ice_aq_desc desc; 5250 5251 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5252 cmd = &desc.params.read_write_gpio; 5253 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5254 cmd->gpio_num = pin_idx; 5255 cmd->gpio_val = value ? 1 : 0; 5256 5257 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5258 } 5259 5260 /** 5261 * ice_aq_get_gpio 5262 * @hw: pointer to the hw struct 5263 * @gpio_ctrl_handle: GPIO controller node handle 5264 * @pin_idx: IO Number of the GPIO that needs to be set 5265 * @value: IO value read 5266 * @cd: pointer to command details structure or NULL 5267 * 5268 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5269 * the topology 5270 */ 5271 int 5272 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5273 bool *value, struct ice_sq_cd *cd) 5274 { 5275 struct ice_aqc_gpio *cmd; 5276 struct ice_aq_desc desc; 5277 int status; 5278 5279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5280 cmd = &desc.params.read_write_gpio; 5281 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5282 cmd->gpio_num = pin_idx; 5283 5284 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5285 if (status) 5286 return status; 5287 5288 *value = !!cmd->gpio_val; 5289 return 0; 5290 } 5291 5292 /** 5293 * ice_is_fw_api_min_ver 5294 * @hw: pointer to the hardware structure 5295 * @maj: major version 5296 * @min: minor version 5297 * @patch: patch version 5298 * 5299 * Checks if the firmware API is minimum version 5300 */ 5301 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5302 { 5303 if (hw->api_maj_ver == maj) { 5304 if (hw->api_min_ver > min) 5305 return true; 5306 if (hw->api_min_ver == min && hw->api_patch >= patch) 5307 return true; 5308 } else if (hw->api_maj_ver > maj) { 5309 return true; 5310 } 5311 5312 return false; 5313 } 5314 5315 /** 5316 * ice_fw_supports_link_override 5317 * @hw: pointer to the hardware structure 5318 * 5319 * Checks if the firmware supports link override 5320 */ 5321 bool ice_fw_supports_link_override(struct ice_hw *hw) 5322 { 5323 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5324 ICE_FW_API_LINK_OVERRIDE_MIN, 5325 ICE_FW_API_LINK_OVERRIDE_PATCH); 5326 } 5327 5328 /** 5329 * ice_get_link_default_override 5330 * @ldo: pointer to the link default override struct 5331 * @pi: pointer to the port info struct 5332 * 5333 * Gets the link default override for a port 5334 */ 5335 int 5336 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5337 struct ice_port_info *pi) 5338 { 5339 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5340 struct ice_hw *hw = pi->hw; 5341 int status; 5342 5343 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5344 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5345 if (status) { 5346 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5347 return status; 5348 } 5349 5350 /* Each port has its own config; calculate for our port */ 5351 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5352 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5353 5354 /* link options first */ 5355 status = ice_read_sr_word(hw, tlv_start, &buf); 5356 if (status) { 5357 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5358 return status; 5359 } 5360 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5361 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5362 ICE_LINK_OVERRIDE_PHY_CFG_S; 5363 5364 /* link PHY config */ 5365 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5366 status = ice_read_sr_word(hw, offset, &buf); 5367 if (status) { 5368 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5369 return status; 5370 } 5371 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5372 5373 /* PHY types low */ 5374 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5375 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5376 status = ice_read_sr_word(hw, (offset + i), &buf); 5377 if (status) { 5378 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5379 return status; 5380 } 5381 /* shift 16 bits at a time to fill 64 bits */ 5382 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5383 } 5384 5385 /* PHY types high */ 5386 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5387 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5388 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5389 status = ice_read_sr_word(hw, (offset + i), &buf); 5390 if (status) { 5391 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5392 return status; 5393 } 5394 /* shift 16 bits at a time to fill 64 bits */ 5395 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5396 } 5397 5398 return status; 5399 } 5400 5401 /** 5402 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5403 * @caps: get PHY capability data 5404 */ 5405 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5406 { 5407 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5408 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5409 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5410 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5411 return true; 5412 5413 return false; 5414 } 5415 5416 /** 5417 * ice_aq_set_lldp_mib - Set the LLDP MIB 5418 * @hw: pointer to the HW struct 5419 * @mib_type: Local, Remote or both Local and Remote MIBs 5420 * @buf: pointer to the caller-supplied buffer to store the MIB block 5421 * @buf_size: size of the buffer (in bytes) 5422 * @cd: pointer to command details structure or NULL 5423 * 5424 * Set the LLDP MIB. (0x0A08) 5425 */ 5426 int 5427 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5428 struct ice_sq_cd *cd) 5429 { 5430 struct ice_aqc_lldp_set_local_mib *cmd; 5431 struct ice_aq_desc desc; 5432 5433 cmd = &desc.params.lldp_set_mib; 5434 5435 if (buf_size == 0 || !buf) 5436 return -EINVAL; 5437 5438 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5439 5440 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5441 desc.datalen = cpu_to_le16(buf_size); 5442 5443 cmd->type = mib_type; 5444 cmd->length = cpu_to_le16(buf_size); 5445 5446 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5447 } 5448 5449 /** 5450 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5451 * @hw: pointer to HW struct 5452 */ 5453 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5454 { 5455 if (hw->mac_type != ICE_MAC_E810) 5456 return false; 5457 5458 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5459 ICE_FW_API_LLDP_FLTR_MIN, 5460 ICE_FW_API_LLDP_FLTR_PATCH); 5461 } 5462 5463 /** 5464 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5465 * @hw: pointer to HW struct 5466 * @vsi_num: absolute HW index for VSI 5467 * @add: boolean for if adding or removing a filter 5468 */ 5469 int 5470 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5471 { 5472 struct ice_aqc_lldp_filter_ctrl *cmd; 5473 struct ice_aq_desc desc; 5474 5475 cmd = &desc.params.lldp_filter_ctrl; 5476 5477 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5478 5479 if (add) 5480 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5481 else 5482 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5483 5484 cmd->vsi_num = cpu_to_le16(vsi_num); 5485 5486 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5487 } 5488 5489 /** 5490 * ice_fw_supports_report_dflt_cfg 5491 * @hw: pointer to the hardware structure 5492 * 5493 * Checks if the firmware supports report default configuration 5494 */ 5495 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5496 { 5497 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 5498 ICE_FW_API_REPORT_DFLT_CFG_MIN, 5499 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 5500 } 5501