1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473 } 474 475 /** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496 { 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520 } 521 522 /** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529 static bool ice_is_media_cage_present(struct ice_port_info *pi) 530 { 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538 } 539 540 /** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545 { 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655 } 656 657 /** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665 { 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673 } 674 675 /** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684 int 685 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687 { 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775 } 776 777 /** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785 static void 786 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788 { 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824 } 825 826 /** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834 int 835 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 { 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852 } 853 854 /** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859 { 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882 } 883 884 /** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889 { 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932 } 933 934 /** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942 { 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958 } 959 960 /** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968 { 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985 } 986 987 /** 988 * ice_init_hw - main hardware initialization routine 989 * @hw: pointer to the hardware structure 990 */ 991 int ice_init_hw(struct ice_hw *hw) 992 { 993 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 994 void *mac_buf __free(kfree) = NULL; 995 u16 mac_buf_len; 996 int status; 997 998 /* Set MAC type based on DeviceID */ 999 status = ice_set_mac_type(hw); 1000 if (status) 1001 return status; 1002 1003 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1004 1005 status = ice_reset(hw, ICE_RESET_PFR); 1006 if (status) 1007 return status; 1008 1009 ice_get_itr_intrl_gran(hw); 1010 1011 status = ice_create_all_ctrlq(hw); 1012 if (status) 1013 goto err_unroll_cqinit; 1014 1015 status = ice_fwlog_init(hw); 1016 if (status) 1017 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1018 status); 1019 1020 status = ice_clear_pf_cfg(hw); 1021 if (status) 1022 goto err_unroll_cqinit; 1023 1024 /* Set bit to enable Flow Director filters */ 1025 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1026 INIT_LIST_HEAD(&hw->fdir_list_head); 1027 1028 ice_clear_pxe_mode(hw); 1029 1030 status = ice_init_nvm(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 status = ice_get_caps(hw); 1035 if (status) 1036 goto err_unroll_cqinit; 1037 1038 if (!hw->port_info) 1039 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1040 sizeof(*hw->port_info), 1041 GFP_KERNEL); 1042 if (!hw->port_info) { 1043 status = -ENOMEM; 1044 goto err_unroll_cqinit; 1045 } 1046 1047 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1048 /* set the back pointer to HW */ 1049 hw->port_info->hw = hw; 1050 1051 /* Initialize port_info struct with switch configuration data */ 1052 status = ice_get_initial_sw_cfg(hw); 1053 if (status) 1054 goto err_unroll_alloc; 1055 1056 hw->evb_veb = true; 1057 1058 /* init xarray for identifying scheduling nodes uniquely */ 1059 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1060 1061 /* Query the allocated resources for Tx scheduler */ 1062 status = ice_sched_query_res_alloc(hw); 1063 if (status) { 1064 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1065 goto err_unroll_alloc; 1066 } 1067 ice_sched_get_psm_clk_freq(hw); 1068 1069 /* Initialize port_info struct with scheduler data */ 1070 status = ice_sched_init_port(hw->port_info); 1071 if (status) 1072 goto err_unroll_sched; 1073 1074 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1075 if (!pcaps) { 1076 status = -ENOMEM; 1077 goto err_unroll_sched; 1078 } 1079 1080 /* Initialize port_info struct with PHY capabilities */ 1081 status = ice_aq_get_phy_caps(hw->port_info, false, 1082 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1083 NULL); 1084 if (status) 1085 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1086 status); 1087 1088 /* Initialize port_info struct with link information */ 1089 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1090 if (status) 1091 goto err_unroll_sched; 1092 1093 /* need a valid SW entry point to build a Tx tree */ 1094 if (!hw->sw_entry_point_layer) { 1095 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1096 status = -EIO; 1097 goto err_unroll_sched; 1098 } 1099 INIT_LIST_HEAD(&hw->agg_list); 1100 /* Initialize max burst size */ 1101 if (!hw->max_burst_size) 1102 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1103 1104 status = ice_init_fltr_mgmt_struct(hw); 1105 if (status) 1106 goto err_unroll_sched; 1107 1108 /* Get MAC information */ 1109 /* A single port can report up to two (LAN and WoL) addresses */ 1110 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1111 GFP_KERNEL); 1112 if (!mac_buf) { 1113 status = -ENOMEM; 1114 goto err_unroll_fltr_mgmt_struct; 1115 } 1116 1117 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1118 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1119 1120 if (status) 1121 goto err_unroll_fltr_mgmt_struct; 1122 /* enable jumbo frame support at MAC level */ 1123 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1124 if (status) 1125 goto err_unroll_fltr_mgmt_struct; 1126 /* Obtain counter base index which would be used by flow director */ 1127 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1128 if (status) 1129 goto err_unroll_fltr_mgmt_struct; 1130 status = ice_init_hw_tbls(hw); 1131 if (status) 1132 goto err_unroll_fltr_mgmt_struct; 1133 mutex_init(&hw->tnl_lock); 1134 ice_init_chk_recipe_reuse_support(hw); 1135 1136 /* Some cards require longer initialization times 1137 * due to necessity of loading FW from an external source. 1138 * This can take even half a minute. 1139 */ 1140 if (ice_is_pf_c827(hw)) { 1141 status = ice_wait_for_fw(hw, 30000); 1142 if (status) { 1143 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1144 goto err_unroll_fltr_mgmt_struct; 1145 } 1146 } 1147 1148 hw->lane_num = ice_get_phy_lane_number(hw); 1149 1150 return 0; 1151 err_unroll_fltr_mgmt_struct: 1152 ice_cleanup_fltr_mgmt_struct(hw); 1153 err_unroll_sched: 1154 ice_sched_cleanup_all(hw); 1155 err_unroll_alloc: 1156 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1157 err_unroll_cqinit: 1158 ice_destroy_all_ctrlq(hw); 1159 return status; 1160 } 1161 1162 /** 1163 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1164 * @hw: pointer to the hardware structure 1165 * 1166 * This should be called only during nominal operation, not as a result of 1167 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1168 * applicable initializations if it fails for any reason. 1169 */ 1170 void ice_deinit_hw(struct ice_hw *hw) 1171 { 1172 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1173 ice_cleanup_fltr_mgmt_struct(hw); 1174 1175 ice_sched_cleanup_all(hw); 1176 ice_sched_clear_agg(hw); 1177 ice_free_seg(hw); 1178 ice_free_hw_tbls(hw); 1179 mutex_destroy(&hw->tnl_lock); 1180 1181 ice_fwlog_deinit(hw); 1182 ice_destroy_all_ctrlq(hw); 1183 1184 /* Clear VSI contexts if not already cleared */ 1185 ice_clear_all_vsi_ctx(hw); 1186 } 1187 1188 /** 1189 * ice_check_reset - Check to see if a global reset is complete 1190 * @hw: pointer to the hardware structure 1191 */ 1192 int ice_check_reset(struct ice_hw *hw) 1193 { 1194 u32 cnt, reg = 0, grst_timeout, uld_mask; 1195 1196 /* Poll for Device Active state in case a recent CORER, GLOBR, 1197 * or EMPR has occurred. The grst delay value is in 100ms units. 1198 * Add 1sec for outstanding AQ commands that can take a long time. 1199 */ 1200 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1201 rd32(hw, GLGEN_RSTCTL)) + 10; 1202 1203 for (cnt = 0; cnt < grst_timeout; cnt++) { 1204 mdelay(100); 1205 reg = rd32(hw, GLGEN_RSTAT); 1206 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1207 break; 1208 } 1209 1210 if (cnt == grst_timeout) { 1211 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1212 return -EIO; 1213 } 1214 1215 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1216 GLNVM_ULD_PCIER_DONE_1_M |\ 1217 GLNVM_ULD_CORER_DONE_M |\ 1218 GLNVM_ULD_GLOBR_DONE_M |\ 1219 GLNVM_ULD_POR_DONE_M |\ 1220 GLNVM_ULD_POR_DONE_1_M |\ 1221 GLNVM_ULD_PCIER_DONE_2_M) 1222 1223 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1224 GLNVM_ULD_PE_DONE_M : 0); 1225 1226 /* Device is Active; check Global Reset processes are done */ 1227 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1228 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1229 if (reg == uld_mask) { 1230 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1231 break; 1232 } 1233 mdelay(10); 1234 } 1235 1236 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1237 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1238 reg); 1239 return -EIO; 1240 } 1241 1242 return 0; 1243 } 1244 1245 /** 1246 * ice_pf_reset - Reset the PF 1247 * @hw: pointer to the hardware structure 1248 * 1249 * If a global reset has been triggered, this function checks 1250 * for its completion and then issues the PF reset 1251 */ 1252 static int ice_pf_reset(struct ice_hw *hw) 1253 { 1254 u32 cnt, reg; 1255 1256 /* If at function entry a global reset was already in progress, i.e. 1257 * state is not 'device active' or any of the reset done bits are not 1258 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1259 * global reset is done. 1260 */ 1261 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1262 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1263 /* poll on global reset currently in progress until done */ 1264 if (ice_check_reset(hw)) 1265 return -EIO; 1266 1267 return 0; 1268 } 1269 1270 /* Reset the PF */ 1271 reg = rd32(hw, PFGEN_CTRL); 1272 1273 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1274 1275 /* Wait for the PFR to complete. The wait time is the global config lock 1276 * timeout plus the PFR timeout which will account for a possible reset 1277 * that is occurring during a download package operation. 1278 */ 1279 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1280 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1281 reg = rd32(hw, PFGEN_CTRL); 1282 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1283 break; 1284 1285 mdelay(1); 1286 } 1287 1288 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1289 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1290 return -EIO; 1291 } 1292 1293 return 0; 1294 } 1295 1296 /** 1297 * ice_reset - Perform different types of reset 1298 * @hw: pointer to the hardware structure 1299 * @req: reset request 1300 * 1301 * This function triggers a reset as specified by the req parameter. 1302 * 1303 * Note: 1304 * If anything other than a PF reset is triggered, PXE mode is restored. 1305 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1306 * interface has been restored in the rebuild flow. 1307 */ 1308 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1309 { 1310 u32 val = 0; 1311 1312 switch (req) { 1313 case ICE_RESET_PFR: 1314 return ice_pf_reset(hw); 1315 case ICE_RESET_CORER: 1316 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1317 val = GLGEN_RTRIG_CORER_M; 1318 break; 1319 case ICE_RESET_GLOBR: 1320 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1321 val = GLGEN_RTRIG_GLOBR_M; 1322 break; 1323 default: 1324 return -EINVAL; 1325 } 1326 1327 val |= rd32(hw, GLGEN_RTRIG); 1328 wr32(hw, GLGEN_RTRIG, val); 1329 ice_flush(hw); 1330 1331 /* wait for the FW to be ready */ 1332 return ice_check_reset(hw); 1333 } 1334 1335 /** 1336 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1337 * @hw: pointer to the hardware structure 1338 * @rxq_ctx: pointer to the packed Rx queue context 1339 * @rxq_index: the index of the Rx queue 1340 */ 1341 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1342 const ice_rxq_ctx_buf_t *rxq_ctx, 1343 u32 rxq_index) 1344 { 1345 /* Copy each dword separately to HW */ 1346 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1347 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1348 1349 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1350 1351 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1352 } 1353 } 1354 1355 /** 1356 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1357 * @hw: pointer to the hardware structure 1358 * @rxq_ctx: pointer to the packed Rx queue context 1359 * @rxq_index: the index of the Rx queue 1360 */ 1361 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1362 ice_rxq_ctx_buf_t *rxq_ctx, 1363 u32 rxq_index) 1364 { 1365 u32 *ctx = (u32 *)rxq_ctx; 1366 1367 /* Copy each dword separately from HW */ 1368 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1369 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1370 1371 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1372 } 1373 } 1374 1375 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1376 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1377 1378 /* LAN Rx Queue Context */ 1379 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1380 /* Field Width LSB */ 1381 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1382 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1383 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1384 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1385 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1386 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1387 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1388 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1389 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1390 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1391 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1392 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1393 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1394 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1395 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1396 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1397 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1398 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1399 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1400 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1401 }; 1402 1403 /** 1404 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1405 * @ctx: the Rx queue context to pack 1406 * @buf: the HW buffer to pack into 1407 * 1408 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1409 * bit-packed HW layout. 1410 */ 1411 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1412 ice_rxq_ctx_buf_t *buf) 1413 { 1414 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1415 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1416 } 1417 1418 /** 1419 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1420 * @buf: the HW buffer to unpack from 1421 * @ctx: the Rx queue context to unpack 1422 * 1423 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1424 * structure. 1425 */ 1426 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1427 struct ice_rlan_ctx *ctx) 1428 { 1429 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1430 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1431 } 1432 1433 /** 1434 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1435 * @hw: pointer to the hardware structure 1436 * @rlan_ctx: pointer to the unpacked Rx queue context 1437 * @rxq_index: the index of the Rx queue 1438 * 1439 * Pack the sparse Rx Queue context into dense hardware format and write it 1440 * into the HW register space. 1441 * 1442 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1443 */ 1444 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1445 u32 rxq_index) 1446 { 1447 ice_rxq_ctx_buf_t buf = {}; 1448 1449 if (rxq_index > QRX_CTRL_MAX_INDEX) 1450 return -EINVAL; 1451 1452 ice_pack_rxq_ctx(rlan_ctx, &buf); 1453 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1454 1455 return 0; 1456 } 1457 1458 /** 1459 * ice_read_rxq_ctx - Read Rx queue context from HW 1460 * @hw: pointer to the hardware structure 1461 * @rlan_ctx: pointer to the Rx queue context 1462 * @rxq_index: the index of the Rx queue 1463 * 1464 * Read the Rx queue context from the hardware registers, and unpack it into 1465 * the sparse Rx queue context structure. 1466 * 1467 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1468 */ 1469 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1470 u32 rxq_index) 1471 { 1472 ice_rxq_ctx_buf_t buf = {}; 1473 1474 if (rxq_index > QRX_CTRL_MAX_INDEX) 1475 return -EINVAL; 1476 1477 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1478 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1479 1480 return 0; 1481 } 1482 1483 /* LAN Tx Queue Context */ 1484 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1485 /* Field Width LSB */ 1486 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1487 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1488 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1489 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1490 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1491 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1492 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1493 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1494 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1495 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1496 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1497 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1498 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1499 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1500 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1501 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1502 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1503 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1504 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1505 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1506 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1507 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1508 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1509 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1510 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1511 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1512 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1513 }; 1514 1515 /** 1516 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1517 * @ctx: the Tx queue context to pack 1518 * @buf: the Admin Queue HW buffer to pack into 1519 * 1520 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1521 * bit-packed Admin Queue layout. 1522 */ 1523 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1524 { 1525 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1526 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1527 } 1528 1529 /** 1530 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1531 * @ctx: the Tx queue context to pack 1532 * @buf: the HW buffer to pack into 1533 * 1534 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1535 * bit-packed HW layout, including the internal data portion. 1536 */ 1537 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1538 ice_txq_ctx_buf_full_t *buf) 1539 { 1540 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1541 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1542 } 1543 1544 /** 1545 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1546 * @buf: the HW buffer to unpack from 1547 * @ctx: the Tx queue context to unpack 1548 * 1549 * Unpack the Tx queue context from the HW buffer (including the full internal 1550 * state) into the CPU-friendly structure. 1551 */ 1552 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1553 struct ice_tlan_ctx *ctx) 1554 { 1555 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1556 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1557 } 1558 1559 /** 1560 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1561 * @hw: pointer to the hardware structure 1562 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1563 * @txq_index: the index of the Tx queue 1564 * 1565 * Copy Tx Queue context from HW register space to dense structure 1566 */ 1567 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1568 ice_txq_ctx_buf_full_t *txq_ctx, 1569 u32 txq_index) 1570 { 1571 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1572 u32 *ctx = (u32 *)txq_ctx; 1573 u32 txq_base, reg; 1574 1575 /* Get Tx queue base within card space */ 1576 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1577 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1578 1579 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1580 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1581 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1582 txq_base + txq_index) | 1583 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1584 1585 /* Prevent other PFs on the same adapter from accessing the Tx queue 1586 * context interface concurrently. 1587 */ 1588 spin_lock(&pf->adapter->txq_ctx_lock); 1589 1590 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1591 ice_flush(hw); 1592 1593 /* Copy each dword separately from HW */ 1594 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1595 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1596 1597 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1598 } 1599 1600 spin_unlock(&pf->adapter->txq_ctx_lock); 1601 } 1602 1603 /** 1604 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1605 * @hw: pointer to the hardware structure 1606 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1607 * @txq_index: the index of the Tx queue 1608 */ 1609 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1610 const ice_txq_ctx_buf_full_t *txq_ctx, 1611 u32 txq_index) 1612 { 1613 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1614 u32 txq_base, reg; 1615 1616 /* Get Tx queue base within card space */ 1617 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1618 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1619 1620 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1621 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1622 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1623 txq_base + txq_index) | 1624 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1625 1626 /* Prevent other PFs on the same adapter from accessing the Tx queue 1627 * context interface concurrently. 1628 */ 1629 spin_lock(&pf->adapter->txq_ctx_lock); 1630 1631 /* Copy each dword separately to HW */ 1632 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1633 u32 ctx = ((const u32 *)txq_ctx)[i]; 1634 1635 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1636 1637 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1638 } 1639 1640 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1641 ice_flush(hw); 1642 1643 spin_unlock(&pf->adapter->txq_ctx_lock); 1644 } 1645 1646 /** 1647 * ice_read_txq_ctx - Read Tx queue context from HW 1648 * @hw: pointer to the hardware structure 1649 * @tlan_ctx: pointer to the Tx queue context 1650 * @txq_index: the index of the Tx queue 1651 * 1652 * Read the Tx queue context from the HW registers, then unpack it into the 1653 * ice_tlan_ctx structure for use. 1654 * 1655 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1656 */ 1657 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1658 u32 txq_index) 1659 { 1660 ice_txq_ctx_buf_full_t buf = {}; 1661 1662 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1663 return -EINVAL; 1664 1665 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1666 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1667 1668 return 0; 1669 } 1670 1671 /** 1672 * ice_write_txq_ctx - Write Tx queue context to HW 1673 * @hw: pointer to the hardware structure 1674 * @tlan_ctx: pointer to the Tx queue context 1675 * @txq_index: the index of the Tx queue 1676 * 1677 * Pack the Tx queue context into the dense HW layout, then write it into the 1678 * HW registers. 1679 * 1680 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1681 */ 1682 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1683 u32 txq_index) 1684 { 1685 ice_txq_ctx_buf_full_t buf = {}; 1686 1687 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1688 return -EINVAL; 1689 1690 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1691 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1692 1693 return 0; 1694 } 1695 1696 /* Sideband Queue command wrappers */ 1697 1698 /** 1699 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1700 * @hw: pointer to the HW struct 1701 * @desc: descriptor describing the command 1702 * @buf: buffer to use for indirect commands (NULL for direct commands) 1703 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1704 * @cd: pointer to command details structure 1705 */ 1706 static int 1707 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1708 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1709 { 1710 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1711 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1712 } 1713 1714 /** 1715 * ice_sbq_rw_reg - Fill Sideband Queue command 1716 * @hw: pointer to the HW struct 1717 * @in: message info to be filled in descriptor 1718 * @flags: control queue descriptor flags 1719 */ 1720 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1721 { 1722 struct ice_sbq_cmd_desc desc = {0}; 1723 struct ice_sbq_msg_req msg = {0}; 1724 u16 msg_len; 1725 int status; 1726 1727 msg_len = sizeof(msg); 1728 1729 msg.dest_dev = in->dest_dev; 1730 msg.opcode = in->opcode; 1731 msg.flags = ICE_SBQ_MSG_FLAGS; 1732 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1733 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1734 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1735 1736 if (in->opcode) 1737 msg.data = cpu_to_le32(in->data); 1738 else 1739 /* data read comes back in completion, so shorten the struct by 1740 * sizeof(msg.data) 1741 */ 1742 msg_len -= sizeof(msg.data); 1743 1744 desc.flags = cpu_to_le16(flags); 1745 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1746 desc.param0.cmd_len = cpu_to_le16(msg_len); 1747 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1748 if (!status && !in->opcode) 1749 in->data = le32_to_cpu 1750 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1751 return status; 1752 } 1753 1754 /* FW Admin Queue command wrappers */ 1755 1756 /* Software lock/mutex that is meant to be held while the Global Config Lock 1757 * in firmware is acquired by the software to prevent most (but not all) types 1758 * of AQ commands from being sent to FW 1759 */ 1760 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1761 1762 /** 1763 * ice_should_retry_sq_send_cmd 1764 * @opcode: AQ opcode 1765 * 1766 * Decide if we should retry the send command routine for the ATQ, depending 1767 * on the opcode. 1768 */ 1769 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1770 { 1771 switch (opcode) { 1772 case ice_aqc_opc_get_link_topo: 1773 case ice_aqc_opc_lldp_stop: 1774 case ice_aqc_opc_lldp_start: 1775 case ice_aqc_opc_lldp_filter_ctrl: 1776 return true; 1777 } 1778 1779 return false; 1780 } 1781 1782 /** 1783 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1784 * @hw: pointer to the HW struct 1785 * @cq: pointer to the specific Control queue 1786 * @desc: prefilled descriptor describing the command 1787 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1788 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1789 * @cd: pointer to command details structure 1790 * 1791 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1792 * Queue if the EBUSY AQ error is returned. 1793 */ 1794 static int 1795 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1796 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1797 struct ice_sq_cd *cd) 1798 { 1799 struct libie_aq_desc desc_cpy; 1800 bool is_cmd_for_retry; 1801 u8 idx = 0; 1802 u16 opcode; 1803 int status; 1804 1805 opcode = le16_to_cpu(desc->opcode); 1806 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1807 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1808 1809 if (is_cmd_for_retry) { 1810 /* All retryable cmds are direct, without buf. */ 1811 WARN_ON(buf); 1812 1813 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1814 } 1815 1816 do { 1817 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1818 1819 if (!is_cmd_for_retry || !status || 1820 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1821 break; 1822 1823 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1824 1825 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1826 1827 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1828 1829 return status; 1830 } 1831 1832 /** 1833 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1834 * @hw: pointer to the HW struct 1835 * @desc: descriptor describing the command 1836 * @buf: buffer to use for indirect commands (NULL for direct commands) 1837 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1838 * @cd: pointer to command details structure 1839 * 1840 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1841 */ 1842 int 1843 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1844 u16 buf_size, struct ice_sq_cd *cd) 1845 { 1846 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1847 bool lock_acquired = false; 1848 int status; 1849 1850 /* When a package download is in process (i.e. when the firmware's 1851 * Global Configuration Lock resource is held), only the Download 1852 * Package, Get Version, Get Package Info List, Upload Section, 1853 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1854 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1855 * Recipes to Profile Association, and Release Resource (with resource 1856 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1857 * must block until the package download completes and the Global Config 1858 * Lock is released. See also ice_acquire_global_cfg_lock(). 1859 */ 1860 switch (le16_to_cpu(desc->opcode)) { 1861 case ice_aqc_opc_download_pkg: 1862 case ice_aqc_opc_get_pkg_info_list: 1863 case ice_aqc_opc_get_ver: 1864 case ice_aqc_opc_upload_section: 1865 case ice_aqc_opc_update_pkg: 1866 case ice_aqc_opc_set_port_params: 1867 case ice_aqc_opc_get_vlan_mode_parameters: 1868 case ice_aqc_opc_set_vlan_mode_parameters: 1869 case ice_aqc_opc_set_tx_topo: 1870 case ice_aqc_opc_get_tx_topo: 1871 case ice_aqc_opc_add_recipe: 1872 case ice_aqc_opc_recipe_to_profile: 1873 case ice_aqc_opc_get_recipe: 1874 case ice_aqc_opc_get_recipe_to_profile: 1875 break; 1876 case ice_aqc_opc_release_res: 1877 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1878 break; 1879 fallthrough; 1880 default: 1881 mutex_lock(&ice_global_cfg_lock_sw); 1882 lock_acquired = true; 1883 break; 1884 } 1885 1886 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1887 if (lock_acquired) 1888 mutex_unlock(&ice_global_cfg_lock_sw); 1889 1890 return status; 1891 } 1892 1893 /** 1894 * ice_aq_get_fw_ver 1895 * @hw: pointer to the HW struct 1896 * @cd: pointer to command details structure or NULL 1897 * 1898 * Get the firmware version (0x0001) from the admin queue commands 1899 */ 1900 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1901 { 1902 struct libie_aqc_get_ver *resp; 1903 struct libie_aq_desc desc; 1904 int status; 1905 1906 resp = &desc.params.get_ver; 1907 1908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1909 1910 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1911 1912 if (!status) { 1913 hw->fw_branch = resp->fw_branch; 1914 hw->fw_maj_ver = resp->fw_major; 1915 hw->fw_min_ver = resp->fw_minor; 1916 hw->fw_patch = resp->fw_patch; 1917 hw->fw_build = le32_to_cpu(resp->fw_build); 1918 hw->api_branch = resp->api_branch; 1919 hw->api_maj_ver = resp->api_major; 1920 hw->api_min_ver = resp->api_minor; 1921 hw->api_patch = resp->api_patch; 1922 } 1923 1924 return status; 1925 } 1926 1927 /** 1928 * ice_aq_send_driver_ver 1929 * @hw: pointer to the HW struct 1930 * @dv: driver's major, minor version 1931 * @cd: pointer to command details structure or NULL 1932 * 1933 * Send the driver version (0x0002) to the firmware 1934 */ 1935 int 1936 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1937 struct ice_sq_cd *cd) 1938 { 1939 struct libie_aqc_driver_ver *cmd; 1940 struct libie_aq_desc desc; 1941 u16 len; 1942 1943 cmd = &desc.params.driver_ver; 1944 1945 if (!dv) 1946 return -EINVAL; 1947 1948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1949 1950 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1951 cmd->major_ver = dv->major_ver; 1952 cmd->minor_ver = dv->minor_ver; 1953 cmd->build_ver = dv->build_ver; 1954 cmd->subbuild_ver = dv->subbuild_ver; 1955 1956 len = 0; 1957 while (len < sizeof(dv->driver_string) && 1958 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1959 len++; 1960 1961 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1962 } 1963 1964 /** 1965 * ice_aq_q_shutdown 1966 * @hw: pointer to the HW struct 1967 * @unloading: is the driver unloading itself 1968 * 1969 * Tell the Firmware that we're shutting down the AdminQ and whether 1970 * or not the driver is unloading as well (0x0003). 1971 */ 1972 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1973 { 1974 struct ice_aqc_q_shutdown *cmd; 1975 struct libie_aq_desc desc; 1976 1977 cmd = libie_aq_raw(&desc); 1978 1979 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1980 1981 if (unloading) 1982 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1983 1984 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1985 } 1986 1987 /** 1988 * ice_aq_req_res 1989 * @hw: pointer to the HW struct 1990 * @res: resource ID 1991 * @access: access type 1992 * @sdp_number: resource number 1993 * @timeout: the maximum time in ms that the driver may hold the resource 1994 * @cd: pointer to command details structure or NULL 1995 * 1996 * Requests common resource using the admin queue commands (0x0008). 1997 * When attempting to acquire the Global Config Lock, the driver can 1998 * learn of three states: 1999 * 1) 0 - acquired lock, and can perform download package 2000 * 2) -EIO - did not get lock, driver should fail to load 2001 * 3) -EALREADY - did not get lock, but another driver has 2002 * successfully downloaded the package; the driver does 2003 * not have to download the package and can continue 2004 * loading 2005 * 2006 * Note that if the caller is in an acquire lock, perform action, release lock 2007 * phase of operation, it is possible that the FW may detect a timeout and issue 2008 * a CORER. In this case, the driver will receive a CORER interrupt and will 2009 * have to determine its cause. The calling thread that is handling this flow 2010 * will likely get an error propagated back to it indicating the Download 2011 * Package, Update Package or the Release Resource AQ commands timed out. 2012 */ 2013 static int 2014 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2015 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2016 struct ice_sq_cd *cd) 2017 { 2018 struct libie_aqc_req_res *cmd_resp; 2019 struct libie_aq_desc desc; 2020 int status; 2021 2022 cmd_resp = &desc.params.res_owner; 2023 2024 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2025 2026 cmd_resp->res_id = cpu_to_le16(res); 2027 cmd_resp->access_type = cpu_to_le16(access); 2028 cmd_resp->res_number = cpu_to_le32(sdp_number); 2029 cmd_resp->timeout = cpu_to_le32(*timeout); 2030 *timeout = 0; 2031 2032 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2033 2034 /* The completion specifies the maximum time in ms that the driver 2035 * may hold the resource in the Timeout field. 2036 */ 2037 2038 /* Global config lock response utilizes an additional status field. 2039 * 2040 * If the Global config lock resource is held by some other driver, the 2041 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2042 * and the timeout field indicates the maximum time the current owner 2043 * of the resource has to free it. 2044 */ 2045 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2046 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2047 *timeout = le32_to_cpu(cmd_resp->timeout); 2048 return 0; 2049 } else if (le16_to_cpu(cmd_resp->status) == 2050 LIBIE_AQ_RES_GLBL_IN_PROG) { 2051 *timeout = le32_to_cpu(cmd_resp->timeout); 2052 return -EIO; 2053 } else if (le16_to_cpu(cmd_resp->status) == 2054 LIBIE_AQ_RES_GLBL_DONE) { 2055 return -EALREADY; 2056 } 2057 2058 /* invalid FW response, force a timeout immediately */ 2059 *timeout = 0; 2060 return -EIO; 2061 } 2062 2063 /* If the resource is held by some other driver, the command completes 2064 * with a busy return value and the timeout field indicates the maximum 2065 * time the current owner of the resource has to free it. 2066 */ 2067 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2068 *timeout = le32_to_cpu(cmd_resp->timeout); 2069 2070 return status; 2071 } 2072 2073 /** 2074 * ice_aq_release_res 2075 * @hw: pointer to the HW struct 2076 * @res: resource ID 2077 * @sdp_number: resource number 2078 * @cd: pointer to command details structure or NULL 2079 * 2080 * release common resource using the admin queue commands (0x0009) 2081 */ 2082 static int 2083 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2084 struct ice_sq_cd *cd) 2085 { 2086 struct libie_aqc_req_res *cmd; 2087 struct libie_aq_desc desc; 2088 2089 cmd = &desc.params.res_owner; 2090 2091 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2092 2093 cmd->res_id = cpu_to_le16(res); 2094 cmd->res_number = cpu_to_le32(sdp_number); 2095 2096 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2097 } 2098 2099 /** 2100 * ice_acquire_res 2101 * @hw: pointer to the HW structure 2102 * @res: resource ID 2103 * @access: access type (read or write) 2104 * @timeout: timeout in milliseconds 2105 * 2106 * This function will attempt to acquire the ownership of a resource. 2107 */ 2108 int 2109 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2110 enum ice_aq_res_access_type access, u32 timeout) 2111 { 2112 #define ICE_RES_POLLING_DELAY_MS 10 2113 u32 delay = ICE_RES_POLLING_DELAY_MS; 2114 u32 time_left = timeout; 2115 int status; 2116 2117 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2118 2119 /* A return code of -EALREADY means that another driver has 2120 * previously acquired the resource and performed any necessary updates; 2121 * in this case the caller does not obtain the resource and has no 2122 * further work to do. 2123 */ 2124 if (status == -EALREADY) 2125 goto ice_acquire_res_exit; 2126 2127 if (status) 2128 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2129 2130 /* If necessary, poll until the current lock owner timeouts */ 2131 timeout = time_left; 2132 while (status && timeout && time_left) { 2133 mdelay(delay); 2134 timeout = (timeout > delay) ? timeout - delay : 0; 2135 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2136 2137 if (status == -EALREADY) 2138 /* lock free, but no work to do */ 2139 break; 2140 2141 if (!status) 2142 /* lock acquired */ 2143 break; 2144 } 2145 if (status && status != -EALREADY) 2146 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2147 2148 ice_acquire_res_exit: 2149 if (status == -EALREADY) { 2150 if (access == ICE_RES_WRITE) 2151 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2152 else 2153 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2154 } 2155 return status; 2156 } 2157 2158 /** 2159 * ice_release_res 2160 * @hw: pointer to the HW structure 2161 * @res: resource ID 2162 * 2163 * This function will release a resource using the proper Admin Command. 2164 */ 2165 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2166 { 2167 unsigned long timeout; 2168 int status; 2169 2170 /* there are some rare cases when trying to release the resource 2171 * results in an admin queue timeout, so handle them correctly 2172 */ 2173 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2174 do { 2175 status = ice_aq_release_res(hw, res, 0, NULL); 2176 if (status != -EIO) 2177 break; 2178 usleep_range(1000, 2000); 2179 } while (time_before(jiffies, timeout)); 2180 } 2181 2182 /** 2183 * ice_aq_alloc_free_res - command to allocate/free resources 2184 * @hw: pointer to the HW struct 2185 * @buf: Indirect buffer to hold data parameters and response 2186 * @buf_size: size of buffer for indirect commands 2187 * @opc: pass in the command opcode 2188 * 2189 * Helper function to allocate/free resources using the admin queue commands 2190 */ 2191 int ice_aq_alloc_free_res(struct ice_hw *hw, 2192 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2193 enum ice_adminq_opc opc) 2194 { 2195 struct ice_aqc_alloc_free_res_cmd *cmd; 2196 struct libie_aq_desc desc; 2197 2198 cmd = libie_aq_raw(&desc); 2199 2200 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2201 return -EINVAL; 2202 2203 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2204 2205 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2206 2207 cmd->num_entries = cpu_to_le16(1); 2208 2209 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2210 } 2211 2212 /** 2213 * ice_alloc_hw_res - allocate resource 2214 * @hw: pointer to the HW struct 2215 * @type: type of resource 2216 * @num: number of resources to allocate 2217 * @btm: allocate from bottom 2218 * @res: pointer to array that will receive the resources 2219 */ 2220 int 2221 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2222 { 2223 struct ice_aqc_alloc_free_res_elem *buf; 2224 u16 buf_len; 2225 int status; 2226 2227 buf_len = struct_size(buf, elem, num); 2228 buf = kzalloc(buf_len, GFP_KERNEL); 2229 if (!buf) 2230 return -ENOMEM; 2231 2232 /* Prepare buffer to allocate resource. */ 2233 buf->num_elems = cpu_to_le16(num); 2234 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2235 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2236 if (btm) 2237 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2238 2239 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2240 if (status) 2241 goto ice_alloc_res_exit; 2242 2243 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2244 2245 ice_alloc_res_exit: 2246 kfree(buf); 2247 return status; 2248 } 2249 2250 /** 2251 * ice_free_hw_res - free allocated HW resource 2252 * @hw: pointer to the HW struct 2253 * @type: type of resource to free 2254 * @num: number of resources 2255 * @res: pointer to array that contains the resources to free 2256 */ 2257 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2258 { 2259 struct ice_aqc_alloc_free_res_elem *buf; 2260 u16 buf_len; 2261 int status; 2262 2263 buf_len = struct_size(buf, elem, num); 2264 buf = kzalloc(buf_len, GFP_KERNEL); 2265 if (!buf) 2266 return -ENOMEM; 2267 2268 /* Prepare buffer to free resource. */ 2269 buf->num_elems = cpu_to_le16(num); 2270 buf->res_type = cpu_to_le16(type); 2271 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2272 2273 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2274 if (status) 2275 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2276 2277 kfree(buf); 2278 return status; 2279 } 2280 2281 /** 2282 * ice_get_num_per_func - determine number of resources per PF 2283 * @hw: pointer to the HW structure 2284 * @max: value to be evenly split between each PF 2285 * 2286 * Determine the number of valid functions by going through the bitmap returned 2287 * from parsing capabilities and use this to calculate the number of resources 2288 * per PF based on the max value passed in. 2289 */ 2290 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2291 { 2292 u8 funcs; 2293 2294 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2295 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2296 ICE_CAPS_VALID_FUNCS_M); 2297 2298 if (!funcs) 2299 return 0; 2300 2301 return max / funcs; 2302 } 2303 2304 /** 2305 * ice_parse_common_caps - parse common device/function capabilities 2306 * @hw: pointer to the HW struct 2307 * @caps: pointer to common capabilities structure 2308 * @elem: the capability element to parse 2309 * @prefix: message prefix for tracing capabilities 2310 * 2311 * Given a capability element, extract relevant details into the common 2312 * capability structure. 2313 * 2314 * Returns: true if the capability matches one of the common capability ids, 2315 * false otherwise. 2316 */ 2317 static bool 2318 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2319 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2320 { 2321 u32 logical_id = le32_to_cpu(elem->logical_id); 2322 u32 phys_id = le32_to_cpu(elem->phys_id); 2323 u32 number = le32_to_cpu(elem->number); 2324 u16 cap = le16_to_cpu(elem->cap); 2325 bool found = true; 2326 2327 switch (cap) { 2328 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2329 caps->valid_functions = number; 2330 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2331 caps->valid_functions); 2332 break; 2333 case LIBIE_AQC_CAPS_SRIOV: 2334 caps->sr_iov_1_1 = (number == 1); 2335 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2336 caps->sr_iov_1_1); 2337 break; 2338 case LIBIE_AQC_CAPS_DCB: 2339 caps->dcb = (number == 1); 2340 caps->active_tc_bitmap = logical_id; 2341 caps->maxtc = phys_id; 2342 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2343 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2344 caps->active_tc_bitmap); 2345 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2346 break; 2347 case LIBIE_AQC_CAPS_RSS: 2348 caps->rss_table_size = number; 2349 caps->rss_table_entry_width = logical_id; 2350 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2351 caps->rss_table_size); 2352 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2353 caps->rss_table_entry_width); 2354 break; 2355 case LIBIE_AQC_CAPS_RXQS: 2356 caps->num_rxq = number; 2357 caps->rxq_first_id = phys_id; 2358 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2359 caps->num_rxq); 2360 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2361 caps->rxq_first_id); 2362 break; 2363 case LIBIE_AQC_CAPS_TXQS: 2364 caps->num_txq = number; 2365 caps->txq_first_id = phys_id; 2366 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2367 caps->num_txq); 2368 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2369 caps->txq_first_id); 2370 break; 2371 case LIBIE_AQC_CAPS_MSIX: 2372 caps->num_msix_vectors = number; 2373 caps->msix_vector_first_id = phys_id; 2374 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2375 caps->num_msix_vectors); 2376 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2377 caps->msix_vector_first_id); 2378 break; 2379 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2380 caps->nvm_update_pending_nvm = true; 2381 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2382 break; 2383 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2384 caps->nvm_update_pending_orom = true; 2385 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2386 break; 2387 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2388 caps->nvm_update_pending_netlist = true; 2389 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2390 break; 2391 case LIBIE_AQC_CAPS_NVM_MGMT: 2392 caps->nvm_unified_update = 2393 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2394 true : false; 2395 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2396 caps->nvm_unified_update); 2397 break; 2398 case LIBIE_AQC_CAPS_RDMA: 2399 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2400 caps->rdma = (number == 1); 2401 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2402 break; 2403 case LIBIE_AQC_CAPS_MAX_MTU: 2404 caps->max_mtu = number; 2405 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2406 prefix, caps->max_mtu); 2407 break; 2408 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2409 caps->pcie_reset_avoidance = (number > 0); 2410 ice_debug(hw, ICE_DBG_INIT, 2411 "%s: pcie_reset_avoidance = %d\n", prefix, 2412 caps->pcie_reset_avoidance); 2413 break; 2414 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2415 caps->reset_restrict_support = (number == 1); 2416 ice_debug(hw, ICE_DBG_INIT, 2417 "%s: reset_restrict_support = %d\n", prefix, 2418 caps->reset_restrict_support); 2419 break; 2420 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2421 caps->roce_lag = !!(number & LIBIE_AQC_BIT_ROCEV2_LAG); 2422 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2423 prefix, caps->roce_lag); 2424 caps->sriov_lag = !!(number & LIBIE_AQC_BIT_SRIOV_LAG); 2425 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2426 prefix, caps->sriov_lag); 2427 break; 2428 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2429 caps->tx_sched_topo_comp_mode_en = (number == 1); 2430 break; 2431 default: 2432 /* Not one of the recognized common capabilities */ 2433 found = false; 2434 } 2435 2436 return found; 2437 } 2438 2439 /** 2440 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2441 * @hw: pointer to the HW structure 2442 * @caps: pointer to capabilities structure to fix 2443 * 2444 * Re-calculate the capabilities that are dependent on the number of physical 2445 * ports; i.e. some features are not supported or function differently on 2446 * devices with more than 4 ports. 2447 */ 2448 static void 2449 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2450 { 2451 /* This assumes device capabilities are always scanned before function 2452 * capabilities during the initialization flow. 2453 */ 2454 if (hw->dev_caps.num_funcs > 4) { 2455 /* Max 4 TCs per port */ 2456 caps->maxtc = 4; 2457 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2458 caps->maxtc); 2459 if (caps->rdma) { 2460 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2461 caps->rdma = 0; 2462 } 2463 2464 /* print message only when processing device capabilities 2465 * during initialization. 2466 */ 2467 if (caps == &hw->dev_caps.common_cap) 2468 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2469 } 2470 } 2471 2472 /** 2473 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2474 * @hw: pointer to the HW struct 2475 * @func_p: pointer to function capabilities structure 2476 * @cap: pointer to the capability element to parse 2477 * 2478 * Extract function capabilities for ICE_AQC_CAPS_VF. 2479 */ 2480 static void 2481 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2482 struct libie_aqc_list_caps_elem *cap) 2483 { 2484 u32 logical_id = le32_to_cpu(cap->logical_id); 2485 u32 number = le32_to_cpu(cap->number); 2486 2487 func_p->num_allocd_vfs = number; 2488 func_p->vf_base_id = logical_id; 2489 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2490 func_p->num_allocd_vfs); 2491 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2492 func_p->vf_base_id); 2493 } 2494 2495 /** 2496 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2497 * @hw: pointer to the HW struct 2498 * @func_p: pointer to function capabilities structure 2499 * @cap: pointer to the capability element to parse 2500 * 2501 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2502 */ 2503 static void 2504 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2505 struct libie_aqc_list_caps_elem *cap) 2506 { 2507 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2508 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2509 le32_to_cpu(cap->number)); 2510 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2511 func_p->guar_num_vsi); 2512 } 2513 2514 /** 2515 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2516 * @hw: pointer to the HW struct 2517 * @func_p: pointer to function capabilities structure 2518 * @cap: pointer to the capability element to parse 2519 * 2520 * Extract function capabilities for ICE_AQC_CAPS_1588. 2521 */ 2522 static void 2523 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2524 struct libie_aqc_list_caps_elem *cap) 2525 { 2526 struct ice_ts_func_info *info = &func_p->ts_func_info; 2527 u32 number = le32_to_cpu(cap->number); 2528 2529 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2530 func_p->common_cap.ieee_1588 = info->ena; 2531 2532 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2533 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2534 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2535 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2536 2537 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2538 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2539 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2540 } else { 2541 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2542 info->clk_src = ICE_CLK_SRC_TIME_REF; 2543 } 2544 2545 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2546 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2547 } else { 2548 /* Unknown clock frequency, so assume a (probably incorrect) 2549 * default to avoid out-of-bounds look ups of frequency 2550 * related information. 2551 */ 2552 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2553 info->clk_freq); 2554 info->time_ref = ICE_TSPLL_FREQ_25_000; 2555 } 2556 2557 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2558 func_p->common_cap.ieee_1588); 2559 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2560 info->src_tmr_owned); 2561 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2562 info->tmr_ena); 2563 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2564 info->tmr_index_owned); 2565 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2566 info->tmr_index_assoc); 2567 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2568 info->clk_freq); 2569 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2570 info->clk_src); 2571 } 2572 2573 /** 2574 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2575 * @hw: pointer to the HW struct 2576 * @func_p: pointer to function capabilities structure 2577 * 2578 * Extract function capabilities for ICE_AQC_CAPS_FD. 2579 */ 2580 static void 2581 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2582 { 2583 u32 reg_val, gsize, bsize; 2584 2585 reg_val = rd32(hw, GLQF_FD_SIZE); 2586 switch (hw->mac_type) { 2587 case ICE_MAC_E830: 2588 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2589 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2590 break; 2591 case ICE_MAC_E810: 2592 default: 2593 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2594 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2595 } 2596 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2597 func_p->fd_fltr_best_effort = bsize; 2598 2599 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2600 func_p->fd_fltr_guar); 2601 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2602 func_p->fd_fltr_best_effort); 2603 } 2604 2605 /** 2606 * ice_parse_func_caps - Parse function capabilities 2607 * @hw: pointer to the HW struct 2608 * @func_p: pointer to function capabilities structure 2609 * @buf: buffer containing the function capability records 2610 * @cap_count: the number of capabilities 2611 * 2612 * Helper function to parse function (0x000A) capabilities list. For 2613 * capabilities shared between device and function, this relies on 2614 * ice_parse_common_caps. 2615 * 2616 * Loop through the list of provided capabilities and extract the relevant 2617 * data into the function capabilities structured. 2618 */ 2619 static void 2620 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2621 void *buf, u32 cap_count) 2622 { 2623 struct libie_aqc_list_caps_elem *cap_resp; 2624 u32 i; 2625 2626 cap_resp = buf; 2627 2628 memset(func_p, 0, sizeof(*func_p)); 2629 2630 for (i = 0; i < cap_count; i++) { 2631 u16 cap = le16_to_cpu(cap_resp[i].cap); 2632 bool found; 2633 2634 found = ice_parse_common_caps(hw, &func_p->common_cap, 2635 &cap_resp[i], "func caps"); 2636 2637 switch (cap) { 2638 case LIBIE_AQC_CAPS_VF: 2639 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2640 break; 2641 case LIBIE_AQC_CAPS_VSI: 2642 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2643 break; 2644 case LIBIE_AQC_CAPS_1588: 2645 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2646 break; 2647 case LIBIE_AQC_CAPS_FD: 2648 ice_parse_fdir_func_caps(hw, func_p); 2649 break; 2650 default: 2651 /* Don't list common capabilities as unknown */ 2652 if (!found) 2653 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2654 i, cap); 2655 break; 2656 } 2657 } 2658 2659 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2660 } 2661 2662 /** 2663 * ice_func_id_to_logical_id - map from function id to logical pf id 2664 * @active_function_bitmap: active function bitmap 2665 * @pf_id: function number of device 2666 * 2667 * Return: logical PF ID. 2668 */ 2669 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2670 { 2671 u8 logical_id = 0; 2672 u8 i; 2673 2674 for (i = 0; i < pf_id; i++) 2675 if (active_function_bitmap & BIT(i)) 2676 logical_id++; 2677 2678 return logical_id; 2679 } 2680 2681 /** 2682 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2683 * @hw: pointer to the HW struct 2684 * @dev_p: pointer to device capabilities structure 2685 * @cap: capability element to parse 2686 * 2687 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2688 */ 2689 static void 2690 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2691 struct libie_aqc_list_caps_elem *cap) 2692 { 2693 u32 number = le32_to_cpu(cap->number); 2694 2695 dev_p->num_funcs = hweight32(number); 2696 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2697 dev_p->num_funcs); 2698 2699 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2700 } 2701 2702 /** 2703 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2704 * @hw: pointer to the HW struct 2705 * @dev_p: pointer to device capabilities structure 2706 * @cap: capability element to parse 2707 * 2708 * Parse ICE_AQC_CAPS_VF for device capabilities. 2709 */ 2710 static void 2711 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2712 struct libie_aqc_list_caps_elem *cap) 2713 { 2714 u32 number = le32_to_cpu(cap->number); 2715 2716 dev_p->num_vfs_exposed = number; 2717 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2718 dev_p->num_vfs_exposed); 2719 } 2720 2721 /** 2722 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2723 * @hw: pointer to the HW struct 2724 * @dev_p: pointer to device capabilities structure 2725 * @cap: capability element to parse 2726 * 2727 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2728 */ 2729 static void 2730 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2731 struct libie_aqc_list_caps_elem *cap) 2732 { 2733 u32 number = le32_to_cpu(cap->number); 2734 2735 dev_p->num_vsi_allocd_to_host = number; 2736 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2737 dev_p->num_vsi_allocd_to_host); 2738 } 2739 2740 /** 2741 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2742 * @hw: pointer to the HW struct 2743 * @dev_p: pointer to device capabilities structure 2744 * @cap: capability element to parse 2745 * 2746 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2747 */ 2748 static void 2749 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2750 struct libie_aqc_list_caps_elem *cap) 2751 { 2752 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2753 u32 logical_id = le32_to_cpu(cap->logical_id); 2754 u32 phys_id = le32_to_cpu(cap->phys_id); 2755 u32 number = le32_to_cpu(cap->number); 2756 2757 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2758 dev_p->common_cap.ieee_1588 = info->ena; 2759 2760 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2761 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2762 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2763 2764 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2765 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2766 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2767 2768 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2769 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2770 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2771 2772 info->ena_ports = logical_id; 2773 info->tmr_own_map = phys_id; 2774 2775 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2776 dev_p->common_cap.ieee_1588); 2777 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2778 info->tmr0_owner); 2779 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2780 info->tmr0_owned); 2781 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2782 info->tmr0_ena); 2783 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2784 info->tmr1_owner); 2785 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2786 info->tmr1_owned); 2787 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2788 info->tmr1_ena); 2789 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2790 info->ts_ll_read); 2791 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2792 info->ts_ll_int_read); 2793 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2794 info->ll_phy_tmr_update); 2795 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2796 info->ena_ports); 2797 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2798 info->tmr_own_map); 2799 } 2800 2801 /** 2802 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2803 * @hw: pointer to the HW struct 2804 * @dev_p: pointer to device capabilities structure 2805 * @cap: capability element to parse 2806 * 2807 * Parse ICE_AQC_CAPS_FD for device capabilities. 2808 */ 2809 static void 2810 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2811 struct libie_aqc_list_caps_elem *cap) 2812 { 2813 u32 number = le32_to_cpu(cap->number); 2814 2815 dev_p->num_flow_director_fltr = number; 2816 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2817 dev_p->num_flow_director_fltr); 2818 } 2819 2820 /** 2821 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2822 * @hw: pointer to the HW struct 2823 * @dev_p: pointer to device capabilities structure 2824 * @cap: capability element to parse 2825 * 2826 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2827 * enabled sensors. 2828 */ 2829 static void 2830 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2831 struct libie_aqc_list_caps_elem *cap) 2832 { 2833 dev_p->supported_sensors = le32_to_cpu(cap->number); 2834 2835 ice_debug(hw, ICE_DBG_INIT, 2836 "dev caps: supported sensors (bitmap) = 0x%x\n", 2837 dev_p->supported_sensors); 2838 } 2839 2840 /** 2841 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2842 * @hw: pointer to the HW struct 2843 * @dev_p: pointer to device capabilities structure 2844 * @cap: capability element to parse 2845 * 2846 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2847 */ 2848 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2849 struct ice_hw_dev_caps *dev_p, 2850 struct libie_aqc_list_caps_elem *cap) 2851 { 2852 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2853 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2854 2855 dev_info(ice_hw_to_dev(hw), 2856 "PF is configured in %s mode with IP instance ID %d\n", 2857 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2858 "primary" : "secondary", dev_p->nac_topo.id); 2859 2860 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2861 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2862 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2863 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2864 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2865 dev_p->nac_topo.id); 2866 } 2867 2868 /** 2869 * ice_parse_dev_caps - Parse device capabilities 2870 * @hw: pointer to the HW struct 2871 * @dev_p: pointer to device capabilities structure 2872 * @buf: buffer containing the device capability records 2873 * @cap_count: the number of capabilities 2874 * 2875 * Helper device to parse device (0x000B) capabilities list. For 2876 * capabilities shared between device and function, this relies on 2877 * ice_parse_common_caps. 2878 * 2879 * Loop through the list of provided capabilities and extract the relevant 2880 * data into the device capabilities structured. 2881 */ 2882 static void 2883 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2884 void *buf, u32 cap_count) 2885 { 2886 struct libie_aqc_list_caps_elem *cap_resp; 2887 u32 i; 2888 2889 cap_resp = buf; 2890 2891 memset(dev_p, 0, sizeof(*dev_p)); 2892 2893 for (i = 0; i < cap_count; i++) { 2894 u16 cap = le16_to_cpu(cap_resp[i].cap); 2895 bool found; 2896 2897 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2898 &cap_resp[i], "dev caps"); 2899 2900 switch (cap) { 2901 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2902 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2903 break; 2904 case LIBIE_AQC_CAPS_VF: 2905 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2906 break; 2907 case LIBIE_AQC_CAPS_VSI: 2908 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2909 break; 2910 case LIBIE_AQC_CAPS_1588: 2911 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2912 break; 2913 case LIBIE_AQC_CAPS_FD: 2914 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2915 break; 2916 case LIBIE_AQC_CAPS_SENSOR_READING: 2917 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2918 break; 2919 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2920 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2921 break; 2922 default: 2923 /* Don't list common capabilities as unknown */ 2924 if (!found) 2925 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2926 i, cap); 2927 break; 2928 } 2929 } 2930 2931 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2932 } 2933 2934 /** 2935 * ice_is_phy_rclk_in_netlist 2936 * @hw: pointer to the hw struct 2937 * 2938 * Check if the PHY Recovered Clock device is present in the netlist 2939 */ 2940 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2941 { 2942 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2943 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2944 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2945 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2946 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2947 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2948 return false; 2949 2950 return true; 2951 } 2952 2953 /** 2954 * ice_is_clock_mux_in_netlist 2955 * @hw: pointer to the hw struct 2956 * 2957 * Check if the Clock Multiplexer device is present in the netlist 2958 */ 2959 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 2960 { 2961 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 2962 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2963 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 2964 NULL)) 2965 return false; 2966 2967 return true; 2968 } 2969 2970 /** 2971 * ice_is_cgu_in_netlist - check for CGU presence 2972 * @hw: pointer to the hw struct 2973 * 2974 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 2975 * Save the CGU part number in the hw structure for later use. 2976 * Return: 2977 * * true - cgu is present 2978 * * false - cgu is not present 2979 */ 2980 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 2981 { 2982 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2983 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2984 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 2985 NULL)) { 2986 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 2987 return true; 2988 } else if (!ice_find_netlist_node(hw, 2989 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 2990 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 2991 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 2992 NULL)) { 2993 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 2994 return true; 2995 } 2996 2997 return false; 2998 } 2999 3000 /** 3001 * ice_is_gps_in_netlist 3002 * @hw: pointer to the hw struct 3003 * 3004 * Check if the GPS generic device is present in the netlist 3005 */ 3006 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3007 { 3008 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3009 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3010 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3011 return false; 3012 3013 return true; 3014 } 3015 3016 /** 3017 * ice_aq_list_caps - query function/device capabilities 3018 * @hw: pointer to the HW struct 3019 * @buf: a buffer to hold the capabilities 3020 * @buf_size: size of the buffer 3021 * @cap_count: if not NULL, set to the number of capabilities reported 3022 * @opc: capabilities type to discover, device or function 3023 * @cd: pointer to command details structure or NULL 3024 * 3025 * Get the function (0x000A) or device (0x000B) capabilities description from 3026 * firmware and store it in the buffer. 3027 * 3028 * If the cap_count pointer is not NULL, then it is set to the number of 3029 * capabilities firmware will report. Note that if the buffer size is too 3030 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3031 * cap_count will still be updated in this case. It is recommended that the 3032 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3033 * firmware could return) to avoid this. 3034 */ 3035 int 3036 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3037 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3038 { 3039 struct libie_aqc_list_caps *cmd; 3040 struct libie_aq_desc desc; 3041 int status; 3042 3043 cmd = &desc.params.get_cap; 3044 3045 if (opc != ice_aqc_opc_list_func_caps && 3046 opc != ice_aqc_opc_list_dev_caps) 3047 return -EINVAL; 3048 3049 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3050 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3051 3052 if (cap_count) 3053 *cap_count = le32_to_cpu(cmd->count); 3054 3055 return status; 3056 } 3057 3058 /** 3059 * ice_discover_dev_caps - Read and extract device capabilities 3060 * @hw: pointer to the hardware structure 3061 * @dev_caps: pointer to device capabilities structure 3062 * 3063 * Read the device capabilities and extract them into the dev_caps structure 3064 * for later use. 3065 */ 3066 int 3067 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3068 { 3069 u32 cap_count = 0; 3070 void *cbuf; 3071 int status; 3072 3073 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3074 if (!cbuf) 3075 return -ENOMEM; 3076 3077 /* Although the driver doesn't know the number of capabilities the 3078 * device will return, we can simply send a 4KB buffer, the maximum 3079 * possible size that firmware can return. 3080 */ 3081 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3082 3083 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3084 ice_aqc_opc_list_dev_caps, NULL); 3085 if (!status) 3086 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3087 kfree(cbuf); 3088 3089 return status; 3090 } 3091 3092 /** 3093 * ice_discover_func_caps - Read and extract function capabilities 3094 * @hw: pointer to the hardware structure 3095 * @func_caps: pointer to function capabilities structure 3096 * 3097 * Read the function capabilities and extract them into the func_caps structure 3098 * for later use. 3099 */ 3100 static int 3101 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3102 { 3103 u32 cap_count = 0; 3104 void *cbuf; 3105 int status; 3106 3107 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3108 if (!cbuf) 3109 return -ENOMEM; 3110 3111 /* Although the driver doesn't know the number of capabilities the 3112 * device will return, we can simply send a 4KB buffer, the maximum 3113 * possible size that firmware can return. 3114 */ 3115 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3116 3117 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3118 ice_aqc_opc_list_func_caps, NULL); 3119 if (!status) 3120 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3121 kfree(cbuf); 3122 3123 return status; 3124 } 3125 3126 /** 3127 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3128 * @hw: pointer to the hardware structure 3129 */ 3130 void ice_set_safe_mode_caps(struct ice_hw *hw) 3131 { 3132 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3133 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3134 struct ice_hw_common_caps cached_caps; 3135 u32 num_funcs; 3136 3137 /* cache some func_caps values that should be restored after memset */ 3138 cached_caps = func_caps->common_cap; 3139 3140 /* unset func capabilities */ 3141 memset(func_caps, 0, sizeof(*func_caps)); 3142 3143 #define ICE_RESTORE_FUNC_CAP(name) \ 3144 func_caps->common_cap.name = cached_caps.name 3145 3146 /* restore cached values */ 3147 ICE_RESTORE_FUNC_CAP(valid_functions); 3148 ICE_RESTORE_FUNC_CAP(txq_first_id); 3149 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3150 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3151 ICE_RESTORE_FUNC_CAP(max_mtu); 3152 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3153 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3154 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3155 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3156 3157 /* one Tx and one Rx queue in safe mode */ 3158 func_caps->common_cap.num_rxq = 1; 3159 func_caps->common_cap.num_txq = 1; 3160 3161 /* two MSIX vectors, one for traffic and one for misc causes */ 3162 func_caps->common_cap.num_msix_vectors = 2; 3163 func_caps->guar_num_vsi = 1; 3164 3165 /* cache some dev_caps values that should be restored after memset */ 3166 cached_caps = dev_caps->common_cap; 3167 num_funcs = dev_caps->num_funcs; 3168 3169 /* unset dev capabilities */ 3170 memset(dev_caps, 0, sizeof(*dev_caps)); 3171 3172 #define ICE_RESTORE_DEV_CAP(name) \ 3173 dev_caps->common_cap.name = cached_caps.name 3174 3175 /* restore cached values */ 3176 ICE_RESTORE_DEV_CAP(valid_functions); 3177 ICE_RESTORE_DEV_CAP(txq_first_id); 3178 ICE_RESTORE_DEV_CAP(rxq_first_id); 3179 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3180 ICE_RESTORE_DEV_CAP(max_mtu); 3181 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3182 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3183 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3184 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3185 dev_caps->num_funcs = num_funcs; 3186 3187 /* one Tx and one Rx queue per function in safe mode */ 3188 dev_caps->common_cap.num_rxq = num_funcs; 3189 dev_caps->common_cap.num_txq = num_funcs; 3190 3191 /* two MSIX vectors per function */ 3192 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3193 } 3194 3195 /** 3196 * ice_get_caps - get info about the HW 3197 * @hw: pointer to the hardware structure 3198 */ 3199 int ice_get_caps(struct ice_hw *hw) 3200 { 3201 int status; 3202 3203 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3204 if (status) 3205 return status; 3206 3207 return ice_discover_func_caps(hw, &hw->func_caps); 3208 } 3209 3210 /** 3211 * ice_aq_manage_mac_write - manage MAC address write command 3212 * @hw: pointer to the HW struct 3213 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3214 * @flags: flags to control write behavior 3215 * @cd: pointer to command details structure or NULL 3216 * 3217 * This function is used to write MAC address to the NVM (0x0108). 3218 */ 3219 int 3220 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3221 struct ice_sq_cd *cd) 3222 { 3223 struct ice_aqc_manage_mac_write *cmd; 3224 struct libie_aq_desc desc; 3225 3226 cmd = libie_aq_raw(&desc); 3227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3228 3229 cmd->flags = flags; 3230 ether_addr_copy(cmd->mac_addr, mac_addr); 3231 3232 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3233 } 3234 3235 /** 3236 * ice_aq_clear_pxe_mode 3237 * @hw: pointer to the HW struct 3238 * 3239 * Tell the firmware that the driver is taking over from PXE (0x0110). 3240 */ 3241 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3242 { 3243 struct ice_aqc_clear_pxe *cmd; 3244 struct libie_aq_desc desc; 3245 3246 cmd = libie_aq_raw(&desc); 3247 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3248 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3249 3250 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3251 } 3252 3253 /** 3254 * ice_clear_pxe_mode - clear pxe operations mode 3255 * @hw: pointer to the HW struct 3256 * 3257 * Make sure all PXE mode settings are cleared, including things 3258 * like descriptor fetch/write-back mode. 3259 */ 3260 void ice_clear_pxe_mode(struct ice_hw *hw) 3261 { 3262 if (ice_check_sq_alive(hw, &hw->adminq)) 3263 ice_aq_clear_pxe_mode(hw); 3264 } 3265 3266 /** 3267 * ice_aq_set_port_params - set physical port parameters. 3268 * @pi: pointer to the port info struct 3269 * @double_vlan: if set double VLAN is enabled 3270 * @cd: pointer to command details structure or NULL 3271 * 3272 * Set Physical port parameters (0x0203) 3273 */ 3274 int 3275 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3276 struct ice_sq_cd *cd) 3277 3278 { 3279 struct ice_aqc_set_port_params *cmd; 3280 struct ice_hw *hw = pi->hw; 3281 struct libie_aq_desc desc; 3282 u16 cmd_flags = 0; 3283 3284 cmd = libie_aq_raw(&desc); 3285 3286 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3287 if (double_vlan) 3288 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3289 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3290 3291 cmd->local_fwd_mode = pi->local_fwd_mode | 3292 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3293 3294 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3295 } 3296 3297 /** 3298 * ice_is_100m_speed_supported 3299 * @hw: pointer to the HW struct 3300 * 3301 * returns true if 100M speeds are supported by the device, 3302 * false otherwise. 3303 */ 3304 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3305 { 3306 switch (hw->device_id) { 3307 case ICE_DEV_ID_E822C_SGMII: 3308 case ICE_DEV_ID_E822L_SGMII: 3309 case ICE_DEV_ID_E823L_1GBE: 3310 case ICE_DEV_ID_E823C_SGMII: 3311 return true; 3312 default: 3313 return false; 3314 } 3315 } 3316 3317 /** 3318 * ice_get_link_speed_based_on_phy_type - returns link speed 3319 * @phy_type_low: lower part of phy_type 3320 * @phy_type_high: higher part of phy_type 3321 * 3322 * This helper function will convert an entry in PHY type structure 3323 * [phy_type_low, phy_type_high] to its corresponding link speed. 3324 * Note: In the structure of [phy_type_low, phy_type_high], there should 3325 * be one bit set, as this function will convert one PHY type to its 3326 * speed. 3327 * 3328 * Return: 3329 * * PHY speed for recognized PHY type 3330 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3331 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3332 */ 3333 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3334 { 3335 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3336 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3337 3338 switch (phy_type_low) { 3339 case ICE_PHY_TYPE_LOW_100BASE_TX: 3340 case ICE_PHY_TYPE_LOW_100M_SGMII: 3341 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3342 break; 3343 case ICE_PHY_TYPE_LOW_1000BASE_T: 3344 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3345 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3346 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3347 case ICE_PHY_TYPE_LOW_1G_SGMII: 3348 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3349 break; 3350 case ICE_PHY_TYPE_LOW_2500BASE_T: 3351 case ICE_PHY_TYPE_LOW_2500BASE_X: 3352 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3353 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3354 break; 3355 case ICE_PHY_TYPE_LOW_5GBASE_T: 3356 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3357 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3358 break; 3359 case ICE_PHY_TYPE_LOW_10GBASE_T: 3360 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3361 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3362 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3363 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3364 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3365 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3366 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3367 break; 3368 case ICE_PHY_TYPE_LOW_25GBASE_T: 3369 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3370 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3371 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3372 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3373 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3374 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3375 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3376 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3377 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3378 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3379 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3380 break; 3381 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3382 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3383 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3384 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3385 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3386 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3387 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3388 break; 3389 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3390 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3391 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3392 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3393 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3394 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3395 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3396 case ICE_PHY_TYPE_LOW_50G_AUI2: 3397 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3398 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3399 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3400 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3401 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3402 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3403 case ICE_PHY_TYPE_LOW_50G_AUI1: 3404 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3405 break; 3406 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3407 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3408 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3409 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3410 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3411 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3412 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3413 case ICE_PHY_TYPE_LOW_100G_AUI4: 3414 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3415 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3416 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3417 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3418 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3419 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3420 break; 3421 default: 3422 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3423 break; 3424 } 3425 3426 switch (phy_type_high) { 3427 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3428 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3429 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3430 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3431 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3432 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3433 break; 3434 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3435 case ICE_PHY_TYPE_HIGH_200G_SR4: 3436 case ICE_PHY_TYPE_HIGH_200G_FR4: 3437 case ICE_PHY_TYPE_HIGH_200G_LR4: 3438 case ICE_PHY_TYPE_HIGH_200G_DR4: 3439 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3440 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3441 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3442 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3443 break; 3444 default: 3445 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3446 break; 3447 } 3448 3449 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3450 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3451 return ICE_AQ_LINK_SPEED_UNKNOWN; 3452 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3453 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3454 return ICE_AQ_LINK_SPEED_UNKNOWN; 3455 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3456 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3457 return speed_phy_type_low; 3458 else 3459 return speed_phy_type_high; 3460 } 3461 3462 /** 3463 * ice_update_phy_type 3464 * @phy_type_low: pointer to the lower part of phy_type 3465 * @phy_type_high: pointer to the higher part of phy_type 3466 * @link_speeds_bitmap: targeted link speeds bitmap 3467 * 3468 * Note: For the link_speeds_bitmap structure, you can check it at 3469 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3470 * link_speeds_bitmap include multiple speeds. 3471 * 3472 * Each entry in this [phy_type_low, phy_type_high] structure will 3473 * present a certain link speed. This helper function will turn on bits 3474 * in [phy_type_low, phy_type_high] structure based on the value of 3475 * link_speeds_bitmap input parameter. 3476 */ 3477 void 3478 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3479 u16 link_speeds_bitmap) 3480 { 3481 u64 pt_high; 3482 u64 pt_low; 3483 int index; 3484 u16 speed; 3485 3486 /* We first check with low part of phy_type */ 3487 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3488 pt_low = BIT_ULL(index); 3489 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3490 3491 if (link_speeds_bitmap & speed) 3492 *phy_type_low |= BIT_ULL(index); 3493 } 3494 3495 /* We then check with high part of phy_type */ 3496 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3497 pt_high = BIT_ULL(index); 3498 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3499 3500 if (link_speeds_bitmap & speed) 3501 *phy_type_high |= BIT_ULL(index); 3502 } 3503 } 3504 3505 /** 3506 * ice_aq_set_phy_cfg 3507 * @hw: pointer to the HW struct 3508 * @pi: port info structure of the interested logical port 3509 * @cfg: structure with PHY configuration data to be set 3510 * @cd: pointer to command details structure or NULL 3511 * 3512 * Set the various PHY configuration parameters supported on the Port. 3513 * One or more of the Set PHY config parameters may be ignored in an MFP 3514 * mode as the PF may not have the privilege to set some of the PHY Config 3515 * parameters. This status will be indicated by the command response (0x0601). 3516 */ 3517 int 3518 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3519 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3520 { 3521 struct ice_aqc_set_phy_cfg *cmd; 3522 struct libie_aq_desc desc; 3523 int status; 3524 3525 if (!cfg) 3526 return -EINVAL; 3527 3528 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3529 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3530 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3531 cfg->caps); 3532 3533 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3534 } 3535 3536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3537 cmd = libie_aq_raw(&desc); 3538 cmd->lport_num = pi->lport; 3539 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3540 3541 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3542 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3543 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3544 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3545 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3546 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3547 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3548 cfg->low_power_ctrl_an); 3549 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3550 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3551 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3552 cfg->link_fec_opt); 3553 3554 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3555 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3556 status = 0; 3557 3558 if (!status) 3559 pi->phy.curr_user_phy_cfg = *cfg; 3560 3561 return status; 3562 } 3563 3564 /** 3565 * ice_update_link_info - update status of the HW network link 3566 * @pi: port info structure of the interested logical port 3567 */ 3568 int ice_update_link_info(struct ice_port_info *pi) 3569 { 3570 struct ice_link_status *li; 3571 int status; 3572 3573 if (!pi) 3574 return -EINVAL; 3575 3576 li = &pi->phy.link_info; 3577 3578 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3579 if (status) 3580 return status; 3581 3582 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3583 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3584 3585 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3586 if (!pcaps) 3587 return -ENOMEM; 3588 3589 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3590 pcaps, NULL); 3591 } 3592 3593 return status; 3594 } 3595 3596 /** 3597 * ice_aq_get_phy_equalization - function to read serdes equaliser 3598 * value from firmware using admin queue command. 3599 * @hw: pointer to the HW struct 3600 * @data_in: represents the serdes equalization parameter requested 3601 * @op_code: represents the serdes number and flag to represent tx or rx 3602 * @serdes_num: represents the serdes number 3603 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3604 * 3605 * Return: non-zero status on error and 0 on success. 3606 */ 3607 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3608 u8 serdes_num, int *output) 3609 { 3610 struct ice_aqc_dnl_call_command *cmd; 3611 struct ice_aqc_dnl_call buf = {}; 3612 struct libie_aq_desc desc; 3613 int err; 3614 3615 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3616 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3617 cpu_to_le16(op_code | (serdes_num & 0xF)); 3618 cmd = libie_aq_raw(&desc); 3619 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3620 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3621 LIBIE_AQ_FLAG_RD | 3622 LIBIE_AQ_FLAG_SI); 3623 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3624 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3625 3626 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3627 NULL); 3628 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3629 3630 return err; 3631 } 3632 3633 #define FEC_REG_PORT(port) { \ 3634 FEC_CORR_LOW_REG_PORT##port, \ 3635 FEC_CORR_HIGH_REG_PORT##port, \ 3636 FEC_UNCORR_LOW_REG_PORT##port, \ 3637 FEC_UNCORR_HIGH_REG_PORT##port, \ 3638 } 3639 3640 static const u32 fec_reg[][ICE_FEC_MAX] = { 3641 FEC_REG_PORT(0), 3642 FEC_REG_PORT(1), 3643 FEC_REG_PORT(2), 3644 FEC_REG_PORT(3) 3645 }; 3646 3647 /** 3648 * ice_aq_get_fec_stats - reads fec stats from phy 3649 * @hw: pointer to the HW struct 3650 * @pcs_quad: represents pcsquad of user input serdes 3651 * @pcs_port: represents the pcs port number part of above pcs quad 3652 * @fec_type: represents FEC stats type 3653 * @output: pointer to the caller-supplied buffer to return requested fec stats 3654 * 3655 * Return: non-zero status on error and 0 on success. 3656 */ 3657 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3658 enum ice_fec_stats_types fec_type, u32 *output) 3659 { 3660 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3661 struct ice_sbq_msg_input msg = {}; 3662 u32 receiver_id, reg_offset; 3663 int err; 3664 3665 if (pcs_port > 3) 3666 return -EINVAL; 3667 3668 reg_offset = fec_reg[pcs_port][fec_type]; 3669 3670 if (pcs_quad == 0) 3671 receiver_id = FEC_RECEIVER_ID_PCS0; 3672 else if (pcs_quad == 1) 3673 receiver_id = FEC_RECEIVER_ID_PCS1; 3674 else 3675 return -EINVAL; 3676 3677 msg.msg_addr_low = lower_16_bits(reg_offset); 3678 msg.msg_addr_high = receiver_id; 3679 msg.opcode = ice_sbq_msg_rd; 3680 msg.dest_dev = ice_sbq_dev_phy_0; 3681 3682 err = ice_sbq_rw_reg(hw, &msg, flag); 3683 if (err) 3684 return err; 3685 3686 *output = msg.data; 3687 return 0; 3688 } 3689 3690 /** 3691 * ice_cache_phy_user_req 3692 * @pi: port information structure 3693 * @cache_data: PHY logging data 3694 * @cache_mode: PHY logging mode 3695 * 3696 * Log the user request on (FC, FEC, SPEED) for later use. 3697 */ 3698 static void 3699 ice_cache_phy_user_req(struct ice_port_info *pi, 3700 struct ice_phy_cache_mode_data cache_data, 3701 enum ice_phy_cache_mode cache_mode) 3702 { 3703 if (!pi) 3704 return; 3705 3706 switch (cache_mode) { 3707 case ICE_FC_MODE: 3708 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3709 break; 3710 case ICE_SPEED_MODE: 3711 pi->phy.curr_user_speed_req = 3712 cache_data.data.curr_user_speed_req; 3713 break; 3714 case ICE_FEC_MODE: 3715 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3716 break; 3717 default: 3718 break; 3719 } 3720 } 3721 3722 /** 3723 * ice_caps_to_fc_mode 3724 * @caps: PHY capabilities 3725 * 3726 * Convert PHY FC capabilities to ice FC mode 3727 */ 3728 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3729 { 3730 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3731 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3732 return ICE_FC_FULL; 3733 3734 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3735 return ICE_FC_TX_PAUSE; 3736 3737 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3738 return ICE_FC_RX_PAUSE; 3739 3740 return ICE_FC_NONE; 3741 } 3742 3743 /** 3744 * ice_caps_to_fec_mode 3745 * @caps: PHY capabilities 3746 * @fec_options: Link FEC options 3747 * 3748 * Convert PHY FEC capabilities to ice FEC mode 3749 */ 3750 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3751 { 3752 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3753 return ICE_FEC_AUTO; 3754 3755 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3756 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3757 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3758 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3759 return ICE_FEC_BASER; 3760 3761 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3762 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3763 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3764 return ICE_FEC_RS; 3765 3766 return ICE_FEC_NONE; 3767 } 3768 3769 /** 3770 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3771 * @pi: port information structure 3772 * @cfg: PHY configuration data to set FC mode 3773 * @req_mode: FC mode to configure 3774 */ 3775 int 3776 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3777 enum ice_fc_mode req_mode) 3778 { 3779 struct ice_phy_cache_mode_data cache_data; 3780 u8 pause_mask = 0x0; 3781 3782 if (!pi || !cfg) 3783 return -EINVAL; 3784 3785 switch (req_mode) { 3786 case ICE_FC_FULL: 3787 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3788 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3789 break; 3790 case ICE_FC_RX_PAUSE: 3791 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3792 break; 3793 case ICE_FC_TX_PAUSE: 3794 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3795 break; 3796 default: 3797 break; 3798 } 3799 3800 /* clear the old pause settings */ 3801 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3802 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3803 3804 /* set the new capabilities */ 3805 cfg->caps |= pause_mask; 3806 3807 /* Cache user FC request */ 3808 cache_data.data.curr_user_fc_req = req_mode; 3809 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3810 3811 return 0; 3812 } 3813 3814 /** 3815 * ice_set_fc 3816 * @pi: port information structure 3817 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3818 * @ena_auto_link_update: enable automatic link update 3819 * 3820 * Set the requested flow control mode. 3821 */ 3822 int 3823 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3824 { 3825 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3826 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3827 struct ice_hw *hw; 3828 int status; 3829 3830 if (!pi || !aq_failures) 3831 return -EINVAL; 3832 3833 *aq_failures = 0; 3834 hw = pi->hw; 3835 3836 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3837 if (!pcaps) 3838 return -ENOMEM; 3839 3840 /* Get the current PHY config */ 3841 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3842 pcaps, NULL); 3843 if (status) { 3844 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3845 goto out; 3846 } 3847 3848 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3849 3850 /* Configure the set PHY data */ 3851 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3852 if (status) 3853 goto out; 3854 3855 /* If the capabilities have changed, then set the new config */ 3856 if (cfg.caps != pcaps->caps) { 3857 int retry_count, retry_max = 10; 3858 3859 /* Auto restart link so settings take effect */ 3860 if (ena_auto_link_update) 3861 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3862 3863 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3864 if (status) { 3865 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3866 goto out; 3867 } 3868 3869 /* Update the link info 3870 * It sometimes takes a really long time for link to 3871 * come back from the atomic reset. Thus, we wait a 3872 * little bit. 3873 */ 3874 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3875 status = ice_update_link_info(pi); 3876 3877 if (!status) 3878 break; 3879 3880 mdelay(100); 3881 } 3882 3883 if (status) 3884 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3885 } 3886 3887 out: 3888 return status; 3889 } 3890 3891 /** 3892 * ice_phy_caps_equals_cfg 3893 * @phy_caps: PHY capabilities 3894 * @phy_cfg: PHY configuration 3895 * 3896 * Helper function to determine if PHY capabilities matches PHY 3897 * configuration 3898 */ 3899 bool 3900 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3901 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3902 { 3903 u8 caps_mask, cfg_mask; 3904 3905 if (!phy_caps || !phy_cfg) 3906 return false; 3907 3908 /* These bits are not common between capabilities and configuration. 3909 * Do not use them to determine equality. 3910 */ 3911 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3912 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3913 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3914 3915 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3916 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3917 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3918 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3919 phy_caps->eee_cap != phy_cfg->eee_cap || 3920 phy_caps->eeer_value != phy_cfg->eeer_value || 3921 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3922 return false; 3923 3924 return true; 3925 } 3926 3927 /** 3928 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3929 * @pi: port information structure 3930 * @caps: PHY ability structure to copy date from 3931 * @cfg: PHY configuration structure to copy data to 3932 * 3933 * Helper function to copy AQC PHY get ability data to PHY set configuration 3934 * data structure 3935 */ 3936 void 3937 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3938 struct ice_aqc_get_phy_caps_data *caps, 3939 struct ice_aqc_set_phy_cfg_data *cfg) 3940 { 3941 if (!pi || !caps || !cfg) 3942 return; 3943 3944 memset(cfg, 0, sizeof(*cfg)); 3945 cfg->phy_type_low = caps->phy_type_low; 3946 cfg->phy_type_high = caps->phy_type_high; 3947 cfg->caps = caps->caps; 3948 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3949 cfg->eee_cap = caps->eee_cap; 3950 cfg->eeer_value = caps->eeer_value; 3951 cfg->link_fec_opt = caps->link_fec_options; 3952 cfg->module_compliance_enforcement = 3953 caps->module_compliance_enforcement; 3954 } 3955 3956 /** 3957 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3958 * @pi: port information structure 3959 * @cfg: PHY configuration data to set FEC mode 3960 * @fec: FEC mode to configure 3961 */ 3962 int 3963 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3964 enum ice_fec_mode fec) 3965 { 3966 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3967 struct ice_hw *hw; 3968 int status; 3969 3970 if (!pi || !cfg) 3971 return -EINVAL; 3972 3973 hw = pi->hw; 3974 3975 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3976 if (!pcaps) 3977 return -ENOMEM; 3978 3979 status = ice_aq_get_phy_caps(pi, false, 3980 (ice_fw_supports_report_dflt_cfg(hw) ? 3981 ICE_AQC_REPORT_DFLT_CFG : 3982 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3983 if (status) 3984 goto out; 3985 3986 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3987 cfg->link_fec_opt = pcaps->link_fec_options; 3988 3989 switch (fec) { 3990 case ICE_FEC_BASER: 3991 /* Clear RS bits, and AND BASE-R ability 3992 * bits and OR request bits. 3993 */ 3994 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3995 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3996 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3997 ICE_AQC_PHY_FEC_25G_KR_REQ; 3998 break; 3999 case ICE_FEC_RS: 4000 /* Clear BASE-R bits, and AND RS ability 4001 * bits and OR request bits. 4002 */ 4003 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4004 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4005 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4006 break; 4007 case ICE_FEC_NONE: 4008 /* Clear all FEC option bits. */ 4009 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4010 break; 4011 case ICE_FEC_AUTO: 4012 /* AND auto FEC bit, and all caps bits. */ 4013 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4014 cfg->link_fec_opt |= pcaps->link_fec_options; 4015 break; 4016 default: 4017 status = -EINVAL; 4018 break; 4019 } 4020 4021 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4022 !ice_fw_supports_report_dflt_cfg(hw)) { 4023 struct ice_link_default_override_tlv tlv = { 0 }; 4024 4025 status = ice_get_link_default_override(&tlv, pi); 4026 if (status) 4027 goto out; 4028 4029 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4030 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4031 cfg->link_fec_opt = tlv.fec_options; 4032 } 4033 4034 out: 4035 return status; 4036 } 4037 4038 /** 4039 * ice_get_link_status - get status of the HW network link 4040 * @pi: port information structure 4041 * @link_up: pointer to bool (true/false = linkup/linkdown) 4042 * 4043 * Variable link_up is true if link is up, false if link is down. 4044 * The variable link_up is invalid if status is non zero. As a 4045 * result of this call, link status reporting becomes enabled 4046 */ 4047 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4048 { 4049 struct ice_phy_info *phy_info; 4050 int status = 0; 4051 4052 if (!pi || !link_up) 4053 return -EINVAL; 4054 4055 phy_info = &pi->phy; 4056 4057 if (phy_info->get_link_info) { 4058 status = ice_update_link_info(pi); 4059 4060 if (status) 4061 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4062 status); 4063 } 4064 4065 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4066 4067 return status; 4068 } 4069 4070 /** 4071 * ice_aq_set_link_restart_an 4072 * @pi: pointer to the port information structure 4073 * @ena_link: if true: enable link, if false: disable link 4074 * @cd: pointer to command details structure or NULL 4075 * 4076 * Sets up the link and restarts the Auto-Negotiation over the link. 4077 */ 4078 int 4079 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4080 struct ice_sq_cd *cd) 4081 { 4082 struct ice_aqc_restart_an *cmd; 4083 struct libie_aq_desc desc; 4084 4085 cmd = libie_aq_raw(&desc); 4086 4087 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4088 4089 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4090 cmd->lport_num = pi->lport; 4091 if (ena_link) 4092 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4093 else 4094 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4095 4096 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4097 } 4098 4099 /** 4100 * ice_aq_set_event_mask 4101 * @hw: pointer to the HW struct 4102 * @port_num: port number of the physical function 4103 * @mask: event mask to be set 4104 * @cd: pointer to command details structure or NULL 4105 * 4106 * Set event mask (0x0613) 4107 */ 4108 int 4109 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4110 struct ice_sq_cd *cd) 4111 { 4112 struct ice_aqc_set_event_mask *cmd; 4113 struct libie_aq_desc desc; 4114 4115 cmd = libie_aq_raw(&desc); 4116 4117 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4118 4119 cmd->lport_num = port_num; 4120 4121 cmd->event_mask = cpu_to_le16(mask); 4122 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4123 } 4124 4125 /** 4126 * ice_aq_set_mac_loopback 4127 * @hw: pointer to the HW struct 4128 * @ena_lpbk: Enable or Disable loopback 4129 * @cd: pointer to command details structure or NULL 4130 * 4131 * Enable/disable loopback on a given port 4132 */ 4133 int 4134 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4135 { 4136 struct ice_aqc_set_mac_lb *cmd; 4137 struct libie_aq_desc desc; 4138 4139 cmd = libie_aq_raw(&desc); 4140 4141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4142 if (ena_lpbk) 4143 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4144 4145 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4146 } 4147 4148 /** 4149 * ice_aq_set_port_id_led 4150 * @pi: pointer to the port information 4151 * @is_orig_mode: is this LED set to original mode (by the net-list) 4152 * @cd: pointer to command details structure or NULL 4153 * 4154 * Set LED value for the given port (0x06e9) 4155 */ 4156 int 4157 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4158 struct ice_sq_cd *cd) 4159 { 4160 struct ice_aqc_set_port_id_led *cmd; 4161 struct ice_hw *hw = pi->hw; 4162 struct libie_aq_desc desc; 4163 4164 cmd = libie_aq_raw(&desc); 4165 4166 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4167 4168 if (is_orig_mode) 4169 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4170 else 4171 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4172 4173 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4174 } 4175 4176 /** 4177 * ice_aq_get_port_options 4178 * @hw: pointer to the HW struct 4179 * @options: buffer for the resultant port options 4180 * @option_count: input - size of the buffer in port options structures, 4181 * output - number of returned port options 4182 * @lport: logical port to call the command with (optional) 4183 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4184 * when PF owns more than 1 port it must be true 4185 * @active_option_idx: index of active port option in returned buffer 4186 * @active_option_valid: active option in returned buffer is valid 4187 * @pending_option_idx: index of pending port option in returned buffer 4188 * @pending_option_valid: pending option in returned buffer is valid 4189 * 4190 * Calls Get Port Options AQC (0x06ea) and verifies result. 4191 */ 4192 int 4193 ice_aq_get_port_options(struct ice_hw *hw, 4194 struct ice_aqc_get_port_options_elem *options, 4195 u8 *option_count, u8 lport, bool lport_valid, 4196 u8 *active_option_idx, bool *active_option_valid, 4197 u8 *pending_option_idx, bool *pending_option_valid) 4198 { 4199 struct ice_aqc_get_port_options *cmd; 4200 struct libie_aq_desc desc; 4201 int status; 4202 u8 i; 4203 4204 /* options buffer shall be able to hold max returned options */ 4205 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4206 return -EINVAL; 4207 4208 cmd = libie_aq_raw(&desc); 4209 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4210 4211 if (lport_valid) 4212 cmd->lport_num = lport; 4213 cmd->lport_num_valid = lport_valid; 4214 4215 status = ice_aq_send_cmd(hw, &desc, options, 4216 *option_count * sizeof(*options), NULL); 4217 if (status) 4218 return status; 4219 4220 /* verify direct FW response & set output parameters */ 4221 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4222 cmd->port_options_count); 4223 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4224 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4225 cmd->port_options); 4226 if (*active_option_valid) { 4227 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4228 cmd->port_options); 4229 if (*active_option_idx > (*option_count - 1)) 4230 return -EIO; 4231 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4232 *active_option_idx); 4233 } 4234 4235 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4236 cmd->pending_port_option_status); 4237 if (*pending_option_valid) { 4238 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4239 cmd->pending_port_option_status); 4240 if (*pending_option_idx > (*option_count - 1)) 4241 return -EIO; 4242 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4243 *pending_option_idx); 4244 } 4245 4246 /* mask output options fields */ 4247 for (i = 0; i < *option_count; i++) { 4248 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4249 options[i].pmd); 4250 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4251 options[i].max_lane_speed); 4252 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4253 options[i].pmd, options[i].max_lane_speed); 4254 } 4255 4256 return 0; 4257 } 4258 4259 /** 4260 * ice_aq_set_port_option 4261 * @hw: pointer to the HW struct 4262 * @lport: logical port to call the command with 4263 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4264 * when PF owns more than 1 port it must be true 4265 * @new_option: new port option to be written 4266 * 4267 * Calls Set Port Options AQC (0x06eb). 4268 */ 4269 int 4270 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4271 u8 new_option) 4272 { 4273 struct ice_aqc_set_port_option *cmd; 4274 struct libie_aq_desc desc; 4275 4276 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4277 return -EINVAL; 4278 4279 cmd = libie_aq_raw(&desc); 4280 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4281 4282 if (lport_valid) 4283 cmd->lport_num = lport; 4284 4285 cmd->lport_num_valid = lport_valid; 4286 cmd->selected_port_option = new_option; 4287 4288 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4289 } 4290 4291 /** 4292 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4293 * @hw: pointer to the hw struct 4294 * 4295 * Return: PHY lane number on success, negative error code otherwise. 4296 */ 4297 int ice_get_phy_lane_number(struct ice_hw *hw) 4298 { 4299 struct ice_aqc_get_port_options_elem *options; 4300 unsigned int lport = 0; 4301 unsigned int lane; 4302 int err; 4303 4304 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4305 if (!options) 4306 return -ENOMEM; 4307 4308 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4309 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4310 u8 speed, active_idx, pending_idx; 4311 bool active_valid, pending_valid; 4312 4313 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4314 true, &active_idx, &active_valid, 4315 &pending_idx, &pending_valid); 4316 if (err) 4317 goto err; 4318 4319 if (!active_valid) 4320 continue; 4321 4322 speed = options[active_idx].max_lane_speed; 4323 /* If we don't get speed for this lane, it's unoccupied */ 4324 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4325 continue; 4326 4327 if (hw->pf_id == lport) { 4328 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4329 ice_is_dual(hw) && !ice_is_primary(hw)) 4330 lane += ICE_PORTS_PER_QUAD; 4331 kfree(options); 4332 return lane; 4333 } 4334 lport++; 4335 } 4336 4337 /* PHY lane not found */ 4338 err = -ENXIO; 4339 err: 4340 kfree(options); 4341 return err; 4342 } 4343 4344 /** 4345 * ice_aq_sff_eeprom 4346 * @hw: pointer to the HW struct 4347 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4348 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4349 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4350 * @page: QSFP page 4351 * @set_page: set or ignore the page 4352 * @data: pointer to data buffer to be read/written to the I2C device. 4353 * @length: 1-16 for read, 1 for write. 4354 * @write: 0 read, 1 for write. 4355 * @cd: pointer to command details structure or NULL 4356 * 4357 * Read/Write SFF EEPROM (0x06EE) 4358 */ 4359 int 4360 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4361 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4362 bool write, struct ice_sq_cd *cd) 4363 { 4364 struct ice_aqc_sff_eeprom *cmd; 4365 struct libie_aq_desc desc; 4366 u16 i2c_bus_addr; 4367 int status; 4368 4369 if (!data || (mem_addr & 0xff00)) 4370 return -EINVAL; 4371 4372 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4373 cmd = libie_aq_raw(&desc); 4374 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4375 cmd->lport_num = (u8)(lport & 0xff); 4376 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4377 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4378 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4379 if (write) 4380 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4381 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4382 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4383 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4384 4385 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4386 return status; 4387 } 4388 4389 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4390 { 4391 switch (type) { 4392 case ICE_LUT_VSI: 4393 return ICE_LUT_VSI_SIZE; 4394 case ICE_LUT_GLOBAL: 4395 return ICE_LUT_GLOBAL_SIZE; 4396 case ICE_LUT_PF: 4397 return ICE_LUT_PF_SIZE; 4398 } 4399 WARN_ONCE(1, "incorrect type passed"); 4400 return ICE_LUT_VSI_SIZE; 4401 } 4402 4403 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4404 { 4405 switch (size) { 4406 case ICE_LUT_VSI_SIZE: 4407 return ICE_AQC_LUT_SIZE_SMALL; 4408 case ICE_LUT_GLOBAL_SIZE: 4409 return ICE_AQC_LUT_SIZE_512; 4410 case ICE_LUT_PF_SIZE: 4411 return ICE_AQC_LUT_SIZE_2K; 4412 } 4413 WARN_ONCE(1, "incorrect size passed"); 4414 return 0; 4415 } 4416 4417 /** 4418 * __ice_aq_get_set_rss_lut 4419 * @hw: pointer to the hardware structure 4420 * @params: RSS LUT parameters 4421 * @set: set true to set the table, false to get the table 4422 * 4423 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4424 */ 4425 static int 4426 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4427 struct ice_aq_get_set_rss_lut_params *params, bool set) 4428 { 4429 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4430 enum ice_lut_type lut_type = params->lut_type; 4431 struct ice_aqc_get_set_rss_lut *desc_params; 4432 enum ice_aqc_lut_flags flags; 4433 enum ice_lut_size lut_size; 4434 struct libie_aq_desc desc; 4435 u8 *lut = params->lut; 4436 4437 4438 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4439 return -EINVAL; 4440 4441 lut_size = ice_lut_type_to_size(lut_type); 4442 if (lut_size > params->lut_size) 4443 return -EINVAL; 4444 else if (set && lut_size != params->lut_size) 4445 return -EINVAL; 4446 4447 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4448 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4449 if (set) 4450 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4451 4452 desc_params = libie_aq_raw(&desc); 4453 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4454 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4455 4456 if (lut_type == ICE_LUT_GLOBAL) 4457 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4458 params->global_lut_id); 4459 4460 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4461 desc_params->flags = cpu_to_le16(flags); 4462 4463 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4464 } 4465 4466 /** 4467 * ice_aq_get_rss_lut 4468 * @hw: pointer to the hardware structure 4469 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4470 * 4471 * get the RSS lookup table, PF or VSI type 4472 */ 4473 int 4474 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4475 { 4476 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4477 } 4478 4479 /** 4480 * ice_aq_set_rss_lut 4481 * @hw: pointer to the hardware structure 4482 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4483 * 4484 * set the RSS lookup table, PF or VSI type 4485 */ 4486 int 4487 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4488 { 4489 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4490 } 4491 4492 /** 4493 * __ice_aq_get_set_rss_key 4494 * @hw: pointer to the HW struct 4495 * @vsi_id: VSI FW index 4496 * @key: pointer to key info struct 4497 * @set: set true to set the key, false to get the key 4498 * 4499 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4500 */ 4501 static int 4502 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4503 struct ice_aqc_get_set_rss_keys *key, bool set) 4504 { 4505 struct ice_aqc_get_set_rss_key *desc_params; 4506 u16 key_size = sizeof(*key); 4507 struct libie_aq_desc desc; 4508 4509 if (set) { 4510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4511 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4512 } else { 4513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4514 } 4515 4516 desc_params = libie_aq_raw(&desc); 4517 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4518 4519 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4520 } 4521 4522 /** 4523 * ice_aq_get_rss_key 4524 * @hw: pointer to the HW struct 4525 * @vsi_handle: software VSI handle 4526 * @key: pointer to key info struct 4527 * 4528 * get the RSS key per VSI 4529 */ 4530 int 4531 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4532 struct ice_aqc_get_set_rss_keys *key) 4533 { 4534 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4535 return -EINVAL; 4536 4537 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4538 key, false); 4539 } 4540 4541 /** 4542 * ice_aq_set_rss_key 4543 * @hw: pointer to the HW struct 4544 * @vsi_handle: software VSI handle 4545 * @keys: pointer to key info struct 4546 * 4547 * set the RSS key per VSI 4548 */ 4549 int 4550 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4551 struct ice_aqc_get_set_rss_keys *keys) 4552 { 4553 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4554 return -EINVAL; 4555 4556 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4557 keys, true); 4558 } 4559 4560 /** 4561 * ice_aq_add_lan_txq 4562 * @hw: pointer to the hardware structure 4563 * @num_qgrps: Number of added queue groups 4564 * @qg_list: list of queue groups to be added 4565 * @buf_size: size of buffer for indirect command 4566 * @cd: pointer to command details structure or NULL 4567 * 4568 * Add Tx LAN queue (0x0C30) 4569 * 4570 * NOTE: 4571 * Prior to calling add Tx LAN queue: 4572 * Initialize the following as part of the Tx queue context: 4573 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4574 * Cache profile and Packet shaper profile. 4575 * 4576 * After add Tx LAN queue AQ command is completed: 4577 * Interrupts should be associated with specific queues, 4578 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4579 * flow. 4580 */ 4581 static int 4582 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4583 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4584 struct ice_sq_cd *cd) 4585 { 4586 struct ice_aqc_add_tx_qgrp *list; 4587 struct ice_aqc_add_txqs *cmd; 4588 struct libie_aq_desc desc; 4589 u16 i, sum_size = 0; 4590 4591 cmd = libie_aq_raw(&desc); 4592 4593 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4594 4595 if (!qg_list) 4596 return -EINVAL; 4597 4598 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4599 return -EINVAL; 4600 4601 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4602 sum_size += struct_size(list, txqs, list->num_txqs); 4603 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4604 list->num_txqs); 4605 } 4606 4607 if (buf_size != sum_size) 4608 return -EINVAL; 4609 4610 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4611 4612 cmd->num_qgrps = num_qgrps; 4613 4614 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4615 } 4616 4617 /** 4618 * ice_aq_dis_lan_txq 4619 * @hw: pointer to the hardware structure 4620 * @num_qgrps: number of groups in the list 4621 * @qg_list: the list of groups to disable 4622 * @buf_size: the total size of the qg_list buffer in bytes 4623 * @rst_src: if called due to reset, specifies the reset source 4624 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4625 * @cd: pointer to command details structure or NULL 4626 * 4627 * Disable LAN Tx queue (0x0C31) 4628 */ 4629 static int 4630 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4631 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4632 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4633 struct ice_sq_cd *cd) 4634 { 4635 struct ice_aqc_dis_txq_item *item; 4636 struct ice_aqc_dis_txqs *cmd; 4637 struct libie_aq_desc desc; 4638 u16 vmvf_and_timeout; 4639 u16 i, sz = 0; 4640 int status; 4641 4642 cmd = libie_aq_raw(&desc); 4643 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4644 4645 /* qg_list can be NULL only in VM/VF reset flow */ 4646 if (!qg_list && !rst_src) 4647 return -EINVAL; 4648 4649 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4650 return -EINVAL; 4651 4652 cmd->num_entries = num_qgrps; 4653 4654 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4655 4656 switch (rst_src) { 4657 case ICE_VM_RESET: 4658 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4659 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4660 break; 4661 case ICE_VF_RESET: 4662 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4663 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4664 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4665 ICE_AQC_Q_DIS_VMVF_NUM_M; 4666 break; 4667 case ICE_NO_RESET: 4668 default: 4669 break; 4670 } 4671 4672 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4673 4674 /* flush pipe on time out */ 4675 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4676 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4677 if (!qg_list) 4678 goto do_aq; 4679 4680 /* set RD bit to indicate that command buffer is provided by the driver 4681 * and it needs to be read by the firmware 4682 */ 4683 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4684 4685 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4686 u16 item_size = struct_size(item, q_id, item->num_qs); 4687 4688 /* If the num of queues is even, add 2 bytes of padding */ 4689 if ((item->num_qs % 2) == 0) 4690 item_size += 2; 4691 4692 sz += item_size; 4693 4694 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4695 } 4696 4697 if (buf_size != sz) 4698 return -EINVAL; 4699 4700 do_aq: 4701 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4702 if (status) { 4703 if (!qg_list) 4704 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4705 vmvf_num, hw->adminq.sq_last_status); 4706 else 4707 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4708 le16_to_cpu(qg_list[0].q_id[0]), 4709 hw->adminq.sq_last_status); 4710 } 4711 return status; 4712 } 4713 4714 /** 4715 * ice_aq_cfg_lan_txq 4716 * @hw: pointer to the hardware structure 4717 * @buf: buffer for command 4718 * @buf_size: size of buffer in bytes 4719 * @num_qs: number of queues being configured 4720 * @oldport: origination lport 4721 * @newport: destination lport 4722 * @cd: pointer to command details structure or NULL 4723 * 4724 * Move/Configure LAN Tx queue (0x0C32) 4725 * 4726 * There is a better AQ command to use for moving nodes, so only coding 4727 * this one for configuring the node. 4728 */ 4729 int 4730 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4731 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4732 struct ice_sq_cd *cd) 4733 { 4734 struct ice_aqc_cfg_txqs *cmd; 4735 struct libie_aq_desc desc; 4736 int status; 4737 4738 cmd = libie_aq_raw(&desc); 4739 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4740 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4741 4742 if (!buf) 4743 return -EINVAL; 4744 4745 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4746 cmd->num_qs = num_qs; 4747 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4748 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4749 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4750 cmd->blocked_cgds = 0; 4751 4752 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4753 if (status) 4754 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4755 hw->adminq.sq_last_status); 4756 return status; 4757 } 4758 4759 /** 4760 * ice_aq_add_rdma_qsets 4761 * @hw: pointer to the hardware structure 4762 * @num_qset_grps: Number of RDMA Qset groups 4763 * @qset_list: list of Qset groups to be added 4764 * @buf_size: size of buffer for indirect command 4765 * @cd: pointer to command details structure or NULL 4766 * 4767 * Add Tx RDMA Qsets (0x0C33) 4768 */ 4769 static int 4770 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4771 struct ice_aqc_add_rdma_qset_data *qset_list, 4772 u16 buf_size, struct ice_sq_cd *cd) 4773 { 4774 struct ice_aqc_add_rdma_qset_data *list; 4775 struct ice_aqc_add_rdma_qset *cmd; 4776 struct libie_aq_desc desc; 4777 u16 i, sum_size = 0; 4778 4779 cmd = libie_aq_raw(&desc); 4780 4781 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4782 4783 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4784 return -EINVAL; 4785 4786 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4787 u16 num_qsets = le16_to_cpu(list->num_qsets); 4788 4789 sum_size += struct_size(list, rdma_qsets, num_qsets); 4790 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4791 num_qsets); 4792 } 4793 4794 if (buf_size != sum_size) 4795 return -EINVAL; 4796 4797 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4798 4799 cmd->num_qset_grps = num_qset_grps; 4800 4801 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4802 } 4803 4804 /* End of FW Admin Queue command wrappers */ 4805 4806 /** 4807 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4808 * @hw: pointer to the HW struct 4809 * @vsi_handle: software VSI handle 4810 * @tc: TC number 4811 * @q_handle: software queue handle 4812 */ 4813 struct ice_q_ctx * 4814 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4815 { 4816 struct ice_vsi_ctx *vsi; 4817 struct ice_q_ctx *q_ctx; 4818 4819 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4820 if (!vsi) 4821 return NULL; 4822 if (q_handle >= vsi->num_lan_q_entries[tc]) 4823 return NULL; 4824 if (!vsi->lan_q_ctx[tc]) 4825 return NULL; 4826 q_ctx = vsi->lan_q_ctx[tc]; 4827 return &q_ctx[q_handle]; 4828 } 4829 4830 /** 4831 * ice_ena_vsi_txq 4832 * @pi: port information structure 4833 * @vsi_handle: software VSI handle 4834 * @tc: TC number 4835 * @q_handle: software queue handle 4836 * @num_qgrps: Number of added queue groups 4837 * @buf: list of queue groups to be added 4838 * @buf_size: size of buffer for indirect command 4839 * @cd: pointer to command details structure or NULL 4840 * 4841 * This function adds one LAN queue 4842 */ 4843 int 4844 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4845 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4846 struct ice_sq_cd *cd) 4847 { 4848 struct ice_aqc_txsched_elem_data node = { 0 }; 4849 struct ice_sched_node *parent; 4850 struct ice_q_ctx *q_ctx; 4851 struct ice_hw *hw; 4852 int status; 4853 4854 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4855 return -EIO; 4856 4857 if (num_qgrps > 1 || buf->num_txqs > 1) 4858 return -ENOSPC; 4859 4860 hw = pi->hw; 4861 4862 if (!ice_is_vsi_valid(hw, vsi_handle)) 4863 return -EINVAL; 4864 4865 mutex_lock(&pi->sched_lock); 4866 4867 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4868 if (!q_ctx) { 4869 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4870 q_handle); 4871 status = -EINVAL; 4872 goto ena_txq_exit; 4873 } 4874 4875 /* find a parent node */ 4876 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4877 ICE_SCHED_NODE_OWNER_LAN); 4878 if (!parent) { 4879 status = -EINVAL; 4880 goto ena_txq_exit; 4881 } 4882 4883 buf->parent_teid = parent->info.node_teid; 4884 node.parent_teid = parent->info.node_teid; 4885 /* Mark that the values in the "generic" section as valid. The default 4886 * value in the "generic" section is zero. This means that : 4887 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4888 * - 0 priority among siblings, indicated by Bit 1-3. 4889 * - WFQ, indicated by Bit 4. 4890 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4891 * Bit 5-6. 4892 * - Bit 7 is reserved. 4893 * Without setting the generic section as valid in valid_sections, the 4894 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4895 */ 4896 buf->txqs[0].info.valid_sections = 4897 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4898 ICE_AQC_ELEM_VALID_EIR; 4899 buf->txqs[0].info.generic = 0; 4900 buf->txqs[0].info.cir_bw.bw_profile_idx = 4901 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4902 buf->txqs[0].info.cir_bw.bw_alloc = 4903 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4904 buf->txqs[0].info.eir_bw.bw_profile_idx = 4905 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4906 buf->txqs[0].info.eir_bw.bw_alloc = 4907 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4908 4909 /* add the LAN queue */ 4910 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4911 if (status) { 4912 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4913 le16_to_cpu(buf->txqs[0].txq_id), 4914 hw->adminq.sq_last_status); 4915 goto ena_txq_exit; 4916 } 4917 4918 node.node_teid = buf->txqs[0].q_teid; 4919 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4920 q_ctx->q_handle = q_handle; 4921 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4922 4923 /* add a leaf node into scheduler tree queue layer */ 4924 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4925 if (!status) 4926 status = ice_sched_replay_q_bw(pi, q_ctx); 4927 4928 ena_txq_exit: 4929 mutex_unlock(&pi->sched_lock); 4930 return status; 4931 } 4932 4933 /** 4934 * ice_dis_vsi_txq 4935 * @pi: port information structure 4936 * @vsi_handle: software VSI handle 4937 * @tc: TC number 4938 * @num_queues: number of queues 4939 * @q_handles: pointer to software queue handle array 4940 * @q_ids: pointer to the q_id array 4941 * @q_teids: pointer to queue node teids 4942 * @rst_src: if called due to reset, specifies the reset source 4943 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4944 * @cd: pointer to command details structure or NULL 4945 * 4946 * This function removes queues and their corresponding nodes in SW DB 4947 */ 4948 int 4949 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4950 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4951 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4952 struct ice_sq_cd *cd) 4953 { 4954 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 4955 u16 i, buf_size = __struct_size(qg_list); 4956 struct ice_q_ctx *q_ctx; 4957 int status = -ENOENT; 4958 struct ice_hw *hw; 4959 4960 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4961 return -EIO; 4962 4963 hw = pi->hw; 4964 4965 if (!num_queues) { 4966 /* if queue is disabled already yet the disable queue command 4967 * has to be sent to complete the VF reset, then call 4968 * ice_aq_dis_lan_txq without any queue information 4969 */ 4970 if (rst_src) 4971 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4972 vmvf_num, NULL); 4973 return -EIO; 4974 } 4975 4976 mutex_lock(&pi->sched_lock); 4977 4978 for (i = 0; i < num_queues; i++) { 4979 struct ice_sched_node *node; 4980 4981 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4982 if (!node) 4983 continue; 4984 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4985 if (!q_ctx) { 4986 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4987 q_handles[i]); 4988 continue; 4989 } 4990 if (q_ctx->q_handle != q_handles[i]) { 4991 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4992 q_ctx->q_handle, q_handles[i]); 4993 continue; 4994 } 4995 qg_list->parent_teid = node->info.parent_teid; 4996 qg_list->num_qs = 1; 4997 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4998 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4999 vmvf_num, cd); 5000 5001 if (status) 5002 break; 5003 ice_free_sched_node(pi, node); 5004 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5005 q_ctx->q_teid = ICE_INVAL_TEID; 5006 } 5007 mutex_unlock(&pi->sched_lock); 5008 return status; 5009 } 5010 5011 /** 5012 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5013 * @pi: port information structure 5014 * @vsi_handle: software VSI handle 5015 * @tc_bitmap: TC bitmap 5016 * @maxqs: max queues array per TC 5017 * @owner: LAN or RDMA 5018 * 5019 * This function adds/updates the VSI queues per TC. 5020 */ 5021 static int 5022 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5023 u16 *maxqs, u8 owner) 5024 { 5025 int status = 0; 5026 u8 i; 5027 5028 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5029 return -EIO; 5030 5031 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5032 return -EINVAL; 5033 5034 mutex_lock(&pi->sched_lock); 5035 5036 ice_for_each_traffic_class(i) { 5037 /* configuration is possible only if TC node is present */ 5038 if (!ice_sched_get_tc_node(pi, i)) 5039 continue; 5040 5041 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5042 ice_is_tc_ena(tc_bitmap, i)); 5043 if (status) 5044 break; 5045 } 5046 5047 mutex_unlock(&pi->sched_lock); 5048 return status; 5049 } 5050 5051 /** 5052 * ice_cfg_vsi_lan - configure VSI LAN queues 5053 * @pi: port information structure 5054 * @vsi_handle: software VSI handle 5055 * @tc_bitmap: TC bitmap 5056 * @max_lanqs: max LAN queues array per TC 5057 * 5058 * This function adds/updates the VSI LAN queues per TC. 5059 */ 5060 int 5061 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5062 u16 *max_lanqs) 5063 { 5064 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5065 ICE_SCHED_NODE_OWNER_LAN); 5066 } 5067 5068 /** 5069 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5070 * @pi: port information structure 5071 * @vsi_handle: software VSI handle 5072 * @tc_bitmap: TC bitmap 5073 * @max_rdmaqs: max RDMA queues array per TC 5074 * 5075 * This function adds/updates the VSI RDMA queues per TC. 5076 */ 5077 int 5078 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5079 u16 *max_rdmaqs) 5080 { 5081 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5082 ICE_SCHED_NODE_OWNER_RDMA); 5083 } 5084 5085 /** 5086 * ice_ena_vsi_rdma_qset 5087 * @pi: port information structure 5088 * @vsi_handle: software VSI handle 5089 * @tc: TC number 5090 * @rdma_qset: pointer to RDMA Qset 5091 * @num_qsets: number of RDMA Qsets 5092 * @qset_teid: pointer to Qset node TEIDs 5093 * 5094 * This function adds RDMA Qset 5095 */ 5096 int 5097 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5098 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5099 { 5100 struct ice_aqc_txsched_elem_data node = { 0 }; 5101 struct ice_aqc_add_rdma_qset_data *buf; 5102 struct ice_sched_node *parent; 5103 struct ice_hw *hw; 5104 u16 i, buf_size; 5105 int ret; 5106 5107 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5108 return -EIO; 5109 hw = pi->hw; 5110 5111 if (!ice_is_vsi_valid(hw, vsi_handle)) 5112 return -EINVAL; 5113 5114 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5115 buf = kzalloc(buf_size, GFP_KERNEL); 5116 if (!buf) 5117 return -ENOMEM; 5118 mutex_lock(&pi->sched_lock); 5119 5120 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5121 ICE_SCHED_NODE_OWNER_RDMA); 5122 if (!parent) { 5123 ret = -EINVAL; 5124 goto rdma_error_exit; 5125 } 5126 buf->parent_teid = parent->info.node_teid; 5127 node.parent_teid = parent->info.node_teid; 5128 5129 buf->num_qsets = cpu_to_le16(num_qsets); 5130 for (i = 0; i < num_qsets; i++) { 5131 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5132 buf->rdma_qsets[i].info.valid_sections = 5133 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5134 ICE_AQC_ELEM_VALID_EIR; 5135 buf->rdma_qsets[i].info.generic = 0; 5136 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5137 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5138 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5139 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5140 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5141 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5142 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5143 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5144 } 5145 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5146 if (ret) { 5147 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5148 goto rdma_error_exit; 5149 } 5150 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5151 for (i = 0; i < num_qsets; i++) { 5152 node.node_teid = buf->rdma_qsets[i].qset_teid; 5153 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5154 &node, NULL); 5155 if (ret) 5156 break; 5157 qset_teid[i] = le32_to_cpu(node.node_teid); 5158 } 5159 rdma_error_exit: 5160 mutex_unlock(&pi->sched_lock); 5161 kfree(buf); 5162 return ret; 5163 } 5164 5165 /** 5166 * ice_dis_vsi_rdma_qset - free RDMA resources 5167 * @pi: port_info struct 5168 * @count: number of RDMA Qsets to free 5169 * @qset_teid: TEID of Qset node 5170 * @q_id: list of queue IDs being disabled 5171 */ 5172 int 5173 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5174 u16 *q_id) 5175 { 5176 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5177 u16 qg_size = __struct_size(qg_list); 5178 struct ice_hw *hw; 5179 int status = 0; 5180 int i; 5181 5182 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5183 return -EIO; 5184 5185 hw = pi->hw; 5186 5187 mutex_lock(&pi->sched_lock); 5188 5189 for (i = 0; i < count; i++) { 5190 struct ice_sched_node *node; 5191 5192 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5193 if (!node) 5194 continue; 5195 5196 qg_list->parent_teid = node->info.parent_teid; 5197 qg_list->num_qs = 1; 5198 qg_list->q_id[0] = 5199 cpu_to_le16(q_id[i] | 5200 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5201 5202 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5203 ICE_NO_RESET, 0, NULL); 5204 if (status) 5205 break; 5206 5207 ice_free_sched_node(pi, node); 5208 } 5209 5210 mutex_unlock(&pi->sched_lock); 5211 return status; 5212 } 5213 5214 /** 5215 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5216 * @hw: pointer to the HW struct 5217 * @dpll_idx: index of dpll to be measured 5218 * @meas: array to be filled with results 5219 * @meas_num: max number of results array can hold 5220 * 5221 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5222 * pins on given dpll. 5223 * 5224 * Return: 0 on success or negative value on failure. 5225 */ 5226 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5227 struct ice_cgu_input_measure *meas, 5228 u16 meas_num) 5229 { 5230 struct ice_aqc_get_cgu_input_measure *cmd; 5231 struct libie_aq_desc desc; 5232 5233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5234 cmd = libie_aq_raw(&desc); 5235 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5236 5237 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5238 } 5239 5240 /** 5241 * ice_aq_get_cgu_abilities - get cgu abilities 5242 * @hw: pointer to the HW struct 5243 * @abilities: CGU abilities 5244 * 5245 * Get CGU abilities (0x0C61) 5246 * Return: 0 on success or negative value on failure. 5247 */ 5248 int 5249 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5250 struct ice_aqc_get_cgu_abilities *abilities) 5251 { 5252 struct libie_aq_desc desc; 5253 5254 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5255 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5256 } 5257 5258 /** 5259 * ice_aq_set_input_pin_cfg - set input pin config 5260 * @hw: pointer to the HW struct 5261 * @input_idx: Input index 5262 * @flags1: Input flags 5263 * @flags2: Input flags 5264 * @freq: Frequency in Hz 5265 * @phase_delay: Delay in ps 5266 * 5267 * Set CGU input config (0x0C62) 5268 * Return: 0 on success or negative value on failure. 5269 */ 5270 int 5271 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5272 u32 freq, s32 phase_delay) 5273 { 5274 struct ice_aqc_set_cgu_input_config *cmd; 5275 struct libie_aq_desc desc; 5276 5277 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5278 cmd = libie_aq_raw(&desc); 5279 cmd->input_idx = input_idx; 5280 cmd->flags1 = flags1; 5281 cmd->flags2 = flags2; 5282 cmd->freq = cpu_to_le32(freq); 5283 cmd->phase_delay = cpu_to_le32(phase_delay); 5284 5285 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5286 } 5287 5288 /** 5289 * ice_aq_get_input_pin_cfg - get input pin config 5290 * @hw: pointer to the HW struct 5291 * @input_idx: Input index 5292 * @status: Pin status 5293 * @type: Pin type 5294 * @flags1: Input flags 5295 * @flags2: Input flags 5296 * @freq: Frequency in Hz 5297 * @phase_delay: Delay in ps 5298 * 5299 * Get CGU input config (0x0C63) 5300 * Return: 0 on success or negative value on failure. 5301 */ 5302 int 5303 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5304 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5305 { 5306 struct ice_aqc_get_cgu_input_config *cmd; 5307 struct libie_aq_desc desc; 5308 int ret; 5309 5310 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5311 cmd = libie_aq_raw(&desc); 5312 cmd->input_idx = input_idx; 5313 5314 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5315 if (!ret) { 5316 if (status) 5317 *status = cmd->status; 5318 if (type) 5319 *type = cmd->type; 5320 if (flags1) 5321 *flags1 = cmd->flags1; 5322 if (flags2) 5323 *flags2 = cmd->flags2; 5324 if (freq) 5325 *freq = le32_to_cpu(cmd->freq); 5326 if (phase_delay) 5327 *phase_delay = le32_to_cpu(cmd->phase_delay); 5328 } 5329 5330 return ret; 5331 } 5332 5333 /** 5334 * ice_aq_set_output_pin_cfg - set output pin config 5335 * @hw: pointer to the HW struct 5336 * @output_idx: Output index 5337 * @flags: Output flags 5338 * @src_sel: Index of DPLL block 5339 * @freq: Output frequency 5340 * @phase_delay: Output phase compensation 5341 * 5342 * Set CGU output config (0x0C64) 5343 * Return: 0 on success or negative value on failure. 5344 */ 5345 int 5346 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5347 u8 src_sel, u32 freq, s32 phase_delay) 5348 { 5349 struct ice_aqc_set_cgu_output_config *cmd; 5350 struct libie_aq_desc desc; 5351 5352 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5353 cmd = libie_aq_raw(&desc); 5354 cmd->output_idx = output_idx; 5355 cmd->flags = flags; 5356 cmd->src_sel = src_sel; 5357 cmd->freq = cpu_to_le32(freq); 5358 cmd->phase_delay = cpu_to_le32(phase_delay); 5359 5360 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5361 } 5362 5363 /** 5364 * ice_aq_get_output_pin_cfg - get output pin config 5365 * @hw: pointer to the HW struct 5366 * @output_idx: Output index 5367 * @flags: Output flags 5368 * @src_sel: Internal DPLL source 5369 * @freq: Output frequency 5370 * @src_freq: Source frequency 5371 * 5372 * Get CGU output config (0x0C65) 5373 * Return: 0 on success or negative value on failure. 5374 */ 5375 int 5376 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5377 u8 *src_sel, u32 *freq, u32 *src_freq) 5378 { 5379 struct ice_aqc_get_cgu_output_config *cmd; 5380 struct libie_aq_desc desc; 5381 int ret; 5382 5383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5384 cmd = libie_aq_raw(&desc); 5385 cmd->output_idx = output_idx; 5386 5387 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5388 if (!ret) { 5389 if (flags) 5390 *flags = cmd->flags; 5391 if (src_sel) 5392 *src_sel = cmd->src_sel; 5393 if (freq) 5394 *freq = le32_to_cpu(cmd->freq); 5395 if (src_freq) 5396 *src_freq = le32_to_cpu(cmd->src_freq); 5397 } 5398 5399 return ret; 5400 } 5401 5402 /** 5403 * ice_aq_get_cgu_dpll_status - get dpll status 5404 * @hw: pointer to the HW struct 5405 * @dpll_num: DPLL index 5406 * @ref_state: Reference clock state 5407 * @config: current DPLL config 5408 * @dpll_state: current DPLL state 5409 * @phase_offset: Phase offset in ns 5410 * @eec_mode: EEC_mode 5411 * 5412 * Get CGU DPLL status (0x0C66) 5413 * Return: 0 on success or negative value on failure. 5414 */ 5415 int 5416 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5417 u8 *dpll_state, u8 *config, s64 *phase_offset, 5418 u8 *eec_mode) 5419 { 5420 struct ice_aqc_get_cgu_dpll_status *cmd; 5421 struct libie_aq_desc desc; 5422 int status; 5423 5424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5425 cmd = libie_aq_raw(&desc); 5426 cmd->dpll_num = dpll_num; 5427 5428 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5429 if (!status) { 5430 *ref_state = cmd->ref_state; 5431 *dpll_state = cmd->dpll_state; 5432 *config = cmd->config; 5433 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5434 *phase_offset <<= 32; 5435 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5436 *phase_offset = sign_extend64(*phase_offset, 47); 5437 *eec_mode = cmd->eec_mode; 5438 } 5439 5440 return status; 5441 } 5442 5443 /** 5444 * ice_aq_set_cgu_dpll_config - set dpll config 5445 * @hw: pointer to the HW struct 5446 * @dpll_num: DPLL index 5447 * @ref_state: Reference clock state 5448 * @config: DPLL config 5449 * @eec_mode: EEC mode 5450 * 5451 * Set CGU DPLL config (0x0C67) 5452 * Return: 0 on success or negative value on failure. 5453 */ 5454 int 5455 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5456 u8 config, u8 eec_mode) 5457 { 5458 struct ice_aqc_set_cgu_dpll_config *cmd; 5459 struct libie_aq_desc desc; 5460 5461 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5462 cmd = libie_aq_raw(&desc); 5463 cmd->dpll_num = dpll_num; 5464 cmd->ref_state = ref_state; 5465 cmd->config = config; 5466 cmd->eec_mode = eec_mode; 5467 5468 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5469 } 5470 5471 /** 5472 * ice_aq_set_cgu_ref_prio - set input reference priority 5473 * @hw: pointer to the HW struct 5474 * @dpll_num: DPLL index 5475 * @ref_idx: Reference pin index 5476 * @ref_priority: Reference input priority 5477 * 5478 * Set CGU reference priority (0x0C68) 5479 * Return: 0 on success or negative value on failure. 5480 */ 5481 int 5482 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5483 u8 ref_priority) 5484 { 5485 struct ice_aqc_set_cgu_ref_prio *cmd; 5486 struct libie_aq_desc desc; 5487 5488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5489 cmd = libie_aq_raw(&desc); 5490 cmd->dpll_num = dpll_num; 5491 cmd->ref_idx = ref_idx; 5492 cmd->ref_priority = ref_priority; 5493 5494 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5495 } 5496 5497 /** 5498 * ice_aq_get_cgu_ref_prio - get input reference priority 5499 * @hw: pointer to the HW struct 5500 * @dpll_num: DPLL index 5501 * @ref_idx: Reference pin index 5502 * @ref_prio: Reference input priority 5503 * 5504 * Get CGU reference priority (0x0C69) 5505 * Return: 0 on success or negative value on failure. 5506 */ 5507 int 5508 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5509 u8 *ref_prio) 5510 { 5511 struct ice_aqc_get_cgu_ref_prio *cmd; 5512 struct libie_aq_desc desc; 5513 int status; 5514 5515 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5516 cmd = libie_aq_raw(&desc); 5517 cmd->dpll_num = dpll_num; 5518 cmd->ref_idx = ref_idx; 5519 5520 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5521 if (!status) 5522 *ref_prio = cmd->ref_priority; 5523 5524 return status; 5525 } 5526 5527 /** 5528 * ice_aq_get_cgu_info - get cgu info 5529 * @hw: pointer to the HW struct 5530 * @cgu_id: CGU ID 5531 * @cgu_cfg_ver: CGU config version 5532 * @cgu_fw_ver: CGU firmware version 5533 * 5534 * Get CGU info (0x0C6A) 5535 * Return: 0 on success or negative value on failure. 5536 */ 5537 int 5538 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5539 u32 *cgu_fw_ver) 5540 { 5541 struct ice_aqc_get_cgu_info *cmd; 5542 struct libie_aq_desc desc; 5543 int status; 5544 5545 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5546 cmd = libie_aq_raw(&desc); 5547 5548 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5549 if (!status) { 5550 *cgu_id = le32_to_cpu(cmd->cgu_id); 5551 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5552 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5553 } 5554 5555 return status; 5556 } 5557 5558 /** 5559 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5560 * @hw: pointer to the HW struct 5561 * @phy_output: PHY reference clock output pin 5562 * @enable: GPIO state to be applied 5563 * @freq: PHY output frequency 5564 * 5565 * Set phy recovered clock as reference (0x0630) 5566 * Return: 0 on success or negative value on failure. 5567 */ 5568 int 5569 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5570 u32 *freq) 5571 { 5572 struct ice_aqc_set_phy_rec_clk_out *cmd; 5573 struct libie_aq_desc desc; 5574 int status; 5575 5576 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5577 cmd = libie_aq_raw(&desc); 5578 cmd->phy_output = phy_output; 5579 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5580 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5581 cmd->freq = cpu_to_le32(*freq); 5582 5583 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5584 if (!status) 5585 *freq = le32_to_cpu(cmd->freq); 5586 5587 return status; 5588 } 5589 5590 /** 5591 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5592 * @hw: pointer to the HW struct 5593 * @phy_output: PHY reference clock output pin 5594 * @port_num: Port number 5595 * @flags: PHY flags 5596 * @node_handle: PHY output frequency 5597 * 5598 * Get PHY recovered clock output info (0x0631) 5599 * Return: 0 on success or negative value on failure. 5600 */ 5601 int 5602 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5603 u8 *flags, u16 *node_handle) 5604 { 5605 struct ice_aqc_get_phy_rec_clk_out *cmd; 5606 struct libie_aq_desc desc; 5607 int status; 5608 5609 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5610 cmd = libie_aq_raw(&desc); 5611 cmd->phy_output = *phy_output; 5612 5613 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5614 if (!status) { 5615 *phy_output = cmd->phy_output; 5616 if (port_num) 5617 *port_num = cmd->port_num; 5618 if (flags) 5619 *flags = cmd->flags; 5620 if (node_handle) 5621 *node_handle = le16_to_cpu(cmd->node_handle); 5622 } 5623 5624 return status; 5625 } 5626 5627 /** 5628 * ice_aq_get_sensor_reading 5629 * @hw: pointer to the HW struct 5630 * @data: pointer to data to be read from the sensor 5631 * 5632 * Get sensor reading (0x0632) 5633 */ 5634 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5635 struct ice_aqc_get_sensor_reading_resp *data) 5636 { 5637 struct ice_aqc_get_sensor_reading *cmd; 5638 struct libie_aq_desc desc; 5639 int status; 5640 5641 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5642 cmd = libie_aq_raw(&desc); 5643 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5644 #define ICE_INTERNAL_TEMP_SENSOR 0 5645 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5646 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5647 5648 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5649 if (!status) 5650 memcpy(data, &desc.params.raw, 5651 sizeof(*data)); 5652 5653 return status; 5654 } 5655 5656 /** 5657 * ice_replay_pre_init - replay pre initialization 5658 * @hw: pointer to the HW struct 5659 * 5660 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5661 */ 5662 static int ice_replay_pre_init(struct ice_hw *hw) 5663 { 5664 struct ice_switch_info *sw = hw->switch_info; 5665 u8 i; 5666 5667 /* Delete old entries from replay filter list head if there is any */ 5668 ice_rm_all_sw_replay_rule_info(hw); 5669 /* In start of replay, move entries into replay_rules list, it 5670 * will allow adding rules entries back to filt_rules list, 5671 * which is operational list. 5672 */ 5673 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5674 list_replace_init(&sw->recp_list[i].filt_rules, 5675 &sw->recp_list[i].filt_replay_rules); 5676 ice_sched_replay_agg_vsi_preinit(hw); 5677 5678 return 0; 5679 } 5680 5681 /** 5682 * ice_replay_vsi - replay VSI configuration 5683 * @hw: pointer to the HW struct 5684 * @vsi_handle: driver VSI handle 5685 * 5686 * Restore all VSI configuration after reset. It is required to call this 5687 * function with main VSI first. 5688 */ 5689 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5690 { 5691 int status; 5692 5693 if (!ice_is_vsi_valid(hw, vsi_handle)) 5694 return -EINVAL; 5695 5696 /* Replay pre-initialization if there is any */ 5697 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5698 status = ice_replay_pre_init(hw); 5699 if (status) 5700 return status; 5701 } 5702 /* Replay per VSI all RSS configurations */ 5703 status = ice_replay_rss_cfg(hw, vsi_handle); 5704 if (status) 5705 return status; 5706 /* Replay per VSI all filters */ 5707 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5708 if (!status) 5709 status = ice_replay_vsi_agg(hw, vsi_handle); 5710 return status; 5711 } 5712 5713 /** 5714 * ice_replay_post - post replay configuration cleanup 5715 * @hw: pointer to the HW struct 5716 * 5717 * Post replay cleanup. 5718 */ 5719 void ice_replay_post(struct ice_hw *hw) 5720 { 5721 /* Delete old entries from replay filter list head */ 5722 ice_rm_all_sw_replay_rule_info(hw); 5723 ice_sched_replay_agg(hw); 5724 } 5725 5726 /** 5727 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5728 * @hw: ptr to the hardware info 5729 * @reg: offset of 64 bit HW register to read from 5730 * @prev_stat_loaded: bool to specify if previous stats are loaded 5731 * @prev_stat: ptr to previous loaded stat value 5732 * @cur_stat: ptr to current stat value 5733 */ 5734 void 5735 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5736 u64 *prev_stat, u64 *cur_stat) 5737 { 5738 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5739 5740 /* device stats are not reset at PFR, they likely will not be zeroed 5741 * when the driver starts. Thus, save the value from the first read 5742 * without adding to the statistic value so that we report stats which 5743 * count up from zero. 5744 */ 5745 if (!prev_stat_loaded) { 5746 *prev_stat = new_data; 5747 return; 5748 } 5749 5750 /* Calculate the difference between the new and old values, and then 5751 * add it to the software stat value. 5752 */ 5753 if (new_data >= *prev_stat) 5754 *cur_stat += new_data - *prev_stat; 5755 else 5756 /* to manage the potential roll-over */ 5757 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5758 5759 /* Update the previously stored value to prepare for next read */ 5760 *prev_stat = new_data; 5761 } 5762 5763 /** 5764 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5765 * @hw: ptr to the hardware info 5766 * @reg: offset of HW register to read from 5767 * @prev_stat_loaded: bool to specify if previous stats are loaded 5768 * @prev_stat: ptr to previous loaded stat value 5769 * @cur_stat: ptr to current stat value 5770 */ 5771 void 5772 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5773 u64 *prev_stat, u64 *cur_stat) 5774 { 5775 u32 new_data; 5776 5777 new_data = rd32(hw, reg); 5778 5779 /* device stats are not reset at PFR, they likely will not be zeroed 5780 * when the driver starts. Thus, save the value from the first read 5781 * without adding to the statistic value so that we report stats which 5782 * count up from zero. 5783 */ 5784 if (!prev_stat_loaded) { 5785 *prev_stat = new_data; 5786 return; 5787 } 5788 5789 /* Calculate the difference between the new and old values, and then 5790 * add it to the software stat value. 5791 */ 5792 if (new_data >= *prev_stat) 5793 *cur_stat += new_data - *prev_stat; 5794 else 5795 /* to manage the potential roll-over */ 5796 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5797 5798 /* Update the previously stored value to prepare for next read */ 5799 *prev_stat = new_data; 5800 } 5801 5802 /** 5803 * ice_sched_query_elem - query element information from HW 5804 * @hw: pointer to the HW struct 5805 * @node_teid: node TEID to be queried 5806 * @buf: buffer to element information 5807 * 5808 * This function queries HW element information 5809 */ 5810 int 5811 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5812 struct ice_aqc_txsched_elem_data *buf) 5813 { 5814 u16 buf_size, num_elem_ret = 0; 5815 int status; 5816 5817 buf_size = sizeof(*buf); 5818 memset(buf, 0, buf_size); 5819 buf->node_teid = cpu_to_le32(node_teid); 5820 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5821 NULL); 5822 if (status || num_elem_ret != 1) 5823 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5824 return status; 5825 } 5826 5827 /** 5828 * ice_aq_read_i2c 5829 * @hw: pointer to the hw struct 5830 * @topo_addr: topology address for a device to communicate with 5831 * @bus_addr: 7-bit I2C bus address 5832 * @addr: I2C memory address (I2C offset) with up to 16 bits 5833 * @params: I2C parameters: bit [7] - Repeated start, 5834 * bits [6:5] data offset size, 5835 * bit [4] - I2C address type, 5836 * bits [3:0] - data size to read (0-16 bytes) 5837 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5838 * @cd: pointer to command details structure or NULL 5839 * 5840 * Read I2C (0x06E2) 5841 */ 5842 int 5843 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5844 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5845 struct ice_sq_cd *cd) 5846 { 5847 struct libie_aq_desc desc = { 0 }; 5848 struct ice_aqc_i2c *cmd; 5849 u8 data_size; 5850 int status; 5851 5852 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5853 cmd = libie_aq_raw(&desc); 5854 5855 if (!data) 5856 return -EINVAL; 5857 5858 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5859 5860 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5861 cmd->topo_addr = topo_addr; 5862 cmd->i2c_params = params; 5863 cmd->i2c_addr = addr; 5864 5865 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5866 if (!status) { 5867 struct ice_aqc_read_i2c_resp *resp; 5868 u8 i; 5869 5870 resp = libie_aq_raw(&desc); 5871 for (i = 0; i < data_size; i++) { 5872 *data = resp->i2c_data[i]; 5873 data++; 5874 } 5875 } 5876 5877 return status; 5878 } 5879 5880 /** 5881 * ice_aq_write_i2c 5882 * @hw: pointer to the hw struct 5883 * @topo_addr: topology address for a device to communicate with 5884 * @bus_addr: 7-bit I2C bus address 5885 * @addr: I2C memory address (I2C offset) with up to 16 bits 5886 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5887 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5888 * @cd: pointer to command details structure or NULL 5889 * 5890 * Write I2C (0x06E3) 5891 * 5892 * * Return: 5893 * * 0 - Successful write to the i2c device 5894 * * -EINVAL - Data size greater than 4 bytes 5895 * * -EIO - FW error 5896 */ 5897 int 5898 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5899 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5900 struct ice_sq_cd *cd) 5901 { 5902 struct libie_aq_desc desc = { 0 }; 5903 struct ice_aqc_i2c *cmd; 5904 u8 data_size; 5905 5906 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5907 cmd = libie_aq_raw(&desc); 5908 5909 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5910 5911 /* data_size limited to 4 */ 5912 if (data_size > 4) 5913 return -EINVAL; 5914 5915 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5916 cmd->topo_addr = topo_addr; 5917 cmd->i2c_params = params; 5918 cmd->i2c_addr = addr; 5919 5920 memcpy(cmd->i2c_data, data, data_size); 5921 5922 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5923 } 5924 5925 /** 5926 * ice_get_pca9575_handle - find and return the PCA9575 controller 5927 * @hw: pointer to the hw struct 5928 * @pca9575_handle: GPIO controller's handle 5929 * 5930 * Find and return the GPIO controller's handle in the netlist. 5931 * When found - the value will be cached in the hw structure and following calls 5932 * will return cached value. 5933 * 5934 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 5935 */ 5936 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5937 { 5938 struct ice_aqc_get_link_topo *cmd; 5939 struct libie_aq_desc desc; 5940 int err; 5941 u8 idx; 5942 5943 /* If handle was read previously return cached value */ 5944 if (hw->io_expander_handle) { 5945 *pca9575_handle = hw->io_expander_handle; 5946 return 0; 5947 } 5948 5949 #define SW_PCA9575_SFP_TOPO_IDX 2 5950 #define SW_PCA9575_QSFP_TOPO_IDX 1 5951 5952 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5953 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5954 idx = SW_PCA9575_SFP_TOPO_IDX; 5955 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5956 idx = SW_PCA9575_QSFP_TOPO_IDX; 5957 else 5958 return -ENXIO; 5959 5960 /* If handle was not detected read it from the netlist */ 5961 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5962 cmd = libie_aq_raw(&desc); 5963 cmd->addr.topo_params.node_type_ctx = 5964 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5965 cmd->addr.topo_params.index = idx; 5966 5967 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5968 if (err) 5969 return -ENXIO; 5970 5971 /* Verify if we found the right IO expander type */ 5972 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5973 return -ENXIO; 5974 5975 /* If present save the handle and return it */ 5976 hw->io_expander_handle = 5977 le16_to_cpu(cmd->addr.handle); 5978 *pca9575_handle = hw->io_expander_handle; 5979 5980 return 0; 5981 } 5982 5983 /** 5984 * ice_read_pca9575_reg - read the register from the PCA9575 controller 5985 * @hw: pointer to the hw struct 5986 * @offset: GPIO controller register offset 5987 * @data: pointer to data to be read from the GPIO controller 5988 * 5989 * Return: 0 on success, negative error code otherwise. 5990 */ 5991 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5992 { 5993 struct ice_aqc_link_topo_addr link_topo; 5994 __le16 addr; 5995 u16 handle; 5996 int err; 5997 5998 memset(&link_topo, 0, sizeof(link_topo)); 5999 6000 err = ice_get_pca9575_handle(hw, &handle); 6001 if (err) 6002 return err; 6003 6004 link_topo.handle = cpu_to_le16(handle); 6005 link_topo.topo_params.node_type_ctx = 6006 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6007 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6008 6009 addr = cpu_to_le16((u16)offset); 6010 6011 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6012 } 6013 6014 /** 6015 * ice_aq_set_gpio 6016 * @hw: pointer to the hw struct 6017 * @gpio_ctrl_handle: GPIO controller node handle 6018 * @pin_idx: IO Number of the GPIO that needs to be set 6019 * @value: SW provide IO value to set in the LSB 6020 * @cd: pointer to command details structure or NULL 6021 * 6022 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6023 */ 6024 int 6025 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6026 struct ice_sq_cd *cd) 6027 { 6028 struct libie_aq_desc desc; 6029 struct ice_aqc_gpio *cmd; 6030 6031 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6032 cmd = libie_aq_raw(&desc); 6033 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6034 cmd->gpio_num = pin_idx; 6035 cmd->gpio_val = value ? 1 : 0; 6036 6037 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6038 } 6039 6040 /** 6041 * ice_aq_get_gpio 6042 * @hw: pointer to the hw struct 6043 * @gpio_ctrl_handle: GPIO controller node handle 6044 * @pin_idx: IO Number of the GPIO that needs to be set 6045 * @value: IO value read 6046 * @cd: pointer to command details structure or NULL 6047 * 6048 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6049 * the topology 6050 */ 6051 int 6052 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6053 bool *value, struct ice_sq_cd *cd) 6054 { 6055 struct libie_aq_desc desc; 6056 struct ice_aqc_gpio *cmd; 6057 int status; 6058 6059 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6060 cmd = libie_aq_raw(&desc); 6061 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6062 cmd->gpio_num = pin_idx; 6063 6064 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6065 if (status) 6066 return status; 6067 6068 *value = !!cmd->gpio_val; 6069 return 0; 6070 } 6071 6072 /** 6073 * ice_is_fw_api_min_ver 6074 * @hw: pointer to the hardware structure 6075 * @maj: major version 6076 * @min: minor version 6077 * @patch: patch version 6078 * 6079 * Checks if the firmware API is minimum version 6080 */ 6081 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6082 { 6083 if (hw->api_maj_ver == maj) { 6084 if (hw->api_min_ver > min) 6085 return true; 6086 if (hw->api_min_ver == min && hw->api_patch >= patch) 6087 return true; 6088 } else if (hw->api_maj_ver > maj) { 6089 return true; 6090 } 6091 6092 return false; 6093 } 6094 6095 /** 6096 * ice_fw_supports_link_override 6097 * @hw: pointer to the hardware structure 6098 * 6099 * Checks if the firmware supports link override 6100 */ 6101 bool ice_fw_supports_link_override(struct ice_hw *hw) 6102 { 6103 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6104 ICE_FW_API_LINK_OVERRIDE_MIN, 6105 ICE_FW_API_LINK_OVERRIDE_PATCH); 6106 } 6107 6108 /** 6109 * ice_get_link_default_override 6110 * @ldo: pointer to the link default override struct 6111 * @pi: pointer to the port info struct 6112 * 6113 * Gets the link default override for a port 6114 */ 6115 int 6116 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6117 struct ice_port_info *pi) 6118 { 6119 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6120 struct ice_hw *hw = pi->hw; 6121 int status; 6122 6123 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6124 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6125 if (status) { 6126 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6127 return status; 6128 } 6129 6130 /* Each port has its own config; calculate for our port */ 6131 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6132 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6133 6134 /* link options first */ 6135 status = ice_read_sr_word(hw, tlv_start, &buf); 6136 if (status) { 6137 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6138 return status; 6139 } 6140 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6141 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6142 ICE_LINK_OVERRIDE_PHY_CFG_S; 6143 6144 /* link PHY config */ 6145 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6146 status = ice_read_sr_word(hw, offset, &buf); 6147 if (status) { 6148 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6149 return status; 6150 } 6151 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6152 6153 /* PHY types low */ 6154 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6155 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6156 status = ice_read_sr_word(hw, (offset + i), &buf); 6157 if (status) { 6158 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6159 return status; 6160 } 6161 /* shift 16 bits at a time to fill 64 bits */ 6162 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6163 } 6164 6165 /* PHY types high */ 6166 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6167 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6168 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6169 status = ice_read_sr_word(hw, (offset + i), &buf); 6170 if (status) { 6171 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6172 return status; 6173 } 6174 /* shift 16 bits at a time to fill 64 bits */ 6175 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6176 } 6177 6178 return status; 6179 } 6180 6181 /** 6182 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6183 * @caps: get PHY capability data 6184 */ 6185 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6186 { 6187 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6188 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6189 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6190 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6191 return true; 6192 6193 return false; 6194 } 6195 6196 /** 6197 * ice_is_fw_health_report_supported - checks if firmware supports health events 6198 * @hw: pointer to the hardware structure 6199 * 6200 * Return: true if firmware supports health status reports, 6201 * false otherwise 6202 */ 6203 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6204 { 6205 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6206 ICE_FW_API_HEALTH_REPORT_MIN, 6207 ICE_FW_API_HEALTH_REPORT_PATCH); 6208 } 6209 6210 /** 6211 * ice_aq_set_health_status_cfg - Configure FW health events 6212 * @hw: pointer to the HW struct 6213 * @event_source: type of diagnostic events to enable 6214 * 6215 * Configure the health status event types that the firmware will send to this 6216 * PF. The supported event types are: PF-specific, all PFs, and global. 6217 * 6218 * Return: 0 on success, negative error code otherwise. 6219 */ 6220 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6221 { 6222 struct ice_aqc_set_health_status_cfg *cmd; 6223 struct libie_aq_desc desc; 6224 6225 cmd = libie_aq_raw(&desc); 6226 6227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6228 6229 cmd->event_source = event_source; 6230 6231 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6232 } 6233 6234 /** 6235 * ice_aq_set_lldp_mib - Set the LLDP MIB 6236 * @hw: pointer to the HW struct 6237 * @mib_type: Local, Remote or both Local and Remote MIBs 6238 * @buf: pointer to the caller-supplied buffer to store the MIB block 6239 * @buf_size: size of the buffer (in bytes) 6240 * @cd: pointer to command details structure or NULL 6241 * 6242 * Set the LLDP MIB. (0x0A08) 6243 */ 6244 int 6245 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6246 struct ice_sq_cd *cd) 6247 { 6248 struct ice_aqc_lldp_set_local_mib *cmd; 6249 struct libie_aq_desc desc; 6250 6251 cmd = libie_aq_raw(&desc); 6252 6253 if (buf_size == 0 || !buf) 6254 return -EINVAL; 6255 6256 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6257 6258 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6259 desc.datalen = cpu_to_le16(buf_size); 6260 6261 cmd->type = mib_type; 6262 cmd->length = cpu_to_le16(buf_size); 6263 6264 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6265 } 6266 6267 /** 6268 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6269 * @hw: pointer to HW struct 6270 */ 6271 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6272 { 6273 if (hw->mac_type != ICE_MAC_E810) 6274 return false; 6275 6276 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6277 ICE_FW_API_LLDP_FLTR_MIN, 6278 ICE_FW_API_LLDP_FLTR_PATCH); 6279 } 6280 6281 /** 6282 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6283 * @hw: pointer to HW struct 6284 * @vsi: VSI to add the filter to 6285 * @add: boolean for if adding or removing a filter 6286 * 6287 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6288 * with this HW or VSI, otherwise an error corresponding to 6289 * the AQ transaction result. 6290 */ 6291 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6292 { 6293 struct ice_aqc_lldp_filter_ctrl *cmd; 6294 struct libie_aq_desc desc; 6295 6296 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6297 return -EOPNOTSUPP; 6298 6299 cmd = libie_aq_raw(&desc); 6300 6301 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6302 6303 if (add) 6304 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6305 else 6306 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6307 6308 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6309 6310 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6311 } 6312 6313 /** 6314 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6315 * @hw: pointer to HW struct 6316 */ 6317 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6318 { 6319 struct libie_aq_desc desc; 6320 6321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6322 6323 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6324 } 6325 6326 /** 6327 * ice_fw_supports_report_dflt_cfg 6328 * @hw: pointer to the hardware structure 6329 * 6330 * Checks if the firmware supports report default configuration 6331 */ 6332 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6333 { 6334 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6335 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6336 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6337 } 6338 6339 /* each of the indexes into the following array match the speed of a return 6340 * value from the list of AQ returned speeds like the range: 6341 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6342 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6343 * array. The array is defined as 15 elements long because the link_speed 6344 * returned by the firmware is a 16 bit * value, but is indexed 6345 * by [fls(speed) - 1] 6346 */ 6347 static const u32 ice_aq_to_link_speed[] = { 6348 SPEED_10, /* BIT(0) */ 6349 SPEED_100, 6350 SPEED_1000, 6351 SPEED_2500, 6352 SPEED_5000, 6353 SPEED_10000, 6354 SPEED_20000, 6355 SPEED_25000, 6356 SPEED_40000, 6357 SPEED_50000, 6358 SPEED_100000, /* BIT(10) */ 6359 SPEED_200000, 6360 }; 6361 6362 /** 6363 * ice_get_link_speed - get integer speed from table 6364 * @index: array index from fls(aq speed) - 1 6365 * 6366 * Returns: u32 value containing integer speed 6367 */ 6368 u32 ice_get_link_speed(u16 index) 6369 { 6370 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6371 return 0; 6372 6373 return ice_aq_to_link_speed[index]; 6374 } 6375 6376 /** 6377 * ice_read_cgu_reg - Read a CGU register 6378 * @hw: Pointer to the HW struct 6379 * @addr: Register address to read 6380 * @val: Storage for register value read 6381 * 6382 * Read the contents of a register of the Clock Generation Unit. Only 6383 * applicable to E82X devices. 6384 * 6385 * Return: 0 on success, other error codes when failed to read from CGU. 6386 */ 6387 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6388 { 6389 struct ice_sbq_msg_input cgu_msg = { 6390 .opcode = ice_sbq_msg_rd, 6391 .dest_dev = ice_sbq_dev_cgu, 6392 .msg_addr_low = addr 6393 }; 6394 int err; 6395 6396 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6397 if (err) { 6398 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6399 addr, err); 6400 return err; 6401 } 6402 6403 *val = cgu_msg.data; 6404 6405 return 0; 6406 } 6407 6408 /** 6409 * ice_write_cgu_reg - Write a CGU register 6410 * @hw: Pointer to the HW struct 6411 * @addr: Register address to write 6412 * @val: Value to write into the register 6413 * 6414 * Write the specified value to a register of the Clock Generation Unit. Only 6415 * applicable to E82X devices. 6416 * 6417 * Return: 0 on success, other error codes when failed to write to CGU. 6418 */ 6419 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6420 { 6421 struct ice_sbq_msg_input cgu_msg = { 6422 .opcode = ice_sbq_msg_wr, 6423 .dest_dev = ice_sbq_dev_cgu, 6424 .msg_addr_low = addr, 6425 .data = val 6426 }; 6427 int err; 6428 6429 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6430 if (err) 6431 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6432 addr, err); 6433 6434 return err; 6435 } 6436