1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_clear_pf_cfg - Clear PF configuration 208 * @hw: pointer to the hardware structure 209 * 210 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 211 * configuration, flow director filters, etc.). 212 */ 213 int ice_clear_pf_cfg(struct ice_hw *hw) 214 { 215 struct libie_aq_desc desc; 216 217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 218 219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 220 } 221 222 /** 223 * ice_aq_manage_mac_read - manage MAC address read command 224 * @hw: pointer to the HW struct 225 * @buf: a virtual buffer to hold the manage MAC read response 226 * @buf_size: Size of the virtual buffer 227 * @cd: pointer to command details structure or NULL 228 * 229 * This function is used to return per PF station MAC address (0x0107). 230 * NOTE: Upon successful completion of this command, MAC address information 231 * is returned in user specified buffer. Please interpret user specified 232 * buffer as "manage_mac_read" response. 233 * Response such as various MAC addresses are stored in HW struct (port.mac) 234 * ice_discover_dev_caps is expected to be called before this function is 235 * called. 236 */ 237 static int 238 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 239 struct ice_sq_cd *cd) 240 { 241 struct ice_aqc_manage_mac_read_resp *resp; 242 struct ice_aqc_manage_mac_read *cmd; 243 struct libie_aq_desc desc; 244 int status; 245 u16 flags; 246 u8 i; 247 248 cmd = libie_aq_raw(&desc); 249 250 if (buf_size < sizeof(*resp)) 251 return -EINVAL; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 254 255 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 256 if (status) 257 return status; 258 259 resp = buf; 260 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 261 262 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 263 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 264 return -EIO; 265 } 266 267 /* A single port can report up to two (LAN and WoL) addresses */ 268 for (i = 0; i < cmd->num_addr; i++) 269 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 270 ether_addr_copy(hw->port_info->mac.lan_addr, 271 resp[i].mac_addr); 272 ether_addr_copy(hw->port_info->mac.perm_addr, 273 resp[i].mac_addr); 274 break; 275 } 276 277 return 0; 278 } 279 280 /** 281 * ice_aq_get_phy_caps - returns PHY capabilities 282 * @pi: port information structure 283 * @qual_mods: report qualified modules 284 * @report_mode: report mode capabilities 285 * @pcaps: structure for PHY capabilities to be filled 286 * @cd: pointer to command details structure or NULL 287 * 288 * Returns the various PHY capabilities supported on the Port (0x0600) 289 */ 290 int 291 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 292 struct ice_aqc_get_phy_caps_data *pcaps, 293 struct ice_sq_cd *cd) 294 { 295 struct ice_aqc_get_phy_caps *cmd; 296 u16 pcaps_size = sizeof(*pcaps); 297 struct libie_aq_desc desc; 298 const char *prefix; 299 struct ice_hw *hw; 300 int status; 301 302 cmd = libie_aq_raw(&desc); 303 304 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 305 return -EINVAL; 306 hw = pi->hw; 307 308 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 309 !ice_fw_supports_report_dflt_cfg(hw)) 310 return -EINVAL; 311 312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 313 314 if (qual_mods) 315 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 316 317 cmd->param0 |= cpu_to_le16(report_mode); 318 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 319 320 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 321 322 switch (report_mode) { 323 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 324 prefix = "phy_caps_media"; 325 break; 326 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 327 prefix = "phy_caps_no_media"; 328 break; 329 case ICE_AQC_REPORT_ACTIVE_CFG: 330 prefix = "phy_caps_active"; 331 break; 332 case ICE_AQC_REPORT_DFLT_CFG: 333 prefix = "phy_caps_default"; 334 break; 335 default: 336 prefix = "phy_caps_invalid"; 337 } 338 339 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 340 le64_to_cpu(pcaps->phy_type_high), prefix); 341 342 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 343 prefix, report_mode); 344 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 345 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 346 pcaps->low_power_ctrl_an); 347 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 348 pcaps->eee_cap); 349 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 350 pcaps->eeer_value); 351 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 352 pcaps->link_fec_options); 353 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 354 prefix, pcaps->module_compliance_enforcement); 355 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 356 prefix, pcaps->extended_compliance_code); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 358 pcaps->module_type[0]); 359 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 360 pcaps->module_type[1]); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 362 pcaps->module_type[2]); 363 364 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 365 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 366 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 367 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 368 sizeof(pi->phy.link_info.module_type)); 369 } 370 371 return status; 372 } 373 374 /** 375 * ice_aq_get_link_topo_handle - get link topology node return status 376 * @pi: port information structure 377 * @node_type: requested node type 378 * @cd: pointer to command details structure or NULL 379 * 380 * Get link topology node return status for specified node type (0x06E0) 381 * 382 * Node type cage can be used to determine if cage is present. If AQC 383 * returns error (ENOENT), then no cage present. If no cage present, then 384 * connection type is backplane or BASE-T. 385 */ 386 static int 387 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 388 struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_topo *cmd; 391 struct libie_aq_desc desc; 392 393 cmd = libie_aq_raw(&desc); 394 395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 396 397 cmd->addr.topo_params.node_type_ctx = 398 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 399 ICE_AQC_LINK_TOPO_NODE_CTX_S); 400 401 /* set node type */ 402 cmd->addr.topo_params.node_type_ctx |= 403 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 404 405 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 406 } 407 408 /** 409 * ice_aq_get_netlist_node 410 * @hw: pointer to the hw struct 411 * @cmd: get_link_topo AQ structure 412 * @node_part_number: output node part number if node found 413 * @node_handle: output node handle parameter if node found 414 * 415 * Get netlist node handle. 416 */ 417 int 418 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 419 u8 *node_part_number, u16 *node_handle) 420 { 421 struct ice_aqc_get_link_topo *resp; 422 struct libie_aq_desc desc; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 resp = libie_aq_raw(&desc); 426 *resp = *cmd; 427 428 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 429 return -EINTR; 430 431 if (node_handle) 432 *node_handle = le16_to_cpu(resp->addr.handle); 433 if (node_part_number) 434 *node_part_number = resp->node_part_num; 435 436 return 0; 437 } 438 439 /** 440 * ice_find_netlist_node 441 * @hw: pointer to the hw struct 442 * @node_type: type of netlist node to look for 443 * @ctx: context of the search 444 * @node_part_number: node part number to look for 445 * @node_handle: output parameter if node found - optional 446 * 447 * Scan the netlist for a node handle of the given node type and part number. 448 * 449 * If node_handle is non-NULL it will be modified on function exit. It is only 450 * valid if the function returns zero, and should be ignored on any non-zero 451 * return value. 452 * 453 * Return: 454 * * 0 if the node is found, 455 * * -ENOENT if no handle was found, 456 * * negative error code on failure to access the AQ. 457 */ 458 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 459 u8 node_part_number, u16 *node_handle) 460 { 461 u8 idx; 462 463 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 464 struct ice_aqc_get_link_topo cmd = {}; 465 u8 rec_node_part_number; 466 int status; 467 468 cmd.addr.topo_params.node_type_ctx = 469 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 470 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 471 cmd.addr.topo_params.index = idx; 472 473 status = ice_aq_get_netlist_node(hw, &cmd, 474 &rec_node_part_number, 475 node_handle); 476 if (status) 477 return status; 478 479 if (rec_node_part_number == node_part_number) 480 return 0; 481 } 482 483 return -ENOENT; 484 } 485 486 /** 487 * ice_is_media_cage_present 488 * @pi: port information structure 489 * 490 * Returns true if media cage is present, else false. If no cage, then 491 * media type is backplane or BASE-T. 492 */ 493 static bool ice_is_media_cage_present(struct ice_port_info *pi) 494 { 495 /* Node type cage can be used to determine if cage is present. If AQC 496 * returns error (ENOENT), then no cage present. If no cage present then 497 * connection type is backplane or BASE-T. 498 */ 499 return !ice_aq_get_link_topo_handle(pi, 500 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 501 NULL); 502 } 503 504 /** 505 * ice_get_media_type - Gets media type 506 * @pi: port information structure 507 */ 508 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 509 { 510 struct ice_link_status *hw_link_info; 511 512 if (!pi) 513 return ICE_MEDIA_UNKNOWN; 514 515 hw_link_info = &pi->phy.link_info; 516 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 517 /* If more than one media type is selected, report unknown */ 518 return ICE_MEDIA_UNKNOWN; 519 520 if (hw_link_info->phy_type_low) { 521 /* 1G SGMII is a special case where some DA cable PHYs 522 * may show this as an option when it really shouldn't 523 * be since SGMII is meant to be between a MAC and a PHY 524 * in a backplane. Try to detect this case and handle it 525 */ 526 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 527 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 528 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 529 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 530 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 531 return ICE_MEDIA_DA; 532 533 switch (hw_link_info->phy_type_low) { 534 case ICE_PHY_TYPE_LOW_1000BASE_SX: 535 case ICE_PHY_TYPE_LOW_1000BASE_LX: 536 case ICE_PHY_TYPE_LOW_10GBASE_SR: 537 case ICE_PHY_TYPE_LOW_10GBASE_LR: 538 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 539 case ICE_PHY_TYPE_LOW_25GBASE_SR: 540 case ICE_PHY_TYPE_LOW_25GBASE_LR: 541 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 542 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 543 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 544 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 545 case ICE_PHY_TYPE_LOW_50GBASE_SR: 546 case ICE_PHY_TYPE_LOW_50GBASE_FR: 547 case ICE_PHY_TYPE_LOW_50GBASE_LR: 548 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 549 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 550 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_DR: 552 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 553 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 554 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 555 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 556 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 557 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 558 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 559 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 560 return ICE_MEDIA_FIBER; 561 case ICE_PHY_TYPE_LOW_100BASE_TX: 562 case ICE_PHY_TYPE_LOW_1000BASE_T: 563 case ICE_PHY_TYPE_LOW_2500BASE_T: 564 case ICE_PHY_TYPE_LOW_5GBASE_T: 565 case ICE_PHY_TYPE_LOW_10GBASE_T: 566 case ICE_PHY_TYPE_LOW_25GBASE_T: 567 return ICE_MEDIA_BASET; 568 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 569 case ICE_PHY_TYPE_LOW_25GBASE_CR: 570 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 571 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 572 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 573 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 574 case ICE_PHY_TYPE_LOW_50GBASE_CP: 575 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 577 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 578 return ICE_MEDIA_DA; 579 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2: 582 case ICE_PHY_TYPE_LOW_50G_AUI2: 583 case ICE_PHY_TYPE_LOW_50G_AUI1: 584 case ICE_PHY_TYPE_LOW_100G_AUI4: 585 case ICE_PHY_TYPE_LOW_100G_CAUI4: 586 if (ice_is_media_cage_present(pi)) 587 return ICE_MEDIA_DA; 588 fallthrough; 589 case ICE_PHY_TYPE_LOW_1000BASE_KX: 590 case ICE_PHY_TYPE_LOW_2500BASE_KX: 591 case ICE_PHY_TYPE_LOW_2500BASE_X: 592 case ICE_PHY_TYPE_LOW_5GBASE_KR: 593 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 594 case ICE_PHY_TYPE_LOW_25GBASE_KR: 595 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 596 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 597 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 599 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 600 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 601 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 602 return ICE_MEDIA_BACKPLANE; 603 } 604 } else { 605 switch (hw_link_info->phy_type_high) { 606 case ICE_PHY_TYPE_HIGH_100G_AUI2: 607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 608 if (ice_is_media_cage_present(pi)) 609 return ICE_MEDIA_DA; 610 fallthrough; 611 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 612 return ICE_MEDIA_BACKPLANE; 613 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 614 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 615 return ICE_MEDIA_FIBER; 616 } 617 } 618 return ICE_MEDIA_UNKNOWN; 619 } 620 621 /** 622 * ice_get_link_status_datalen 623 * @hw: pointer to the HW struct 624 * 625 * Returns datalength for the Get Link Status AQ command, which is bigger for 626 * newer adapter families handled by ice driver. 627 */ 628 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 629 { 630 switch (hw->mac_type) { 631 case ICE_MAC_E830: 632 return ICE_AQC_LS_DATA_SIZE_V2; 633 case ICE_MAC_E810: 634 default: 635 return ICE_AQC_LS_DATA_SIZE_V1; 636 } 637 } 638 639 /** 640 * ice_aq_get_link_info 641 * @pi: port information structure 642 * @ena_lse: enable/disable LinkStatusEvent reporting 643 * @link: pointer to link status structure - optional 644 * @cd: pointer to command details structure or NULL 645 * 646 * Get Link Status (0x607). Returns the link status of the adapter. 647 */ 648 int 649 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 650 struct ice_link_status *link, struct ice_sq_cd *cd) 651 { 652 struct ice_aqc_get_link_status_data link_data = { 0 }; 653 struct ice_aqc_get_link_status *resp; 654 struct ice_link_status *li_old, *li; 655 enum ice_media_type *hw_media_type; 656 struct ice_fc_info *hw_fc_info; 657 struct libie_aq_desc desc; 658 bool tx_pause, rx_pause; 659 struct ice_hw *hw; 660 u16 cmd_flags; 661 int status; 662 663 if (!pi) 664 return -EINVAL; 665 hw = pi->hw; 666 li_old = &pi->phy.link_info_old; 667 hw_media_type = &pi->phy.media_type; 668 li = &pi->phy.link_info; 669 hw_fc_info = &pi->fc; 670 671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 672 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 673 resp = libie_aq_raw(&desc); 674 resp->cmd_flags = cpu_to_le16(cmd_flags); 675 resp->lport_num = pi->lport; 676 677 status = ice_aq_send_cmd(hw, &desc, &link_data, 678 ice_get_link_status_datalen(hw), cd); 679 if (status) 680 return status; 681 682 /* save off old link status information */ 683 *li_old = *li; 684 685 /* update current link status information */ 686 li->link_speed = le16_to_cpu(link_data.link_speed); 687 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 688 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 689 *hw_media_type = ice_get_media_type(pi); 690 li->link_info = link_data.link_info; 691 li->link_cfg_err = link_data.link_cfg_err; 692 li->an_info = link_data.an_info; 693 li->ext_info = link_data.ext_info; 694 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 695 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 696 li->topo_media_conflict = link_data.topo_media_conflict; 697 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 698 ICE_AQ_CFG_PACING_TYPE_M); 699 700 /* update fc info */ 701 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 702 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 703 if (tx_pause && rx_pause) 704 hw_fc_info->current_mode = ICE_FC_FULL; 705 else if (tx_pause) 706 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 707 else if (rx_pause) 708 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 709 else 710 hw_fc_info->current_mode = ICE_FC_NONE; 711 712 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 713 714 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 715 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 716 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 717 (unsigned long long)li->phy_type_low); 718 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 719 (unsigned long long)li->phy_type_high); 720 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 721 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 722 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 723 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 724 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 725 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 726 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 727 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 728 li->max_frame_size); 729 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 730 731 /* save link status information */ 732 if (link) 733 *link = *li; 734 735 /* flag cleared so calling functions don't call AQ again */ 736 pi->phy.get_link_info = false; 737 738 return 0; 739 } 740 741 /** 742 * ice_fill_tx_timer_and_fc_thresh 743 * @hw: pointer to the HW struct 744 * @cmd: pointer to MAC cfg structure 745 * 746 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 747 * descriptor 748 */ 749 static void 750 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 751 struct ice_aqc_set_mac_cfg *cmd) 752 { 753 u32 val, fc_thres_m; 754 755 /* We read back the transmit timer and FC threshold value of 756 * LFC. Thus, we will use index = 757 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 758 * 759 * Also, because we are operating on transmit timer and FC 760 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 761 */ 762 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 763 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 764 765 if (hw->mac_type == ICE_MAC_E830) { 766 /* Retrieve the transmit timer */ 767 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 768 cmd->tx_tmr_value = 769 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 770 771 /* Retrieve the fc threshold */ 772 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 773 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 774 } else { 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, 777 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 778 cmd->tx_tmr_value = 779 le16_encode_bits(val, 780 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 781 782 /* Retrieve the fc threshold */ 783 val = rd32(hw, 784 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 785 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 786 } 787 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 788 } 789 790 /** 791 * ice_aq_set_mac_cfg 792 * @hw: pointer to the HW struct 793 * @max_frame_size: Maximum Frame Size to be supported 794 * @cd: pointer to command details structure or NULL 795 * 796 * Set MAC configuration (0x0603) 797 */ 798 int 799 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 800 { 801 struct ice_aqc_set_mac_cfg *cmd; 802 struct libie_aq_desc desc; 803 804 cmd = libie_aq_raw(&desc); 805 806 if (max_frame_size == 0) 807 return -EINVAL; 808 809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 810 811 cmd->max_frame_size = cpu_to_le16(max_frame_size); 812 813 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 814 815 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 816 } 817 818 /** 819 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 820 * @hw: pointer to the HW struct 821 */ 822 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 823 { 824 struct ice_switch_info *sw; 825 int status; 826 827 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 828 sizeof(*hw->switch_info), GFP_KERNEL); 829 sw = hw->switch_info; 830 831 if (!sw) 832 return -ENOMEM; 833 834 INIT_LIST_HEAD(&sw->vsi_list_map_head); 835 sw->prof_res_bm_init = 0; 836 837 /* Initialize recipe count with default recipes read from NVM */ 838 sw->recp_cnt = ICE_SW_LKUP_LAST; 839 840 status = ice_init_def_sw_recp(hw); 841 if (status) { 842 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 843 return status; 844 } 845 return 0; 846 } 847 848 /** 849 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 850 * @hw: pointer to the HW struct 851 */ 852 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 853 { 854 struct ice_switch_info *sw = hw->switch_info; 855 struct ice_vsi_list_map_info *v_pos_map; 856 struct ice_vsi_list_map_info *v_tmp_map; 857 struct ice_sw_recipe *recps; 858 u8 i; 859 860 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 861 list_entry) { 862 list_del(&v_pos_map->list_entry); 863 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 864 } 865 recps = sw->recp_list; 866 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 867 recps[i].root_rid = i; 868 869 if (recps[i].adv_rule) { 870 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 871 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 872 873 mutex_destroy(&recps[i].filt_rule_lock); 874 list_for_each_entry_safe(lst_itr, tmp_entry, 875 &recps[i].filt_rules, 876 list_entry) { 877 list_del(&lst_itr->list_entry); 878 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 879 devm_kfree(ice_hw_to_dev(hw), lst_itr); 880 } 881 } else { 882 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 883 884 mutex_destroy(&recps[i].filt_rule_lock); 885 list_for_each_entry_safe(lst_itr, tmp_entry, 886 &recps[i].filt_rules, 887 list_entry) { 888 list_del(&lst_itr->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), lst_itr); 890 } 891 } 892 } 893 ice_rm_all_sw_replay_rule_info(hw); 894 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 895 devm_kfree(ice_hw_to_dev(hw), sw); 896 } 897 898 /** 899 * ice_get_itr_intrl_gran 900 * @hw: pointer to the HW struct 901 * 902 * Determines the ITR/INTRL granularities based on the maximum aggregate 903 * bandwidth according to the device's configuration during power-on. 904 */ 905 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 906 { 907 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 908 rd32(hw, GL_PWR_MODE_CTL)); 909 910 switch (max_agg_bw) { 911 case ICE_MAX_AGG_BW_200G: 912 case ICE_MAX_AGG_BW_100G: 913 case ICE_MAX_AGG_BW_50G: 914 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 915 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 916 break; 917 case ICE_MAX_AGG_BW_25G: 918 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 919 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 920 break; 921 } 922 } 923 924 /** 925 * ice_wait_fw_load - wait for PHY firmware loading to complete 926 * @hw: pointer to the hardware structure 927 * @timeout: milliseconds that can elapse before timing out, 0 to bypass waiting 928 * 929 * Return: 930 * * 0 on success 931 * * negative on timeout 932 */ 933 static int ice_wait_fw_load(struct ice_hw *hw, u32 timeout) 934 { 935 int fw_loading_reg; 936 937 if (!timeout) 938 return 0; 939 940 fw_loading_reg = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 941 /* notify the user only once if PHY FW is still loading */ 942 if (fw_loading_reg) 943 dev_info(ice_hw_to_dev(hw), "Link initialization is blocked by PHY FW initialization. Link initialization will continue after PHY FW initialization completes.\n"); 944 else 945 return 0; 946 947 return rd32_poll_timeout(hw, GL_MNG_FWSM, fw_loading_reg, 948 !(fw_loading_reg & GL_MNG_FWSM_FW_LOADING_M), 949 10000, timeout * 1000); 950 } 951 952 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 953 u16 size) 954 { 955 struct ice_hw *hw = priv; 956 957 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 958 } 959 960 static int __fwlog_init(struct ice_hw *hw) 961 { 962 struct ice_pf *pf = hw->back; 963 struct libie_fwlog_api api = { 964 .pdev = pf->pdev, 965 .send_cmd = __fwlog_send_cmd, 966 .priv = hw, 967 }; 968 int err; 969 970 /* only support fw log commands on PF 0 */ 971 if (hw->bus.func) 972 return -EINVAL; 973 974 err = ice_debugfs_pf_init(pf); 975 if (err) 976 return err; 977 978 api.debugfs_root = pf->ice_debugfs_pf; 979 980 return libie_fwlog_init(&hw->fwlog, &api); 981 } 982 983 /** 984 * ice_init_hw - main hardware initialization routine 985 * @hw: pointer to the hardware structure 986 */ 987 int ice_init_hw(struct ice_hw *hw) 988 { 989 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 990 void *mac_buf __free(kfree) = NULL; 991 u16 mac_buf_len; 992 int status; 993 994 /* Set MAC type based on DeviceID */ 995 status = ice_set_mac_type(hw); 996 if (status) 997 return status; 998 999 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1000 1001 status = ice_reset(hw, ICE_RESET_PFR); 1002 if (status) 1003 return status; 1004 1005 ice_get_itr_intrl_gran(hw); 1006 1007 status = ice_create_all_ctrlq(hw); 1008 if (status) 1009 goto err_unroll_cqinit; 1010 1011 status = __fwlog_init(hw); 1012 if (status) 1013 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1014 status); 1015 1016 status = ice_clear_pf_cfg(hw); 1017 if (status) 1018 goto err_unroll_cqinit; 1019 1020 /* Set bit to enable Flow Director filters */ 1021 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1022 INIT_LIST_HEAD(&hw->fdir_list_head); 1023 1024 ice_clear_pxe_mode(hw); 1025 1026 status = ice_init_nvm(hw); 1027 if (status) 1028 goto err_unroll_cqinit; 1029 1030 status = ice_get_caps(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 if (!hw->port_info) 1035 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1036 sizeof(*hw->port_info), 1037 GFP_KERNEL); 1038 if (!hw->port_info) { 1039 status = -ENOMEM; 1040 goto err_unroll_cqinit; 1041 } 1042 1043 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1044 /* set the back pointer to HW */ 1045 hw->port_info->hw = hw; 1046 1047 /* Initialize port_info struct with switch configuration data */ 1048 status = ice_get_initial_sw_cfg(hw); 1049 if (status) 1050 goto err_unroll_alloc; 1051 1052 hw->evb_veb = true; 1053 1054 /* init xarray for identifying scheduling nodes uniquely */ 1055 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1056 1057 /* Query the allocated resources for Tx scheduler */ 1058 status = ice_sched_query_res_alloc(hw); 1059 if (status) { 1060 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1061 goto err_unroll_alloc; 1062 } 1063 ice_sched_get_psm_clk_freq(hw); 1064 1065 /* Initialize port_info struct with scheduler data */ 1066 status = ice_sched_init_port(hw->port_info); 1067 if (status) 1068 goto err_unroll_sched; 1069 1070 pcaps = kzalloc_obj(*pcaps); 1071 if (!pcaps) { 1072 status = -ENOMEM; 1073 goto err_unroll_sched; 1074 } 1075 1076 /* Initialize port_info struct with PHY capabilities */ 1077 status = ice_aq_get_phy_caps(hw->port_info, false, 1078 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1079 NULL); 1080 if (status) 1081 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1082 status); 1083 1084 /* Initialize port_info struct with link information */ 1085 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1086 if (status) 1087 goto err_unroll_sched; 1088 1089 /* need a valid SW entry point to build a Tx tree */ 1090 if (!hw->sw_entry_point_layer) { 1091 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1092 status = -EIO; 1093 goto err_unroll_sched; 1094 } 1095 INIT_LIST_HEAD(&hw->agg_list); 1096 /* Initialize max burst size */ 1097 if (!hw->max_burst_size) 1098 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1099 1100 status = ice_init_fltr_mgmt_struct(hw); 1101 if (status) 1102 goto err_unroll_sched; 1103 1104 /* Get MAC information */ 1105 /* A single port can report up to two (LAN and WoL) addresses */ 1106 mac_buf = kzalloc_objs(struct ice_aqc_manage_mac_read_resp, 2); 1107 if (!mac_buf) { 1108 status = -ENOMEM; 1109 goto err_unroll_fltr_mgmt_struct; 1110 } 1111 1112 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1113 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1114 1115 if (status) 1116 goto err_unroll_fltr_mgmt_struct; 1117 /* enable jumbo frame support at MAC level */ 1118 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1119 if (status) 1120 goto err_unroll_fltr_mgmt_struct; 1121 /* Obtain counter base index which would be used by flow director */ 1122 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1123 if (status) 1124 goto err_unroll_fltr_mgmt_struct; 1125 status = ice_init_hw_tbls(hw); 1126 if (status) 1127 goto err_unroll_fltr_mgmt_struct; 1128 1129 ice_init_dev_hw(hw->back); 1130 1131 mutex_init(&hw->tnl_lock); 1132 ice_init_chk_recipe_reuse_support(hw); 1133 1134 /* Some cards require longer initialization times 1135 * due to necessity of loading FW from an external source. 1136 * This can take even half a minute. 1137 */ 1138 status = ice_wait_fw_load(hw, 30000); 1139 if (status) { 1140 dev_err(ice_hw_to_dev(hw), "ice_wait_fw_load timed out"); 1141 goto err_unroll_fltr_mgmt_struct; 1142 } 1143 1144 hw->lane_num = ice_get_phy_lane_number(hw); 1145 1146 return 0; 1147 err_unroll_fltr_mgmt_struct: 1148 ice_cleanup_fltr_mgmt_struct(hw); 1149 err_unroll_sched: 1150 ice_sched_cleanup_all(hw); 1151 err_unroll_alloc: 1152 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1153 err_unroll_cqinit: 1154 ice_destroy_all_ctrlq(hw); 1155 return status; 1156 } 1157 1158 static void __fwlog_deinit(struct ice_hw *hw) 1159 { 1160 /* only support fw log commands on PF 0 */ 1161 if (hw->bus.func) 1162 return; 1163 1164 ice_debugfs_pf_deinit(hw->back); 1165 libie_fwlog_deinit(&hw->fwlog); 1166 } 1167 1168 /** 1169 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1170 * @hw: pointer to the hardware structure 1171 * 1172 * This should be called only during nominal operation, not as a result of 1173 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1174 * applicable initializations if it fails for any reason. 1175 */ 1176 void ice_deinit_hw(struct ice_hw *hw) 1177 { 1178 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1179 ice_cleanup_fltr_mgmt_struct(hw); 1180 1181 ice_sched_cleanup_all(hw); 1182 ice_sched_clear_agg(hw); 1183 ice_free_seg(hw); 1184 ice_free_hw_tbls(hw); 1185 mutex_destroy(&hw->tnl_lock); 1186 __fwlog_deinit(hw); 1187 ice_destroy_all_ctrlq(hw); 1188 1189 /* Clear VSI contexts if not already cleared */ 1190 ice_clear_all_vsi_ctx(hw); 1191 } 1192 1193 /** 1194 * ice_check_reset - Check to see if a global reset is complete 1195 * @hw: pointer to the hardware structure 1196 */ 1197 int ice_check_reset(struct ice_hw *hw) 1198 { 1199 u32 cnt, reg = 0, grst_timeout, uld_mask; 1200 1201 /* Poll for Device Active state in case a recent CORER, GLOBR, 1202 * or EMPR has occurred. The grst delay value is in 100ms units. 1203 * Add 1sec for outstanding AQ commands that can take a long time. 1204 */ 1205 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1206 rd32(hw, GLGEN_RSTCTL)) + 10; 1207 1208 for (cnt = 0; cnt < grst_timeout; cnt++) { 1209 mdelay(100); 1210 reg = rd32(hw, GLGEN_RSTAT); 1211 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1212 break; 1213 } 1214 1215 if (cnt == grst_timeout) { 1216 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1217 return -EIO; 1218 } 1219 1220 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1221 GLNVM_ULD_PCIER_DONE_1_M |\ 1222 GLNVM_ULD_CORER_DONE_M |\ 1223 GLNVM_ULD_GLOBR_DONE_M |\ 1224 GLNVM_ULD_POR_DONE_M |\ 1225 GLNVM_ULD_POR_DONE_1_M |\ 1226 GLNVM_ULD_PCIER_DONE_2_M) 1227 1228 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1229 GLNVM_ULD_PE_DONE_M : 0); 1230 1231 /* Device is Active; check Global Reset processes are done */ 1232 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1233 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1234 if (reg == uld_mask) { 1235 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1236 break; 1237 } 1238 mdelay(10); 1239 } 1240 1241 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1242 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1243 reg); 1244 return -EIO; 1245 } 1246 1247 return 0; 1248 } 1249 1250 /** 1251 * ice_pf_reset - Reset the PF 1252 * @hw: pointer to the hardware structure 1253 * 1254 * If a global reset has been triggered, this function checks 1255 * for its completion and then issues the PF reset 1256 */ 1257 static int ice_pf_reset(struct ice_hw *hw) 1258 { 1259 u32 cnt, reg; 1260 1261 /* If at function entry a global reset was already in progress, i.e. 1262 * state is not 'device active' or any of the reset done bits are not 1263 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1264 * global reset is done. 1265 */ 1266 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1267 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1268 /* poll on global reset currently in progress until done */ 1269 if (ice_check_reset(hw)) 1270 return -EIO; 1271 1272 return 0; 1273 } 1274 1275 /* Reset the PF */ 1276 reg = rd32(hw, PFGEN_CTRL); 1277 1278 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1279 1280 /* Wait for the PFR to complete. The wait time is the global config lock 1281 * timeout plus the PFR timeout which will account for a possible reset 1282 * that is occurring during a download package operation. 1283 */ 1284 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1285 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1286 reg = rd32(hw, PFGEN_CTRL); 1287 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1288 break; 1289 1290 mdelay(1); 1291 } 1292 1293 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1294 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1295 return -EIO; 1296 } 1297 1298 return 0; 1299 } 1300 1301 /** 1302 * ice_reset - Perform different types of reset 1303 * @hw: pointer to the hardware structure 1304 * @req: reset request 1305 * 1306 * This function triggers a reset as specified by the req parameter. 1307 * 1308 * Note: 1309 * If anything other than a PF reset is triggered, PXE mode is restored. 1310 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1311 * interface has been restored in the rebuild flow. 1312 */ 1313 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1314 { 1315 u32 val = 0; 1316 1317 switch (req) { 1318 case ICE_RESET_PFR: 1319 return ice_pf_reset(hw); 1320 case ICE_RESET_CORER: 1321 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1322 val = GLGEN_RTRIG_CORER_M; 1323 break; 1324 case ICE_RESET_GLOBR: 1325 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1326 val = GLGEN_RTRIG_GLOBR_M; 1327 break; 1328 default: 1329 return -EINVAL; 1330 } 1331 1332 val |= rd32(hw, GLGEN_RTRIG); 1333 wr32(hw, GLGEN_RTRIG, val); 1334 ice_flush(hw); 1335 1336 /* wait for the FW to be ready */ 1337 return ice_check_reset(hw); 1338 } 1339 1340 /** 1341 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1342 * @hw: pointer to the hardware structure 1343 * @rxq_ctx: pointer to the packed Rx queue context 1344 * @rxq_index: the index of the Rx queue 1345 */ 1346 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1347 const ice_rxq_ctx_buf_t *rxq_ctx, 1348 u32 rxq_index) 1349 { 1350 /* Copy each dword separately to HW */ 1351 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1352 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1353 1354 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1355 1356 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1357 } 1358 } 1359 1360 /** 1361 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1362 * @hw: pointer to the hardware structure 1363 * @rxq_ctx: pointer to the packed Rx queue context 1364 * @rxq_index: the index of the Rx queue 1365 */ 1366 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1367 ice_rxq_ctx_buf_t *rxq_ctx, 1368 u32 rxq_index) 1369 { 1370 u32 *ctx = (u32 *)rxq_ctx; 1371 1372 /* Copy each dword separately from HW */ 1373 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1374 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1375 1376 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1377 } 1378 } 1379 1380 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1381 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1382 1383 /* LAN Rx Queue Context */ 1384 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1385 /* Field Width LSB */ 1386 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1387 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1388 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1389 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1390 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1391 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1392 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1393 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1394 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1395 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1396 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1397 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1398 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1399 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1400 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1401 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1402 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1403 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1404 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1405 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1406 }; 1407 1408 /** 1409 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1410 * @ctx: the Rx queue context to pack 1411 * @buf: the HW buffer to pack into 1412 * 1413 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1414 * bit-packed HW layout. 1415 */ 1416 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1417 ice_rxq_ctx_buf_t *buf) 1418 { 1419 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1420 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1421 } 1422 1423 /** 1424 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1425 * @buf: the HW buffer to unpack from 1426 * @ctx: the Rx queue context to unpack 1427 * 1428 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1429 * structure. 1430 */ 1431 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1432 struct ice_rlan_ctx *ctx) 1433 { 1434 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1435 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1436 } 1437 1438 /** 1439 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1440 * @hw: pointer to the hardware structure 1441 * @rlan_ctx: pointer to the unpacked Rx queue context 1442 * @rxq_index: the index of the Rx queue 1443 * 1444 * Pack the sparse Rx Queue context into dense hardware format and write it 1445 * into the HW register space. 1446 * 1447 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1448 */ 1449 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1450 u32 rxq_index) 1451 { 1452 ice_rxq_ctx_buf_t buf = {}; 1453 1454 if (rxq_index > QRX_CTRL_MAX_INDEX) 1455 return -EINVAL; 1456 1457 ice_pack_rxq_ctx(rlan_ctx, &buf); 1458 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1459 1460 return 0; 1461 } 1462 1463 /** 1464 * ice_read_rxq_ctx - Read Rx queue context from HW 1465 * @hw: pointer to the hardware structure 1466 * @rlan_ctx: pointer to the Rx queue context 1467 * @rxq_index: the index of the Rx queue 1468 * 1469 * Read the Rx queue context from the hardware registers, and unpack it into 1470 * the sparse Rx queue context structure. 1471 * 1472 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1473 */ 1474 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1475 u32 rxq_index) 1476 { 1477 ice_rxq_ctx_buf_t buf = {}; 1478 1479 if (rxq_index > QRX_CTRL_MAX_INDEX) 1480 return -EINVAL; 1481 1482 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1483 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1484 1485 return 0; 1486 } 1487 1488 /* LAN Tx Queue Context */ 1489 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1490 /* Field Width LSB */ 1491 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1492 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1493 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1494 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1495 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1496 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1497 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1498 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1499 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1500 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1501 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1502 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1503 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1504 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1505 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1506 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1507 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1508 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1509 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1510 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1511 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1512 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1513 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1514 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1515 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1516 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1517 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1518 }; 1519 1520 /** 1521 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1522 * @ctx: the Tx queue context to pack 1523 * @buf: the Admin Queue HW buffer to pack into 1524 * 1525 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1526 * bit-packed Admin Queue layout. 1527 */ 1528 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1529 { 1530 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1531 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1532 } 1533 1534 /** 1535 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1536 * @ctx: the Tx queue context to pack 1537 * @buf: the HW buffer to pack into 1538 * 1539 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1540 * bit-packed HW layout, including the internal data portion. 1541 */ 1542 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1543 ice_txq_ctx_buf_full_t *buf) 1544 { 1545 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1546 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1547 } 1548 1549 /** 1550 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1551 * @buf: the HW buffer to unpack from 1552 * @ctx: the Tx queue context to unpack 1553 * 1554 * Unpack the Tx queue context from the HW buffer (including the full internal 1555 * state) into the CPU-friendly structure. 1556 */ 1557 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1558 struct ice_tlan_ctx *ctx) 1559 { 1560 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1561 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1562 } 1563 1564 /** 1565 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1566 * @hw: pointer to the hardware structure 1567 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1568 * @txq_index: the index of the Tx queue 1569 * 1570 * Copy Tx Queue context from HW register space to dense structure 1571 */ 1572 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1573 ice_txq_ctx_buf_full_t *txq_ctx, 1574 u32 txq_index) 1575 { 1576 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1577 u32 *ctx = (u32 *)txq_ctx; 1578 u32 txq_base, reg; 1579 1580 /* Get Tx queue base within card space */ 1581 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1582 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1583 1584 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1585 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1586 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1587 txq_base + txq_index) | 1588 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1589 1590 /* Prevent other PFs on the same adapter from accessing the Tx queue 1591 * context interface concurrently. 1592 */ 1593 spin_lock(&pf->adapter->txq_ctx_lock); 1594 1595 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1596 ice_flush(hw); 1597 1598 /* Copy each dword separately from HW */ 1599 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1600 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1601 1602 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1603 } 1604 1605 spin_unlock(&pf->adapter->txq_ctx_lock); 1606 } 1607 1608 /** 1609 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1610 * @hw: pointer to the hardware structure 1611 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1612 * @txq_index: the index of the Tx queue 1613 */ 1614 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1615 const ice_txq_ctx_buf_full_t *txq_ctx, 1616 u32 txq_index) 1617 { 1618 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1619 u32 txq_base, reg; 1620 1621 /* Get Tx queue base within card space */ 1622 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1623 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1624 1625 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1626 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1627 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1628 txq_base + txq_index) | 1629 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1630 1631 /* Prevent other PFs on the same adapter from accessing the Tx queue 1632 * context interface concurrently. 1633 */ 1634 spin_lock(&pf->adapter->txq_ctx_lock); 1635 1636 /* Copy each dword separately to HW */ 1637 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1638 u32 ctx = ((const u32 *)txq_ctx)[i]; 1639 1640 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1641 1642 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1643 } 1644 1645 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1646 ice_flush(hw); 1647 1648 spin_unlock(&pf->adapter->txq_ctx_lock); 1649 } 1650 1651 /** 1652 * ice_read_txq_ctx - Read Tx queue context from HW 1653 * @hw: pointer to the hardware structure 1654 * @tlan_ctx: pointer to the Tx queue context 1655 * @txq_index: the index of the Tx queue 1656 * 1657 * Read the Tx queue context from the HW registers, then unpack it into the 1658 * ice_tlan_ctx structure for use. 1659 * 1660 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1661 */ 1662 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1663 u32 txq_index) 1664 { 1665 ice_txq_ctx_buf_full_t buf = {}; 1666 1667 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1668 return -EINVAL; 1669 1670 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1671 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1672 1673 return 0; 1674 } 1675 1676 /** 1677 * ice_write_txq_ctx - Write Tx queue context to HW 1678 * @hw: pointer to the hardware structure 1679 * @tlan_ctx: pointer to the Tx queue context 1680 * @txq_index: the index of the Tx queue 1681 * 1682 * Pack the Tx queue context into the dense HW layout, then write it into the 1683 * HW registers. 1684 * 1685 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1686 */ 1687 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1688 u32 txq_index) 1689 { 1690 ice_txq_ctx_buf_full_t buf = {}; 1691 1692 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1693 return -EINVAL; 1694 1695 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1696 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1697 1698 return 0; 1699 } 1700 1701 /* Tx time Queue Context */ 1702 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1703 /* Field Width LSB */ 1704 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1705 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1706 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1707 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1708 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1709 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1710 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1711 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1712 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1713 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1714 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1715 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1716 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1717 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1718 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1719 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1720 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1721 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1722 }; 1723 1724 /** 1725 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1726 * @ctx: the Tx time queue context to pack 1727 * @buf: the HW buffer to pack into 1728 * 1729 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1730 * its bit-packed HW layout. 1731 */ 1732 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1733 ice_txtime_ctx_buf_t *buf) 1734 { 1735 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1736 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1737 } 1738 1739 /* Sideband Queue command wrappers */ 1740 1741 /** 1742 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1743 * @hw: pointer to the HW struct 1744 * @desc: descriptor describing the command 1745 * @buf: buffer to use for indirect commands (NULL for direct commands) 1746 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1747 * @cd: pointer to command details structure 1748 */ 1749 static int 1750 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1751 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1752 { 1753 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1754 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1755 } 1756 1757 /** 1758 * ice_sbq_rw_reg - Fill Sideband Queue command 1759 * @hw: pointer to the HW struct 1760 * @in: message info to be filled in descriptor 1761 * @flags: control queue descriptor flags 1762 */ 1763 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1764 { 1765 struct ice_sbq_cmd_desc desc = {0}; 1766 struct ice_sbq_msg_req msg = {0}; 1767 u16 msg_len; 1768 int status; 1769 1770 msg_len = sizeof(msg); 1771 1772 msg.dest_dev = in->dest_dev; 1773 msg.opcode = in->opcode; 1774 msg.flags = ICE_SBQ_MSG_FLAGS; 1775 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1776 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1777 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1778 1779 if (in->opcode) 1780 msg.data = cpu_to_le32(in->data); 1781 else 1782 /* data read comes back in completion, so shorten the struct by 1783 * sizeof(msg.data) 1784 */ 1785 msg_len -= sizeof(msg.data); 1786 1787 desc.flags = cpu_to_le16(flags); 1788 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1789 desc.param0.cmd_len = cpu_to_le16(msg_len); 1790 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1791 if (!status && !in->opcode) 1792 in->data = le32_to_cpu 1793 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1794 return status; 1795 } 1796 1797 /* FW Admin Queue command wrappers */ 1798 1799 /* Software lock/mutex that is meant to be held while the Global Config Lock 1800 * in firmware is acquired by the software to prevent most (but not all) types 1801 * of AQ commands from being sent to FW 1802 */ 1803 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1804 1805 /** 1806 * ice_should_retry_sq_send_cmd 1807 * @opcode: AQ opcode 1808 * 1809 * Decide if we should retry the send command routine for the ATQ, depending 1810 * on the opcode. 1811 */ 1812 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1813 { 1814 switch (opcode) { 1815 case ice_aqc_opc_get_link_topo: 1816 case ice_aqc_opc_lldp_stop: 1817 case ice_aqc_opc_lldp_start: 1818 case ice_aqc_opc_lldp_filter_ctrl: 1819 return true; 1820 } 1821 1822 return false; 1823 } 1824 1825 /** 1826 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1827 * @hw: pointer to the HW struct 1828 * @cq: pointer to the specific Control queue 1829 * @desc: prefilled descriptor describing the command 1830 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1831 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1832 * @cd: pointer to command details structure 1833 * 1834 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1835 * Queue if the EBUSY AQ error is returned. 1836 */ 1837 static int 1838 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1839 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1840 struct ice_sq_cd *cd) 1841 { 1842 struct libie_aq_desc desc_cpy; 1843 bool is_cmd_for_retry; 1844 u8 idx = 0; 1845 u16 opcode; 1846 int status; 1847 1848 opcode = le16_to_cpu(desc->opcode); 1849 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1850 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1851 1852 if (is_cmd_for_retry) { 1853 /* All retryable cmds are direct, without buf. */ 1854 WARN_ON(buf); 1855 1856 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1857 } 1858 1859 do { 1860 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1861 1862 if (!is_cmd_for_retry || !status || 1863 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1864 break; 1865 1866 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1867 1868 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1869 1870 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1871 1872 return status; 1873 } 1874 1875 /** 1876 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1877 * @hw: pointer to the HW struct 1878 * @desc: descriptor describing the command 1879 * @buf: buffer to use for indirect commands (NULL for direct commands) 1880 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1881 * @cd: pointer to command details structure 1882 * 1883 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1884 */ 1885 int 1886 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1887 u16 buf_size, struct ice_sq_cd *cd) 1888 { 1889 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1890 bool lock_acquired = false; 1891 int status; 1892 1893 /* When a package download is in process (i.e. when the firmware's 1894 * Global Configuration Lock resource is held), only the Download 1895 * Package, Get Version, Get Package Info List, Upload Section, 1896 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1897 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1898 * Recipes to Profile Association, and Release Resource (with resource 1899 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1900 * must block until the package download completes and the Global Config 1901 * Lock is released. See also ice_acquire_global_cfg_lock(). 1902 */ 1903 switch (le16_to_cpu(desc->opcode)) { 1904 case ice_aqc_opc_download_pkg: 1905 case ice_aqc_opc_get_pkg_info_list: 1906 case ice_aqc_opc_get_ver: 1907 case ice_aqc_opc_upload_section: 1908 case ice_aqc_opc_update_pkg: 1909 case ice_aqc_opc_set_port_params: 1910 case ice_aqc_opc_get_vlan_mode_parameters: 1911 case ice_aqc_opc_set_vlan_mode_parameters: 1912 case ice_aqc_opc_set_tx_topo: 1913 case ice_aqc_opc_get_tx_topo: 1914 case ice_aqc_opc_add_recipe: 1915 case ice_aqc_opc_recipe_to_profile: 1916 case ice_aqc_opc_get_recipe: 1917 case ice_aqc_opc_get_recipe_to_profile: 1918 break; 1919 case ice_aqc_opc_release_res: 1920 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1921 break; 1922 fallthrough; 1923 default: 1924 mutex_lock(&ice_global_cfg_lock_sw); 1925 lock_acquired = true; 1926 break; 1927 } 1928 1929 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1930 if (lock_acquired) 1931 mutex_unlock(&ice_global_cfg_lock_sw); 1932 1933 return status; 1934 } 1935 1936 /** 1937 * ice_aq_get_fw_ver 1938 * @hw: pointer to the HW struct 1939 * @cd: pointer to command details structure or NULL 1940 * 1941 * Get the firmware version (0x0001) from the admin queue commands 1942 */ 1943 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1944 { 1945 struct libie_aqc_get_ver *resp; 1946 struct libie_aq_desc desc; 1947 int status; 1948 1949 resp = &desc.params.get_ver; 1950 1951 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1952 1953 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1954 1955 if (!status) { 1956 hw->fw_branch = resp->fw_branch; 1957 hw->fw_maj_ver = resp->fw_major; 1958 hw->fw_min_ver = resp->fw_minor; 1959 hw->fw_patch = resp->fw_patch; 1960 hw->fw_build = le32_to_cpu(resp->fw_build); 1961 hw->api_branch = resp->api_branch; 1962 hw->api_maj_ver = resp->api_major; 1963 hw->api_min_ver = resp->api_minor; 1964 hw->api_patch = resp->api_patch; 1965 } 1966 1967 return status; 1968 } 1969 1970 /** 1971 * ice_aq_send_driver_ver 1972 * @hw: pointer to the HW struct 1973 * @dv: driver's major, minor version 1974 * @cd: pointer to command details structure or NULL 1975 * 1976 * Send the driver version (0x0002) to the firmware 1977 */ 1978 int 1979 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1980 struct ice_sq_cd *cd) 1981 { 1982 struct libie_aqc_driver_ver *cmd; 1983 struct libie_aq_desc desc; 1984 u16 len; 1985 1986 cmd = &desc.params.driver_ver; 1987 1988 if (!dv) 1989 return -EINVAL; 1990 1991 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1992 1993 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1994 cmd->major_ver = dv->major_ver; 1995 cmd->minor_ver = dv->minor_ver; 1996 cmd->build_ver = dv->build_ver; 1997 cmd->subbuild_ver = dv->subbuild_ver; 1998 1999 len = 0; 2000 while (len < sizeof(dv->driver_string) && 2001 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2002 len++; 2003 2004 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2005 } 2006 2007 /** 2008 * ice_aq_q_shutdown 2009 * @hw: pointer to the HW struct 2010 * @unloading: is the driver unloading itself 2011 * 2012 * Tell the Firmware that we're shutting down the AdminQ and whether 2013 * or not the driver is unloading as well (0x0003). 2014 */ 2015 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2016 { 2017 struct ice_aqc_q_shutdown *cmd; 2018 struct libie_aq_desc desc; 2019 2020 cmd = libie_aq_raw(&desc); 2021 2022 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2023 2024 if (unloading) 2025 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2026 2027 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2028 } 2029 2030 /** 2031 * ice_aq_req_res 2032 * @hw: pointer to the HW struct 2033 * @res: resource ID 2034 * @access: access type 2035 * @sdp_number: resource number 2036 * @timeout: the maximum time in ms that the driver may hold the resource 2037 * @cd: pointer to command details structure or NULL 2038 * 2039 * Requests common resource using the admin queue commands (0x0008). 2040 * When attempting to acquire the Global Config Lock, the driver can 2041 * learn of three states: 2042 * 1) 0 - acquired lock, and can perform download package 2043 * 2) -EIO - did not get lock, driver should fail to load 2044 * 3) -EALREADY - did not get lock, but another driver has 2045 * successfully downloaded the package; the driver does 2046 * not have to download the package and can continue 2047 * loading 2048 * 2049 * Note that if the caller is in an acquire lock, perform action, release lock 2050 * phase of operation, it is possible that the FW may detect a timeout and issue 2051 * a CORER. In this case, the driver will receive a CORER interrupt and will 2052 * have to determine its cause. The calling thread that is handling this flow 2053 * will likely get an error propagated back to it indicating the Download 2054 * Package, Update Package or the Release Resource AQ commands timed out. 2055 */ 2056 static int 2057 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2058 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2059 struct ice_sq_cd *cd) 2060 { 2061 struct libie_aqc_req_res *cmd_resp; 2062 struct libie_aq_desc desc; 2063 int status; 2064 2065 cmd_resp = &desc.params.res_owner; 2066 2067 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2068 2069 cmd_resp->res_id = cpu_to_le16(res); 2070 cmd_resp->access_type = cpu_to_le16(access); 2071 cmd_resp->res_number = cpu_to_le32(sdp_number); 2072 cmd_resp->timeout = cpu_to_le32(*timeout); 2073 *timeout = 0; 2074 2075 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2076 2077 /* The completion specifies the maximum time in ms that the driver 2078 * may hold the resource in the Timeout field. 2079 */ 2080 2081 /* Global config lock response utilizes an additional status field. 2082 * 2083 * If the Global config lock resource is held by some other driver, the 2084 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2085 * and the timeout field indicates the maximum time the current owner 2086 * of the resource has to free it. 2087 */ 2088 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2089 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2090 *timeout = le32_to_cpu(cmd_resp->timeout); 2091 return 0; 2092 } else if (le16_to_cpu(cmd_resp->status) == 2093 LIBIE_AQ_RES_GLBL_IN_PROG) { 2094 *timeout = le32_to_cpu(cmd_resp->timeout); 2095 return -EIO; 2096 } else if (le16_to_cpu(cmd_resp->status) == 2097 LIBIE_AQ_RES_GLBL_DONE) { 2098 return -EALREADY; 2099 } 2100 2101 /* invalid FW response, force a timeout immediately */ 2102 *timeout = 0; 2103 return -EIO; 2104 } 2105 2106 /* If the resource is held by some other driver, the command completes 2107 * with a busy return value and the timeout field indicates the maximum 2108 * time the current owner of the resource has to free it. 2109 */ 2110 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2111 *timeout = le32_to_cpu(cmd_resp->timeout); 2112 2113 return status; 2114 } 2115 2116 /** 2117 * ice_aq_release_res 2118 * @hw: pointer to the HW struct 2119 * @res: resource ID 2120 * @sdp_number: resource number 2121 * @cd: pointer to command details structure or NULL 2122 * 2123 * release common resource using the admin queue commands (0x0009) 2124 */ 2125 static int 2126 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2127 struct ice_sq_cd *cd) 2128 { 2129 struct libie_aqc_req_res *cmd; 2130 struct libie_aq_desc desc; 2131 2132 cmd = &desc.params.res_owner; 2133 2134 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2135 2136 cmd->res_id = cpu_to_le16(res); 2137 cmd->res_number = cpu_to_le32(sdp_number); 2138 2139 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2140 } 2141 2142 /** 2143 * ice_acquire_res 2144 * @hw: pointer to the HW structure 2145 * @res: resource ID 2146 * @access: access type (read or write) 2147 * @timeout: timeout in milliseconds 2148 * 2149 * This function will attempt to acquire the ownership of a resource. 2150 */ 2151 int 2152 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2153 enum ice_aq_res_access_type access, u32 timeout) 2154 { 2155 #define ICE_RES_POLLING_DELAY_MS 10 2156 u32 delay = ICE_RES_POLLING_DELAY_MS; 2157 u32 time_left = timeout; 2158 int status; 2159 2160 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2161 2162 /* A return code of -EALREADY means that another driver has 2163 * previously acquired the resource and performed any necessary updates; 2164 * in this case the caller does not obtain the resource and has no 2165 * further work to do. 2166 */ 2167 if (status == -EALREADY) 2168 goto ice_acquire_res_exit; 2169 2170 if (status) 2171 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2172 2173 /* If necessary, poll until the current lock owner timeouts */ 2174 timeout = time_left; 2175 while (status && timeout && time_left) { 2176 mdelay(delay); 2177 timeout = (timeout > delay) ? timeout - delay : 0; 2178 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2179 2180 if (status == -EALREADY) 2181 /* lock free, but no work to do */ 2182 break; 2183 2184 if (!status) 2185 /* lock acquired */ 2186 break; 2187 } 2188 if (status && status != -EALREADY) 2189 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2190 2191 ice_acquire_res_exit: 2192 if (status == -EALREADY) { 2193 if (access == ICE_RES_WRITE) 2194 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2195 else 2196 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2197 } 2198 return status; 2199 } 2200 2201 /** 2202 * ice_release_res 2203 * @hw: pointer to the HW structure 2204 * @res: resource ID 2205 * 2206 * This function will release a resource using the proper Admin Command. 2207 */ 2208 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2209 { 2210 unsigned long timeout; 2211 int status; 2212 2213 /* there are some rare cases when trying to release the resource 2214 * results in an admin queue timeout, so handle them correctly 2215 */ 2216 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2217 do { 2218 status = ice_aq_release_res(hw, res, 0, NULL); 2219 if (status != -EIO) 2220 break; 2221 usleep_range(1000, 2000); 2222 } while (time_before(jiffies, timeout)); 2223 } 2224 2225 /** 2226 * ice_aq_alloc_free_res - command to allocate/free resources 2227 * @hw: pointer to the HW struct 2228 * @buf: Indirect buffer to hold data parameters and response 2229 * @buf_size: size of buffer for indirect commands 2230 * @opc: pass in the command opcode 2231 * 2232 * Helper function to allocate/free resources using the admin queue commands 2233 */ 2234 int ice_aq_alloc_free_res(struct ice_hw *hw, 2235 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2236 enum ice_adminq_opc opc) 2237 { 2238 struct ice_aqc_alloc_free_res_cmd *cmd; 2239 struct libie_aq_desc desc; 2240 2241 cmd = libie_aq_raw(&desc); 2242 2243 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2244 return -EINVAL; 2245 2246 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2247 2248 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2249 2250 cmd->num_entries = cpu_to_le16(1); 2251 2252 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2253 } 2254 2255 /** 2256 * ice_alloc_hw_res - allocate resource 2257 * @hw: pointer to the HW struct 2258 * @type: type of resource 2259 * @num: number of resources to allocate 2260 * @btm: allocate from bottom 2261 * @res: pointer to array that will receive the resources 2262 */ 2263 int 2264 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2265 { 2266 struct ice_aqc_alloc_free_res_elem *buf; 2267 u16 buf_len; 2268 int status; 2269 2270 buf_len = struct_size(buf, elem, num); 2271 buf = kzalloc(buf_len, GFP_KERNEL); 2272 if (!buf) 2273 return -ENOMEM; 2274 2275 /* Prepare buffer to allocate resource. */ 2276 buf->num_elems = cpu_to_le16(num); 2277 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2278 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2279 if (btm) 2280 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2281 2282 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2283 if (status) 2284 goto ice_alloc_res_exit; 2285 2286 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2287 2288 ice_alloc_res_exit: 2289 kfree(buf); 2290 return status; 2291 } 2292 2293 /** 2294 * ice_free_hw_res - free allocated HW resource 2295 * @hw: pointer to the HW struct 2296 * @type: type of resource to free 2297 * @num: number of resources 2298 * @res: pointer to array that contains the resources to free 2299 */ 2300 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2301 { 2302 struct ice_aqc_alloc_free_res_elem *buf; 2303 u16 buf_len; 2304 int status; 2305 2306 buf_len = struct_size(buf, elem, num); 2307 buf = kzalloc(buf_len, GFP_KERNEL); 2308 if (!buf) 2309 return -ENOMEM; 2310 2311 /* Prepare buffer to free resource. */ 2312 buf->num_elems = cpu_to_le16(num); 2313 buf->res_type = cpu_to_le16(type); 2314 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2315 2316 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2317 if (status) 2318 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2319 2320 kfree(buf); 2321 return status; 2322 } 2323 2324 /** 2325 * ice_get_num_per_func - determine number of resources per PF 2326 * @hw: pointer to the HW structure 2327 * @max: value to be evenly split between each PF 2328 * 2329 * Determine the number of valid functions by going through the bitmap returned 2330 * from parsing capabilities and use this to calculate the number of resources 2331 * per PF based on the max value passed in. 2332 */ 2333 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2334 { 2335 u8 funcs; 2336 2337 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2338 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2339 ICE_CAPS_VALID_FUNCS_M); 2340 2341 if (!funcs) 2342 return 0; 2343 2344 return max / funcs; 2345 } 2346 2347 /** 2348 * ice_parse_common_caps - parse common device/function capabilities 2349 * @hw: pointer to the HW struct 2350 * @caps: pointer to common capabilities structure 2351 * @elem: the capability element to parse 2352 * @prefix: message prefix for tracing capabilities 2353 * 2354 * Given a capability element, extract relevant details into the common 2355 * capability structure. 2356 * 2357 * Returns: true if the capability matches one of the common capability ids, 2358 * false otherwise. 2359 */ 2360 static bool 2361 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2362 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2363 { 2364 u32 logical_id = le32_to_cpu(elem->logical_id); 2365 u32 phys_id = le32_to_cpu(elem->phys_id); 2366 u32 number = le32_to_cpu(elem->number); 2367 u16 cap = le16_to_cpu(elem->cap); 2368 bool found = true; 2369 2370 switch (cap) { 2371 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2372 caps->valid_functions = number; 2373 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2374 caps->valid_functions); 2375 break; 2376 case LIBIE_AQC_CAPS_SRIOV: 2377 caps->sr_iov_1_1 = (number == 1); 2378 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2379 caps->sr_iov_1_1); 2380 break; 2381 case LIBIE_AQC_CAPS_DCB: 2382 caps->dcb = (number == 1); 2383 caps->active_tc_bitmap = logical_id; 2384 caps->maxtc = phys_id; 2385 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2386 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2387 caps->active_tc_bitmap); 2388 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2389 break; 2390 case LIBIE_AQC_CAPS_RSS: 2391 caps->rss_table_size = number; 2392 caps->rss_table_entry_width = logical_id; 2393 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2394 caps->rss_table_size); 2395 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2396 caps->rss_table_entry_width); 2397 break; 2398 case LIBIE_AQC_CAPS_RXQS: 2399 caps->num_rxq = number; 2400 caps->rxq_first_id = phys_id; 2401 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2402 caps->num_rxq); 2403 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2404 caps->rxq_first_id); 2405 break; 2406 case LIBIE_AQC_CAPS_TXQS: 2407 caps->num_txq = number; 2408 caps->txq_first_id = phys_id; 2409 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2410 caps->num_txq); 2411 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2412 caps->txq_first_id); 2413 break; 2414 case LIBIE_AQC_CAPS_MSIX: 2415 caps->num_msix_vectors = number; 2416 caps->msix_vector_first_id = phys_id; 2417 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2418 caps->num_msix_vectors); 2419 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2420 caps->msix_vector_first_id); 2421 break; 2422 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2423 caps->nvm_update_pending_nvm = true; 2424 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2425 break; 2426 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2427 caps->nvm_update_pending_orom = true; 2428 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2429 break; 2430 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2431 caps->nvm_update_pending_netlist = true; 2432 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2433 break; 2434 case LIBIE_AQC_CAPS_NVM_MGMT: 2435 caps->nvm_unified_update = 2436 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2437 true : false; 2438 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2439 caps->nvm_unified_update); 2440 break; 2441 case LIBIE_AQC_CAPS_RDMA: 2442 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2443 caps->rdma = (number == 1); 2444 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2445 break; 2446 case LIBIE_AQC_CAPS_MAX_MTU: 2447 caps->max_mtu = number; 2448 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2449 prefix, caps->max_mtu); 2450 break; 2451 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2452 caps->pcie_reset_avoidance = (number > 0); 2453 ice_debug(hw, ICE_DBG_INIT, 2454 "%s: pcie_reset_avoidance = %d\n", prefix, 2455 caps->pcie_reset_avoidance); 2456 break; 2457 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2458 caps->reset_restrict_support = (number == 1); 2459 ice_debug(hw, ICE_DBG_INIT, 2460 "%s: reset_restrict_support = %d\n", prefix, 2461 caps->reset_restrict_support); 2462 break; 2463 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2464 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2465 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2466 prefix, caps->roce_lag); 2467 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2468 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2469 prefix, caps->sriov_lag); 2470 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2471 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2472 prefix, caps->sriov_aa_lag); 2473 break; 2474 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2475 caps->tx_sched_topo_comp_mode_en = (number == 1); 2476 break; 2477 default: 2478 /* Not one of the recognized common capabilities */ 2479 found = false; 2480 } 2481 2482 return found; 2483 } 2484 2485 /** 2486 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2487 * @hw: pointer to the HW structure 2488 * @caps: pointer to capabilities structure to fix 2489 * 2490 * Re-calculate the capabilities that are dependent on the number of physical 2491 * ports; i.e. some features are not supported or function differently on 2492 * devices with more than 4 ports. 2493 */ 2494 static void 2495 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2496 { 2497 /* This assumes device capabilities are always scanned before function 2498 * capabilities during the initialization flow. 2499 */ 2500 if (hw->dev_caps.num_funcs > 4) { 2501 /* Max 4 TCs per port */ 2502 caps->maxtc = 4; 2503 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2504 caps->maxtc); 2505 if (caps->rdma) { 2506 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2507 caps->rdma = 0; 2508 } 2509 2510 /* print message only when processing device capabilities 2511 * during initialization. 2512 */ 2513 if (caps == &hw->dev_caps.common_cap) 2514 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2515 } 2516 } 2517 2518 /** 2519 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2520 * @hw: pointer to the HW struct 2521 * @func_p: pointer to function capabilities structure 2522 * @cap: pointer to the capability element to parse 2523 * 2524 * Extract function capabilities for ICE_AQC_CAPS_VF. 2525 */ 2526 static void 2527 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2528 struct libie_aqc_list_caps_elem *cap) 2529 { 2530 u32 logical_id = le32_to_cpu(cap->logical_id); 2531 u32 number = le32_to_cpu(cap->number); 2532 2533 func_p->num_allocd_vfs = number; 2534 func_p->vf_base_id = logical_id; 2535 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2536 func_p->num_allocd_vfs); 2537 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2538 func_p->vf_base_id); 2539 } 2540 2541 /** 2542 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2543 * @hw: pointer to the HW struct 2544 * @func_p: pointer to function capabilities structure 2545 * @cap: pointer to the capability element to parse 2546 * 2547 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2548 */ 2549 static void 2550 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2551 struct libie_aqc_list_caps_elem *cap) 2552 { 2553 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2554 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2555 le32_to_cpu(cap->number)); 2556 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2557 func_p->guar_num_vsi); 2558 } 2559 2560 /** 2561 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2562 * @hw: pointer to the HW struct 2563 * @func_p: pointer to function capabilities structure 2564 * @cap: pointer to the capability element to parse 2565 * 2566 * Extract function capabilities for ICE_AQC_CAPS_1588. 2567 */ 2568 static void 2569 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2570 struct libie_aqc_list_caps_elem *cap) 2571 { 2572 struct ice_ts_func_info *info = &func_p->ts_func_info; 2573 u32 number = le32_to_cpu(cap->number); 2574 2575 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2576 func_p->common_cap.ieee_1588 = info->ena; 2577 2578 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2579 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2580 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2581 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2582 2583 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2584 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2585 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2586 } else { 2587 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2588 info->clk_src = ICE_CLK_SRC_TIME_REF; 2589 } 2590 2591 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2592 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2593 } else { 2594 /* Unknown clock frequency, so assume a (probably incorrect) 2595 * default to avoid out-of-bounds look ups of frequency 2596 * related information. 2597 */ 2598 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2599 info->clk_freq); 2600 info->time_ref = ICE_TSPLL_FREQ_25_000; 2601 } 2602 2603 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2604 func_p->common_cap.ieee_1588); 2605 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2606 info->src_tmr_owned); 2607 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2608 info->tmr_ena); 2609 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2610 info->tmr_index_owned); 2611 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2612 info->tmr_index_assoc); 2613 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2614 info->clk_freq); 2615 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2616 info->clk_src); 2617 } 2618 2619 /** 2620 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2621 * @hw: pointer to the HW struct 2622 * @func_p: pointer to function capabilities structure 2623 * 2624 * Extract function capabilities for ICE_AQC_CAPS_FD. 2625 */ 2626 static void 2627 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2628 { 2629 u32 reg_val, gsize, bsize; 2630 2631 reg_val = rd32(hw, GLQF_FD_SIZE); 2632 switch (hw->mac_type) { 2633 case ICE_MAC_E830: 2634 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2635 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2636 break; 2637 case ICE_MAC_E810: 2638 default: 2639 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2640 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2641 } 2642 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2643 func_p->fd_fltr_best_effort = bsize; 2644 2645 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2646 func_p->fd_fltr_guar); 2647 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2648 func_p->fd_fltr_best_effort); 2649 } 2650 2651 /** 2652 * ice_parse_func_caps - Parse function capabilities 2653 * @hw: pointer to the HW struct 2654 * @func_p: pointer to function capabilities structure 2655 * @buf: buffer containing the function capability records 2656 * @cap_count: the number of capabilities 2657 * 2658 * Helper function to parse function (0x000A) capabilities list. For 2659 * capabilities shared between device and function, this relies on 2660 * ice_parse_common_caps. 2661 * 2662 * Loop through the list of provided capabilities and extract the relevant 2663 * data into the function capabilities structured. 2664 */ 2665 static void 2666 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2667 void *buf, u32 cap_count) 2668 { 2669 struct libie_aqc_list_caps_elem *cap_resp; 2670 u32 i; 2671 2672 cap_resp = buf; 2673 2674 memset(func_p, 0, sizeof(*func_p)); 2675 2676 for (i = 0; i < cap_count; i++) { 2677 u16 cap = le16_to_cpu(cap_resp[i].cap); 2678 bool found; 2679 2680 found = ice_parse_common_caps(hw, &func_p->common_cap, 2681 &cap_resp[i], "func caps"); 2682 2683 switch (cap) { 2684 case LIBIE_AQC_CAPS_VF: 2685 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2686 break; 2687 case LIBIE_AQC_CAPS_VSI: 2688 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2689 break; 2690 case LIBIE_AQC_CAPS_1588: 2691 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2692 break; 2693 case LIBIE_AQC_CAPS_FD: 2694 ice_parse_fdir_func_caps(hw, func_p); 2695 break; 2696 default: 2697 /* Don't list common capabilities as unknown */ 2698 if (!found) 2699 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2700 i, cap); 2701 break; 2702 } 2703 } 2704 2705 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2706 } 2707 2708 /** 2709 * ice_func_id_to_logical_id - map from function id to logical pf id 2710 * @active_function_bitmap: active function bitmap 2711 * @pf_id: function number of device 2712 * 2713 * Return: logical PF ID. 2714 */ 2715 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2716 { 2717 u8 logical_id = 0; 2718 u8 i; 2719 2720 for (i = 0; i < pf_id; i++) 2721 if (active_function_bitmap & BIT(i)) 2722 logical_id++; 2723 2724 return logical_id; 2725 } 2726 2727 /** 2728 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2729 * @hw: pointer to the HW struct 2730 * @dev_p: pointer to device capabilities structure 2731 * @cap: capability element to parse 2732 * 2733 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2734 */ 2735 static void 2736 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2737 struct libie_aqc_list_caps_elem *cap) 2738 { 2739 u32 number = le32_to_cpu(cap->number); 2740 2741 dev_p->num_funcs = hweight32(number); 2742 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2743 dev_p->num_funcs); 2744 2745 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2746 } 2747 2748 /** 2749 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2750 * @hw: pointer to the HW struct 2751 * @dev_p: pointer to device capabilities structure 2752 * @cap: capability element to parse 2753 * 2754 * Parse ICE_AQC_CAPS_VF for device capabilities. 2755 */ 2756 static void 2757 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2758 struct libie_aqc_list_caps_elem *cap) 2759 { 2760 u32 number = le32_to_cpu(cap->number); 2761 2762 dev_p->num_vfs_exposed = number; 2763 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2764 dev_p->num_vfs_exposed); 2765 } 2766 2767 /** 2768 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2769 * @hw: pointer to the HW struct 2770 * @dev_p: pointer to device capabilities structure 2771 * @cap: capability element to parse 2772 * 2773 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2774 */ 2775 static void 2776 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2777 struct libie_aqc_list_caps_elem *cap) 2778 { 2779 u32 number = le32_to_cpu(cap->number); 2780 2781 dev_p->num_vsi_allocd_to_host = number; 2782 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2783 dev_p->num_vsi_allocd_to_host); 2784 } 2785 2786 /** 2787 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2788 * @hw: pointer to the HW struct 2789 * @dev_p: pointer to device capabilities structure 2790 * @cap: capability element to parse 2791 * 2792 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2793 */ 2794 static void 2795 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2796 struct libie_aqc_list_caps_elem *cap) 2797 { 2798 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2799 u32 logical_id = le32_to_cpu(cap->logical_id); 2800 u32 phys_id = le32_to_cpu(cap->phys_id); 2801 u32 number = le32_to_cpu(cap->number); 2802 2803 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2804 dev_p->common_cap.ieee_1588 = info->ena; 2805 2806 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2807 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2808 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2809 2810 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2811 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2812 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2813 2814 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2815 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2816 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2817 2818 info->ena_ports = logical_id; 2819 info->tmr_own_map = phys_id; 2820 2821 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2822 dev_p->common_cap.ieee_1588); 2823 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2824 info->tmr0_owner); 2825 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2826 info->tmr0_owned); 2827 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2828 info->tmr0_ena); 2829 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2830 info->tmr1_owner); 2831 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2832 info->tmr1_owned); 2833 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2834 info->tmr1_ena); 2835 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2836 info->ts_ll_read); 2837 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2838 info->ts_ll_int_read); 2839 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2840 info->ll_phy_tmr_update); 2841 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2842 info->ena_ports); 2843 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2844 info->tmr_own_map); 2845 } 2846 2847 /** 2848 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2849 * @hw: pointer to the HW struct 2850 * @dev_p: pointer to device capabilities structure 2851 * @cap: capability element to parse 2852 * 2853 * Parse ICE_AQC_CAPS_FD for device capabilities. 2854 */ 2855 static void 2856 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2857 struct libie_aqc_list_caps_elem *cap) 2858 { 2859 u32 number = le32_to_cpu(cap->number); 2860 2861 dev_p->num_flow_director_fltr = number; 2862 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2863 dev_p->num_flow_director_fltr); 2864 } 2865 2866 /** 2867 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2868 * @hw: pointer to the HW struct 2869 * @dev_p: pointer to device capabilities structure 2870 * @cap: capability element to parse 2871 * 2872 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2873 * enabled sensors. 2874 */ 2875 static void 2876 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2877 struct libie_aqc_list_caps_elem *cap) 2878 { 2879 dev_p->supported_sensors = le32_to_cpu(cap->number); 2880 2881 ice_debug(hw, ICE_DBG_INIT, 2882 "dev caps: supported sensors (bitmap) = 0x%x\n", 2883 dev_p->supported_sensors); 2884 } 2885 2886 /** 2887 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2888 * @hw: pointer to the HW struct 2889 * @dev_p: pointer to device capabilities structure 2890 * @cap: capability element to parse 2891 * 2892 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2893 */ 2894 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2895 struct ice_hw_dev_caps *dev_p, 2896 struct libie_aqc_list_caps_elem *cap) 2897 { 2898 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2899 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2900 2901 dev_info(ice_hw_to_dev(hw), 2902 "PF is configured in %s mode with IP instance ID %d\n", 2903 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2904 "primary" : "secondary", dev_p->nac_topo.id); 2905 2906 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2907 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2908 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2909 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2910 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2911 dev_p->nac_topo.id); 2912 } 2913 2914 /** 2915 * ice_parse_dev_caps - Parse device capabilities 2916 * @hw: pointer to the HW struct 2917 * @dev_p: pointer to device capabilities structure 2918 * @buf: buffer containing the device capability records 2919 * @cap_count: the number of capabilities 2920 * 2921 * Helper device to parse device (0x000B) capabilities list. For 2922 * capabilities shared between device and function, this relies on 2923 * ice_parse_common_caps. 2924 * 2925 * Loop through the list of provided capabilities and extract the relevant 2926 * data into the device capabilities structured. 2927 */ 2928 static void 2929 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2930 void *buf, u32 cap_count) 2931 { 2932 struct libie_aqc_list_caps_elem *cap_resp; 2933 u32 i; 2934 2935 cap_resp = buf; 2936 2937 memset(dev_p, 0, sizeof(*dev_p)); 2938 2939 for (i = 0; i < cap_count; i++) { 2940 u16 cap = le16_to_cpu(cap_resp[i].cap); 2941 bool found; 2942 2943 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2944 &cap_resp[i], "dev caps"); 2945 2946 switch (cap) { 2947 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2948 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2949 break; 2950 case LIBIE_AQC_CAPS_VF: 2951 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2952 break; 2953 case LIBIE_AQC_CAPS_VSI: 2954 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2955 break; 2956 case LIBIE_AQC_CAPS_1588: 2957 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2958 break; 2959 case LIBIE_AQC_CAPS_FD: 2960 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2961 break; 2962 case LIBIE_AQC_CAPS_SENSOR_READING: 2963 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2964 break; 2965 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2966 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2967 break; 2968 default: 2969 /* Don't list common capabilities as unknown */ 2970 if (!found) 2971 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2972 i, cap); 2973 break; 2974 } 2975 } 2976 2977 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2978 } 2979 2980 /** 2981 * ice_is_phy_rclk_in_netlist 2982 * @hw: pointer to the hw struct 2983 * 2984 * Check if the PHY Recovered Clock device is present in the netlist 2985 */ 2986 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2987 { 2988 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2989 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2990 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2991 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2992 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2993 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2994 return false; 2995 2996 return true; 2997 } 2998 2999 /** 3000 * ice_is_clock_mux_in_netlist 3001 * @hw: pointer to the hw struct 3002 * 3003 * Check if the Clock Multiplexer device is present in the netlist 3004 */ 3005 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3006 { 3007 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3008 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3009 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3010 NULL)) 3011 return false; 3012 3013 return true; 3014 } 3015 3016 /** 3017 * ice_is_cgu_in_netlist - check for CGU presence 3018 * @hw: pointer to the hw struct 3019 * 3020 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3021 * Save the CGU part number in the hw structure for later use. 3022 * Return: 3023 * * true - cgu is present 3024 * * false - cgu is not present 3025 */ 3026 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3027 { 3028 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3029 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3030 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3031 NULL)) { 3032 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3033 return true; 3034 } else if (!ice_find_netlist_node(hw, 3035 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3036 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3037 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3038 NULL)) { 3039 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3040 return true; 3041 } 3042 3043 return false; 3044 } 3045 3046 /** 3047 * ice_is_gps_in_netlist 3048 * @hw: pointer to the hw struct 3049 * 3050 * Check if the GPS generic device is present in the netlist 3051 */ 3052 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3053 { 3054 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3055 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3056 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3057 return false; 3058 3059 return true; 3060 } 3061 3062 /** 3063 * ice_aq_list_caps - query function/device capabilities 3064 * @hw: pointer to the HW struct 3065 * @buf: a buffer to hold the capabilities 3066 * @buf_size: size of the buffer 3067 * @cap_count: if not NULL, set to the number of capabilities reported 3068 * @opc: capabilities type to discover, device or function 3069 * @cd: pointer to command details structure or NULL 3070 * 3071 * Get the function (0x000A) or device (0x000B) capabilities description from 3072 * firmware and store it in the buffer. 3073 * 3074 * If the cap_count pointer is not NULL, then it is set to the number of 3075 * capabilities firmware will report. Note that if the buffer size is too 3076 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3077 * cap_count will still be updated in this case. It is recommended that the 3078 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3079 * firmware could return) to avoid this. 3080 */ 3081 int 3082 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3083 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3084 { 3085 struct libie_aqc_list_caps *cmd; 3086 struct libie_aq_desc desc; 3087 int status; 3088 3089 cmd = &desc.params.get_cap; 3090 3091 if (opc != ice_aqc_opc_list_func_caps && 3092 opc != ice_aqc_opc_list_dev_caps) 3093 return -EINVAL; 3094 3095 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3096 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3097 3098 if (cap_count) 3099 *cap_count = le32_to_cpu(cmd->count); 3100 3101 return status; 3102 } 3103 3104 /** 3105 * ice_discover_dev_caps - Read and extract device capabilities 3106 * @hw: pointer to the hardware structure 3107 * @dev_caps: pointer to device capabilities structure 3108 * 3109 * Read the device capabilities and extract them into the dev_caps structure 3110 * for later use. 3111 */ 3112 int 3113 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3114 { 3115 u32 cap_count = 0; 3116 void *cbuf; 3117 int status; 3118 3119 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3120 if (!cbuf) 3121 return -ENOMEM; 3122 3123 /* Although the driver doesn't know the number of capabilities the 3124 * device will return, we can simply send a 4KB buffer, the maximum 3125 * possible size that firmware can return. 3126 */ 3127 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3128 3129 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3130 ice_aqc_opc_list_dev_caps, NULL); 3131 if (!status) 3132 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3133 kfree(cbuf); 3134 3135 return status; 3136 } 3137 3138 /** 3139 * ice_discover_func_caps - Read and extract function capabilities 3140 * @hw: pointer to the hardware structure 3141 * @func_caps: pointer to function capabilities structure 3142 * 3143 * Read the function capabilities and extract them into the func_caps structure 3144 * for later use. 3145 */ 3146 static int 3147 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3148 { 3149 u32 cap_count = 0; 3150 void *cbuf; 3151 int status; 3152 3153 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3154 if (!cbuf) 3155 return -ENOMEM; 3156 3157 /* Although the driver doesn't know the number of capabilities the 3158 * device will return, we can simply send a 4KB buffer, the maximum 3159 * possible size that firmware can return. 3160 */ 3161 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3162 3163 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3164 ice_aqc_opc_list_func_caps, NULL); 3165 if (!status) 3166 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3167 kfree(cbuf); 3168 3169 return status; 3170 } 3171 3172 /** 3173 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3174 * @hw: pointer to the hardware structure 3175 */ 3176 void ice_set_safe_mode_caps(struct ice_hw *hw) 3177 { 3178 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3179 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3180 struct ice_hw_common_caps cached_caps; 3181 u32 num_funcs; 3182 3183 /* cache some func_caps values that should be restored after memset */ 3184 cached_caps = func_caps->common_cap; 3185 3186 /* unset func capabilities */ 3187 memset(func_caps, 0, sizeof(*func_caps)); 3188 3189 #define ICE_RESTORE_FUNC_CAP(name) \ 3190 func_caps->common_cap.name = cached_caps.name 3191 3192 /* restore cached values */ 3193 ICE_RESTORE_FUNC_CAP(valid_functions); 3194 ICE_RESTORE_FUNC_CAP(txq_first_id); 3195 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3196 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3197 ICE_RESTORE_FUNC_CAP(max_mtu); 3198 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3199 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3200 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3201 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3202 3203 /* one Tx and one Rx queue in safe mode */ 3204 func_caps->common_cap.num_rxq = 1; 3205 func_caps->common_cap.num_txq = 1; 3206 3207 /* two MSIX vectors, one for traffic and one for misc causes */ 3208 func_caps->common_cap.num_msix_vectors = 2; 3209 func_caps->guar_num_vsi = 1; 3210 3211 /* cache some dev_caps values that should be restored after memset */ 3212 cached_caps = dev_caps->common_cap; 3213 num_funcs = dev_caps->num_funcs; 3214 3215 /* unset dev capabilities */ 3216 memset(dev_caps, 0, sizeof(*dev_caps)); 3217 3218 #define ICE_RESTORE_DEV_CAP(name) \ 3219 dev_caps->common_cap.name = cached_caps.name 3220 3221 /* restore cached values */ 3222 ICE_RESTORE_DEV_CAP(valid_functions); 3223 ICE_RESTORE_DEV_CAP(txq_first_id); 3224 ICE_RESTORE_DEV_CAP(rxq_first_id); 3225 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3226 ICE_RESTORE_DEV_CAP(max_mtu); 3227 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3228 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3229 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3230 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3231 dev_caps->num_funcs = num_funcs; 3232 3233 /* one Tx and one Rx queue per function in safe mode */ 3234 dev_caps->common_cap.num_rxq = num_funcs; 3235 dev_caps->common_cap.num_txq = num_funcs; 3236 3237 /* two MSIX vectors per function */ 3238 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3239 } 3240 3241 /** 3242 * ice_get_caps - get info about the HW 3243 * @hw: pointer to the hardware structure 3244 */ 3245 int ice_get_caps(struct ice_hw *hw) 3246 { 3247 int status; 3248 3249 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3250 if (status) 3251 return status; 3252 3253 return ice_discover_func_caps(hw, &hw->func_caps); 3254 } 3255 3256 /** 3257 * ice_aq_manage_mac_write - manage MAC address write command 3258 * @hw: pointer to the HW struct 3259 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3260 * @flags: flags to control write behavior 3261 * @cd: pointer to command details structure or NULL 3262 * 3263 * This function is used to write MAC address to the NVM (0x0108). 3264 */ 3265 int 3266 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3267 struct ice_sq_cd *cd) 3268 { 3269 struct ice_aqc_manage_mac_write *cmd; 3270 struct libie_aq_desc desc; 3271 3272 cmd = libie_aq_raw(&desc); 3273 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3274 3275 cmd->flags = flags; 3276 ether_addr_copy(cmd->mac_addr, mac_addr); 3277 3278 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3279 } 3280 3281 /** 3282 * ice_aq_clear_pxe_mode 3283 * @hw: pointer to the HW struct 3284 * 3285 * Tell the firmware that the driver is taking over from PXE (0x0110). 3286 */ 3287 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3288 { 3289 struct ice_aqc_clear_pxe *cmd; 3290 struct libie_aq_desc desc; 3291 3292 cmd = libie_aq_raw(&desc); 3293 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3294 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3295 3296 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3297 } 3298 3299 /** 3300 * ice_clear_pxe_mode - clear pxe operations mode 3301 * @hw: pointer to the HW struct 3302 * 3303 * Make sure all PXE mode settings are cleared, including things 3304 * like descriptor fetch/write-back mode. 3305 */ 3306 void ice_clear_pxe_mode(struct ice_hw *hw) 3307 { 3308 if (ice_check_sq_alive(hw, &hw->adminq)) 3309 ice_aq_clear_pxe_mode(hw); 3310 } 3311 3312 /** 3313 * ice_aq_set_port_params - set physical port parameters. 3314 * @pi: pointer to the port info struct 3315 * @double_vlan: if set double VLAN is enabled 3316 * @cd: pointer to command details structure or NULL 3317 * 3318 * Set Physical port parameters (0x0203) 3319 */ 3320 int 3321 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3322 struct ice_sq_cd *cd) 3323 3324 { 3325 struct ice_aqc_set_port_params *cmd; 3326 struct ice_hw *hw = pi->hw; 3327 struct libie_aq_desc desc; 3328 u16 cmd_flags = 0; 3329 3330 cmd = libie_aq_raw(&desc); 3331 3332 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3333 if (double_vlan) 3334 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3335 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3336 3337 cmd->local_fwd_mode = pi->local_fwd_mode | 3338 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3339 3340 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3341 } 3342 3343 /** 3344 * ice_is_100m_speed_supported 3345 * @hw: pointer to the HW struct 3346 * 3347 * returns true if 100M speeds are supported by the device, 3348 * false otherwise. 3349 */ 3350 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3351 { 3352 switch (hw->device_id) { 3353 case ICE_DEV_ID_E822C_SGMII: 3354 case ICE_DEV_ID_E822L_SGMII: 3355 case ICE_DEV_ID_E823L_1GBE: 3356 case ICE_DEV_ID_E823C_SGMII: 3357 case ICE_DEV_ID_E825C_SGMII: 3358 return true; 3359 default: 3360 return false; 3361 } 3362 } 3363 3364 /** 3365 * ice_get_link_speed_based_on_phy_type - returns link speed 3366 * @phy_type_low: lower part of phy_type 3367 * @phy_type_high: higher part of phy_type 3368 * 3369 * This helper function will convert an entry in PHY type structure 3370 * [phy_type_low, phy_type_high] to its corresponding link speed. 3371 * Note: In the structure of [phy_type_low, phy_type_high], there should 3372 * be one bit set, as this function will convert one PHY type to its 3373 * speed. 3374 * 3375 * Return: 3376 * * PHY speed for recognized PHY type 3377 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3378 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3379 */ 3380 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3381 { 3382 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3383 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3384 3385 switch (phy_type_low) { 3386 case ICE_PHY_TYPE_LOW_100BASE_TX: 3387 case ICE_PHY_TYPE_LOW_100M_SGMII: 3388 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3389 break; 3390 case ICE_PHY_TYPE_LOW_1000BASE_T: 3391 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3392 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3393 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3394 case ICE_PHY_TYPE_LOW_1G_SGMII: 3395 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3396 break; 3397 case ICE_PHY_TYPE_LOW_2500BASE_T: 3398 case ICE_PHY_TYPE_LOW_2500BASE_X: 3399 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3400 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3401 break; 3402 case ICE_PHY_TYPE_LOW_5GBASE_T: 3403 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3404 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3405 break; 3406 case ICE_PHY_TYPE_LOW_10GBASE_T: 3407 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3408 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3409 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3410 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3411 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3412 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3413 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3414 break; 3415 case ICE_PHY_TYPE_LOW_25GBASE_T: 3416 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3417 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3418 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3419 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3420 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3421 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3422 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3423 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3424 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3425 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3426 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3427 break; 3428 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3429 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3430 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3431 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3432 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3433 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3434 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3435 break; 3436 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3437 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3438 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3439 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3440 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3441 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3442 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3443 case ICE_PHY_TYPE_LOW_50G_AUI2: 3444 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3445 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3446 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3447 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3448 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3449 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3450 case ICE_PHY_TYPE_LOW_50G_AUI1: 3451 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3452 break; 3453 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3454 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3455 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3456 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3457 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3458 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3459 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3460 case ICE_PHY_TYPE_LOW_100G_AUI4: 3461 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3462 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3463 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3464 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3465 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3466 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3467 break; 3468 default: 3469 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3470 break; 3471 } 3472 3473 switch (phy_type_high) { 3474 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3475 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3476 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3477 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3478 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3479 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3480 break; 3481 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3482 case ICE_PHY_TYPE_HIGH_200G_SR4: 3483 case ICE_PHY_TYPE_HIGH_200G_FR4: 3484 case ICE_PHY_TYPE_HIGH_200G_LR4: 3485 case ICE_PHY_TYPE_HIGH_200G_DR4: 3486 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3487 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3488 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3489 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3490 break; 3491 default: 3492 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3493 break; 3494 } 3495 3496 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3497 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3498 return ICE_AQ_LINK_SPEED_UNKNOWN; 3499 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3500 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3501 return ICE_AQ_LINK_SPEED_UNKNOWN; 3502 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3503 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3504 return speed_phy_type_low; 3505 else 3506 return speed_phy_type_high; 3507 } 3508 3509 /** 3510 * ice_update_phy_type 3511 * @phy_type_low: pointer to the lower part of phy_type 3512 * @phy_type_high: pointer to the higher part of phy_type 3513 * @link_speeds_bitmap: targeted link speeds bitmap 3514 * 3515 * Note: For the link_speeds_bitmap structure, you can check it at 3516 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3517 * link_speeds_bitmap include multiple speeds. 3518 * 3519 * Each entry in this [phy_type_low, phy_type_high] structure will 3520 * present a certain link speed. This helper function will turn on bits 3521 * in [phy_type_low, phy_type_high] structure based on the value of 3522 * link_speeds_bitmap input parameter. 3523 */ 3524 void 3525 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3526 u16 link_speeds_bitmap) 3527 { 3528 u64 pt_high; 3529 u64 pt_low; 3530 int index; 3531 u16 speed; 3532 3533 /* We first check with low part of phy_type */ 3534 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3535 pt_low = BIT_ULL(index); 3536 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3537 3538 if (link_speeds_bitmap & speed) 3539 *phy_type_low |= BIT_ULL(index); 3540 } 3541 3542 /* We then check with high part of phy_type */ 3543 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3544 pt_high = BIT_ULL(index); 3545 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3546 3547 if (link_speeds_bitmap & speed) 3548 *phy_type_high |= BIT_ULL(index); 3549 } 3550 } 3551 3552 /** 3553 * ice_aq_set_phy_cfg 3554 * @hw: pointer to the HW struct 3555 * @pi: port info structure of the interested logical port 3556 * @cfg: structure with PHY configuration data to be set 3557 * @cd: pointer to command details structure or NULL 3558 * 3559 * Set the various PHY configuration parameters supported on the Port. 3560 * One or more of the Set PHY config parameters may be ignored in an MFP 3561 * mode as the PF may not have the privilege to set some of the PHY Config 3562 * parameters. This status will be indicated by the command response (0x0601). 3563 */ 3564 int 3565 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3566 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3567 { 3568 struct ice_aqc_set_phy_cfg *cmd; 3569 struct libie_aq_desc desc; 3570 int status; 3571 3572 if (!cfg) 3573 return -EINVAL; 3574 3575 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3576 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3577 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3578 cfg->caps); 3579 3580 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3581 } 3582 3583 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3584 cmd = libie_aq_raw(&desc); 3585 cmd->lport_num = pi->lport; 3586 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3587 3588 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3589 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3590 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3591 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3592 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3593 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3594 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3595 cfg->low_power_ctrl_an); 3596 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3597 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3598 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3599 cfg->link_fec_opt); 3600 3601 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3602 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3603 status = 0; 3604 3605 if (!status) 3606 pi->phy.curr_user_phy_cfg = *cfg; 3607 3608 return status; 3609 } 3610 3611 /** 3612 * ice_update_link_info - update status of the HW network link 3613 * @pi: port info structure of the interested logical port 3614 */ 3615 int ice_update_link_info(struct ice_port_info *pi) 3616 { 3617 struct ice_link_status *li; 3618 int status; 3619 3620 if (!pi) 3621 return -EINVAL; 3622 3623 li = &pi->phy.link_info; 3624 3625 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3626 if (status) 3627 return status; 3628 3629 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3630 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3631 3632 pcaps = kzalloc_obj(*pcaps); 3633 if (!pcaps) 3634 return -ENOMEM; 3635 3636 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3637 pcaps, NULL); 3638 } 3639 3640 return status; 3641 } 3642 3643 /** 3644 * ice_aq_get_phy_equalization - function to read serdes equaliser 3645 * value from firmware using admin queue command. 3646 * @hw: pointer to the HW struct 3647 * @data_in: represents the serdes equalization parameter requested 3648 * @op_code: represents the serdes number and flag to represent tx or rx 3649 * @serdes_num: represents the serdes number 3650 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3651 * 3652 * Return: non-zero status on error and 0 on success. 3653 */ 3654 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3655 u8 serdes_num, int *output) 3656 { 3657 struct ice_aqc_dnl_call_command *cmd; 3658 struct ice_aqc_dnl_call buf = {}; 3659 struct libie_aq_desc desc; 3660 int err; 3661 3662 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3663 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3664 cpu_to_le16(op_code | (serdes_num & 0xF)); 3665 cmd = libie_aq_raw(&desc); 3666 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3667 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3668 LIBIE_AQ_FLAG_RD | 3669 LIBIE_AQ_FLAG_SI); 3670 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3671 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3672 3673 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3674 NULL); 3675 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3676 3677 return err; 3678 } 3679 3680 #define FEC_REG_PORT(port) { \ 3681 FEC_CORR_LOW_REG_PORT##port, \ 3682 FEC_CORR_HIGH_REG_PORT##port, \ 3683 FEC_UNCORR_LOW_REG_PORT##port, \ 3684 FEC_UNCORR_HIGH_REG_PORT##port, \ 3685 } 3686 3687 static const u32 fec_reg[][ICE_FEC_MAX] = { 3688 FEC_REG_PORT(0), 3689 FEC_REG_PORT(1), 3690 FEC_REG_PORT(2), 3691 FEC_REG_PORT(3) 3692 }; 3693 3694 /** 3695 * ice_aq_get_fec_stats - reads fec stats from phy 3696 * @hw: pointer to the HW struct 3697 * @pcs_quad: represents pcsquad of user input serdes 3698 * @pcs_port: represents the pcs port number part of above pcs quad 3699 * @fec_type: represents FEC stats type 3700 * @output: pointer to the caller-supplied buffer to return requested fec stats 3701 * 3702 * Return: non-zero status on error and 0 on success. 3703 */ 3704 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3705 enum ice_fec_stats_types fec_type, u32 *output) 3706 { 3707 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3708 struct ice_sbq_msg_input msg = {}; 3709 u32 receiver_id, reg_offset; 3710 int err; 3711 3712 if (pcs_port > 3) 3713 return -EINVAL; 3714 3715 reg_offset = fec_reg[pcs_port][fec_type]; 3716 3717 if (pcs_quad == 0) 3718 receiver_id = FEC_RECEIVER_ID_PCS0; 3719 else if (pcs_quad == 1) 3720 receiver_id = FEC_RECEIVER_ID_PCS1; 3721 else 3722 return -EINVAL; 3723 3724 msg.msg_addr_low = lower_16_bits(reg_offset); 3725 msg.msg_addr_high = receiver_id; 3726 msg.opcode = ice_sbq_msg_rd; 3727 msg.dest_dev = ice_sbq_dev_phy_0; 3728 3729 err = ice_sbq_rw_reg(hw, &msg, flag); 3730 if (err) 3731 return err; 3732 3733 *output = msg.data; 3734 return 0; 3735 } 3736 3737 /** 3738 * ice_cache_phy_user_req 3739 * @pi: port information structure 3740 * @cache_data: PHY logging data 3741 * @cache_mode: PHY logging mode 3742 * 3743 * Log the user request on (FC, FEC, SPEED) for later use. 3744 */ 3745 static void 3746 ice_cache_phy_user_req(struct ice_port_info *pi, 3747 struct ice_phy_cache_mode_data cache_data, 3748 enum ice_phy_cache_mode cache_mode) 3749 { 3750 if (!pi) 3751 return; 3752 3753 switch (cache_mode) { 3754 case ICE_FC_MODE: 3755 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3756 break; 3757 case ICE_SPEED_MODE: 3758 pi->phy.curr_user_speed_req = 3759 cache_data.data.curr_user_speed_req; 3760 break; 3761 case ICE_FEC_MODE: 3762 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3763 break; 3764 default: 3765 break; 3766 } 3767 } 3768 3769 /** 3770 * ice_caps_to_fc_mode 3771 * @caps: PHY capabilities 3772 * 3773 * Convert PHY FC capabilities to ice FC mode 3774 */ 3775 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3776 { 3777 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3778 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3779 return ICE_FC_FULL; 3780 3781 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3782 return ICE_FC_TX_PAUSE; 3783 3784 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3785 return ICE_FC_RX_PAUSE; 3786 3787 return ICE_FC_NONE; 3788 } 3789 3790 /** 3791 * ice_caps_to_fec_mode 3792 * @caps: PHY capabilities 3793 * @fec_options: Link FEC options 3794 * 3795 * Convert PHY FEC capabilities to ice FEC mode 3796 */ 3797 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3798 { 3799 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3800 return ICE_FEC_AUTO; 3801 3802 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3803 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3804 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3805 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3806 return ICE_FEC_BASER; 3807 3808 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3809 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3810 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3811 return ICE_FEC_RS; 3812 3813 return ICE_FEC_NONE; 3814 } 3815 3816 /** 3817 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3818 * @pi: port information structure 3819 * @cfg: PHY configuration data to set FC mode 3820 * @req_mode: FC mode to configure 3821 */ 3822 int 3823 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3824 enum ice_fc_mode req_mode) 3825 { 3826 struct ice_phy_cache_mode_data cache_data; 3827 u8 pause_mask = 0x0; 3828 3829 if (!pi || !cfg) 3830 return -EINVAL; 3831 3832 switch (req_mode) { 3833 case ICE_FC_FULL: 3834 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3835 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3836 break; 3837 case ICE_FC_RX_PAUSE: 3838 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3839 break; 3840 case ICE_FC_TX_PAUSE: 3841 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3842 break; 3843 default: 3844 break; 3845 } 3846 3847 /* clear the old pause settings */ 3848 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3849 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3850 3851 /* set the new capabilities */ 3852 cfg->caps |= pause_mask; 3853 3854 /* Cache user FC request */ 3855 cache_data.data.curr_user_fc_req = req_mode; 3856 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3857 3858 return 0; 3859 } 3860 3861 /** 3862 * ice_set_fc 3863 * @pi: port information structure 3864 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3865 * @ena_auto_link_update: enable automatic link update 3866 * 3867 * Set the requested flow control mode. 3868 */ 3869 int 3870 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3871 { 3872 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3873 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3874 struct ice_hw *hw; 3875 int status; 3876 3877 if (!pi || !aq_failures) 3878 return -EINVAL; 3879 3880 *aq_failures = 0; 3881 hw = pi->hw; 3882 3883 pcaps = kzalloc_obj(*pcaps); 3884 if (!pcaps) 3885 return -ENOMEM; 3886 3887 /* Get the current PHY config */ 3888 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3889 pcaps, NULL); 3890 if (status) { 3891 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3892 goto out; 3893 } 3894 3895 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3896 3897 /* Configure the set PHY data */ 3898 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3899 if (status) 3900 goto out; 3901 3902 /* If the capabilities have changed, then set the new config */ 3903 if (cfg.caps != pcaps->caps) { 3904 int retry_count, retry_max = 10; 3905 3906 /* Auto restart link so settings take effect */ 3907 if (ena_auto_link_update) 3908 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3909 3910 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3911 if (status) { 3912 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3913 goto out; 3914 } 3915 3916 /* Update the link info 3917 * It sometimes takes a really long time for link to 3918 * come back from the atomic reset. Thus, we wait a 3919 * little bit. 3920 */ 3921 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3922 status = ice_update_link_info(pi); 3923 3924 if (!status) 3925 break; 3926 3927 mdelay(100); 3928 } 3929 3930 if (status) 3931 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3932 } 3933 3934 out: 3935 return status; 3936 } 3937 3938 /** 3939 * ice_phy_caps_equals_cfg 3940 * @phy_caps: PHY capabilities 3941 * @phy_cfg: PHY configuration 3942 * 3943 * Helper function to determine if PHY capabilities matches PHY 3944 * configuration 3945 */ 3946 bool 3947 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3948 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3949 { 3950 u8 caps_mask, cfg_mask; 3951 3952 if (!phy_caps || !phy_cfg) 3953 return false; 3954 3955 /* These bits are not common between capabilities and configuration. 3956 * Do not use them to determine equality. 3957 */ 3958 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3959 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3960 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3961 3962 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3963 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3964 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3965 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3966 phy_caps->eee_cap != phy_cfg->eee_cap || 3967 phy_caps->eeer_value != phy_cfg->eeer_value || 3968 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3969 return false; 3970 3971 return true; 3972 } 3973 3974 /** 3975 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3976 * @pi: port information structure 3977 * @caps: PHY ability structure to copy date from 3978 * @cfg: PHY configuration structure to copy data to 3979 * 3980 * Helper function to copy AQC PHY get ability data to PHY set configuration 3981 * data structure 3982 */ 3983 void 3984 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3985 struct ice_aqc_get_phy_caps_data *caps, 3986 struct ice_aqc_set_phy_cfg_data *cfg) 3987 { 3988 if (!pi || !caps || !cfg) 3989 return; 3990 3991 memset(cfg, 0, sizeof(*cfg)); 3992 cfg->phy_type_low = caps->phy_type_low; 3993 cfg->phy_type_high = caps->phy_type_high; 3994 cfg->caps = caps->caps; 3995 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3996 cfg->eee_cap = caps->eee_cap; 3997 cfg->eeer_value = caps->eeer_value; 3998 cfg->link_fec_opt = caps->link_fec_options; 3999 cfg->module_compliance_enforcement = 4000 caps->module_compliance_enforcement; 4001 } 4002 4003 /** 4004 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4005 * @pi: port information structure 4006 * @cfg: PHY configuration data to set FEC mode 4007 * @fec: FEC mode to configure 4008 */ 4009 int 4010 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4011 enum ice_fec_mode fec) 4012 { 4013 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4014 struct ice_hw *hw; 4015 int status; 4016 4017 if (!pi || !cfg) 4018 return -EINVAL; 4019 4020 hw = pi->hw; 4021 4022 pcaps = kzalloc_obj(*pcaps); 4023 if (!pcaps) 4024 return -ENOMEM; 4025 4026 status = ice_aq_get_phy_caps(pi, false, 4027 (ice_fw_supports_report_dflt_cfg(hw) ? 4028 ICE_AQC_REPORT_DFLT_CFG : 4029 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4030 if (status) 4031 goto out; 4032 4033 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4034 cfg->link_fec_opt = pcaps->link_fec_options; 4035 4036 switch (fec) { 4037 case ICE_FEC_BASER: 4038 /* Clear RS bits, and AND BASE-R ability 4039 * bits and OR request bits. 4040 */ 4041 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4042 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4043 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4044 ICE_AQC_PHY_FEC_25G_KR_REQ; 4045 break; 4046 case ICE_FEC_RS: 4047 /* Clear BASE-R bits, and AND RS ability 4048 * bits and OR request bits. 4049 */ 4050 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4051 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4052 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4053 break; 4054 case ICE_FEC_NONE: 4055 /* Clear all FEC option bits. */ 4056 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4057 break; 4058 case ICE_FEC_AUTO: 4059 /* AND auto FEC bit, and all caps bits. */ 4060 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4061 cfg->link_fec_opt |= pcaps->link_fec_options; 4062 break; 4063 default: 4064 status = -EINVAL; 4065 break; 4066 } 4067 4068 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4069 !ice_fw_supports_report_dflt_cfg(hw)) { 4070 struct ice_link_default_override_tlv tlv = { 0 }; 4071 4072 status = ice_get_link_default_override(&tlv, pi); 4073 if (status) 4074 goto out; 4075 4076 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4077 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4078 cfg->link_fec_opt = tlv.fec_options; 4079 } 4080 4081 out: 4082 return status; 4083 } 4084 4085 /** 4086 * ice_get_link_status - get status of the HW network link 4087 * @pi: port information structure 4088 * @link_up: pointer to bool (true/false = linkup/linkdown) 4089 * 4090 * Variable link_up is true if link is up, false if link is down. 4091 * The variable link_up is invalid if status is non zero. As a 4092 * result of this call, link status reporting becomes enabled 4093 */ 4094 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4095 { 4096 struct ice_phy_info *phy_info; 4097 int status = 0; 4098 4099 if (!pi || !link_up) 4100 return -EINVAL; 4101 4102 phy_info = &pi->phy; 4103 4104 if (phy_info->get_link_info) { 4105 status = ice_update_link_info(pi); 4106 4107 if (status) 4108 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4109 status); 4110 } 4111 4112 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4113 4114 return status; 4115 } 4116 4117 /** 4118 * ice_aq_set_link_restart_an 4119 * @pi: pointer to the port information structure 4120 * @ena_link: if true: enable link, if false: disable link 4121 * @cd: pointer to command details structure or NULL 4122 * 4123 * Sets up the link and restarts the Auto-Negotiation over the link. 4124 */ 4125 int 4126 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4127 struct ice_sq_cd *cd) 4128 { 4129 struct ice_aqc_restart_an *cmd; 4130 struct libie_aq_desc desc; 4131 4132 cmd = libie_aq_raw(&desc); 4133 4134 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4135 4136 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4137 cmd->lport_num = pi->lport; 4138 if (ena_link) 4139 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4140 else 4141 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4142 4143 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4144 } 4145 4146 /** 4147 * ice_aq_set_event_mask 4148 * @hw: pointer to the HW struct 4149 * @port_num: port number of the physical function 4150 * @mask: event mask to be set 4151 * @cd: pointer to command details structure or NULL 4152 * 4153 * Set event mask (0x0613) 4154 */ 4155 int 4156 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4157 struct ice_sq_cd *cd) 4158 { 4159 struct ice_aqc_set_event_mask *cmd; 4160 struct libie_aq_desc desc; 4161 4162 cmd = libie_aq_raw(&desc); 4163 4164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4165 4166 cmd->lport_num = port_num; 4167 4168 cmd->event_mask = cpu_to_le16(mask); 4169 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4170 } 4171 4172 /** 4173 * ice_aq_set_mac_loopback 4174 * @hw: pointer to the HW struct 4175 * @ena_lpbk: Enable or Disable loopback 4176 * @cd: pointer to command details structure or NULL 4177 * 4178 * Enable/disable loopback on a given port 4179 */ 4180 int 4181 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4182 { 4183 struct ice_aqc_set_mac_lb *cmd; 4184 struct libie_aq_desc desc; 4185 4186 cmd = libie_aq_raw(&desc); 4187 4188 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4189 if (ena_lpbk) 4190 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4191 4192 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4193 } 4194 4195 /** 4196 * ice_aq_set_port_id_led 4197 * @pi: pointer to the port information 4198 * @is_orig_mode: is this LED set to original mode (by the net-list) 4199 * @cd: pointer to command details structure or NULL 4200 * 4201 * Set LED value for the given port (0x06e9) 4202 */ 4203 int 4204 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4205 struct ice_sq_cd *cd) 4206 { 4207 struct ice_aqc_set_port_id_led *cmd; 4208 struct ice_hw *hw = pi->hw; 4209 struct libie_aq_desc desc; 4210 4211 cmd = libie_aq_raw(&desc); 4212 4213 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4214 4215 if (is_orig_mode) 4216 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4217 else 4218 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4219 4220 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4221 } 4222 4223 /** 4224 * ice_aq_get_port_options 4225 * @hw: pointer to the HW struct 4226 * @options: buffer for the resultant port options 4227 * @option_count: input - size of the buffer in port options structures, 4228 * output - number of returned port options 4229 * @lport: logical port to call the command with (optional) 4230 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4231 * when PF owns more than 1 port it must be true 4232 * @active_option_idx: index of active port option in returned buffer 4233 * @active_option_valid: active option in returned buffer is valid 4234 * @pending_option_idx: index of pending port option in returned buffer 4235 * @pending_option_valid: pending option in returned buffer is valid 4236 * 4237 * Calls Get Port Options AQC (0x06ea) and verifies result. 4238 */ 4239 int 4240 ice_aq_get_port_options(struct ice_hw *hw, 4241 struct ice_aqc_get_port_options_elem *options, 4242 u8 *option_count, u8 lport, bool lport_valid, 4243 u8 *active_option_idx, bool *active_option_valid, 4244 u8 *pending_option_idx, bool *pending_option_valid) 4245 { 4246 struct ice_aqc_get_port_options *cmd; 4247 struct libie_aq_desc desc; 4248 int status; 4249 u8 i; 4250 4251 /* options buffer shall be able to hold max returned options */ 4252 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4253 return -EINVAL; 4254 4255 cmd = libie_aq_raw(&desc); 4256 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4257 4258 if (lport_valid) 4259 cmd->lport_num = lport; 4260 cmd->lport_num_valid = lport_valid; 4261 4262 status = ice_aq_send_cmd(hw, &desc, options, 4263 *option_count * sizeof(*options), NULL); 4264 if (status) 4265 return status; 4266 4267 /* verify direct FW response & set output parameters */ 4268 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4269 cmd->port_options_count); 4270 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4271 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4272 cmd->port_options); 4273 if (*active_option_valid) { 4274 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4275 cmd->port_options); 4276 if (*active_option_idx > (*option_count - 1)) 4277 return -EIO; 4278 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4279 *active_option_idx); 4280 } 4281 4282 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4283 cmd->pending_port_option_status); 4284 if (*pending_option_valid) { 4285 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4286 cmd->pending_port_option_status); 4287 if (*pending_option_idx > (*option_count - 1)) 4288 return -EIO; 4289 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4290 *pending_option_idx); 4291 } 4292 4293 /* mask output options fields */ 4294 for (i = 0; i < *option_count; i++) { 4295 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4296 options[i].pmd); 4297 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4298 options[i].max_lane_speed); 4299 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4300 options[i].pmd, options[i].max_lane_speed); 4301 } 4302 4303 return 0; 4304 } 4305 4306 /** 4307 * ice_aq_set_port_option 4308 * @hw: pointer to the HW struct 4309 * @lport: logical port to call the command with 4310 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4311 * when PF owns more than 1 port it must be true 4312 * @new_option: new port option to be written 4313 * 4314 * Calls Set Port Options AQC (0x06eb). 4315 */ 4316 int 4317 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4318 u8 new_option) 4319 { 4320 struct ice_aqc_set_port_option *cmd; 4321 struct libie_aq_desc desc; 4322 4323 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4324 return -EINVAL; 4325 4326 cmd = libie_aq_raw(&desc); 4327 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4328 4329 if (lport_valid) 4330 cmd->lport_num = lport; 4331 4332 cmd->lport_num_valid = lport_valid; 4333 cmd->selected_port_option = new_option; 4334 4335 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4336 } 4337 4338 /** 4339 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4340 * @hw: pointer to the hw struct 4341 * 4342 * Return: PHY lane number on success, negative error code otherwise. 4343 */ 4344 int ice_get_phy_lane_number(struct ice_hw *hw) 4345 { 4346 struct ice_aqc_get_port_options_elem *options; 4347 unsigned int lport = 0; 4348 unsigned int lane; 4349 int err; 4350 4351 /* E82X does not have sequential IDs, lane number is PF ID. 4352 * For E825 device, the exception is the variant with external 4353 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4354 * mapping. 4355 */ 4356 if (hw->mac_type == ICE_MAC_GENERIC || 4357 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4358 return hw->pf_id; 4359 4360 options = kzalloc_objs(*options, ICE_AQC_PORT_OPT_MAX); 4361 if (!options) 4362 return -ENOMEM; 4363 4364 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4365 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4366 u8 speed, active_idx, pending_idx; 4367 bool active_valid, pending_valid; 4368 4369 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4370 true, &active_idx, &active_valid, 4371 &pending_idx, &pending_valid); 4372 if (err) 4373 goto err; 4374 4375 if (!active_valid) 4376 continue; 4377 4378 speed = options[active_idx].max_lane_speed; 4379 /* If we don't get speed for this lane, it's unoccupied */ 4380 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4381 continue; 4382 4383 if (hw->pf_id == lport) { 4384 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4385 ice_is_dual(hw) && !ice_is_primary(hw)) 4386 lane += ICE_PORTS_PER_QUAD; 4387 kfree(options); 4388 return lane; 4389 } 4390 lport++; 4391 } 4392 4393 /* PHY lane not found */ 4394 err = -ENXIO; 4395 err: 4396 kfree(options); 4397 return err; 4398 } 4399 4400 /** 4401 * ice_aq_sff_eeprom 4402 * @hw: pointer to the HW struct 4403 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4404 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4405 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4406 * @page: QSFP page 4407 * @set_page: set or ignore the page 4408 * @data: pointer to data buffer to be read/written to the I2C device. 4409 * @length: 1-16 for read, 1 for write. 4410 * @write: 0 read, 1 for write. 4411 * @cd: pointer to command details structure or NULL 4412 * 4413 * Read/Write SFF EEPROM (0x06EE) 4414 */ 4415 int 4416 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4417 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4418 bool write, struct ice_sq_cd *cd) 4419 { 4420 struct ice_aqc_sff_eeprom *cmd; 4421 struct libie_aq_desc desc; 4422 u16 i2c_bus_addr; 4423 int status; 4424 4425 if (!data || (mem_addr & 0xff00)) 4426 return -EINVAL; 4427 4428 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4429 cmd = libie_aq_raw(&desc); 4430 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4431 cmd->lport_num = (u8)(lport & 0xff); 4432 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4433 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4434 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4435 if (write) 4436 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4437 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4438 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4439 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4440 4441 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4442 return status; 4443 } 4444 4445 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4446 { 4447 switch (type) { 4448 case ICE_LUT_VSI: 4449 return ICE_LUT_VSI_SIZE; 4450 case ICE_LUT_GLOBAL: 4451 return ICE_LUT_GLOBAL_SIZE; 4452 case ICE_LUT_PF: 4453 return ICE_LUT_PF_SIZE; 4454 } 4455 WARN_ONCE(1, "incorrect type passed"); 4456 return ICE_LUT_VSI_SIZE; 4457 } 4458 4459 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4460 { 4461 switch (size) { 4462 case ICE_LUT_VSI_SIZE: 4463 return ICE_AQC_LUT_SIZE_SMALL; 4464 case ICE_LUT_GLOBAL_SIZE: 4465 return ICE_AQC_LUT_SIZE_512; 4466 case ICE_LUT_PF_SIZE: 4467 return ICE_AQC_LUT_SIZE_2K; 4468 } 4469 WARN_ONCE(1, "incorrect size passed"); 4470 return 0; 4471 } 4472 4473 /** 4474 * __ice_aq_get_set_rss_lut 4475 * @hw: pointer to the hardware structure 4476 * @params: RSS LUT parameters 4477 * @set: set true to set the table, false to get the table 4478 * 4479 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4480 */ 4481 static int 4482 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4483 struct ice_aq_get_set_rss_lut_params *params, bool set) 4484 { 4485 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4486 enum ice_lut_type lut_type = params->lut_type; 4487 struct ice_aqc_get_set_rss_lut *desc_params; 4488 enum ice_aqc_lut_flags flags; 4489 enum ice_lut_size lut_size; 4490 struct libie_aq_desc desc; 4491 u8 *lut = params->lut; 4492 4493 4494 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4495 return -EINVAL; 4496 4497 lut_size = ice_lut_type_to_size(lut_type); 4498 if (lut_size > params->lut_size) 4499 return -EINVAL; 4500 else if (set && lut_size != params->lut_size) 4501 return -EINVAL; 4502 4503 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4504 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4505 if (set) 4506 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4507 4508 desc_params = libie_aq_raw(&desc); 4509 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4510 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4511 4512 if (lut_type == ICE_LUT_GLOBAL) 4513 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4514 params->global_lut_id); 4515 4516 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4517 desc_params->flags = cpu_to_le16(flags); 4518 4519 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4520 } 4521 4522 /** 4523 * ice_aq_get_rss_lut 4524 * @hw: pointer to the hardware structure 4525 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4526 * 4527 * get the RSS lookup table, PF or VSI type 4528 */ 4529 int 4530 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4531 { 4532 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4533 } 4534 4535 /** 4536 * ice_aq_set_rss_lut 4537 * @hw: pointer to the hardware structure 4538 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4539 * 4540 * set the RSS lookup table, PF or VSI type 4541 */ 4542 int 4543 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4544 { 4545 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4546 } 4547 4548 /** 4549 * __ice_aq_get_set_rss_key 4550 * @hw: pointer to the HW struct 4551 * @vsi_id: VSI FW index 4552 * @key: pointer to key info struct 4553 * @set: set true to set the key, false to get the key 4554 * 4555 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4556 */ 4557 static int 4558 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4559 struct ice_aqc_get_set_rss_keys *key, bool set) 4560 { 4561 struct ice_aqc_get_set_rss_key *desc_params; 4562 u16 key_size = sizeof(*key); 4563 struct libie_aq_desc desc; 4564 4565 if (set) { 4566 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4567 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4568 } else { 4569 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4570 } 4571 4572 desc_params = libie_aq_raw(&desc); 4573 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4574 4575 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4576 } 4577 4578 /** 4579 * ice_aq_get_rss_key 4580 * @hw: pointer to the HW struct 4581 * @vsi_handle: software VSI handle 4582 * @key: pointer to key info struct 4583 * 4584 * get the RSS key per VSI 4585 */ 4586 int 4587 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4588 struct ice_aqc_get_set_rss_keys *key) 4589 { 4590 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4591 return -EINVAL; 4592 4593 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4594 key, false); 4595 } 4596 4597 /** 4598 * ice_aq_set_rss_key 4599 * @hw: pointer to the HW struct 4600 * @vsi_handle: software VSI handle 4601 * @keys: pointer to key info struct 4602 * 4603 * set the RSS key per VSI 4604 */ 4605 int 4606 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4607 struct ice_aqc_get_set_rss_keys *keys) 4608 { 4609 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4610 return -EINVAL; 4611 4612 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4613 keys, true); 4614 } 4615 4616 /** 4617 * ice_aq_add_lan_txq 4618 * @hw: pointer to the hardware structure 4619 * @num_qgrps: Number of added queue groups 4620 * @qg_list: list of queue groups to be added 4621 * @buf_size: size of buffer for indirect command 4622 * @cd: pointer to command details structure or NULL 4623 * 4624 * Add Tx LAN queue (0x0C30) 4625 * 4626 * NOTE: 4627 * Prior to calling add Tx LAN queue: 4628 * Initialize the following as part of the Tx queue context: 4629 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4630 * Cache profile and Packet shaper profile. 4631 * 4632 * After add Tx LAN queue AQ command is completed: 4633 * Interrupts should be associated with specific queues, 4634 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4635 * flow. 4636 */ 4637 static int 4638 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4639 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4640 struct ice_sq_cd *cd) 4641 { 4642 struct ice_aqc_add_tx_qgrp *list; 4643 struct ice_aqc_add_txqs *cmd; 4644 struct libie_aq_desc desc; 4645 u16 i, sum_size = 0; 4646 4647 cmd = libie_aq_raw(&desc); 4648 4649 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4650 4651 if (!qg_list) 4652 return -EINVAL; 4653 4654 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4655 return -EINVAL; 4656 4657 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4658 sum_size += struct_size(list, txqs, list->num_txqs); 4659 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4660 list->num_txqs); 4661 } 4662 4663 if (buf_size != sum_size) 4664 return -EINVAL; 4665 4666 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4667 4668 cmd->num_qgrps = num_qgrps; 4669 4670 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4671 } 4672 4673 /** 4674 * ice_aq_dis_lan_txq 4675 * @hw: pointer to the hardware structure 4676 * @num_qgrps: number of groups in the list 4677 * @qg_list: the list of groups to disable 4678 * @buf_size: the total size of the qg_list buffer in bytes 4679 * @rst_src: if called due to reset, specifies the reset source 4680 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4681 * @cd: pointer to command details structure or NULL 4682 * 4683 * Disable LAN Tx queue (0x0C31) 4684 */ 4685 static int 4686 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4687 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4688 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4689 struct ice_sq_cd *cd) 4690 { 4691 struct ice_aqc_dis_txq_item *item; 4692 struct ice_aqc_dis_txqs *cmd; 4693 struct libie_aq_desc desc; 4694 u16 vmvf_and_timeout; 4695 u16 i, sz = 0; 4696 int status; 4697 4698 cmd = libie_aq_raw(&desc); 4699 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4700 4701 /* qg_list can be NULL only in VM/VF reset flow */ 4702 if (!qg_list && !rst_src) 4703 return -EINVAL; 4704 4705 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4706 return -EINVAL; 4707 4708 cmd->num_entries = num_qgrps; 4709 4710 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4711 4712 switch (rst_src) { 4713 case ICE_VM_RESET: 4714 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4715 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4716 break; 4717 case ICE_VF_RESET: 4718 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4719 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4720 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4721 ICE_AQC_Q_DIS_VMVF_NUM_M; 4722 break; 4723 case ICE_NO_RESET: 4724 default: 4725 break; 4726 } 4727 4728 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4729 4730 /* flush pipe on time out */ 4731 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4732 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4733 if (!qg_list) 4734 goto do_aq; 4735 4736 /* set RD bit to indicate that command buffer is provided by the driver 4737 * and it needs to be read by the firmware 4738 */ 4739 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4740 4741 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4742 u16 item_size = struct_size(item, q_id, item->num_qs); 4743 4744 /* If the num of queues is even, add 2 bytes of padding */ 4745 if ((item->num_qs % 2) == 0) 4746 item_size += 2; 4747 4748 sz += item_size; 4749 4750 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4751 } 4752 4753 if (buf_size != sz) 4754 return -EINVAL; 4755 4756 do_aq: 4757 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4758 if (status) { 4759 if (!qg_list) 4760 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4761 vmvf_num, hw->adminq.sq_last_status); 4762 else 4763 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4764 le16_to_cpu(qg_list[0].q_id[0]), 4765 hw->adminq.sq_last_status); 4766 } 4767 return status; 4768 } 4769 4770 /** 4771 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4772 * @hw: pointer to the hardware structure 4773 * @buf: buffer for command 4774 * @buf_size: size of buffer in bytes 4775 * @num_qs: number of queues being configured 4776 * @oldport: origination lport 4777 * @newport: destination lport 4778 * @mode: cmd_type for move to use 4779 * @cd: pointer to command details structure or NULL 4780 * 4781 * Move/Configure LAN Tx queue (0x0C32) 4782 * 4783 * Return: Zero on success, associated error code on failure. 4784 */ 4785 int 4786 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4787 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4788 u8 mode, struct ice_sq_cd *cd) 4789 { 4790 struct ice_aqc_cfg_txqs *cmd; 4791 struct libie_aq_desc desc; 4792 int status; 4793 4794 cmd = libie_aq_raw(&desc); 4795 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4796 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4797 4798 if (!buf) 4799 return -EINVAL; 4800 4801 cmd->cmd_type = mode; 4802 cmd->num_qs = num_qs; 4803 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4804 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4805 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4806 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4807 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4808 cmd->blocked_cgds = 0; 4809 4810 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4811 if (status) 4812 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4813 hw->adminq.sq_last_status); 4814 return status; 4815 } 4816 4817 /** 4818 * ice_aq_add_rdma_qsets 4819 * @hw: pointer to the hardware structure 4820 * @num_qset_grps: Number of RDMA Qset groups 4821 * @qset_list: list of Qset groups to be added 4822 * @buf_size: size of buffer for indirect command 4823 * @cd: pointer to command details structure or NULL 4824 * 4825 * Add Tx RDMA Qsets (0x0C33) 4826 */ 4827 static int 4828 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4829 struct ice_aqc_add_rdma_qset_data *qset_list, 4830 u16 buf_size, struct ice_sq_cd *cd) 4831 { 4832 struct ice_aqc_add_rdma_qset_data *list; 4833 struct ice_aqc_add_rdma_qset *cmd; 4834 struct libie_aq_desc desc; 4835 u16 i, sum_size = 0; 4836 4837 cmd = libie_aq_raw(&desc); 4838 4839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4840 4841 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4842 return -EINVAL; 4843 4844 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4845 u16 num_qsets = le16_to_cpu(list->num_qsets); 4846 4847 sum_size += struct_size(list, rdma_qsets, num_qsets); 4848 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4849 num_qsets); 4850 } 4851 4852 if (buf_size != sum_size) 4853 return -EINVAL; 4854 4855 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4856 4857 cmd->num_qset_grps = num_qset_grps; 4858 4859 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4860 } 4861 4862 /** 4863 * ice_aq_set_txtimeq - set Tx time queues 4864 * @hw: pointer to the hardware structure 4865 * @txtimeq: first Tx time queue id to configure 4866 * @q_count: number of queues to configure 4867 * @txtime_qg: queue group to be set 4868 * @buf_size: size of buffer for indirect command 4869 * @cd: pointer to command details structure or NULL 4870 * 4871 * Set Tx Time queue (0x0C35) 4872 * Return: 0 on success or negative value on failure. 4873 */ 4874 int 4875 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4876 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4877 struct ice_sq_cd *cd) 4878 { 4879 struct ice_aqc_set_txtimeqs *cmd; 4880 struct libie_aq_desc desc; 4881 u16 size; 4882 4883 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4884 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4885 return -EINVAL; 4886 4887 size = struct_size(txtime_qg, txtimeqs, q_count); 4888 if (buf_size != size) 4889 return -EINVAL; 4890 4891 cmd = libie_aq_raw(&desc); 4892 4893 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4894 4895 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4896 4897 cmd->q_id = cpu_to_le16(txtimeq); 4898 cmd->q_amount = cpu_to_le16(q_count); 4899 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4900 } 4901 4902 /* End of FW Admin Queue command wrappers */ 4903 4904 /** 4905 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4906 * @hw: pointer to the HW struct 4907 * @vsi_handle: software VSI handle 4908 * @tc: TC number 4909 * @q_handle: software queue handle 4910 */ 4911 struct ice_q_ctx * 4912 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4913 { 4914 struct ice_vsi_ctx *vsi; 4915 struct ice_q_ctx *q_ctx; 4916 4917 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4918 if (!vsi) 4919 return NULL; 4920 if (q_handle >= vsi->num_lan_q_entries[tc]) 4921 return NULL; 4922 if (!vsi->lan_q_ctx[tc]) 4923 return NULL; 4924 q_ctx = vsi->lan_q_ctx[tc]; 4925 return &q_ctx[q_handle]; 4926 } 4927 4928 /** 4929 * ice_ena_vsi_txq 4930 * @pi: port information structure 4931 * @vsi_handle: software VSI handle 4932 * @tc: TC number 4933 * @q_handle: software queue handle 4934 * @num_qgrps: Number of added queue groups 4935 * @buf: list of queue groups to be added 4936 * @buf_size: size of buffer for indirect command 4937 * @cd: pointer to command details structure or NULL 4938 * 4939 * This function adds one LAN queue 4940 */ 4941 int 4942 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4943 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4944 struct ice_sq_cd *cd) 4945 { 4946 struct ice_aqc_txsched_elem_data node = { 0 }; 4947 struct ice_sched_node *parent; 4948 struct ice_q_ctx *q_ctx; 4949 struct ice_hw *hw; 4950 int status; 4951 4952 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4953 return -EIO; 4954 4955 if (num_qgrps > 1 || buf->num_txqs > 1) 4956 return -ENOSPC; 4957 4958 hw = pi->hw; 4959 4960 if (!ice_is_vsi_valid(hw, vsi_handle)) 4961 return -EINVAL; 4962 4963 mutex_lock(&pi->sched_lock); 4964 4965 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4966 if (!q_ctx) { 4967 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4968 q_handle); 4969 status = -EINVAL; 4970 goto ena_txq_exit; 4971 } 4972 4973 /* find a parent node */ 4974 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4975 ICE_SCHED_NODE_OWNER_LAN); 4976 if (!parent) { 4977 status = -EINVAL; 4978 goto ena_txq_exit; 4979 } 4980 4981 buf->parent_teid = parent->info.node_teid; 4982 node.parent_teid = parent->info.node_teid; 4983 /* Mark that the values in the "generic" section as valid. The default 4984 * value in the "generic" section is zero. This means that : 4985 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4986 * - 0 priority among siblings, indicated by Bit 1-3. 4987 * - WFQ, indicated by Bit 4. 4988 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4989 * Bit 5-6. 4990 * - Bit 7 is reserved. 4991 * Without setting the generic section as valid in valid_sections, the 4992 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4993 */ 4994 buf->txqs[0].info.valid_sections = 4995 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4996 ICE_AQC_ELEM_VALID_EIR; 4997 buf->txqs[0].info.generic = 0; 4998 buf->txqs[0].info.cir_bw.bw_profile_idx = 4999 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5000 buf->txqs[0].info.cir_bw.bw_alloc = 5001 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5002 buf->txqs[0].info.eir_bw.bw_profile_idx = 5003 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5004 buf->txqs[0].info.eir_bw.bw_alloc = 5005 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5006 5007 /* add the LAN queue */ 5008 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5009 if (status) { 5010 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5011 le16_to_cpu(buf->txqs[0].txq_id), 5012 hw->adminq.sq_last_status); 5013 goto ena_txq_exit; 5014 } 5015 5016 node.node_teid = buf->txqs[0].q_teid; 5017 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5018 q_ctx->q_handle = q_handle; 5019 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5020 5021 /* add a leaf node into scheduler tree queue layer */ 5022 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5023 if (!status) 5024 status = ice_sched_replay_q_bw(pi, q_ctx); 5025 5026 ena_txq_exit: 5027 mutex_unlock(&pi->sched_lock); 5028 return status; 5029 } 5030 5031 /** 5032 * ice_dis_vsi_txq 5033 * @pi: port information structure 5034 * @vsi_handle: software VSI handle 5035 * @tc: TC number 5036 * @num_queues: number of queues 5037 * @q_handles: pointer to software queue handle array 5038 * @q_ids: pointer to the q_id array 5039 * @q_teids: pointer to queue node teids 5040 * @rst_src: if called due to reset, specifies the reset source 5041 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5042 * @cd: pointer to command details structure or NULL 5043 * 5044 * This function removes queues and their corresponding nodes in SW DB 5045 */ 5046 int 5047 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5048 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5049 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5050 struct ice_sq_cd *cd) 5051 { 5052 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5053 u16 i, buf_size = __struct_size(qg_list); 5054 struct ice_q_ctx *q_ctx; 5055 int status = -ENOENT; 5056 struct ice_hw *hw; 5057 5058 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5059 return -EIO; 5060 5061 hw = pi->hw; 5062 5063 if (!num_queues) { 5064 /* if queue is disabled already yet the disable queue command 5065 * has to be sent to complete the VF reset, then call 5066 * ice_aq_dis_lan_txq without any queue information 5067 */ 5068 if (rst_src) 5069 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5070 vmvf_num, NULL); 5071 return -EIO; 5072 } 5073 5074 mutex_lock(&pi->sched_lock); 5075 5076 for (i = 0; i < num_queues; i++) { 5077 struct ice_sched_node *node; 5078 5079 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5080 if (!node) 5081 continue; 5082 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5083 if (!q_ctx) { 5084 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5085 q_handles[i]); 5086 continue; 5087 } 5088 if (q_ctx->q_handle != q_handles[i]) { 5089 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5090 q_ctx->q_handle, q_handles[i]); 5091 continue; 5092 } 5093 qg_list->parent_teid = node->info.parent_teid; 5094 qg_list->num_qs = 1; 5095 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5096 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5097 vmvf_num, cd); 5098 5099 if (status) 5100 break; 5101 ice_free_sched_node(pi, node); 5102 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5103 q_ctx->q_teid = ICE_INVAL_TEID; 5104 } 5105 mutex_unlock(&pi->sched_lock); 5106 return status; 5107 } 5108 5109 /** 5110 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5111 * @pi: port information structure 5112 * @vsi_handle: software VSI handle 5113 * @tc_bitmap: TC bitmap 5114 * @maxqs: max queues array per TC 5115 * @owner: LAN or RDMA 5116 * 5117 * This function adds/updates the VSI queues per TC. 5118 */ 5119 static int 5120 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5121 u16 *maxqs, u8 owner) 5122 { 5123 int status = 0; 5124 u8 i; 5125 5126 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5127 return -EIO; 5128 5129 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5130 return -EINVAL; 5131 5132 mutex_lock(&pi->sched_lock); 5133 5134 ice_for_each_traffic_class(i) { 5135 /* configuration is possible only if TC node is present */ 5136 if (!ice_sched_get_tc_node(pi, i)) 5137 continue; 5138 5139 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5140 ice_is_tc_ena(tc_bitmap, i)); 5141 if (status) 5142 break; 5143 } 5144 5145 mutex_unlock(&pi->sched_lock); 5146 return status; 5147 } 5148 5149 /** 5150 * ice_cfg_vsi_lan - configure VSI LAN queues 5151 * @pi: port information structure 5152 * @vsi_handle: software VSI handle 5153 * @tc_bitmap: TC bitmap 5154 * @max_lanqs: max LAN queues array per TC 5155 * 5156 * This function adds/updates the VSI LAN queues per TC. 5157 */ 5158 int 5159 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5160 u16 *max_lanqs) 5161 { 5162 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5163 ICE_SCHED_NODE_OWNER_LAN); 5164 } 5165 5166 /** 5167 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5168 * @pi: port information structure 5169 * @vsi_handle: software VSI handle 5170 * @tc_bitmap: TC bitmap 5171 * @max_rdmaqs: max RDMA queues array per TC 5172 * 5173 * This function adds/updates the VSI RDMA queues per TC. 5174 */ 5175 int 5176 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5177 u16 *max_rdmaqs) 5178 { 5179 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5180 ICE_SCHED_NODE_OWNER_RDMA); 5181 } 5182 5183 /** 5184 * ice_ena_vsi_rdma_qset 5185 * @pi: port information structure 5186 * @vsi_handle: software VSI handle 5187 * @tc: TC number 5188 * @rdma_qset: pointer to RDMA Qset 5189 * @num_qsets: number of RDMA Qsets 5190 * @qset_teid: pointer to Qset node TEIDs 5191 * 5192 * This function adds RDMA Qset 5193 */ 5194 int 5195 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5196 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5197 { 5198 struct ice_aqc_txsched_elem_data node = { 0 }; 5199 struct ice_aqc_add_rdma_qset_data *buf; 5200 struct ice_sched_node *parent; 5201 struct ice_hw *hw; 5202 u16 i, buf_size; 5203 int ret; 5204 5205 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5206 return -EIO; 5207 hw = pi->hw; 5208 5209 if (!ice_is_vsi_valid(hw, vsi_handle)) 5210 return -EINVAL; 5211 5212 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5213 buf = kzalloc(buf_size, GFP_KERNEL); 5214 if (!buf) 5215 return -ENOMEM; 5216 mutex_lock(&pi->sched_lock); 5217 5218 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5219 ICE_SCHED_NODE_OWNER_RDMA); 5220 if (!parent) { 5221 ret = -EINVAL; 5222 goto rdma_error_exit; 5223 } 5224 buf->parent_teid = parent->info.node_teid; 5225 node.parent_teid = parent->info.node_teid; 5226 5227 buf->num_qsets = cpu_to_le16(num_qsets); 5228 for (i = 0; i < num_qsets; i++) { 5229 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5230 buf->rdma_qsets[i].info.valid_sections = 5231 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5232 ICE_AQC_ELEM_VALID_EIR; 5233 buf->rdma_qsets[i].info.generic = 0; 5234 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5235 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5236 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5237 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5238 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5239 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5240 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5241 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5242 } 5243 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5244 if (ret) { 5245 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5246 goto rdma_error_exit; 5247 } 5248 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5249 for (i = 0; i < num_qsets; i++) { 5250 node.node_teid = buf->rdma_qsets[i].qset_teid; 5251 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5252 &node, NULL); 5253 if (ret) 5254 break; 5255 qset_teid[i] = le32_to_cpu(node.node_teid); 5256 } 5257 rdma_error_exit: 5258 mutex_unlock(&pi->sched_lock); 5259 kfree(buf); 5260 return ret; 5261 } 5262 5263 /** 5264 * ice_dis_vsi_rdma_qset - free RDMA resources 5265 * @pi: port_info struct 5266 * @count: number of RDMA Qsets to free 5267 * @qset_teid: TEID of Qset node 5268 * @q_id: list of queue IDs being disabled 5269 */ 5270 int 5271 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5272 u16 *q_id) 5273 { 5274 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5275 u16 qg_size = __struct_size(qg_list); 5276 struct ice_hw *hw; 5277 int status = 0; 5278 int i; 5279 5280 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5281 return -EIO; 5282 5283 hw = pi->hw; 5284 5285 mutex_lock(&pi->sched_lock); 5286 5287 for (i = 0; i < count; i++) { 5288 struct ice_sched_node *node; 5289 5290 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5291 if (!node) 5292 continue; 5293 5294 qg_list->parent_teid = node->info.parent_teid; 5295 qg_list->num_qs = 1; 5296 qg_list->q_id[0] = 5297 cpu_to_le16(q_id[i] | 5298 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5299 5300 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5301 ICE_NO_RESET, 0, NULL); 5302 if (status) 5303 break; 5304 5305 ice_free_sched_node(pi, node); 5306 } 5307 5308 mutex_unlock(&pi->sched_lock); 5309 return status; 5310 } 5311 5312 /** 5313 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5314 * @hw: pointer to the HW struct 5315 * @dpll_idx: index of dpll to be measured 5316 * @meas: array to be filled with results 5317 * @meas_num: max number of results array can hold 5318 * 5319 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5320 * pins on given dpll. 5321 * 5322 * Return: 0 on success or negative value on failure. 5323 */ 5324 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5325 struct ice_cgu_input_measure *meas, 5326 u16 meas_num) 5327 { 5328 struct ice_aqc_get_cgu_input_measure *cmd; 5329 struct libie_aq_desc desc; 5330 5331 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5332 cmd = libie_aq_raw(&desc); 5333 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5334 5335 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5336 } 5337 5338 /** 5339 * ice_aq_get_cgu_abilities - get cgu abilities 5340 * @hw: pointer to the HW struct 5341 * @abilities: CGU abilities 5342 * 5343 * Get CGU abilities (0x0C61) 5344 * Return: 0 on success or negative value on failure. 5345 */ 5346 int 5347 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5348 struct ice_aqc_get_cgu_abilities *abilities) 5349 { 5350 struct libie_aq_desc desc; 5351 5352 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5353 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5354 } 5355 5356 /** 5357 * ice_aq_set_input_pin_cfg - set input pin config 5358 * @hw: pointer to the HW struct 5359 * @input_idx: Input index 5360 * @flags1: Input flags 5361 * @flags2: Input flags 5362 * @freq: Frequency in Hz 5363 * @phase_delay: Delay in ps 5364 * 5365 * Set CGU input config (0x0C62) 5366 * Return: 0 on success or negative value on failure. 5367 */ 5368 int 5369 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5370 u32 freq, s32 phase_delay) 5371 { 5372 struct ice_aqc_set_cgu_input_config *cmd; 5373 struct libie_aq_desc desc; 5374 5375 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5376 cmd = libie_aq_raw(&desc); 5377 cmd->input_idx = input_idx; 5378 cmd->flags1 = flags1; 5379 cmd->flags2 = flags2; 5380 cmd->freq = cpu_to_le32(freq); 5381 cmd->phase_delay = cpu_to_le32(phase_delay); 5382 5383 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5384 } 5385 5386 /** 5387 * ice_aq_get_input_pin_cfg - get input pin config 5388 * @hw: pointer to the HW struct 5389 * @input_idx: Input index 5390 * @status: Pin status 5391 * @type: Pin type 5392 * @flags1: Input flags 5393 * @flags2: Input flags 5394 * @freq: Frequency in Hz 5395 * @phase_delay: Delay in ps 5396 * 5397 * Get CGU input config (0x0C63) 5398 * Return: 0 on success or negative value on failure. 5399 */ 5400 int 5401 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5402 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5403 { 5404 struct ice_aqc_get_cgu_input_config *cmd; 5405 struct libie_aq_desc desc; 5406 int ret; 5407 5408 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5409 cmd = libie_aq_raw(&desc); 5410 cmd->input_idx = input_idx; 5411 5412 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5413 if (!ret) { 5414 if (status) 5415 *status = cmd->status; 5416 if (type) 5417 *type = cmd->type; 5418 if (flags1) 5419 *flags1 = cmd->flags1; 5420 if (flags2) 5421 *flags2 = cmd->flags2; 5422 if (freq) 5423 *freq = le32_to_cpu(cmd->freq); 5424 if (phase_delay) 5425 *phase_delay = le32_to_cpu(cmd->phase_delay); 5426 } 5427 5428 return ret; 5429 } 5430 5431 /** 5432 * ice_aq_set_output_pin_cfg - set output pin config 5433 * @hw: pointer to the HW struct 5434 * @output_idx: Output index 5435 * @flags: Output flags 5436 * @src_sel: Index of DPLL block 5437 * @freq: Output frequency 5438 * @phase_delay: Output phase compensation 5439 * 5440 * Set CGU output config (0x0C64) 5441 * Return: 0 on success or negative value on failure. 5442 */ 5443 int 5444 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5445 u8 src_sel, u32 freq, s32 phase_delay) 5446 { 5447 struct ice_aqc_set_cgu_output_config *cmd; 5448 struct libie_aq_desc desc; 5449 5450 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5451 cmd = libie_aq_raw(&desc); 5452 cmd->output_idx = output_idx; 5453 cmd->flags = flags; 5454 cmd->src_sel = src_sel; 5455 cmd->freq = cpu_to_le32(freq); 5456 cmd->phase_delay = cpu_to_le32(phase_delay); 5457 5458 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5459 } 5460 5461 /** 5462 * ice_aq_get_output_pin_cfg - get output pin config 5463 * @hw: pointer to the HW struct 5464 * @output_idx: Output index 5465 * @flags: Output flags 5466 * @src_sel: Internal DPLL source 5467 * @freq: Output frequency 5468 * @src_freq: Source frequency 5469 * 5470 * Get CGU output config (0x0C65) 5471 * Return: 0 on success or negative value on failure. 5472 */ 5473 int 5474 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5475 u8 *src_sel, u32 *freq, u32 *src_freq) 5476 { 5477 struct ice_aqc_get_cgu_output_config *cmd; 5478 struct libie_aq_desc desc; 5479 int ret; 5480 5481 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5482 cmd = libie_aq_raw(&desc); 5483 cmd->output_idx = output_idx; 5484 5485 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5486 if (!ret) { 5487 if (flags) 5488 *flags = cmd->flags; 5489 if (src_sel) 5490 *src_sel = cmd->src_sel; 5491 if (freq) 5492 *freq = le32_to_cpu(cmd->freq); 5493 if (src_freq) 5494 *src_freq = le32_to_cpu(cmd->src_freq); 5495 } 5496 5497 return ret; 5498 } 5499 5500 /** 5501 * ice_aq_get_cgu_dpll_status - get dpll status 5502 * @hw: pointer to the HW struct 5503 * @dpll_num: DPLL index 5504 * @ref_state: Reference clock state 5505 * @config: current DPLL config 5506 * @dpll_state: current DPLL state 5507 * @phase_offset: Phase offset in ns 5508 * @eec_mode: EEC_mode 5509 * 5510 * Get CGU DPLL status (0x0C66) 5511 * Return: 0 on success or negative value on failure. 5512 */ 5513 int 5514 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5515 u8 *dpll_state, u8 *config, s64 *phase_offset, 5516 u8 *eec_mode) 5517 { 5518 struct ice_aqc_get_cgu_dpll_status *cmd; 5519 struct libie_aq_desc desc; 5520 int status; 5521 5522 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5523 cmd = libie_aq_raw(&desc); 5524 cmd->dpll_num = dpll_num; 5525 5526 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5527 if (!status) { 5528 *ref_state = cmd->ref_state; 5529 *dpll_state = cmd->dpll_state; 5530 *config = cmd->config; 5531 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5532 *phase_offset <<= 32; 5533 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5534 *phase_offset = sign_extend64(*phase_offset, 47); 5535 *eec_mode = cmd->eec_mode; 5536 } 5537 5538 return status; 5539 } 5540 5541 /** 5542 * ice_aq_set_cgu_dpll_config - set dpll config 5543 * @hw: pointer to the HW struct 5544 * @dpll_num: DPLL index 5545 * @ref_state: Reference clock state 5546 * @config: DPLL config 5547 * @eec_mode: EEC mode 5548 * 5549 * Set CGU DPLL config (0x0C67) 5550 * Return: 0 on success or negative value on failure. 5551 */ 5552 int 5553 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5554 u8 config, u8 eec_mode) 5555 { 5556 struct ice_aqc_set_cgu_dpll_config *cmd; 5557 struct libie_aq_desc desc; 5558 5559 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5560 cmd = libie_aq_raw(&desc); 5561 cmd->dpll_num = dpll_num; 5562 cmd->ref_state = ref_state; 5563 cmd->config = config; 5564 cmd->eec_mode = eec_mode; 5565 5566 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5567 } 5568 5569 /** 5570 * ice_aq_set_cgu_ref_prio - set input reference priority 5571 * @hw: pointer to the HW struct 5572 * @dpll_num: DPLL index 5573 * @ref_idx: Reference pin index 5574 * @ref_priority: Reference input priority 5575 * 5576 * Set CGU reference priority (0x0C68) 5577 * Return: 0 on success or negative value on failure. 5578 */ 5579 int 5580 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5581 u8 ref_priority) 5582 { 5583 struct ice_aqc_set_cgu_ref_prio *cmd; 5584 struct libie_aq_desc desc; 5585 5586 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5587 cmd = libie_aq_raw(&desc); 5588 cmd->dpll_num = dpll_num; 5589 cmd->ref_idx = ref_idx; 5590 cmd->ref_priority = ref_priority; 5591 5592 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5593 } 5594 5595 /** 5596 * ice_aq_get_cgu_ref_prio - get input reference priority 5597 * @hw: pointer to the HW struct 5598 * @dpll_num: DPLL index 5599 * @ref_idx: Reference pin index 5600 * @ref_prio: Reference input priority 5601 * 5602 * Get CGU reference priority (0x0C69) 5603 * Return: 0 on success or negative value on failure. 5604 */ 5605 int 5606 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5607 u8 *ref_prio) 5608 { 5609 struct ice_aqc_get_cgu_ref_prio *cmd; 5610 struct libie_aq_desc desc; 5611 int status; 5612 5613 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5614 cmd = libie_aq_raw(&desc); 5615 cmd->dpll_num = dpll_num; 5616 cmd->ref_idx = ref_idx; 5617 5618 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5619 if (!status) 5620 *ref_prio = cmd->ref_priority; 5621 5622 return status; 5623 } 5624 5625 /** 5626 * ice_aq_get_cgu_info - get cgu info 5627 * @hw: pointer to the HW struct 5628 * @cgu_id: CGU ID 5629 * @cgu_cfg_ver: CGU config version 5630 * @cgu_fw_ver: CGU firmware version 5631 * 5632 * Get CGU info (0x0C6A) 5633 * Return: 0 on success or negative value on failure. 5634 */ 5635 int 5636 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5637 u32 *cgu_fw_ver) 5638 { 5639 struct ice_aqc_get_cgu_info *cmd; 5640 struct libie_aq_desc desc; 5641 int status; 5642 5643 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5644 cmd = libie_aq_raw(&desc); 5645 5646 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5647 if (!status) { 5648 *cgu_id = le32_to_cpu(cmd->cgu_id); 5649 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5650 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5651 } 5652 5653 return status; 5654 } 5655 5656 /** 5657 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5658 * @hw: pointer to the HW struct 5659 * @phy_output: PHY reference clock output pin 5660 * @enable: GPIO state to be applied 5661 * @freq: PHY output frequency 5662 * 5663 * Set phy recovered clock as reference (0x0630) 5664 * Return: 0 on success or negative value on failure. 5665 */ 5666 int 5667 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5668 u32 *freq) 5669 { 5670 struct ice_aqc_set_phy_rec_clk_out *cmd; 5671 struct libie_aq_desc desc; 5672 int status; 5673 5674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5675 cmd = libie_aq_raw(&desc); 5676 cmd->phy_output = phy_output; 5677 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5678 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5679 cmd->freq = cpu_to_le32(*freq); 5680 5681 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5682 if (!status) 5683 *freq = le32_to_cpu(cmd->freq); 5684 5685 return status; 5686 } 5687 5688 /** 5689 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5690 * @hw: pointer to the HW struct 5691 * @phy_output: PHY reference clock output pin 5692 * @port_num: Port number 5693 * @flags: PHY flags 5694 * @node_handle: PHY output frequency 5695 * 5696 * Get PHY recovered clock output info (0x0631) 5697 * Return: 0 on success or negative value on failure. 5698 */ 5699 int 5700 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5701 u8 *flags, u16 *node_handle) 5702 { 5703 struct ice_aqc_get_phy_rec_clk_out *cmd; 5704 struct libie_aq_desc desc; 5705 int status; 5706 5707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5708 cmd = libie_aq_raw(&desc); 5709 cmd->phy_output = *phy_output; 5710 5711 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5712 if (!status) { 5713 *phy_output = cmd->phy_output; 5714 if (port_num) 5715 *port_num = cmd->port_num; 5716 if (flags) 5717 *flags = cmd->flags; 5718 if (node_handle) 5719 *node_handle = le16_to_cpu(cmd->node_handle); 5720 } 5721 5722 return status; 5723 } 5724 5725 /** 5726 * ice_aq_get_sensor_reading 5727 * @hw: pointer to the HW struct 5728 * @data: pointer to data to be read from the sensor 5729 * 5730 * Get sensor reading (0x0632) 5731 */ 5732 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5733 struct ice_aqc_get_sensor_reading_resp *data) 5734 { 5735 struct ice_aqc_get_sensor_reading *cmd; 5736 struct libie_aq_desc desc; 5737 int status; 5738 5739 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5740 cmd = libie_aq_raw(&desc); 5741 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5742 #define ICE_INTERNAL_TEMP_SENSOR 0 5743 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5744 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5745 5746 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5747 if (!status) 5748 memcpy(data, &desc.params.raw, 5749 sizeof(*data)); 5750 5751 return status; 5752 } 5753 5754 /** 5755 * ice_replay_pre_init - replay pre initialization 5756 * @hw: pointer to the HW struct 5757 * 5758 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5759 */ 5760 static int ice_replay_pre_init(struct ice_hw *hw) 5761 { 5762 struct ice_switch_info *sw = hw->switch_info; 5763 u8 i; 5764 5765 /* Delete old entries from replay filter list head if there is any */ 5766 ice_rm_all_sw_replay_rule_info(hw); 5767 /* In start of replay, move entries into replay_rules list, it 5768 * will allow adding rules entries back to filt_rules list, 5769 * which is operational list. 5770 */ 5771 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5772 list_replace_init(&sw->recp_list[i].filt_rules, 5773 &sw->recp_list[i].filt_replay_rules); 5774 ice_sched_replay_agg_vsi_preinit(hw); 5775 5776 return 0; 5777 } 5778 5779 /** 5780 * ice_replay_vsi - replay VSI configuration 5781 * @hw: pointer to the HW struct 5782 * @vsi_handle: driver VSI handle 5783 * 5784 * Restore all VSI configuration after reset. It is required to call this 5785 * function with main VSI first. 5786 */ 5787 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5788 { 5789 int status; 5790 5791 if (!ice_is_vsi_valid(hw, vsi_handle)) 5792 return -EINVAL; 5793 5794 /* Replay pre-initialization if there is any */ 5795 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5796 status = ice_replay_pre_init(hw); 5797 if (status) 5798 return status; 5799 } 5800 /* Replay per VSI all RSS configurations */ 5801 status = ice_replay_rss_cfg(hw, vsi_handle); 5802 if (status) 5803 return status; 5804 /* Replay per VSI all filters */ 5805 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5806 if (!status) 5807 status = ice_replay_vsi_agg(hw, vsi_handle); 5808 return status; 5809 } 5810 5811 /** 5812 * ice_replay_post - post replay configuration cleanup 5813 * @hw: pointer to the HW struct 5814 * 5815 * Post replay cleanup. 5816 */ 5817 void ice_replay_post(struct ice_hw *hw) 5818 { 5819 /* Delete old entries from replay filter list head */ 5820 ice_rm_all_sw_replay_rule_info(hw); 5821 ice_sched_replay_agg(hw); 5822 } 5823 5824 /** 5825 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5826 * @hw: ptr to the hardware info 5827 * @reg: offset of 64 bit HW register to read from 5828 * @prev_stat_loaded: bool to specify if previous stats are loaded 5829 * @prev_stat: ptr to previous loaded stat value 5830 * @cur_stat: ptr to current stat value 5831 */ 5832 void 5833 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5834 u64 *prev_stat, u64 *cur_stat) 5835 { 5836 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5837 5838 /* device stats are not reset at PFR, they likely will not be zeroed 5839 * when the driver starts. Thus, save the value from the first read 5840 * without adding to the statistic value so that we report stats which 5841 * count up from zero. 5842 */ 5843 if (!prev_stat_loaded) { 5844 *prev_stat = new_data; 5845 return; 5846 } 5847 5848 /* Calculate the difference between the new and old values, and then 5849 * add it to the software stat value. 5850 */ 5851 if (new_data >= *prev_stat) 5852 *cur_stat += new_data - *prev_stat; 5853 else 5854 /* to manage the potential roll-over */ 5855 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5856 5857 /* Update the previously stored value to prepare for next read */ 5858 *prev_stat = new_data; 5859 } 5860 5861 /** 5862 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5863 * @hw: ptr to the hardware info 5864 * @reg: offset of HW register to read from 5865 * @prev_stat_loaded: bool to specify if previous stats are loaded 5866 * @prev_stat: ptr to previous loaded stat value 5867 * @cur_stat: ptr to current stat value 5868 */ 5869 void 5870 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5871 u64 *prev_stat, u64 *cur_stat) 5872 { 5873 u32 new_data; 5874 5875 new_data = rd32(hw, reg); 5876 5877 /* device stats are not reset at PFR, they likely will not be zeroed 5878 * when the driver starts. Thus, save the value from the first read 5879 * without adding to the statistic value so that we report stats which 5880 * count up from zero. 5881 */ 5882 if (!prev_stat_loaded) { 5883 *prev_stat = new_data; 5884 return; 5885 } 5886 5887 /* Calculate the difference between the new and old values, and then 5888 * add it to the software stat value. 5889 */ 5890 if (new_data >= *prev_stat) 5891 *cur_stat += new_data - *prev_stat; 5892 else 5893 /* to manage the potential roll-over */ 5894 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5895 5896 /* Update the previously stored value to prepare for next read */ 5897 *prev_stat = new_data; 5898 } 5899 5900 /** 5901 * ice_sched_query_elem - query element information from HW 5902 * @hw: pointer to the HW struct 5903 * @node_teid: node TEID to be queried 5904 * @buf: buffer to element information 5905 * 5906 * This function queries HW element information 5907 */ 5908 int 5909 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5910 struct ice_aqc_txsched_elem_data *buf) 5911 { 5912 u16 buf_size, num_elem_ret = 0; 5913 int status; 5914 5915 buf_size = sizeof(*buf); 5916 memset(buf, 0, buf_size); 5917 buf->node_teid = cpu_to_le32(node_teid); 5918 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5919 NULL); 5920 if (status || num_elem_ret != 1) 5921 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5922 return status; 5923 } 5924 5925 /** 5926 * ice_aq_read_i2c 5927 * @hw: pointer to the hw struct 5928 * @topo_addr: topology address for a device to communicate with 5929 * @bus_addr: 7-bit I2C bus address 5930 * @addr: I2C memory address (I2C offset) with up to 16 bits 5931 * @params: I2C parameters: bit [7] - Repeated start, 5932 * bits [6:5] data offset size, 5933 * bit [4] - I2C address type, 5934 * bits [3:0] - data size to read (0-16 bytes) 5935 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5936 * @cd: pointer to command details structure or NULL 5937 * 5938 * Read I2C (0x06E2) 5939 */ 5940 int 5941 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5942 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5943 struct ice_sq_cd *cd) 5944 { 5945 struct libie_aq_desc desc = { 0 }; 5946 struct ice_aqc_i2c *cmd; 5947 u8 data_size; 5948 int status; 5949 5950 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5951 cmd = libie_aq_raw(&desc); 5952 5953 if (!data) 5954 return -EINVAL; 5955 5956 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5957 5958 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5959 cmd->topo_addr = topo_addr; 5960 cmd->i2c_params = params; 5961 cmd->i2c_addr = addr; 5962 5963 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5964 if (!status) { 5965 struct ice_aqc_read_i2c_resp *resp; 5966 u8 i; 5967 5968 resp = libie_aq_raw(&desc); 5969 for (i = 0; i < data_size; i++) { 5970 *data = resp->i2c_data[i]; 5971 data++; 5972 } 5973 } 5974 5975 return status; 5976 } 5977 5978 /** 5979 * ice_aq_write_i2c 5980 * @hw: pointer to the hw struct 5981 * @topo_addr: topology address for a device to communicate with 5982 * @bus_addr: 7-bit I2C bus address 5983 * @addr: I2C memory address (I2C offset) with up to 16 bits 5984 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5985 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5986 * @cd: pointer to command details structure or NULL 5987 * 5988 * Write I2C (0x06E3) 5989 * 5990 * * Return: 5991 * * 0 - Successful write to the i2c device 5992 * * -EINVAL - Data size greater than 4 bytes 5993 * * -EIO - FW error 5994 */ 5995 int 5996 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5997 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5998 struct ice_sq_cd *cd) 5999 { 6000 struct libie_aq_desc desc = { 0 }; 6001 struct ice_aqc_i2c *cmd; 6002 u8 data_size; 6003 6004 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6005 cmd = libie_aq_raw(&desc); 6006 6007 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6008 6009 /* data_size limited to 4 */ 6010 if (data_size > 4) 6011 return -EINVAL; 6012 6013 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6014 cmd->topo_addr = topo_addr; 6015 cmd->i2c_params = params; 6016 cmd->i2c_addr = addr; 6017 6018 memcpy(cmd->i2c_data, data, data_size); 6019 6020 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6021 } 6022 6023 /** 6024 * ice_get_pca9575_handle - find and return the PCA9575 controller 6025 * @hw: pointer to the hw struct 6026 * @pca9575_handle: GPIO controller's handle 6027 * 6028 * Find and return the GPIO controller's handle in the netlist. 6029 * When found - the value will be cached in the hw structure and following calls 6030 * will return cached value. 6031 * 6032 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6033 */ 6034 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6035 { 6036 struct ice_aqc_get_link_topo *cmd; 6037 struct libie_aq_desc desc; 6038 int err; 6039 u8 idx; 6040 6041 /* If handle was read previously return cached value */ 6042 if (hw->io_expander_handle) { 6043 *pca9575_handle = hw->io_expander_handle; 6044 return 0; 6045 } 6046 6047 #define SW_PCA9575_SFP_TOPO_IDX 2 6048 #define SW_PCA9575_QSFP_TOPO_IDX 1 6049 6050 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6051 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6052 idx = SW_PCA9575_SFP_TOPO_IDX; 6053 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6054 idx = SW_PCA9575_QSFP_TOPO_IDX; 6055 else 6056 return -ENXIO; 6057 6058 /* If handle was not detected read it from the netlist */ 6059 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6060 cmd = libie_aq_raw(&desc); 6061 cmd->addr.topo_params.node_type_ctx = 6062 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6063 cmd->addr.topo_params.index = idx; 6064 6065 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6066 if (err) 6067 return -ENXIO; 6068 6069 /* Verify if we found the right IO expander type */ 6070 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6071 return -ENXIO; 6072 6073 /* If present save the handle and return it */ 6074 hw->io_expander_handle = 6075 le16_to_cpu(cmd->addr.handle); 6076 *pca9575_handle = hw->io_expander_handle; 6077 6078 return 0; 6079 } 6080 6081 /** 6082 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6083 * @hw: pointer to the hw struct 6084 * @offset: GPIO controller register offset 6085 * @data: pointer to data to be read from the GPIO controller 6086 * 6087 * Return: 0 on success, negative error code otherwise. 6088 */ 6089 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6090 { 6091 struct ice_aqc_link_topo_addr link_topo; 6092 __le16 addr; 6093 u16 handle; 6094 int err; 6095 6096 memset(&link_topo, 0, sizeof(link_topo)); 6097 6098 err = ice_get_pca9575_handle(hw, &handle); 6099 if (err) 6100 return err; 6101 6102 link_topo.handle = cpu_to_le16(handle); 6103 link_topo.topo_params.node_type_ctx = 6104 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6105 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6106 6107 addr = cpu_to_le16((u16)offset); 6108 6109 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6110 } 6111 6112 /** 6113 * ice_aq_set_gpio 6114 * @hw: pointer to the hw struct 6115 * @gpio_ctrl_handle: GPIO controller node handle 6116 * @pin_idx: IO Number of the GPIO that needs to be set 6117 * @value: SW provide IO value to set in the LSB 6118 * @cd: pointer to command details structure or NULL 6119 * 6120 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6121 */ 6122 int 6123 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6124 struct ice_sq_cd *cd) 6125 { 6126 struct libie_aq_desc desc; 6127 struct ice_aqc_gpio *cmd; 6128 6129 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6130 cmd = libie_aq_raw(&desc); 6131 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6132 cmd->gpio_num = pin_idx; 6133 cmd->gpio_val = value ? 1 : 0; 6134 6135 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6136 } 6137 6138 /** 6139 * ice_aq_get_gpio 6140 * @hw: pointer to the hw struct 6141 * @gpio_ctrl_handle: GPIO controller node handle 6142 * @pin_idx: IO Number of the GPIO that needs to be set 6143 * @value: IO value read 6144 * @cd: pointer to command details structure or NULL 6145 * 6146 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6147 * the topology 6148 */ 6149 int 6150 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6151 bool *value, struct ice_sq_cd *cd) 6152 { 6153 struct libie_aq_desc desc; 6154 struct ice_aqc_gpio *cmd; 6155 int status; 6156 6157 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6158 cmd = libie_aq_raw(&desc); 6159 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6160 cmd->gpio_num = pin_idx; 6161 6162 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6163 if (status) 6164 return status; 6165 6166 *value = !!cmd->gpio_val; 6167 return 0; 6168 } 6169 6170 /** 6171 * ice_is_fw_api_min_ver 6172 * @hw: pointer to the hardware structure 6173 * @maj: major version 6174 * @min: minor version 6175 * @patch: patch version 6176 * 6177 * Checks if the firmware API is minimum version 6178 */ 6179 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6180 { 6181 if (hw->api_maj_ver == maj) { 6182 if (hw->api_min_ver > min) 6183 return true; 6184 if (hw->api_min_ver == min && hw->api_patch >= patch) 6185 return true; 6186 } else if (hw->api_maj_ver > maj) { 6187 return true; 6188 } 6189 6190 return false; 6191 } 6192 6193 /** 6194 * ice_fw_supports_link_override 6195 * @hw: pointer to the hardware structure 6196 * 6197 * Checks if the firmware supports link override 6198 */ 6199 bool ice_fw_supports_link_override(struct ice_hw *hw) 6200 { 6201 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6202 ICE_FW_API_LINK_OVERRIDE_MIN, 6203 ICE_FW_API_LINK_OVERRIDE_PATCH); 6204 } 6205 6206 /** 6207 * ice_get_link_default_override 6208 * @ldo: pointer to the link default override struct 6209 * @pi: pointer to the port info struct 6210 * 6211 * Gets the link default override for a port 6212 */ 6213 int 6214 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6215 struct ice_port_info *pi) 6216 { 6217 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6218 struct ice_hw *hw = pi->hw; 6219 int status; 6220 6221 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6222 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6223 if (status) { 6224 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6225 return status; 6226 } 6227 6228 /* Each port has its own config; calculate for our port */ 6229 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6230 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6231 6232 /* link options first */ 6233 status = ice_read_sr_word(hw, tlv_start, &buf); 6234 if (status) { 6235 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6236 return status; 6237 } 6238 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6239 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6240 ICE_LINK_OVERRIDE_PHY_CFG_S; 6241 6242 /* link PHY config */ 6243 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6244 status = ice_read_sr_word(hw, offset, &buf); 6245 if (status) { 6246 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6247 return status; 6248 } 6249 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6250 6251 /* PHY types low */ 6252 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6253 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6254 status = ice_read_sr_word(hw, (offset + i), &buf); 6255 if (status) { 6256 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6257 return status; 6258 } 6259 /* shift 16 bits at a time to fill 64 bits */ 6260 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6261 } 6262 6263 /* PHY types high */ 6264 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6265 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6266 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6267 status = ice_read_sr_word(hw, (offset + i), &buf); 6268 if (status) { 6269 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6270 return status; 6271 } 6272 /* shift 16 bits at a time to fill 64 bits */ 6273 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6274 } 6275 6276 return status; 6277 } 6278 6279 /** 6280 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6281 * @caps: get PHY capability data 6282 */ 6283 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6284 { 6285 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6286 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6287 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6288 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6289 return true; 6290 6291 return false; 6292 } 6293 6294 /** 6295 * ice_is_fw_health_report_supported - checks if firmware supports health events 6296 * @hw: pointer to the hardware structure 6297 * 6298 * Return: true if firmware supports health status reports, 6299 * false otherwise 6300 */ 6301 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6302 { 6303 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6304 ICE_FW_API_HEALTH_REPORT_MIN, 6305 ICE_FW_API_HEALTH_REPORT_PATCH); 6306 } 6307 6308 /** 6309 * ice_aq_set_health_status_cfg - Configure FW health events 6310 * @hw: pointer to the HW struct 6311 * @event_source: type of diagnostic events to enable 6312 * 6313 * Configure the health status event types that the firmware will send to this 6314 * PF. The supported event types are: PF-specific, all PFs, and global. 6315 * 6316 * Return: 0 on success, negative error code otherwise. 6317 */ 6318 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6319 { 6320 struct ice_aqc_set_health_status_cfg *cmd; 6321 struct libie_aq_desc desc; 6322 6323 cmd = libie_aq_raw(&desc); 6324 6325 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6326 6327 cmd->event_source = event_source; 6328 6329 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6330 } 6331 6332 /** 6333 * ice_aq_set_lldp_mib - Set the LLDP MIB 6334 * @hw: pointer to the HW struct 6335 * @mib_type: Local, Remote or both Local and Remote MIBs 6336 * @buf: pointer to the caller-supplied buffer to store the MIB block 6337 * @buf_size: size of the buffer (in bytes) 6338 * @cd: pointer to command details structure or NULL 6339 * 6340 * Set the LLDP MIB. (0x0A08) 6341 */ 6342 int 6343 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6344 struct ice_sq_cd *cd) 6345 { 6346 struct ice_aqc_lldp_set_local_mib *cmd; 6347 struct libie_aq_desc desc; 6348 6349 cmd = libie_aq_raw(&desc); 6350 6351 if (buf_size == 0 || !buf) 6352 return -EINVAL; 6353 6354 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6355 6356 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6357 desc.datalen = cpu_to_le16(buf_size); 6358 6359 cmd->type = mib_type; 6360 cmd->length = cpu_to_le16(buf_size); 6361 6362 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6363 } 6364 6365 /** 6366 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6367 * @hw: pointer to HW struct 6368 */ 6369 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6370 { 6371 if (hw->mac_type != ICE_MAC_E810) 6372 return false; 6373 6374 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6375 ICE_FW_API_LLDP_FLTR_MIN, 6376 ICE_FW_API_LLDP_FLTR_PATCH); 6377 } 6378 6379 /** 6380 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6381 * @hw: pointer to HW struct 6382 * @vsi: VSI to add the filter to 6383 * @add: boolean for if adding or removing a filter 6384 * 6385 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6386 * with this HW or VSI, otherwise an error corresponding to 6387 * the AQ transaction result. 6388 */ 6389 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6390 { 6391 struct ice_aqc_lldp_filter_ctrl *cmd; 6392 struct libie_aq_desc desc; 6393 6394 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6395 return -EOPNOTSUPP; 6396 6397 cmd = libie_aq_raw(&desc); 6398 6399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6400 6401 if (add) 6402 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6403 else 6404 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6405 6406 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6407 6408 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6409 } 6410 6411 /** 6412 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6413 * @hw: pointer to HW struct 6414 */ 6415 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6416 { 6417 struct libie_aq_desc desc; 6418 6419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6420 6421 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6422 } 6423 6424 /** 6425 * ice_fw_supports_report_dflt_cfg 6426 * @hw: pointer to the hardware structure 6427 * 6428 * Checks if the firmware supports report default configuration 6429 */ 6430 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6431 { 6432 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6433 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6434 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6435 } 6436 6437 /* each of the indexes into the following array match the speed of a return 6438 * value from the list of AQ returned speeds like the range: 6439 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6440 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6441 * array. The array is defined as 15 elements long because the link_speed 6442 * returned by the firmware is a 16 bit * value, but is indexed 6443 * by [fls(speed) - 1] 6444 */ 6445 static const u32 ice_aq_to_link_speed[] = { 6446 SPEED_10, /* BIT(0) */ 6447 SPEED_100, 6448 SPEED_1000, 6449 SPEED_2500, 6450 SPEED_5000, 6451 SPEED_10000, 6452 SPEED_20000, 6453 SPEED_25000, 6454 SPEED_40000, 6455 SPEED_50000, 6456 SPEED_100000, /* BIT(10) */ 6457 SPEED_200000, 6458 }; 6459 6460 /** 6461 * ice_get_link_speed - get integer speed from table 6462 * @index: array index from fls(aq speed) - 1 6463 * 6464 * Returns: u32 value containing integer speed 6465 */ 6466 u32 ice_get_link_speed(u16 index) 6467 { 6468 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6469 return 0; 6470 6471 return ice_aq_to_link_speed[index]; 6472 } 6473 6474 /** 6475 * ice_get_dest_cgu - get destination CGU dev for given HW 6476 * @hw: pointer to the HW struct 6477 * 6478 * Get CGU client id for CGU register read/write operations. 6479 * 6480 * Return: CGU device id to use in SBQ transactions. 6481 */ 6482 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6483 { 6484 /* On dual complex E825 only complex 0 has functional CGU powering all 6485 * the PHYs. 6486 * SBQ destination device cgu points to CGU on a current complex and to 6487 * access primary CGU from the secondary complex, the driver should use 6488 * cgu_peer as a destination device. 6489 */ 6490 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6491 !ice_is_primary(hw)) 6492 return ice_sbq_dev_cgu_peer; 6493 return ice_sbq_dev_cgu; 6494 } 6495 6496 /** 6497 * ice_read_cgu_reg - Read a CGU register 6498 * @hw: Pointer to the HW struct 6499 * @addr: Register address to read 6500 * @val: Storage for register value read 6501 * 6502 * Read the contents of a register of the Clock Generation Unit. Only 6503 * applicable to E82X devices. 6504 * 6505 * Return: 0 on success, other error codes when failed to read from CGU. 6506 */ 6507 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6508 { 6509 struct ice_sbq_msg_input cgu_msg = { 6510 .dest_dev = ice_get_dest_cgu(hw), 6511 .opcode = ice_sbq_msg_rd, 6512 .msg_addr_low = addr 6513 }; 6514 int err; 6515 6516 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6517 if (err) { 6518 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6519 addr, err); 6520 return err; 6521 } 6522 6523 *val = cgu_msg.data; 6524 6525 return 0; 6526 } 6527 6528 /** 6529 * ice_write_cgu_reg - Write a CGU register 6530 * @hw: Pointer to the HW struct 6531 * @addr: Register address to write 6532 * @val: Value to write into the register 6533 * 6534 * Write the specified value to a register of the Clock Generation Unit. Only 6535 * applicable to E82X devices. 6536 * 6537 * Return: 0 on success, other error codes when failed to write to CGU. 6538 */ 6539 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6540 { 6541 struct ice_sbq_msg_input cgu_msg = { 6542 .dest_dev = ice_get_dest_cgu(hw), 6543 .opcode = ice_sbq_msg_wr, 6544 .msg_addr_low = addr, 6545 .data = val 6546 }; 6547 int err; 6548 6549 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6550 if (err) 6551 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6552 addr, err); 6553 6554 return err; 6555 } 6556