1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473 } 474 475 /** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496 { 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520 } 521 522 /** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529 static bool ice_is_media_cage_present(struct ice_port_info *pi) 530 { 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538 } 539 540 /** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545 { 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655 } 656 657 /** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665 { 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673 } 674 675 /** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684 int 685 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687 { 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775 } 776 777 /** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785 static void 786 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788 { 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824 } 825 826 /** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834 int 835 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 { 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852 } 853 854 /** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859 { 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882 } 883 884 /** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889 { 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932 } 933 934 /** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942 { 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958 } 959 960 /** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968 { 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985 } 986 987 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 988 u16 size) 989 { 990 struct ice_hw *hw = priv; 991 992 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 993 } 994 995 static int __fwlog_init(struct ice_hw *hw) 996 { 997 struct ice_pf *pf = hw->back; 998 struct libie_fwlog_api api = { 999 .pdev = pf->pdev, 1000 .send_cmd = __fwlog_send_cmd, 1001 .priv = hw, 1002 }; 1003 int err; 1004 1005 /* only support fw log commands on PF 0 */ 1006 if (hw->bus.func) 1007 return -EINVAL; 1008 1009 err = ice_debugfs_pf_init(pf); 1010 if (err) 1011 return err; 1012 1013 api.debugfs_root = pf->ice_debugfs_pf; 1014 1015 return libie_fwlog_init(&hw->fwlog, &api); 1016 } 1017 1018 /** 1019 * ice_init_hw - main hardware initialization routine 1020 * @hw: pointer to the hardware structure 1021 */ 1022 int ice_init_hw(struct ice_hw *hw) 1023 { 1024 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1025 void *mac_buf __free(kfree) = NULL; 1026 u16 mac_buf_len; 1027 int status; 1028 1029 /* Set MAC type based on DeviceID */ 1030 status = ice_set_mac_type(hw); 1031 if (status) 1032 return status; 1033 1034 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1035 1036 status = ice_reset(hw, ICE_RESET_PFR); 1037 if (status) 1038 return status; 1039 1040 ice_get_itr_intrl_gran(hw); 1041 1042 status = ice_create_all_ctrlq(hw); 1043 if (status) 1044 goto err_unroll_cqinit; 1045 1046 status = __fwlog_init(hw); 1047 if (status) 1048 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1049 status); 1050 1051 status = ice_clear_pf_cfg(hw); 1052 if (status) 1053 goto err_unroll_cqinit; 1054 1055 /* Set bit to enable Flow Director filters */ 1056 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1057 INIT_LIST_HEAD(&hw->fdir_list_head); 1058 1059 ice_clear_pxe_mode(hw); 1060 1061 status = ice_init_nvm(hw); 1062 if (status) 1063 goto err_unroll_cqinit; 1064 1065 status = ice_get_caps(hw); 1066 if (status) 1067 goto err_unroll_cqinit; 1068 1069 if (!hw->port_info) 1070 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1071 sizeof(*hw->port_info), 1072 GFP_KERNEL); 1073 if (!hw->port_info) { 1074 status = -ENOMEM; 1075 goto err_unroll_cqinit; 1076 } 1077 1078 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1079 /* set the back pointer to HW */ 1080 hw->port_info->hw = hw; 1081 1082 /* Initialize port_info struct with switch configuration data */ 1083 status = ice_get_initial_sw_cfg(hw); 1084 if (status) 1085 goto err_unroll_alloc; 1086 1087 hw->evb_veb = true; 1088 1089 /* init xarray for identifying scheduling nodes uniquely */ 1090 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1091 1092 /* Query the allocated resources for Tx scheduler */ 1093 status = ice_sched_query_res_alloc(hw); 1094 if (status) { 1095 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1096 goto err_unroll_alloc; 1097 } 1098 ice_sched_get_psm_clk_freq(hw); 1099 1100 /* Initialize port_info struct with scheduler data */ 1101 status = ice_sched_init_port(hw->port_info); 1102 if (status) 1103 goto err_unroll_sched; 1104 1105 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1106 if (!pcaps) { 1107 status = -ENOMEM; 1108 goto err_unroll_sched; 1109 } 1110 1111 /* Initialize port_info struct with PHY capabilities */ 1112 status = ice_aq_get_phy_caps(hw->port_info, false, 1113 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1114 NULL); 1115 if (status) 1116 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1117 status); 1118 1119 /* Initialize port_info struct with link information */ 1120 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1121 if (status) 1122 goto err_unroll_sched; 1123 1124 /* need a valid SW entry point to build a Tx tree */ 1125 if (!hw->sw_entry_point_layer) { 1126 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1127 status = -EIO; 1128 goto err_unroll_sched; 1129 } 1130 INIT_LIST_HEAD(&hw->agg_list); 1131 /* Initialize max burst size */ 1132 if (!hw->max_burst_size) 1133 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1134 1135 status = ice_init_fltr_mgmt_struct(hw); 1136 if (status) 1137 goto err_unroll_sched; 1138 1139 /* Get MAC information */ 1140 /* A single port can report up to two (LAN and WoL) addresses */ 1141 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1142 GFP_KERNEL); 1143 if (!mac_buf) { 1144 status = -ENOMEM; 1145 goto err_unroll_fltr_mgmt_struct; 1146 } 1147 1148 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1149 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1150 1151 if (status) 1152 goto err_unroll_fltr_mgmt_struct; 1153 /* enable jumbo frame support at MAC level */ 1154 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1155 if (status) 1156 goto err_unroll_fltr_mgmt_struct; 1157 /* Obtain counter base index which would be used by flow director */ 1158 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1159 if (status) 1160 goto err_unroll_fltr_mgmt_struct; 1161 status = ice_init_hw_tbls(hw); 1162 if (status) 1163 goto err_unroll_fltr_mgmt_struct; 1164 1165 ice_init_dev_hw(hw->back); 1166 1167 mutex_init(&hw->tnl_lock); 1168 ice_init_chk_recipe_reuse_support(hw); 1169 1170 /* Some cards require longer initialization times 1171 * due to necessity of loading FW from an external source. 1172 * This can take even half a minute. 1173 */ 1174 if (ice_is_pf_c827(hw)) { 1175 status = ice_wait_for_fw(hw, 30000); 1176 if (status) { 1177 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1178 goto err_unroll_fltr_mgmt_struct; 1179 } 1180 } 1181 1182 hw->lane_num = ice_get_phy_lane_number(hw); 1183 1184 return 0; 1185 err_unroll_fltr_mgmt_struct: 1186 ice_cleanup_fltr_mgmt_struct(hw); 1187 err_unroll_sched: 1188 ice_sched_cleanup_all(hw); 1189 err_unroll_alloc: 1190 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1191 err_unroll_cqinit: 1192 ice_destroy_all_ctrlq(hw); 1193 return status; 1194 } 1195 1196 static void __fwlog_deinit(struct ice_hw *hw) 1197 { 1198 /* only support fw log commands on PF 0 */ 1199 if (hw->bus.func) 1200 return; 1201 1202 ice_debugfs_pf_deinit(hw->back); 1203 libie_fwlog_deinit(&hw->fwlog); 1204 } 1205 1206 /** 1207 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1208 * @hw: pointer to the hardware structure 1209 * 1210 * This should be called only during nominal operation, not as a result of 1211 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1212 * applicable initializations if it fails for any reason. 1213 */ 1214 void ice_deinit_hw(struct ice_hw *hw) 1215 { 1216 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1217 ice_cleanup_fltr_mgmt_struct(hw); 1218 1219 ice_sched_cleanup_all(hw); 1220 ice_sched_clear_agg(hw); 1221 ice_free_seg(hw); 1222 ice_free_hw_tbls(hw); 1223 mutex_destroy(&hw->tnl_lock); 1224 __fwlog_deinit(hw); 1225 ice_destroy_all_ctrlq(hw); 1226 1227 /* Clear VSI contexts if not already cleared */ 1228 ice_clear_all_vsi_ctx(hw); 1229 } 1230 1231 /** 1232 * ice_check_reset - Check to see if a global reset is complete 1233 * @hw: pointer to the hardware structure 1234 */ 1235 int ice_check_reset(struct ice_hw *hw) 1236 { 1237 u32 cnt, reg = 0, grst_timeout, uld_mask; 1238 1239 /* Poll for Device Active state in case a recent CORER, GLOBR, 1240 * or EMPR has occurred. The grst delay value is in 100ms units. 1241 * Add 1sec for outstanding AQ commands that can take a long time. 1242 */ 1243 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1244 rd32(hw, GLGEN_RSTCTL)) + 10; 1245 1246 for (cnt = 0; cnt < grst_timeout; cnt++) { 1247 mdelay(100); 1248 reg = rd32(hw, GLGEN_RSTAT); 1249 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1250 break; 1251 } 1252 1253 if (cnt == grst_timeout) { 1254 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1255 return -EIO; 1256 } 1257 1258 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1259 GLNVM_ULD_PCIER_DONE_1_M |\ 1260 GLNVM_ULD_CORER_DONE_M |\ 1261 GLNVM_ULD_GLOBR_DONE_M |\ 1262 GLNVM_ULD_POR_DONE_M |\ 1263 GLNVM_ULD_POR_DONE_1_M |\ 1264 GLNVM_ULD_PCIER_DONE_2_M) 1265 1266 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1267 GLNVM_ULD_PE_DONE_M : 0); 1268 1269 /* Device is Active; check Global Reset processes are done */ 1270 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1271 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1272 if (reg == uld_mask) { 1273 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1274 break; 1275 } 1276 mdelay(10); 1277 } 1278 1279 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1280 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1281 reg); 1282 return -EIO; 1283 } 1284 1285 return 0; 1286 } 1287 1288 /** 1289 * ice_pf_reset - Reset the PF 1290 * @hw: pointer to the hardware structure 1291 * 1292 * If a global reset has been triggered, this function checks 1293 * for its completion and then issues the PF reset 1294 */ 1295 static int ice_pf_reset(struct ice_hw *hw) 1296 { 1297 u32 cnt, reg; 1298 1299 /* If at function entry a global reset was already in progress, i.e. 1300 * state is not 'device active' or any of the reset done bits are not 1301 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1302 * global reset is done. 1303 */ 1304 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1305 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1306 /* poll on global reset currently in progress until done */ 1307 if (ice_check_reset(hw)) 1308 return -EIO; 1309 1310 return 0; 1311 } 1312 1313 /* Reset the PF */ 1314 reg = rd32(hw, PFGEN_CTRL); 1315 1316 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1317 1318 /* Wait for the PFR to complete. The wait time is the global config lock 1319 * timeout plus the PFR timeout which will account for a possible reset 1320 * that is occurring during a download package operation. 1321 */ 1322 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1323 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1324 reg = rd32(hw, PFGEN_CTRL); 1325 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1326 break; 1327 1328 mdelay(1); 1329 } 1330 1331 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1332 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1333 return -EIO; 1334 } 1335 1336 return 0; 1337 } 1338 1339 /** 1340 * ice_reset - Perform different types of reset 1341 * @hw: pointer to the hardware structure 1342 * @req: reset request 1343 * 1344 * This function triggers a reset as specified by the req parameter. 1345 * 1346 * Note: 1347 * If anything other than a PF reset is triggered, PXE mode is restored. 1348 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1349 * interface has been restored in the rebuild flow. 1350 */ 1351 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1352 { 1353 u32 val = 0; 1354 1355 switch (req) { 1356 case ICE_RESET_PFR: 1357 return ice_pf_reset(hw); 1358 case ICE_RESET_CORER: 1359 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1360 val = GLGEN_RTRIG_CORER_M; 1361 break; 1362 case ICE_RESET_GLOBR: 1363 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1364 val = GLGEN_RTRIG_GLOBR_M; 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 val |= rd32(hw, GLGEN_RTRIG); 1371 wr32(hw, GLGEN_RTRIG, val); 1372 ice_flush(hw); 1373 1374 /* wait for the FW to be ready */ 1375 return ice_check_reset(hw); 1376 } 1377 1378 /** 1379 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1380 * @hw: pointer to the hardware structure 1381 * @rxq_ctx: pointer to the packed Rx queue context 1382 * @rxq_index: the index of the Rx queue 1383 */ 1384 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1385 const ice_rxq_ctx_buf_t *rxq_ctx, 1386 u32 rxq_index) 1387 { 1388 /* Copy each dword separately to HW */ 1389 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1390 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1391 1392 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1393 1394 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1395 } 1396 } 1397 1398 /** 1399 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1400 * @hw: pointer to the hardware structure 1401 * @rxq_ctx: pointer to the packed Rx queue context 1402 * @rxq_index: the index of the Rx queue 1403 */ 1404 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1405 ice_rxq_ctx_buf_t *rxq_ctx, 1406 u32 rxq_index) 1407 { 1408 u32 *ctx = (u32 *)rxq_ctx; 1409 1410 /* Copy each dword separately from HW */ 1411 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1412 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1413 1414 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1415 } 1416 } 1417 1418 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1419 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1420 1421 /* LAN Rx Queue Context */ 1422 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1423 /* Field Width LSB */ 1424 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1425 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1426 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1427 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1428 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1429 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1430 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1431 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1432 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1433 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1434 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1435 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1436 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1437 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1438 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1439 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1440 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1441 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1442 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1443 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1444 }; 1445 1446 /** 1447 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1448 * @ctx: the Rx queue context to pack 1449 * @buf: the HW buffer to pack into 1450 * 1451 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1452 * bit-packed HW layout. 1453 */ 1454 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1455 ice_rxq_ctx_buf_t *buf) 1456 { 1457 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1458 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1459 } 1460 1461 /** 1462 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1463 * @buf: the HW buffer to unpack from 1464 * @ctx: the Rx queue context to unpack 1465 * 1466 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1467 * structure. 1468 */ 1469 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1470 struct ice_rlan_ctx *ctx) 1471 { 1472 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1473 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1474 } 1475 1476 /** 1477 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1478 * @hw: pointer to the hardware structure 1479 * @rlan_ctx: pointer to the unpacked Rx queue context 1480 * @rxq_index: the index of the Rx queue 1481 * 1482 * Pack the sparse Rx Queue context into dense hardware format and write it 1483 * into the HW register space. 1484 * 1485 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1486 */ 1487 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1488 u32 rxq_index) 1489 { 1490 ice_rxq_ctx_buf_t buf = {}; 1491 1492 if (rxq_index > QRX_CTRL_MAX_INDEX) 1493 return -EINVAL; 1494 1495 ice_pack_rxq_ctx(rlan_ctx, &buf); 1496 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1497 1498 return 0; 1499 } 1500 1501 /** 1502 * ice_read_rxq_ctx - Read Rx queue context from HW 1503 * @hw: pointer to the hardware structure 1504 * @rlan_ctx: pointer to the Rx queue context 1505 * @rxq_index: the index of the Rx queue 1506 * 1507 * Read the Rx queue context from the hardware registers, and unpack it into 1508 * the sparse Rx queue context structure. 1509 * 1510 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1511 */ 1512 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1513 u32 rxq_index) 1514 { 1515 ice_rxq_ctx_buf_t buf = {}; 1516 1517 if (rxq_index > QRX_CTRL_MAX_INDEX) 1518 return -EINVAL; 1519 1520 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1521 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1522 1523 return 0; 1524 } 1525 1526 /* LAN Tx Queue Context */ 1527 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1528 /* Field Width LSB */ 1529 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1530 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1531 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1532 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1533 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1534 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1535 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1536 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1537 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1538 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1539 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1540 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1541 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1542 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1543 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1544 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1545 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1546 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1547 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1548 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1549 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1550 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1551 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1552 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1553 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1554 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1555 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1556 }; 1557 1558 /** 1559 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1560 * @ctx: the Tx queue context to pack 1561 * @buf: the Admin Queue HW buffer to pack into 1562 * 1563 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1564 * bit-packed Admin Queue layout. 1565 */ 1566 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1567 { 1568 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1569 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1570 } 1571 1572 /** 1573 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1574 * @ctx: the Tx queue context to pack 1575 * @buf: the HW buffer to pack into 1576 * 1577 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1578 * bit-packed HW layout, including the internal data portion. 1579 */ 1580 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1581 ice_txq_ctx_buf_full_t *buf) 1582 { 1583 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1584 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1585 } 1586 1587 /** 1588 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1589 * @buf: the HW buffer to unpack from 1590 * @ctx: the Tx queue context to unpack 1591 * 1592 * Unpack the Tx queue context from the HW buffer (including the full internal 1593 * state) into the CPU-friendly structure. 1594 */ 1595 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1596 struct ice_tlan_ctx *ctx) 1597 { 1598 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1599 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1600 } 1601 1602 /** 1603 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1604 * @hw: pointer to the hardware structure 1605 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1606 * @txq_index: the index of the Tx queue 1607 * 1608 * Copy Tx Queue context from HW register space to dense structure 1609 */ 1610 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1611 ice_txq_ctx_buf_full_t *txq_ctx, 1612 u32 txq_index) 1613 { 1614 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1615 u32 *ctx = (u32 *)txq_ctx; 1616 u32 txq_base, reg; 1617 1618 /* Get Tx queue base within card space */ 1619 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1620 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1621 1622 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1623 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1624 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1625 txq_base + txq_index) | 1626 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1627 1628 /* Prevent other PFs on the same adapter from accessing the Tx queue 1629 * context interface concurrently. 1630 */ 1631 spin_lock(&pf->adapter->txq_ctx_lock); 1632 1633 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1634 ice_flush(hw); 1635 1636 /* Copy each dword separately from HW */ 1637 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1638 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1639 1640 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1641 } 1642 1643 spin_unlock(&pf->adapter->txq_ctx_lock); 1644 } 1645 1646 /** 1647 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1648 * @hw: pointer to the hardware structure 1649 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1650 * @txq_index: the index of the Tx queue 1651 */ 1652 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1653 const ice_txq_ctx_buf_full_t *txq_ctx, 1654 u32 txq_index) 1655 { 1656 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1657 u32 txq_base, reg; 1658 1659 /* Get Tx queue base within card space */ 1660 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1661 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1662 1663 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1664 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1665 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1666 txq_base + txq_index) | 1667 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1668 1669 /* Prevent other PFs on the same adapter from accessing the Tx queue 1670 * context interface concurrently. 1671 */ 1672 spin_lock(&pf->adapter->txq_ctx_lock); 1673 1674 /* Copy each dword separately to HW */ 1675 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1676 u32 ctx = ((const u32 *)txq_ctx)[i]; 1677 1678 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1679 1680 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1681 } 1682 1683 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1684 ice_flush(hw); 1685 1686 spin_unlock(&pf->adapter->txq_ctx_lock); 1687 } 1688 1689 /** 1690 * ice_read_txq_ctx - Read Tx queue context from HW 1691 * @hw: pointer to the hardware structure 1692 * @tlan_ctx: pointer to the Tx queue context 1693 * @txq_index: the index of the Tx queue 1694 * 1695 * Read the Tx queue context from the HW registers, then unpack it into the 1696 * ice_tlan_ctx structure for use. 1697 * 1698 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1699 */ 1700 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1701 u32 txq_index) 1702 { 1703 ice_txq_ctx_buf_full_t buf = {}; 1704 1705 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1706 return -EINVAL; 1707 1708 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1709 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1710 1711 return 0; 1712 } 1713 1714 /** 1715 * ice_write_txq_ctx - Write Tx queue context to HW 1716 * @hw: pointer to the hardware structure 1717 * @tlan_ctx: pointer to the Tx queue context 1718 * @txq_index: the index of the Tx queue 1719 * 1720 * Pack the Tx queue context into the dense HW layout, then write it into the 1721 * HW registers. 1722 * 1723 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1724 */ 1725 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1726 u32 txq_index) 1727 { 1728 ice_txq_ctx_buf_full_t buf = {}; 1729 1730 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1731 return -EINVAL; 1732 1733 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1734 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1735 1736 return 0; 1737 } 1738 1739 /* Tx time Queue Context */ 1740 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1741 /* Field Width LSB */ 1742 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1743 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1744 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1745 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1746 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1747 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1748 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1749 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1750 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1751 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1752 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1753 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1754 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1755 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1756 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1757 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1758 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1759 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1760 }; 1761 1762 /** 1763 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1764 * @ctx: the Tx time queue context to pack 1765 * @buf: the HW buffer to pack into 1766 * 1767 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1768 * its bit-packed HW layout. 1769 */ 1770 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1771 ice_txtime_ctx_buf_t *buf) 1772 { 1773 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1774 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1775 } 1776 1777 /* Sideband Queue command wrappers */ 1778 1779 /** 1780 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1781 * @hw: pointer to the HW struct 1782 * @desc: descriptor describing the command 1783 * @buf: buffer to use for indirect commands (NULL for direct commands) 1784 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1785 * @cd: pointer to command details structure 1786 */ 1787 static int 1788 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1789 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1790 { 1791 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1792 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1793 } 1794 1795 /** 1796 * ice_sbq_rw_reg - Fill Sideband Queue command 1797 * @hw: pointer to the HW struct 1798 * @in: message info to be filled in descriptor 1799 * @flags: control queue descriptor flags 1800 */ 1801 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1802 { 1803 struct ice_sbq_cmd_desc desc = {0}; 1804 struct ice_sbq_msg_req msg = {0}; 1805 u16 msg_len; 1806 int status; 1807 1808 msg_len = sizeof(msg); 1809 1810 msg.dest_dev = in->dest_dev; 1811 msg.opcode = in->opcode; 1812 msg.flags = ICE_SBQ_MSG_FLAGS; 1813 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1814 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1815 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1816 1817 if (in->opcode) 1818 msg.data = cpu_to_le32(in->data); 1819 else 1820 /* data read comes back in completion, so shorten the struct by 1821 * sizeof(msg.data) 1822 */ 1823 msg_len -= sizeof(msg.data); 1824 1825 desc.flags = cpu_to_le16(flags); 1826 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1827 desc.param0.cmd_len = cpu_to_le16(msg_len); 1828 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1829 if (!status && !in->opcode) 1830 in->data = le32_to_cpu 1831 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1832 return status; 1833 } 1834 1835 /* FW Admin Queue command wrappers */ 1836 1837 /* Software lock/mutex that is meant to be held while the Global Config Lock 1838 * in firmware is acquired by the software to prevent most (but not all) types 1839 * of AQ commands from being sent to FW 1840 */ 1841 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1842 1843 /** 1844 * ice_should_retry_sq_send_cmd 1845 * @opcode: AQ opcode 1846 * 1847 * Decide if we should retry the send command routine for the ATQ, depending 1848 * on the opcode. 1849 */ 1850 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1851 { 1852 switch (opcode) { 1853 case ice_aqc_opc_get_link_topo: 1854 case ice_aqc_opc_lldp_stop: 1855 case ice_aqc_opc_lldp_start: 1856 case ice_aqc_opc_lldp_filter_ctrl: 1857 return true; 1858 } 1859 1860 return false; 1861 } 1862 1863 /** 1864 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1865 * @hw: pointer to the HW struct 1866 * @cq: pointer to the specific Control queue 1867 * @desc: prefilled descriptor describing the command 1868 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1869 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1870 * @cd: pointer to command details structure 1871 * 1872 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1873 * Queue if the EBUSY AQ error is returned. 1874 */ 1875 static int 1876 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1877 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1878 struct ice_sq_cd *cd) 1879 { 1880 struct libie_aq_desc desc_cpy; 1881 bool is_cmd_for_retry; 1882 u8 idx = 0; 1883 u16 opcode; 1884 int status; 1885 1886 opcode = le16_to_cpu(desc->opcode); 1887 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1888 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1889 1890 if (is_cmd_for_retry) { 1891 /* All retryable cmds are direct, without buf. */ 1892 WARN_ON(buf); 1893 1894 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1895 } 1896 1897 do { 1898 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1899 1900 if (!is_cmd_for_retry || !status || 1901 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1902 break; 1903 1904 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1905 1906 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1907 1908 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1909 1910 return status; 1911 } 1912 1913 /** 1914 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1915 * @hw: pointer to the HW struct 1916 * @desc: descriptor describing the command 1917 * @buf: buffer to use for indirect commands (NULL for direct commands) 1918 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1919 * @cd: pointer to command details structure 1920 * 1921 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1922 */ 1923 int 1924 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1925 u16 buf_size, struct ice_sq_cd *cd) 1926 { 1927 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1928 bool lock_acquired = false; 1929 int status; 1930 1931 /* When a package download is in process (i.e. when the firmware's 1932 * Global Configuration Lock resource is held), only the Download 1933 * Package, Get Version, Get Package Info List, Upload Section, 1934 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1935 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1936 * Recipes to Profile Association, and Release Resource (with resource 1937 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1938 * must block until the package download completes and the Global Config 1939 * Lock is released. See also ice_acquire_global_cfg_lock(). 1940 */ 1941 switch (le16_to_cpu(desc->opcode)) { 1942 case ice_aqc_opc_download_pkg: 1943 case ice_aqc_opc_get_pkg_info_list: 1944 case ice_aqc_opc_get_ver: 1945 case ice_aqc_opc_upload_section: 1946 case ice_aqc_opc_update_pkg: 1947 case ice_aqc_opc_set_port_params: 1948 case ice_aqc_opc_get_vlan_mode_parameters: 1949 case ice_aqc_opc_set_vlan_mode_parameters: 1950 case ice_aqc_opc_set_tx_topo: 1951 case ice_aqc_opc_get_tx_topo: 1952 case ice_aqc_opc_add_recipe: 1953 case ice_aqc_opc_recipe_to_profile: 1954 case ice_aqc_opc_get_recipe: 1955 case ice_aqc_opc_get_recipe_to_profile: 1956 break; 1957 case ice_aqc_opc_release_res: 1958 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1959 break; 1960 fallthrough; 1961 default: 1962 mutex_lock(&ice_global_cfg_lock_sw); 1963 lock_acquired = true; 1964 break; 1965 } 1966 1967 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1968 if (lock_acquired) 1969 mutex_unlock(&ice_global_cfg_lock_sw); 1970 1971 return status; 1972 } 1973 1974 /** 1975 * ice_aq_get_fw_ver 1976 * @hw: pointer to the HW struct 1977 * @cd: pointer to command details structure or NULL 1978 * 1979 * Get the firmware version (0x0001) from the admin queue commands 1980 */ 1981 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1982 { 1983 struct libie_aqc_get_ver *resp; 1984 struct libie_aq_desc desc; 1985 int status; 1986 1987 resp = &desc.params.get_ver; 1988 1989 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1990 1991 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1992 1993 if (!status) { 1994 hw->fw_branch = resp->fw_branch; 1995 hw->fw_maj_ver = resp->fw_major; 1996 hw->fw_min_ver = resp->fw_minor; 1997 hw->fw_patch = resp->fw_patch; 1998 hw->fw_build = le32_to_cpu(resp->fw_build); 1999 hw->api_branch = resp->api_branch; 2000 hw->api_maj_ver = resp->api_major; 2001 hw->api_min_ver = resp->api_minor; 2002 hw->api_patch = resp->api_patch; 2003 } 2004 2005 return status; 2006 } 2007 2008 /** 2009 * ice_aq_send_driver_ver 2010 * @hw: pointer to the HW struct 2011 * @dv: driver's major, minor version 2012 * @cd: pointer to command details structure or NULL 2013 * 2014 * Send the driver version (0x0002) to the firmware 2015 */ 2016 int 2017 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 2018 struct ice_sq_cd *cd) 2019 { 2020 struct libie_aqc_driver_ver *cmd; 2021 struct libie_aq_desc desc; 2022 u16 len; 2023 2024 cmd = &desc.params.driver_ver; 2025 2026 if (!dv) 2027 return -EINVAL; 2028 2029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 2030 2031 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2032 cmd->major_ver = dv->major_ver; 2033 cmd->minor_ver = dv->minor_ver; 2034 cmd->build_ver = dv->build_ver; 2035 cmd->subbuild_ver = dv->subbuild_ver; 2036 2037 len = 0; 2038 while (len < sizeof(dv->driver_string) && 2039 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2040 len++; 2041 2042 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2043 } 2044 2045 /** 2046 * ice_aq_q_shutdown 2047 * @hw: pointer to the HW struct 2048 * @unloading: is the driver unloading itself 2049 * 2050 * Tell the Firmware that we're shutting down the AdminQ and whether 2051 * or not the driver is unloading as well (0x0003). 2052 */ 2053 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2054 { 2055 struct ice_aqc_q_shutdown *cmd; 2056 struct libie_aq_desc desc; 2057 2058 cmd = libie_aq_raw(&desc); 2059 2060 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2061 2062 if (unloading) 2063 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2064 2065 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2066 } 2067 2068 /** 2069 * ice_aq_req_res 2070 * @hw: pointer to the HW struct 2071 * @res: resource ID 2072 * @access: access type 2073 * @sdp_number: resource number 2074 * @timeout: the maximum time in ms that the driver may hold the resource 2075 * @cd: pointer to command details structure or NULL 2076 * 2077 * Requests common resource using the admin queue commands (0x0008). 2078 * When attempting to acquire the Global Config Lock, the driver can 2079 * learn of three states: 2080 * 1) 0 - acquired lock, and can perform download package 2081 * 2) -EIO - did not get lock, driver should fail to load 2082 * 3) -EALREADY - did not get lock, but another driver has 2083 * successfully downloaded the package; the driver does 2084 * not have to download the package and can continue 2085 * loading 2086 * 2087 * Note that if the caller is in an acquire lock, perform action, release lock 2088 * phase of operation, it is possible that the FW may detect a timeout and issue 2089 * a CORER. In this case, the driver will receive a CORER interrupt and will 2090 * have to determine its cause. The calling thread that is handling this flow 2091 * will likely get an error propagated back to it indicating the Download 2092 * Package, Update Package or the Release Resource AQ commands timed out. 2093 */ 2094 static int 2095 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2096 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2097 struct ice_sq_cd *cd) 2098 { 2099 struct libie_aqc_req_res *cmd_resp; 2100 struct libie_aq_desc desc; 2101 int status; 2102 2103 cmd_resp = &desc.params.res_owner; 2104 2105 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2106 2107 cmd_resp->res_id = cpu_to_le16(res); 2108 cmd_resp->access_type = cpu_to_le16(access); 2109 cmd_resp->res_number = cpu_to_le32(sdp_number); 2110 cmd_resp->timeout = cpu_to_le32(*timeout); 2111 *timeout = 0; 2112 2113 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2114 2115 /* The completion specifies the maximum time in ms that the driver 2116 * may hold the resource in the Timeout field. 2117 */ 2118 2119 /* Global config lock response utilizes an additional status field. 2120 * 2121 * If the Global config lock resource is held by some other driver, the 2122 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2123 * and the timeout field indicates the maximum time the current owner 2124 * of the resource has to free it. 2125 */ 2126 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2127 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2128 *timeout = le32_to_cpu(cmd_resp->timeout); 2129 return 0; 2130 } else if (le16_to_cpu(cmd_resp->status) == 2131 LIBIE_AQ_RES_GLBL_IN_PROG) { 2132 *timeout = le32_to_cpu(cmd_resp->timeout); 2133 return -EIO; 2134 } else if (le16_to_cpu(cmd_resp->status) == 2135 LIBIE_AQ_RES_GLBL_DONE) { 2136 return -EALREADY; 2137 } 2138 2139 /* invalid FW response, force a timeout immediately */ 2140 *timeout = 0; 2141 return -EIO; 2142 } 2143 2144 /* If the resource is held by some other driver, the command completes 2145 * with a busy return value and the timeout field indicates the maximum 2146 * time the current owner of the resource has to free it. 2147 */ 2148 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2149 *timeout = le32_to_cpu(cmd_resp->timeout); 2150 2151 return status; 2152 } 2153 2154 /** 2155 * ice_aq_release_res 2156 * @hw: pointer to the HW struct 2157 * @res: resource ID 2158 * @sdp_number: resource number 2159 * @cd: pointer to command details structure or NULL 2160 * 2161 * release common resource using the admin queue commands (0x0009) 2162 */ 2163 static int 2164 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2165 struct ice_sq_cd *cd) 2166 { 2167 struct libie_aqc_req_res *cmd; 2168 struct libie_aq_desc desc; 2169 2170 cmd = &desc.params.res_owner; 2171 2172 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2173 2174 cmd->res_id = cpu_to_le16(res); 2175 cmd->res_number = cpu_to_le32(sdp_number); 2176 2177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2178 } 2179 2180 /** 2181 * ice_acquire_res 2182 * @hw: pointer to the HW structure 2183 * @res: resource ID 2184 * @access: access type (read or write) 2185 * @timeout: timeout in milliseconds 2186 * 2187 * This function will attempt to acquire the ownership of a resource. 2188 */ 2189 int 2190 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2191 enum ice_aq_res_access_type access, u32 timeout) 2192 { 2193 #define ICE_RES_POLLING_DELAY_MS 10 2194 u32 delay = ICE_RES_POLLING_DELAY_MS; 2195 u32 time_left = timeout; 2196 int status; 2197 2198 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2199 2200 /* A return code of -EALREADY means that another driver has 2201 * previously acquired the resource and performed any necessary updates; 2202 * in this case the caller does not obtain the resource and has no 2203 * further work to do. 2204 */ 2205 if (status == -EALREADY) 2206 goto ice_acquire_res_exit; 2207 2208 if (status) 2209 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2210 2211 /* If necessary, poll until the current lock owner timeouts */ 2212 timeout = time_left; 2213 while (status && timeout && time_left) { 2214 mdelay(delay); 2215 timeout = (timeout > delay) ? timeout - delay : 0; 2216 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2217 2218 if (status == -EALREADY) 2219 /* lock free, but no work to do */ 2220 break; 2221 2222 if (!status) 2223 /* lock acquired */ 2224 break; 2225 } 2226 if (status && status != -EALREADY) 2227 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2228 2229 ice_acquire_res_exit: 2230 if (status == -EALREADY) { 2231 if (access == ICE_RES_WRITE) 2232 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2233 else 2234 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2235 } 2236 return status; 2237 } 2238 2239 /** 2240 * ice_release_res 2241 * @hw: pointer to the HW structure 2242 * @res: resource ID 2243 * 2244 * This function will release a resource using the proper Admin Command. 2245 */ 2246 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2247 { 2248 unsigned long timeout; 2249 int status; 2250 2251 /* there are some rare cases when trying to release the resource 2252 * results in an admin queue timeout, so handle them correctly 2253 */ 2254 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2255 do { 2256 status = ice_aq_release_res(hw, res, 0, NULL); 2257 if (status != -EIO) 2258 break; 2259 usleep_range(1000, 2000); 2260 } while (time_before(jiffies, timeout)); 2261 } 2262 2263 /** 2264 * ice_aq_alloc_free_res - command to allocate/free resources 2265 * @hw: pointer to the HW struct 2266 * @buf: Indirect buffer to hold data parameters and response 2267 * @buf_size: size of buffer for indirect commands 2268 * @opc: pass in the command opcode 2269 * 2270 * Helper function to allocate/free resources using the admin queue commands 2271 */ 2272 int ice_aq_alloc_free_res(struct ice_hw *hw, 2273 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2274 enum ice_adminq_opc opc) 2275 { 2276 struct ice_aqc_alloc_free_res_cmd *cmd; 2277 struct libie_aq_desc desc; 2278 2279 cmd = libie_aq_raw(&desc); 2280 2281 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2282 return -EINVAL; 2283 2284 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2285 2286 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2287 2288 cmd->num_entries = cpu_to_le16(1); 2289 2290 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2291 } 2292 2293 /** 2294 * ice_alloc_hw_res - allocate resource 2295 * @hw: pointer to the HW struct 2296 * @type: type of resource 2297 * @num: number of resources to allocate 2298 * @btm: allocate from bottom 2299 * @res: pointer to array that will receive the resources 2300 */ 2301 int 2302 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2303 { 2304 struct ice_aqc_alloc_free_res_elem *buf; 2305 u16 buf_len; 2306 int status; 2307 2308 buf_len = struct_size(buf, elem, num); 2309 buf = kzalloc(buf_len, GFP_KERNEL); 2310 if (!buf) 2311 return -ENOMEM; 2312 2313 /* Prepare buffer to allocate resource. */ 2314 buf->num_elems = cpu_to_le16(num); 2315 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2316 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2317 if (btm) 2318 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2319 2320 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2321 if (status) 2322 goto ice_alloc_res_exit; 2323 2324 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2325 2326 ice_alloc_res_exit: 2327 kfree(buf); 2328 return status; 2329 } 2330 2331 /** 2332 * ice_free_hw_res - free allocated HW resource 2333 * @hw: pointer to the HW struct 2334 * @type: type of resource to free 2335 * @num: number of resources 2336 * @res: pointer to array that contains the resources to free 2337 */ 2338 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2339 { 2340 struct ice_aqc_alloc_free_res_elem *buf; 2341 u16 buf_len; 2342 int status; 2343 2344 buf_len = struct_size(buf, elem, num); 2345 buf = kzalloc(buf_len, GFP_KERNEL); 2346 if (!buf) 2347 return -ENOMEM; 2348 2349 /* Prepare buffer to free resource. */ 2350 buf->num_elems = cpu_to_le16(num); 2351 buf->res_type = cpu_to_le16(type); 2352 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2353 2354 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2355 if (status) 2356 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2357 2358 kfree(buf); 2359 return status; 2360 } 2361 2362 /** 2363 * ice_get_num_per_func - determine number of resources per PF 2364 * @hw: pointer to the HW structure 2365 * @max: value to be evenly split between each PF 2366 * 2367 * Determine the number of valid functions by going through the bitmap returned 2368 * from parsing capabilities and use this to calculate the number of resources 2369 * per PF based on the max value passed in. 2370 */ 2371 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2372 { 2373 u8 funcs; 2374 2375 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2376 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2377 ICE_CAPS_VALID_FUNCS_M); 2378 2379 if (!funcs) 2380 return 0; 2381 2382 return max / funcs; 2383 } 2384 2385 /** 2386 * ice_parse_common_caps - parse common device/function capabilities 2387 * @hw: pointer to the HW struct 2388 * @caps: pointer to common capabilities structure 2389 * @elem: the capability element to parse 2390 * @prefix: message prefix for tracing capabilities 2391 * 2392 * Given a capability element, extract relevant details into the common 2393 * capability structure. 2394 * 2395 * Returns: true if the capability matches one of the common capability ids, 2396 * false otherwise. 2397 */ 2398 static bool 2399 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2400 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2401 { 2402 u32 logical_id = le32_to_cpu(elem->logical_id); 2403 u32 phys_id = le32_to_cpu(elem->phys_id); 2404 u32 number = le32_to_cpu(elem->number); 2405 u16 cap = le16_to_cpu(elem->cap); 2406 bool found = true; 2407 2408 switch (cap) { 2409 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2410 caps->valid_functions = number; 2411 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2412 caps->valid_functions); 2413 break; 2414 case LIBIE_AQC_CAPS_SRIOV: 2415 caps->sr_iov_1_1 = (number == 1); 2416 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2417 caps->sr_iov_1_1); 2418 break; 2419 case LIBIE_AQC_CAPS_DCB: 2420 caps->dcb = (number == 1); 2421 caps->active_tc_bitmap = logical_id; 2422 caps->maxtc = phys_id; 2423 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2424 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2425 caps->active_tc_bitmap); 2426 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2427 break; 2428 case LIBIE_AQC_CAPS_RSS: 2429 caps->rss_table_size = number; 2430 caps->rss_table_entry_width = logical_id; 2431 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2432 caps->rss_table_size); 2433 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2434 caps->rss_table_entry_width); 2435 break; 2436 case LIBIE_AQC_CAPS_RXQS: 2437 caps->num_rxq = number; 2438 caps->rxq_first_id = phys_id; 2439 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2440 caps->num_rxq); 2441 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2442 caps->rxq_first_id); 2443 break; 2444 case LIBIE_AQC_CAPS_TXQS: 2445 caps->num_txq = number; 2446 caps->txq_first_id = phys_id; 2447 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2448 caps->num_txq); 2449 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2450 caps->txq_first_id); 2451 break; 2452 case LIBIE_AQC_CAPS_MSIX: 2453 caps->num_msix_vectors = number; 2454 caps->msix_vector_first_id = phys_id; 2455 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2456 caps->num_msix_vectors); 2457 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2458 caps->msix_vector_first_id); 2459 break; 2460 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2461 caps->nvm_update_pending_nvm = true; 2462 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2463 break; 2464 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2465 caps->nvm_update_pending_orom = true; 2466 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2467 break; 2468 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2469 caps->nvm_update_pending_netlist = true; 2470 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2471 break; 2472 case LIBIE_AQC_CAPS_NVM_MGMT: 2473 caps->nvm_unified_update = 2474 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2475 true : false; 2476 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2477 caps->nvm_unified_update); 2478 break; 2479 case LIBIE_AQC_CAPS_RDMA: 2480 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2481 caps->rdma = (number == 1); 2482 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2483 break; 2484 case LIBIE_AQC_CAPS_MAX_MTU: 2485 caps->max_mtu = number; 2486 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2487 prefix, caps->max_mtu); 2488 break; 2489 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2490 caps->pcie_reset_avoidance = (number > 0); 2491 ice_debug(hw, ICE_DBG_INIT, 2492 "%s: pcie_reset_avoidance = %d\n", prefix, 2493 caps->pcie_reset_avoidance); 2494 break; 2495 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2496 caps->reset_restrict_support = (number == 1); 2497 ice_debug(hw, ICE_DBG_INIT, 2498 "%s: reset_restrict_support = %d\n", prefix, 2499 caps->reset_restrict_support); 2500 break; 2501 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2502 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2503 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2504 prefix, caps->roce_lag); 2505 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2506 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2507 prefix, caps->sriov_lag); 2508 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2509 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2510 prefix, caps->sriov_aa_lag); 2511 break; 2512 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2513 caps->tx_sched_topo_comp_mode_en = (number == 1); 2514 break; 2515 default: 2516 /* Not one of the recognized common capabilities */ 2517 found = false; 2518 } 2519 2520 return found; 2521 } 2522 2523 /** 2524 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2525 * @hw: pointer to the HW structure 2526 * @caps: pointer to capabilities structure to fix 2527 * 2528 * Re-calculate the capabilities that are dependent on the number of physical 2529 * ports; i.e. some features are not supported or function differently on 2530 * devices with more than 4 ports. 2531 */ 2532 static void 2533 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2534 { 2535 /* This assumes device capabilities are always scanned before function 2536 * capabilities during the initialization flow. 2537 */ 2538 if (hw->dev_caps.num_funcs > 4) { 2539 /* Max 4 TCs per port */ 2540 caps->maxtc = 4; 2541 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2542 caps->maxtc); 2543 if (caps->rdma) { 2544 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2545 caps->rdma = 0; 2546 } 2547 2548 /* print message only when processing device capabilities 2549 * during initialization. 2550 */ 2551 if (caps == &hw->dev_caps.common_cap) 2552 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2553 } 2554 } 2555 2556 /** 2557 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2558 * @hw: pointer to the HW struct 2559 * @func_p: pointer to function capabilities structure 2560 * @cap: pointer to the capability element to parse 2561 * 2562 * Extract function capabilities for ICE_AQC_CAPS_VF. 2563 */ 2564 static void 2565 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2566 struct libie_aqc_list_caps_elem *cap) 2567 { 2568 u32 logical_id = le32_to_cpu(cap->logical_id); 2569 u32 number = le32_to_cpu(cap->number); 2570 2571 func_p->num_allocd_vfs = number; 2572 func_p->vf_base_id = logical_id; 2573 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2574 func_p->num_allocd_vfs); 2575 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2576 func_p->vf_base_id); 2577 } 2578 2579 /** 2580 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2581 * @hw: pointer to the HW struct 2582 * @func_p: pointer to function capabilities structure 2583 * @cap: pointer to the capability element to parse 2584 * 2585 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2586 */ 2587 static void 2588 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2589 struct libie_aqc_list_caps_elem *cap) 2590 { 2591 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2592 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2593 le32_to_cpu(cap->number)); 2594 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2595 func_p->guar_num_vsi); 2596 } 2597 2598 /** 2599 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2600 * @hw: pointer to the HW struct 2601 * @func_p: pointer to function capabilities structure 2602 * @cap: pointer to the capability element to parse 2603 * 2604 * Extract function capabilities for ICE_AQC_CAPS_1588. 2605 */ 2606 static void 2607 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2608 struct libie_aqc_list_caps_elem *cap) 2609 { 2610 struct ice_ts_func_info *info = &func_p->ts_func_info; 2611 u32 number = le32_to_cpu(cap->number); 2612 2613 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2614 func_p->common_cap.ieee_1588 = info->ena; 2615 2616 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2617 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2618 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2619 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2620 2621 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2622 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2623 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2624 } else { 2625 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2626 info->clk_src = ICE_CLK_SRC_TIME_REF; 2627 } 2628 2629 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2630 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2631 } else { 2632 /* Unknown clock frequency, so assume a (probably incorrect) 2633 * default to avoid out-of-bounds look ups of frequency 2634 * related information. 2635 */ 2636 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2637 info->clk_freq); 2638 info->time_ref = ICE_TSPLL_FREQ_25_000; 2639 } 2640 2641 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2642 func_p->common_cap.ieee_1588); 2643 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2644 info->src_tmr_owned); 2645 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2646 info->tmr_ena); 2647 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2648 info->tmr_index_owned); 2649 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2650 info->tmr_index_assoc); 2651 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2652 info->clk_freq); 2653 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2654 info->clk_src); 2655 } 2656 2657 /** 2658 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2659 * @hw: pointer to the HW struct 2660 * @func_p: pointer to function capabilities structure 2661 * 2662 * Extract function capabilities for ICE_AQC_CAPS_FD. 2663 */ 2664 static void 2665 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2666 { 2667 u32 reg_val, gsize, bsize; 2668 2669 reg_val = rd32(hw, GLQF_FD_SIZE); 2670 switch (hw->mac_type) { 2671 case ICE_MAC_E830: 2672 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2673 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2674 break; 2675 case ICE_MAC_E810: 2676 default: 2677 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2678 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2679 } 2680 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2681 func_p->fd_fltr_best_effort = bsize; 2682 2683 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2684 func_p->fd_fltr_guar); 2685 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2686 func_p->fd_fltr_best_effort); 2687 } 2688 2689 /** 2690 * ice_parse_func_caps - Parse function capabilities 2691 * @hw: pointer to the HW struct 2692 * @func_p: pointer to function capabilities structure 2693 * @buf: buffer containing the function capability records 2694 * @cap_count: the number of capabilities 2695 * 2696 * Helper function to parse function (0x000A) capabilities list. For 2697 * capabilities shared between device and function, this relies on 2698 * ice_parse_common_caps. 2699 * 2700 * Loop through the list of provided capabilities and extract the relevant 2701 * data into the function capabilities structured. 2702 */ 2703 static void 2704 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2705 void *buf, u32 cap_count) 2706 { 2707 struct libie_aqc_list_caps_elem *cap_resp; 2708 u32 i; 2709 2710 cap_resp = buf; 2711 2712 memset(func_p, 0, sizeof(*func_p)); 2713 2714 for (i = 0; i < cap_count; i++) { 2715 u16 cap = le16_to_cpu(cap_resp[i].cap); 2716 bool found; 2717 2718 found = ice_parse_common_caps(hw, &func_p->common_cap, 2719 &cap_resp[i], "func caps"); 2720 2721 switch (cap) { 2722 case LIBIE_AQC_CAPS_VF: 2723 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2724 break; 2725 case LIBIE_AQC_CAPS_VSI: 2726 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2727 break; 2728 case LIBIE_AQC_CAPS_1588: 2729 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2730 break; 2731 case LIBIE_AQC_CAPS_FD: 2732 ice_parse_fdir_func_caps(hw, func_p); 2733 break; 2734 default: 2735 /* Don't list common capabilities as unknown */ 2736 if (!found) 2737 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2738 i, cap); 2739 break; 2740 } 2741 } 2742 2743 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2744 } 2745 2746 /** 2747 * ice_func_id_to_logical_id - map from function id to logical pf id 2748 * @active_function_bitmap: active function bitmap 2749 * @pf_id: function number of device 2750 * 2751 * Return: logical PF ID. 2752 */ 2753 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2754 { 2755 u8 logical_id = 0; 2756 u8 i; 2757 2758 for (i = 0; i < pf_id; i++) 2759 if (active_function_bitmap & BIT(i)) 2760 logical_id++; 2761 2762 return logical_id; 2763 } 2764 2765 /** 2766 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2767 * @hw: pointer to the HW struct 2768 * @dev_p: pointer to device capabilities structure 2769 * @cap: capability element to parse 2770 * 2771 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2772 */ 2773 static void 2774 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2775 struct libie_aqc_list_caps_elem *cap) 2776 { 2777 u32 number = le32_to_cpu(cap->number); 2778 2779 dev_p->num_funcs = hweight32(number); 2780 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2781 dev_p->num_funcs); 2782 2783 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2784 } 2785 2786 /** 2787 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2788 * @hw: pointer to the HW struct 2789 * @dev_p: pointer to device capabilities structure 2790 * @cap: capability element to parse 2791 * 2792 * Parse ICE_AQC_CAPS_VF for device capabilities. 2793 */ 2794 static void 2795 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2796 struct libie_aqc_list_caps_elem *cap) 2797 { 2798 u32 number = le32_to_cpu(cap->number); 2799 2800 dev_p->num_vfs_exposed = number; 2801 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2802 dev_p->num_vfs_exposed); 2803 } 2804 2805 /** 2806 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2807 * @hw: pointer to the HW struct 2808 * @dev_p: pointer to device capabilities structure 2809 * @cap: capability element to parse 2810 * 2811 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2812 */ 2813 static void 2814 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2815 struct libie_aqc_list_caps_elem *cap) 2816 { 2817 u32 number = le32_to_cpu(cap->number); 2818 2819 dev_p->num_vsi_allocd_to_host = number; 2820 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2821 dev_p->num_vsi_allocd_to_host); 2822 } 2823 2824 /** 2825 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2826 * @hw: pointer to the HW struct 2827 * @dev_p: pointer to device capabilities structure 2828 * @cap: capability element to parse 2829 * 2830 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2831 */ 2832 static void 2833 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2834 struct libie_aqc_list_caps_elem *cap) 2835 { 2836 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2837 u32 logical_id = le32_to_cpu(cap->logical_id); 2838 u32 phys_id = le32_to_cpu(cap->phys_id); 2839 u32 number = le32_to_cpu(cap->number); 2840 2841 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2842 dev_p->common_cap.ieee_1588 = info->ena; 2843 2844 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2845 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2846 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2847 2848 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2849 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2850 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2851 2852 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2853 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2854 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2855 2856 info->ena_ports = logical_id; 2857 info->tmr_own_map = phys_id; 2858 2859 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2860 dev_p->common_cap.ieee_1588); 2861 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2862 info->tmr0_owner); 2863 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2864 info->tmr0_owned); 2865 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2866 info->tmr0_ena); 2867 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2868 info->tmr1_owner); 2869 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2870 info->tmr1_owned); 2871 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2872 info->tmr1_ena); 2873 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2874 info->ts_ll_read); 2875 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2876 info->ts_ll_int_read); 2877 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2878 info->ll_phy_tmr_update); 2879 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2880 info->ena_ports); 2881 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2882 info->tmr_own_map); 2883 } 2884 2885 /** 2886 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2887 * @hw: pointer to the HW struct 2888 * @dev_p: pointer to device capabilities structure 2889 * @cap: capability element to parse 2890 * 2891 * Parse ICE_AQC_CAPS_FD for device capabilities. 2892 */ 2893 static void 2894 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2895 struct libie_aqc_list_caps_elem *cap) 2896 { 2897 u32 number = le32_to_cpu(cap->number); 2898 2899 dev_p->num_flow_director_fltr = number; 2900 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2901 dev_p->num_flow_director_fltr); 2902 } 2903 2904 /** 2905 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2906 * @hw: pointer to the HW struct 2907 * @dev_p: pointer to device capabilities structure 2908 * @cap: capability element to parse 2909 * 2910 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2911 * enabled sensors. 2912 */ 2913 static void 2914 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2915 struct libie_aqc_list_caps_elem *cap) 2916 { 2917 dev_p->supported_sensors = le32_to_cpu(cap->number); 2918 2919 ice_debug(hw, ICE_DBG_INIT, 2920 "dev caps: supported sensors (bitmap) = 0x%x\n", 2921 dev_p->supported_sensors); 2922 } 2923 2924 /** 2925 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2926 * @hw: pointer to the HW struct 2927 * @dev_p: pointer to device capabilities structure 2928 * @cap: capability element to parse 2929 * 2930 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2931 */ 2932 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2933 struct ice_hw_dev_caps *dev_p, 2934 struct libie_aqc_list_caps_elem *cap) 2935 { 2936 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2937 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2938 2939 dev_info(ice_hw_to_dev(hw), 2940 "PF is configured in %s mode with IP instance ID %d\n", 2941 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2942 "primary" : "secondary", dev_p->nac_topo.id); 2943 2944 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2945 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2946 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2947 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2948 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2949 dev_p->nac_topo.id); 2950 } 2951 2952 /** 2953 * ice_parse_dev_caps - Parse device capabilities 2954 * @hw: pointer to the HW struct 2955 * @dev_p: pointer to device capabilities structure 2956 * @buf: buffer containing the device capability records 2957 * @cap_count: the number of capabilities 2958 * 2959 * Helper device to parse device (0x000B) capabilities list. For 2960 * capabilities shared between device and function, this relies on 2961 * ice_parse_common_caps. 2962 * 2963 * Loop through the list of provided capabilities and extract the relevant 2964 * data into the device capabilities structured. 2965 */ 2966 static void 2967 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2968 void *buf, u32 cap_count) 2969 { 2970 struct libie_aqc_list_caps_elem *cap_resp; 2971 u32 i; 2972 2973 cap_resp = buf; 2974 2975 memset(dev_p, 0, sizeof(*dev_p)); 2976 2977 for (i = 0; i < cap_count; i++) { 2978 u16 cap = le16_to_cpu(cap_resp[i].cap); 2979 bool found; 2980 2981 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2982 &cap_resp[i], "dev caps"); 2983 2984 switch (cap) { 2985 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2986 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2987 break; 2988 case LIBIE_AQC_CAPS_VF: 2989 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2990 break; 2991 case LIBIE_AQC_CAPS_VSI: 2992 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2993 break; 2994 case LIBIE_AQC_CAPS_1588: 2995 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2996 break; 2997 case LIBIE_AQC_CAPS_FD: 2998 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2999 break; 3000 case LIBIE_AQC_CAPS_SENSOR_READING: 3001 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 3002 break; 3003 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 3004 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 3005 break; 3006 default: 3007 /* Don't list common capabilities as unknown */ 3008 if (!found) 3009 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 3010 i, cap); 3011 break; 3012 } 3013 } 3014 3015 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 3016 } 3017 3018 /** 3019 * ice_is_phy_rclk_in_netlist 3020 * @hw: pointer to the hw struct 3021 * 3022 * Check if the PHY Recovered Clock device is present in the netlist 3023 */ 3024 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 3025 { 3026 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3027 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3028 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 3029 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3030 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3031 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3032 return false; 3033 3034 return true; 3035 } 3036 3037 /** 3038 * ice_is_clock_mux_in_netlist 3039 * @hw: pointer to the hw struct 3040 * 3041 * Check if the Clock Multiplexer device is present in the netlist 3042 */ 3043 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3044 { 3045 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3046 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3047 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3048 NULL)) 3049 return false; 3050 3051 return true; 3052 } 3053 3054 /** 3055 * ice_is_cgu_in_netlist - check for CGU presence 3056 * @hw: pointer to the hw struct 3057 * 3058 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3059 * Save the CGU part number in the hw structure for later use. 3060 * Return: 3061 * * true - cgu is present 3062 * * false - cgu is not present 3063 */ 3064 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3065 { 3066 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3067 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3068 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3069 NULL)) { 3070 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3071 return true; 3072 } else if (!ice_find_netlist_node(hw, 3073 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3074 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3075 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3076 NULL)) { 3077 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3078 return true; 3079 } 3080 3081 return false; 3082 } 3083 3084 /** 3085 * ice_is_gps_in_netlist 3086 * @hw: pointer to the hw struct 3087 * 3088 * Check if the GPS generic device is present in the netlist 3089 */ 3090 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3091 { 3092 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3093 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3094 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3095 return false; 3096 3097 return true; 3098 } 3099 3100 /** 3101 * ice_aq_list_caps - query function/device capabilities 3102 * @hw: pointer to the HW struct 3103 * @buf: a buffer to hold the capabilities 3104 * @buf_size: size of the buffer 3105 * @cap_count: if not NULL, set to the number of capabilities reported 3106 * @opc: capabilities type to discover, device or function 3107 * @cd: pointer to command details structure or NULL 3108 * 3109 * Get the function (0x000A) or device (0x000B) capabilities description from 3110 * firmware and store it in the buffer. 3111 * 3112 * If the cap_count pointer is not NULL, then it is set to the number of 3113 * capabilities firmware will report. Note that if the buffer size is too 3114 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3115 * cap_count will still be updated in this case. It is recommended that the 3116 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3117 * firmware could return) to avoid this. 3118 */ 3119 int 3120 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3121 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3122 { 3123 struct libie_aqc_list_caps *cmd; 3124 struct libie_aq_desc desc; 3125 int status; 3126 3127 cmd = &desc.params.get_cap; 3128 3129 if (opc != ice_aqc_opc_list_func_caps && 3130 opc != ice_aqc_opc_list_dev_caps) 3131 return -EINVAL; 3132 3133 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3134 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3135 3136 if (cap_count) 3137 *cap_count = le32_to_cpu(cmd->count); 3138 3139 return status; 3140 } 3141 3142 /** 3143 * ice_discover_dev_caps - Read and extract device capabilities 3144 * @hw: pointer to the hardware structure 3145 * @dev_caps: pointer to device capabilities structure 3146 * 3147 * Read the device capabilities and extract them into the dev_caps structure 3148 * for later use. 3149 */ 3150 int 3151 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3152 { 3153 u32 cap_count = 0; 3154 void *cbuf; 3155 int status; 3156 3157 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3158 if (!cbuf) 3159 return -ENOMEM; 3160 3161 /* Although the driver doesn't know the number of capabilities the 3162 * device will return, we can simply send a 4KB buffer, the maximum 3163 * possible size that firmware can return. 3164 */ 3165 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3166 3167 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3168 ice_aqc_opc_list_dev_caps, NULL); 3169 if (!status) 3170 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3171 kfree(cbuf); 3172 3173 return status; 3174 } 3175 3176 /** 3177 * ice_discover_func_caps - Read and extract function capabilities 3178 * @hw: pointer to the hardware structure 3179 * @func_caps: pointer to function capabilities structure 3180 * 3181 * Read the function capabilities and extract them into the func_caps structure 3182 * for later use. 3183 */ 3184 static int 3185 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3186 { 3187 u32 cap_count = 0; 3188 void *cbuf; 3189 int status; 3190 3191 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3192 if (!cbuf) 3193 return -ENOMEM; 3194 3195 /* Although the driver doesn't know the number of capabilities the 3196 * device will return, we can simply send a 4KB buffer, the maximum 3197 * possible size that firmware can return. 3198 */ 3199 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3200 3201 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3202 ice_aqc_opc_list_func_caps, NULL); 3203 if (!status) 3204 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3205 kfree(cbuf); 3206 3207 return status; 3208 } 3209 3210 /** 3211 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3212 * @hw: pointer to the hardware structure 3213 */ 3214 void ice_set_safe_mode_caps(struct ice_hw *hw) 3215 { 3216 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3217 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3218 struct ice_hw_common_caps cached_caps; 3219 u32 num_funcs; 3220 3221 /* cache some func_caps values that should be restored after memset */ 3222 cached_caps = func_caps->common_cap; 3223 3224 /* unset func capabilities */ 3225 memset(func_caps, 0, sizeof(*func_caps)); 3226 3227 #define ICE_RESTORE_FUNC_CAP(name) \ 3228 func_caps->common_cap.name = cached_caps.name 3229 3230 /* restore cached values */ 3231 ICE_RESTORE_FUNC_CAP(valid_functions); 3232 ICE_RESTORE_FUNC_CAP(txq_first_id); 3233 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3234 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3235 ICE_RESTORE_FUNC_CAP(max_mtu); 3236 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3237 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3238 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3239 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3240 3241 /* one Tx and one Rx queue in safe mode */ 3242 func_caps->common_cap.num_rxq = 1; 3243 func_caps->common_cap.num_txq = 1; 3244 3245 /* two MSIX vectors, one for traffic and one for misc causes */ 3246 func_caps->common_cap.num_msix_vectors = 2; 3247 func_caps->guar_num_vsi = 1; 3248 3249 /* cache some dev_caps values that should be restored after memset */ 3250 cached_caps = dev_caps->common_cap; 3251 num_funcs = dev_caps->num_funcs; 3252 3253 /* unset dev capabilities */ 3254 memset(dev_caps, 0, sizeof(*dev_caps)); 3255 3256 #define ICE_RESTORE_DEV_CAP(name) \ 3257 dev_caps->common_cap.name = cached_caps.name 3258 3259 /* restore cached values */ 3260 ICE_RESTORE_DEV_CAP(valid_functions); 3261 ICE_RESTORE_DEV_CAP(txq_first_id); 3262 ICE_RESTORE_DEV_CAP(rxq_first_id); 3263 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3264 ICE_RESTORE_DEV_CAP(max_mtu); 3265 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3266 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3267 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3268 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3269 dev_caps->num_funcs = num_funcs; 3270 3271 /* one Tx and one Rx queue per function in safe mode */ 3272 dev_caps->common_cap.num_rxq = num_funcs; 3273 dev_caps->common_cap.num_txq = num_funcs; 3274 3275 /* two MSIX vectors per function */ 3276 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3277 } 3278 3279 /** 3280 * ice_get_caps - get info about the HW 3281 * @hw: pointer to the hardware structure 3282 */ 3283 int ice_get_caps(struct ice_hw *hw) 3284 { 3285 int status; 3286 3287 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3288 if (status) 3289 return status; 3290 3291 return ice_discover_func_caps(hw, &hw->func_caps); 3292 } 3293 3294 /** 3295 * ice_aq_manage_mac_write - manage MAC address write command 3296 * @hw: pointer to the HW struct 3297 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3298 * @flags: flags to control write behavior 3299 * @cd: pointer to command details structure or NULL 3300 * 3301 * This function is used to write MAC address to the NVM (0x0108). 3302 */ 3303 int 3304 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3305 struct ice_sq_cd *cd) 3306 { 3307 struct ice_aqc_manage_mac_write *cmd; 3308 struct libie_aq_desc desc; 3309 3310 cmd = libie_aq_raw(&desc); 3311 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3312 3313 cmd->flags = flags; 3314 ether_addr_copy(cmd->mac_addr, mac_addr); 3315 3316 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3317 } 3318 3319 /** 3320 * ice_aq_clear_pxe_mode 3321 * @hw: pointer to the HW struct 3322 * 3323 * Tell the firmware that the driver is taking over from PXE (0x0110). 3324 */ 3325 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3326 { 3327 struct ice_aqc_clear_pxe *cmd; 3328 struct libie_aq_desc desc; 3329 3330 cmd = libie_aq_raw(&desc); 3331 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3332 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3333 3334 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3335 } 3336 3337 /** 3338 * ice_clear_pxe_mode - clear pxe operations mode 3339 * @hw: pointer to the HW struct 3340 * 3341 * Make sure all PXE mode settings are cleared, including things 3342 * like descriptor fetch/write-back mode. 3343 */ 3344 void ice_clear_pxe_mode(struct ice_hw *hw) 3345 { 3346 if (ice_check_sq_alive(hw, &hw->adminq)) 3347 ice_aq_clear_pxe_mode(hw); 3348 } 3349 3350 /** 3351 * ice_aq_set_port_params - set physical port parameters. 3352 * @pi: pointer to the port info struct 3353 * @double_vlan: if set double VLAN is enabled 3354 * @cd: pointer to command details structure or NULL 3355 * 3356 * Set Physical port parameters (0x0203) 3357 */ 3358 int 3359 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3360 struct ice_sq_cd *cd) 3361 3362 { 3363 struct ice_aqc_set_port_params *cmd; 3364 struct ice_hw *hw = pi->hw; 3365 struct libie_aq_desc desc; 3366 u16 cmd_flags = 0; 3367 3368 cmd = libie_aq_raw(&desc); 3369 3370 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3371 if (double_vlan) 3372 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3373 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3374 3375 cmd->local_fwd_mode = pi->local_fwd_mode | 3376 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3377 3378 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3379 } 3380 3381 /** 3382 * ice_is_100m_speed_supported 3383 * @hw: pointer to the HW struct 3384 * 3385 * returns true if 100M speeds are supported by the device, 3386 * false otherwise. 3387 */ 3388 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3389 { 3390 switch (hw->device_id) { 3391 case ICE_DEV_ID_E822C_SGMII: 3392 case ICE_DEV_ID_E822L_SGMII: 3393 case ICE_DEV_ID_E823L_1GBE: 3394 case ICE_DEV_ID_E823C_SGMII: 3395 case ICE_DEV_ID_E825C_SGMII: 3396 return true; 3397 default: 3398 return false; 3399 } 3400 } 3401 3402 /** 3403 * ice_get_link_speed_based_on_phy_type - returns link speed 3404 * @phy_type_low: lower part of phy_type 3405 * @phy_type_high: higher part of phy_type 3406 * 3407 * This helper function will convert an entry in PHY type structure 3408 * [phy_type_low, phy_type_high] to its corresponding link speed. 3409 * Note: In the structure of [phy_type_low, phy_type_high], there should 3410 * be one bit set, as this function will convert one PHY type to its 3411 * speed. 3412 * 3413 * Return: 3414 * * PHY speed for recognized PHY type 3415 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3416 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3417 */ 3418 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3419 { 3420 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3421 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3422 3423 switch (phy_type_low) { 3424 case ICE_PHY_TYPE_LOW_100BASE_TX: 3425 case ICE_PHY_TYPE_LOW_100M_SGMII: 3426 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3427 break; 3428 case ICE_PHY_TYPE_LOW_1000BASE_T: 3429 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3430 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3431 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3432 case ICE_PHY_TYPE_LOW_1G_SGMII: 3433 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3434 break; 3435 case ICE_PHY_TYPE_LOW_2500BASE_T: 3436 case ICE_PHY_TYPE_LOW_2500BASE_X: 3437 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3438 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3439 break; 3440 case ICE_PHY_TYPE_LOW_5GBASE_T: 3441 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3442 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3443 break; 3444 case ICE_PHY_TYPE_LOW_10GBASE_T: 3445 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3446 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3447 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3448 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3449 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3450 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3451 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3452 break; 3453 case ICE_PHY_TYPE_LOW_25GBASE_T: 3454 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3455 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3456 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3457 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3458 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3459 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3460 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3461 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3462 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3463 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3464 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3465 break; 3466 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3467 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3468 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3469 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3470 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3471 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3472 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3473 break; 3474 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3475 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3476 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3477 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3478 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3479 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3480 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3481 case ICE_PHY_TYPE_LOW_50G_AUI2: 3482 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3483 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3484 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3485 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3486 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3487 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3488 case ICE_PHY_TYPE_LOW_50G_AUI1: 3489 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3490 break; 3491 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3492 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3493 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3494 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3495 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3496 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3497 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3498 case ICE_PHY_TYPE_LOW_100G_AUI4: 3499 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3500 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3501 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3502 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3503 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3504 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3505 break; 3506 default: 3507 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3508 break; 3509 } 3510 3511 switch (phy_type_high) { 3512 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3513 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3514 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3515 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3516 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3517 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3518 break; 3519 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3520 case ICE_PHY_TYPE_HIGH_200G_SR4: 3521 case ICE_PHY_TYPE_HIGH_200G_FR4: 3522 case ICE_PHY_TYPE_HIGH_200G_LR4: 3523 case ICE_PHY_TYPE_HIGH_200G_DR4: 3524 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3525 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3526 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3527 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3528 break; 3529 default: 3530 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3531 break; 3532 } 3533 3534 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3535 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3536 return ICE_AQ_LINK_SPEED_UNKNOWN; 3537 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3538 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3539 return ICE_AQ_LINK_SPEED_UNKNOWN; 3540 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3541 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3542 return speed_phy_type_low; 3543 else 3544 return speed_phy_type_high; 3545 } 3546 3547 /** 3548 * ice_update_phy_type 3549 * @phy_type_low: pointer to the lower part of phy_type 3550 * @phy_type_high: pointer to the higher part of phy_type 3551 * @link_speeds_bitmap: targeted link speeds bitmap 3552 * 3553 * Note: For the link_speeds_bitmap structure, you can check it at 3554 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3555 * link_speeds_bitmap include multiple speeds. 3556 * 3557 * Each entry in this [phy_type_low, phy_type_high] structure will 3558 * present a certain link speed. This helper function will turn on bits 3559 * in [phy_type_low, phy_type_high] structure based on the value of 3560 * link_speeds_bitmap input parameter. 3561 */ 3562 void 3563 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3564 u16 link_speeds_bitmap) 3565 { 3566 u64 pt_high; 3567 u64 pt_low; 3568 int index; 3569 u16 speed; 3570 3571 /* We first check with low part of phy_type */ 3572 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3573 pt_low = BIT_ULL(index); 3574 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3575 3576 if (link_speeds_bitmap & speed) 3577 *phy_type_low |= BIT_ULL(index); 3578 } 3579 3580 /* We then check with high part of phy_type */ 3581 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3582 pt_high = BIT_ULL(index); 3583 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3584 3585 if (link_speeds_bitmap & speed) 3586 *phy_type_high |= BIT_ULL(index); 3587 } 3588 } 3589 3590 /** 3591 * ice_aq_set_phy_cfg 3592 * @hw: pointer to the HW struct 3593 * @pi: port info structure of the interested logical port 3594 * @cfg: structure with PHY configuration data to be set 3595 * @cd: pointer to command details structure or NULL 3596 * 3597 * Set the various PHY configuration parameters supported on the Port. 3598 * One or more of the Set PHY config parameters may be ignored in an MFP 3599 * mode as the PF may not have the privilege to set some of the PHY Config 3600 * parameters. This status will be indicated by the command response (0x0601). 3601 */ 3602 int 3603 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3604 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3605 { 3606 struct ice_aqc_set_phy_cfg *cmd; 3607 struct libie_aq_desc desc; 3608 int status; 3609 3610 if (!cfg) 3611 return -EINVAL; 3612 3613 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3614 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3615 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3616 cfg->caps); 3617 3618 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3619 } 3620 3621 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3622 cmd = libie_aq_raw(&desc); 3623 cmd->lport_num = pi->lport; 3624 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3625 3626 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3627 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3628 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3629 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3630 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3631 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3632 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3633 cfg->low_power_ctrl_an); 3634 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3635 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3636 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3637 cfg->link_fec_opt); 3638 3639 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3640 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3641 status = 0; 3642 3643 if (!status) 3644 pi->phy.curr_user_phy_cfg = *cfg; 3645 3646 return status; 3647 } 3648 3649 /** 3650 * ice_update_link_info - update status of the HW network link 3651 * @pi: port info structure of the interested logical port 3652 */ 3653 int ice_update_link_info(struct ice_port_info *pi) 3654 { 3655 struct ice_link_status *li; 3656 int status; 3657 3658 if (!pi) 3659 return -EINVAL; 3660 3661 li = &pi->phy.link_info; 3662 3663 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3664 if (status) 3665 return status; 3666 3667 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3668 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3669 3670 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3671 if (!pcaps) 3672 return -ENOMEM; 3673 3674 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3675 pcaps, NULL); 3676 } 3677 3678 return status; 3679 } 3680 3681 /** 3682 * ice_aq_get_phy_equalization - function to read serdes equaliser 3683 * value from firmware using admin queue command. 3684 * @hw: pointer to the HW struct 3685 * @data_in: represents the serdes equalization parameter requested 3686 * @op_code: represents the serdes number and flag to represent tx or rx 3687 * @serdes_num: represents the serdes number 3688 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3689 * 3690 * Return: non-zero status on error and 0 on success. 3691 */ 3692 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3693 u8 serdes_num, int *output) 3694 { 3695 struct ice_aqc_dnl_call_command *cmd; 3696 struct ice_aqc_dnl_call buf = {}; 3697 struct libie_aq_desc desc; 3698 int err; 3699 3700 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3701 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3702 cpu_to_le16(op_code | (serdes_num & 0xF)); 3703 cmd = libie_aq_raw(&desc); 3704 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3705 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3706 LIBIE_AQ_FLAG_RD | 3707 LIBIE_AQ_FLAG_SI); 3708 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3709 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3710 3711 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3712 NULL); 3713 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3714 3715 return err; 3716 } 3717 3718 #define FEC_REG_PORT(port) { \ 3719 FEC_CORR_LOW_REG_PORT##port, \ 3720 FEC_CORR_HIGH_REG_PORT##port, \ 3721 FEC_UNCORR_LOW_REG_PORT##port, \ 3722 FEC_UNCORR_HIGH_REG_PORT##port, \ 3723 } 3724 3725 static const u32 fec_reg[][ICE_FEC_MAX] = { 3726 FEC_REG_PORT(0), 3727 FEC_REG_PORT(1), 3728 FEC_REG_PORT(2), 3729 FEC_REG_PORT(3) 3730 }; 3731 3732 /** 3733 * ice_aq_get_fec_stats - reads fec stats from phy 3734 * @hw: pointer to the HW struct 3735 * @pcs_quad: represents pcsquad of user input serdes 3736 * @pcs_port: represents the pcs port number part of above pcs quad 3737 * @fec_type: represents FEC stats type 3738 * @output: pointer to the caller-supplied buffer to return requested fec stats 3739 * 3740 * Return: non-zero status on error and 0 on success. 3741 */ 3742 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3743 enum ice_fec_stats_types fec_type, u32 *output) 3744 { 3745 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3746 struct ice_sbq_msg_input msg = {}; 3747 u32 receiver_id, reg_offset; 3748 int err; 3749 3750 if (pcs_port > 3) 3751 return -EINVAL; 3752 3753 reg_offset = fec_reg[pcs_port][fec_type]; 3754 3755 if (pcs_quad == 0) 3756 receiver_id = FEC_RECEIVER_ID_PCS0; 3757 else if (pcs_quad == 1) 3758 receiver_id = FEC_RECEIVER_ID_PCS1; 3759 else 3760 return -EINVAL; 3761 3762 msg.msg_addr_low = lower_16_bits(reg_offset); 3763 msg.msg_addr_high = receiver_id; 3764 msg.opcode = ice_sbq_msg_rd; 3765 msg.dest_dev = ice_sbq_dev_phy_0; 3766 3767 err = ice_sbq_rw_reg(hw, &msg, flag); 3768 if (err) 3769 return err; 3770 3771 *output = msg.data; 3772 return 0; 3773 } 3774 3775 /** 3776 * ice_cache_phy_user_req 3777 * @pi: port information structure 3778 * @cache_data: PHY logging data 3779 * @cache_mode: PHY logging mode 3780 * 3781 * Log the user request on (FC, FEC, SPEED) for later use. 3782 */ 3783 static void 3784 ice_cache_phy_user_req(struct ice_port_info *pi, 3785 struct ice_phy_cache_mode_data cache_data, 3786 enum ice_phy_cache_mode cache_mode) 3787 { 3788 if (!pi) 3789 return; 3790 3791 switch (cache_mode) { 3792 case ICE_FC_MODE: 3793 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3794 break; 3795 case ICE_SPEED_MODE: 3796 pi->phy.curr_user_speed_req = 3797 cache_data.data.curr_user_speed_req; 3798 break; 3799 case ICE_FEC_MODE: 3800 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3801 break; 3802 default: 3803 break; 3804 } 3805 } 3806 3807 /** 3808 * ice_caps_to_fc_mode 3809 * @caps: PHY capabilities 3810 * 3811 * Convert PHY FC capabilities to ice FC mode 3812 */ 3813 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3814 { 3815 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3816 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3817 return ICE_FC_FULL; 3818 3819 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3820 return ICE_FC_TX_PAUSE; 3821 3822 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3823 return ICE_FC_RX_PAUSE; 3824 3825 return ICE_FC_NONE; 3826 } 3827 3828 /** 3829 * ice_caps_to_fec_mode 3830 * @caps: PHY capabilities 3831 * @fec_options: Link FEC options 3832 * 3833 * Convert PHY FEC capabilities to ice FEC mode 3834 */ 3835 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3836 { 3837 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3838 return ICE_FEC_AUTO; 3839 3840 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3841 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3842 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3843 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3844 return ICE_FEC_BASER; 3845 3846 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3847 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3848 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3849 return ICE_FEC_RS; 3850 3851 return ICE_FEC_NONE; 3852 } 3853 3854 /** 3855 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3856 * @pi: port information structure 3857 * @cfg: PHY configuration data to set FC mode 3858 * @req_mode: FC mode to configure 3859 */ 3860 int 3861 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3862 enum ice_fc_mode req_mode) 3863 { 3864 struct ice_phy_cache_mode_data cache_data; 3865 u8 pause_mask = 0x0; 3866 3867 if (!pi || !cfg) 3868 return -EINVAL; 3869 3870 switch (req_mode) { 3871 case ICE_FC_FULL: 3872 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3873 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3874 break; 3875 case ICE_FC_RX_PAUSE: 3876 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3877 break; 3878 case ICE_FC_TX_PAUSE: 3879 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3880 break; 3881 default: 3882 break; 3883 } 3884 3885 /* clear the old pause settings */ 3886 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3887 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3888 3889 /* set the new capabilities */ 3890 cfg->caps |= pause_mask; 3891 3892 /* Cache user FC request */ 3893 cache_data.data.curr_user_fc_req = req_mode; 3894 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3895 3896 return 0; 3897 } 3898 3899 /** 3900 * ice_set_fc 3901 * @pi: port information structure 3902 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3903 * @ena_auto_link_update: enable automatic link update 3904 * 3905 * Set the requested flow control mode. 3906 */ 3907 int 3908 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3909 { 3910 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3911 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3912 struct ice_hw *hw; 3913 int status; 3914 3915 if (!pi || !aq_failures) 3916 return -EINVAL; 3917 3918 *aq_failures = 0; 3919 hw = pi->hw; 3920 3921 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3922 if (!pcaps) 3923 return -ENOMEM; 3924 3925 /* Get the current PHY config */ 3926 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3927 pcaps, NULL); 3928 if (status) { 3929 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3930 goto out; 3931 } 3932 3933 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3934 3935 /* Configure the set PHY data */ 3936 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3937 if (status) 3938 goto out; 3939 3940 /* If the capabilities have changed, then set the new config */ 3941 if (cfg.caps != pcaps->caps) { 3942 int retry_count, retry_max = 10; 3943 3944 /* Auto restart link so settings take effect */ 3945 if (ena_auto_link_update) 3946 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3947 3948 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3949 if (status) { 3950 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3951 goto out; 3952 } 3953 3954 /* Update the link info 3955 * It sometimes takes a really long time for link to 3956 * come back from the atomic reset. Thus, we wait a 3957 * little bit. 3958 */ 3959 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3960 status = ice_update_link_info(pi); 3961 3962 if (!status) 3963 break; 3964 3965 mdelay(100); 3966 } 3967 3968 if (status) 3969 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3970 } 3971 3972 out: 3973 return status; 3974 } 3975 3976 /** 3977 * ice_phy_caps_equals_cfg 3978 * @phy_caps: PHY capabilities 3979 * @phy_cfg: PHY configuration 3980 * 3981 * Helper function to determine if PHY capabilities matches PHY 3982 * configuration 3983 */ 3984 bool 3985 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3986 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3987 { 3988 u8 caps_mask, cfg_mask; 3989 3990 if (!phy_caps || !phy_cfg) 3991 return false; 3992 3993 /* These bits are not common between capabilities and configuration. 3994 * Do not use them to determine equality. 3995 */ 3996 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3997 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3998 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3999 4000 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 4001 phy_caps->phy_type_high != phy_cfg->phy_type_high || 4002 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 4003 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 4004 phy_caps->eee_cap != phy_cfg->eee_cap || 4005 phy_caps->eeer_value != phy_cfg->eeer_value || 4006 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 4007 return false; 4008 4009 return true; 4010 } 4011 4012 /** 4013 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 4014 * @pi: port information structure 4015 * @caps: PHY ability structure to copy date from 4016 * @cfg: PHY configuration structure to copy data to 4017 * 4018 * Helper function to copy AQC PHY get ability data to PHY set configuration 4019 * data structure 4020 */ 4021 void 4022 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 4023 struct ice_aqc_get_phy_caps_data *caps, 4024 struct ice_aqc_set_phy_cfg_data *cfg) 4025 { 4026 if (!pi || !caps || !cfg) 4027 return; 4028 4029 memset(cfg, 0, sizeof(*cfg)); 4030 cfg->phy_type_low = caps->phy_type_low; 4031 cfg->phy_type_high = caps->phy_type_high; 4032 cfg->caps = caps->caps; 4033 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4034 cfg->eee_cap = caps->eee_cap; 4035 cfg->eeer_value = caps->eeer_value; 4036 cfg->link_fec_opt = caps->link_fec_options; 4037 cfg->module_compliance_enforcement = 4038 caps->module_compliance_enforcement; 4039 } 4040 4041 /** 4042 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4043 * @pi: port information structure 4044 * @cfg: PHY configuration data to set FEC mode 4045 * @fec: FEC mode to configure 4046 */ 4047 int 4048 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4049 enum ice_fec_mode fec) 4050 { 4051 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4052 struct ice_hw *hw; 4053 int status; 4054 4055 if (!pi || !cfg) 4056 return -EINVAL; 4057 4058 hw = pi->hw; 4059 4060 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 4061 if (!pcaps) 4062 return -ENOMEM; 4063 4064 status = ice_aq_get_phy_caps(pi, false, 4065 (ice_fw_supports_report_dflt_cfg(hw) ? 4066 ICE_AQC_REPORT_DFLT_CFG : 4067 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4068 if (status) 4069 goto out; 4070 4071 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4072 cfg->link_fec_opt = pcaps->link_fec_options; 4073 4074 switch (fec) { 4075 case ICE_FEC_BASER: 4076 /* Clear RS bits, and AND BASE-R ability 4077 * bits and OR request bits. 4078 */ 4079 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4080 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4081 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4082 ICE_AQC_PHY_FEC_25G_KR_REQ; 4083 break; 4084 case ICE_FEC_RS: 4085 /* Clear BASE-R bits, and AND RS ability 4086 * bits and OR request bits. 4087 */ 4088 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4089 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4090 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4091 break; 4092 case ICE_FEC_NONE: 4093 /* Clear all FEC option bits. */ 4094 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4095 break; 4096 case ICE_FEC_AUTO: 4097 /* AND auto FEC bit, and all caps bits. */ 4098 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4099 cfg->link_fec_opt |= pcaps->link_fec_options; 4100 break; 4101 default: 4102 status = -EINVAL; 4103 break; 4104 } 4105 4106 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4107 !ice_fw_supports_report_dflt_cfg(hw)) { 4108 struct ice_link_default_override_tlv tlv = { 0 }; 4109 4110 status = ice_get_link_default_override(&tlv, pi); 4111 if (status) 4112 goto out; 4113 4114 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4115 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4116 cfg->link_fec_opt = tlv.fec_options; 4117 } 4118 4119 out: 4120 return status; 4121 } 4122 4123 /** 4124 * ice_get_link_status - get status of the HW network link 4125 * @pi: port information structure 4126 * @link_up: pointer to bool (true/false = linkup/linkdown) 4127 * 4128 * Variable link_up is true if link is up, false if link is down. 4129 * The variable link_up is invalid if status is non zero. As a 4130 * result of this call, link status reporting becomes enabled 4131 */ 4132 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4133 { 4134 struct ice_phy_info *phy_info; 4135 int status = 0; 4136 4137 if (!pi || !link_up) 4138 return -EINVAL; 4139 4140 phy_info = &pi->phy; 4141 4142 if (phy_info->get_link_info) { 4143 status = ice_update_link_info(pi); 4144 4145 if (status) 4146 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4147 status); 4148 } 4149 4150 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4151 4152 return status; 4153 } 4154 4155 /** 4156 * ice_aq_set_link_restart_an 4157 * @pi: pointer to the port information structure 4158 * @ena_link: if true: enable link, if false: disable link 4159 * @cd: pointer to command details structure or NULL 4160 * 4161 * Sets up the link and restarts the Auto-Negotiation over the link. 4162 */ 4163 int 4164 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4165 struct ice_sq_cd *cd) 4166 { 4167 struct ice_aqc_restart_an *cmd; 4168 struct libie_aq_desc desc; 4169 4170 cmd = libie_aq_raw(&desc); 4171 4172 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4173 4174 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4175 cmd->lport_num = pi->lport; 4176 if (ena_link) 4177 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4178 else 4179 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4180 4181 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4182 } 4183 4184 /** 4185 * ice_aq_set_event_mask 4186 * @hw: pointer to the HW struct 4187 * @port_num: port number of the physical function 4188 * @mask: event mask to be set 4189 * @cd: pointer to command details structure or NULL 4190 * 4191 * Set event mask (0x0613) 4192 */ 4193 int 4194 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4195 struct ice_sq_cd *cd) 4196 { 4197 struct ice_aqc_set_event_mask *cmd; 4198 struct libie_aq_desc desc; 4199 4200 cmd = libie_aq_raw(&desc); 4201 4202 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4203 4204 cmd->lport_num = port_num; 4205 4206 cmd->event_mask = cpu_to_le16(mask); 4207 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4208 } 4209 4210 /** 4211 * ice_aq_set_mac_loopback 4212 * @hw: pointer to the HW struct 4213 * @ena_lpbk: Enable or Disable loopback 4214 * @cd: pointer to command details structure or NULL 4215 * 4216 * Enable/disable loopback on a given port 4217 */ 4218 int 4219 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4220 { 4221 struct ice_aqc_set_mac_lb *cmd; 4222 struct libie_aq_desc desc; 4223 4224 cmd = libie_aq_raw(&desc); 4225 4226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4227 if (ena_lpbk) 4228 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4229 4230 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4231 } 4232 4233 /** 4234 * ice_aq_set_port_id_led 4235 * @pi: pointer to the port information 4236 * @is_orig_mode: is this LED set to original mode (by the net-list) 4237 * @cd: pointer to command details structure or NULL 4238 * 4239 * Set LED value for the given port (0x06e9) 4240 */ 4241 int 4242 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4243 struct ice_sq_cd *cd) 4244 { 4245 struct ice_aqc_set_port_id_led *cmd; 4246 struct ice_hw *hw = pi->hw; 4247 struct libie_aq_desc desc; 4248 4249 cmd = libie_aq_raw(&desc); 4250 4251 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4252 4253 if (is_orig_mode) 4254 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4255 else 4256 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4257 4258 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4259 } 4260 4261 /** 4262 * ice_aq_get_port_options 4263 * @hw: pointer to the HW struct 4264 * @options: buffer for the resultant port options 4265 * @option_count: input - size of the buffer in port options structures, 4266 * output - number of returned port options 4267 * @lport: logical port to call the command with (optional) 4268 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4269 * when PF owns more than 1 port it must be true 4270 * @active_option_idx: index of active port option in returned buffer 4271 * @active_option_valid: active option in returned buffer is valid 4272 * @pending_option_idx: index of pending port option in returned buffer 4273 * @pending_option_valid: pending option in returned buffer is valid 4274 * 4275 * Calls Get Port Options AQC (0x06ea) and verifies result. 4276 */ 4277 int 4278 ice_aq_get_port_options(struct ice_hw *hw, 4279 struct ice_aqc_get_port_options_elem *options, 4280 u8 *option_count, u8 lport, bool lport_valid, 4281 u8 *active_option_idx, bool *active_option_valid, 4282 u8 *pending_option_idx, bool *pending_option_valid) 4283 { 4284 struct ice_aqc_get_port_options *cmd; 4285 struct libie_aq_desc desc; 4286 int status; 4287 u8 i; 4288 4289 /* options buffer shall be able to hold max returned options */ 4290 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4291 return -EINVAL; 4292 4293 cmd = libie_aq_raw(&desc); 4294 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4295 4296 if (lport_valid) 4297 cmd->lport_num = lport; 4298 cmd->lport_num_valid = lport_valid; 4299 4300 status = ice_aq_send_cmd(hw, &desc, options, 4301 *option_count * sizeof(*options), NULL); 4302 if (status) 4303 return status; 4304 4305 /* verify direct FW response & set output parameters */ 4306 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4307 cmd->port_options_count); 4308 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4309 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4310 cmd->port_options); 4311 if (*active_option_valid) { 4312 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4313 cmd->port_options); 4314 if (*active_option_idx > (*option_count - 1)) 4315 return -EIO; 4316 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4317 *active_option_idx); 4318 } 4319 4320 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4321 cmd->pending_port_option_status); 4322 if (*pending_option_valid) { 4323 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4324 cmd->pending_port_option_status); 4325 if (*pending_option_idx > (*option_count - 1)) 4326 return -EIO; 4327 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4328 *pending_option_idx); 4329 } 4330 4331 /* mask output options fields */ 4332 for (i = 0; i < *option_count; i++) { 4333 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4334 options[i].pmd); 4335 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4336 options[i].max_lane_speed); 4337 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4338 options[i].pmd, options[i].max_lane_speed); 4339 } 4340 4341 return 0; 4342 } 4343 4344 /** 4345 * ice_aq_set_port_option 4346 * @hw: pointer to the HW struct 4347 * @lport: logical port to call the command with 4348 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4349 * when PF owns more than 1 port it must be true 4350 * @new_option: new port option to be written 4351 * 4352 * Calls Set Port Options AQC (0x06eb). 4353 */ 4354 int 4355 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4356 u8 new_option) 4357 { 4358 struct ice_aqc_set_port_option *cmd; 4359 struct libie_aq_desc desc; 4360 4361 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4362 return -EINVAL; 4363 4364 cmd = libie_aq_raw(&desc); 4365 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4366 4367 if (lport_valid) 4368 cmd->lport_num = lport; 4369 4370 cmd->lport_num_valid = lport_valid; 4371 cmd->selected_port_option = new_option; 4372 4373 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4374 } 4375 4376 /** 4377 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4378 * @hw: pointer to the hw struct 4379 * 4380 * Return: PHY lane number on success, negative error code otherwise. 4381 */ 4382 int ice_get_phy_lane_number(struct ice_hw *hw) 4383 { 4384 struct ice_aqc_get_port_options_elem *options; 4385 unsigned int lport = 0; 4386 unsigned int lane; 4387 int err; 4388 4389 /* E82X does not have sequential IDs, lane number is PF ID. 4390 * For E825 device, the exception is the variant with external 4391 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4392 * mapping. 4393 */ 4394 if (hw->mac_type == ICE_MAC_GENERIC || 4395 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4396 return hw->pf_id; 4397 4398 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4399 if (!options) 4400 return -ENOMEM; 4401 4402 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4403 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4404 u8 speed, active_idx, pending_idx; 4405 bool active_valid, pending_valid; 4406 4407 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4408 true, &active_idx, &active_valid, 4409 &pending_idx, &pending_valid); 4410 if (err) 4411 goto err; 4412 4413 if (!active_valid) 4414 continue; 4415 4416 speed = options[active_idx].max_lane_speed; 4417 /* If we don't get speed for this lane, it's unoccupied */ 4418 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4419 continue; 4420 4421 if (hw->pf_id == lport) { 4422 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4423 ice_is_dual(hw) && !ice_is_primary(hw)) 4424 lane += ICE_PORTS_PER_QUAD; 4425 kfree(options); 4426 return lane; 4427 } 4428 lport++; 4429 } 4430 4431 /* PHY lane not found */ 4432 err = -ENXIO; 4433 err: 4434 kfree(options); 4435 return err; 4436 } 4437 4438 /** 4439 * ice_aq_sff_eeprom 4440 * @hw: pointer to the HW struct 4441 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4442 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4443 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4444 * @page: QSFP page 4445 * @set_page: set or ignore the page 4446 * @data: pointer to data buffer to be read/written to the I2C device. 4447 * @length: 1-16 for read, 1 for write. 4448 * @write: 0 read, 1 for write. 4449 * @cd: pointer to command details structure or NULL 4450 * 4451 * Read/Write SFF EEPROM (0x06EE) 4452 */ 4453 int 4454 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4455 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4456 bool write, struct ice_sq_cd *cd) 4457 { 4458 struct ice_aqc_sff_eeprom *cmd; 4459 struct libie_aq_desc desc; 4460 u16 i2c_bus_addr; 4461 int status; 4462 4463 if (!data || (mem_addr & 0xff00)) 4464 return -EINVAL; 4465 4466 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4467 cmd = libie_aq_raw(&desc); 4468 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4469 cmd->lport_num = (u8)(lport & 0xff); 4470 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4471 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4472 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4473 if (write) 4474 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4475 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4476 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4477 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4478 4479 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4480 return status; 4481 } 4482 4483 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4484 { 4485 switch (type) { 4486 case ICE_LUT_VSI: 4487 return ICE_LUT_VSI_SIZE; 4488 case ICE_LUT_GLOBAL: 4489 return ICE_LUT_GLOBAL_SIZE; 4490 case ICE_LUT_PF: 4491 return ICE_LUT_PF_SIZE; 4492 } 4493 WARN_ONCE(1, "incorrect type passed"); 4494 return ICE_LUT_VSI_SIZE; 4495 } 4496 4497 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4498 { 4499 switch (size) { 4500 case ICE_LUT_VSI_SIZE: 4501 return ICE_AQC_LUT_SIZE_SMALL; 4502 case ICE_LUT_GLOBAL_SIZE: 4503 return ICE_AQC_LUT_SIZE_512; 4504 case ICE_LUT_PF_SIZE: 4505 return ICE_AQC_LUT_SIZE_2K; 4506 } 4507 WARN_ONCE(1, "incorrect size passed"); 4508 return 0; 4509 } 4510 4511 /** 4512 * __ice_aq_get_set_rss_lut 4513 * @hw: pointer to the hardware structure 4514 * @params: RSS LUT parameters 4515 * @set: set true to set the table, false to get the table 4516 * 4517 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4518 */ 4519 static int 4520 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4521 struct ice_aq_get_set_rss_lut_params *params, bool set) 4522 { 4523 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4524 enum ice_lut_type lut_type = params->lut_type; 4525 struct ice_aqc_get_set_rss_lut *desc_params; 4526 enum ice_aqc_lut_flags flags; 4527 enum ice_lut_size lut_size; 4528 struct libie_aq_desc desc; 4529 u8 *lut = params->lut; 4530 4531 4532 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4533 return -EINVAL; 4534 4535 lut_size = ice_lut_type_to_size(lut_type); 4536 if (lut_size > params->lut_size) 4537 return -EINVAL; 4538 else if (set && lut_size != params->lut_size) 4539 return -EINVAL; 4540 4541 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4542 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4543 if (set) 4544 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4545 4546 desc_params = libie_aq_raw(&desc); 4547 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4548 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4549 4550 if (lut_type == ICE_LUT_GLOBAL) 4551 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4552 params->global_lut_id); 4553 4554 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4555 desc_params->flags = cpu_to_le16(flags); 4556 4557 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4558 } 4559 4560 /** 4561 * ice_aq_get_rss_lut 4562 * @hw: pointer to the hardware structure 4563 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4564 * 4565 * get the RSS lookup table, PF or VSI type 4566 */ 4567 int 4568 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4569 { 4570 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4571 } 4572 4573 /** 4574 * ice_aq_set_rss_lut 4575 * @hw: pointer to the hardware structure 4576 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4577 * 4578 * set the RSS lookup table, PF or VSI type 4579 */ 4580 int 4581 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4582 { 4583 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4584 } 4585 4586 /** 4587 * __ice_aq_get_set_rss_key 4588 * @hw: pointer to the HW struct 4589 * @vsi_id: VSI FW index 4590 * @key: pointer to key info struct 4591 * @set: set true to set the key, false to get the key 4592 * 4593 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4594 */ 4595 static int 4596 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4597 struct ice_aqc_get_set_rss_keys *key, bool set) 4598 { 4599 struct ice_aqc_get_set_rss_key *desc_params; 4600 u16 key_size = sizeof(*key); 4601 struct libie_aq_desc desc; 4602 4603 if (set) { 4604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4605 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4606 } else { 4607 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4608 } 4609 4610 desc_params = libie_aq_raw(&desc); 4611 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4612 4613 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4614 } 4615 4616 /** 4617 * ice_aq_get_rss_key 4618 * @hw: pointer to the HW struct 4619 * @vsi_handle: software VSI handle 4620 * @key: pointer to key info struct 4621 * 4622 * get the RSS key per VSI 4623 */ 4624 int 4625 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4626 struct ice_aqc_get_set_rss_keys *key) 4627 { 4628 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4629 return -EINVAL; 4630 4631 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4632 key, false); 4633 } 4634 4635 /** 4636 * ice_aq_set_rss_key 4637 * @hw: pointer to the HW struct 4638 * @vsi_handle: software VSI handle 4639 * @keys: pointer to key info struct 4640 * 4641 * set the RSS key per VSI 4642 */ 4643 int 4644 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4645 struct ice_aqc_get_set_rss_keys *keys) 4646 { 4647 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4648 return -EINVAL; 4649 4650 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4651 keys, true); 4652 } 4653 4654 /** 4655 * ice_aq_add_lan_txq 4656 * @hw: pointer to the hardware structure 4657 * @num_qgrps: Number of added queue groups 4658 * @qg_list: list of queue groups to be added 4659 * @buf_size: size of buffer for indirect command 4660 * @cd: pointer to command details structure or NULL 4661 * 4662 * Add Tx LAN queue (0x0C30) 4663 * 4664 * NOTE: 4665 * Prior to calling add Tx LAN queue: 4666 * Initialize the following as part of the Tx queue context: 4667 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4668 * Cache profile and Packet shaper profile. 4669 * 4670 * After add Tx LAN queue AQ command is completed: 4671 * Interrupts should be associated with specific queues, 4672 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4673 * flow. 4674 */ 4675 static int 4676 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4677 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4678 struct ice_sq_cd *cd) 4679 { 4680 struct ice_aqc_add_tx_qgrp *list; 4681 struct ice_aqc_add_txqs *cmd; 4682 struct libie_aq_desc desc; 4683 u16 i, sum_size = 0; 4684 4685 cmd = libie_aq_raw(&desc); 4686 4687 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4688 4689 if (!qg_list) 4690 return -EINVAL; 4691 4692 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4693 return -EINVAL; 4694 4695 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4696 sum_size += struct_size(list, txqs, list->num_txqs); 4697 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4698 list->num_txqs); 4699 } 4700 4701 if (buf_size != sum_size) 4702 return -EINVAL; 4703 4704 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4705 4706 cmd->num_qgrps = num_qgrps; 4707 4708 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4709 } 4710 4711 /** 4712 * ice_aq_dis_lan_txq 4713 * @hw: pointer to the hardware structure 4714 * @num_qgrps: number of groups in the list 4715 * @qg_list: the list of groups to disable 4716 * @buf_size: the total size of the qg_list buffer in bytes 4717 * @rst_src: if called due to reset, specifies the reset source 4718 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4719 * @cd: pointer to command details structure or NULL 4720 * 4721 * Disable LAN Tx queue (0x0C31) 4722 */ 4723 static int 4724 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4725 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4726 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4727 struct ice_sq_cd *cd) 4728 { 4729 struct ice_aqc_dis_txq_item *item; 4730 struct ice_aqc_dis_txqs *cmd; 4731 struct libie_aq_desc desc; 4732 u16 vmvf_and_timeout; 4733 u16 i, sz = 0; 4734 int status; 4735 4736 cmd = libie_aq_raw(&desc); 4737 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4738 4739 /* qg_list can be NULL only in VM/VF reset flow */ 4740 if (!qg_list && !rst_src) 4741 return -EINVAL; 4742 4743 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4744 return -EINVAL; 4745 4746 cmd->num_entries = num_qgrps; 4747 4748 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4749 4750 switch (rst_src) { 4751 case ICE_VM_RESET: 4752 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4753 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4754 break; 4755 case ICE_VF_RESET: 4756 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4757 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4758 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4759 ICE_AQC_Q_DIS_VMVF_NUM_M; 4760 break; 4761 case ICE_NO_RESET: 4762 default: 4763 break; 4764 } 4765 4766 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4767 4768 /* flush pipe on time out */ 4769 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4770 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4771 if (!qg_list) 4772 goto do_aq; 4773 4774 /* set RD bit to indicate that command buffer is provided by the driver 4775 * and it needs to be read by the firmware 4776 */ 4777 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4778 4779 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4780 u16 item_size = struct_size(item, q_id, item->num_qs); 4781 4782 /* If the num of queues is even, add 2 bytes of padding */ 4783 if ((item->num_qs % 2) == 0) 4784 item_size += 2; 4785 4786 sz += item_size; 4787 4788 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4789 } 4790 4791 if (buf_size != sz) 4792 return -EINVAL; 4793 4794 do_aq: 4795 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4796 if (status) { 4797 if (!qg_list) 4798 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4799 vmvf_num, hw->adminq.sq_last_status); 4800 else 4801 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4802 le16_to_cpu(qg_list[0].q_id[0]), 4803 hw->adminq.sq_last_status); 4804 } 4805 return status; 4806 } 4807 4808 /** 4809 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4810 * @hw: pointer to the hardware structure 4811 * @buf: buffer for command 4812 * @buf_size: size of buffer in bytes 4813 * @num_qs: number of queues being configured 4814 * @oldport: origination lport 4815 * @newport: destination lport 4816 * @mode: cmd_type for move to use 4817 * @cd: pointer to command details structure or NULL 4818 * 4819 * Move/Configure LAN Tx queue (0x0C32) 4820 * 4821 * Return: Zero on success, associated error code on failure. 4822 */ 4823 int 4824 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4825 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4826 u8 mode, struct ice_sq_cd *cd) 4827 { 4828 struct ice_aqc_cfg_txqs *cmd; 4829 struct libie_aq_desc desc; 4830 int status; 4831 4832 cmd = libie_aq_raw(&desc); 4833 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4834 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4835 4836 if (!buf) 4837 return -EINVAL; 4838 4839 cmd->cmd_type = mode; 4840 cmd->num_qs = num_qs; 4841 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4842 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4843 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4844 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4845 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4846 cmd->blocked_cgds = 0; 4847 4848 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4849 if (status) 4850 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4851 hw->adminq.sq_last_status); 4852 return status; 4853 } 4854 4855 /** 4856 * ice_aq_add_rdma_qsets 4857 * @hw: pointer to the hardware structure 4858 * @num_qset_grps: Number of RDMA Qset groups 4859 * @qset_list: list of Qset groups to be added 4860 * @buf_size: size of buffer for indirect command 4861 * @cd: pointer to command details structure or NULL 4862 * 4863 * Add Tx RDMA Qsets (0x0C33) 4864 */ 4865 static int 4866 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4867 struct ice_aqc_add_rdma_qset_data *qset_list, 4868 u16 buf_size, struct ice_sq_cd *cd) 4869 { 4870 struct ice_aqc_add_rdma_qset_data *list; 4871 struct ice_aqc_add_rdma_qset *cmd; 4872 struct libie_aq_desc desc; 4873 u16 i, sum_size = 0; 4874 4875 cmd = libie_aq_raw(&desc); 4876 4877 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4878 4879 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4880 return -EINVAL; 4881 4882 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4883 u16 num_qsets = le16_to_cpu(list->num_qsets); 4884 4885 sum_size += struct_size(list, rdma_qsets, num_qsets); 4886 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4887 num_qsets); 4888 } 4889 4890 if (buf_size != sum_size) 4891 return -EINVAL; 4892 4893 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4894 4895 cmd->num_qset_grps = num_qset_grps; 4896 4897 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4898 } 4899 4900 /** 4901 * ice_aq_set_txtimeq - set Tx time queues 4902 * @hw: pointer to the hardware structure 4903 * @txtimeq: first Tx time queue id to configure 4904 * @q_count: number of queues to configure 4905 * @txtime_qg: queue group to be set 4906 * @buf_size: size of buffer for indirect command 4907 * @cd: pointer to command details structure or NULL 4908 * 4909 * Set Tx Time queue (0x0C35) 4910 * Return: 0 on success or negative value on failure. 4911 */ 4912 int 4913 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4914 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4915 struct ice_sq_cd *cd) 4916 { 4917 struct ice_aqc_set_txtimeqs *cmd; 4918 struct libie_aq_desc desc; 4919 u16 size; 4920 4921 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4922 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4923 return -EINVAL; 4924 4925 size = struct_size(txtime_qg, txtimeqs, q_count); 4926 if (buf_size != size) 4927 return -EINVAL; 4928 4929 cmd = libie_aq_raw(&desc); 4930 4931 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4932 4933 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4934 4935 cmd->q_id = cpu_to_le16(txtimeq); 4936 cmd->q_amount = cpu_to_le16(q_count); 4937 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4938 } 4939 4940 /* End of FW Admin Queue command wrappers */ 4941 4942 /** 4943 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4944 * @hw: pointer to the HW struct 4945 * @vsi_handle: software VSI handle 4946 * @tc: TC number 4947 * @q_handle: software queue handle 4948 */ 4949 struct ice_q_ctx * 4950 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4951 { 4952 struct ice_vsi_ctx *vsi; 4953 struct ice_q_ctx *q_ctx; 4954 4955 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4956 if (!vsi) 4957 return NULL; 4958 if (q_handle >= vsi->num_lan_q_entries[tc]) 4959 return NULL; 4960 if (!vsi->lan_q_ctx[tc]) 4961 return NULL; 4962 q_ctx = vsi->lan_q_ctx[tc]; 4963 return &q_ctx[q_handle]; 4964 } 4965 4966 /** 4967 * ice_ena_vsi_txq 4968 * @pi: port information structure 4969 * @vsi_handle: software VSI handle 4970 * @tc: TC number 4971 * @q_handle: software queue handle 4972 * @num_qgrps: Number of added queue groups 4973 * @buf: list of queue groups to be added 4974 * @buf_size: size of buffer for indirect command 4975 * @cd: pointer to command details structure or NULL 4976 * 4977 * This function adds one LAN queue 4978 */ 4979 int 4980 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4981 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4982 struct ice_sq_cd *cd) 4983 { 4984 struct ice_aqc_txsched_elem_data node = { 0 }; 4985 struct ice_sched_node *parent; 4986 struct ice_q_ctx *q_ctx; 4987 struct ice_hw *hw; 4988 int status; 4989 4990 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4991 return -EIO; 4992 4993 if (num_qgrps > 1 || buf->num_txqs > 1) 4994 return -ENOSPC; 4995 4996 hw = pi->hw; 4997 4998 if (!ice_is_vsi_valid(hw, vsi_handle)) 4999 return -EINVAL; 5000 5001 mutex_lock(&pi->sched_lock); 5002 5003 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 5004 if (!q_ctx) { 5005 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 5006 q_handle); 5007 status = -EINVAL; 5008 goto ena_txq_exit; 5009 } 5010 5011 /* find a parent node */ 5012 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5013 ICE_SCHED_NODE_OWNER_LAN); 5014 if (!parent) { 5015 status = -EINVAL; 5016 goto ena_txq_exit; 5017 } 5018 5019 buf->parent_teid = parent->info.node_teid; 5020 node.parent_teid = parent->info.node_teid; 5021 /* Mark that the values in the "generic" section as valid. The default 5022 * value in the "generic" section is zero. This means that : 5023 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 5024 * - 0 priority among siblings, indicated by Bit 1-3. 5025 * - WFQ, indicated by Bit 4. 5026 * - 0 Adjustment value is used in PSM credit update flow, indicated by 5027 * Bit 5-6. 5028 * - Bit 7 is reserved. 5029 * Without setting the generic section as valid in valid_sections, the 5030 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5031 */ 5032 buf->txqs[0].info.valid_sections = 5033 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5034 ICE_AQC_ELEM_VALID_EIR; 5035 buf->txqs[0].info.generic = 0; 5036 buf->txqs[0].info.cir_bw.bw_profile_idx = 5037 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5038 buf->txqs[0].info.cir_bw.bw_alloc = 5039 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5040 buf->txqs[0].info.eir_bw.bw_profile_idx = 5041 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5042 buf->txqs[0].info.eir_bw.bw_alloc = 5043 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5044 5045 /* add the LAN queue */ 5046 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5047 if (status) { 5048 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5049 le16_to_cpu(buf->txqs[0].txq_id), 5050 hw->adminq.sq_last_status); 5051 goto ena_txq_exit; 5052 } 5053 5054 node.node_teid = buf->txqs[0].q_teid; 5055 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5056 q_ctx->q_handle = q_handle; 5057 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5058 5059 /* add a leaf node into scheduler tree queue layer */ 5060 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5061 if (!status) 5062 status = ice_sched_replay_q_bw(pi, q_ctx); 5063 5064 ena_txq_exit: 5065 mutex_unlock(&pi->sched_lock); 5066 return status; 5067 } 5068 5069 /** 5070 * ice_dis_vsi_txq 5071 * @pi: port information structure 5072 * @vsi_handle: software VSI handle 5073 * @tc: TC number 5074 * @num_queues: number of queues 5075 * @q_handles: pointer to software queue handle array 5076 * @q_ids: pointer to the q_id array 5077 * @q_teids: pointer to queue node teids 5078 * @rst_src: if called due to reset, specifies the reset source 5079 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5080 * @cd: pointer to command details structure or NULL 5081 * 5082 * This function removes queues and their corresponding nodes in SW DB 5083 */ 5084 int 5085 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5086 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5087 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5088 struct ice_sq_cd *cd) 5089 { 5090 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5091 u16 i, buf_size = __struct_size(qg_list); 5092 struct ice_q_ctx *q_ctx; 5093 int status = -ENOENT; 5094 struct ice_hw *hw; 5095 5096 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5097 return -EIO; 5098 5099 hw = pi->hw; 5100 5101 if (!num_queues) { 5102 /* if queue is disabled already yet the disable queue command 5103 * has to be sent to complete the VF reset, then call 5104 * ice_aq_dis_lan_txq without any queue information 5105 */ 5106 if (rst_src) 5107 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5108 vmvf_num, NULL); 5109 return -EIO; 5110 } 5111 5112 mutex_lock(&pi->sched_lock); 5113 5114 for (i = 0; i < num_queues; i++) { 5115 struct ice_sched_node *node; 5116 5117 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5118 if (!node) 5119 continue; 5120 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5121 if (!q_ctx) { 5122 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5123 q_handles[i]); 5124 continue; 5125 } 5126 if (q_ctx->q_handle != q_handles[i]) { 5127 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5128 q_ctx->q_handle, q_handles[i]); 5129 continue; 5130 } 5131 qg_list->parent_teid = node->info.parent_teid; 5132 qg_list->num_qs = 1; 5133 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5134 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5135 vmvf_num, cd); 5136 5137 if (status) 5138 break; 5139 ice_free_sched_node(pi, node); 5140 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5141 q_ctx->q_teid = ICE_INVAL_TEID; 5142 } 5143 mutex_unlock(&pi->sched_lock); 5144 return status; 5145 } 5146 5147 /** 5148 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5149 * @pi: port information structure 5150 * @vsi_handle: software VSI handle 5151 * @tc_bitmap: TC bitmap 5152 * @maxqs: max queues array per TC 5153 * @owner: LAN or RDMA 5154 * 5155 * This function adds/updates the VSI queues per TC. 5156 */ 5157 static int 5158 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5159 u16 *maxqs, u8 owner) 5160 { 5161 int status = 0; 5162 u8 i; 5163 5164 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5165 return -EIO; 5166 5167 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5168 return -EINVAL; 5169 5170 mutex_lock(&pi->sched_lock); 5171 5172 ice_for_each_traffic_class(i) { 5173 /* configuration is possible only if TC node is present */ 5174 if (!ice_sched_get_tc_node(pi, i)) 5175 continue; 5176 5177 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5178 ice_is_tc_ena(tc_bitmap, i)); 5179 if (status) 5180 break; 5181 } 5182 5183 mutex_unlock(&pi->sched_lock); 5184 return status; 5185 } 5186 5187 /** 5188 * ice_cfg_vsi_lan - configure VSI LAN queues 5189 * @pi: port information structure 5190 * @vsi_handle: software VSI handle 5191 * @tc_bitmap: TC bitmap 5192 * @max_lanqs: max LAN queues array per TC 5193 * 5194 * This function adds/updates the VSI LAN queues per TC. 5195 */ 5196 int 5197 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5198 u16 *max_lanqs) 5199 { 5200 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5201 ICE_SCHED_NODE_OWNER_LAN); 5202 } 5203 5204 /** 5205 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5206 * @pi: port information structure 5207 * @vsi_handle: software VSI handle 5208 * @tc_bitmap: TC bitmap 5209 * @max_rdmaqs: max RDMA queues array per TC 5210 * 5211 * This function adds/updates the VSI RDMA queues per TC. 5212 */ 5213 int 5214 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5215 u16 *max_rdmaqs) 5216 { 5217 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5218 ICE_SCHED_NODE_OWNER_RDMA); 5219 } 5220 5221 /** 5222 * ice_ena_vsi_rdma_qset 5223 * @pi: port information structure 5224 * @vsi_handle: software VSI handle 5225 * @tc: TC number 5226 * @rdma_qset: pointer to RDMA Qset 5227 * @num_qsets: number of RDMA Qsets 5228 * @qset_teid: pointer to Qset node TEIDs 5229 * 5230 * This function adds RDMA Qset 5231 */ 5232 int 5233 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5234 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5235 { 5236 struct ice_aqc_txsched_elem_data node = { 0 }; 5237 struct ice_aqc_add_rdma_qset_data *buf; 5238 struct ice_sched_node *parent; 5239 struct ice_hw *hw; 5240 u16 i, buf_size; 5241 int ret; 5242 5243 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5244 return -EIO; 5245 hw = pi->hw; 5246 5247 if (!ice_is_vsi_valid(hw, vsi_handle)) 5248 return -EINVAL; 5249 5250 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5251 buf = kzalloc(buf_size, GFP_KERNEL); 5252 if (!buf) 5253 return -ENOMEM; 5254 mutex_lock(&pi->sched_lock); 5255 5256 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5257 ICE_SCHED_NODE_OWNER_RDMA); 5258 if (!parent) { 5259 ret = -EINVAL; 5260 goto rdma_error_exit; 5261 } 5262 buf->parent_teid = parent->info.node_teid; 5263 node.parent_teid = parent->info.node_teid; 5264 5265 buf->num_qsets = cpu_to_le16(num_qsets); 5266 for (i = 0; i < num_qsets; i++) { 5267 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5268 buf->rdma_qsets[i].info.valid_sections = 5269 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5270 ICE_AQC_ELEM_VALID_EIR; 5271 buf->rdma_qsets[i].info.generic = 0; 5272 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5273 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5274 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5275 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5276 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5277 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5278 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5279 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5280 } 5281 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5282 if (ret) { 5283 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5284 goto rdma_error_exit; 5285 } 5286 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5287 for (i = 0; i < num_qsets; i++) { 5288 node.node_teid = buf->rdma_qsets[i].qset_teid; 5289 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5290 &node, NULL); 5291 if (ret) 5292 break; 5293 qset_teid[i] = le32_to_cpu(node.node_teid); 5294 } 5295 rdma_error_exit: 5296 mutex_unlock(&pi->sched_lock); 5297 kfree(buf); 5298 return ret; 5299 } 5300 5301 /** 5302 * ice_dis_vsi_rdma_qset - free RDMA resources 5303 * @pi: port_info struct 5304 * @count: number of RDMA Qsets to free 5305 * @qset_teid: TEID of Qset node 5306 * @q_id: list of queue IDs being disabled 5307 */ 5308 int 5309 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5310 u16 *q_id) 5311 { 5312 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5313 u16 qg_size = __struct_size(qg_list); 5314 struct ice_hw *hw; 5315 int status = 0; 5316 int i; 5317 5318 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5319 return -EIO; 5320 5321 hw = pi->hw; 5322 5323 mutex_lock(&pi->sched_lock); 5324 5325 for (i = 0; i < count; i++) { 5326 struct ice_sched_node *node; 5327 5328 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5329 if (!node) 5330 continue; 5331 5332 qg_list->parent_teid = node->info.parent_teid; 5333 qg_list->num_qs = 1; 5334 qg_list->q_id[0] = 5335 cpu_to_le16(q_id[i] | 5336 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5337 5338 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5339 ICE_NO_RESET, 0, NULL); 5340 if (status) 5341 break; 5342 5343 ice_free_sched_node(pi, node); 5344 } 5345 5346 mutex_unlock(&pi->sched_lock); 5347 return status; 5348 } 5349 5350 /** 5351 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5352 * @hw: pointer to the HW struct 5353 * @dpll_idx: index of dpll to be measured 5354 * @meas: array to be filled with results 5355 * @meas_num: max number of results array can hold 5356 * 5357 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5358 * pins on given dpll. 5359 * 5360 * Return: 0 on success or negative value on failure. 5361 */ 5362 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5363 struct ice_cgu_input_measure *meas, 5364 u16 meas_num) 5365 { 5366 struct ice_aqc_get_cgu_input_measure *cmd; 5367 struct libie_aq_desc desc; 5368 5369 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5370 cmd = libie_aq_raw(&desc); 5371 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5372 5373 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5374 } 5375 5376 /** 5377 * ice_aq_get_cgu_abilities - get cgu abilities 5378 * @hw: pointer to the HW struct 5379 * @abilities: CGU abilities 5380 * 5381 * Get CGU abilities (0x0C61) 5382 * Return: 0 on success or negative value on failure. 5383 */ 5384 int 5385 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5386 struct ice_aqc_get_cgu_abilities *abilities) 5387 { 5388 struct libie_aq_desc desc; 5389 5390 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5391 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5392 } 5393 5394 /** 5395 * ice_aq_set_input_pin_cfg - set input pin config 5396 * @hw: pointer to the HW struct 5397 * @input_idx: Input index 5398 * @flags1: Input flags 5399 * @flags2: Input flags 5400 * @freq: Frequency in Hz 5401 * @phase_delay: Delay in ps 5402 * 5403 * Set CGU input config (0x0C62) 5404 * Return: 0 on success or negative value on failure. 5405 */ 5406 int 5407 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5408 u32 freq, s32 phase_delay) 5409 { 5410 struct ice_aqc_set_cgu_input_config *cmd; 5411 struct libie_aq_desc desc; 5412 5413 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5414 cmd = libie_aq_raw(&desc); 5415 cmd->input_idx = input_idx; 5416 cmd->flags1 = flags1; 5417 cmd->flags2 = flags2; 5418 cmd->freq = cpu_to_le32(freq); 5419 cmd->phase_delay = cpu_to_le32(phase_delay); 5420 5421 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5422 } 5423 5424 /** 5425 * ice_aq_get_input_pin_cfg - get input pin config 5426 * @hw: pointer to the HW struct 5427 * @input_idx: Input index 5428 * @status: Pin status 5429 * @type: Pin type 5430 * @flags1: Input flags 5431 * @flags2: Input flags 5432 * @freq: Frequency in Hz 5433 * @phase_delay: Delay in ps 5434 * 5435 * Get CGU input config (0x0C63) 5436 * Return: 0 on success or negative value on failure. 5437 */ 5438 int 5439 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5440 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5441 { 5442 struct ice_aqc_get_cgu_input_config *cmd; 5443 struct libie_aq_desc desc; 5444 int ret; 5445 5446 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5447 cmd = libie_aq_raw(&desc); 5448 cmd->input_idx = input_idx; 5449 5450 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5451 if (!ret) { 5452 if (status) 5453 *status = cmd->status; 5454 if (type) 5455 *type = cmd->type; 5456 if (flags1) 5457 *flags1 = cmd->flags1; 5458 if (flags2) 5459 *flags2 = cmd->flags2; 5460 if (freq) 5461 *freq = le32_to_cpu(cmd->freq); 5462 if (phase_delay) 5463 *phase_delay = le32_to_cpu(cmd->phase_delay); 5464 } 5465 5466 return ret; 5467 } 5468 5469 /** 5470 * ice_aq_set_output_pin_cfg - set output pin config 5471 * @hw: pointer to the HW struct 5472 * @output_idx: Output index 5473 * @flags: Output flags 5474 * @src_sel: Index of DPLL block 5475 * @freq: Output frequency 5476 * @phase_delay: Output phase compensation 5477 * 5478 * Set CGU output config (0x0C64) 5479 * Return: 0 on success or negative value on failure. 5480 */ 5481 int 5482 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5483 u8 src_sel, u32 freq, s32 phase_delay) 5484 { 5485 struct ice_aqc_set_cgu_output_config *cmd; 5486 struct libie_aq_desc desc; 5487 5488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5489 cmd = libie_aq_raw(&desc); 5490 cmd->output_idx = output_idx; 5491 cmd->flags = flags; 5492 cmd->src_sel = src_sel; 5493 cmd->freq = cpu_to_le32(freq); 5494 cmd->phase_delay = cpu_to_le32(phase_delay); 5495 5496 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5497 } 5498 5499 /** 5500 * ice_aq_get_output_pin_cfg - get output pin config 5501 * @hw: pointer to the HW struct 5502 * @output_idx: Output index 5503 * @flags: Output flags 5504 * @src_sel: Internal DPLL source 5505 * @freq: Output frequency 5506 * @src_freq: Source frequency 5507 * 5508 * Get CGU output config (0x0C65) 5509 * Return: 0 on success or negative value on failure. 5510 */ 5511 int 5512 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5513 u8 *src_sel, u32 *freq, u32 *src_freq) 5514 { 5515 struct ice_aqc_get_cgu_output_config *cmd; 5516 struct libie_aq_desc desc; 5517 int ret; 5518 5519 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5520 cmd = libie_aq_raw(&desc); 5521 cmd->output_idx = output_idx; 5522 5523 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5524 if (!ret) { 5525 if (flags) 5526 *flags = cmd->flags; 5527 if (src_sel) 5528 *src_sel = cmd->src_sel; 5529 if (freq) 5530 *freq = le32_to_cpu(cmd->freq); 5531 if (src_freq) 5532 *src_freq = le32_to_cpu(cmd->src_freq); 5533 } 5534 5535 return ret; 5536 } 5537 5538 /** 5539 * ice_aq_get_cgu_dpll_status - get dpll status 5540 * @hw: pointer to the HW struct 5541 * @dpll_num: DPLL index 5542 * @ref_state: Reference clock state 5543 * @config: current DPLL config 5544 * @dpll_state: current DPLL state 5545 * @phase_offset: Phase offset in ns 5546 * @eec_mode: EEC_mode 5547 * 5548 * Get CGU DPLL status (0x0C66) 5549 * Return: 0 on success or negative value on failure. 5550 */ 5551 int 5552 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5553 u8 *dpll_state, u8 *config, s64 *phase_offset, 5554 u8 *eec_mode) 5555 { 5556 struct ice_aqc_get_cgu_dpll_status *cmd; 5557 struct libie_aq_desc desc; 5558 int status; 5559 5560 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5561 cmd = libie_aq_raw(&desc); 5562 cmd->dpll_num = dpll_num; 5563 5564 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5565 if (!status) { 5566 *ref_state = cmd->ref_state; 5567 *dpll_state = cmd->dpll_state; 5568 *config = cmd->config; 5569 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5570 *phase_offset <<= 32; 5571 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5572 *phase_offset = sign_extend64(*phase_offset, 47); 5573 *eec_mode = cmd->eec_mode; 5574 } 5575 5576 return status; 5577 } 5578 5579 /** 5580 * ice_aq_set_cgu_dpll_config - set dpll config 5581 * @hw: pointer to the HW struct 5582 * @dpll_num: DPLL index 5583 * @ref_state: Reference clock state 5584 * @config: DPLL config 5585 * @eec_mode: EEC mode 5586 * 5587 * Set CGU DPLL config (0x0C67) 5588 * Return: 0 on success or negative value on failure. 5589 */ 5590 int 5591 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5592 u8 config, u8 eec_mode) 5593 { 5594 struct ice_aqc_set_cgu_dpll_config *cmd; 5595 struct libie_aq_desc desc; 5596 5597 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5598 cmd = libie_aq_raw(&desc); 5599 cmd->dpll_num = dpll_num; 5600 cmd->ref_state = ref_state; 5601 cmd->config = config; 5602 cmd->eec_mode = eec_mode; 5603 5604 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5605 } 5606 5607 /** 5608 * ice_aq_set_cgu_ref_prio - set input reference priority 5609 * @hw: pointer to the HW struct 5610 * @dpll_num: DPLL index 5611 * @ref_idx: Reference pin index 5612 * @ref_priority: Reference input priority 5613 * 5614 * Set CGU reference priority (0x0C68) 5615 * Return: 0 on success or negative value on failure. 5616 */ 5617 int 5618 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5619 u8 ref_priority) 5620 { 5621 struct ice_aqc_set_cgu_ref_prio *cmd; 5622 struct libie_aq_desc desc; 5623 5624 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5625 cmd = libie_aq_raw(&desc); 5626 cmd->dpll_num = dpll_num; 5627 cmd->ref_idx = ref_idx; 5628 cmd->ref_priority = ref_priority; 5629 5630 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5631 } 5632 5633 /** 5634 * ice_aq_get_cgu_ref_prio - get input reference priority 5635 * @hw: pointer to the HW struct 5636 * @dpll_num: DPLL index 5637 * @ref_idx: Reference pin index 5638 * @ref_prio: Reference input priority 5639 * 5640 * Get CGU reference priority (0x0C69) 5641 * Return: 0 on success or negative value on failure. 5642 */ 5643 int 5644 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5645 u8 *ref_prio) 5646 { 5647 struct ice_aqc_get_cgu_ref_prio *cmd; 5648 struct libie_aq_desc desc; 5649 int status; 5650 5651 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5652 cmd = libie_aq_raw(&desc); 5653 cmd->dpll_num = dpll_num; 5654 cmd->ref_idx = ref_idx; 5655 5656 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5657 if (!status) 5658 *ref_prio = cmd->ref_priority; 5659 5660 return status; 5661 } 5662 5663 /** 5664 * ice_aq_get_cgu_info - get cgu info 5665 * @hw: pointer to the HW struct 5666 * @cgu_id: CGU ID 5667 * @cgu_cfg_ver: CGU config version 5668 * @cgu_fw_ver: CGU firmware version 5669 * 5670 * Get CGU info (0x0C6A) 5671 * Return: 0 on success or negative value on failure. 5672 */ 5673 int 5674 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5675 u32 *cgu_fw_ver) 5676 { 5677 struct ice_aqc_get_cgu_info *cmd; 5678 struct libie_aq_desc desc; 5679 int status; 5680 5681 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5682 cmd = libie_aq_raw(&desc); 5683 5684 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5685 if (!status) { 5686 *cgu_id = le32_to_cpu(cmd->cgu_id); 5687 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5688 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5689 } 5690 5691 return status; 5692 } 5693 5694 /** 5695 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5696 * @hw: pointer to the HW struct 5697 * @phy_output: PHY reference clock output pin 5698 * @enable: GPIO state to be applied 5699 * @freq: PHY output frequency 5700 * 5701 * Set phy recovered clock as reference (0x0630) 5702 * Return: 0 on success or negative value on failure. 5703 */ 5704 int 5705 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5706 u32 *freq) 5707 { 5708 struct ice_aqc_set_phy_rec_clk_out *cmd; 5709 struct libie_aq_desc desc; 5710 int status; 5711 5712 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5713 cmd = libie_aq_raw(&desc); 5714 cmd->phy_output = phy_output; 5715 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5716 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5717 cmd->freq = cpu_to_le32(*freq); 5718 5719 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5720 if (!status) 5721 *freq = le32_to_cpu(cmd->freq); 5722 5723 return status; 5724 } 5725 5726 /** 5727 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5728 * @hw: pointer to the HW struct 5729 * @phy_output: PHY reference clock output pin 5730 * @port_num: Port number 5731 * @flags: PHY flags 5732 * @node_handle: PHY output frequency 5733 * 5734 * Get PHY recovered clock output info (0x0631) 5735 * Return: 0 on success or negative value on failure. 5736 */ 5737 int 5738 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5739 u8 *flags, u16 *node_handle) 5740 { 5741 struct ice_aqc_get_phy_rec_clk_out *cmd; 5742 struct libie_aq_desc desc; 5743 int status; 5744 5745 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5746 cmd = libie_aq_raw(&desc); 5747 cmd->phy_output = *phy_output; 5748 5749 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5750 if (!status) { 5751 *phy_output = cmd->phy_output; 5752 if (port_num) 5753 *port_num = cmd->port_num; 5754 if (flags) 5755 *flags = cmd->flags; 5756 if (node_handle) 5757 *node_handle = le16_to_cpu(cmd->node_handle); 5758 } 5759 5760 return status; 5761 } 5762 5763 /** 5764 * ice_aq_get_sensor_reading 5765 * @hw: pointer to the HW struct 5766 * @data: pointer to data to be read from the sensor 5767 * 5768 * Get sensor reading (0x0632) 5769 */ 5770 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5771 struct ice_aqc_get_sensor_reading_resp *data) 5772 { 5773 struct ice_aqc_get_sensor_reading *cmd; 5774 struct libie_aq_desc desc; 5775 int status; 5776 5777 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5778 cmd = libie_aq_raw(&desc); 5779 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5780 #define ICE_INTERNAL_TEMP_SENSOR 0 5781 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5782 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5783 5784 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5785 if (!status) 5786 memcpy(data, &desc.params.raw, 5787 sizeof(*data)); 5788 5789 return status; 5790 } 5791 5792 /** 5793 * ice_replay_pre_init - replay pre initialization 5794 * @hw: pointer to the HW struct 5795 * 5796 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5797 */ 5798 static int ice_replay_pre_init(struct ice_hw *hw) 5799 { 5800 struct ice_switch_info *sw = hw->switch_info; 5801 u8 i; 5802 5803 /* Delete old entries from replay filter list head if there is any */ 5804 ice_rm_all_sw_replay_rule_info(hw); 5805 /* In start of replay, move entries into replay_rules list, it 5806 * will allow adding rules entries back to filt_rules list, 5807 * which is operational list. 5808 */ 5809 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5810 list_replace_init(&sw->recp_list[i].filt_rules, 5811 &sw->recp_list[i].filt_replay_rules); 5812 ice_sched_replay_agg_vsi_preinit(hw); 5813 5814 return 0; 5815 } 5816 5817 /** 5818 * ice_replay_vsi - replay VSI configuration 5819 * @hw: pointer to the HW struct 5820 * @vsi_handle: driver VSI handle 5821 * 5822 * Restore all VSI configuration after reset. It is required to call this 5823 * function with main VSI first. 5824 */ 5825 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5826 { 5827 int status; 5828 5829 if (!ice_is_vsi_valid(hw, vsi_handle)) 5830 return -EINVAL; 5831 5832 /* Replay pre-initialization if there is any */ 5833 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5834 status = ice_replay_pre_init(hw); 5835 if (status) 5836 return status; 5837 } 5838 /* Replay per VSI all RSS configurations */ 5839 status = ice_replay_rss_cfg(hw, vsi_handle); 5840 if (status) 5841 return status; 5842 /* Replay per VSI all filters */ 5843 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5844 if (!status) 5845 status = ice_replay_vsi_agg(hw, vsi_handle); 5846 return status; 5847 } 5848 5849 /** 5850 * ice_replay_post - post replay configuration cleanup 5851 * @hw: pointer to the HW struct 5852 * 5853 * Post replay cleanup. 5854 */ 5855 void ice_replay_post(struct ice_hw *hw) 5856 { 5857 /* Delete old entries from replay filter list head */ 5858 ice_rm_all_sw_replay_rule_info(hw); 5859 ice_sched_replay_agg(hw); 5860 } 5861 5862 /** 5863 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5864 * @hw: ptr to the hardware info 5865 * @reg: offset of 64 bit HW register to read from 5866 * @prev_stat_loaded: bool to specify if previous stats are loaded 5867 * @prev_stat: ptr to previous loaded stat value 5868 * @cur_stat: ptr to current stat value 5869 */ 5870 void 5871 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5872 u64 *prev_stat, u64 *cur_stat) 5873 { 5874 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5875 5876 /* device stats are not reset at PFR, they likely will not be zeroed 5877 * when the driver starts. Thus, save the value from the first read 5878 * without adding to the statistic value so that we report stats which 5879 * count up from zero. 5880 */ 5881 if (!prev_stat_loaded) { 5882 *prev_stat = new_data; 5883 return; 5884 } 5885 5886 /* Calculate the difference between the new and old values, and then 5887 * add it to the software stat value. 5888 */ 5889 if (new_data >= *prev_stat) 5890 *cur_stat += new_data - *prev_stat; 5891 else 5892 /* to manage the potential roll-over */ 5893 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5894 5895 /* Update the previously stored value to prepare for next read */ 5896 *prev_stat = new_data; 5897 } 5898 5899 /** 5900 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5901 * @hw: ptr to the hardware info 5902 * @reg: offset of HW register to read from 5903 * @prev_stat_loaded: bool to specify if previous stats are loaded 5904 * @prev_stat: ptr to previous loaded stat value 5905 * @cur_stat: ptr to current stat value 5906 */ 5907 void 5908 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5909 u64 *prev_stat, u64 *cur_stat) 5910 { 5911 u32 new_data; 5912 5913 new_data = rd32(hw, reg); 5914 5915 /* device stats are not reset at PFR, they likely will not be zeroed 5916 * when the driver starts. Thus, save the value from the first read 5917 * without adding to the statistic value so that we report stats which 5918 * count up from zero. 5919 */ 5920 if (!prev_stat_loaded) { 5921 *prev_stat = new_data; 5922 return; 5923 } 5924 5925 /* Calculate the difference between the new and old values, and then 5926 * add it to the software stat value. 5927 */ 5928 if (new_data >= *prev_stat) 5929 *cur_stat += new_data - *prev_stat; 5930 else 5931 /* to manage the potential roll-over */ 5932 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5933 5934 /* Update the previously stored value to prepare for next read */ 5935 *prev_stat = new_data; 5936 } 5937 5938 /** 5939 * ice_sched_query_elem - query element information from HW 5940 * @hw: pointer to the HW struct 5941 * @node_teid: node TEID to be queried 5942 * @buf: buffer to element information 5943 * 5944 * This function queries HW element information 5945 */ 5946 int 5947 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5948 struct ice_aqc_txsched_elem_data *buf) 5949 { 5950 u16 buf_size, num_elem_ret = 0; 5951 int status; 5952 5953 buf_size = sizeof(*buf); 5954 memset(buf, 0, buf_size); 5955 buf->node_teid = cpu_to_le32(node_teid); 5956 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5957 NULL); 5958 if (status || num_elem_ret != 1) 5959 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5960 return status; 5961 } 5962 5963 /** 5964 * ice_aq_read_i2c 5965 * @hw: pointer to the hw struct 5966 * @topo_addr: topology address for a device to communicate with 5967 * @bus_addr: 7-bit I2C bus address 5968 * @addr: I2C memory address (I2C offset) with up to 16 bits 5969 * @params: I2C parameters: bit [7] - Repeated start, 5970 * bits [6:5] data offset size, 5971 * bit [4] - I2C address type, 5972 * bits [3:0] - data size to read (0-16 bytes) 5973 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5974 * @cd: pointer to command details structure or NULL 5975 * 5976 * Read I2C (0x06E2) 5977 */ 5978 int 5979 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5980 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5981 struct ice_sq_cd *cd) 5982 { 5983 struct libie_aq_desc desc = { 0 }; 5984 struct ice_aqc_i2c *cmd; 5985 u8 data_size; 5986 int status; 5987 5988 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5989 cmd = libie_aq_raw(&desc); 5990 5991 if (!data) 5992 return -EINVAL; 5993 5994 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5995 5996 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5997 cmd->topo_addr = topo_addr; 5998 cmd->i2c_params = params; 5999 cmd->i2c_addr = addr; 6000 6001 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6002 if (!status) { 6003 struct ice_aqc_read_i2c_resp *resp; 6004 u8 i; 6005 6006 resp = libie_aq_raw(&desc); 6007 for (i = 0; i < data_size; i++) { 6008 *data = resp->i2c_data[i]; 6009 data++; 6010 } 6011 } 6012 6013 return status; 6014 } 6015 6016 /** 6017 * ice_aq_write_i2c 6018 * @hw: pointer to the hw struct 6019 * @topo_addr: topology address for a device to communicate with 6020 * @bus_addr: 7-bit I2C bus address 6021 * @addr: I2C memory address (I2C offset) with up to 16 bits 6022 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 6023 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 6024 * @cd: pointer to command details structure or NULL 6025 * 6026 * Write I2C (0x06E3) 6027 * 6028 * * Return: 6029 * * 0 - Successful write to the i2c device 6030 * * -EINVAL - Data size greater than 4 bytes 6031 * * -EIO - FW error 6032 */ 6033 int 6034 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6035 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6036 struct ice_sq_cd *cd) 6037 { 6038 struct libie_aq_desc desc = { 0 }; 6039 struct ice_aqc_i2c *cmd; 6040 u8 data_size; 6041 6042 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6043 cmd = libie_aq_raw(&desc); 6044 6045 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6046 6047 /* data_size limited to 4 */ 6048 if (data_size > 4) 6049 return -EINVAL; 6050 6051 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6052 cmd->topo_addr = topo_addr; 6053 cmd->i2c_params = params; 6054 cmd->i2c_addr = addr; 6055 6056 memcpy(cmd->i2c_data, data, data_size); 6057 6058 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6059 } 6060 6061 /** 6062 * ice_get_pca9575_handle - find and return the PCA9575 controller 6063 * @hw: pointer to the hw struct 6064 * @pca9575_handle: GPIO controller's handle 6065 * 6066 * Find and return the GPIO controller's handle in the netlist. 6067 * When found - the value will be cached in the hw structure and following calls 6068 * will return cached value. 6069 * 6070 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6071 */ 6072 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6073 { 6074 struct ice_aqc_get_link_topo *cmd; 6075 struct libie_aq_desc desc; 6076 int err; 6077 u8 idx; 6078 6079 /* If handle was read previously return cached value */ 6080 if (hw->io_expander_handle) { 6081 *pca9575_handle = hw->io_expander_handle; 6082 return 0; 6083 } 6084 6085 #define SW_PCA9575_SFP_TOPO_IDX 2 6086 #define SW_PCA9575_QSFP_TOPO_IDX 1 6087 6088 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6089 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6090 idx = SW_PCA9575_SFP_TOPO_IDX; 6091 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6092 idx = SW_PCA9575_QSFP_TOPO_IDX; 6093 else 6094 return -ENXIO; 6095 6096 /* If handle was not detected read it from the netlist */ 6097 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6098 cmd = libie_aq_raw(&desc); 6099 cmd->addr.topo_params.node_type_ctx = 6100 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6101 cmd->addr.topo_params.index = idx; 6102 6103 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6104 if (err) 6105 return -ENXIO; 6106 6107 /* Verify if we found the right IO expander type */ 6108 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6109 return -ENXIO; 6110 6111 /* If present save the handle and return it */ 6112 hw->io_expander_handle = 6113 le16_to_cpu(cmd->addr.handle); 6114 *pca9575_handle = hw->io_expander_handle; 6115 6116 return 0; 6117 } 6118 6119 /** 6120 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6121 * @hw: pointer to the hw struct 6122 * @offset: GPIO controller register offset 6123 * @data: pointer to data to be read from the GPIO controller 6124 * 6125 * Return: 0 on success, negative error code otherwise. 6126 */ 6127 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6128 { 6129 struct ice_aqc_link_topo_addr link_topo; 6130 __le16 addr; 6131 u16 handle; 6132 int err; 6133 6134 memset(&link_topo, 0, sizeof(link_topo)); 6135 6136 err = ice_get_pca9575_handle(hw, &handle); 6137 if (err) 6138 return err; 6139 6140 link_topo.handle = cpu_to_le16(handle); 6141 link_topo.topo_params.node_type_ctx = 6142 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6143 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6144 6145 addr = cpu_to_le16((u16)offset); 6146 6147 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6148 } 6149 6150 /** 6151 * ice_aq_set_gpio 6152 * @hw: pointer to the hw struct 6153 * @gpio_ctrl_handle: GPIO controller node handle 6154 * @pin_idx: IO Number of the GPIO that needs to be set 6155 * @value: SW provide IO value to set in the LSB 6156 * @cd: pointer to command details structure or NULL 6157 * 6158 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6159 */ 6160 int 6161 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6162 struct ice_sq_cd *cd) 6163 { 6164 struct libie_aq_desc desc; 6165 struct ice_aqc_gpio *cmd; 6166 6167 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6168 cmd = libie_aq_raw(&desc); 6169 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6170 cmd->gpio_num = pin_idx; 6171 cmd->gpio_val = value ? 1 : 0; 6172 6173 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6174 } 6175 6176 /** 6177 * ice_aq_get_gpio 6178 * @hw: pointer to the hw struct 6179 * @gpio_ctrl_handle: GPIO controller node handle 6180 * @pin_idx: IO Number of the GPIO that needs to be set 6181 * @value: IO value read 6182 * @cd: pointer to command details structure or NULL 6183 * 6184 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6185 * the topology 6186 */ 6187 int 6188 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6189 bool *value, struct ice_sq_cd *cd) 6190 { 6191 struct libie_aq_desc desc; 6192 struct ice_aqc_gpio *cmd; 6193 int status; 6194 6195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6196 cmd = libie_aq_raw(&desc); 6197 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6198 cmd->gpio_num = pin_idx; 6199 6200 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6201 if (status) 6202 return status; 6203 6204 *value = !!cmd->gpio_val; 6205 return 0; 6206 } 6207 6208 /** 6209 * ice_is_fw_api_min_ver 6210 * @hw: pointer to the hardware structure 6211 * @maj: major version 6212 * @min: minor version 6213 * @patch: patch version 6214 * 6215 * Checks if the firmware API is minimum version 6216 */ 6217 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6218 { 6219 if (hw->api_maj_ver == maj) { 6220 if (hw->api_min_ver > min) 6221 return true; 6222 if (hw->api_min_ver == min && hw->api_patch >= patch) 6223 return true; 6224 } else if (hw->api_maj_ver > maj) { 6225 return true; 6226 } 6227 6228 return false; 6229 } 6230 6231 /** 6232 * ice_fw_supports_link_override 6233 * @hw: pointer to the hardware structure 6234 * 6235 * Checks if the firmware supports link override 6236 */ 6237 bool ice_fw_supports_link_override(struct ice_hw *hw) 6238 { 6239 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6240 ICE_FW_API_LINK_OVERRIDE_MIN, 6241 ICE_FW_API_LINK_OVERRIDE_PATCH); 6242 } 6243 6244 /** 6245 * ice_get_link_default_override 6246 * @ldo: pointer to the link default override struct 6247 * @pi: pointer to the port info struct 6248 * 6249 * Gets the link default override for a port 6250 */ 6251 int 6252 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6253 struct ice_port_info *pi) 6254 { 6255 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6256 struct ice_hw *hw = pi->hw; 6257 int status; 6258 6259 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6260 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6261 if (status) { 6262 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6263 return status; 6264 } 6265 6266 /* Each port has its own config; calculate for our port */ 6267 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6268 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6269 6270 /* link options first */ 6271 status = ice_read_sr_word(hw, tlv_start, &buf); 6272 if (status) { 6273 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6274 return status; 6275 } 6276 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6277 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6278 ICE_LINK_OVERRIDE_PHY_CFG_S; 6279 6280 /* link PHY config */ 6281 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6282 status = ice_read_sr_word(hw, offset, &buf); 6283 if (status) { 6284 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6285 return status; 6286 } 6287 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6288 6289 /* PHY types low */ 6290 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6291 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6292 status = ice_read_sr_word(hw, (offset + i), &buf); 6293 if (status) { 6294 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6295 return status; 6296 } 6297 /* shift 16 bits at a time to fill 64 bits */ 6298 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6299 } 6300 6301 /* PHY types high */ 6302 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6303 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6304 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6305 status = ice_read_sr_word(hw, (offset + i), &buf); 6306 if (status) { 6307 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6308 return status; 6309 } 6310 /* shift 16 bits at a time to fill 64 bits */ 6311 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6312 } 6313 6314 return status; 6315 } 6316 6317 /** 6318 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6319 * @caps: get PHY capability data 6320 */ 6321 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6322 { 6323 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6324 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6325 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6326 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6327 return true; 6328 6329 return false; 6330 } 6331 6332 /** 6333 * ice_is_fw_health_report_supported - checks if firmware supports health events 6334 * @hw: pointer to the hardware structure 6335 * 6336 * Return: true if firmware supports health status reports, 6337 * false otherwise 6338 */ 6339 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6340 { 6341 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6342 ICE_FW_API_HEALTH_REPORT_MIN, 6343 ICE_FW_API_HEALTH_REPORT_PATCH); 6344 } 6345 6346 /** 6347 * ice_aq_set_health_status_cfg - Configure FW health events 6348 * @hw: pointer to the HW struct 6349 * @event_source: type of diagnostic events to enable 6350 * 6351 * Configure the health status event types that the firmware will send to this 6352 * PF. The supported event types are: PF-specific, all PFs, and global. 6353 * 6354 * Return: 0 on success, negative error code otherwise. 6355 */ 6356 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6357 { 6358 struct ice_aqc_set_health_status_cfg *cmd; 6359 struct libie_aq_desc desc; 6360 6361 cmd = libie_aq_raw(&desc); 6362 6363 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6364 6365 cmd->event_source = event_source; 6366 6367 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6368 } 6369 6370 /** 6371 * ice_aq_set_lldp_mib - Set the LLDP MIB 6372 * @hw: pointer to the HW struct 6373 * @mib_type: Local, Remote or both Local and Remote MIBs 6374 * @buf: pointer to the caller-supplied buffer to store the MIB block 6375 * @buf_size: size of the buffer (in bytes) 6376 * @cd: pointer to command details structure or NULL 6377 * 6378 * Set the LLDP MIB. (0x0A08) 6379 */ 6380 int 6381 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6382 struct ice_sq_cd *cd) 6383 { 6384 struct ice_aqc_lldp_set_local_mib *cmd; 6385 struct libie_aq_desc desc; 6386 6387 cmd = libie_aq_raw(&desc); 6388 6389 if (buf_size == 0 || !buf) 6390 return -EINVAL; 6391 6392 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6393 6394 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6395 desc.datalen = cpu_to_le16(buf_size); 6396 6397 cmd->type = mib_type; 6398 cmd->length = cpu_to_le16(buf_size); 6399 6400 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6401 } 6402 6403 /** 6404 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6405 * @hw: pointer to HW struct 6406 */ 6407 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6408 { 6409 if (hw->mac_type != ICE_MAC_E810) 6410 return false; 6411 6412 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6413 ICE_FW_API_LLDP_FLTR_MIN, 6414 ICE_FW_API_LLDP_FLTR_PATCH); 6415 } 6416 6417 /** 6418 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6419 * @hw: pointer to HW struct 6420 * @vsi: VSI to add the filter to 6421 * @add: boolean for if adding or removing a filter 6422 * 6423 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6424 * with this HW or VSI, otherwise an error corresponding to 6425 * the AQ transaction result. 6426 */ 6427 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6428 { 6429 struct ice_aqc_lldp_filter_ctrl *cmd; 6430 struct libie_aq_desc desc; 6431 6432 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6433 return -EOPNOTSUPP; 6434 6435 cmd = libie_aq_raw(&desc); 6436 6437 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6438 6439 if (add) 6440 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6441 else 6442 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6443 6444 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6445 6446 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6447 } 6448 6449 /** 6450 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6451 * @hw: pointer to HW struct 6452 */ 6453 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6454 { 6455 struct libie_aq_desc desc; 6456 6457 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6458 6459 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6460 } 6461 6462 /** 6463 * ice_fw_supports_report_dflt_cfg 6464 * @hw: pointer to the hardware structure 6465 * 6466 * Checks if the firmware supports report default configuration 6467 */ 6468 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6469 { 6470 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6471 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6472 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6473 } 6474 6475 /* each of the indexes into the following array match the speed of a return 6476 * value from the list of AQ returned speeds like the range: 6477 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6478 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6479 * array. The array is defined as 15 elements long because the link_speed 6480 * returned by the firmware is a 16 bit * value, but is indexed 6481 * by [fls(speed) - 1] 6482 */ 6483 static const u32 ice_aq_to_link_speed[] = { 6484 SPEED_10, /* BIT(0) */ 6485 SPEED_100, 6486 SPEED_1000, 6487 SPEED_2500, 6488 SPEED_5000, 6489 SPEED_10000, 6490 SPEED_20000, 6491 SPEED_25000, 6492 SPEED_40000, 6493 SPEED_50000, 6494 SPEED_100000, /* BIT(10) */ 6495 SPEED_200000, 6496 }; 6497 6498 /** 6499 * ice_get_link_speed - get integer speed from table 6500 * @index: array index from fls(aq speed) - 1 6501 * 6502 * Returns: u32 value containing integer speed 6503 */ 6504 u32 ice_get_link_speed(u16 index) 6505 { 6506 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6507 return 0; 6508 6509 return ice_aq_to_link_speed[index]; 6510 } 6511 6512 /** 6513 * ice_get_dest_cgu - get destination CGU dev for given HW 6514 * @hw: pointer to the HW struct 6515 * 6516 * Get CGU client id for CGU register read/write operations. 6517 * 6518 * Return: CGU device id to use in SBQ transactions. 6519 */ 6520 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6521 { 6522 /* On dual complex E825 only complex 0 has functional CGU powering all 6523 * the PHYs. 6524 * SBQ destination device cgu points to CGU on a current complex and to 6525 * access primary CGU from the secondary complex, the driver should use 6526 * cgu_peer as a destination device. 6527 */ 6528 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6529 !ice_is_primary(hw)) 6530 return ice_sbq_dev_cgu_peer; 6531 return ice_sbq_dev_cgu; 6532 } 6533 6534 /** 6535 * ice_read_cgu_reg - Read a CGU register 6536 * @hw: Pointer to the HW struct 6537 * @addr: Register address to read 6538 * @val: Storage for register value read 6539 * 6540 * Read the contents of a register of the Clock Generation Unit. Only 6541 * applicable to E82X devices. 6542 * 6543 * Return: 0 on success, other error codes when failed to read from CGU. 6544 */ 6545 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6546 { 6547 struct ice_sbq_msg_input cgu_msg = { 6548 .dest_dev = ice_get_dest_cgu(hw), 6549 .opcode = ice_sbq_msg_rd, 6550 .msg_addr_low = addr 6551 }; 6552 int err; 6553 6554 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6555 if (err) { 6556 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6557 addr, err); 6558 return err; 6559 } 6560 6561 *val = cgu_msg.data; 6562 6563 return 0; 6564 } 6565 6566 /** 6567 * ice_write_cgu_reg - Write a CGU register 6568 * @hw: Pointer to the HW struct 6569 * @addr: Register address to write 6570 * @val: Value to write into the register 6571 * 6572 * Write the specified value to a register of the Clock Generation Unit. Only 6573 * applicable to E82X devices. 6574 * 6575 * Return: 0 on success, other error codes when failed to write to CGU. 6576 */ 6577 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6578 { 6579 struct ice_sbq_msg_input cgu_msg = { 6580 .dest_dev = ice_get_dest_cgu(hw), 6581 .opcode = ice_sbq_msg_wr, 6582 .msg_addr_low = addr, 6583 .data = val 6584 }; 6585 int err; 6586 6587 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6588 if (err) 6589 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6590 addr, err); 6591 6592 return err; 6593 } 6594