1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212 static bool ice_is_pf_c827(struct ice_hw *hw) 213 { 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240 } 241 242 /** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 { 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256 } 257 258 /** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273 static int 274 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276 { 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314 } 315 316 /** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326 int 327 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330 { 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408 } 409 410 /** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422 static int 423 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425 { 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442 } 443 444 /** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453 int 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456 { 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473 } 474 475 /** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496 { 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520 } 521 522 /** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529 static bool ice_is_media_cage_present(struct ice_port_info *pi) 530 { 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538 } 539 540 /** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545 { 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655 } 656 657 /** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665 { 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673 } 674 675 /** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684 int 685 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687 { 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775 } 776 777 /** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785 static void 786 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788 { 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824 } 825 826 /** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834 int 835 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 { 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852 } 853 854 /** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859 { 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882 } 883 884 /** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889 { 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932 } 933 934 /** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942 { 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958 } 959 960 /** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967 static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968 { 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985 } 986 987 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 988 u16 size) 989 { 990 struct ice_hw *hw = priv; 991 992 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 993 } 994 995 static int __fwlog_init(struct ice_hw *hw) 996 { 997 struct ice_pf *pf = hw->back; 998 struct libie_fwlog_api api = { 999 .pdev = pf->pdev, 1000 .send_cmd = __fwlog_send_cmd, 1001 .priv = hw, 1002 }; 1003 int err; 1004 1005 /* only support fw log commands on PF 0 */ 1006 if (hw->bus.func) 1007 return -EINVAL; 1008 1009 err = ice_debugfs_pf_init(pf); 1010 if (err) 1011 return err; 1012 1013 api.debugfs_root = pf->ice_debugfs_pf; 1014 1015 return libie_fwlog_init(&hw->fwlog, &api); 1016 } 1017 1018 /** 1019 * ice_init_hw - main hardware initialization routine 1020 * @hw: pointer to the hardware structure 1021 */ 1022 int ice_init_hw(struct ice_hw *hw) 1023 { 1024 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1025 void *mac_buf __free(kfree) = NULL; 1026 u16 mac_buf_len; 1027 int status; 1028 1029 /* Set MAC type based on DeviceID */ 1030 status = ice_set_mac_type(hw); 1031 if (status) 1032 return status; 1033 1034 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1035 1036 status = ice_reset(hw, ICE_RESET_PFR); 1037 if (status) 1038 return status; 1039 1040 ice_get_itr_intrl_gran(hw); 1041 1042 status = ice_create_all_ctrlq(hw); 1043 if (status) 1044 goto err_unroll_cqinit; 1045 1046 status = __fwlog_init(hw); 1047 if (status) 1048 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1049 status); 1050 1051 status = ice_clear_pf_cfg(hw); 1052 if (status) 1053 goto err_unroll_cqinit; 1054 1055 /* Set bit to enable Flow Director filters */ 1056 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1057 INIT_LIST_HEAD(&hw->fdir_list_head); 1058 1059 ice_clear_pxe_mode(hw); 1060 1061 status = ice_init_nvm(hw); 1062 if (status) 1063 goto err_unroll_cqinit; 1064 1065 status = ice_get_caps(hw); 1066 if (status) 1067 goto err_unroll_cqinit; 1068 1069 if (!hw->port_info) 1070 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1071 sizeof(*hw->port_info), 1072 GFP_KERNEL); 1073 if (!hw->port_info) { 1074 status = -ENOMEM; 1075 goto err_unroll_cqinit; 1076 } 1077 1078 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1079 /* set the back pointer to HW */ 1080 hw->port_info->hw = hw; 1081 1082 /* Initialize port_info struct with switch configuration data */ 1083 status = ice_get_initial_sw_cfg(hw); 1084 if (status) 1085 goto err_unroll_alloc; 1086 1087 hw->evb_veb = true; 1088 1089 /* init xarray for identifying scheduling nodes uniquely */ 1090 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1091 1092 /* Query the allocated resources for Tx scheduler */ 1093 status = ice_sched_query_res_alloc(hw); 1094 if (status) { 1095 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1096 goto err_unroll_alloc; 1097 } 1098 ice_sched_get_psm_clk_freq(hw); 1099 1100 /* Initialize port_info struct with scheduler data */ 1101 status = ice_sched_init_port(hw->port_info); 1102 if (status) 1103 goto err_unroll_sched; 1104 1105 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1106 if (!pcaps) { 1107 status = -ENOMEM; 1108 goto err_unroll_sched; 1109 } 1110 1111 /* Initialize port_info struct with PHY capabilities */ 1112 status = ice_aq_get_phy_caps(hw->port_info, false, 1113 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1114 NULL); 1115 if (status) 1116 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1117 status); 1118 1119 /* Initialize port_info struct with link information */ 1120 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1121 if (status) 1122 goto err_unroll_sched; 1123 1124 /* need a valid SW entry point to build a Tx tree */ 1125 if (!hw->sw_entry_point_layer) { 1126 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1127 status = -EIO; 1128 goto err_unroll_sched; 1129 } 1130 INIT_LIST_HEAD(&hw->agg_list); 1131 /* Initialize max burst size */ 1132 if (!hw->max_burst_size) 1133 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1134 1135 status = ice_init_fltr_mgmt_struct(hw); 1136 if (status) 1137 goto err_unroll_sched; 1138 1139 /* Get MAC information */ 1140 /* A single port can report up to two (LAN and WoL) addresses */ 1141 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1142 GFP_KERNEL); 1143 if (!mac_buf) { 1144 status = -ENOMEM; 1145 goto err_unroll_fltr_mgmt_struct; 1146 } 1147 1148 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1149 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1150 1151 if (status) 1152 goto err_unroll_fltr_mgmt_struct; 1153 /* enable jumbo frame support at MAC level */ 1154 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1155 if (status) 1156 goto err_unroll_fltr_mgmt_struct; 1157 /* Obtain counter base index which would be used by flow director */ 1158 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1159 if (status) 1160 goto err_unroll_fltr_mgmt_struct; 1161 status = ice_init_hw_tbls(hw); 1162 if (status) 1163 goto err_unroll_fltr_mgmt_struct; 1164 mutex_init(&hw->tnl_lock); 1165 ice_init_chk_recipe_reuse_support(hw); 1166 1167 /* Some cards require longer initialization times 1168 * due to necessity of loading FW from an external source. 1169 * This can take even half a minute. 1170 */ 1171 if (ice_is_pf_c827(hw)) { 1172 status = ice_wait_for_fw(hw, 30000); 1173 if (status) { 1174 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1175 goto err_unroll_fltr_mgmt_struct; 1176 } 1177 } 1178 1179 hw->lane_num = ice_get_phy_lane_number(hw); 1180 1181 return 0; 1182 err_unroll_fltr_mgmt_struct: 1183 ice_cleanup_fltr_mgmt_struct(hw); 1184 err_unroll_sched: 1185 ice_sched_cleanup_all(hw); 1186 err_unroll_alloc: 1187 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1188 err_unroll_cqinit: 1189 ice_destroy_all_ctrlq(hw); 1190 return status; 1191 } 1192 1193 static void __fwlog_deinit(struct ice_hw *hw) 1194 { 1195 /* only support fw log commands on PF 0 */ 1196 if (hw->bus.func) 1197 return; 1198 1199 ice_debugfs_pf_deinit(hw->back); 1200 libie_fwlog_deinit(&hw->fwlog); 1201 } 1202 1203 /** 1204 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1205 * @hw: pointer to the hardware structure 1206 * 1207 * This should be called only during nominal operation, not as a result of 1208 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1209 * applicable initializations if it fails for any reason. 1210 */ 1211 void ice_deinit_hw(struct ice_hw *hw) 1212 { 1213 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1214 ice_cleanup_fltr_mgmt_struct(hw); 1215 1216 ice_sched_cleanup_all(hw); 1217 ice_sched_clear_agg(hw); 1218 ice_free_seg(hw); 1219 ice_free_hw_tbls(hw); 1220 mutex_destroy(&hw->tnl_lock); 1221 __fwlog_deinit(hw); 1222 ice_destroy_all_ctrlq(hw); 1223 1224 /* Clear VSI contexts if not already cleared */ 1225 ice_clear_all_vsi_ctx(hw); 1226 } 1227 1228 /** 1229 * ice_check_reset - Check to see if a global reset is complete 1230 * @hw: pointer to the hardware structure 1231 */ 1232 int ice_check_reset(struct ice_hw *hw) 1233 { 1234 u32 cnt, reg = 0, grst_timeout, uld_mask; 1235 1236 /* Poll for Device Active state in case a recent CORER, GLOBR, 1237 * or EMPR has occurred. The grst delay value is in 100ms units. 1238 * Add 1sec for outstanding AQ commands that can take a long time. 1239 */ 1240 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1241 rd32(hw, GLGEN_RSTCTL)) + 10; 1242 1243 for (cnt = 0; cnt < grst_timeout; cnt++) { 1244 mdelay(100); 1245 reg = rd32(hw, GLGEN_RSTAT); 1246 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1247 break; 1248 } 1249 1250 if (cnt == grst_timeout) { 1251 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1252 return -EIO; 1253 } 1254 1255 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1256 GLNVM_ULD_PCIER_DONE_1_M |\ 1257 GLNVM_ULD_CORER_DONE_M |\ 1258 GLNVM_ULD_GLOBR_DONE_M |\ 1259 GLNVM_ULD_POR_DONE_M |\ 1260 GLNVM_ULD_POR_DONE_1_M |\ 1261 GLNVM_ULD_PCIER_DONE_2_M) 1262 1263 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1264 GLNVM_ULD_PE_DONE_M : 0); 1265 1266 /* Device is Active; check Global Reset processes are done */ 1267 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1268 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1269 if (reg == uld_mask) { 1270 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1271 break; 1272 } 1273 mdelay(10); 1274 } 1275 1276 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1277 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1278 reg); 1279 return -EIO; 1280 } 1281 1282 return 0; 1283 } 1284 1285 /** 1286 * ice_pf_reset - Reset the PF 1287 * @hw: pointer to the hardware structure 1288 * 1289 * If a global reset has been triggered, this function checks 1290 * for its completion and then issues the PF reset 1291 */ 1292 static int ice_pf_reset(struct ice_hw *hw) 1293 { 1294 u32 cnt, reg; 1295 1296 /* If at function entry a global reset was already in progress, i.e. 1297 * state is not 'device active' or any of the reset done bits are not 1298 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1299 * global reset is done. 1300 */ 1301 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1302 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1303 /* poll on global reset currently in progress until done */ 1304 if (ice_check_reset(hw)) 1305 return -EIO; 1306 1307 return 0; 1308 } 1309 1310 /* Reset the PF */ 1311 reg = rd32(hw, PFGEN_CTRL); 1312 1313 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1314 1315 /* Wait for the PFR to complete. The wait time is the global config lock 1316 * timeout plus the PFR timeout which will account for a possible reset 1317 * that is occurring during a download package operation. 1318 */ 1319 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1320 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1321 reg = rd32(hw, PFGEN_CTRL); 1322 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1323 break; 1324 1325 mdelay(1); 1326 } 1327 1328 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1329 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1330 return -EIO; 1331 } 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * ice_reset - Perform different types of reset 1338 * @hw: pointer to the hardware structure 1339 * @req: reset request 1340 * 1341 * This function triggers a reset as specified by the req parameter. 1342 * 1343 * Note: 1344 * If anything other than a PF reset is triggered, PXE mode is restored. 1345 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1346 * interface has been restored in the rebuild flow. 1347 */ 1348 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1349 { 1350 u32 val = 0; 1351 1352 switch (req) { 1353 case ICE_RESET_PFR: 1354 return ice_pf_reset(hw); 1355 case ICE_RESET_CORER: 1356 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1357 val = GLGEN_RTRIG_CORER_M; 1358 break; 1359 case ICE_RESET_GLOBR: 1360 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1361 val = GLGEN_RTRIG_GLOBR_M; 1362 break; 1363 default: 1364 return -EINVAL; 1365 } 1366 1367 val |= rd32(hw, GLGEN_RTRIG); 1368 wr32(hw, GLGEN_RTRIG, val); 1369 ice_flush(hw); 1370 1371 /* wait for the FW to be ready */ 1372 return ice_check_reset(hw); 1373 } 1374 1375 /** 1376 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1377 * @hw: pointer to the hardware structure 1378 * @rxq_ctx: pointer to the packed Rx queue context 1379 * @rxq_index: the index of the Rx queue 1380 */ 1381 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1382 const ice_rxq_ctx_buf_t *rxq_ctx, 1383 u32 rxq_index) 1384 { 1385 /* Copy each dword separately to HW */ 1386 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1387 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1388 1389 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1390 1391 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1392 } 1393 } 1394 1395 /** 1396 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1397 * @hw: pointer to the hardware structure 1398 * @rxq_ctx: pointer to the packed Rx queue context 1399 * @rxq_index: the index of the Rx queue 1400 */ 1401 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1402 ice_rxq_ctx_buf_t *rxq_ctx, 1403 u32 rxq_index) 1404 { 1405 u32 *ctx = (u32 *)rxq_ctx; 1406 1407 /* Copy each dword separately from HW */ 1408 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1409 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1410 1411 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1412 } 1413 } 1414 1415 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1416 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1417 1418 /* LAN Rx Queue Context */ 1419 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1420 /* Field Width LSB */ 1421 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1422 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1423 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1424 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1425 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1426 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1427 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1428 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1429 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1430 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1431 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1432 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1433 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1434 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1435 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1436 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1437 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1438 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1439 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1440 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1441 }; 1442 1443 /** 1444 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1445 * @ctx: the Rx queue context to pack 1446 * @buf: the HW buffer to pack into 1447 * 1448 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1449 * bit-packed HW layout. 1450 */ 1451 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1452 ice_rxq_ctx_buf_t *buf) 1453 { 1454 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1455 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1456 } 1457 1458 /** 1459 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1460 * @buf: the HW buffer to unpack from 1461 * @ctx: the Rx queue context to unpack 1462 * 1463 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1464 * structure. 1465 */ 1466 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1467 struct ice_rlan_ctx *ctx) 1468 { 1469 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1470 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1471 } 1472 1473 /** 1474 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1475 * @hw: pointer to the hardware structure 1476 * @rlan_ctx: pointer to the unpacked Rx queue context 1477 * @rxq_index: the index of the Rx queue 1478 * 1479 * Pack the sparse Rx Queue context into dense hardware format and write it 1480 * into the HW register space. 1481 * 1482 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1483 */ 1484 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1485 u32 rxq_index) 1486 { 1487 ice_rxq_ctx_buf_t buf = {}; 1488 1489 if (rxq_index > QRX_CTRL_MAX_INDEX) 1490 return -EINVAL; 1491 1492 ice_pack_rxq_ctx(rlan_ctx, &buf); 1493 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1494 1495 return 0; 1496 } 1497 1498 /** 1499 * ice_read_rxq_ctx - Read Rx queue context from HW 1500 * @hw: pointer to the hardware structure 1501 * @rlan_ctx: pointer to the Rx queue context 1502 * @rxq_index: the index of the Rx queue 1503 * 1504 * Read the Rx queue context from the hardware registers, and unpack it into 1505 * the sparse Rx queue context structure. 1506 * 1507 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1508 */ 1509 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1510 u32 rxq_index) 1511 { 1512 ice_rxq_ctx_buf_t buf = {}; 1513 1514 if (rxq_index > QRX_CTRL_MAX_INDEX) 1515 return -EINVAL; 1516 1517 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1518 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1519 1520 return 0; 1521 } 1522 1523 /* LAN Tx Queue Context */ 1524 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1525 /* Field Width LSB */ 1526 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1527 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1528 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1529 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1530 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1531 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1532 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1533 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1534 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1535 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1536 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1537 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1538 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1539 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1540 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1541 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1542 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1543 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1544 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1545 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1546 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1547 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1548 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1549 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1550 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1551 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1552 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1553 }; 1554 1555 /** 1556 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1557 * @ctx: the Tx queue context to pack 1558 * @buf: the Admin Queue HW buffer to pack into 1559 * 1560 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1561 * bit-packed Admin Queue layout. 1562 */ 1563 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1564 { 1565 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1566 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1567 } 1568 1569 /** 1570 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1571 * @ctx: the Tx queue context to pack 1572 * @buf: the HW buffer to pack into 1573 * 1574 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1575 * bit-packed HW layout, including the internal data portion. 1576 */ 1577 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1578 ice_txq_ctx_buf_full_t *buf) 1579 { 1580 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1581 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1582 } 1583 1584 /** 1585 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1586 * @buf: the HW buffer to unpack from 1587 * @ctx: the Tx queue context to unpack 1588 * 1589 * Unpack the Tx queue context from the HW buffer (including the full internal 1590 * state) into the CPU-friendly structure. 1591 */ 1592 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1593 struct ice_tlan_ctx *ctx) 1594 { 1595 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1596 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1597 } 1598 1599 /** 1600 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1601 * @hw: pointer to the hardware structure 1602 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1603 * @txq_index: the index of the Tx queue 1604 * 1605 * Copy Tx Queue context from HW register space to dense structure 1606 */ 1607 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1608 ice_txq_ctx_buf_full_t *txq_ctx, 1609 u32 txq_index) 1610 { 1611 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1612 u32 *ctx = (u32 *)txq_ctx; 1613 u32 txq_base, reg; 1614 1615 /* Get Tx queue base within card space */ 1616 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1617 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1618 1619 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1620 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1621 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1622 txq_base + txq_index) | 1623 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1624 1625 /* Prevent other PFs on the same adapter from accessing the Tx queue 1626 * context interface concurrently. 1627 */ 1628 spin_lock(&pf->adapter->txq_ctx_lock); 1629 1630 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1631 ice_flush(hw); 1632 1633 /* Copy each dword separately from HW */ 1634 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1635 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1636 1637 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1638 } 1639 1640 spin_unlock(&pf->adapter->txq_ctx_lock); 1641 } 1642 1643 /** 1644 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1645 * @hw: pointer to the hardware structure 1646 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1647 * @txq_index: the index of the Tx queue 1648 */ 1649 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1650 const ice_txq_ctx_buf_full_t *txq_ctx, 1651 u32 txq_index) 1652 { 1653 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1654 u32 txq_base, reg; 1655 1656 /* Get Tx queue base within card space */ 1657 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1658 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1659 1660 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1661 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1662 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1663 txq_base + txq_index) | 1664 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1665 1666 /* Prevent other PFs on the same adapter from accessing the Tx queue 1667 * context interface concurrently. 1668 */ 1669 spin_lock(&pf->adapter->txq_ctx_lock); 1670 1671 /* Copy each dword separately to HW */ 1672 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1673 u32 ctx = ((const u32 *)txq_ctx)[i]; 1674 1675 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1676 1677 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1678 } 1679 1680 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1681 ice_flush(hw); 1682 1683 spin_unlock(&pf->adapter->txq_ctx_lock); 1684 } 1685 1686 /** 1687 * ice_read_txq_ctx - Read Tx queue context from HW 1688 * @hw: pointer to the hardware structure 1689 * @tlan_ctx: pointer to the Tx queue context 1690 * @txq_index: the index of the Tx queue 1691 * 1692 * Read the Tx queue context from the HW registers, then unpack it into the 1693 * ice_tlan_ctx structure for use. 1694 * 1695 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1696 */ 1697 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1698 u32 txq_index) 1699 { 1700 ice_txq_ctx_buf_full_t buf = {}; 1701 1702 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1703 return -EINVAL; 1704 1705 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1706 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1707 1708 return 0; 1709 } 1710 1711 /** 1712 * ice_write_txq_ctx - Write Tx queue context to HW 1713 * @hw: pointer to the hardware structure 1714 * @tlan_ctx: pointer to the Tx queue context 1715 * @txq_index: the index of the Tx queue 1716 * 1717 * Pack the Tx queue context into the dense HW layout, then write it into the 1718 * HW registers. 1719 * 1720 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1721 */ 1722 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1723 u32 txq_index) 1724 { 1725 ice_txq_ctx_buf_full_t buf = {}; 1726 1727 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1728 return -EINVAL; 1729 1730 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1731 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1732 1733 return 0; 1734 } 1735 1736 /* Tx time Queue Context */ 1737 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1738 /* Field Width LSB */ 1739 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1740 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1741 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1742 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1743 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1744 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1745 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1746 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1747 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1748 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1749 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1750 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1751 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1752 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1753 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1754 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1755 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1756 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1757 }; 1758 1759 /** 1760 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1761 * @ctx: the Tx time queue context to pack 1762 * @buf: the HW buffer to pack into 1763 * 1764 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1765 * its bit-packed HW layout. 1766 */ 1767 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1768 ice_txtime_ctx_buf_t *buf) 1769 { 1770 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1771 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1772 } 1773 1774 /* Sideband Queue command wrappers */ 1775 1776 /** 1777 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1778 * @hw: pointer to the HW struct 1779 * @desc: descriptor describing the command 1780 * @buf: buffer to use for indirect commands (NULL for direct commands) 1781 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1782 * @cd: pointer to command details structure 1783 */ 1784 static int 1785 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1786 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1787 { 1788 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1789 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1790 } 1791 1792 /** 1793 * ice_sbq_rw_reg - Fill Sideband Queue command 1794 * @hw: pointer to the HW struct 1795 * @in: message info to be filled in descriptor 1796 * @flags: control queue descriptor flags 1797 */ 1798 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1799 { 1800 struct ice_sbq_cmd_desc desc = {0}; 1801 struct ice_sbq_msg_req msg = {0}; 1802 u16 msg_len; 1803 int status; 1804 1805 msg_len = sizeof(msg); 1806 1807 msg.dest_dev = in->dest_dev; 1808 msg.opcode = in->opcode; 1809 msg.flags = ICE_SBQ_MSG_FLAGS; 1810 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1811 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1812 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1813 1814 if (in->opcode) 1815 msg.data = cpu_to_le32(in->data); 1816 else 1817 /* data read comes back in completion, so shorten the struct by 1818 * sizeof(msg.data) 1819 */ 1820 msg_len -= sizeof(msg.data); 1821 1822 desc.flags = cpu_to_le16(flags); 1823 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1824 desc.param0.cmd_len = cpu_to_le16(msg_len); 1825 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1826 if (!status && !in->opcode) 1827 in->data = le32_to_cpu 1828 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1829 return status; 1830 } 1831 1832 /* FW Admin Queue command wrappers */ 1833 1834 /* Software lock/mutex that is meant to be held while the Global Config Lock 1835 * in firmware is acquired by the software to prevent most (but not all) types 1836 * of AQ commands from being sent to FW 1837 */ 1838 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1839 1840 /** 1841 * ice_should_retry_sq_send_cmd 1842 * @opcode: AQ opcode 1843 * 1844 * Decide if we should retry the send command routine for the ATQ, depending 1845 * on the opcode. 1846 */ 1847 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1848 { 1849 switch (opcode) { 1850 case ice_aqc_opc_get_link_topo: 1851 case ice_aqc_opc_lldp_stop: 1852 case ice_aqc_opc_lldp_start: 1853 case ice_aqc_opc_lldp_filter_ctrl: 1854 return true; 1855 } 1856 1857 return false; 1858 } 1859 1860 /** 1861 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1862 * @hw: pointer to the HW struct 1863 * @cq: pointer to the specific Control queue 1864 * @desc: prefilled descriptor describing the command 1865 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1866 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1867 * @cd: pointer to command details structure 1868 * 1869 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1870 * Queue if the EBUSY AQ error is returned. 1871 */ 1872 static int 1873 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1874 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1875 struct ice_sq_cd *cd) 1876 { 1877 struct libie_aq_desc desc_cpy; 1878 bool is_cmd_for_retry; 1879 u8 idx = 0; 1880 u16 opcode; 1881 int status; 1882 1883 opcode = le16_to_cpu(desc->opcode); 1884 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1885 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1886 1887 if (is_cmd_for_retry) { 1888 /* All retryable cmds are direct, without buf. */ 1889 WARN_ON(buf); 1890 1891 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1892 } 1893 1894 do { 1895 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1896 1897 if (!is_cmd_for_retry || !status || 1898 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1899 break; 1900 1901 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1902 1903 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1904 1905 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1906 1907 return status; 1908 } 1909 1910 /** 1911 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1912 * @hw: pointer to the HW struct 1913 * @desc: descriptor describing the command 1914 * @buf: buffer to use for indirect commands (NULL for direct commands) 1915 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1916 * @cd: pointer to command details structure 1917 * 1918 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1919 */ 1920 int 1921 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1922 u16 buf_size, struct ice_sq_cd *cd) 1923 { 1924 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1925 bool lock_acquired = false; 1926 int status; 1927 1928 /* When a package download is in process (i.e. when the firmware's 1929 * Global Configuration Lock resource is held), only the Download 1930 * Package, Get Version, Get Package Info List, Upload Section, 1931 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1932 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1933 * Recipes to Profile Association, and Release Resource (with resource 1934 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1935 * must block until the package download completes and the Global Config 1936 * Lock is released. See also ice_acquire_global_cfg_lock(). 1937 */ 1938 switch (le16_to_cpu(desc->opcode)) { 1939 case ice_aqc_opc_download_pkg: 1940 case ice_aqc_opc_get_pkg_info_list: 1941 case ice_aqc_opc_get_ver: 1942 case ice_aqc_opc_upload_section: 1943 case ice_aqc_opc_update_pkg: 1944 case ice_aqc_opc_set_port_params: 1945 case ice_aqc_opc_get_vlan_mode_parameters: 1946 case ice_aqc_opc_set_vlan_mode_parameters: 1947 case ice_aqc_opc_set_tx_topo: 1948 case ice_aqc_opc_get_tx_topo: 1949 case ice_aqc_opc_add_recipe: 1950 case ice_aqc_opc_recipe_to_profile: 1951 case ice_aqc_opc_get_recipe: 1952 case ice_aqc_opc_get_recipe_to_profile: 1953 break; 1954 case ice_aqc_opc_release_res: 1955 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1956 break; 1957 fallthrough; 1958 default: 1959 mutex_lock(&ice_global_cfg_lock_sw); 1960 lock_acquired = true; 1961 break; 1962 } 1963 1964 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1965 if (lock_acquired) 1966 mutex_unlock(&ice_global_cfg_lock_sw); 1967 1968 return status; 1969 } 1970 1971 /** 1972 * ice_aq_get_fw_ver 1973 * @hw: pointer to the HW struct 1974 * @cd: pointer to command details structure or NULL 1975 * 1976 * Get the firmware version (0x0001) from the admin queue commands 1977 */ 1978 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1979 { 1980 struct libie_aqc_get_ver *resp; 1981 struct libie_aq_desc desc; 1982 int status; 1983 1984 resp = &desc.params.get_ver; 1985 1986 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1987 1988 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1989 1990 if (!status) { 1991 hw->fw_branch = resp->fw_branch; 1992 hw->fw_maj_ver = resp->fw_major; 1993 hw->fw_min_ver = resp->fw_minor; 1994 hw->fw_patch = resp->fw_patch; 1995 hw->fw_build = le32_to_cpu(resp->fw_build); 1996 hw->api_branch = resp->api_branch; 1997 hw->api_maj_ver = resp->api_major; 1998 hw->api_min_ver = resp->api_minor; 1999 hw->api_patch = resp->api_patch; 2000 } 2001 2002 return status; 2003 } 2004 2005 /** 2006 * ice_aq_send_driver_ver 2007 * @hw: pointer to the HW struct 2008 * @dv: driver's major, minor version 2009 * @cd: pointer to command details structure or NULL 2010 * 2011 * Send the driver version (0x0002) to the firmware 2012 */ 2013 int 2014 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 2015 struct ice_sq_cd *cd) 2016 { 2017 struct libie_aqc_driver_ver *cmd; 2018 struct libie_aq_desc desc; 2019 u16 len; 2020 2021 cmd = &desc.params.driver_ver; 2022 2023 if (!dv) 2024 return -EINVAL; 2025 2026 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 2027 2028 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2029 cmd->major_ver = dv->major_ver; 2030 cmd->minor_ver = dv->minor_ver; 2031 cmd->build_ver = dv->build_ver; 2032 cmd->subbuild_ver = dv->subbuild_ver; 2033 2034 len = 0; 2035 while (len < sizeof(dv->driver_string) && 2036 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2037 len++; 2038 2039 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2040 } 2041 2042 /** 2043 * ice_aq_q_shutdown 2044 * @hw: pointer to the HW struct 2045 * @unloading: is the driver unloading itself 2046 * 2047 * Tell the Firmware that we're shutting down the AdminQ and whether 2048 * or not the driver is unloading as well (0x0003). 2049 */ 2050 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2051 { 2052 struct ice_aqc_q_shutdown *cmd; 2053 struct libie_aq_desc desc; 2054 2055 cmd = libie_aq_raw(&desc); 2056 2057 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2058 2059 if (unloading) 2060 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2061 2062 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2063 } 2064 2065 /** 2066 * ice_aq_req_res 2067 * @hw: pointer to the HW struct 2068 * @res: resource ID 2069 * @access: access type 2070 * @sdp_number: resource number 2071 * @timeout: the maximum time in ms that the driver may hold the resource 2072 * @cd: pointer to command details structure or NULL 2073 * 2074 * Requests common resource using the admin queue commands (0x0008). 2075 * When attempting to acquire the Global Config Lock, the driver can 2076 * learn of three states: 2077 * 1) 0 - acquired lock, and can perform download package 2078 * 2) -EIO - did not get lock, driver should fail to load 2079 * 3) -EALREADY - did not get lock, but another driver has 2080 * successfully downloaded the package; the driver does 2081 * not have to download the package and can continue 2082 * loading 2083 * 2084 * Note that if the caller is in an acquire lock, perform action, release lock 2085 * phase of operation, it is possible that the FW may detect a timeout and issue 2086 * a CORER. In this case, the driver will receive a CORER interrupt and will 2087 * have to determine its cause. The calling thread that is handling this flow 2088 * will likely get an error propagated back to it indicating the Download 2089 * Package, Update Package or the Release Resource AQ commands timed out. 2090 */ 2091 static int 2092 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2093 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2094 struct ice_sq_cd *cd) 2095 { 2096 struct libie_aqc_req_res *cmd_resp; 2097 struct libie_aq_desc desc; 2098 int status; 2099 2100 cmd_resp = &desc.params.res_owner; 2101 2102 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2103 2104 cmd_resp->res_id = cpu_to_le16(res); 2105 cmd_resp->access_type = cpu_to_le16(access); 2106 cmd_resp->res_number = cpu_to_le32(sdp_number); 2107 cmd_resp->timeout = cpu_to_le32(*timeout); 2108 *timeout = 0; 2109 2110 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2111 2112 /* The completion specifies the maximum time in ms that the driver 2113 * may hold the resource in the Timeout field. 2114 */ 2115 2116 /* Global config lock response utilizes an additional status field. 2117 * 2118 * If the Global config lock resource is held by some other driver, the 2119 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2120 * and the timeout field indicates the maximum time the current owner 2121 * of the resource has to free it. 2122 */ 2123 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2124 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2125 *timeout = le32_to_cpu(cmd_resp->timeout); 2126 return 0; 2127 } else if (le16_to_cpu(cmd_resp->status) == 2128 LIBIE_AQ_RES_GLBL_IN_PROG) { 2129 *timeout = le32_to_cpu(cmd_resp->timeout); 2130 return -EIO; 2131 } else if (le16_to_cpu(cmd_resp->status) == 2132 LIBIE_AQ_RES_GLBL_DONE) { 2133 return -EALREADY; 2134 } 2135 2136 /* invalid FW response, force a timeout immediately */ 2137 *timeout = 0; 2138 return -EIO; 2139 } 2140 2141 /* If the resource is held by some other driver, the command completes 2142 * with a busy return value and the timeout field indicates the maximum 2143 * time the current owner of the resource has to free it. 2144 */ 2145 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2146 *timeout = le32_to_cpu(cmd_resp->timeout); 2147 2148 return status; 2149 } 2150 2151 /** 2152 * ice_aq_release_res 2153 * @hw: pointer to the HW struct 2154 * @res: resource ID 2155 * @sdp_number: resource number 2156 * @cd: pointer to command details structure or NULL 2157 * 2158 * release common resource using the admin queue commands (0x0009) 2159 */ 2160 static int 2161 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2162 struct ice_sq_cd *cd) 2163 { 2164 struct libie_aqc_req_res *cmd; 2165 struct libie_aq_desc desc; 2166 2167 cmd = &desc.params.res_owner; 2168 2169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2170 2171 cmd->res_id = cpu_to_le16(res); 2172 cmd->res_number = cpu_to_le32(sdp_number); 2173 2174 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2175 } 2176 2177 /** 2178 * ice_acquire_res 2179 * @hw: pointer to the HW structure 2180 * @res: resource ID 2181 * @access: access type (read or write) 2182 * @timeout: timeout in milliseconds 2183 * 2184 * This function will attempt to acquire the ownership of a resource. 2185 */ 2186 int 2187 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2188 enum ice_aq_res_access_type access, u32 timeout) 2189 { 2190 #define ICE_RES_POLLING_DELAY_MS 10 2191 u32 delay = ICE_RES_POLLING_DELAY_MS; 2192 u32 time_left = timeout; 2193 int status; 2194 2195 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2196 2197 /* A return code of -EALREADY means that another driver has 2198 * previously acquired the resource and performed any necessary updates; 2199 * in this case the caller does not obtain the resource and has no 2200 * further work to do. 2201 */ 2202 if (status == -EALREADY) 2203 goto ice_acquire_res_exit; 2204 2205 if (status) 2206 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2207 2208 /* If necessary, poll until the current lock owner timeouts */ 2209 timeout = time_left; 2210 while (status && timeout && time_left) { 2211 mdelay(delay); 2212 timeout = (timeout > delay) ? timeout - delay : 0; 2213 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2214 2215 if (status == -EALREADY) 2216 /* lock free, but no work to do */ 2217 break; 2218 2219 if (!status) 2220 /* lock acquired */ 2221 break; 2222 } 2223 if (status && status != -EALREADY) 2224 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2225 2226 ice_acquire_res_exit: 2227 if (status == -EALREADY) { 2228 if (access == ICE_RES_WRITE) 2229 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2230 else 2231 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2232 } 2233 return status; 2234 } 2235 2236 /** 2237 * ice_release_res 2238 * @hw: pointer to the HW structure 2239 * @res: resource ID 2240 * 2241 * This function will release a resource using the proper Admin Command. 2242 */ 2243 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2244 { 2245 unsigned long timeout; 2246 int status; 2247 2248 /* there are some rare cases when trying to release the resource 2249 * results in an admin queue timeout, so handle them correctly 2250 */ 2251 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; 2252 do { 2253 status = ice_aq_release_res(hw, res, 0, NULL); 2254 if (status != -EIO) 2255 break; 2256 usleep_range(1000, 2000); 2257 } while (time_before(jiffies, timeout)); 2258 } 2259 2260 /** 2261 * ice_aq_alloc_free_res - command to allocate/free resources 2262 * @hw: pointer to the HW struct 2263 * @buf: Indirect buffer to hold data parameters and response 2264 * @buf_size: size of buffer for indirect commands 2265 * @opc: pass in the command opcode 2266 * 2267 * Helper function to allocate/free resources using the admin queue commands 2268 */ 2269 int ice_aq_alloc_free_res(struct ice_hw *hw, 2270 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2271 enum ice_adminq_opc opc) 2272 { 2273 struct ice_aqc_alloc_free_res_cmd *cmd; 2274 struct libie_aq_desc desc; 2275 2276 cmd = libie_aq_raw(&desc); 2277 2278 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2279 return -EINVAL; 2280 2281 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2282 2283 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2284 2285 cmd->num_entries = cpu_to_le16(1); 2286 2287 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2288 } 2289 2290 /** 2291 * ice_alloc_hw_res - allocate resource 2292 * @hw: pointer to the HW struct 2293 * @type: type of resource 2294 * @num: number of resources to allocate 2295 * @btm: allocate from bottom 2296 * @res: pointer to array that will receive the resources 2297 */ 2298 int 2299 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2300 { 2301 struct ice_aqc_alloc_free_res_elem *buf; 2302 u16 buf_len; 2303 int status; 2304 2305 buf_len = struct_size(buf, elem, num); 2306 buf = kzalloc(buf_len, GFP_KERNEL); 2307 if (!buf) 2308 return -ENOMEM; 2309 2310 /* Prepare buffer to allocate resource. */ 2311 buf->num_elems = cpu_to_le16(num); 2312 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2313 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2314 if (btm) 2315 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2316 2317 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2318 if (status) 2319 goto ice_alloc_res_exit; 2320 2321 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2322 2323 ice_alloc_res_exit: 2324 kfree(buf); 2325 return status; 2326 } 2327 2328 /** 2329 * ice_free_hw_res - free allocated HW resource 2330 * @hw: pointer to the HW struct 2331 * @type: type of resource to free 2332 * @num: number of resources 2333 * @res: pointer to array that contains the resources to free 2334 */ 2335 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2336 { 2337 struct ice_aqc_alloc_free_res_elem *buf; 2338 u16 buf_len; 2339 int status; 2340 2341 buf_len = struct_size(buf, elem, num); 2342 buf = kzalloc(buf_len, GFP_KERNEL); 2343 if (!buf) 2344 return -ENOMEM; 2345 2346 /* Prepare buffer to free resource. */ 2347 buf->num_elems = cpu_to_le16(num); 2348 buf->res_type = cpu_to_le16(type); 2349 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2350 2351 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2352 if (status) 2353 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2354 2355 kfree(buf); 2356 return status; 2357 } 2358 2359 /** 2360 * ice_get_num_per_func - determine number of resources per PF 2361 * @hw: pointer to the HW structure 2362 * @max: value to be evenly split between each PF 2363 * 2364 * Determine the number of valid functions by going through the bitmap returned 2365 * from parsing capabilities and use this to calculate the number of resources 2366 * per PF based on the max value passed in. 2367 */ 2368 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2369 { 2370 u8 funcs; 2371 2372 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2373 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2374 ICE_CAPS_VALID_FUNCS_M); 2375 2376 if (!funcs) 2377 return 0; 2378 2379 return max / funcs; 2380 } 2381 2382 /** 2383 * ice_parse_common_caps - parse common device/function capabilities 2384 * @hw: pointer to the HW struct 2385 * @caps: pointer to common capabilities structure 2386 * @elem: the capability element to parse 2387 * @prefix: message prefix for tracing capabilities 2388 * 2389 * Given a capability element, extract relevant details into the common 2390 * capability structure. 2391 * 2392 * Returns: true if the capability matches one of the common capability ids, 2393 * false otherwise. 2394 */ 2395 static bool 2396 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2397 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2398 { 2399 u32 logical_id = le32_to_cpu(elem->logical_id); 2400 u32 phys_id = le32_to_cpu(elem->phys_id); 2401 u32 number = le32_to_cpu(elem->number); 2402 u16 cap = le16_to_cpu(elem->cap); 2403 bool found = true; 2404 2405 switch (cap) { 2406 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2407 caps->valid_functions = number; 2408 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2409 caps->valid_functions); 2410 break; 2411 case LIBIE_AQC_CAPS_SRIOV: 2412 caps->sr_iov_1_1 = (number == 1); 2413 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2414 caps->sr_iov_1_1); 2415 break; 2416 case LIBIE_AQC_CAPS_DCB: 2417 caps->dcb = (number == 1); 2418 caps->active_tc_bitmap = logical_id; 2419 caps->maxtc = phys_id; 2420 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2421 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2422 caps->active_tc_bitmap); 2423 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2424 break; 2425 case LIBIE_AQC_CAPS_RSS: 2426 caps->rss_table_size = number; 2427 caps->rss_table_entry_width = logical_id; 2428 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2429 caps->rss_table_size); 2430 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2431 caps->rss_table_entry_width); 2432 break; 2433 case LIBIE_AQC_CAPS_RXQS: 2434 caps->num_rxq = number; 2435 caps->rxq_first_id = phys_id; 2436 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2437 caps->num_rxq); 2438 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2439 caps->rxq_first_id); 2440 break; 2441 case LIBIE_AQC_CAPS_TXQS: 2442 caps->num_txq = number; 2443 caps->txq_first_id = phys_id; 2444 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2445 caps->num_txq); 2446 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2447 caps->txq_first_id); 2448 break; 2449 case LIBIE_AQC_CAPS_MSIX: 2450 caps->num_msix_vectors = number; 2451 caps->msix_vector_first_id = phys_id; 2452 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2453 caps->num_msix_vectors); 2454 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2455 caps->msix_vector_first_id); 2456 break; 2457 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2458 caps->nvm_update_pending_nvm = true; 2459 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2460 break; 2461 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2462 caps->nvm_update_pending_orom = true; 2463 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2464 break; 2465 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2466 caps->nvm_update_pending_netlist = true; 2467 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2468 break; 2469 case LIBIE_AQC_CAPS_NVM_MGMT: 2470 caps->nvm_unified_update = 2471 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2472 true : false; 2473 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2474 caps->nvm_unified_update); 2475 break; 2476 case LIBIE_AQC_CAPS_RDMA: 2477 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2478 caps->rdma = (number == 1); 2479 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2480 break; 2481 case LIBIE_AQC_CAPS_MAX_MTU: 2482 caps->max_mtu = number; 2483 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2484 prefix, caps->max_mtu); 2485 break; 2486 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2487 caps->pcie_reset_avoidance = (number > 0); 2488 ice_debug(hw, ICE_DBG_INIT, 2489 "%s: pcie_reset_avoidance = %d\n", prefix, 2490 caps->pcie_reset_avoidance); 2491 break; 2492 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2493 caps->reset_restrict_support = (number == 1); 2494 ice_debug(hw, ICE_DBG_INIT, 2495 "%s: reset_restrict_support = %d\n", prefix, 2496 caps->reset_restrict_support); 2497 break; 2498 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2499 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2500 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2501 prefix, caps->roce_lag); 2502 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2503 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2504 prefix, caps->sriov_lag); 2505 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2506 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2507 prefix, caps->sriov_aa_lag); 2508 break; 2509 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2510 caps->tx_sched_topo_comp_mode_en = (number == 1); 2511 break; 2512 default: 2513 /* Not one of the recognized common capabilities */ 2514 found = false; 2515 } 2516 2517 return found; 2518 } 2519 2520 /** 2521 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2522 * @hw: pointer to the HW structure 2523 * @caps: pointer to capabilities structure to fix 2524 * 2525 * Re-calculate the capabilities that are dependent on the number of physical 2526 * ports; i.e. some features are not supported or function differently on 2527 * devices with more than 4 ports. 2528 */ 2529 static void 2530 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2531 { 2532 /* This assumes device capabilities are always scanned before function 2533 * capabilities during the initialization flow. 2534 */ 2535 if (hw->dev_caps.num_funcs > 4) { 2536 /* Max 4 TCs per port */ 2537 caps->maxtc = 4; 2538 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2539 caps->maxtc); 2540 if (caps->rdma) { 2541 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2542 caps->rdma = 0; 2543 } 2544 2545 /* print message only when processing device capabilities 2546 * during initialization. 2547 */ 2548 if (caps == &hw->dev_caps.common_cap) 2549 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2550 } 2551 } 2552 2553 /** 2554 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2555 * @hw: pointer to the HW struct 2556 * @func_p: pointer to function capabilities structure 2557 * @cap: pointer to the capability element to parse 2558 * 2559 * Extract function capabilities for ICE_AQC_CAPS_VF. 2560 */ 2561 static void 2562 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2563 struct libie_aqc_list_caps_elem *cap) 2564 { 2565 u32 logical_id = le32_to_cpu(cap->logical_id); 2566 u32 number = le32_to_cpu(cap->number); 2567 2568 func_p->num_allocd_vfs = number; 2569 func_p->vf_base_id = logical_id; 2570 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2571 func_p->num_allocd_vfs); 2572 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2573 func_p->vf_base_id); 2574 } 2575 2576 /** 2577 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2578 * @hw: pointer to the HW struct 2579 * @func_p: pointer to function capabilities structure 2580 * @cap: pointer to the capability element to parse 2581 * 2582 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2583 */ 2584 static void 2585 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2586 struct libie_aqc_list_caps_elem *cap) 2587 { 2588 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2589 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2590 le32_to_cpu(cap->number)); 2591 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2592 func_p->guar_num_vsi); 2593 } 2594 2595 /** 2596 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2597 * @hw: pointer to the HW struct 2598 * @func_p: pointer to function capabilities structure 2599 * @cap: pointer to the capability element to parse 2600 * 2601 * Extract function capabilities for ICE_AQC_CAPS_1588. 2602 */ 2603 static void 2604 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2605 struct libie_aqc_list_caps_elem *cap) 2606 { 2607 struct ice_ts_func_info *info = &func_p->ts_func_info; 2608 u32 number = le32_to_cpu(cap->number); 2609 2610 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2611 func_p->common_cap.ieee_1588 = info->ena; 2612 2613 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2614 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2615 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2616 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2617 2618 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2619 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2620 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2621 } else { 2622 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2623 info->clk_src = ICE_CLK_SRC_TIME_REF; 2624 } 2625 2626 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2627 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2628 } else { 2629 /* Unknown clock frequency, so assume a (probably incorrect) 2630 * default to avoid out-of-bounds look ups of frequency 2631 * related information. 2632 */ 2633 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2634 info->clk_freq); 2635 info->time_ref = ICE_TSPLL_FREQ_25_000; 2636 } 2637 2638 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2639 func_p->common_cap.ieee_1588); 2640 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2641 info->src_tmr_owned); 2642 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2643 info->tmr_ena); 2644 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2645 info->tmr_index_owned); 2646 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2647 info->tmr_index_assoc); 2648 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2649 info->clk_freq); 2650 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2651 info->clk_src); 2652 } 2653 2654 /** 2655 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2656 * @hw: pointer to the HW struct 2657 * @func_p: pointer to function capabilities structure 2658 * 2659 * Extract function capabilities for ICE_AQC_CAPS_FD. 2660 */ 2661 static void 2662 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2663 { 2664 u32 reg_val, gsize, bsize; 2665 2666 reg_val = rd32(hw, GLQF_FD_SIZE); 2667 switch (hw->mac_type) { 2668 case ICE_MAC_E830: 2669 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2670 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2671 break; 2672 case ICE_MAC_E810: 2673 default: 2674 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2675 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2676 } 2677 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2678 func_p->fd_fltr_best_effort = bsize; 2679 2680 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2681 func_p->fd_fltr_guar); 2682 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2683 func_p->fd_fltr_best_effort); 2684 } 2685 2686 /** 2687 * ice_parse_func_caps - Parse function capabilities 2688 * @hw: pointer to the HW struct 2689 * @func_p: pointer to function capabilities structure 2690 * @buf: buffer containing the function capability records 2691 * @cap_count: the number of capabilities 2692 * 2693 * Helper function to parse function (0x000A) capabilities list. For 2694 * capabilities shared between device and function, this relies on 2695 * ice_parse_common_caps. 2696 * 2697 * Loop through the list of provided capabilities and extract the relevant 2698 * data into the function capabilities structured. 2699 */ 2700 static void 2701 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2702 void *buf, u32 cap_count) 2703 { 2704 struct libie_aqc_list_caps_elem *cap_resp; 2705 u32 i; 2706 2707 cap_resp = buf; 2708 2709 memset(func_p, 0, sizeof(*func_p)); 2710 2711 for (i = 0; i < cap_count; i++) { 2712 u16 cap = le16_to_cpu(cap_resp[i].cap); 2713 bool found; 2714 2715 found = ice_parse_common_caps(hw, &func_p->common_cap, 2716 &cap_resp[i], "func caps"); 2717 2718 switch (cap) { 2719 case LIBIE_AQC_CAPS_VF: 2720 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2721 break; 2722 case LIBIE_AQC_CAPS_VSI: 2723 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2724 break; 2725 case LIBIE_AQC_CAPS_1588: 2726 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2727 break; 2728 case LIBIE_AQC_CAPS_FD: 2729 ice_parse_fdir_func_caps(hw, func_p); 2730 break; 2731 default: 2732 /* Don't list common capabilities as unknown */ 2733 if (!found) 2734 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2735 i, cap); 2736 break; 2737 } 2738 } 2739 2740 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2741 } 2742 2743 /** 2744 * ice_func_id_to_logical_id - map from function id to logical pf id 2745 * @active_function_bitmap: active function bitmap 2746 * @pf_id: function number of device 2747 * 2748 * Return: logical PF ID. 2749 */ 2750 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2751 { 2752 u8 logical_id = 0; 2753 u8 i; 2754 2755 for (i = 0; i < pf_id; i++) 2756 if (active_function_bitmap & BIT(i)) 2757 logical_id++; 2758 2759 return logical_id; 2760 } 2761 2762 /** 2763 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2764 * @hw: pointer to the HW struct 2765 * @dev_p: pointer to device capabilities structure 2766 * @cap: capability element to parse 2767 * 2768 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2769 */ 2770 static void 2771 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2772 struct libie_aqc_list_caps_elem *cap) 2773 { 2774 u32 number = le32_to_cpu(cap->number); 2775 2776 dev_p->num_funcs = hweight32(number); 2777 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2778 dev_p->num_funcs); 2779 2780 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2781 } 2782 2783 /** 2784 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2785 * @hw: pointer to the HW struct 2786 * @dev_p: pointer to device capabilities structure 2787 * @cap: capability element to parse 2788 * 2789 * Parse ICE_AQC_CAPS_VF for device capabilities. 2790 */ 2791 static void 2792 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2793 struct libie_aqc_list_caps_elem *cap) 2794 { 2795 u32 number = le32_to_cpu(cap->number); 2796 2797 dev_p->num_vfs_exposed = number; 2798 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2799 dev_p->num_vfs_exposed); 2800 } 2801 2802 /** 2803 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2804 * @hw: pointer to the HW struct 2805 * @dev_p: pointer to device capabilities structure 2806 * @cap: capability element to parse 2807 * 2808 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2809 */ 2810 static void 2811 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2812 struct libie_aqc_list_caps_elem *cap) 2813 { 2814 u32 number = le32_to_cpu(cap->number); 2815 2816 dev_p->num_vsi_allocd_to_host = number; 2817 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2818 dev_p->num_vsi_allocd_to_host); 2819 } 2820 2821 /** 2822 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2823 * @hw: pointer to the HW struct 2824 * @dev_p: pointer to device capabilities structure 2825 * @cap: capability element to parse 2826 * 2827 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2828 */ 2829 static void 2830 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2831 struct libie_aqc_list_caps_elem *cap) 2832 { 2833 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2834 u32 logical_id = le32_to_cpu(cap->logical_id); 2835 u32 phys_id = le32_to_cpu(cap->phys_id); 2836 u32 number = le32_to_cpu(cap->number); 2837 2838 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2839 dev_p->common_cap.ieee_1588 = info->ena; 2840 2841 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2842 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2843 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2844 2845 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2846 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2847 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2848 2849 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2850 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2851 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2852 2853 info->ena_ports = logical_id; 2854 info->tmr_own_map = phys_id; 2855 2856 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2857 dev_p->common_cap.ieee_1588); 2858 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2859 info->tmr0_owner); 2860 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2861 info->tmr0_owned); 2862 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2863 info->tmr0_ena); 2864 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2865 info->tmr1_owner); 2866 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2867 info->tmr1_owned); 2868 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2869 info->tmr1_ena); 2870 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2871 info->ts_ll_read); 2872 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2873 info->ts_ll_int_read); 2874 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2875 info->ll_phy_tmr_update); 2876 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2877 info->ena_ports); 2878 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2879 info->tmr_own_map); 2880 } 2881 2882 /** 2883 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2884 * @hw: pointer to the HW struct 2885 * @dev_p: pointer to device capabilities structure 2886 * @cap: capability element to parse 2887 * 2888 * Parse ICE_AQC_CAPS_FD for device capabilities. 2889 */ 2890 static void 2891 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2892 struct libie_aqc_list_caps_elem *cap) 2893 { 2894 u32 number = le32_to_cpu(cap->number); 2895 2896 dev_p->num_flow_director_fltr = number; 2897 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2898 dev_p->num_flow_director_fltr); 2899 } 2900 2901 /** 2902 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2903 * @hw: pointer to the HW struct 2904 * @dev_p: pointer to device capabilities structure 2905 * @cap: capability element to parse 2906 * 2907 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2908 * enabled sensors. 2909 */ 2910 static void 2911 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2912 struct libie_aqc_list_caps_elem *cap) 2913 { 2914 dev_p->supported_sensors = le32_to_cpu(cap->number); 2915 2916 ice_debug(hw, ICE_DBG_INIT, 2917 "dev caps: supported sensors (bitmap) = 0x%x\n", 2918 dev_p->supported_sensors); 2919 } 2920 2921 /** 2922 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2923 * @hw: pointer to the HW struct 2924 * @dev_p: pointer to device capabilities structure 2925 * @cap: capability element to parse 2926 * 2927 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2928 */ 2929 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2930 struct ice_hw_dev_caps *dev_p, 2931 struct libie_aqc_list_caps_elem *cap) 2932 { 2933 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2934 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2935 2936 dev_info(ice_hw_to_dev(hw), 2937 "PF is configured in %s mode with IP instance ID %d\n", 2938 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2939 "primary" : "secondary", dev_p->nac_topo.id); 2940 2941 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2942 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2943 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2944 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2945 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2946 dev_p->nac_topo.id); 2947 } 2948 2949 /** 2950 * ice_parse_dev_caps - Parse device capabilities 2951 * @hw: pointer to the HW struct 2952 * @dev_p: pointer to device capabilities structure 2953 * @buf: buffer containing the device capability records 2954 * @cap_count: the number of capabilities 2955 * 2956 * Helper device to parse device (0x000B) capabilities list. For 2957 * capabilities shared between device and function, this relies on 2958 * ice_parse_common_caps. 2959 * 2960 * Loop through the list of provided capabilities and extract the relevant 2961 * data into the device capabilities structured. 2962 */ 2963 static void 2964 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2965 void *buf, u32 cap_count) 2966 { 2967 struct libie_aqc_list_caps_elem *cap_resp; 2968 u32 i; 2969 2970 cap_resp = buf; 2971 2972 memset(dev_p, 0, sizeof(*dev_p)); 2973 2974 for (i = 0; i < cap_count; i++) { 2975 u16 cap = le16_to_cpu(cap_resp[i].cap); 2976 bool found; 2977 2978 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2979 &cap_resp[i], "dev caps"); 2980 2981 switch (cap) { 2982 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2983 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2984 break; 2985 case LIBIE_AQC_CAPS_VF: 2986 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2987 break; 2988 case LIBIE_AQC_CAPS_VSI: 2989 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2990 break; 2991 case LIBIE_AQC_CAPS_1588: 2992 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2993 break; 2994 case LIBIE_AQC_CAPS_FD: 2995 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2996 break; 2997 case LIBIE_AQC_CAPS_SENSOR_READING: 2998 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2999 break; 3000 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 3001 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 3002 break; 3003 default: 3004 /* Don't list common capabilities as unknown */ 3005 if (!found) 3006 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 3007 i, cap); 3008 break; 3009 } 3010 } 3011 3012 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 3013 } 3014 3015 /** 3016 * ice_is_phy_rclk_in_netlist 3017 * @hw: pointer to the hw struct 3018 * 3019 * Check if the PHY Recovered Clock device is present in the netlist 3020 */ 3021 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 3022 { 3023 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3024 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3025 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 3026 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3027 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3028 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3029 return false; 3030 3031 return true; 3032 } 3033 3034 /** 3035 * ice_is_clock_mux_in_netlist 3036 * @hw: pointer to the hw struct 3037 * 3038 * Check if the Clock Multiplexer device is present in the netlist 3039 */ 3040 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3041 { 3042 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3043 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3044 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3045 NULL)) 3046 return false; 3047 3048 return true; 3049 } 3050 3051 /** 3052 * ice_is_cgu_in_netlist - check for CGU presence 3053 * @hw: pointer to the hw struct 3054 * 3055 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3056 * Save the CGU part number in the hw structure for later use. 3057 * Return: 3058 * * true - cgu is present 3059 * * false - cgu is not present 3060 */ 3061 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3062 { 3063 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3064 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3065 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3066 NULL)) { 3067 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3068 return true; 3069 } else if (!ice_find_netlist_node(hw, 3070 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3071 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3072 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3073 NULL)) { 3074 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3075 return true; 3076 } 3077 3078 return false; 3079 } 3080 3081 /** 3082 * ice_is_gps_in_netlist 3083 * @hw: pointer to the hw struct 3084 * 3085 * Check if the GPS generic device is present in the netlist 3086 */ 3087 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3088 { 3089 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3090 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3091 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3092 return false; 3093 3094 return true; 3095 } 3096 3097 /** 3098 * ice_aq_list_caps - query function/device capabilities 3099 * @hw: pointer to the HW struct 3100 * @buf: a buffer to hold the capabilities 3101 * @buf_size: size of the buffer 3102 * @cap_count: if not NULL, set to the number of capabilities reported 3103 * @opc: capabilities type to discover, device or function 3104 * @cd: pointer to command details structure or NULL 3105 * 3106 * Get the function (0x000A) or device (0x000B) capabilities description from 3107 * firmware and store it in the buffer. 3108 * 3109 * If the cap_count pointer is not NULL, then it is set to the number of 3110 * capabilities firmware will report. Note that if the buffer size is too 3111 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3112 * cap_count will still be updated in this case. It is recommended that the 3113 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3114 * firmware could return) to avoid this. 3115 */ 3116 int 3117 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3118 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3119 { 3120 struct libie_aqc_list_caps *cmd; 3121 struct libie_aq_desc desc; 3122 int status; 3123 3124 cmd = &desc.params.get_cap; 3125 3126 if (opc != ice_aqc_opc_list_func_caps && 3127 opc != ice_aqc_opc_list_dev_caps) 3128 return -EINVAL; 3129 3130 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3131 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3132 3133 if (cap_count) 3134 *cap_count = le32_to_cpu(cmd->count); 3135 3136 return status; 3137 } 3138 3139 /** 3140 * ice_discover_dev_caps - Read and extract device capabilities 3141 * @hw: pointer to the hardware structure 3142 * @dev_caps: pointer to device capabilities structure 3143 * 3144 * Read the device capabilities and extract them into the dev_caps structure 3145 * for later use. 3146 */ 3147 int 3148 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3149 { 3150 u32 cap_count = 0; 3151 void *cbuf; 3152 int status; 3153 3154 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3155 if (!cbuf) 3156 return -ENOMEM; 3157 3158 /* Although the driver doesn't know the number of capabilities the 3159 * device will return, we can simply send a 4KB buffer, the maximum 3160 * possible size that firmware can return. 3161 */ 3162 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3163 3164 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3165 ice_aqc_opc_list_dev_caps, NULL); 3166 if (!status) 3167 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3168 kfree(cbuf); 3169 3170 return status; 3171 } 3172 3173 /** 3174 * ice_discover_func_caps - Read and extract function capabilities 3175 * @hw: pointer to the hardware structure 3176 * @func_caps: pointer to function capabilities structure 3177 * 3178 * Read the function capabilities and extract them into the func_caps structure 3179 * for later use. 3180 */ 3181 static int 3182 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3183 { 3184 u32 cap_count = 0; 3185 void *cbuf; 3186 int status; 3187 3188 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3189 if (!cbuf) 3190 return -ENOMEM; 3191 3192 /* Although the driver doesn't know the number of capabilities the 3193 * device will return, we can simply send a 4KB buffer, the maximum 3194 * possible size that firmware can return. 3195 */ 3196 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3197 3198 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3199 ice_aqc_opc_list_func_caps, NULL); 3200 if (!status) 3201 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3202 kfree(cbuf); 3203 3204 return status; 3205 } 3206 3207 /** 3208 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3209 * @hw: pointer to the hardware structure 3210 */ 3211 void ice_set_safe_mode_caps(struct ice_hw *hw) 3212 { 3213 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3214 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3215 struct ice_hw_common_caps cached_caps; 3216 u32 num_funcs; 3217 3218 /* cache some func_caps values that should be restored after memset */ 3219 cached_caps = func_caps->common_cap; 3220 3221 /* unset func capabilities */ 3222 memset(func_caps, 0, sizeof(*func_caps)); 3223 3224 #define ICE_RESTORE_FUNC_CAP(name) \ 3225 func_caps->common_cap.name = cached_caps.name 3226 3227 /* restore cached values */ 3228 ICE_RESTORE_FUNC_CAP(valid_functions); 3229 ICE_RESTORE_FUNC_CAP(txq_first_id); 3230 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3231 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3232 ICE_RESTORE_FUNC_CAP(max_mtu); 3233 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3234 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3235 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3236 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3237 3238 /* one Tx and one Rx queue in safe mode */ 3239 func_caps->common_cap.num_rxq = 1; 3240 func_caps->common_cap.num_txq = 1; 3241 3242 /* two MSIX vectors, one for traffic and one for misc causes */ 3243 func_caps->common_cap.num_msix_vectors = 2; 3244 func_caps->guar_num_vsi = 1; 3245 3246 /* cache some dev_caps values that should be restored after memset */ 3247 cached_caps = dev_caps->common_cap; 3248 num_funcs = dev_caps->num_funcs; 3249 3250 /* unset dev capabilities */ 3251 memset(dev_caps, 0, sizeof(*dev_caps)); 3252 3253 #define ICE_RESTORE_DEV_CAP(name) \ 3254 dev_caps->common_cap.name = cached_caps.name 3255 3256 /* restore cached values */ 3257 ICE_RESTORE_DEV_CAP(valid_functions); 3258 ICE_RESTORE_DEV_CAP(txq_first_id); 3259 ICE_RESTORE_DEV_CAP(rxq_first_id); 3260 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3261 ICE_RESTORE_DEV_CAP(max_mtu); 3262 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3263 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3264 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3265 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3266 dev_caps->num_funcs = num_funcs; 3267 3268 /* one Tx and one Rx queue per function in safe mode */ 3269 dev_caps->common_cap.num_rxq = num_funcs; 3270 dev_caps->common_cap.num_txq = num_funcs; 3271 3272 /* two MSIX vectors per function */ 3273 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3274 } 3275 3276 /** 3277 * ice_get_caps - get info about the HW 3278 * @hw: pointer to the hardware structure 3279 */ 3280 int ice_get_caps(struct ice_hw *hw) 3281 { 3282 int status; 3283 3284 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3285 if (status) 3286 return status; 3287 3288 return ice_discover_func_caps(hw, &hw->func_caps); 3289 } 3290 3291 /** 3292 * ice_aq_manage_mac_write - manage MAC address write command 3293 * @hw: pointer to the HW struct 3294 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3295 * @flags: flags to control write behavior 3296 * @cd: pointer to command details structure or NULL 3297 * 3298 * This function is used to write MAC address to the NVM (0x0108). 3299 */ 3300 int 3301 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3302 struct ice_sq_cd *cd) 3303 { 3304 struct ice_aqc_manage_mac_write *cmd; 3305 struct libie_aq_desc desc; 3306 3307 cmd = libie_aq_raw(&desc); 3308 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3309 3310 cmd->flags = flags; 3311 ether_addr_copy(cmd->mac_addr, mac_addr); 3312 3313 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3314 } 3315 3316 /** 3317 * ice_aq_clear_pxe_mode 3318 * @hw: pointer to the HW struct 3319 * 3320 * Tell the firmware that the driver is taking over from PXE (0x0110). 3321 */ 3322 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3323 { 3324 struct ice_aqc_clear_pxe *cmd; 3325 struct libie_aq_desc desc; 3326 3327 cmd = libie_aq_raw(&desc); 3328 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3329 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3330 3331 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3332 } 3333 3334 /** 3335 * ice_clear_pxe_mode - clear pxe operations mode 3336 * @hw: pointer to the HW struct 3337 * 3338 * Make sure all PXE mode settings are cleared, including things 3339 * like descriptor fetch/write-back mode. 3340 */ 3341 void ice_clear_pxe_mode(struct ice_hw *hw) 3342 { 3343 if (ice_check_sq_alive(hw, &hw->adminq)) 3344 ice_aq_clear_pxe_mode(hw); 3345 } 3346 3347 /** 3348 * ice_aq_set_port_params - set physical port parameters. 3349 * @pi: pointer to the port info struct 3350 * @double_vlan: if set double VLAN is enabled 3351 * @cd: pointer to command details structure or NULL 3352 * 3353 * Set Physical port parameters (0x0203) 3354 */ 3355 int 3356 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3357 struct ice_sq_cd *cd) 3358 3359 { 3360 struct ice_aqc_set_port_params *cmd; 3361 struct ice_hw *hw = pi->hw; 3362 struct libie_aq_desc desc; 3363 u16 cmd_flags = 0; 3364 3365 cmd = libie_aq_raw(&desc); 3366 3367 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3368 if (double_vlan) 3369 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3370 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3371 3372 cmd->local_fwd_mode = pi->local_fwd_mode | 3373 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3374 3375 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3376 } 3377 3378 /** 3379 * ice_is_100m_speed_supported 3380 * @hw: pointer to the HW struct 3381 * 3382 * returns true if 100M speeds are supported by the device, 3383 * false otherwise. 3384 */ 3385 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3386 { 3387 switch (hw->device_id) { 3388 case ICE_DEV_ID_E822C_SGMII: 3389 case ICE_DEV_ID_E822L_SGMII: 3390 case ICE_DEV_ID_E823L_1GBE: 3391 case ICE_DEV_ID_E823C_SGMII: 3392 return true; 3393 default: 3394 return false; 3395 } 3396 } 3397 3398 /** 3399 * ice_get_link_speed_based_on_phy_type - returns link speed 3400 * @phy_type_low: lower part of phy_type 3401 * @phy_type_high: higher part of phy_type 3402 * 3403 * This helper function will convert an entry in PHY type structure 3404 * [phy_type_low, phy_type_high] to its corresponding link speed. 3405 * Note: In the structure of [phy_type_low, phy_type_high], there should 3406 * be one bit set, as this function will convert one PHY type to its 3407 * speed. 3408 * 3409 * Return: 3410 * * PHY speed for recognized PHY type 3411 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3412 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3413 */ 3414 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3415 { 3416 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3417 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3418 3419 switch (phy_type_low) { 3420 case ICE_PHY_TYPE_LOW_100BASE_TX: 3421 case ICE_PHY_TYPE_LOW_100M_SGMII: 3422 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3423 break; 3424 case ICE_PHY_TYPE_LOW_1000BASE_T: 3425 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3426 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3427 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3428 case ICE_PHY_TYPE_LOW_1G_SGMII: 3429 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3430 break; 3431 case ICE_PHY_TYPE_LOW_2500BASE_T: 3432 case ICE_PHY_TYPE_LOW_2500BASE_X: 3433 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3434 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3435 break; 3436 case ICE_PHY_TYPE_LOW_5GBASE_T: 3437 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3438 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3439 break; 3440 case ICE_PHY_TYPE_LOW_10GBASE_T: 3441 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3442 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3443 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3444 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3445 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3446 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3447 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3448 break; 3449 case ICE_PHY_TYPE_LOW_25GBASE_T: 3450 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3451 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3452 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3453 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3454 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3455 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3456 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3457 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3458 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3459 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3460 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3461 break; 3462 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3463 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3464 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3465 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3466 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3467 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3468 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3469 break; 3470 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3471 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3472 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3473 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3474 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3475 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3476 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3477 case ICE_PHY_TYPE_LOW_50G_AUI2: 3478 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3479 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3480 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3481 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3482 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3483 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3484 case ICE_PHY_TYPE_LOW_50G_AUI1: 3485 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3486 break; 3487 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3488 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3489 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3490 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3491 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3492 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3493 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3494 case ICE_PHY_TYPE_LOW_100G_AUI4: 3495 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3496 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3497 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3498 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3499 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3500 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3501 break; 3502 default: 3503 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3504 break; 3505 } 3506 3507 switch (phy_type_high) { 3508 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3509 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3510 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3511 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3512 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3513 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3514 break; 3515 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3516 case ICE_PHY_TYPE_HIGH_200G_SR4: 3517 case ICE_PHY_TYPE_HIGH_200G_FR4: 3518 case ICE_PHY_TYPE_HIGH_200G_LR4: 3519 case ICE_PHY_TYPE_HIGH_200G_DR4: 3520 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3521 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3522 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3523 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3524 break; 3525 default: 3526 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3527 break; 3528 } 3529 3530 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3531 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3532 return ICE_AQ_LINK_SPEED_UNKNOWN; 3533 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3534 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3535 return ICE_AQ_LINK_SPEED_UNKNOWN; 3536 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3537 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3538 return speed_phy_type_low; 3539 else 3540 return speed_phy_type_high; 3541 } 3542 3543 /** 3544 * ice_update_phy_type 3545 * @phy_type_low: pointer to the lower part of phy_type 3546 * @phy_type_high: pointer to the higher part of phy_type 3547 * @link_speeds_bitmap: targeted link speeds bitmap 3548 * 3549 * Note: For the link_speeds_bitmap structure, you can check it at 3550 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3551 * link_speeds_bitmap include multiple speeds. 3552 * 3553 * Each entry in this [phy_type_low, phy_type_high] structure will 3554 * present a certain link speed. This helper function will turn on bits 3555 * in [phy_type_low, phy_type_high] structure based on the value of 3556 * link_speeds_bitmap input parameter. 3557 */ 3558 void 3559 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3560 u16 link_speeds_bitmap) 3561 { 3562 u64 pt_high; 3563 u64 pt_low; 3564 int index; 3565 u16 speed; 3566 3567 /* We first check with low part of phy_type */ 3568 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3569 pt_low = BIT_ULL(index); 3570 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3571 3572 if (link_speeds_bitmap & speed) 3573 *phy_type_low |= BIT_ULL(index); 3574 } 3575 3576 /* We then check with high part of phy_type */ 3577 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3578 pt_high = BIT_ULL(index); 3579 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3580 3581 if (link_speeds_bitmap & speed) 3582 *phy_type_high |= BIT_ULL(index); 3583 } 3584 } 3585 3586 /** 3587 * ice_aq_set_phy_cfg 3588 * @hw: pointer to the HW struct 3589 * @pi: port info structure of the interested logical port 3590 * @cfg: structure with PHY configuration data to be set 3591 * @cd: pointer to command details structure or NULL 3592 * 3593 * Set the various PHY configuration parameters supported on the Port. 3594 * One or more of the Set PHY config parameters may be ignored in an MFP 3595 * mode as the PF may not have the privilege to set some of the PHY Config 3596 * parameters. This status will be indicated by the command response (0x0601). 3597 */ 3598 int 3599 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3600 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3601 { 3602 struct ice_aqc_set_phy_cfg *cmd; 3603 struct libie_aq_desc desc; 3604 int status; 3605 3606 if (!cfg) 3607 return -EINVAL; 3608 3609 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3610 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3611 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3612 cfg->caps); 3613 3614 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3615 } 3616 3617 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3618 cmd = libie_aq_raw(&desc); 3619 cmd->lport_num = pi->lport; 3620 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3621 3622 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3623 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3624 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3625 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3626 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3627 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3628 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3629 cfg->low_power_ctrl_an); 3630 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3631 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3632 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3633 cfg->link_fec_opt); 3634 3635 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3636 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3637 status = 0; 3638 3639 if (!status) 3640 pi->phy.curr_user_phy_cfg = *cfg; 3641 3642 return status; 3643 } 3644 3645 /** 3646 * ice_update_link_info - update status of the HW network link 3647 * @pi: port info structure of the interested logical port 3648 */ 3649 int ice_update_link_info(struct ice_port_info *pi) 3650 { 3651 struct ice_link_status *li; 3652 int status; 3653 3654 if (!pi) 3655 return -EINVAL; 3656 3657 li = &pi->phy.link_info; 3658 3659 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3660 if (status) 3661 return status; 3662 3663 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3664 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3665 3666 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3667 if (!pcaps) 3668 return -ENOMEM; 3669 3670 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3671 pcaps, NULL); 3672 } 3673 3674 return status; 3675 } 3676 3677 /** 3678 * ice_aq_get_phy_equalization - function to read serdes equaliser 3679 * value from firmware using admin queue command. 3680 * @hw: pointer to the HW struct 3681 * @data_in: represents the serdes equalization parameter requested 3682 * @op_code: represents the serdes number and flag to represent tx or rx 3683 * @serdes_num: represents the serdes number 3684 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3685 * 3686 * Return: non-zero status on error and 0 on success. 3687 */ 3688 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3689 u8 serdes_num, int *output) 3690 { 3691 struct ice_aqc_dnl_call_command *cmd; 3692 struct ice_aqc_dnl_call buf = {}; 3693 struct libie_aq_desc desc; 3694 int err; 3695 3696 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3697 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3698 cpu_to_le16(op_code | (serdes_num & 0xF)); 3699 cmd = libie_aq_raw(&desc); 3700 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3701 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3702 LIBIE_AQ_FLAG_RD | 3703 LIBIE_AQ_FLAG_SI); 3704 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3705 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3706 3707 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3708 NULL); 3709 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3710 3711 return err; 3712 } 3713 3714 #define FEC_REG_PORT(port) { \ 3715 FEC_CORR_LOW_REG_PORT##port, \ 3716 FEC_CORR_HIGH_REG_PORT##port, \ 3717 FEC_UNCORR_LOW_REG_PORT##port, \ 3718 FEC_UNCORR_HIGH_REG_PORT##port, \ 3719 } 3720 3721 static const u32 fec_reg[][ICE_FEC_MAX] = { 3722 FEC_REG_PORT(0), 3723 FEC_REG_PORT(1), 3724 FEC_REG_PORT(2), 3725 FEC_REG_PORT(3) 3726 }; 3727 3728 /** 3729 * ice_aq_get_fec_stats - reads fec stats from phy 3730 * @hw: pointer to the HW struct 3731 * @pcs_quad: represents pcsquad of user input serdes 3732 * @pcs_port: represents the pcs port number part of above pcs quad 3733 * @fec_type: represents FEC stats type 3734 * @output: pointer to the caller-supplied buffer to return requested fec stats 3735 * 3736 * Return: non-zero status on error and 0 on success. 3737 */ 3738 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3739 enum ice_fec_stats_types fec_type, u32 *output) 3740 { 3741 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3742 struct ice_sbq_msg_input msg = {}; 3743 u32 receiver_id, reg_offset; 3744 int err; 3745 3746 if (pcs_port > 3) 3747 return -EINVAL; 3748 3749 reg_offset = fec_reg[pcs_port][fec_type]; 3750 3751 if (pcs_quad == 0) 3752 receiver_id = FEC_RECEIVER_ID_PCS0; 3753 else if (pcs_quad == 1) 3754 receiver_id = FEC_RECEIVER_ID_PCS1; 3755 else 3756 return -EINVAL; 3757 3758 msg.msg_addr_low = lower_16_bits(reg_offset); 3759 msg.msg_addr_high = receiver_id; 3760 msg.opcode = ice_sbq_msg_rd; 3761 msg.dest_dev = ice_sbq_dev_phy_0; 3762 3763 err = ice_sbq_rw_reg(hw, &msg, flag); 3764 if (err) 3765 return err; 3766 3767 *output = msg.data; 3768 return 0; 3769 } 3770 3771 /** 3772 * ice_cache_phy_user_req 3773 * @pi: port information structure 3774 * @cache_data: PHY logging data 3775 * @cache_mode: PHY logging mode 3776 * 3777 * Log the user request on (FC, FEC, SPEED) for later use. 3778 */ 3779 static void 3780 ice_cache_phy_user_req(struct ice_port_info *pi, 3781 struct ice_phy_cache_mode_data cache_data, 3782 enum ice_phy_cache_mode cache_mode) 3783 { 3784 if (!pi) 3785 return; 3786 3787 switch (cache_mode) { 3788 case ICE_FC_MODE: 3789 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3790 break; 3791 case ICE_SPEED_MODE: 3792 pi->phy.curr_user_speed_req = 3793 cache_data.data.curr_user_speed_req; 3794 break; 3795 case ICE_FEC_MODE: 3796 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3797 break; 3798 default: 3799 break; 3800 } 3801 } 3802 3803 /** 3804 * ice_caps_to_fc_mode 3805 * @caps: PHY capabilities 3806 * 3807 * Convert PHY FC capabilities to ice FC mode 3808 */ 3809 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3810 { 3811 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3812 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3813 return ICE_FC_FULL; 3814 3815 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3816 return ICE_FC_TX_PAUSE; 3817 3818 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3819 return ICE_FC_RX_PAUSE; 3820 3821 return ICE_FC_NONE; 3822 } 3823 3824 /** 3825 * ice_caps_to_fec_mode 3826 * @caps: PHY capabilities 3827 * @fec_options: Link FEC options 3828 * 3829 * Convert PHY FEC capabilities to ice FEC mode 3830 */ 3831 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3832 { 3833 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3834 return ICE_FEC_AUTO; 3835 3836 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3837 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3838 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3839 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3840 return ICE_FEC_BASER; 3841 3842 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3843 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3844 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3845 return ICE_FEC_RS; 3846 3847 return ICE_FEC_NONE; 3848 } 3849 3850 /** 3851 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3852 * @pi: port information structure 3853 * @cfg: PHY configuration data to set FC mode 3854 * @req_mode: FC mode to configure 3855 */ 3856 int 3857 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3858 enum ice_fc_mode req_mode) 3859 { 3860 struct ice_phy_cache_mode_data cache_data; 3861 u8 pause_mask = 0x0; 3862 3863 if (!pi || !cfg) 3864 return -EINVAL; 3865 3866 switch (req_mode) { 3867 case ICE_FC_FULL: 3868 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3869 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3870 break; 3871 case ICE_FC_RX_PAUSE: 3872 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3873 break; 3874 case ICE_FC_TX_PAUSE: 3875 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3876 break; 3877 default: 3878 break; 3879 } 3880 3881 /* clear the old pause settings */ 3882 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3883 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3884 3885 /* set the new capabilities */ 3886 cfg->caps |= pause_mask; 3887 3888 /* Cache user FC request */ 3889 cache_data.data.curr_user_fc_req = req_mode; 3890 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3891 3892 return 0; 3893 } 3894 3895 /** 3896 * ice_set_fc 3897 * @pi: port information structure 3898 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3899 * @ena_auto_link_update: enable automatic link update 3900 * 3901 * Set the requested flow control mode. 3902 */ 3903 int 3904 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3905 { 3906 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3907 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3908 struct ice_hw *hw; 3909 int status; 3910 3911 if (!pi || !aq_failures) 3912 return -EINVAL; 3913 3914 *aq_failures = 0; 3915 hw = pi->hw; 3916 3917 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3918 if (!pcaps) 3919 return -ENOMEM; 3920 3921 /* Get the current PHY config */ 3922 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3923 pcaps, NULL); 3924 if (status) { 3925 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3926 goto out; 3927 } 3928 3929 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3930 3931 /* Configure the set PHY data */ 3932 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3933 if (status) 3934 goto out; 3935 3936 /* If the capabilities have changed, then set the new config */ 3937 if (cfg.caps != pcaps->caps) { 3938 int retry_count, retry_max = 10; 3939 3940 /* Auto restart link so settings take effect */ 3941 if (ena_auto_link_update) 3942 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3943 3944 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3945 if (status) { 3946 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3947 goto out; 3948 } 3949 3950 /* Update the link info 3951 * It sometimes takes a really long time for link to 3952 * come back from the atomic reset. Thus, we wait a 3953 * little bit. 3954 */ 3955 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3956 status = ice_update_link_info(pi); 3957 3958 if (!status) 3959 break; 3960 3961 mdelay(100); 3962 } 3963 3964 if (status) 3965 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3966 } 3967 3968 out: 3969 return status; 3970 } 3971 3972 /** 3973 * ice_phy_caps_equals_cfg 3974 * @phy_caps: PHY capabilities 3975 * @phy_cfg: PHY configuration 3976 * 3977 * Helper function to determine if PHY capabilities matches PHY 3978 * configuration 3979 */ 3980 bool 3981 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3982 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3983 { 3984 u8 caps_mask, cfg_mask; 3985 3986 if (!phy_caps || !phy_cfg) 3987 return false; 3988 3989 /* These bits are not common between capabilities and configuration. 3990 * Do not use them to determine equality. 3991 */ 3992 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3993 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3994 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3995 3996 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3997 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3998 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3999 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 4000 phy_caps->eee_cap != phy_cfg->eee_cap || 4001 phy_caps->eeer_value != phy_cfg->eeer_value || 4002 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 4003 return false; 4004 4005 return true; 4006 } 4007 4008 /** 4009 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 4010 * @pi: port information structure 4011 * @caps: PHY ability structure to copy date from 4012 * @cfg: PHY configuration structure to copy data to 4013 * 4014 * Helper function to copy AQC PHY get ability data to PHY set configuration 4015 * data structure 4016 */ 4017 void 4018 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 4019 struct ice_aqc_get_phy_caps_data *caps, 4020 struct ice_aqc_set_phy_cfg_data *cfg) 4021 { 4022 if (!pi || !caps || !cfg) 4023 return; 4024 4025 memset(cfg, 0, sizeof(*cfg)); 4026 cfg->phy_type_low = caps->phy_type_low; 4027 cfg->phy_type_high = caps->phy_type_high; 4028 cfg->caps = caps->caps; 4029 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4030 cfg->eee_cap = caps->eee_cap; 4031 cfg->eeer_value = caps->eeer_value; 4032 cfg->link_fec_opt = caps->link_fec_options; 4033 cfg->module_compliance_enforcement = 4034 caps->module_compliance_enforcement; 4035 } 4036 4037 /** 4038 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4039 * @pi: port information structure 4040 * @cfg: PHY configuration data to set FEC mode 4041 * @fec: FEC mode to configure 4042 */ 4043 int 4044 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4045 enum ice_fec_mode fec) 4046 { 4047 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4048 struct ice_hw *hw; 4049 int status; 4050 4051 if (!pi || !cfg) 4052 return -EINVAL; 4053 4054 hw = pi->hw; 4055 4056 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 4057 if (!pcaps) 4058 return -ENOMEM; 4059 4060 status = ice_aq_get_phy_caps(pi, false, 4061 (ice_fw_supports_report_dflt_cfg(hw) ? 4062 ICE_AQC_REPORT_DFLT_CFG : 4063 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4064 if (status) 4065 goto out; 4066 4067 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4068 cfg->link_fec_opt = pcaps->link_fec_options; 4069 4070 switch (fec) { 4071 case ICE_FEC_BASER: 4072 /* Clear RS bits, and AND BASE-R ability 4073 * bits and OR request bits. 4074 */ 4075 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4076 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4077 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4078 ICE_AQC_PHY_FEC_25G_KR_REQ; 4079 break; 4080 case ICE_FEC_RS: 4081 /* Clear BASE-R bits, and AND RS ability 4082 * bits and OR request bits. 4083 */ 4084 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4085 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4086 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4087 break; 4088 case ICE_FEC_NONE: 4089 /* Clear all FEC option bits. */ 4090 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4091 break; 4092 case ICE_FEC_AUTO: 4093 /* AND auto FEC bit, and all caps bits. */ 4094 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4095 cfg->link_fec_opt |= pcaps->link_fec_options; 4096 break; 4097 default: 4098 status = -EINVAL; 4099 break; 4100 } 4101 4102 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4103 !ice_fw_supports_report_dflt_cfg(hw)) { 4104 struct ice_link_default_override_tlv tlv = { 0 }; 4105 4106 status = ice_get_link_default_override(&tlv, pi); 4107 if (status) 4108 goto out; 4109 4110 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4111 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4112 cfg->link_fec_opt = tlv.fec_options; 4113 } 4114 4115 out: 4116 return status; 4117 } 4118 4119 /** 4120 * ice_get_link_status - get status of the HW network link 4121 * @pi: port information structure 4122 * @link_up: pointer to bool (true/false = linkup/linkdown) 4123 * 4124 * Variable link_up is true if link is up, false if link is down. 4125 * The variable link_up is invalid if status is non zero. As a 4126 * result of this call, link status reporting becomes enabled 4127 */ 4128 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4129 { 4130 struct ice_phy_info *phy_info; 4131 int status = 0; 4132 4133 if (!pi || !link_up) 4134 return -EINVAL; 4135 4136 phy_info = &pi->phy; 4137 4138 if (phy_info->get_link_info) { 4139 status = ice_update_link_info(pi); 4140 4141 if (status) 4142 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4143 status); 4144 } 4145 4146 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4147 4148 return status; 4149 } 4150 4151 /** 4152 * ice_aq_set_link_restart_an 4153 * @pi: pointer to the port information structure 4154 * @ena_link: if true: enable link, if false: disable link 4155 * @cd: pointer to command details structure or NULL 4156 * 4157 * Sets up the link and restarts the Auto-Negotiation over the link. 4158 */ 4159 int 4160 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4161 struct ice_sq_cd *cd) 4162 { 4163 struct ice_aqc_restart_an *cmd; 4164 struct libie_aq_desc desc; 4165 4166 cmd = libie_aq_raw(&desc); 4167 4168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4169 4170 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4171 cmd->lport_num = pi->lport; 4172 if (ena_link) 4173 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4174 else 4175 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4176 4177 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4178 } 4179 4180 /** 4181 * ice_aq_set_event_mask 4182 * @hw: pointer to the HW struct 4183 * @port_num: port number of the physical function 4184 * @mask: event mask to be set 4185 * @cd: pointer to command details structure or NULL 4186 * 4187 * Set event mask (0x0613) 4188 */ 4189 int 4190 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4191 struct ice_sq_cd *cd) 4192 { 4193 struct ice_aqc_set_event_mask *cmd; 4194 struct libie_aq_desc desc; 4195 4196 cmd = libie_aq_raw(&desc); 4197 4198 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4199 4200 cmd->lport_num = port_num; 4201 4202 cmd->event_mask = cpu_to_le16(mask); 4203 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4204 } 4205 4206 /** 4207 * ice_aq_set_mac_loopback 4208 * @hw: pointer to the HW struct 4209 * @ena_lpbk: Enable or Disable loopback 4210 * @cd: pointer to command details structure or NULL 4211 * 4212 * Enable/disable loopback on a given port 4213 */ 4214 int 4215 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4216 { 4217 struct ice_aqc_set_mac_lb *cmd; 4218 struct libie_aq_desc desc; 4219 4220 cmd = libie_aq_raw(&desc); 4221 4222 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4223 if (ena_lpbk) 4224 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4225 4226 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4227 } 4228 4229 /** 4230 * ice_aq_set_port_id_led 4231 * @pi: pointer to the port information 4232 * @is_orig_mode: is this LED set to original mode (by the net-list) 4233 * @cd: pointer to command details structure or NULL 4234 * 4235 * Set LED value for the given port (0x06e9) 4236 */ 4237 int 4238 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4239 struct ice_sq_cd *cd) 4240 { 4241 struct ice_aqc_set_port_id_led *cmd; 4242 struct ice_hw *hw = pi->hw; 4243 struct libie_aq_desc desc; 4244 4245 cmd = libie_aq_raw(&desc); 4246 4247 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4248 4249 if (is_orig_mode) 4250 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4251 else 4252 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4253 4254 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4255 } 4256 4257 /** 4258 * ice_aq_get_port_options 4259 * @hw: pointer to the HW struct 4260 * @options: buffer for the resultant port options 4261 * @option_count: input - size of the buffer in port options structures, 4262 * output - number of returned port options 4263 * @lport: logical port to call the command with (optional) 4264 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4265 * when PF owns more than 1 port it must be true 4266 * @active_option_idx: index of active port option in returned buffer 4267 * @active_option_valid: active option in returned buffer is valid 4268 * @pending_option_idx: index of pending port option in returned buffer 4269 * @pending_option_valid: pending option in returned buffer is valid 4270 * 4271 * Calls Get Port Options AQC (0x06ea) and verifies result. 4272 */ 4273 int 4274 ice_aq_get_port_options(struct ice_hw *hw, 4275 struct ice_aqc_get_port_options_elem *options, 4276 u8 *option_count, u8 lport, bool lport_valid, 4277 u8 *active_option_idx, bool *active_option_valid, 4278 u8 *pending_option_idx, bool *pending_option_valid) 4279 { 4280 struct ice_aqc_get_port_options *cmd; 4281 struct libie_aq_desc desc; 4282 int status; 4283 u8 i; 4284 4285 /* options buffer shall be able to hold max returned options */ 4286 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4287 return -EINVAL; 4288 4289 cmd = libie_aq_raw(&desc); 4290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4291 4292 if (lport_valid) 4293 cmd->lport_num = lport; 4294 cmd->lport_num_valid = lport_valid; 4295 4296 status = ice_aq_send_cmd(hw, &desc, options, 4297 *option_count * sizeof(*options), NULL); 4298 if (status) 4299 return status; 4300 4301 /* verify direct FW response & set output parameters */ 4302 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4303 cmd->port_options_count); 4304 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4305 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4306 cmd->port_options); 4307 if (*active_option_valid) { 4308 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4309 cmd->port_options); 4310 if (*active_option_idx > (*option_count - 1)) 4311 return -EIO; 4312 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4313 *active_option_idx); 4314 } 4315 4316 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4317 cmd->pending_port_option_status); 4318 if (*pending_option_valid) { 4319 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4320 cmd->pending_port_option_status); 4321 if (*pending_option_idx > (*option_count - 1)) 4322 return -EIO; 4323 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4324 *pending_option_idx); 4325 } 4326 4327 /* mask output options fields */ 4328 for (i = 0; i < *option_count; i++) { 4329 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4330 options[i].pmd); 4331 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4332 options[i].max_lane_speed); 4333 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4334 options[i].pmd, options[i].max_lane_speed); 4335 } 4336 4337 return 0; 4338 } 4339 4340 /** 4341 * ice_aq_set_port_option 4342 * @hw: pointer to the HW struct 4343 * @lport: logical port to call the command with 4344 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4345 * when PF owns more than 1 port it must be true 4346 * @new_option: new port option to be written 4347 * 4348 * Calls Set Port Options AQC (0x06eb). 4349 */ 4350 int 4351 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4352 u8 new_option) 4353 { 4354 struct ice_aqc_set_port_option *cmd; 4355 struct libie_aq_desc desc; 4356 4357 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4358 return -EINVAL; 4359 4360 cmd = libie_aq_raw(&desc); 4361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4362 4363 if (lport_valid) 4364 cmd->lport_num = lport; 4365 4366 cmd->lport_num_valid = lport_valid; 4367 cmd->selected_port_option = new_option; 4368 4369 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4370 } 4371 4372 /** 4373 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4374 * @hw: pointer to the hw struct 4375 * 4376 * Return: PHY lane number on success, negative error code otherwise. 4377 */ 4378 int ice_get_phy_lane_number(struct ice_hw *hw) 4379 { 4380 struct ice_aqc_get_port_options_elem *options; 4381 unsigned int lport = 0; 4382 unsigned int lane; 4383 int err; 4384 4385 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4386 if (!options) 4387 return -ENOMEM; 4388 4389 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4390 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4391 u8 speed, active_idx, pending_idx; 4392 bool active_valid, pending_valid; 4393 4394 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4395 true, &active_idx, &active_valid, 4396 &pending_idx, &pending_valid); 4397 if (err) 4398 goto err; 4399 4400 if (!active_valid) 4401 continue; 4402 4403 speed = options[active_idx].max_lane_speed; 4404 /* If we don't get speed for this lane, it's unoccupied */ 4405 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4406 continue; 4407 4408 if (hw->pf_id == lport) { 4409 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4410 ice_is_dual(hw) && !ice_is_primary(hw)) 4411 lane += ICE_PORTS_PER_QUAD; 4412 kfree(options); 4413 return lane; 4414 } 4415 lport++; 4416 } 4417 4418 /* PHY lane not found */ 4419 err = -ENXIO; 4420 err: 4421 kfree(options); 4422 return err; 4423 } 4424 4425 /** 4426 * ice_aq_sff_eeprom 4427 * @hw: pointer to the HW struct 4428 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4429 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4430 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4431 * @page: QSFP page 4432 * @set_page: set or ignore the page 4433 * @data: pointer to data buffer to be read/written to the I2C device. 4434 * @length: 1-16 for read, 1 for write. 4435 * @write: 0 read, 1 for write. 4436 * @cd: pointer to command details structure or NULL 4437 * 4438 * Read/Write SFF EEPROM (0x06EE) 4439 */ 4440 int 4441 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4442 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4443 bool write, struct ice_sq_cd *cd) 4444 { 4445 struct ice_aqc_sff_eeprom *cmd; 4446 struct libie_aq_desc desc; 4447 u16 i2c_bus_addr; 4448 int status; 4449 4450 if (!data || (mem_addr & 0xff00)) 4451 return -EINVAL; 4452 4453 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4454 cmd = libie_aq_raw(&desc); 4455 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4456 cmd->lport_num = (u8)(lport & 0xff); 4457 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4458 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4459 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4460 if (write) 4461 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4462 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4463 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4464 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4465 4466 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4467 return status; 4468 } 4469 4470 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4471 { 4472 switch (type) { 4473 case ICE_LUT_VSI: 4474 return ICE_LUT_VSI_SIZE; 4475 case ICE_LUT_GLOBAL: 4476 return ICE_LUT_GLOBAL_SIZE; 4477 case ICE_LUT_PF: 4478 return ICE_LUT_PF_SIZE; 4479 } 4480 WARN_ONCE(1, "incorrect type passed"); 4481 return ICE_LUT_VSI_SIZE; 4482 } 4483 4484 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4485 { 4486 switch (size) { 4487 case ICE_LUT_VSI_SIZE: 4488 return ICE_AQC_LUT_SIZE_SMALL; 4489 case ICE_LUT_GLOBAL_SIZE: 4490 return ICE_AQC_LUT_SIZE_512; 4491 case ICE_LUT_PF_SIZE: 4492 return ICE_AQC_LUT_SIZE_2K; 4493 } 4494 WARN_ONCE(1, "incorrect size passed"); 4495 return 0; 4496 } 4497 4498 /** 4499 * __ice_aq_get_set_rss_lut 4500 * @hw: pointer to the hardware structure 4501 * @params: RSS LUT parameters 4502 * @set: set true to set the table, false to get the table 4503 * 4504 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4505 */ 4506 static int 4507 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4508 struct ice_aq_get_set_rss_lut_params *params, bool set) 4509 { 4510 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4511 enum ice_lut_type lut_type = params->lut_type; 4512 struct ice_aqc_get_set_rss_lut *desc_params; 4513 enum ice_aqc_lut_flags flags; 4514 enum ice_lut_size lut_size; 4515 struct libie_aq_desc desc; 4516 u8 *lut = params->lut; 4517 4518 4519 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4520 return -EINVAL; 4521 4522 lut_size = ice_lut_type_to_size(lut_type); 4523 if (lut_size > params->lut_size) 4524 return -EINVAL; 4525 else if (set && lut_size != params->lut_size) 4526 return -EINVAL; 4527 4528 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4529 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4530 if (set) 4531 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4532 4533 desc_params = libie_aq_raw(&desc); 4534 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4535 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4536 4537 if (lut_type == ICE_LUT_GLOBAL) 4538 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4539 params->global_lut_id); 4540 4541 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4542 desc_params->flags = cpu_to_le16(flags); 4543 4544 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4545 } 4546 4547 /** 4548 * ice_aq_get_rss_lut 4549 * @hw: pointer to the hardware structure 4550 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4551 * 4552 * get the RSS lookup table, PF or VSI type 4553 */ 4554 int 4555 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4556 { 4557 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4558 } 4559 4560 /** 4561 * ice_aq_set_rss_lut 4562 * @hw: pointer to the hardware structure 4563 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4564 * 4565 * set the RSS lookup table, PF or VSI type 4566 */ 4567 int 4568 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4569 { 4570 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4571 } 4572 4573 /** 4574 * __ice_aq_get_set_rss_key 4575 * @hw: pointer to the HW struct 4576 * @vsi_id: VSI FW index 4577 * @key: pointer to key info struct 4578 * @set: set true to set the key, false to get the key 4579 * 4580 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4581 */ 4582 static int 4583 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4584 struct ice_aqc_get_set_rss_keys *key, bool set) 4585 { 4586 struct ice_aqc_get_set_rss_key *desc_params; 4587 u16 key_size = sizeof(*key); 4588 struct libie_aq_desc desc; 4589 4590 if (set) { 4591 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4592 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4593 } else { 4594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4595 } 4596 4597 desc_params = libie_aq_raw(&desc); 4598 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4599 4600 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4601 } 4602 4603 /** 4604 * ice_aq_get_rss_key 4605 * @hw: pointer to the HW struct 4606 * @vsi_handle: software VSI handle 4607 * @key: pointer to key info struct 4608 * 4609 * get the RSS key per VSI 4610 */ 4611 int 4612 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4613 struct ice_aqc_get_set_rss_keys *key) 4614 { 4615 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4616 return -EINVAL; 4617 4618 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4619 key, false); 4620 } 4621 4622 /** 4623 * ice_aq_set_rss_key 4624 * @hw: pointer to the HW struct 4625 * @vsi_handle: software VSI handle 4626 * @keys: pointer to key info struct 4627 * 4628 * set the RSS key per VSI 4629 */ 4630 int 4631 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4632 struct ice_aqc_get_set_rss_keys *keys) 4633 { 4634 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4635 return -EINVAL; 4636 4637 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4638 keys, true); 4639 } 4640 4641 /** 4642 * ice_aq_add_lan_txq 4643 * @hw: pointer to the hardware structure 4644 * @num_qgrps: Number of added queue groups 4645 * @qg_list: list of queue groups to be added 4646 * @buf_size: size of buffer for indirect command 4647 * @cd: pointer to command details structure or NULL 4648 * 4649 * Add Tx LAN queue (0x0C30) 4650 * 4651 * NOTE: 4652 * Prior to calling add Tx LAN queue: 4653 * Initialize the following as part of the Tx queue context: 4654 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4655 * Cache profile and Packet shaper profile. 4656 * 4657 * After add Tx LAN queue AQ command is completed: 4658 * Interrupts should be associated with specific queues, 4659 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4660 * flow. 4661 */ 4662 static int 4663 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4664 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4665 struct ice_sq_cd *cd) 4666 { 4667 struct ice_aqc_add_tx_qgrp *list; 4668 struct ice_aqc_add_txqs *cmd; 4669 struct libie_aq_desc desc; 4670 u16 i, sum_size = 0; 4671 4672 cmd = libie_aq_raw(&desc); 4673 4674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4675 4676 if (!qg_list) 4677 return -EINVAL; 4678 4679 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4680 return -EINVAL; 4681 4682 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4683 sum_size += struct_size(list, txqs, list->num_txqs); 4684 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4685 list->num_txqs); 4686 } 4687 4688 if (buf_size != sum_size) 4689 return -EINVAL; 4690 4691 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4692 4693 cmd->num_qgrps = num_qgrps; 4694 4695 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4696 } 4697 4698 /** 4699 * ice_aq_dis_lan_txq 4700 * @hw: pointer to the hardware structure 4701 * @num_qgrps: number of groups in the list 4702 * @qg_list: the list of groups to disable 4703 * @buf_size: the total size of the qg_list buffer in bytes 4704 * @rst_src: if called due to reset, specifies the reset source 4705 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4706 * @cd: pointer to command details structure or NULL 4707 * 4708 * Disable LAN Tx queue (0x0C31) 4709 */ 4710 static int 4711 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4712 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4713 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4714 struct ice_sq_cd *cd) 4715 { 4716 struct ice_aqc_dis_txq_item *item; 4717 struct ice_aqc_dis_txqs *cmd; 4718 struct libie_aq_desc desc; 4719 u16 vmvf_and_timeout; 4720 u16 i, sz = 0; 4721 int status; 4722 4723 cmd = libie_aq_raw(&desc); 4724 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4725 4726 /* qg_list can be NULL only in VM/VF reset flow */ 4727 if (!qg_list && !rst_src) 4728 return -EINVAL; 4729 4730 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4731 return -EINVAL; 4732 4733 cmd->num_entries = num_qgrps; 4734 4735 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4736 4737 switch (rst_src) { 4738 case ICE_VM_RESET: 4739 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4740 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4741 break; 4742 case ICE_VF_RESET: 4743 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4744 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4745 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4746 ICE_AQC_Q_DIS_VMVF_NUM_M; 4747 break; 4748 case ICE_NO_RESET: 4749 default: 4750 break; 4751 } 4752 4753 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4754 4755 /* flush pipe on time out */ 4756 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4757 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4758 if (!qg_list) 4759 goto do_aq; 4760 4761 /* set RD bit to indicate that command buffer is provided by the driver 4762 * and it needs to be read by the firmware 4763 */ 4764 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4765 4766 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4767 u16 item_size = struct_size(item, q_id, item->num_qs); 4768 4769 /* If the num of queues is even, add 2 bytes of padding */ 4770 if ((item->num_qs % 2) == 0) 4771 item_size += 2; 4772 4773 sz += item_size; 4774 4775 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4776 } 4777 4778 if (buf_size != sz) 4779 return -EINVAL; 4780 4781 do_aq: 4782 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4783 if (status) { 4784 if (!qg_list) 4785 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4786 vmvf_num, hw->adminq.sq_last_status); 4787 else 4788 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4789 le16_to_cpu(qg_list[0].q_id[0]), 4790 hw->adminq.sq_last_status); 4791 } 4792 return status; 4793 } 4794 4795 /** 4796 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4797 * @hw: pointer to the hardware structure 4798 * @buf: buffer for command 4799 * @buf_size: size of buffer in bytes 4800 * @num_qs: number of queues being configured 4801 * @oldport: origination lport 4802 * @newport: destination lport 4803 * @mode: cmd_type for move to use 4804 * @cd: pointer to command details structure or NULL 4805 * 4806 * Move/Configure LAN Tx queue (0x0C32) 4807 * 4808 * Return: Zero on success, associated error code on failure. 4809 */ 4810 int 4811 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4812 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4813 u8 mode, struct ice_sq_cd *cd) 4814 { 4815 struct ice_aqc_cfg_txqs *cmd; 4816 struct libie_aq_desc desc; 4817 int status; 4818 4819 cmd = libie_aq_raw(&desc); 4820 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4821 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4822 4823 if (!buf) 4824 return -EINVAL; 4825 4826 cmd->cmd_type = mode; 4827 cmd->num_qs = num_qs; 4828 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4829 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4830 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4831 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4832 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4833 cmd->blocked_cgds = 0; 4834 4835 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4836 if (status) 4837 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4838 hw->adminq.sq_last_status); 4839 return status; 4840 } 4841 4842 /** 4843 * ice_aq_add_rdma_qsets 4844 * @hw: pointer to the hardware structure 4845 * @num_qset_grps: Number of RDMA Qset groups 4846 * @qset_list: list of Qset groups to be added 4847 * @buf_size: size of buffer for indirect command 4848 * @cd: pointer to command details structure or NULL 4849 * 4850 * Add Tx RDMA Qsets (0x0C33) 4851 */ 4852 static int 4853 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4854 struct ice_aqc_add_rdma_qset_data *qset_list, 4855 u16 buf_size, struct ice_sq_cd *cd) 4856 { 4857 struct ice_aqc_add_rdma_qset_data *list; 4858 struct ice_aqc_add_rdma_qset *cmd; 4859 struct libie_aq_desc desc; 4860 u16 i, sum_size = 0; 4861 4862 cmd = libie_aq_raw(&desc); 4863 4864 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4865 4866 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4867 return -EINVAL; 4868 4869 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4870 u16 num_qsets = le16_to_cpu(list->num_qsets); 4871 4872 sum_size += struct_size(list, rdma_qsets, num_qsets); 4873 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4874 num_qsets); 4875 } 4876 4877 if (buf_size != sum_size) 4878 return -EINVAL; 4879 4880 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4881 4882 cmd->num_qset_grps = num_qset_grps; 4883 4884 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4885 } 4886 4887 /** 4888 * ice_aq_set_txtimeq - set Tx time queues 4889 * @hw: pointer to the hardware structure 4890 * @txtimeq: first Tx time queue id to configure 4891 * @q_count: number of queues to configure 4892 * @txtime_qg: queue group to be set 4893 * @buf_size: size of buffer for indirect command 4894 * @cd: pointer to command details structure or NULL 4895 * 4896 * Set Tx Time queue (0x0C35) 4897 * Return: 0 on success or negative value on failure. 4898 */ 4899 int 4900 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4901 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4902 struct ice_sq_cd *cd) 4903 { 4904 struct ice_aqc_set_txtimeqs *cmd; 4905 struct libie_aq_desc desc; 4906 u16 size; 4907 4908 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4909 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4910 return -EINVAL; 4911 4912 size = struct_size(txtime_qg, txtimeqs, q_count); 4913 if (buf_size != size) 4914 return -EINVAL; 4915 4916 cmd = libie_aq_raw(&desc); 4917 4918 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4919 4920 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4921 4922 cmd->q_id = cpu_to_le16(txtimeq); 4923 cmd->q_amount = cpu_to_le16(q_count); 4924 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4925 } 4926 4927 /* End of FW Admin Queue command wrappers */ 4928 4929 /** 4930 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4931 * @hw: pointer to the HW struct 4932 * @vsi_handle: software VSI handle 4933 * @tc: TC number 4934 * @q_handle: software queue handle 4935 */ 4936 struct ice_q_ctx * 4937 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4938 { 4939 struct ice_vsi_ctx *vsi; 4940 struct ice_q_ctx *q_ctx; 4941 4942 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4943 if (!vsi) 4944 return NULL; 4945 if (q_handle >= vsi->num_lan_q_entries[tc]) 4946 return NULL; 4947 if (!vsi->lan_q_ctx[tc]) 4948 return NULL; 4949 q_ctx = vsi->lan_q_ctx[tc]; 4950 return &q_ctx[q_handle]; 4951 } 4952 4953 /** 4954 * ice_ena_vsi_txq 4955 * @pi: port information structure 4956 * @vsi_handle: software VSI handle 4957 * @tc: TC number 4958 * @q_handle: software queue handle 4959 * @num_qgrps: Number of added queue groups 4960 * @buf: list of queue groups to be added 4961 * @buf_size: size of buffer for indirect command 4962 * @cd: pointer to command details structure or NULL 4963 * 4964 * This function adds one LAN queue 4965 */ 4966 int 4967 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4968 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4969 struct ice_sq_cd *cd) 4970 { 4971 struct ice_aqc_txsched_elem_data node = { 0 }; 4972 struct ice_sched_node *parent; 4973 struct ice_q_ctx *q_ctx; 4974 struct ice_hw *hw; 4975 int status; 4976 4977 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4978 return -EIO; 4979 4980 if (num_qgrps > 1 || buf->num_txqs > 1) 4981 return -ENOSPC; 4982 4983 hw = pi->hw; 4984 4985 if (!ice_is_vsi_valid(hw, vsi_handle)) 4986 return -EINVAL; 4987 4988 mutex_lock(&pi->sched_lock); 4989 4990 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4991 if (!q_ctx) { 4992 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4993 q_handle); 4994 status = -EINVAL; 4995 goto ena_txq_exit; 4996 } 4997 4998 /* find a parent node */ 4999 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5000 ICE_SCHED_NODE_OWNER_LAN); 5001 if (!parent) { 5002 status = -EINVAL; 5003 goto ena_txq_exit; 5004 } 5005 5006 buf->parent_teid = parent->info.node_teid; 5007 node.parent_teid = parent->info.node_teid; 5008 /* Mark that the values in the "generic" section as valid. The default 5009 * value in the "generic" section is zero. This means that : 5010 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 5011 * - 0 priority among siblings, indicated by Bit 1-3. 5012 * - WFQ, indicated by Bit 4. 5013 * - 0 Adjustment value is used in PSM credit update flow, indicated by 5014 * Bit 5-6. 5015 * - Bit 7 is reserved. 5016 * Without setting the generic section as valid in valid_sections, the 5017 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5018 */ 5019 buf->txqs[0].info.valid_sections = 5020 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5021 ICE_AQC_ELEM_VALID_EIR; 5022 buf->txqs[0].info.generic = 0; 5023 buf->txqs[0].info.cir_bw.bw_profile_idx = 5024 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5025 buf->txqs[0].info.cir_bw.bw_alloc = 5026 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5027 buf->txqs[0].info.eir_bw.bw_profile_idx = 5028 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5029 buf->txqs[0].info.eir_bw.bw_alloc = 5030 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5031 5032 /* add the LAN queue */ 5033 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5034 if (status) { 5035 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5036 le16_to_cpu(buf->txqs[0].txq_id), 5037 hw->adminq.sq_last_status); 5038 goto ena_txq_exit; 5039 } 5040 5041 node.node_teid = buf->txqs[0].q_teid; 5042 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5043 q_ctx->q_handle = q_handle; 5044 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5045 5046 /* add a leaf node into scheduler tree queue layer */ 5047 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5048 if (!status) 5049 status = ice_sched_replay_q_bw(pi, q_ctx); 5050 5051 ena_txq_exit: 5052 mutex_unlock(&pi->sched_lock); 5053 return status; 5054 } 5055 5056 /** 5057 * ice_dis_vsi_txq 5058 * @pi: port information structure 5059 * @vsi_handle: software VSI handle 5060 * @tc: TC number 5061 * @num_queues: number of queues 5062 * @q_handles: pointer to software queue handle array 5063 * @q_ids: pointer to the q_id array 5064 * @q_teids: pointer to queue node teids 5065 * @rst_src: if called due to reset, specifies the reset source 5066 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5067 * @cd: pointer to command details structure or NULL 5068 * 5069 * This function removes queues and their corresponding nodes in SW DB 5070 */ 5071 int 5072 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5073 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5074 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5075 struct ice_sq_cd *cd) 5076 { 5077 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5078 u16 i, buf_size = __struct_size(qg_list); 5079 struct ice_q_ctx *q_ctx; 5080 int status = -ENOENT; 5081 struct ice_hw *hw; 5082 5083 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5084 return -EIO; 5085 5086 hw = pi->hw; 5087 5088 if (!num_queues) { 5089 /* if queue is disabled already yet the disable queue command 5090 * has to be sent to complete the VF reset, then call 5091 * ice_aq_dis_lan_txq without any queue information 5092 */ 5093 if (rst_src) 5094 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5095 vmvf_num, NULL); 5096 return -EIO; 5097 } 5098 5099 mutex_lock(&pi->sched_lock); 5100 5101 for (i = 0; i < num_queues; i++) { 5102 struct ice_sched_node *node; 5103 5104 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5105 if (!node) 5106 continue; 5107 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5108 if (!q_ctx) { 5109 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5110 q_handles[i]); 5111 continue; 5112 } 5113 if (q_ctx->q_handle != q_handles[i]) { 5114 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5115 q_ctx->q_handle, q_handles[i]); 5116 continue; 5117 } 5118 qg_list->parent_teid = node->info.parent_teid; 5119 qg_list->num_qs = 1; 5120 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5121 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5122 vmvf_num, cd); 5123 5124 if (status) 5125 break; 5126 ice_free_sched_node(pi, node); 5127 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5128 q_ctx->q_teid = ICE_INVAL_TEID; 5129 } 5130 mutex_unlock(&pi->sched_lock); 5131 return status; 5132 } 5133 5134 /** 5135 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5136 * @pi: port information structure 5137 * @vsi_handle: software VSI handle 5138 * @tc_bitmap: TC bitmap 5139 * @maxqs: max queues array per TC 5140 * @owner: LAN or RDMA 5141 * 5142 * This function adds/updates the VSI queues per TC. 5143 */ 5144 static int 5145 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5146 u16 *maxqs, u8 owner) 5147 { 5148 int status = 0; 5149 u8 i; 5150 5151 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5152 return -EIO; 5153 5154 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5155 return -EINVAL; 5156 5157 mutex_lock(&pi->sched_lock); 5158 5159 ice_for_each_traffic_class(i) { 5160 /* configuration is possible only if TC node is present */ 5161 if (!ice_sched_get_tc_node(pi, i)) 5162 continue; 5163 5164 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5165 ice_is_tc_ena(tc_bitmap, i)); 5166 if (status) 5167 break; 5168 } 5169 5170 mutex_unlock(&pi->sched_lock); 5171 return status; 5172 } 5173 5174 /** 5175 * ice_cfg_vsi_lan - configure VSI LAN queues 5176 * @pi: port information structure 5177 * @vsi_handle: software VSI handle 5178 * @tc_bitmap: TC bitmap 5179 * @max_lanqs: max LAN queues array per TC 5180 * 5181 * This function adds/updates the VSI LAN queues per TC. 5182 */ 5183 int 5184 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5185 u16 *max_lanqs) 5186 { 5187 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5188 ICE_SCHED_NODE_OWNER_LAN); 5189 } 5190 5191 /** 5192 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5193 * @pi: port information structure 5194 * @vsi_handle: software VSI handle 5195 * @tc_bitmap: TC bitmap 5196 * @max_rdmaqs: max RDMA queues array per TC 5197 * 5198 * This function adds/updates the VSI RDMA queues per TC. 5199 */ 5200 int 5201 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5202 u16 *max_rdmaqs) 5203 { 5204 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5205 ICE_SCHED_NODE_OWNER_RDMA); 5206 } 5207 5208 /** 5209 * ice_ena_vsi_rdma_qset 5210 * @pi: port information structure 5211 * @vsi_handle: software VSI handle 5212 * @tc: TC number 5213 * @rdma_qset: pointer to RDMA Qset 5214 * @num_qsets: number of RDMA Qsets 5215 * @qset_teid: pointer to Qset node TEIDs 5216 * 5217 * This function adds RDMA Qset 5218 */ 5219 int 5220 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5221 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5222 { 5223 struct ice_aqc_txsched_elem_data node = { 0 }; 5224 struct ice_aqc_add_rdma_qset_data *buf; 5225 struct ice_sched_node *parent; 5226 struct ice_hw *hw; 5227 u16 i, buf_size; 5228 int ret; 5229 5230 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5231 return -EIO; 5232 hw = pi->hw; 5233 5234 if (!ice_is_vsi_valid(hw, vsi_handle)) 5235 return -EINVAL; 5236 5237 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5238 buf = kzalloc(buf_size, GFP_KERNEL); 5239 if (!buf) 5240 return -ENOMEM; 5241 mutex_lock(&pi->sched_lock); 5242 5243 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5244 ICE_SCHED_NODE_OWNER_RDMA); 5245 if (!parent) { 5246 ret = -EINVAL; 5247 goto rdma_error_exit; 5248 } 5249 buf->parent_teid = parent->info.node_teid; 5250 node.parent_teid = parent->info.node_teid; 5251 5252 buf->num_qsets = cpu_to_le16(num_qsets); 5253 for (i = 0; i < num_qsets; i++) { 5254 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5255 buf->rdma_qsets[i].info.valid_sections = 5256 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5257 ICE_AQC_ELEM_VALID_EIR; 5258 buf->rdma_qsets[i].info.generic = 0; 5259 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5260 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5261 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5262 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5263 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5264 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5265 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5266 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5267 } 5268 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5269 if (ret) { 5270 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5271 goto rdma_error_exit; 5272 } 5273 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5274 for (i = 0; i < num_qsets; i++) { 5275 node.node_teid = buf->rdma_qsets[i].qset_teid; 5276 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5277 &node, NULL); 5278 if (ret) 5279 break; 5280 qset_teid[i] = le32_to_cpu(node.node_teid); 5281 } 5282 rdma_error_exit: 5283 mutex_unlock(&pi->sched_lock); 5284 kfree(buf); 5285 return ret; 5286 } 5287 5288 /** 5289 * ice_dis_vsi_rdma_qset - free RDMA resources 5290 * @pi: port_info struct 5291 * @count: number of RDMA Qsets to free 5292 * @qset_teid: TEID of Qset node 5293 * @q_id: list of queue IDs being disabled 5294 */ 5295 int 5296 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5297 u16 *q_id) 5298 { 5299 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5300 u16 qg_size = __struct_size(qg_list); 5301 struct ice_hw *hw; 5302 int status = 0; 5303 int i; 5304 5305 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5306 return -EIO; 5307 5308 hw = pi->hw; 5309 5310 mutex_lock(&pi->sched_lock); 5311 5312 for (i = 0; i < count; i++) { 5313 struct ice_sched_node *node; 5314 5315 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5316 if (!node) 5317 continue; 5318 5319 qg_list->parent_teid = node->info.parent_teid; 5320 qg_list->num_qs = 1; 5321 qg_list->q_id[0] = 5322 cpu_to_le16(q_id[i] | 5323 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5324 5325 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5326 ICE_NO_RESET, 0, NULL); 5327 if (status) 5328 break; 5329 5330 ice_free_sched_node(pi, node); 5331 } 5332 5333 mutex_unlock(&pi->sched_lock); 5334 return status; 5335 } 5336 5337 /** 5338 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5339 * @hw: pointer to the HW struct 5340 * @dpll_idx: index of dpll to be measured 5341 * @meas: array to be filled with results 5342 * @meas_num: max number of results array can hold 5343 * 5344 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5345 * pins on given dpll. 5346 * 5347 * Return: 0 on success or negative value on failure. 5348 */ 5349 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5350 struct ice_cgu_input_measure *meas, 5351 u16 meas_num) 5352 { 5353 struct ice_aqc_get_cgu_input_measure *cmd; 5354 struct libie_aq_desc desc; 5355 5356 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5357 cmd = libie_aq_raw(&desc); 5358 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5359 5360 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5361 } 5362 5363 /** 5364 * ice_aq_get_cgu_abilities - get cgu abilities 5365 * @hw: pointer to the HW struct 5366 * @abilities: CGU abilities 5367 * 5368 * Get CGU abilities (0x0C61) 5369 * Return: 0 on success or negative value on failure. 5370 */ 5371 int 5372 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5373 struct ice_aqc_get_cgu_abilities *abilities) 5374 { 5375 struct libie_aq_desc desc; 5376 5377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5378 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5379 } 5380 5381 /** 5382 * ice_aq_set_input_pin_cfg - set input pin config 5383 * @hw: pointer to the HW struct 5384 * @input_idx: Input index 5385 * @flags1: Input flags 5386 * @flags2: Input flags 5387 * @freq: Frequency in Hz 5388 * @phase_delay: Delay in ps 5389 * 5390 * Set CGU input config (0x0C62) 5391 * Return: 0 on success or negative value on failure. 5392 */ 5393 int 5394 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5395 u32 freq, s32 phase_delay) 5396 { 5397 struct ice_aqc_set_cgu_input_config *cmd; 5398 struct libie_aq_desc desc; 5399 5400 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5401 cmd = libie_aq_raw(&desc); 5402 cmd->input_idx = input_idx; 5403 cmd->flags1 = flags1; 5404 cmd->flags2 = flags2; 5405 cmd->freq = cpu_to_le32(freq); 5406 cmd->phase_delay = cpu_to_le32(phase_delay); 5407 5408 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5409 } 5410 5411 /** 5412 * ice_aq_get_input_pin_cfg - get input pin config 5413 * @hw: pointer to the HW struct 5414 * @input_idx: Input index 5415 * @status: Pin status 5416 * @type: Pin type 5417 * @flags1: Input flags 5418 * @flags2: Input flags 5419 * @freq: Frequency in Hz 5420 * @phase_delay: Delay in ps 5421 * 5422 * Get CGU input config (0x0C63) 5423 * Return: 0 on success or negative value on failure. 5424 */ 5425 int 5426 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5427 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5428 { 5429 struct ice_aqc_get_cgu_input_config *cmd; 5430 struct libie_aq_desc desc; 5431 int ret; 5432 5433 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5434 cmd = libie_aq_raw(&desc); 5435 cmd->input_idx = input_idx; 5436 5437 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5438 if (!ret) { 5439 if (status) 5440 *status = cmd->status; 5441 if (type) 5442 *type = cmd->type; 5443 if (flags1) 5444 *flags1 = cmd->flags1; 5445 if (flags2) 5446 *flags2 = cmd->flags2; 5447 if (freq) 5448 *freq = le32_to_cpu(cmd->freq); 5449 if (phase_delay) 5450 *phase_delay = le32_to_cpu(cmd->phase_delay); 5451 } 5452 5453 return ret; 5454 } 5455 5456 /** 5457 * ice_aq_set_output_pin_cfg - set output pin config 5458 * @hw: pointer to the HW struct 5459 * @output_idx: Output index 5460 * @flags: Output flags 5461 * @src_sel: Index of DPLL block 5462 * @freq: Output frequency 5463 * @phase_delay: Output phase compensation 5464 * 5465 * Set CGU output config (0x0C64) 5466 * Return: 0 on success or negative value on failure. 5467 */ 5468 int 5469 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5470 u8 src_sel, u32 freq, s32 phase_delay) 5471 { 5472 struct ice_aqc_set_cgu_output_config *cmd; 5473 struct libie_aq_desc desc; 5474 5475 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5476 cmd = libie_aq_raw(&desc); 5477 cmd->output_idx = output_idx; 5478 cmd->flags = flags; 5479 cmd->src_sel = src_sel; 5480 cmd->freq = cpu_to_le32(freq); 5481 cmd->phase_delay = cpu_to_le32(phase_delay); 5482 5483 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5484 } 5485 5486 /** 5487 * ice_aq_get_output_pin_cfg - get output pin config 5488 * @hw: pointer to the HW struct 5489 * @output_idx: Output index 5490 * @flags: Output flags 5491 * @src_sel: Internal DPLL source 5492 * @freq: Output frequency 5493 * @src_freq: Source frequency 5494 * 5495 * Get CGU output config (0x0C65) 5496 * Return: 0 on success or negative value on failure. 5497 */ 5498 int 5499 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5500 u8 *src_sel, u32 *freq, u32 *src_freq) 5501 { 5502 struct ice_aqc_get_cgu_output_config *cmd; 5503 struct libie_aq_desc desc; 5504 int ret; 5505 5506 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5507 cmd = libie_aq_raw(&desc); 5508 cmd->output_idx = output_idx; 5509 5510 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5511 if (!ret) { 5512 if (flags) 5513 *flags = cmd->flags; 5514 if (src_sel) 5515 *src_sel = cmd->src_sel; 5516 if (freq) 5517 *freq = le32_to_cpu(cmd->freq); 5518 if (src_freq) 5519 *src_freq = le32_to_cpu(cmd->src_freq); 5520 } 5521 5522 return ret; 5523 } 5524 5525 /** 5526 * ice_aq_get_cgu_dpll_status - get dpll status 5527 * @hw: pointer to the HW struct 5528 * @dpll_num: DPLL index 5529 * @ref_state: Reference clock state 5530 * @config: current DPLL config 5531 * @dpll_state: current DPLL state 5532 * @phase_offset: Phase offset in ns 5533 * @eec_mode: EEC_mode 5534 * 5535 * Get CGU DPLL status (0x0C66) 5536 * Return: 0 on success or negative value on failure. 5537 */ 5538 int 5539 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5540 u8 *dpll_state, u8 *config, s64 *phase_offset, 5541 u8 *eec_mode) 5542 { 5543 struct ice_aqc_get_cgu_dpll_status *cmd; 5544 struct libie_aq_desc desc; 5545 int status; 5546 5547 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5548 cmd = libie_aq_raw(&desc); 5549 cmd->dpll_num = dpll_num; 5550 5551 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5552 if (!status) { 5553 *ref_state = cmd->ref_state; 5554 *dpll_state = cmd->dpll_state; 5555 *config = cmd->config; 5556 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5557 *phase_offset <<= 32; 5558 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5559 *phase_offset = sign_extend64(*phase_offset, 47); 5560 *eec_mode = cmd->eec_mode; 5561 } 5562 5563 return status; 5564 } 5565 5566 /** 5567 * ice_aq_set_cgu_dpll_config - set dpll config 5568 * @hw: pointer to the HW struct 5569 * @dpll_num: DPLL index 5570 * @ref_state: Reference clock state 5571 * @config: DPLL config 5572 * @eec_mode: EEC mode 5573 * 5574 * Set CGU DPLL config (0x0C67) 5575 * Return: 0 on success or negative value on failure. 5576 */ 5577 int 5578 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5579 u8 config, u8 eec_mode) 5580 { 5581 struct ice_aqc_set_cgu_dpll_config *cmd; 5582 struct libie_aq_desc desc; 5583 5584 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5585 cmd = libie_aq_raw(&desc); 5586 cmd->dpll_num = dpll_num; 5587 cmd->ref_state = ref_state; 5588 cmd->config = config; 5589 cmd->eec_mode = eec_mode; 5590 5591 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5592 } 5593 5594 /** 5595 * ice_aq_set_cgu_ref_prio - set input reference priority 5596 * @hw: pointer to the HW struct 5597 * @dpll_num: DPLL index 5598 * @ref_idx: Reference pin index 5599 * @ref_priority: Reference input priority 5600 * 5601 * Set CGU reference priority (0x0C68) 5602 * Return: 0 on success or negative value on failure. 5603 */ 5604 int 5605 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5606 u8 ref_priority) 5607 { 5608 struct ice_aqc_set_cgu_ref_prio *cmd; 5609 struct libie_aq_desc desc; 5610 5611 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5612 cmd = libie_aq_raw(&desc); 5613 cmd->dpll_num = dpll_num; 5614 cmd->ref_idx = ref_idx; 5615 cmd->ref_priority = ref_priority; 5616 5617 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5618 } 5619 5620 /** 5621 * ice_aq_get_cgu_ref_prio - get input reference priority 5622 * @hw: pointer to the HW struct 5623 * @dpll_num: DPLL index 5624 * @ref_idx: Reference pin index 5625 * @ref_prio: Reference input priority 5626 * 5627 * Get CGU reference priority (0x0C69) 5628 * Return: 0 on success or negative value on failure. 5629 */ 5630 int 5631 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5632 u8 *ref_prio) 5633 { 5634 struct ice_aqc_get_cgu_ref_prio *cmd; 5635 struct libie_aq_desc desc; 5636 int status; 5637 5638 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5639 cmd = libie_aq_raw(&desc); 5640 cmd->dpll_num = dpll_num; 5641 cmd->ref_idx = ref_idx; 5642 5643 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5644 if (!status) 5645 *ref_prio = cmd->ref_priority; 5646 5647 return status; 5648 } 5649 5650 /** 5651 * ice_aq_get_cgu_info - get cgu info 5652 * @hw: pointer to the HW struct 5653 * @cgu_id: CGU ID 5654 * @cgu_cfg_ver: CGU config version 5655 * @cgu_fw_ver: CGU firmware version 5656 * 5657 * Get CGU info (0x0C6A) 5658 * Return: 0 on success or negative value on failure. 5659 */ 5660 int 5661 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5662 u32 *cgu_fw_ver) 5663 { 5664 struct ice_aqc_get_cgu_info *cmd; 5665 struct libie_aq_desc desc; 5666 int status; 5667 5668 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5669 cmd = libie_aq_raw(&desc); 5670 5671 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5672 if (!status) { 5673 *cgu_id = le32_to_cpu(cmd->cgu_id); 5674 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5675 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5676 } 5677 5678 return status; 5679 } 5680 5681 /** 5682 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5683 * @hw: pointer to the HW struct 5684 * @phy_output: PHY reference clock output pin 5685 * @enable: GPIO state to be applied 5686 * @freq: PHY output frequency 5687 * 5688 * Set phy recovered clock as reference (0x0630) 5689 * Return: 0 on success or negative value on failure. 5690 */ 5691 int 5692 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5693 u32 *freq) 5694 { 5695 struct ice_aqc_set_phy_rec_clk_out *cmd; 5696 struct libie_aq_desc desc; 5697 int status; 5698 5699 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5700 cmd = libie_aq_raw(&desc); 5701 cmd->phy_output = phy_output; 5702 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5703 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5704 cmd->freq = cpu_to_le32(*freq); 5705 5706 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5707 if (!status) 5708 *freq = le32_to_cpu(cmd->freq); 5709 5710 return status; 5711 } 5712 5713 /** 5714 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5715 * @hw: pointer to the HW struct 5716 * @phy_output: PHY reference clock output pin 5717 * @port_num: Port number 5718 * @flags: PHY flags 5719 * @node_handle: PHY output frequency 5720 * 5721 * Get PHY recovered clock output info (0x0631) 5722 * Return: 0 on success or negative value on failure. 5723 */ 5724 int 5725 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5726 u8 *flags, u16 *node_handle) 5727 { 5728 struct ice_aqc_get_phy_rec_clk_out *cmd; 5729 struct libie_aq_desc desc; 5730 int status; 5731 5732 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5733 cmd = libie_aq_raw(&desc); 5734 cmd->phy_output = *phy_output; 5735 5736 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5737 if (!status) { 5738 *phy_output = cmd->phy_output; 5739 if (port_num) 5740 *port_num = cmd->port_num; 5741 if (flags) 5742 *flags = cmd->flags; 5743 if (node_handle) 5744 *node_handle = le16_to_cpu(cmd->node_handle); 5745 } 5746 5747 return status; 5748 } 5749 5750 /** 5751 * ice_aq_get_sensor_reading 5752 * @hw: pointer to the HW struct 5753 * @data: pointer to data to be read from the sensor 5754 * 5755 * Get sensor reading (0x0632) 5756 */ 5757 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5758 struct ice_aqc_get_sensor_reading_resp *data) 5759 { 5760 struct ice_aqc_get_sensor_reading *cmd; 5761 struct libie_aq_desc desc; 5762 int status; 5763 5764 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5765 cmd = libie_aq_raw(&desc); 5766 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5767 #define ICE_INTERNAL_TEMP_SENSOR 0 5768 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5769 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5770 5771 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5772 if (!status) 5773 memcpy(data, &desc.params.raw, 5774 sizeof(*data)); 5775 5776 return status; 5777 } 5778 5779 /** 5780 * ice_replay_pre_init - replay pre initialization 5781 * @hw: pointer to the HW struct 5782 * 5783 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5784 */ 5785 static int ice_replay_pre_init(struct ice_hw *hw) 5786 { 5787 struct ice_switch_info *sw = hw->switch_info; 5788 u8 i; 5789 5790 /* Delete old entries from replay filter list head if there is any */ 5791 ice_rm_all_sw_replay_rule_info(hw); 5792 /* In start of replay, move entries into replay_rules list, it 5793 * will allow adding rules entries back to filt_rules list, 5794 * which is operational list. 5795 */ 5796 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5797 list_replace_init(&sw->recp_list[i].filt_rules, 5798 &sw->recp_list[i].filt_replay_rules); 5799 ice_sched_replay_agg_vsi_preinit(hw); 5800 5801 return 0; 5802 } 5803 5804 /** 5805 * ice_replay_vsi - replay VSI configuration 5806 * @hw: pointer to the HW struct 5807 * @vsi_handle: driver VSI handle 5808 * 5809 * Restore all VSI configuration after reset. It is required to call this 5810 * function with main VSI first. 5811 */ 5812 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5813 { 5814 int status; 5815 5816 if (!ice_is_vsi_valid(hw, vsi_handle)) 5817 return -EINVAL; 5818 5819 /* Replay pre-initialization if there is any */ 5820 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5821 status = ice_replay_pre_init(hw); 5822 if (status) 5823 return status; 5824 } 5825 /* Replay per VSI all RSS configurations */ 5826 status = ice_replay_rss_cfg(hw, vsi_handle); 5827 if (status) 5828 return status; 5829 /* Replay per VSI all filters */ 5830 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5831 if (!status) 5832 status = ice_replay_vsi_agg(hw, vsi_handle); 5833 return status; 5834 } 5835 5836 /** 5837 * ice_replay_post - post replay configuration cleanup 5838 * @hw: pointer to the HW struct 5839 * 5840 * Post replay cleanup. 5841 */ 5842 void ice_replay_post(struct ice_hw *hw) 5843 { 5844 /* Delete old entries from replay filter list head */ 5845 ice_rm_all_sw_replay_rule_info(hw); 5846 ice_sched_replay_agg(hw); 5847 } 5848 5849 /** 5850 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5851 * @hw: ptr to the hardware info 5852 * @reg: offset of 64 bit HW register to read from 5853 * @prev_stat_loaded: bool to specify if previous stats are loaded 5854 * @prev_stat: ptr to previous loaded stat value 5855 * @cur_stat: ptr to current stat value 5856 */ 5857 void 5858 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5859 u64 *prev_stat, u64 *cur_stat) 5860 { 5861 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5862 5863 /* device stats are not reset at PFR, they likely will not be zeroed 5864 * when the driver starts. Thus, save the value from the first read 5865 * without adding to the statistic value so that we report stats which 5866 * count up from zero. 5867 */ 5868 if (!prev_stat_loaded) { 5869 *prev_stat = new_data; 5870 return; 5871 } 5872 5873 /* Calculate the difference between the new and old values, and then 5874 * add it to the software stat value. 5875 */ 5876 if (new_data >= *prev_stat) 5877 *cur_stat += new_data - *prev_stat; 5878 else 5879 /* to manage the potential roll-over */ 5880 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5881 5882 /* Update the previously stored value to prepare for next read */ 5883 *prev_stat = new_data; 5884 } 5885 5886 /** 5887 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5888 * @hw: ptr to the hardware info 5889 * @reg: offset of HW register to read from 5890 * @prev_stat_loaded: bool to specify if previous stats are loaded 5891 * @prev_stat: ptr to previous loaded stat value 5892 * @cur_stat: ptr to current stat value 5893 */ 5894 void 5895 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5896 u64 *prev_stat, u64 *cur_stat) 5897 { 5898 u32 new_data; 5899 5900 new_data = rd32(hw, reg); 5901 5902 /* device stats are not reset at PFR, they likely will not be zeroed 5903 * when the driver starts. Thus, save the value from the first read 5904 * without adding to the statistic value so that we report stats which 5905 * count up from zero. 5906 */ 5907 if (!prev_stat_loaded) { 5908 *prev_stat = new_data; 5909 return; 5910 } 5911 5912 /* Calculate the difference between the new and old values, and then 5913 * add it to the software stat value. 5914 */ 5915 if (new_data >= *prev_stat) 5916 *cur_stat += new_data - *prev_stat; 5917 else 5918 /* to manage the potential roll-over */ 5919 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5920 5921 /* Update the previously stored value to prepare for next read */ 5922 *prev_stat = new_data; 5923 } 5924 5925 /** 5926 * ice_sched_query_elem - query element information from HW 5927 * @hw: pointer to the HW struct 5928 * @node_teid: node TEID to be queried 5929 * @buf: buffer to element information 5930 * 5931 * This function queries HW element information 5932 */ 5933 int 5934 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5935 struct ice_aqc_txsched_elem_data *buf) 5936 { 5937 u16 buf_size, num_elem_ret = 0; 5938 int status; 5939 5940 buf_size = sizeof(*buf); 5941 memset(buf, 0, buf_size); 5942 buf->node_teid = cpu_to_le32(node_teid); 5943 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5944 NULL); 5945 if (status || num_elem_ret != 1) 5946 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5947 return status; 5948 } 5949 5950 /** 5951 * ice_aq_read_i2c 5952 * @hw: pointer to the hw struct 5953 * @topo_addr: topology address for a device to communicate with 5954 * @bus_addr: 7-bit I2C bus address 5955 * @addr: I2C memory address (I2C offset) with up to 16 bits 5956 * @params: I2C parameters: bit [7] - Repeated start, 5957 * bits [6:5] data offset size, 5958 * bit [4] - I2C address type, 5959 * bits [3:0] - data size to read (0-16 bytes) 5960 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5961 * @cd: pointer to command details structure or NULL 5962 * 5963 * Read I2C (0x06E2) 5964 */ 5965 int 5966 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5967 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5968 struct ice_sq_cd *cd) 5969 { 5970 struct libie_aq_desc desc = { 0 }; 5971 struct ice_aqc_i2c *cmd; 5972 u8 data_size; 5973 int status; 5974 5975 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5976 cmd = libie_aq_raw(&desc); 5977 5978 if (!data) 5979 return -EINVAL; 5980 5981 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5982 5983 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5984 cmd->topo_addr = topo_addr; 5985 cmd->i2c_params = params; 5986 cmd->i2c_addr = addr; 5987 5988 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5989 if (!status) { 5990 struct ice_aqc_read_i2c_resp *resp; 5991 u8 i; 5992 5993 resp = libie_aq_raw(&desc); 5994 for (i = 0; i < data_size; i++) { 5995 *data = resp->i2c_data[i]; 5996 data++; 5997 } 5998 } 5999 6000 return status; 6001 } 6002 6003 /** 6004 * ice_aq_write_i2c 6005 * @hw: pointer to the hw struct 6006 * @topo_addr: topology address for a device to communicate with 6007 * @bus_addr: 7-bit I2C bus address 6008 * @addr: I2C memory address (I2C offset) with up to 16 bits 6009 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 6010 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 6011 * @cd: pointer to command details structure or NULL 6012 * 6013 * Write I2C (0x06E3) 6014 * 6015 * * Return: 6016 * * 0 - Successful write to the i2c device 6017 * * -EINVAL - Data size greater than 4 bytes 6018 * * -EIO - FW error 6019 */ 6020 int 6021 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6022 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6023 struct ice_sq_cd *cd) 6024 { 6025 struct libie_aq_desc desc = { 0 }; 6026 struct ice_aqc_i2c *cmd; 6027 u8 data_size; 6028 6029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6030 cmd = libie_aq_raw(&desc); 6031 6032 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6033 6034 /* data_size limited to 4 */ 6035 if (data_size > 4) 6036 return -EINVAL; 6037 6038 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6039 cmd->topo_addr = topo_addr; 6040 cmd->i2c_params = params; 6041 cmd->i2c_addr = addr; 6042 6043 memcpy(cmd->i2c_data, data, data_size); 6044 6045 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6046 } 6047 6048 /** 6049 * ice_get_pca9575_handle - find and return the PCA9575 controller 6050 * @hw: pointer to the hw struct 6051 * @pca9575_handle: GPIO controller's handle 6052 * 6053 * Find and return the GPIO controller's handle in the netlist. 6054 * When found - the value will be cached in the hw structure and following calls 6055 * will return cached value. 6056 * 6057 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6058 */ 6059 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6060 { 6061 struct ice_aqc_get_link_topo *cmd; 6062 struct libie_aq_desc desc; 6063 int err; 6064 u8 idx; 6065 6066 /* If handle was read previously return cached value */ 6067 if (hw->io_expander_handle) { 6068 *pca9575_handle = hw->io_expander_handle; 6069 return 0; 6070 } 6071 6072 #define SW_PCA9575_SFP_TOPO_IDX 2 6073 #define SW_PCA9575_QSFP_TOPO_IDX 1 6074 6075 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6076 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6077 idx = SW_PCA9575_SFP_TOPO_IDX; 6078 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6079 idx = SW_PCA9575_QSFP_TOPO_IDX; 6080 else 6081 return -ENXIO; 6082 6083 /* If handle was not detected read it from the netlist */ 6084 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6085 cmd = libie_aq_raw(&desc); 6086 cmd->addr.topo_params.node_type_ctx = 6087 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6088 cmd->addr.topo_params.index = idx; 6089 6090 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6091 if (err) 6092 return -ENXIO; 6093 6094 /* Verify if we found the right IO expander type */ 6095 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6096 return -ENXIO; 6097 6098 /* If present save the handle and return it */ 6099 hw->io_expander_handle = 6100 le16_to_cpu(cmd->addr.handle); 6101 *pca9575_handle = hw->io_expander_handle; 6102 6103 return 0; 6104 } 6105 6106 /** 6107 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6108 * @hw: pointer to the hw struct 6109 * @offset: GPIO controller register offset 6110 * @data: pointer to data to be read from the GPIO controller 6111 * 6112 * Return: 0 on success, negative error code otherwise. 6113 */ 6114 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6115 { 6116 struct ice_aqc_link_topo_addr link_topo; 6117 __le16 addr; 6118 u16 handle; 6119 int err; 6120 6121 memset(&link_topo, 0, sizeof(link_topo)); 6122 6123 err = ice_get_pca9575_handle(hw, &handle); 6124 if (err) 6125 return err; 6126 6127 link_topo.handle = cpu_to_le16(handle); 6128 link_topo.topo_params.node_type_ctx = 6129 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6130 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6131 6132 addr = cpu_to_le16((u16)offset); 6133 6134 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6135 } 6136 6137 /** 6138 * ice_aq_set_gpio 6139 * @hw: pointer to the hw struct 6140 * @gpio_ctrl_handle: GPIO controller node handle 6141 * @pin_idx: IO Number of the GPIO that needs to be set 6142 * @value: SW provide IO value to set in the LSB 6143 * @cd: pointer to command details structure or NULL 6144 * 6145 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6146 */ 6147 int 6148 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6149 struct ice_sq_cd *cd) 6150 { 6151 struct libie_aq_desc desc; 6152 struct ice_aqc_gpio *cmd; 6153 6154 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6155 cmd = libie_aq_raw(&desc); 6156 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6157 cmd->gpio_num = pin_idx; 6158 cmd->gpio_val = value ? 1 : 0; 6159 6160 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6161 } 6162 6163 /** 6164 * ice_aq_get_gpio 6165 * @hw: pointer to the hw struct 6166 * @gpio_ctrl_handle: GPIO controller node handle 6167 * @pin_idx: IO Number of the GPIO that needs to be set 6168 * @value: IO value read 6169 * @cd: pointer to command details structure or NULL 6170 * 6171 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6172 * the topology 6173 */ 6174 int 6175 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6176 bool *value, struct ice_sq_cd *cd) 6177 { 6178 struct libie_aq_desc desc; 6179 struct ice_aqc_gpio *cmd; 6180 int status; 6181 6182 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6183 cmd = libie_aq_raw(&desc); 6184 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6185 cmd->gpio_num = pin_idx; 6186 6187 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6188 if (status) 6189 return status; 6190 6191 *value = !!cmd->gpio_val; 6192 return 0; 6193 } 6194 6195 /** 6196 * ice_is_fw_api_min_ver 6197 * @hw: pointer to the hardware structure 6198 * @maj: major version 6199 * @min: minor version 6200 * @patch: patch version 6201 * 6202 * Checks if the firmware API is minimum version 6203 */ 6204 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6205 { 6206 if (hw->api_maj_ver == maj) { 6207 if (hw->api_min_ver > min) 6208 return true; 6209 if (hw->api_min_ver == min && hw->api_patch >= patch) 6210 return true; 6211 } else if (hw->api_maj_ver > maj) { 6212 return true; 6213 } 6214 6215 return false; 6216 } 6217 6218 /** 6219 * ice_fw_supports_link_override 6220 * @hw: pointer to the hardware structure 6221 * 6222 * Checks if the firmware supports link override 6223 */ 6224 bool ice_fw_supports_link_override(struct ice_hw *hw) 6225 { 6226 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6227 ICE_FW_API_LINK_OVERRIDE_MIN, 6228 ICE_FW_API_LINK_OVERRIDE_PATCH); 6229 } 6230 6231 /** 6232 * ice_get_link_default_override 6233 * @ldo: pointer to the link default override struct 6234 * @pi: pointer to the port info struct 6235 * 6236 * Gets the link default override for a port 6237 */ 6238 int 6239 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6240 struct ice_port_info *pi) 6241 { 6242 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6243 struct ice_hw *hw = pi->hw; 6244 int status; 6245 6246 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6247 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6248 if (status) { 6249 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6250 return status; 6251 } 6252 6253 /* Each port has its own config; calculate for our port */ 6254 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6255 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6256 6257 /* link options first */ 6258 status = ice_read_sr_word(hw, tlv_start, &buf); 6259 if (status) { 6260 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6261 return status; 6262 } 6263 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6264 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6265 ICE_LINK_OVERRIDE_PHY_CFG_S; 6266 6267 /* link PHY config */ 6268 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6269 status = ice_read_sr_word(hw, offset, &buf); 6270 if (status) { 6271 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6272 return status; 6273 } 6274 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6275 6276 /* PHY types low */ 6277 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6278 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6279 status = ice_read_sr_word(hw, (offset + i), &buf); 6280 if (status) { 6281 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6282 return status; 6283 } 6284 /* shift 16 bits at a time to fill 64 bits */ 6285 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6286 } 6287 6288 /* PHY types high */ 6289 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6290 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6291 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6292 status = ice_read_sr_word(hw, (offset + i), &buf); 6293 if (status) { 6294 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6295 return status; 6296 } 6297 /* shift 16 bits at a time to fill 64 bits */ 6298 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6299 } 6300 6301 return status; 6302 } 6303 6304 /** 6305 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6306 * @caps: get PHY capability data 6307 */ 6308 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6309 { 6310 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6311 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6312 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6313 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6314 return true; 6315 6316 return false; 6317 } 6318 6319 /** 6320 * ice_is_fw_health_report_supported - checks if firmware supports health events 6321 * @hw: pointer to the hardware structure 6322 * 6323 * Return: true if firmware supports health status reports, 6324 * false otherwise 6325 */ 6326 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6327 { 6328 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6329 ICE_FW_API_HEALTH_REPORT_MIN, 6330 ICE_FW_API_HEALTH_REPORT_PATCH); 6331 } 6332 6333 /** 6334 * ice_aq_set_health_status_cfg - Configure FW health events 6335 * @hw: pointer to the HW struct 6336 * @event_source: type of diagnostic events to enable 6337 * 6338 * Configure the health status event types that the firmware will send to this 6339 * PF. The supported event types are: PF-specific, all PFs, and global. 6340 * 6341 * Return: 0 on success, negative error code otherwise. 6342 */ 6343 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6344 { 6345 struct ice_aqc_set_health_status_cfg *cmd; 6346 struct libie_aq_desc desc; 6347 6348 cmd = libie_aq_raw(&desc); 6349 6350 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6351 6352 cmd->event_source = event_source; 6353 6354 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6355 } 6356 6357 /** 6358 * ice_aq_set_lldp_mib - Set the LLDP MIB 6359 * @hw: pointer to the HW struct 6360 * @mib_type: Local, Remote or both Local and Remote MIBs 6361 * @buf: pointer to the caller-supplied buffer to store the MIB block 6362 * @buf_size: size of the buffer (in bytes) 6363 * @cd: pointer to command details structure or NULL 6364 * 6365 * Set the LLDP MIB. (0x0A08) 6366 */ 6367 int 6368 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6369 struct ice_sq_cd *cd) 6370 { 6371 struct ice_aqc_lldp_set_local_mib *cmd; 6372 struct libie_aq_desc desc; 6373 6374 cmd = libie_aq_raw(&desc); 6375 6376 if (buf_size == 0 || !buf) 6377 return -EINVAL; 6378 6379 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6380 6381 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6382 desc.datalen = cpu_to_le16(buf_size); 6383 6384 cmd->type = mib_type; 6385 cmd->length = cpu_to_le16(buf_size); 6386 6387 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6388 } 6389 6390 /** 6391 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6392 * @hw: pointer to HW struct 6393 */ 6394 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6395 { 6396 if (hw->mac_type != ICE_MAC_E810) 6397 return false; 6398 6399 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6400 ICE_FW_API_LLDP_FLTR_MIN, 6401 ICE_FW_API_LLDP_FLTR_PATCH); 6402 } 6403 6404 /** 6405 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6406 * @hw: pointer to HW struct 6407 * @vsi: VSI to add the filter to 6408 * @add: boolean for if adding or removing a filter 6409 * 6410 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6411 * with this HW or VSI, otherwise an error corresponding to 6412 * the AQ transaction result. 6413 */ 6414 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6415 { 6416 struct ice_aqc_lldp_filter_ctrl *cmd; 6417 struct libie_aq_desc desc; 6418 6419 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6420 return -EOPNOTSUPP; 6421 6422 cmd = libie_aq_raw(&desc); 6423 6424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6425 6426 if (add) 6427 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6428 else 6429 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6430 6431 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6432 6433 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6434 } 6435 6436 /** 6437 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6438 * @hw: pointer to HW struct 6439 */ 6440 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6441 { 6442 struct libie_aq_desc desc; 6443 6444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6445 6446 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6447 } 6448 6449 /** 6450 * ice_fw_supports_report_dflt_cfg 6451 * @hw: pointer to the hardware structure 6452 * 6453 * Checks if the firmware supports report default configuration 6454 */ 6455 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6456 { 6457 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6458 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6459 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6460 } 6461 6462 /* each of the indexes into the following array match the speed of a return 6463 * value from the list of AQ returned speeds like the range: 6464 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6465 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6466 * array. The array is defined as 15 elements long because the link_speed 6467 * returned by the firmware is a 16 bit * value, but is indexed 6468 * by [fls(speed) - 1] 6469 */ 6470 static const u32 ice_aq_to_link_speed[] = { 6471 SPEED_10, /* BIT(0) */ 6472 SPEED_100, 6473 SPEED_1000, 6474 SPEED_2500, 6475 SPEED_5000, 6476 SPEED_10000, 6477 SPEED_20000, 6478 SPEED_25000, 6479 SPEED_40000, 6480 SPEED_50000, 6481 SPEED_100000, /* BIT(10) */ 6482 SPEED_200000, 6483 }; 6484 6485 /** 6486 * ice_get_link_speed - get integer speed from table 6487 * @index: array index from fls(aq speed) - 1 6488 * 6489 * Returns: u32 value containing integer speed 6490 */ 6491 u32 ice_get_link_speed(u16 index) 6492 { 6493 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6494 return 0; 6495 6496 return ice_aq_to_link_speed[index]; 6497 } 6498 6499 /** 6500 * ice_read_cgu_reg - Read a CGU register 6501 * @hw: Pointer to the HW struct 6502 * @addr: Register address to read 6503 * @val: Storage for register value read 6504 * 6505 * Read the contents of a register of the Clock Generation Unit. Only 6506 * applicable to E82X devices. 6507 * 6508 * Return: 0 on success, other error codes when failed to read from CGU. 6509 */ 6510 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6511 { 6512 struct ice_sbq_msg_input cgu_msg = { 6513 .opcode = ice_sbq_msg_rd, 6514 .dest_dev = ice_sbq_dev_cgu, 6515 .msg_addr_low = addr 6516 }; 6517 int err; 6518 6519 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6520 if (err) { 6521 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6522 addr, err); 6523 return err; 6524 } 6525 6526 *val = cgu_msg.data; 6527 6528 return 0; 6529 } 6530 6531 /** 6532 * ice_write_cgu_reg - Write a CGU register 6533 * @hw: Pointer to the HW struct 6534 * @addr: Register address to write 6535 * @val: Value to write into the register 6536 * 6537 * Write the specified value to a register of the Clock Generation Unit. Only 6538 * applicable to E82X devices. 6539 * 6540 * Return: 0 on success, other error codes when failed to write to CGU. 6541 */ 6542 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6543 { 6544 struct ice_sbq_msg_input cgu_msg = { 6545 .opcode = ice_sbq_msg_wr, 6546 .dest_dev = ice_sbq_dev_cgu, 6547 .msg_addr_low = addr, 6548 .data = val 6549 }; 6550 int err; 6551 6552 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6553 if (err) 6554 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6555 addr, err); 6556 6557 return err; 6558 } 6559