1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include <net/xdp_sock_drv.h> 5 #include "ice_base.h" 6 #include "ice_lib.h" 7 #include "ice_dcb_lib.h" 8 #include "ice_sriov.h" 9 10 /** 11 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 12 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 13 * 14 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 15 */ 16 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 17 { 18 unsigned int offset, i; 19 20 mutex_lock(qs_cfg->qs_mutex); 21 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 22 0, qs_cfg->q_count, 0); 23 if (offset >= qs_cfg->pf_map_size) { 24 mutex_unlock(qs_cfg->qs_mutex); 25 return -ENOMEM; 26 } 27 28 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 29 for (i = 0; i < qs_cfg->q_count; i++) 30 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset); 31 mutex_unlock(qs_cfg->qs_mutex); 32 33 return 0; 34 } 35 36 /** 37 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 38 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 39 * 40 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 41 */ 42 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 43 { 44 unsigned int i, index = 0; 45 46 mutex_lock(qs_cfg->qs_mutex); 47 for (i = 0; i < qs_cfg->q_count; i++) { 48 index = find_next_zero_bit(qs_cfg->pf_map, 49 qs_cfg->pf_map_size, index); 50 if (index >= qs_cfg->pf_map_size) 51 goto err_scatter; 52 set_bit(index, qs_cfg->pf_map); 53 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index; 54 } 55 mutex_unlock(qs_cfg->qs_mutex); 56 57 return 0; 58 err_scatter: 59 for (index = 0; index < i; index++) { 60 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 61 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 62 } 63 mutex_unlock(qs_cfg->qs_mutex); 64 65 return -ENOMEM; 66 } 67 68 /** 69 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 70 * @pf: the PF being configured 71 * @pf_q: the PF queue 72 * @ena: enable or disable state of the queue 73 * 74 * This routine will wait for the given Rx queue of the PF to reach the 75 * enabled or disabled state. 76 * Returns -ETIMEDOUT in case of failing to reach the requested state after 77 * multiple retries; else will return 0 in case of success. 78 */ 79 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 80 { 81 int i; 82 83 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 84 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 85 QRX_CTRL_QENA_STAT_M)) 86 return 0; 87 88 usleep_range(20, 40); 89 } 90 91 return -ETIMEDOUT; 92 } 93 94 /** 95 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 96 * @vsi: the VSI being configured 97 * @v_idx: index of the vector in the VSI struct 98 * 99 * We allocate one q_vector and set default value for ITR setting associated 100 * with this q_vector. If allocation fails we return -ENOMEM. 101 */ 102 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx) 103 { 104 struct ice_pf *pf = vsi->back; 105 struct ice_q_vector *q_vector; 106 int err; 107 108 /* allocate q_vector */ 109 q_vector = kzalloc(sizeof(*q_vector), GFP_KERNEL); 110 if (!q_vector) 111 return -ENOMEM; 112 113 q_vector->vsi = vsi; 114 q_vector->v_idx = v_idx; 115 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 116 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 117 q_vector->tx.itr_mode = ITR_DYNAMIC; 118 q_vector->rx.itr_mode = ITR_DYNAMIC; 119 q_vector->tx.type = ICE_TX_CONTAINER; 120 q_vector->rx.type = ICE_RX_CONTAINER; 121 q_vector->irq.index = -ENOENT; 122 123 if (vsi->type == ICE_VSI_VF) { 124 ice_calc_vf_reg_idx(vsi->vf, q_vector); 125 goto out; 126 } else if (vsi->type == ICE_VSI_CTRL && vsi->vf) { 127 struct ice_vsi *ctrl_vsi = ice_get_vf_ctrl_vsi(pf, vsi); 128 129 if (ctrl_vsi) { 130 if (unlikely(!ctrl_vsi->q_vectors)) { 131 err = -ENOENT; 132 goto err_free_q_vector; 133 } 134 135 q_vector->irq = ctrl_vsi->q_vectors[0]->irq; 136 goto skip_alloc; 137 } 138 } 139 140 q_vector->irq = ice_alloc_irq(pf, vsi->irq_dyn_alloc); 141 if (q_vector->irq.index < 0) { 142 err = -ENOMEM; 143 goto err_free_q_vector; 144 } 145 146 skip_alloc: 147 q_vector->reg_idx = q_vector->irq.index; 148 q_vector->vf_reg_idx = q_vector->irq.index; 149 150 /* only set affinity_mask if the CPU is online */ 151 if (cpu_online(v_idx)) 152 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 153 154 /* This will not be called in the driver load path because the netdev 155 * will not be created yet. All other cases with register the NAPI 156 * handler here (i.e. resume, reset/rebuild, etc.) 157 */ 158 if (vsi->netdev) 159 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll); 160 161 out: 162 /* tie q_vector and VSI together */ 163 vsi->q_vectors[v_idx] = q_vector; 164 165 return 0; 166 167 err_free_q_vector: 168 kfree(q_vector); 169 170 return err; 171 } 172 173 /** 174 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 175 * @vsi: VSI having the memory freed 176 * @v_idx: index of the vector to be freed 177 */ 178 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 179 { 180 struct ice_q_vector *q_vector; 181 struct ice_pf *pf = vsi->back; 182 struct ice_tx_ring *tx_ring; 183 struct ice_rx_ring *rx_ring; 184 struct device *dev; 185 186 dev = ice_pf_to_dev(pf); 187 if (!vsi->q_vectors[v_idx]) { 188 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 189 return; 190 } 191 q_vector = vsi->q_vectors[v_idx]; 192 193 ice_for_each_tx_ring(tx_ring, vsi->q_vectors[v_idx]->tx) 194 tx_ring->q_vector = NULL; 195 196 ice_for_each_rx_ring(rx_ring, vsi->q_vectors[v_idx]->rx) 197 rx_ring->q_vector = NULL; 198 199 /* only VSI with an associated netdev is set up with NAPI */ 200 if (vsi->netdev) 201 netif_napi_del(&q_vector->napi); 202 203 /* release MSIX interrupt if q_vector had interrupt allocated */ 204 if (q_vector->irq.index < 0) 205 goto free_q_vector; 206 207 /* only free last VF ctrl vsi interrupt */ 208 if (vsi->type == ICE_VSI_CTRL && vsi->vf && 209 ice_get_vf_ctrl_vsi(pf, vsi)) 210 goto free_q_vector; 211 212 ice_free_irq(pf, q_vector->irq); 213 214 free_q_vector: 215 kfree(q_vector); 216 vsi->q_vectors[v_idx] = NULL; 217 } 218 219 /** 220 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 221 * @hw: board specific structure 222 */ 223 static void ice_cfg_itr_gran(struct ice_hw *hw) 224 { 225 u32 regval = rd32(hw, GLINT_CTL); 226 227 /* no need to update global register if ITR gran is already set */ 228 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 229 (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) && 230 (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) && 231 (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) && 232 (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US)) 233 return; 234 235 regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) | 236 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) | 237 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) | 238 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US); 239 wr32(hw, GLINT_CTL, regval); 240 } 241 242 /** 243 * ice_calc_txq_handle - calculate the queue handle 244 * @vsi: VSI that ring belongs to 245 * @ring: ring to get the absolute queue index 246 * @tc: traffic class number 247 */ 248 static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc) 249 { 250 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n"); 251 252 if (ring->ch) 253 return ring->q_index - ring->ch->base_q; 254 255 /* Idea here for calculation is that we subtract the number of queue 256 * count from TC that ring belongs to from it's absolute queue index 257 * and as a result we get the queue's index within TC. 258 */ 259 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 260 } 261 262 /** 263 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring 264 * @ring: The Tx ring to configure 265 * 266 * This enables/disables XPS for a given Tx descriptor ring 267 * based on the TCs enabled for the VSI that ring belongs to. 268 */ 269 static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring) 270 { 271 if (!ring->q_vector || !ring->netdev) 272 return; 273 274 /* We only initialize XPS once, so as not to overwrite user settings */ 275 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state)) 276 return; 277 278 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask, 279 ring->q_index); 280 } 281 282 /** 283 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 284 * @ring: The Tx ring to configure 285 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 286 * @pf_q: queue index in the PF space 287 * 288 * Configure the Tx descriptor ring in TLAN context. 289 */ 290 static void 291 ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 292 { 293 struct ice_vsi *vsi = ring->vsi; 294 struct ice_hw *hw = &vsi->back->hw; 295 296 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 297 298 tlan_ctx->port_num = vsi->port_info->lport; 299 300 /* Transmit Queue Length */ 301 tlan_ctx->qlen = ring->count; 302 303 ice_set_cgd_num(tlan_ctx, ring->dcb_tc); 304 305 /* PF number */ 306 tlan_ctx->pf_num = hw->pf_id; 307 308 /* queue belongs to a specific VSI type 309 * VF / VM index should be programmed per vmvf_type setting: 310 * for vmvf_type = VF, it is VF number between 0-256 311 * for vmvf_type = VM, it is VM number between 0-767 312 * for PF or EMP this field should be set to zero 313 */ 314 switch (vsi->type) { 315 case ICE_VSI_LB: 316 case ICE_VSI_CTRL: 317 case ICE_VSI_PF: 318 if (ring->ch) 319 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ; 320 else 321 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 322 break; 323 case ICE_VSI_VF: 324 /* Firmware expects vmvf_num to be absolute VF ID */ 325 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf->vf_id; 326 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 327 break; 328 default: 329 return; 330 } 331 332 /* make sure the context is associated with the right VSI */ 333 if (ring->ch) 334 tlan_ctx->src_vsi = ring->ch->vsi_num; 335 else 336 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 337 338 /* Restrict Tx timestamps to the PF VSI */ 339 switch (vsi->type) { 340 case ICE_VSI_PF: 341 tlan_ctx->tsyn_ena = 1; 342 break; 343 default: 344 break; 345 } 346 347 tlan_ctx->tso_ena = ICE_TX_LEGACY; 348 tlan_ctx->tso_qnum = pf_q; 349 350 /* Legacy or Advanced Host Interface: 351 * 0: Advanced Host Interface 352 * 1: Legacy Host Interface 353 */ 354 tlan_ctx->legacy_int = ICE_TX_LEGACY; 355 } 356 357 /** 358 * ice_rx_offset - Return expected offset into page to access data 359 * @rx_ring: Ring we are requesting offset of 360 * 361 * Returns the offset value for ring into the data buffer. 362 */ 363 static unsigned int ice_rx_offset(struct ice_rx_ring *rx_ring) 364 { 365 if (ice_ring_uses_build_skb(rx_ring)) 366 return ICE_SKB_PAD; 367 return 0; 368 } 369 370 /** 371 * ice_setup_rx_ctx - Configure a receive ring context 372 * @ring: The Rx ring to configure 373 * 374 * Configure the Rx descriptor ring in RLAN context. 375 */ 376 static int ice_setup_rx_ctx(struct ice_rx_ring *ring) 377 { 378 struct ice_vsi *vsi = ring->vsi; 379 u32 rxdid = ICE_RXDID_FLEX_NIC; 380 struct ice_rlan_ctx rlan_ctx; 381 struct ice_hw *hw; 382 u16 pf_q; 383 int err; 384 385 hw = &vsi->back->hw; 386 387 /* what is Rx queue number in global space of 2K Rx queues */ 388 pf_q = vsi->rxq_map[ring->q_index]; 389 390 /* clear the context structure first */ 391 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 392 393 /* Receive Queue Base Address. 394 * Indicates the starting address of the descriptor queue defined in 395 * 128 Byte units. 396 */ 397 rlan_ctx.base = ring->dma >> ICE_RLAN_BASE_S; 398 399 rlan_ctx.qlen = ring->count; 400 401 /* Receive Packet Data Buffer Size. 402 * The Packet Data Buffer Size is defined in 128 byte units. 403 */ 404 rlan_ctx.dbuf = DIV_ROUND_UP(ring->rx_buf_len, 405 BIT_ULL(ICE_RLAN_CTX_DBUF_S)); 406 407 /* use 32 byte descriptors */ 408 rlan_ctx.dsize = 1; 409 410 /* Strip the Ethernet CRC bytes before the packet is posted to host 411 * memory. 412 */ 413 rlan_ctx.crcstrip = !(ring->flags & ICE_RX_FLAGS_CRC_STRIP_DIS); 414 415 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor 416 * and it needs to remain 1 for non-DVM capable configurations to not 417 * break backward compatibility for VF drivers. Setting this field to 0 418 * will cause the single/outer VLAN tag to be stripped to the L2TAG2_2ND 419 * field in the Rx descriptor. Setting it to 1 allows the VLAN tag to 420 * be stripped in L2TAG1 of the Rx descriptor, which is where VFs will 421 * check for the tag 422 */ 423 if (ice_is_dvm_ena(hw)) 424 if (vsi->type == ICE_VSI_VF && 425 ice_vf_is_port_vlan_ena(vsi->vf)) 426 rlan_ctx.l2tsel = 1; 427 else 428 rlan_ctx.l2tsel = 0; 429 else 430 rlan_ctx.l2tsel = 1; 431 432 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 433 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 434 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 435 436 /* This controls whether VLAN is stripped from inner headers 437 * The VLAN in the inner L2 header is stripped to the receive 438 * descriptor if enabled by this flag. 439 */ 440 rlan_ctx.showiv = 0; 441 442 /* Max packet size for this queue - must not be set to a larger value 443 * than 5 x DBUF 444 */ 445 rlan_ctx.rxmax = min_t(u32, vsi->max_frame, 446 ICE_MAX_CHAINED_RX_BUFS * ring->rx_buf_len); 447 448 /* Rx queue threshold in units of 64 */ 449 rlan_ctx.lrxqthresh = 1; 450 451 /* PF acts as uplink for switchdev; set flex descriptor with src_vsi 452 * metadata and flags to allow redirecting to PR netdev 453 */ 454 if (ice_is_eswitch_mode_switchdev(vsi->back)) { 455 ring->flags |= ICE_RX_FLAGS_MULTIDEV; 456 rxdid = ICE_RXDID_FLEX_NIC_2; 457 } 458 459 /* Enable Flexible Descriptors in the queue context which 460 * allows this driver to select a specific receive descriptor format 461 * increasing context priority to pick up profile ID; default is 0x01; 462 * setting to 0x03 to ensure profile is programming if prev context is 463 * of same priority 464 */ 465 if (vsi->type != ICE_VSI_VF) 466 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true); 467 else 468 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3, 469 false); 470 471 /* Absolute queue number out of 2K needs to be passed */ 472 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 473 if (err) { 474 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 475 pf_q, err); 476 return -EIO; 477 } 478 479 if (vsi->type == ICE_VSI_VF) 480 return 0; 481 482 /* configure Rx buffer alignment */ 483 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 484 ice_clear_ring_build_skb_ena(ring); 485 else 486 ice_set_ring_build_skb_ena(ring); 487 488 ring->rx_offset = ice_rx_offset(ring); 489 490 /* init queue specific tail register */ 491 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 492 writel(0, ring->tail); 493 494 return 0; 495 } 496 497 static void ice_xsk_pool_fill_cb(struct ice_rx_ring *ring) 498 { 499 void *ctx_ptr = &ring->pkt_ctx; 500 struct xsk_cb_desc desc = {}; 501 502 XSK_CHECK_PRIV_TYPE(struct ice_xdp_buff); 503 desc.src = &ctx_ptr; 504 desc.off = offsetof(struct ice_xdp_buff, pkt_ctx) - 505 sizeof(struct xdp_buff); 506 desc.bytes = sizeof(ctx_ptr); 507 xsk_pool_fill_cb(ring->xsk_pool, &desc); 508 } 509 510 /** 511 * ice_get_frame_sz - calculate xdp_buff::frame_sz 512 * @rx_ring: the ring being configured 513 * 514 * Return frame size based on underlying PAGE_SIZE 515 */ 516 static unsigned int ice_get_frame_sz(struct ice_rx_ring *rx_ring) 517 { 518 unsigned int frame_sz; 519 520 #if (PAGE_SIZE >= 8192) 521 frame_sz = rx_ring->rx_buf_len; 522 #else 523 frame_sz = ice_rx_pg_size(rx_ring) / 2; 524 #endif 525 526 return frame_sz; 527 } 528 529 /** 530 * ice_vsi_cfg_rxq - Configure an Rx queue 531 * @ring: the ring being configured 532 * 533 * Return 0 on success and a negative value on error. 534 */ 535 static int ice_vsi_cfg_rxq(struct ice_rx_ring *ring) 536 { 537 struct device *dev = ice_pf_to_dev(ring->vsi->back); 538 u32 num_bufs = ICE_RX_DESC_UNUSED(ring); 539 int err; 540 541 ring->rx_buf_len = ring->vsi->rx_buf_len; 542 543 if (ring->vsi->type == ICE_VSI_PF) { 544 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) { 545 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 546 ring->q_index, 547 ring->q_vector->napi.napi_id, 548 ring->rx_buf_len); 549 if (err) 550 return err; 551 } 552 553 ice_rx_xsk_pool(ring); 554 if (ring->xsk_pool) { 555 xdp_rxq_info_unreg(&ring->xdp_rxq); 556 557 ring->rx_buf_len = 558 xsk_pool_get_rx_frame_size(ring->xsk_pool); 559 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 560 ring->q_index, 561 ring->q_vector->napi.napi_id, 562 ring->rx_buf_len); 563 if (err) 564 return err; 565 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 566 MEM_TYPE_XSK_BUFF_POOL, 567 NULL); 568 if (err) 569 return err; 570 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 571 ice_xsk_pool_fill_cb(ring); 572 573 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n", 574 ring->q_index); 575 } else { 576 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) { 577 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 578 ring->q_index, 579 ring->q_vector->napi.napi_id, 580 ring->rx_buf_len); 581 if (err) 582 return err; 583 } 584 585 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 586 MEM_TYPE_PAGE_SHARED, 587 NULL); 588 if (err) 589 return err; 590 } 591 } 592 593 xdp_init_buff(&ring->xdp, ice_get_frame_sz(ring), &ring->xdp_rxq); 594 ring->xdp.data = NULL; 595 ring->xdp_ext.pkt_ctx = &ring->pkt_ctx; 596 err = ice_setup_rx_ctx(ring); 597 if (err) { 598 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n", 599 ring->q_index, err); 600 return err; 601 } 602 603 if (ring->xsk_pool) { 604 bool ok; 605 606 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) { 607 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n", 608 num_bufs, ring->q_index); 609 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n"); 610 611 return 0; 612 } 613 614 ok = ice_alloc_rx_bufs_zc(ring, ring->xsk_pool, num_bufs); 615 if (!ok) { 616 u16 pf_q = ring->vsi->rxq_map[ring->q_index]; 617 618 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n", 619 ring->q_index, pf_q); 620 } 621 622 return 0; 623 } 624 625 ice_alloc_rx_bufs(ring, num_bufs); 626 627 return 0; 628 } 629 630 int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx) 631 { 632 if (q_idx >= vsi->num_rxq) 633 return -EINVAL; 634 635 return ice_vsi_cfg_rxq(vsi->rx_rings[q_idx]); 636 } 637 638 /** 639 * ice_vsi_cfg_frame_size - setup max frame size and Rx buffer length 640 * @vsi: VSI 641 */ 642 static void ice_vsi_cfg_frame_size(struct ice_vsi *vsi) 643 { 644 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) { 645 vsi->max_frame = ICE_MAX_FRAME_LEGACY_RX; 646 vsi->rx_buf_len = ICE_RXBUF_1664; 647 #if (PAGE_SIZE < 8192) 648 } else if (!ICE_2K_TOO_SMALL_WITH_PADDING && 649 (vsi->netdev->mtu <= ETH_DATA_LEN)) { 650 vsi->max_frame = ICE_RXBUF_1536 - NET_IP_ALIGN; 651 vsi->rx_buf_len = ICE_RXBUF_1536 - NET_IP_ALIGN; 652 #endif 653 } else { 654 vsi->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX; 655 vsi->rx_buf_len = ICE_RXBUF_3072; 656 } 657 } 658 659 /** 660 * ice_vsi_cfg_rxqs - Configure the VSI for Rx 661 * @vsi: the VSI being configured 662 * 663 * Return 0 on success and a negative value on error 664 * Configure the Rx VSI for operation. 665 */ 666 int ice_vsi_cfg_rxqs(struct ice_vsi *vsi) 667 { 668 u16 i; 669 670 if (vsi->type == ICE_VSI_VF) 671 goto setup_rings; 672 673 ice_vsi_cfg_frame_size(vsi); 674 setup_rings: 675 /* set up individual rings */ 676 ice_for_each_rxq(vsi, i) { 677 int err = ice_vsi_cfg_rxq(vsi->rx_rings[i]); 678 679 if (err) 680 return err; 681 } 682 683 return 0; 684 } 685 686 /** 687 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 688 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 689 * 690 * This function first tries to find contiguous space. If it is not successful, 691 * it tries with the scatter approach. 692 * 693 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 694 */ 695 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 696 { 697 int ret = 0; 698 699 ret = __ice_vsi_get_qs_contig(qs_cfg); 700 if (ret) { 701 /* contig failed, so try with scatter approach */ 702 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 703 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count, 704 qs_cfg->scatter_count); 705 ret = __ice_vsi_get_qs_sc(qs_cfg); 706 } 707 return ret; 708 } 709 710 /** 711 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait 712 * @vsi: the VSI being configured 713 * @ena: start or stop the Rx ring 714 * @rxq_idx: 0-based Rx queue index for the VSI passed in 715 * @wait: wait or don't wait for configuration to finish in hardware 716 * 717 * Return 0 on success and negative on error. 718 */ 719 int 720 ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait) 721 { 722 int pf_q = vsi->rxq_map[rxq_idx]; 723 struct ice_pf *pf = vsi->back; 724 struct ice_hw *hw = &pf->hw; 725 u32 rx_reg; 726 727 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 728 729 /* Skip if the queue is already in the requested state */ 730 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 731 return 0; 732 733 /* turn on/off the queue */ 734 if (ena) 735 rx_reg |= QRX_CTRL_QENA_REQ_M; 736 else 737 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 738 wr32(hw, QRX_CTRL(pf_q), rx_reg); 739 740 if (!wait) 741 return 0; 742 743 ice_flush(hw); 744 return ice_pf_rxq_wait(pf, pf_q, ena); 745 } 746 747 /** 748 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started 749 * @vsi: the VSI being configured 750 * @ena: true/false to verify Rx ring has been enabled/disabled respectively 751 * @rxq_idx: 0-based Rx queue index for the VSI passed in 752 * 753 * This routine will wait for the given Rx queue of the VSI to reach the 754 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach 755 * the requested state after multiple retries; else will return 0 in case of 756 * success. 757 */ 758 int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 759 { 760 int pf_q = vsi->rxq_map[rxq_idx]; 761 struct ice_pf *pf = vsi->back; 762 763 return ice_pf_rxq_wait(pf, pf_q, ena); 764 } 765 766 /** 767 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 768 * @vsi: the VSI being configured 769 * 770 * We allocate one q_vector per queue interrupt. If allocation fails we 771 * return -ENOMEM. 772 */ 773 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 774 { 775 struct device *dev = ice_pf_to_dev(vsi->back); 776 u16 v_idx; 777 int err; 778 779 if (vsi->q_vectors[0]) { 780 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 781 return -EEXIST; 782 } 783 784 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 785 err = ice_vsi_alloc_q_vector(vsi, v_idx); 786 if (err) 787 goto err_out; 788 } 789 790 return 0; 791 792 err_out: 793 while (v_idx--) 794 ice_free_q_vector(vsi, v_idx); 795 796 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 797 vsi->num_q_vectors, vsi->vsi_num, err); 798 vsi->num_q_vectors = 0; 799 return err; 800 } 801 802 /** 803 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 804 * @vsi: the VSI being configured 805 * 806 * This function maps descriptor rings to the queue-specific vectors allotted 807 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 808 * and Rx rings to the vector as "efficiently" as possible. 809 */ 810 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 811 { 812 int q_vectors = vsi->num_q_vectors; 813 u16 tx_rings_rem, rx_rings_rem; 814 int v_id; 815 816 /* initially assigning remaining rings count to VSIs num queue value */ 817 tx_rings_rem = vsi->num_txq; 818 rx_rings_rem = vsi->num_rxq; 819 820 for (v_id = 0; v_id < q_vectors; v_id++) { 821 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 822 u8 tx_rings_per_v, rx_rings_per_v; 823 u16 q_id, q_base; 824 825 /* Tx rings mapping to vector */ 826 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem, 827 q_vectors - v_id); 828 q_vector->num_ring_tx = tx_rings_per_v; 829 q_vector->tx.tx_ring = NULL; 830 q_vector->tx.itr_idx = ICE_TX_ITR; 831 q_base = vsi->num_txq - tx_rings_rem; 832 833 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 834 struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id]; 835 836 tx_ring->q_vector = q_vector; 837 tx_ring->next = q_vector->tx.tx_ring; 838 q_vector->tx.tx_ring = tx_ring; 839 } 840 tx_rings_rem -= tx_rings_per_v; 841 842 /* Rx rings mapping to vector */ 843 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem, 844 q_vectors - v_id); 845 q_vector->num_ring_rx = rx_rings_per_v; 846 q_vector->rx.rx_ring = NULL; 847 q_vector->rx.itr_idx = ICE_RX_ITR; 848 q_base = vsi->num_rxq - rx_rings_rem; 849 850 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 851 struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id]; 852 853 rx_ring->q_vector = q_vector; 854 rx_ring->next = q_vector->rx.rx_ring; 855 q_vector->rx.rx_ring = rx_ring; 856 } 857 rx_rings_rem -= rx_rings_per_v; 858 } 859 860 if (ice_is_xdp_ena_vsi(vsi)) 861 ice_map_xdp_rings(vsi); 862 } 863 864 /** 865 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 866 * @vsi: the VSI having memory freed 867 */ 868 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 869 { 870 int v_idx; 871 872 ice_for_each_q_vector(vsi, v_idx) 873 ice_free_q_vector(vsi, v_idx); 874 875 vsi->num_q_vectors = 0; 876 } 877 878 /** 879 * ice_vsi_cfg_txq - Configure single Tx queue 880 * @vsi: the VSI that queue belongs to 881 * @ring: Tx ring to be configured 882 * @qg_buf: queue group buffer 883 */ 884 static int 885 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring, 886 struct ice_aqc_add_tx_qgrp *qg_buf) 887 { 888 u8 buf_len = struct_size(qg_buf, txqs, 1); 889 struct ice_tlan_ctx tlan_ctx = { 0 }; 890 struct ice_aqc_add_txqs_perq *txq; 891 struct ice_channel *ch = ring->ch; 892 struct ice_pf *pf = vsi->back; 893 struct ice_hw *hw = &pf->hw; 894 int status; 895 u16 pf_q; 896 u8 tc; 897 898 /* Configure XPS */ 899 ice_cfg_xps_tx_ring(ring); 900 901 pf_q = ring->reg_idx; 902 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 903 /* copy context contents into the qg_buf */ 904 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 905 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 906 ice_tlan_ctx_info); 907 908 /* init queue specific tail reg. It is referred as 909 * transmit comm scheduler queue doorbell. 910 */ 911 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q); 912 913 if (IS_ENABLED(CONFIG_DCB)) 914 tc = ring->dcb_tc; 915 else 916 tc = 0; 917 918 /* Add unique software queue handle of the Tx queue per 919 * TC into the VSI Tx ring 920 */ 921 ring->q_handle = ice_calc_txq_handle(vsi, ring, tc); 922 923 if (ch) 924 status = ice_ena_vsi_txq(vsi->port_info, ch->ch_vsi->idx, 0, 925 ring->q_handle, 1, qg_buf, buf_len, 926 NULL); 927 else 928 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, 929 ring->q_handle, 1, qg_buf, buf_len, 930 NULL); 931 if (status) { 932 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n", 933 status); 934 return status; 935 } 936 937 /* Add Tx Queue TEID into the VSI Tx ring from the 938 * response. This will complete configuring and 939 * enabling the queue. 940 */ 941 txq = &qg_buf->txqs[0]; 942 if (pf_q == le16_to_cpu(txq->txq_id)) 943 ring->txq_teid = le32_to_cpu(txq->q_teid); 944 945 return 0; 946 } 947 948 int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_tx_ring **tx_rings, 949 u16 q_idx) 950 { 951 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1); 952 953 if (q_idx >= vsi->alloc_txq || !tx_rings || !tx_rings[q_idx]) 954 return -EINVAL; 955 956 qg_buf->num_txqs = 1; 957 958 return ice_vsi_cfg_txq(vsi, tx_rings[q_idx], qg_buf); 959 } 960 961 /** 962 * ice_vsi_cfg_txqs - Configure the VSI for Tx 963 * @vsi: the VSI being configured 964 * @rings: Tx ring array to be configured 965 * @count: number of Tx ring array elements 966 * 967 * Return 0 on success and a negative value on error 968 * Configure the Tx VSI for operation. 969 */ 970 static int 971 ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_tx_ring **rings, u16 count) 972 { 973 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1); 974 int err = 0; 975 u16 q_idx; 976 977 qg_buf->num_txqs = 1; 978 979 for (q_idx = 0; q_idx < count; q_idx++) { 980 err = ice_vsi_cfg_txq(vsi, rings[q_idx], qg_buf); 981 if (err) 982 break; 983 } 984 985 return err; 986 } 987 988 /** 989 * ice_vsi_cfg_lan_txqs - Configure the VSI for Tx 990 * @vsi: the VSI being configured 991 * 992 * Return 0 on success and a negative value on error 993 * Configure the Tx VSI for operation. 994 */ 995 int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi) 996 { 997 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq); 998 } 999 1000 /** 1001 * ice_vsi_cfg_xdp_txqs - Configure Tx queues dedicated for XDP in given VSI 1002 * @vsi: the VSI being configured 1003 * 1004 * Return 0 on success and a negative value on error 1005 * Configure the Tx queues dedicated for XDP in given VSI for operation. 1006 */ 1007 int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi) 1008 { 1009 int ret; 1010 int i; 1011 1012 ret = ice_vsi_cfg_txqs(vsi, vsi->xdp_rings, vsi->num_xdp_txq); 1013 if (ret) 1014 return ret; 1015 1016 ice_for_each_rxq(vsi, i) 1017 ice_tx_xsk_pool(vsi, i); 1018 1019 return 0; 1020 } 1021 1022 /** 1023 * ice_cfg_itr - configure the initial interrupt throttle values 1024 * @hw: pointer to the HW structure 1025 * @q_vector: interrupt vector that's being configured 1026 * 1027 * Configure interrupt throttling values for the ring containers that are 1028 * associated with the interrupt vector passed in. 1029 */ 1030 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 1031 { 1032 ice_cfg_itr_gran(hw); 1033 1034 if (q_vector->num_ring_rx) 1035 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting); 1036 1037 if (q_vector->num_ring_tx) 1038 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting); 1039 1040 ice_write_intrl(q_vector, q_vector->intrl); 1041 } 1042 1043 /** 1044 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 1045 * @vsi: the VSI being configured 1046 * @txq: Tx queue being mapped to MSI-X vector 1047 * @msix_idx: MSI-X vector index within the function 1048 * @itr_idx: ITR index of the interrupt cause 1049 * 1050 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 1051 * within the function space. 1052 */ 1053 void 1054 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 1055 { 1056 struct ice_pf *pf = vsi->back; 1057 struct ice_hw *hw = &pf->hw; 1058 u32 val; 1059 1060 itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx); 1061 1062 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 1063 FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx); 1064 1065 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 1066 if (ice_is_xdp_ena_vsi(vsi)) { 1067 u32 xdp_txq = txq + vsi->num_xdp_txq; 1068 1069 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 1070 val); 1071 } 1072 ice_flush(hw); 1073 } 1074 1075 /** 1076 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 1077 * @vsi: the VSI being configured 1078 * @rxq: Rx queue being mapped to MSI-X vector 1079 * @msix_idx: MSI-X vector index within the function 1080 * @itr_idx: ITR index of the interrupt cause 1081 * 1082 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 1083 * within the function space. 1084 */ 1085 void 1086 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 1087 { 1088 struct ice_pf *pf = vsi->back; 1089 struct ice_hw *hw = &pf->hw; 1090 u32 val; 1091 1092 itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx); 1093 1094 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 1095 FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx); 1096 1097 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 1098 1099 ice_flush(hw); 1100 } 1101 1102 /** 1103 * ice_trigger_sw_intr - trigger a software interrupt 1104 * @hw: pointer to the HW structure 1105 * @q_vector: interrupt vector to trigger the software interrupt for 1106 */ 1107 void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector) 1108 { 1109 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 1110 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 1111 GLINT_DYN_CTL_SWINT_TRIG_M | 1112 GLINT_DYN_CTL_INTENA_M); 1113 } 1114 1115 /** 1116 * ice_vsi_stop_tx_ring - Disable single Tx ring 1117 * @vsi: the VSI being configured 1118 * @rst_src: reset source 1119 * @rel_vmvf_num: Relative ID of VF/VM 1120 * @ring: Tx ring to be stopped 1121 * @txq_meta: Meta data of Tx ring to be stopped 1122 */ 1123 int 1124 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 1125 u16 rel_vmvf_num, struct ice_tx_ring *ring, 1126 struct ice_txq_meta *txq_meta) 1127 { 1128 struct ice_pf *pf = vsi->back; 1129 struct ice_q_vector *q_vector; 1130 struct ice_hw *hw = &pf->hw; 1131 int status; 1132 u32 val; 1133 1134 /* clear cause_ena bit for disabled queues */ 1135 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 1136 val &= ~QINT_TQCTL_CAUSE_ENA_M; 1137 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 1138 1139 /* software is expected to wait for 100 ns */ 1140 ndelay(100); 1141 1142 /* trigger a software interrupt for the vector 1143 * associated to the queue to schedule NAPI handler 1144 */ 1145 q_vector = ring->q_vector; 1146 if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf))) 1147 ice_trigger_sw_intr(hw, q_vector); 1148 1149 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 1150 txq_meta->tc, 1, &txq_meta->q_handle, 1151 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 1152 rel_vmvf_num, NULL); 1153 1154 /* if the disable queue command was exercised during an 1155 * active reset flow, -EBUSY is returned. 1156 * This is not an error as the reset operation disables 1157 * queues at the hardware level anyway. 1158 */ 1159 if (status == -EBUSY) { 1160 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 1161 } else if (status == -ENOENT) { 1162 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 1163 } else if (status) { 1164 dev_dbg(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n", 1165 status); 1166 return status; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /** 1173 * ice_fill_txq_meta - Prepare the Tx queue's meta data 1174 * @vsi: VSI that ring belongs to 1175 * @ring: ring that txq_meta will be based on 1176 * @txq_meta: a helper struct that wraps Tx queue's information 1177 * 1178 * Set up a helper struct that will contain all the necessary fields that 1179 * are needed for stopping Tx queue 1180 */ 1181 void 1182 ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring, 1183 struct ice_txq_meta *txq_meta) 1184 { 1185 struct ice_channel *ch = ring->ch; 1186 u8 tc; 1187 1188 if (IS_ENABLED(CONFIG_DCB)) 1189 tc = ring->dcb_tc; 1190 else 1191 tc = 0; 1192 1193 txq_meta->q_id = ring->reg_idx; 1194 txq_meta->q_teid = ring->txq_teid; 1195 txq_meta->q_handle = ring->q_handle; 1196 if (ch) { 1197 txq_meta->vsi_idx = ch->ch_vsi->idx; 1198 txq_meta->tc = 0; 1199 } else { 1200 txq_meta->vsi_idx = vsi->idx; 1201 txq_meta->tc = tc; 1202 } 1203 } 1204