1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 121 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 122 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 123 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 124 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 125 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 126 #define ICE_AQC_BIT_SRIOV_LAG 0x02 127 128 u8 major_ver; 129 u8 minor_ver; 130 /* Number of resources described by this capability */ 131 __le32 number; 132 /* Only meaningful for some types of resources */ 133 __le32 logical_id; 134 /* Only meaningful for some types of resources */ 135 __le32 phys_id; 136 __le64 rsvd1; 137 __le64 rsvd2; 138 }; 139 140 /* Manage MAC address, read command - indirect (0x0107) 141 * This struct is also used for the response 142 */ 143 struct ice_aqc_manage_mac_read { 144 __le16 flags; /* Zeroed by device driver */ 145 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 146 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 147 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 148 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 149 #define ICE_AQC_MAN_MAC_READ_S 4 150 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 151 u8 rsvd[2]; 152 u8 num_addr; /* Used in response */ 153 u8 rsvd1[3]; 154 __le32 addr_high; 155 __le32 addr_low; 156 }; 157 158 /* Response buffer format for manage MAC read command */ 159 struct ice_aqc_manage_mac_read_resp { 160 u8 lport_num; 161 u8 addr_type; 162 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 163 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 164 u8 mac_addr[ETH_ALEN]; 165 }; 166 167 /* Manage MAC address, write command - direct (0x0108) */ 168 struct ice_aqc_manage_mac_write { 169 u8 rsvd; 170 u8 flags; 171 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 172 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 173 #define ICE_AQC_MAN_MAC_WR_S 6 174 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 175 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 176 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 177 /* byte stream in network order */ 178 u8 mac_addr[ETH_ALEN]; 179 __le32 addr_high; 180 __le32 addr_low; 181 }; 182 183 /* Clear PXE Command and response (direct 0x0110) */ 184 struct ice_aqc_clear_pxe { 185 u8 rx_cnt; 186 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 187 u8 reserved[15]; 188 }; 189 190 /* Get switch configuration (0x0200) */ 191 struct ice_aqc_get_sw_cfg { 192 /* Reserved for command and copy of request flags for response */ 193 __le16 flags; 194 /* First desc in case of command and next_elem in case of response 195 * In case of response, if it is not zero, means all the configuration 196 * was not returned and new command shall be sent with this value in 197 * the 'first desc' field 198 */ 199 __le16 element; 200 /* Reserved for command, only used for response */ 201 __le16 num_elems; 202 __le16 rsvd; 203 __le32 addr_high; 204 __le32 addr_low; 205 }; 206 207 /* Each entry in the response buffer is of the following type: */ 208 struct ice_aqc_get_sw_cfg_resp_elem { 209 /* VSI/Port Number */ 210 __le16 vsi_port_num; 211 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 212 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 213 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 214 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 215 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 216 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 217 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 218 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 219 220 /* SWID VSI/Port belongs to */ 221 __le16 swid; 222 223 /* Bit 14..0 : PF/VF number VSI belongs to 224 * Bit 15 : VF indication bit 225 */ 226 __le16 pf_vf_num; 227 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 228 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 229 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 230 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 231 }; 232 233 /* Set Port parameters, (direct, 0x0203) */ 234 struct ice_aqc_set_port_params { 235 __le16 cmd_flags; 236 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 237 __le16 bad_frame_vsi; 238 __le16 swid; 239 #define ICE_AQC_PORT_SWID_VALID BIT(15) 240 #define ICE_AQC_PORT_SWID_M 0xFF 241 u8 reserved[10]; 242 }; 243 244 /* These resource type defines are used for all switch resource 245 * commands where a resource type is required, such as: 246 * Get Resource Allocation command (indirect 0x0204) 247 * Allocate Resources command (indirect 0x0208) 248 * Free Resources command (indirect 0x0209) 249 * Get Allocated Resource Descriptors Command (indirect 0x020A) 250 * Share Resource command (indirect 0x020B) 251 */ 252 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 253 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 254 #define ICE_AQC_RES_TYPE_RECIPE 0x05 255 #define ICE_AQC_RES_TYPE_SWID 0x07 256 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 257 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 258 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 259 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 260 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 261 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 262 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 263 264 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 265 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 266 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 267 268 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 269 270 #define ICE_AQC_RES_TYPE_S 0 271 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 272 273 /* Allocate Resources command (indirect 0x0208) 274 * Free Resources command (indirect 0x0209) 275 * Share Resource command (indirect 0x020B) 276 */ 277 struct ice_aqc_alloc_free_res_cmd { 278 __le16 num_entries; /* Number of Resource entries */ 279 u8 reserved[6]; 280 __le32 addr_high; 281 __le32 addr_low; 282 }; 283 284 /* Resource descriptor */ 285 struct ice_aqc_res_elem { 286 union { 287 __le16 sw_resp; 288 __le16 flu_resp; 289 } e; 290 }; 291 292 /* Buffer for Allocate/Free Resources commands */ 293 struct ice_aqc_alloc_free_res_elem { 294 __le16 res_type; /* Types defined above cmd 0x0204 */ 295 #define ICE_AQC_RES_TYPE_SHARED_S 7 296 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 297 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 298 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 299 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 300 __le16 num_elems; 301 struct ice_aqc_res_elem elem[]; 302 }; 303 304 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 305 struct ice_aqc_set_vlan_mode { 306 u8 reserved; 307 u8 l2tag_prio_tagging; 308 #define ICE_AQ_VLAN_PRIO_TAG_S 0 309 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 310 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 311 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 312 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 313 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 314 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 315 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 316 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 317 u8 l2tag_reserved[64]; 318 u8 rdma_packet; 319 #define ICE_AQ_VLAN_RDMA_TAG_S 0 320 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 321 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 322 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 323 u8 rdma_reserved[2]; 324 u8 mng_vlan_prot_id; 325 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 326 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 327 u8 prot_id_reserved[30]; 328 }; 329 330 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 331 struct ice_aqc_get_vlan_mode { 332 u8 vlan_mode; 333 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 334 u8 l2tag_prio_tagging; 335 u8 reserved[98]; 336 }; 337 338 /* Add VSI (indirect 0x0210) 339 * Update VSI (indirect 0x0211) 340 * Get VSI (indirect 0x0212) 341 * Free VSI (indirect 0x0213) 342 */ 343 struct ice_aqc_add_get_update_free_vsi { 344 __le16 vsi_num; 345 #define ICE_AQ_VSI_NUM_S 0 346 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 347 #define ICE_AQ_VSI_IS_VALID BIT(15) 348 __le16 cmd_flags; 349 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 350 u8 vf_id; 351 u8 reserved; 352 __le16 vsi_flags; 353 #define ICE_AQ_VSI_TYPE_S 0 354 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 355 #define ICE_AQ_VSI_TYPE_VF 0x0 356 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 357 #define ICE_AQ_VSI_TYPE_PF 0x2 358 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 359 __le32 addr_high; 360 __le32 addr_low; 361 }; 362 363 /* Response descriptor for: 364 * Add VSI (indirect 0x0210) 365 * Update VSI (indirect 0x0211) 366 * Free VSI (indirect 0x0213) 367 */ 368 struct ice_aqc_add_update_free_vsi_resp { 369 __le16 vsi_num; 370 __le16 ext_status; 371 __le16 vsi_used; 372 __le16 vsi_free; 373 __le32 addr_high; 374 __le32 addr_low; 375 }; 376 377 struct ice_aqc_vsi_props { 378 __le16 valid_sections; 379 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 380 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 381 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 382 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 383 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 384 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 385 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 386 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 387 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 388 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 389 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 390 /* switch section */ 391 u8 sw_id; 392 u8 sw_flags; 393 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 394 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 395 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 396 u8 sw_flags2; 397 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 398 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 399 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 400 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 401 u8 veb_stat_id; 402 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 403 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 404 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 405 /* security section */ 406 u8 sec_flags; 407 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 408 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 409 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 410 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 411 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 412 u8 sec_reserved; 413 /* VLAN section */ 414 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 415 u8 inner_vlan_reserved[2]; 416 u8 inner_vlan_flags; 417 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 418 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 419 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 420 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 421 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 422 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 423 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 424 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 425 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 426 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 427 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 428 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 429 u8 inner_vlan_reserved2[3]; 430 /* ingress egress up sections */ 431 __le32 ingress_table; /* bitmap, 3 bits per up */ 432 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 433 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 434 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 435 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 436 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 437 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 438 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 439 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 440 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 441 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 442 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 443 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 444 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 445 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 446 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 447 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 448 __le32 egress_table; /* same defines as for ingress table */ 449 /* outer tags section */ 450 __le16 port_based_outer_vlan; 451 u8 outer_vlan_flags; 452 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 453 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 454 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 455 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 456 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 457 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 458 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 459 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 460 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 461 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 462 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 463 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 464 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 465 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 466 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 467 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 468 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 469 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 470 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 471 u8 outer_vlan_reserved; 472 /* queue mapping section */ 473 __le16 mapping_flags; 474 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 475 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 476 __le16 q_mapping[16]; 477 #define ICE_AQ_VSI_Q_S 0 478 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 479 __le16 tc_mapping[8]; 480 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 481 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 482 #define ICE_AQ_VSI_TC_Q_NUM_S 11 483 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 484 /* queueing option section */ 485 u8 q_opt_rss; 486 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 487 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 488 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 489 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 490 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 491 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 492 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 493 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 494 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 495 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 496 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 497 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 498 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 499 u8 q_opt_tc; 500 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 501 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 502 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 503 u8 q_opt_flags; 504 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 505 u8 q_opt_reserved[3]; 506 /* outer up section */ 507 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 508 /* section 10 */ 509 __le16 sect_10_reserved; 510 /* flow director section */ 511 __le16 fd_options; 512 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 513 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 514 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 515 __le16 max_fd_fltr_dedicated; 516 __le16 max_fd_fltr_shared; 517 __le16 fd_def_q; 518 #define ICE_AQ_VSI_FD_DEF_Q_S 0 519 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 520 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 521 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 522 __le16 fd_report_opt; 523 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 524 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 525 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 526 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 527 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 528 /* PASID section */ 529 __le32 pasid_id; 530 #define ICE_AQ_VSI_PASID_ID_S 0 531 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 532 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 533 u8 reserved[24]; 534 }; 535 536 #define ICE_MAX_NUM_RECIPES 64 537 538 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 539 struct ice_aqc_add_get_recipe { 540 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 541 __le16 return_index; /* Input, used for Get cmd only */ 542 u8 reserved[4]; 543 __le32 addr_high; 544 __le32 addr_low; 545 }; 546 547 struct ice_aqc_recipe_content { 548 u8 rid; 549 #define ICE_AQ_RECIPE_ID_S 0 550 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 551 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 552 #define ICE_AQ_SW_ID_LKUP_IDX 0 553 u8 lkup_indx[5]; 554 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 555 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 556 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 557 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 558 __le16 mask[5]; 559 u8 result_indx; 560 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 561 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 562 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 563 u8 rsvd0[3]; 564 u8 act_ctrl_join_priority; 565 u8 act_ctrl_fwd_priority; 566 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 567 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 568 u8 act_ctrl; 569 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 570 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 571 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 572 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 573 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 574 u8 rsvd1; 575 __le32 dflt_act; 576 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 577 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 578 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 579 }; 580 581 struct ice_aqc_recipe_data_elem { 582 u8 recipe_indx; 583 u8 resp_bits; 584 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 585 u8 rsvd0[2]; 586 u8 recipe_bitmap[8]; 587 u8 rsvd1[4]; 588 struct ice_aqc_recipe_content content; 589 u8 rsvd2[20]; 590 }; 591 592 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 593 struct ice_aqc_recipe_to_profile { 594 __le16 profile_id; 595 u8 rsvd[6]; 596 DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES); 597 }; 598 599 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 600 */ 601 struct ice_aqc_sw_rules { 602 /* ops: add switch rules, referring the number of rules. 603 * ops: update switch rules, referring the number of filters 604 * ops: remove switch rules, referring the entry index. 605 * ops: get switch rules, referring to the number of filters. 606 */ 607 __le16 num_rules_fltr_entry_index; 608 u8 reserved[6]; 609 __le32 addr_high; 610 __le32 addr_low; 611 }; 612 613 /* Add switch rule response: 614 * Content of return buffer is same as the input buffer. The status field and 615 * LUT index are updated as part of the response 616 */ 617 struct ice_aqc_sw_rules_elem_hdr { 618 __le16 type; /* Switch rule type, one of T_... */ 619 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 620 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 621 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 622 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 623 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 624 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 625 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 626 __le16 status; 627 } __packed __aligned(sizeof(__le16)); 628 629 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 630 * This structures describes the lookup rules and associated actions. "index" 631 * is returned as part of a response to a successful Add command, and can be 632 * used to identify the rule for Update/Get/Remove commands. 633 */ 634 struct ice_sw_rule_lkup_rx_tx { 635 struct ice_aqc_sw_rules_elem_hdr hdr; 636 637 __le16 recipe_id; 638 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 639 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 640 __le16 src; 641 __le32 act; 642 643 /* Bit 0:1 - Action type */ 644 #define ICE_SINGLE_ACT_TYPE_S 0x00 645 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 646 647 /* Bit 2 - Loop back enable 648 * Bit 3 - LAN enable 649 */ 650 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 651 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 652 653 /* Action type = 0 - Forward to VSI or VSI list */ 654 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 655 656 #define ICE_SINGLE_ACT_VSI_ID_S 4 657 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 658 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 659 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 660 /* This bit needs to be set if action is forward to VSI list */ 661 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 662 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 663 #define ICE_SINGLE_ACT_DROP BIT(18) 664 665 /* Action type = 1 - Forward to Queue of Queue group */ 666 #define ICE_SINGLE_ACT_TO_Q 0x1 667 #define ICE_SINGLE_ACT_Q_INDEX_S 4 668 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 669 #define ICE_SINGLE_ACT_Q_REGION_S 15 670 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 671 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 672 673 /* Action type = 2 - Prune */ 674 #define ICE_SINGLE_ACT_PRUNE 0x2 675 #define ICE_SINGLE_ACT_EGRESS BIT(15) 676 #define ICE_SINGLE_ACT_INGRESS BIT(16) 677 #define ICE_SINGLE_ACT_PRUNET BIT(17) 678 /* Bit 18 should be set to 0 for this action */ 679 680 /* Action type = 2 - Pointer */ 681 #define ICE_SINGLE_ACT_PTR 0x2 682 #define ICE_SINGLE_ACT_PTR_VAL_S 4 683 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 684 /* Bit 18 should be set to 1 */ 685 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 686 687 /* Action type = 3 - Other actions. Last two bits 688 * are other action identifier 689 */ 690 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 691 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 692 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 693 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 694 695 /* Bit 17:18 - Defines other actions */ 696 /* Other action = 0 - Mirror VSI */ 697 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 698 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 699 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 700 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 701 702 /* Other action = 3 - Set Stat count */ 703 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 704 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 705 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 706 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 707 708 __le16 index; /* The index of the rule in the lookup table */ 709 /* Length and values of the header to be matched per recipe or 710 * lookup-type 711 */ 712 __le16 hdr_len; 713 u8 hdr_data[]; 714 } __packed __aligned(sizeof(__le16)); 715 716 /* Add/Update/Remove large action command/response entry 717 * "index" is returned as part of a response to a successful Add command, and 718 * can be used to identify the action for Update/Get/Remove commands. 719 */ 720 struct ice_sw_rule_lg_act { 721 struct ice_aqc_sw_rules_elem_hdr hdr; 722 723 __le16 index; /* Index in large action table */ 724 __le16 size; 725 /* Max number of large actions */ 726 #define ICE_MAX_LG_ACT 4 727 /* Bit 0:1 - Action type */ 728 #define ICE_LG_ACT_TYPE_S 0 729 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 730 731 /* Action type = 0 - Forward to VSI or VSI list */ 732 #define ICE_LG_ACT_VSI_FORWARDING 0 733 #define ICE_LG_ACT_VSI_ID_S 3 734 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 735 #define ICE_LG_ACT_VSI_LIST_ID_S 3 736 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 737 /* This bit needs to be set if action is forward to VSI list */ 738 #define ICE_LG_ACT_VSI_LIST BIT(13) 739 740 #define ICE_LG_ACT_VALID_BIT BIT(16) 741 742 /* Action type = 1 - Forward to Queue of Queue group */ 743 #define ICE_LG_ACT_TO_Q 0x1 744 #define ICE_LG_ACT_Q_INDEX_S 3 745 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 746 #define ICE_LG_ACT_Q_REGION_S 14 747 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 748 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 749 750 /* Action type = 2 - Prune */ 751 #define ICE_LG_ACT_PRUNE 0x2 752 #define ICE_LG_ACT_EGRESS BIT(14) 753 #define ICE_LG_ACT_INGRESS BIT(15) 754 #define ICE_LG_ACT_PRUNET BIT(16) 755 756 /* Action type = 3 - Mirror VSI */ 757 #define ICE_LG_OTHER_ACT_MIRROR 0x3 758 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 759 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 760 761 /* Action type = 5 - Generic Value */ 762 #define ICE_LG_ACT_GENERIC 0x5 763 #define ICE_LG_ACT_GENERIC_VALUE_S 3 764 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 765 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 766 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 767 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 768 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 769 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 770 771 /* Action = 7 - Set Stat count */ 772 #define ICE_LG_ACT_STAT_COUNT 0x7 773 #define ICE_LG_ACT_STAT_COUNT_S 3 774 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 775 __le32 act[]; /* array of size for actions */ 776 } __packed __aligned(sizeof(__le16)); 777 778 /* Add/Update/Remove VSI list command/response entry 779 * "index" is returned as part of a response to a successful Add command, and 780 * can be used to identify the VSI list for Update/Get/Remove commands. 781 */ 782 struct ice_sw_rule_vsi_list { 783 struct ice_aqc_sw_rules_elem_hdr hdr; 784 785 __le16 index; /* Index of VSI/Prune list */ 786 __le16 number_vsi; 787 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 788 } __packed __aligned(sizeof(__le16)); 789 790 /* Query PFC Mode (direct 0x0302) 791 * Set PFC Mode (direct 0x0303) 792 */ 793 struct ice_aqc_set_query_pfc_mode { 794 u8 pfc_mode; 795 /* For Query Command response, reserved in all other cases */ 796 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 797 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 798 u8 rsvd[15]; 799 }; 800 /* Get Default Topology (indirect 0x0400) */ 801 struct ice_aqc_get_topo { 802 u8 port_num; 803 u8 num_branches; 804 __le16 reserved1; 805 __le32 reserved2; 806 __le32 addr_high; 807 __le32 addr_low; 808 }; 809 810 /* Update TSE (indirect 0x0403) 811 * Get TSE (indirect 0x0404) 812 * Add TSE (indirect 0x0401) 813 * Delete TSE (indirect 0x040F) 814 * Move TSE (indirect 0x0408) 815 * Suspend Nodes (indirect 0x0409) 816 * Resume Nodes (indirect 0x040A) 817 */ 818 struct ice_aqc_sched_elem_cmd { 819 __le16 num_elem_req; /* Used by commands */ 820 __le16 num_elem_resp; /* Used by responses */ 821 __le32 reserved; 822 __le32 addr_high; 823 __le32 addr_low; 824 }; 825 826 struct ice_aqc_txsched_move_grp_info_hdr { 827 __le32 src_parent_teid; 828 __le32 dest_parent_teid; 829 __le16 num_elems; 830 u8 mode; 831 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 832 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 833 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 834 u8 reserved; 835 }; 836 837 struct ice_aqc_move_elem { 838 struct ice_aqc_txsched_move_grp_info_hdr hdr; 839 __le32 teid[]; 840 }; 841 842 struct ice_aqc_elem_info_bw { 843 __le16 bw_profile_idx; 844 __le16 bw_alloc; 845 }; 846 847 struct ice_aqc_txsched_elem { 848 u8 elem_type; /* Special field, reserved for some aq calls */ 849 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 850 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 851 #define ICE_AQC_ELEM_TYPE_TC 0x2 852 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 853 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 854 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 855 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 856 u8 valid_sections; 857 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 858 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 859 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 860 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 861 u8 generic; 862 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 863 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 864 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 865 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 866 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 867 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 868 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 869 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 870 u8 flags; /* Special field, reserved for some aq calls */ 871 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 872 struct ice_aqc_elem_info_bw cir_bw; 873 struct ice_aqc_elem_info_bw eir_bw; 874 __le16 srl_id; 875 __le16 reserved2; 876 }; 877 878 struct ice_aqc_txsched_elem_data { 879 __le32 parent_teid; 880 __le32 node_teid; 881 struct ice_aqc_txsched_elem data; 882 }; 883 884 struct ice_aqc_txsched_topo_grp_info_hdr { 885 __le32 parent_teid; 886 __le16 num_elems; 887 __le16 reserved2; 888 }; 889 890 struct ice_aqc_add_elem { 891 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 892 struct ice_aqc_txsched_elem_data generic[]; 893 }; 894 895 struct ice_aqc_get_topo_elem { 896 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 897 struct ice_aqc_txsched_elem_data 898 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 899 }; 900 901 struct ice_aqc_delete_elem { 902 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 903 __le32 teid[]; 904 }; 905 906 /* Query Port ETS (indirect 0x040E) 907 * 908 * This indirect command is used to query port TC node configuration. 909 */ 910 struct ice_aqc_query_port_ets { 911 __le32 port_teid; 912 __le32 reserved; 913 __le32 addr_high; 914 __le32 addr_low; 915 }; 916 917 struct ice_aqc_port_ets_elem { 918 u8 tc_valid_bits; 919 u8 reserved[3]; 920 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 921 __le32 up2tc; 922 u8 tc_bw_share[8]; 923 __le32 port_eir_prof_id; 924 __le32 port_cir_prof_id; 925 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 926 __le32 tc_node_prio; 927 #define ICE_TC_NODE_PRIO_S 0x4 928 u8 reserved1[4]; 929 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 930 }; 931 932 /* Rate limiting profile for 933 * Add RL profile (indirect 0x0410) 934 * Query RL profile (indirect 0x0411) 935 * Remove RL profile (indirect 0x0415) 936 * These indirect commands acts on single or multiple 937 * RL profiles with specified data. 938 */ 939 struct ice_aqc_rl_profile { 940 __le16 num_profiles; 941 __le16 num_processed; /* Only for response. Reserved in Command. */ 942 u8 reserved[4]; 943 __le32 addr_high; 944 __le32 addr_low; 945 }; 946 947 struct ice_aqc_rl_profile_elem { 948 u8 level; 949 u8 flags; 950 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 951 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 952 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 953 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 954 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 955 /* The following flag is used for Query RL Profile Data */ 956 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 957 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 958 959 __le16 profile_id; 960 __le16 max_burst_size; 961 __le16 rl_multiply; 962 __le16 wake_up_calc; 963 __le16 rl_encode; 964 }; 965 966 /* Query Scheduler Resource Allocation (indirect 0x0412) 967 * This indirect command retrieves the scheduler resources allocated by 968 * EMP Firmware to the given PF. 969 */ 970 struct ice_aqc_query_txsched_res { 971 u8 reserved[8]; 972 __le32 addr_high; 973 __le32 addr_low; 974 }; 975 976 struct ice_aqc_generic_sched_props { 977 __le16 phys_levels; 978 __le16 logical_levels; 979 u8 flattening_bitmap; 980 u8 max_device_cgds; 981 u8 max_pf_cgds; 982 u8 rsvd0; 983 __le16 rdma_qsets; 984 u8 rsvd1[22]; 985 }; 986 987 struct ice_aqc_layer_props { 988 u8 logical_layer; 989 u8 chunk_size; 990 __le16 max_device_nodes; 991 __le16 max_pf_nodes; 992 u8 rsvd0[4]; 993 __le16 max_sibl_grp_sz; 994 __le16 max_cir_rl_profiles; 995 __le16 max_eir_rl_profiles; 996 __le16 max_srl_profiles; 997 u8 rsvd1[14]; 998 }; 999 1000 struct ice_aqc_query_txsched_res_resp { 1001 struct ice_aqc_generic_sched_props sched_props; 1002 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1003 }; 1004 1005 /* Get PHY capabilities (indirect 0x0600) */ 1006 struct ice_aqc_get_phy_caps { 1007 u8 lport_num; 1008 u8 reserved; 1009 __le16 param0; 1010 /* 18.0 - Report qualified modules */ 1011 #define ICE_AQC_GET_PHY_RQM BIT(0) 1012 /* 18.1 - 18.3 : Report mode 1013 * 000b - Report NVM capabilities 1014 * 001b - Report topology capabilities 1015 * 010b - Report SW configured 1016 * 100b - Report default capabilities 1017 */ 1018 #define ICE_AQC_REPORT_MODE_S 1 1019 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1020 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1021 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1022 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1023 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1024 __le32 reserved1; 1025 __le32 addr_high; 1026 __le32 addr_low; 1027 }; 1028 1029 /* This is #define of PHY type (Extended): 1030 * The first set of defines is for phy_type_low. 1031 */ 1032 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1033 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1034 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1035 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1036 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1037 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1038 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1039 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1040 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1041 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1042 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1043 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1044 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1045 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1046 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1047 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1048 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1049 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1050 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1051 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1052 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1053 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1054 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1055 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1056 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1057 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1058 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1059 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1060 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1061 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1062 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1063 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1064 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1065 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1066 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1067 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1068 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1069 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1070 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1071 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1072 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1073 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1074 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1075 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1076 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1077 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1078 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1079 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1080 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1081 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1082 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1083 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1084 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1085 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1086 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1087 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1088 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1089 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1090 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1091 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1092 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1093 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1094 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1095 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1096 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1097 /* The second set of defines is for phy_type_high. */ 1098 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1099 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1100 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1101 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1102 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1103 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1104 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1105 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1106 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1107 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1108 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1109 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1110 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1111 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1112 1113 struct ice_aqc_get_phy_caps_data { 1114 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1115 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1116 u8 caps; 1117 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1118 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1119 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1120 #define ICE_AQC_PHY_EN_LINK BIT(3) 1121 #define ICE_AQC_PHY_AN_MODE BIT(4) 1122 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1123 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1124 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1125 u8 low_power_ctrl_an; 1126 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1127 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1128 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1129 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1130 __le16 eee_cap; 1131 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1132 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1133 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1134 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1135 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1136 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1137 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1138 __le16 eeer_value; 1139 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1140 u8 phy_fw_ver[8]; 1141 u8 link_fec_options; 1142 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1143 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1144 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1145 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1146 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1147 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1148 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1149 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1150 u8 module_compliance_enforcement; 1151 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1152 u8 extended_compliance_code; 1153 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1154 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1155 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1156 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1157 #define ICE_AQC_MOD_TYPE_IDENT 1 1158 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1159 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1160 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1161 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1162 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1163 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1164 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1165 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1166 u8 qualified_module_count; 1167 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1168 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1169 struct { 1170 u8 v_oui[3]; 1171 u8 rsvd3; 1172 u8 v_part[16]; 1173 __le32 v_rev; 1174 __le64 rsvd4; 1175 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1176 }; 1177 1178 /* Set PHY capabilities (direct 0x0601) 1179 * NOTE: This command must be followed by setup link and restart auto-neg 1180 */ 1181 struct ice_aqc_set_phy_cfg { 1182 u8 lport_num; 1183 u8 reserved[7]; 1184 __le32 addr_high; 1185 __le32 addr_low; 1186 }; 1187 1188 /* Set PHY config command data structure */ 1189 struct ice_aqc_set_phy_cfg_data { 1190 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1191 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1192 u8 caps; 1193 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1194 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1195 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1196 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1197 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1198 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1199 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1200 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1201 u8 low_power_ctrl_an; 1202 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1203 __le16 eeer_value; 1204 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1205 u8 module_compliance_enforcement; 1206 }; 1207 1208 /* Set MAC Config command data structure (direct 0x0603) */ 1209 struct ice_aqc_set_mac_cfg { 1210 __le16 max_frame_size; 1211 u8 params; 1212 #define ICE_AQ_SET_MAC_PACE_S 3 1213 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1214 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1215 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1216 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1217 u8 tx_tmr_priority; 1218 __le16 tx_tmr_value; 1219 __le16 fc_refresh_threshold; 1220 u8 drop_opts; 1221 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1222 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1223 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1224 u8 reserved[7]; 1225 }; 1226 1227 /* Restart AN command data structure (direct 0x0605) 1228 * Also used for response, with only the lport_num field present. 1229 */ 1230 struct ice_aqc_restart_an { 1231 u8 lport_num; 1232 u8 reserved; 1233 u8 cmd_flags; 1234 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1235 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1236 u8 reserved2[13]; 1237 }; 1238 1239 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1240 struct ice_aqc_get_link_status { 1241 u8 lport_num; 1242 u8 reserved; 1243 __le16 cmd_flags; 1244 #define ICE_AQ_LSE_M 0x3 1245 #define ICE_AQ_LSE_NOP 0x0 1246 #define ICE_AQ_LSE_DIS 0x2 1247 #define ICE_AQ_LSE_ENA 0x3 1248 /* only response uses this flag */ 1249 #define ICE_AQ_LSE_IS_ENABLED 0x1 1250 __le32 reserved2; 1251 __le32 addr_high; 1252 __le32 addr_low; 1253 }; 1254 1255 /* Get link status response data structure, also used for Link Status Event */ 1256 struct ice_aqc_get_link_status_data { 1257 u8 topo_media_conflict; 1258 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1259 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1260 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1261 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1262 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1263 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1264 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1265 u8 link_cfg_err; 1266 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1267 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1268 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1269 u8 link_info; 1270 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1271 #define ICE_AQ_LINK_FAULT BIT(1) 1272 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1273 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1274 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1275 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1276 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1277 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1278 u8 an_info; 1279 #define ICE_AQ_AN_COMPLETED BIT(0) 1280 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1281 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1282 #define ICE_AQ_FEC_EN BIT(3) 1283 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1284 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1285 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1286 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1287 u8 ext_info; 1288 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1289 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1290 /* Port Tx Suspended */ 1291 #define ICE_AQ_LINK_TX_S 2 1292 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1293 #define ICE_AQ_LINK_TX_ACTIVE 0 1294 #define ICE_AQ_LINK_TX_DRAINED 1 1295 #define ICE_AQ_LINK_TX_FLUSHED 3 1296 u8 reserved2; 1297 __le16 max_frame_size; 1298 u8 cfg; 1299 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1300 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1301 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1302 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1303 /* Pacing Config */ 1304 #define ICE_AQ_CFG_PACING_S 3 1305 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1306 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1307 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1308 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1309 /* External Device Power Ability */ 1310 u8 power_desc; 1311 #define ICE_AQ_PWR_CLASS_M 0x3F 1312 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1313 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1314 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1315 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1316 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1317 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1318 __le16 link_speed; 1319 #define ICE_AQ_LINK_SPEED_M 0x7FF 1320 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1321 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1322 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1323 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1324 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1325 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1326 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1327 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1328 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1329 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1330 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1331 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1332 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1333 /* Aligns next field to 8-byte boundary */ 1334 __le16 reserved3; 1335 u8 ext_fec_status; 1336 /* RS 272 FEC enabled */ 1337 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1338 u8 reserved4; 1339 /* Use values from ICE_PHY_TYPE_LOW_* */ 1340 __le64 phy_type_low; 1341 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1342 __le64 phy_type_high; 1343 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1344 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1345 /* Get link status v2 link partner data */ 1346 __le64 lp_phy_type_low; 1347 __le64 lp_phy_type_high; 1348 u8 lp_fec_adv; 1349 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1350 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1351 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1352 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1353 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1354 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1355 u8 lp_fec_req; 1356 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1357 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1358 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1359 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1360 u8 lp_flowcontrol; 1361 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1362 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1363 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1364 offsetofend(struct ice_aqc_get_link_status_data, lp_flowcontrol) 1365 } __packed; 1366 1367 /* Set event mask command (direct 0x0613) */ 1368 struct ice_aqc_set_event_mask { 1369 u8 lport_num; 1370 u8 reserved[7]; 1371 __le16 event_mask; 1372 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1373 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1374 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1375 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1376 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1377 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1378 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1379 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1380 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1381 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1382 u8 reserved1[6]; 1383 }; 1384 1385 /* Set MAC Loopback command (direct 0x0620) */ 1386 struct ice_aqc_set_mac_lb { 1387 u8 lb_mode; 1388 #define ICE_AQ_MAC_LB_EN BIT(0) 1389 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1390 u8 reserved[15]; 1391 }; 1392 1393 /* Set PHY recovered clock output (direct 0x0630) */ 1394 struct ice_aqc_set_phy_rec_clk_out { 1395 u8 phy_output; 1396 u8 port_num; 1397 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1398 u8 flags; 1399 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1400 u8 rsvd; 1401 __le32 freq; 1402 u8 rsvd2[6]; 1403 __le16 node_handle; 1404 }; 1405 1406 /* Get PHY recovered clock output (direct 0x0631) */ 1407 struct ice_aqc_get_phy_rec_clk_out { 1408 u8 phy_output; 1409 u8 port_num; 1410 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1411 u8 flags; 1412 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1413 u8 rsvd[11]; 1414 __le16 node_handle; 1415 }; 1416 1417 /* Get sensor reading (direct 0x0632) */ 1418 struct ice_aqc_get_sensor_reading { 1419 u8 sensor; 1420 u8 format; 1421 u8 reserved[6]; 1422 __le32 addr_high; 1423 __le32 addr_low; 1424 }; 1425 1426 /* Get sensor reading response (direct 0x0632) */ 1427 struct ice_aqc_get_sensor_reading_resp { 1428 union { 1429 u8 raw[8]; 1430 /* Output data for sensor 0x00, format 0x00 */ 1431 struct _packed { 1432 s8 temp; 1433 u8 temp_warning_threshold; 1434 u8 temp_critical_threshold; 1435 u8 temp_fatal_threshold; 1436 u8 reserved[4]; 1437 } s0f0; 1438 } data; 1439 }; 1440 1441 struct ice_aqc_link_topo_params { 1442 u8 lport_num; 1443 u8 lport_num_valid; 1444 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1445 u8 node_type_ctx; 1446 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1447 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1448 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1449 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1450 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1451 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1452 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1453 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1454 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1455 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1456 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1457 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1458 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1459 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1460 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1461 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1462 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1463 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1464 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1465 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1466 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1467 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1468 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1469 u8 index; 1470 }; 1471 1472 struct ice_aqc_link_topo_addr { 1473 struct ice_aqc_link_topo_params topo_params; 1474 __le16 handle; 1475 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1476 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1477 /* Used to decode the handle field */ 1478 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1479 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1480 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1481 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1482 /* In case of a Mezzanine type */ 1483 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1484 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1485 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1486 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1487 /* In case of a LOM type */ 1488 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1489 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1490 }; 1491 1492 /* Get Link Topology Handle (direct, 0x06E0) */ 1493 struct ice_aqc_get_link_topo { 1494 struct ice_aqc_link_topo_addr addr; 1495 u8 node_part_num; 1496 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1497 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1498 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1499 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1500 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1501 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1502 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1503 u8 rsvd[9]; 1504 }; 1505 1506 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1507 struct ice_aqc_i2c { 1508 struct ice_aqc_link_topo_addr topo_addr; 1509 __le16 i2c_addr; 1510 u8 i2c_params; 1511 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1512 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1513 1514 u8 rsvd; 1515 __le16 i2c_bus_addr; 1516 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1517 }; 1518 1519 /* Read I2C Response (direct, 0x06E2) */ 1520 struct ice_aqc_read_i2c_resp { 1521 u8 i2c_data[16]; 1522 }; 1523 1524 /* Set Port Identification LED (direct, 0x06E9) */ 1525 struct ice_aqc_set_port_id_led { 1526 u8 lport_num; 1527 u8 lport_num_valid; 1528 u8 ident_mode; 1529 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1530 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1531 u8 rsvd[13]; 1532 }; 1533 1534 /* Get Port Options (indirect, 0x06EA) */ 1535 struct ice_aqc_get_port_options { 1536 u8 lport_num; 1537 u8 lport_num_valid; 1538 u8 port_options_count; 1539 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1540 #define ICE_AQC_PORT_OPT_MAX 16 1541 1542 u8 innermost_phy_index; 1543 u8 port_options; 1544 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1545 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1546 1547 u8 pending_port_option_status; 1548 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1549 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1550 1551 u8 rsvd[2]; 1552 __le32 addr_high; 1553 __le32 addr_low; 1554 }; 1555 1556 struct ice_aqc_get_port_options_elem { 1557 u8 pmd; 1558 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1559 1560 u8 max_lane_speed; 1561 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1562 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1563 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1564 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1565 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1566 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1567 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1568 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1569 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1570 1571 u8 global_scid[2]; 1572 u8 phy_scid[2]; 1573 u8 pf2port_cid[2]; 1574 }; 1575 1576 /* Set Port Option (direct, 0x06EB) */ 1577 struct ice_aqc_set_port_option { 1578 u8 lport_num; 1579 u8 lport_num_valid; 1580 u8 selected_port_option; 1581 u8 rsvd[13]; 1582 }; 1583 1584 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1585 struct ice_aqc_gpio { 1586 __le16 gpio_ctrl_handle; 1587 #define ICE_AQC_GPIO_HANDLE_S 0 1588 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1589 u8 gpio_num; 1590 u8 gpio_val; 1591 u8 rsvd[12]; 1592 }; 1593 1594 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1595 struct ice_aqc_sff_eeprom { 1596 u8 lport_num; 1597 u8 lport_num_valid; 1598 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1599 __le16 i2c_bus_addr; 1600 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1601 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1602 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1603 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1604 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1605 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1606 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1607 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1608 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1609 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1610 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1611 __le16 i2c_mem_addr; 1612 __le16 eeprom_page; 1613 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1614 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1615 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1616 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1617 __le32 addr_high; 1618 __le32 addr_low; 1619 }; 1620 1621 /* NVM Read command (indirect 0x0701) 1622 * NVM Erase commands (direct 0x0702) 1623 * NVM Update commands (indirect 0x0703) 1624 */ 1625 struct ice_aqc_nvm { 1626 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1627 __le16 offset_low; 1628 u8 offset_high; 1629 u8 cmd_flags; 1630 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1631 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1632 #define ICE_AQC_NVM_PRESERVATION_S 1 1633 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1634 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1635 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1636 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1637 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1638 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1639 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1640 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1641 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1642 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1643 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1644 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1645 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1646 #define ICE_AQC_NVM_POR_FLAG 0 1647 #define ICE_AQC_NVM_PERST_FLAG 1 1648 #define ICE_AQC_NVM_EMPR_FLAG 2 1649 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1650 /* For Write Activate, several flags are sent as part of a separate 1651 * flags2 field using a separate byte. For simplicity of the software 1652 * interface, we pass the flags as a 16 bit value so these flags are 1653 * all offset by 8 bits 1654 */ 1655 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1656 __le16 module_typeid; 1657 __le16 length; 1658 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1659 __le32 addr_high; 1660 __le32 addr_low; 1661 }; 1662 1663 #define ICE_AQC_NVM_START_POINT 0 1664 1665 /* NVM Checksum Command (direct, 0x0706) */ 1666 struct ice_aqc_nvm_checksum { 1667 u8 flags; 1668 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1669 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1670 u8 rsvd; 1671 __le16 checksum; /* Used only by response */ 1672 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1673 u8 rsvd2[12]; 1674 }; 1675 1676 /* Used for NVM Set Package Data command - 0x070A */ 1677 struct ice_aqc_nvm_pkg_data { 1678 u8 reserved[3]; 1679 u8 cmd_flags; 1680 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1681 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1682 1683 u32 reserved1; 1684 __le32 addr_high; 1685 __le32 addr_low; 1686 }; 1687 1688 /* Used for Pass Component Table command - 0x070B */ 1689 struct ice_aqc_nvm_pass_comp_tbl { 1690 u8 component_response; /* Response only */ 1691 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1692 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1693 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1694 u8 component_response_code; /* Response only */ 1695 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1696 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1697 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1698 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1699 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1700 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1701 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1702 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1703 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1704 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1705 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1706 u8 reserved; 1707 u8 transfer_flag; 1708 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1709 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1710 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1711 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1712 __le32 reserved1; 1713 __le32 addr_high; 1714 __le32 addr_low; 1715 }; 1716 1717 struct ice_aqc_nvm_comp_tbl { 1718 __le16 comp_class; 1719 #define NVM_COMP_CLASS_ALL_FW 0x000A 1720 1721 __le16 comp_id; 1722 #define NVM_COMP_ID_OROM 0x5 1723 #define NVM_COMP_ID_NVM 0x6 1724 #define NVM_COMP_ID_NETLIST 0x8 1725 1726 u8 comp_class_idx; 1727 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1728 1729 __le32 comp_cmp_stamp; 1730 u8 cvs_type; 1731 #define NVM_CVS_TYPE_ASCII 0x1 1732 1733 u8 cvs_len; 1734 u8 cvs[]; /* Component Version String */ 1735 } __packed; 1736 1737 /* Send to PF command (indirect 0x0801) ID is only used by PF 1738 * 1739 * Send to VF command (indirect 0x0802) ID is only used by PF 1740 * 1741 */ 1742 struct ice_aqc_pf_vf_msg { 1743 __le32 id; 1744 u32 reserved; 1745 __le32 addr_high; 1746 __le32 addr_low; 1747 }; 1748 1749 /* Get LLDP MIB (indirect 0x0A00) 1750 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1751 * as the format is the same. 1752 */ 1753 struct ice_aqc_lldp_get_mib { 1754 u8 type; 1755 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1756 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1757 #define ICE_AQ_LLDP_MIB_LOCAL 0 1758 #define ICE_AQ_LLDP_MIB_REMOTE 1 1759 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1760 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1761 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1762 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1763 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1764 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1765 #define ICE_AQ_LLDP_TX_S 0x4 1766 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1767 #define ICE_AQ_LLDP_TX_ACTIVE 0 1768 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1769 #define ICE_AQ_LLDP_TX_FLUSHED 3 1770 /* DCBX mode */ 1771 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1772 #define ICE_AQ_LLDP_DCBX_NA 0 1773 #define ICE_AQ_LLDP_DCBX_CEE 1 1774 #define ICE_AQ_LLDP_DCBX_IEEE 2 1775 1776 u8 state; 1777 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1778 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1779 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1780 1781 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1782 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1783 * Get LLDP MIB (0x0A00) response only. 1784 */ 1785 __le16 local_len; 1786 __le16 remote_len; 1787 u8 reserved[2]; 1788 __le32 addr_high; 1789 __le32 addr_low; 1790 }; 1791 1792 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1793 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1794 struct ice_aqc_lldp_set_mib_change { 1795 u8 command; 1796 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1797 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1798 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1799 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1800 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1801 u8 reserved[15]; 1802 }; 1803 1804 /* Stop LLDP (direct 0x0A05) */ 1805 struct ice_aqc_lldp_stop { 1806 u8 command; 1807 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1808 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1809 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1810 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1811 u8 reserved[15]; 1812 }; 1813 1814 /* Start LLDP (direct 0x0A06) */ 1815 struct ice_aqc_lldp_start { 1816 u8 command; 1817 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1818 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1819 u8 reserved[15]; 1820 }; 1821 1822 /* Get CEE DCBX Oper Config (0x0A07) 1823 * The command uses the generic descriptor struct and 1824 * returns the struct below as an indirect response. 1825 */ 1826 struct ice_aqc_get_cee_dcb_cfg_resp { 1827 u8 oper_num_tc; 1828 u8 oper_prio_tc[4]; 1829 u8 oper_tc_bw[8]; 1830 u8 oper_pfc_en; 1831 __le16 oper_app_prio; 1832 #define ICE_AQC_CEE_APP_FCOE_S 0 1833 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1834 #define ICE_AQC_CEE_APP_ISCSI_S 3 1835 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1836 #define ICE_AQC_CEE_APP_FIP_S 8 1837 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1838 __le32 tlv_status; 1839 #define ICE_AQC_CEE_PG_STATUS_S 0 1840 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1841 #define ICE_AQC_CEE_PFC_STATUS_S 3 1842 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1843 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1844 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1845 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1846 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1847 #define ICE_AQC_CEE_FIP_STATUS_S 16 1848 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1849 u8 reserved[12]; 1850 }; 1851 1852 /* Set Local LLDP MIB (indirect 0x0A08) 1853 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1854 */ 1855 struct ice_aqc_lldp_set_local_mib { 1856 u8 type; 1857 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1858 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1859 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1860 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1861 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1862 u8 reserved0; 1863 __le16 length; 1864 u8 reserved1[4]; 1865 __le32 addr_high; 1866 __le32 addr_low; 1867 }; 1868 1869 /* Stop/Start LLDP Agent (direct 0x0A09) 1870 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1871 * The same structure is used for the response, with the command field 1872 * being used as the status field. 1873 */ 1874 struct ice_aqc_lldp_stop_start_specific_agent { 1875 u8 command; 1876 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1877 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1878 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1879 u8 reserved[15]; 1880 }; 1881 1882 /* LLDP Filter Control (direct 0x0A0A) */ 1883 struct ice_aqc_lldp_filter_ctrl { 1884 u8 cmd_flags; 1885 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1886 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1887 u8 reserved1; 1888 __le16 vsi_num; 1889 u8 reserved2[12]; 1890 }; 1891 1892 #define ICE_AQC_RSS_VSI_VALID BIT(15) 1893 1894 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1895 struct ice_aqc_get_set_rss_key { 1896 __le16 vsi_id; 1897 u8 reserved[6]; 1898 __le32 addr_high; 1899 __le32 addr_low; 1900 }; 1901 1902 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1903 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1904 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1905 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1906 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1907 1908 struct ice_aqc_get_set_rss_keys { 1909 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1910 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1911 }; 1912 1913 enum ice_lut_type { 1914 ICE_LUT_VSI = 0, 1915 ICE_LUT_PF = 1, 1916 ICE_LUT_GLOBAL = 2, 1917 }; 1918 1919 enum ice_lut_size { 1920 ICE_LUT_VSI_SIZE = 64, 1921 ICE_LUT_GLOBAL_SIZE = 512, 1922 ICE_LUT_PF_SIZE = 2048, 1923 }; 1924 1925 /* enum ice_aqc_lut_flags combines constants used to fill 1926 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1927 * LUT size and LUT type, last of which does not need neither shift nor mask. 1928 */ 1929 enum ice_aqc_lut_flags { 1930 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1931 ICE_AQC_LUT_SIZE_512 = BIT(2), 1932 ICE_AQC_LUT_SIZE_2K = BIT(3), 1933 1934 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1935 }; 1936 1937 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1938 struct ice_aqc_get_set_rss_lut { 1939 __le16 vsi_id; 1940 __le16 flags; 1941 __le32 reserved; 1942 __le32 addr_high; 1943 __le32 addr_low; 1944 }; 1945 1946 /* Sideband Control Interface Commands */ 1947 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1948 struct ice_aqc_neigh_dev_req { 1949 __le16 sb_data_len; 1950 u8 reserved[6]; 1951 __le32 addr_high; 1952 __le32 addr_low; 1953 }; 1954 1955 /* Add Tx LAN Queues (indirect 0x0C30) */ 1956 struct ice_aqc_add_txqs { 1957 u8 num_qgrps; 1958 u8 reserved[3]; 1959 __le32 reserved1; 1960 __le32 addr_high; 1961 __le32 addr_low; 1962 }; 1963 1964 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1965 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1966 */ 1967 struct ice_aqc_add_txqs_perq { 1968 __le16 txq_id; 1969 u8 rsvd[2]; 1970 __le32 q_teid; 1971 u8 txq_ctx[22]; 1972 u8 rsvd2[2]; 1973 struct ice_aqc_txsched_elem info; 1974 }; 1975 1976 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1977 * is an array of the following structs. Please note that the length of 1978 * each struct ice_aqc_add_tx_qgrp is variable due 1979 * to the variable number of queues in each group! 1980 */ 1981 struct ice_aqc_add_tx_qgrp { 1982 __le32 parent_teid; 1983 u8 num_txqs; 1984 u8 rsvd[3]; 1985 struct ice_aqc_add_txqs_perq txqs[]; 1986 }; 1987 1988 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1989 struct ice_aqc_dis_txqs { 1990 u8 cmd_type; 1991 #define ICE_AQC_Q_DIS_CMD_S 0 1992 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1993 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1994 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1995 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1996 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1997 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1998 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1999 u8 num_entries; 2000 __le16 vmvf_and_timeout; 2001 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2002 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2003 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2004 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2005 __le32 blocked_cgds; 2006 __le32 addr_high; 2007 __le32 addr_low; 2008 }; 2009 2010 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2011 * contains the following structures, arrayed one after the 2012 * other. 2013 * Note: Since the q_id is 16 bits wide, if the 2014 * number of queues is even, then 2 bytes of alignment MUST be 2015 * added before the start of the next group, to allow correct 2016 * alignment of the parent_teid field. 2017 */ 2018 struct ice_aqc_dis_txq_item { 2019 __le32 parent_teid; 2020 u8 num_qs; 2021 u8 rsvd; 2022 /* The length of the q_id array varies according to num_qs */ 2023 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2024 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2025 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2026 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2027 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2028 __le16 q_id[]; 2029 } __packed; 2030 2031 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2032 struct ice_aqc_cfg_txqs { 2033 u8 cmd_type; 2034 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2035 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2036 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2037 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2038 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2039 u8 num_qs; 2040 u8 port_num_chng; 2041 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2042 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2043 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2044 u8 time_out; 2045 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2046 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2047 __le32 blocked_cgds; 2048 __le32 addr_high; 2049 __le32 addr_low; 2050 }; 2051 2052 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2053 struct ice_aqc_cfg_txq_perq { 2054 __le16 q_handle; 2055 u8 tc; 2056 u8 rsvd; 2057 __le32 q_teid; 2058 }; 2059 2060 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2061 struct ice_aqc_cfg_txqs_buf { 2062 __le32 src_parent_teid; 2063 __le32 dst_parent_teid; 2064 struct ice_aqc_cfg_txq_perq queue_info[]; 2065 }; 2066 2067 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2068 struct ice_aqc_add_rdma_qset { 2069 u8 num_qset_grps; 2070 u8 reserved[7]; 2071 __le32 addr_high; 2072 __le32 addr_low; 2073 }; 2074 2075 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2076 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2077 */ 2078 struct ice_aqc_add_tx_rdma_qset_entry { 2079 __le16 tx_qset_id; 2080 u8 rsvd[2]; 2081 __le32 qset_teid; 2082 struct ice_aqc_txsched_elem info; 2083 }; 2084 2085 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2086 * is an array of the following structs. Please note that the length of 2087 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2088 * number of queues in each group! 2089 */ 2090 struct ice_aqc_add_rdma_qset_data { 2091 __le32 parent_teid; 2092 __le16 num_qsets; 2093 u8 rsvd[2]; 2094 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2095 }; 2096 2097 /* Configure Firmware Logging Command (indirect 0xFF09) 2098 * Logging Information Read Response (indirect 0xFF10) 2099 * Note: The 0xFF10 command has no input parameters. 2100 */ 2101 struct ice_aqc_fw_logging { 2102 u8 log_ctrl; 2103 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 2104 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 2105 u8 rsvd0; 2106 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 2107 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 2108 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 2109 u8 rsvd1[5]; 2110 __le32 addr_high; 2111 __le32 addr_low; 2112 }; 2113 2114 enum ice_aqc_fw_logging_mod { 2115 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2116 ICE_AQC_FW_LOG_ID_CTRL, 2117 ICE_AQC_FW_LOG_ID_LINK, 2118 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2119 ICE_AQC_FW_LOG_ID_DNL, 2120 ICE_AQC_FW_LOG_ID_I2C, 2121 ICE_AQC_FW_LOG_ID_SDP, 2122 ICE_AQC_FW_LOG_ID_MDIO, 2123 ICE_AQC_FW_LOG_ID_ADMINQ, 2124 ICE_AQC_FW_LOG_ID_HDMA, 2125 ICE_AQC_FW_LOG_ID_LLDP, 2126 ICE_AQC_FW_LOG_ID_DCBX, 2127 ICE_AQC_FW_LOG_ID_DCB, 2128 ICE_AQC_FW_LOG_ID_NETPROXY, 2129 ICE_AQC_FW_LOG_ID_NVM, 2130 ICE_AQC_FW_LOG_ID_AUTH, 2131 ICE_AQC_FW_LOG_ID_VPD, 2132 ICE_AQC_FW_LOG_ID_IOSF, 2133 ICE_AQC_FW_LOG_ID_PARSER, 2134 ICE_AQC_FW_LOG_ID_SW, 2135 ICE_AQC_FW_LOG_ID_SCHEDULER, 2136 ICE_AQC_FW_LOG_ID_TXQ, 2137 ICE_AQC_FW_LOG_ID_RSVD, 2138 ICE_AQC_FW_LOG_ID_POST, 2139 ICE_AQC_FW_LOG_ID_WATCHDOG, 2140 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2141 ICE_AQC_FW_LOG_ID_MNG, 2142 ICE_AQC_FW_LOG_ID_MAX, 2143 }; 2144 2145 /* Defines for both above FW logging command/response buffers */ 2146 #define ICE_AQC_FW_LOG_ID_S 0 2147 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 2148 2149 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 2150 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 2151 2152 #define ICE_AQC_FW_LOG_EN_S 12 2153 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 2154 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 2155 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 2156 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 2157 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 2158 2159 /* Get/Clear FW Log (indirect 0xFF11) */ 2160 struct ice_aqc_get_clear_fw_log { 2161 u8 flags; 2162 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 2163 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 2164 u8 rsvd1[7]; 2165 __le32 addr_high; 2166 __le32 addr_low; 2167 }; 2168 2169 /* Download Package (indirect 0x0C40) */ 2170 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2171 struct ice_aqc_download_pkg { 2172 u8 flags; 2173 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2174 u8 reserved[3]; 2175 __le32 reserved1; 2176 __le32 addr_high; 2177 __le32 addr_low; 2178 }; 2179 2180 struct ice_aqc_download_pkg_resp { 2181 __le32 error_offset; 2182 __le32 error_info; 2183 __le32 addr_high; 2184 __le32 addr_low; 2185 }; 2186 2187 /* Get Package Info List (indirect 0x0C43) */ 2188 struct ice_aqc_get_pkg_info_list { 2189 __le32 reserved1; 2190 __le32 reserved2; 2191 __le32 addr_high; 2192 __le32 addr_low; 2193 }; 2194 2195 /* Version format for packages */ 2196 struct ice_pkg_ver { 2197 u8 major; 2198 u8 minor; 2199 u8 update; 2200 u8 draft; 2201 }; 2202 2203 #define ICE_PKG_NAME_SIZE 32 2204 #define ICE_SEG_ID_SIZE 28 2205 #define ICE_SEG_NAME_SIZE 28 2206 2207 struct ice_aqc_get_pkg_info { 2208 struct ice_pkg_ver ver; 2209 char name[ICE_SEG_NAME_SIZE]; 2210 __le32 track_id; 2211 u8 is_in_nvm; 2212 u8 is_active; 2213 u8 is_active_at_boot; 2214 u8 is_modified; 2215 }; 2216 2217 /* Get Package Info List response buffer format (0x0C43) */ 2218 struct ice_aqc_get_pkg_info_resp { 2219 __le32 count; 2220 struct ice_aqc_get_pkg_info pkg_info[]; 2221 }; 2222 2223 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2224 struct ice_aqc_get_cgu_abilities { 2225 u8 num_inputs; 2226 u8 num_outputs; 2227 u8 pps_dpll_idx; 2228 u8 eec_dpll_idx; 2229 __le32 max_in_freq; 2230 __le32 max_in_phase_adj; 2231 __le32 max_out_freq; 2232 __le32 max_out_phase_adj; 2233 u8 cgu_part_num; 2234 u8 rsvd[3]; 2235 }; 2236 2237 /* Set CGU input config (direct 0x0C62) */ 2238 struct ice_aqc_set_cgu_input_config { 2239 u8 input_idx; 2240 u8 flags1; 2241 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2242 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2243 u8 flags2; 2244 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2245 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2246 u8 rsvd; 2247 __le32 freq; 2248 __le32 phase_delay; 2249 u8 rsvd2[2]; 2250 __le16 node_handle; 2251 }; 2252 2253 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2254 struct ice_aqc_get_cgu_input_config { 2255 u8 input_idx; 2256 u8 status; 2257 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2258 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2259 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2260 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2261 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2262 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2263 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2264 u8 type; 2265 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2266 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2267 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2268 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2269 u8 flags1; 2270 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2271 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2272 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2273 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2274 __le32 freq; 2275 __le32 phase_delay; 2276 u8 flags2; 2277 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2278 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2279 u8 rsvd[1]; 2280 __le16 node_handle; 2281 }; 2282 2283 /* Set CGU output config (direct 0x0C64) */ 2284 struct ice_aqc_set_cgu_output_config { 2285 u8 output_idx; 2286 u8 flags; 2287 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2288 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2289 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2290 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2291 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2292 u8 src_sel; 2293 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2294 u8 rsvd; 2295 __le32 freq; 2296 __le32 phase_delay; 2297 u8 rsvd2[2]; 2298 __le16 node_handle; 2299 }; 2300 2301 /* Get CGU output config (direct 0x0C65) */ 2302 struct ice_aqc_get_cgu_output_config { 2303 u8 output_idx; 2304 u8 flags; 2305 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2306 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2307 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2308 u8 src_sel; 2309 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2310 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2311 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2312 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2313 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2314 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2315 u8 rsvd; 2316 __le32 freq; 2317 __le32 src_freq; 2318 u8 rsvd2[2]; 2319 __le16 node_handle; 2320 }; 2321 2322 /* Get CGU DPLL status (direct 0x0C66) */ 2323 struct ice_aqc_get_cgu_dpll_status { 2324 u8 dpll_num; 2325 u8 ref_state; 2326 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2327 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2328 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2329 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2330 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2331 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2332 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2333 u8 dpll_state; 2334 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2335 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2336 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2337 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2338 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2339 u8 config; 2340 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2341 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2342 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2343 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2344 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2345 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2346 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2347 __le32 phase_offset_h; 2348 __le32 phase_offset_l; 2349 u8 eec_mode; 2350 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2351 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2352 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2353 u8 rsvd[1]; 2354 __le16 node_handle; 2355 }; 2356 2357 /* Set CGU DPLL config (direct 0x0C67) */ 2358 struct ice_aqc_set_cgu_dpll_config { 2359 u8 dpll_num; 2360 u8 ref_state; 2361 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2362 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2363 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2364 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2365 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2366 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2367 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2368 u8 rsvd; 2369 u8 config; 2370 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2371 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2372 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2373 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2374 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2375 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2376 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2377 u8 rsvd2[8]; 2378 u8 eec_mode; 2379 u8 rsvd3[1]; 2380 __le16 node_handle; 2381 }; 2382 2383 /* Set CGU reference priority (direct 0x0C68) */ 2384 struct ice_aqc_set_cgu_ref_prio { 2385 u8 dpll_num; 2386 u8 ref_idx; 2387 u8 ref_priority; 2388 u8 rsvd[11]; 2389 __le16 node_handle; 2390 }; 2391 2392 /* Get CGU reference priority (direct 0x0C69) */ 2393 struct ice_aqc_get_cgu_ref_prio { 2394 u8 dpll_num; 2395 u8 ref_idx; 2396 u8 ref_priority; /* Valid only in response */ 2397 u8 rsvd[13]; 2398 }; 2399 2400 /* Get CGU info (direct 0x0C6A) */ 2401 struct ice_aqc_get_cgu_info { 2402 __le32 cgu_id; 2403 __le32 cgu_cfg_ver; 2404 __le32 cgu_fw_ver; 2405 u8 node_part_num; 2406 u8 dev_rev; 2407 __le16 node_handle; 2408 }; 2409 2410 /* Driver Shared Parameters (direct, 0x0C90) */ 2411 struct ice_aqc_driver_shared_params { 2412 u8 set_or_get_op; 2413 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2414 #define ICE_AQC_DRIVER_PARAM_SET 0 2415 #define ICE_AQC_DRIVER_PARAM_GET 1 2416 u8 param_indx; 2417 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2418 u8 rsvd[2]; 2419 __le32 param_val; 2420 __le32 addr_high; 2421 __le32 addr_low; 2422 }; 2423 2424 /* Lan Queue Overflow Event (direct, 0x1001) */ 2425 struct ice_aqc_event_lan_overflow { 2426 __le32 prtdcb_ruptq; 2427 __le32 qtx_ctl; 2428 u8 reserved[8]; 2429 }; 2430 2431 /** 2432 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2433 * @flags: ICE_AQ_FLAG_* flags 2434 * @opcode: AQ command opcode 2435 * @datalen: length in bytes of indirect/external data buffer 2436 * @retval: return value from firmware 2437 * @cookie_high: opaque data high-half 2438 * @cookie_low: opaque data low-half 2439 * @params: command-specific parameters 2440 * 2441 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2442 * (ATQ). The firmware writes back onto the command descriptor and returns 2443 * the result of the command. Asynchronous events that are not an immediate 2444 * result of the command are written to the Admin Receive Queue (ARQ) using 2445 * the same descriptor format. Descriptors are in little-endian notation with 2446 * 32-bit words. 2447 */ 2448 struct ice_aq_desc { 2449 __le16 flags; 2450 __le16 opcode; 2451 __le16 datalen; 2452 __le16 retval; 2453 __le32 cookie_high; 2454 __le32 cookie_low; 2455 union { 2456 u8 raw[16]; 2457 struct ice_aqc_generic generic; 2458 struct ice_aqc_get_ver get_ver; 2459 struct ice_aqc_driver_ver driver_ver; 2460 struct ice_aqc_q_shutdown q_shutdown; 2461 struct ice_aqc_req_res res_owner; 2462 struct ice_aqc_manage_mac_read mac_read; 2463 struct ice_aqc_manage_mac_write mac_write; 2464 struct ice_aqc_clear_pxe clear_pxe; 2465 struct ice_aqc_list_caps get_cap; 2466 struct ice_aqc_get_phy_caps get_phy; 2467 struct ice_aqc_set_phy_cfg set_phy; 2468 struct ice_aqc_restart_an restart_an; 2469 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2470 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2471 struct ice_aqc_get_sensor_reading get_sensor_reading; 2472 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2473 struct ice_aqc_gpio read_write_gpio; 2474 struct ice_aqc_sff_eeprom read_write_sff_param; 2475 struct ice_aqc_set_port_id_led set_port_id_led; 2476 struct ice_aqc_get_port_options get_port_options; 2477 struct ice_aqc_set_port_option set_port_option; 2478 struct ice_aqc_get_sw_cfg get_sw_conf; 2479 struct ice_aqc_set_port_params set_port_params; 2480 struct ice_aqc_sw_rules sw_rules; 2481 struct ice_aqc_add_get_recipe add_get_recipe; 2482 struct ice_aqc_recipe_to_profile recipe_to_profile; 2483 struct ice_aqc_get_topo get_topo; 2484 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2485 struct ice_aqc_query_txsched_res query_sched_res; 2486 struct ice_aqc_query_port_ets port_ets; 2487 struct ice_aqc_rl_profile rl_profile; 2488 struct ice_aqc_nvm nvm; 2489 struct ice_aqc_nvm_checksum nvm_checksum; 2490 struct ice_aqc_nvm_pkg_data pkg_data; 2491 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2492 struct ice_aqc_pf_vf_msg virt; 2493 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2494 struct ice_aqc_lldp_get_mib lldp_get_mib; 2495 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2496 struct ice_aqc_lldp_stop lldp_stop; 2497 struct ice_aqc_lldp_start lldp_start; 2498 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2499 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2500 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2501 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2502 struct ice_aqc_get_set_rss_key get_set_rss_key; 2503 struct ice_aqc_neigh_dev_req neigh_dev; 2504 struct ice_aqc_add_txqs add_txqs; 2505 struct ice_aqc_dis_txqs dis_txqs; 2506 struct ice_aqc_cfg_txqs cfg_txqs; 2507 struct ice_aqc_add_rdma_qset add_rdma_qset; 2508 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2509 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2510 struct ice_aqc_fw_logging fw_logging; 2511 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 2512 struct ice_aqc_download_pkg download_pkg; 2513 struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2514 struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2515 struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2516 struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2517 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2518 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2519 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2520 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2521 struct ice_aqc_get_cgu_info get_cgu_info; 2522 struct ice_aqc_driver_shared_params drv_shared_params; 2523 struct ice_aqc_set_mac_lb set_mac_lb; 2524 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2525 struct ice_aqc_set_mac_cfg set_mac_cfg; 2526 struct ice_aqc_set_event_mask set_event_mask; 2527 struct ice_aqc_get_link_status get_link_status; 2528 struct ice_aqc_event_lan_overflow lan_overflow; 2529 struct ice_aqc_get_link_topo get_link_topo; 2530 struct ice_aqc_i2c read_write_i2c; 2531 struct ice_aqc_read_i2c_resp read_i2c_resp; 2532 } params; 2533 }; 2534 2535 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2536 #define ICE_AQ_LG_BUF 512 2537 2538 #define ICE_AQ_FLAG_ERR_S 2 2539 #define ICE_AQ_FLAG_LB_S 9 2540 #define ICE_AQ_FLAG_RD_S 10 2541 #define ICE_AQ_FLAG_BUF_S 12 2542 #define ICE_AQ_FLAG_SI_S 13 2543 2544 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2545 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2546 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2547 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2548 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2549 2550 /* error codes */ 2551 enum ice_aq_err { 2552 ICE_AQ_RC_OK = 0, /* Success */ 2553 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2554 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2555 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2556 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2557 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2558 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2559 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2560 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2561 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2562 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2563 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2564 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2565 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2566 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2567 }; 2568 2569 /* Admin Queue command opcodes */ 2570 enum ice_adminq_opc { 2571 /* AQ commands */ 2572 ice_aqc_opc_get_ver = 0x0001, 2573 ice_aqc_opc_driver_ver = 0x0002, 2574 ice_aqc_opc_q_shutdown = 0x0003, 2575 2576 /* resource ownership */ 2577 ice_aqc_opc_req_res = 0x0008, 2578 ice_aqc_opc_release_res = 0x0009, 2579 2580 /* device/function capabilities */ 2581 ice_aqc_opc_list_func_caps = 0x000A, 2582 ice_aqc_opc_list_dev_caps = 0x000B, 2583 2584 /* manage MAC address */ 2585 ice_aqc_opc_manage_mac_read = 0x0107, 2586 ice_aqc_opc_manage_mac_write = 0x0108, 2587 2588 /* PXE */ 2589 ice_aqc_opc_clear_pxe_mode = 0x0110, 2590 2591 /* internal switch commands */ 2592 ice_aqc_opc_get_sw_cfg = 0x0200, 2593 ice_aqc_opc_set_port_params = 0x0203, 2594 2595 /* Alloc/Free/Get Resources */ 2596 ice_aqc_opc_alloc_res = 0x0208, 2597 ice_aqc_opc_free_res = 0x0209, 2598 ice_aqc_opc_share_res = 0x020B, 2599 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2600 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2601 2602 /* VSI commands */ 2603 ice_aqc_opc_add_vsi = 0x0210, 2604 ice_aqc_opc_update_vsi = 0x0211, 2605 ice_aqc_opc_free_vsi = 0x0213, 2606 2607 /* recipe commands */ 2608 ice_aqc_opc_add_recipe = 0x0290, 2609 ice_aqc_opc_recipe_to_profile = 0x0291, 2610 ice_aqc_opc_get_recipe = 0x0292, 2611 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2612 2613 /* switch rules population commands */ 2614 ice_aqc_opc_add_sw_rules = 0x02A0, 2615 ice_aqc_opc_update_sw_rules = 0x02A1, 2616 ice_aqc_opc_remove_sw_rules = 0x02A2, 2617 2618 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2619 2620 /* DCB commands */ 2621 ice_aqc_opc_query_pfc_mode = 0x0302, 2622 ice_aqc_opc_set_pfc_mode = 0x0303, 2623 2624 /* transmit scheduler commands */ 2625 ice_aqc_opc_get_dflt_topo = 0x0400, 2626 ice_aqc_opc_add_sched_elems = 0x0401, 2627 ice_aqc_opc_cfg_sched_elems = 0x0403, 2628 ice_aqc_opc_get_sched_elems = 0x0404, 2629 ice_aqc_opc_move_sched_elems = 0x0408, 2630 ice_aqc_opc_suspend_sched_elems = 0x0409, 2631 ice_aqc_opc_resume_sched_elems = 0x040A, 2632 ice_aqc_opc_query_port_ets = 0x040E, 2633 ice_aqc_opc_delete_sched_elems = 0x040F, 2634 ice_aqc_opc_add_rl_profiles = 0x0410, 2635 ice_aqc_opc_query_sched_res = 0x0412, 2636 ice_aqc_opc_remove_rl_profiles = 0x0415, 2637 2638 /* PHY commands */ 2639 ice_aqc_opc_get_phy_caps = 0x0600, 2640 ice_aqc_opc_set_phy_cfg = 0x0601, 2641 ice_aqc_opc_set_mac_cfg = 0x0603, 2642 ice_aqc_opc_restart_an = 0x0605, 2643 ice_aqc_opc_get_link_status = 0x0607, 2644 ice_aqc_opc_set_event_mask = 0x0613, 2645 ice_aqc_opc_set_mac_lb = 0x0620, 2646 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2647 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2648 ice_aqc_opc_get_sensor_reading = 0x0632, 2649 ice_aqc_opc_get_link_topo = 0x06E0, 2650 ice_aqc_opc_read_i2c = 0x06E2, 2651 ice_aqc_opc_write_i2c = 0x06E3, 2652 ice_aqc_opc_set_port_id_led = 0x06E9, 2653 ice_aqc_opc_get_port_options = 0x06EA, 2654 ice_aqc_opc_set_port_option = 0x06EB, 2655 ice_aqc_opc_set_gpio = 0x06EC, 2656 ice_aqc_opc_get_gpio = 0x06ED, 2657 ice_aqc_opc_sff_eeprom = 0x06EE, 2658 2659 /* NVM commands */ 2660 ice_aqc_opc_nvm_read = 0x0701, 2661 ice_aqc_opc_nvm_erase = 0x0702, 2662 ice_aqc_opc_nvm_write = 0x0703, 2663 ice_aqc_opc_nvm_checksum = 0x0706, 2664 ice_aqc_opc_nvm_write_activate = 0x0707, 2665 ice_aqc_opc_nvm_update_empr = 0x0709, 2666 ice_aqc_opc_nvm_pkg_data = 0x070A, 2667 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2668 2669 /* PF/VF mailbox commands */ 2670 ice_mbx_opc_send_msg_to_pf = 0x0801, 2671 ice_mbx_opc_send_msg_to_vf = 0x0802, 2672 /* LLDP commands */ 2673 ice_aqc_opc_lldp_get_mib = 0x0A00, 2674 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2675 ice_aqc_opc_lldp_stop = 0x0A05, 2676 ice_aqc_opc_lldp_start = 0x0A06, 2677 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2678 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2679 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2680 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2681 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2682 2683 /* RSS commands */ 2684 ice_aqc_opc_set_rss_key = 0x0B02, 2685 ice_aqc_opc_set_rss_lut = 0x0B03, 2686 ice_aqc_opc_get_rss_key = 0x0B04, 2687 ice_aqc_opc_get_rss_lut = 0x0B05, 2688 2689 /* Sideband Control Interface commands */ 2690 ice_aqc_opc_neighbour_device_request = 0x0C00, 2691 2692 /* Tx queue handling commands/events */ 2693 ice_aqc_opc_add_txqs = 0x0C30, 2694 ice_aqc_opc_dis_txqs = 0x0C31, 2695 ice_aqc_opc_cfg_txqs = 0x0C32, 2696 ice_aqc_opc_add_rdma_qset = 0x0C33, 2697 2698 /* package commands */ 2699 ice_aqc_opc_download_pkg = 0x0C40, 2700 ice_aqc_opc_upload_section = 0x0C41, 2701 ice_aqc_opc_update_pkg = 0x0C42, 2702 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2703 2704 /* 1588/SyncE commands/events */ 2705 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2706 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2707 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2708 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2709 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2710 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2711 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2712 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2713 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2714 ice_aqc_opc_get_cgu_info = 0x0C6A, 2715 2716 ice_aqc_opc_driver_shared_params = 0x0C90, 2717 2718 /* Standalone Commands/Events */ 2719 ice_aqc_opc_event_lan_overflow = 0x1001, 2720 2721 /* debug commands */ 2722 ice_aqc_opc_fw_logging = 0xFF09, 2723 ice_aqc_opc_fw_logging_info = 0xFF10, 2724 }; 2725 2726 #endif /* _ICE_ADMINQ_CMD_H_ */ 2727