1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 #define ICE_AQC_CAPS_NVM_VER 0x0048 113 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 114 #define ICE_AQC_CAPS_OROM_VER 0x004A 115 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 116 #define ICE_AQC_CAPS_NET_VER 0x004C 117 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 118 #define ICE_AQC_CAPS_RDMA 0x0051 119 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 120 121 u8 major_ver; 122 u8 minor_ver; 123 /* Number of resources described by this capability */ 124 __le32 number; 125 /* Only meaningful for some types of resources */ 126 __le32 logical_id; 127 /* Only meaningful for some types of resources */ 128 __le32 phys_id; 129 __le64 rsvd1; 130 __le64 rsvd2; 131 }; 132 133 /* Manage MAC address, read command - indirect (0x0107) 134 * This struct is also used for the response 135 */ 136 struct ice_aqc_manage_mac_read { 137 __le16 flags; /* Zeroed by device driver */ 138 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 139 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 140 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 141 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 142 #define ICE_AQC_MAN_MAC_READ_S 4 143 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 144 u8 rsvd[2]; 145 u8 num_addr; /* Used in response */ 146 u8 rsvd1[3]; 147 __le32 addr_high; 148 __le32 addr_low; 149 }; 150 151 /* Response buffer format for manage MAC read command */ 152 struct ice_aqc_manage_mac_read_resp { 153 u8 lport_num; 154 u8 addr_type; 155 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 156 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 157 u8 mac_addr[ETH_ALEN]; 158 }; 159 160 /* Manage MAC address, write command - direct (0x0108) */ 161 struct ice_aqc_manage_mac_write { 162 u8 rsvd; 163 u8 flags; 164 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 165 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 166 #define ICE_AQC_MAN_MAC_WR_S 6 167 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 168 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 169 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 170 /* byte stream in network order */ 171 u8 mac_addr[ETH_ALEN]; 172 __le32 addr_high; 173 __le32 addr_low; 174 }; 175 176 /* Clear PXE Command and response (direct 0x0110) */ 177 struct ice_aqc_clear_pxe { 178 u8 rx_cnt; 179 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 180 u8 reserved[15]; 181 }; 182 183 /* Get switch configuration (0x0200) */ 184 struct ice_aqc_get_sw_cfg { 185 /* Reserved for command and copy of request flags for response */ 186 __le16 flags; 187 /* First desc in case of command and next_elem in case of response 188 * In case of response, if it is not zero, means all the configuration 189 * was not returned and new command shall be sent with this value in 190 * the 'first desc' field 191 */ 192 __le16 element; 193 /* Reserved for command, only used for response */ 194 __le16 num_elems; 195 __le16 rsvd; 196 __le32 addr_high; 197 __le32 addr_low; 198 }; 199 200 /* Each entry in the response buffer is of the following type: */ 201 struct ice_aqc_get_sw_cfg_resp_elem { 202 /* VSI/Port Number */ 203 __le16 vsi_port_num; 204 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 206 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 207 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 209 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 210 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 211 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 212 213 /* SWID VSI/Port belongs to */ 214 __le16 swid; 215 216 /* Bit 14..0 : PF/VF number VSI belongs to 217 * Bit 15 : VF indication bit 218 */ 219 __le16 pf_vf_num; 220 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 222 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 223 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 224 }; 225 226 /* These resource type defines are used for all switch resource 227 * commands where a resource type is required, such as: 228 * Get Resource Allocation command (indirect 0x0204) 229 * Allocate Resources command (indirect 0x0208) 230 * Free Resources command (indirect 0x0209) 231 * Get Allocated Resource Descriptors Command (indirect 0x020A) 232 */ 233 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 234 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 235 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 236 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 237 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 238 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 239 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 240 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 241 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 242 243 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 244 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 245 246 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 247 248 #define ICE_AQC_RES_TYPE_S 0 249 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 250 251 /* Allocate Resources command (indirect 0x0208) 252 * Free Resources command (indirect 0x0209) 253 */ 254 struct ice_aqc_alloc_free_res_cmd { 255 __le16 num_entries; /* Number of Resource entries */ 256 u8 reserved[6]; 257 __le32 addr_high; 258 __le32 addr_low; 259 }; 260 261 /* Resource descriptor */ 262 struct ice_aqc_res_elem { 263 union { 264 __le16 sw_resp; 265 __le16 flu_resp; 266 } e; 267 }; 268 269 /* Buffer for Allocate/Free Resources commands */ 270 struct ice_aqc_alloc_free_res_elem { 271 __le16 res_type; /* Types defined above cmd 0x0204 */ 272 #define ICE_AQC_RES_TYPE_SHARED_S 7 273 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 274 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 275 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 276 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 277 __le16 num_elems; 278 struct ice_aqc_res_elem elem[]; 279 }; 280 281 /* Add VSI (indirect 0x0210) 282 * Update VSI (indirect 0x0211) 283 * Get VSI (indirect 0x0212) 284 * Free VSI (indirect 0x0213) 285 */ 286 struct ice_aqc_add_get_update_free_vsi { 287 __le16 vsi_num; 288 #define ICE_AQ_VSI_NUM_S 0 289 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 290 #define ICE_AQ_VSI_IS_VALID BIT(15) 291 __le16 cmd_flags; 292 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 293 u8 vf_id; 294 u8 reserved; 295 __le16 vsi_flags; 296 #define ICE_AQ_VSI_TYPE_S 0 297 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 298 #define ICE_AQ_VSI_TYPE_VF 0x0 299 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 300 #define ICE_AQ_VSI_TYPE_PF 0x2 301 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 302 __le32 addr_high; 303 __le32 addr_low; 304 }; 305 306 /* Response descriptor for: 307 * Add VSI (indirect 0x0210) 308 * Update VSI (indirect 0x0211) 309 * Free VSI (indirect 0x0213) 310 */ 311 struct ice_aqc_add_update_free_vsi_resp { 312 __le16 vsi_num; 313 __le16 ext_status; 314 __le16 vsi_used; 315 __le16 vsi_free; 316 __le32 addr_high; 317 __le32 addr_low; 318 }; 319 320 struct ice_aqc_vsi_props { 321 __le16 valid_sections; 322 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 323 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 324 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 325 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 326 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 327 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 328 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 329 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 330 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 331 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 332 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 333 /* switch section */ 334 u8 sw_id; 335 u8 sw_flags; 336 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 337 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 338 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 339 u8 sw_flags2; 340 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 341 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 342 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 343 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 344 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 345 u8 veb_stat_id; 346 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 347 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 348 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 349 /* security section */ 350 u8 sec_flags; 351 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 352 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 353 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 354 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 355 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 356 u8 sec_reserved; 357 /* VLAN section */ 358 __le16 pvid; /* VLANS include priority bits */ 359 u8 pvlan_reserved[2]; 360 u8 vlan_flags; 361 #define ICE_AQ_VSI_VLAN_MODE_S 0 362 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 363 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 364 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 365 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 366 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 367 #define ICE_AQ_VSI_VLAN_EMOD_S 3 368 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 369 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 370 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 371 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 372 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 373 u8 pvlan_reserved2[3]; 374 /* ingress egress up sections */ 375 __le32 ingress_table; /* bitmap, 3 bits per up */ 376 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 377 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 378 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 379 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 380 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 381 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 382 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 383 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 384 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 385 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 386 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 387 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 388 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 389 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 390 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 391 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 392 __le32 egress_table; /* same defines as for ingress table */ 393 /* outer tags section */ 394 __le16 outer_tag; 395 u8 outer_tag_flags; 396 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 397 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 398 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 399 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 400 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 401 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 402 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 403 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 404 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 405 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 406 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 407 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 408 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 409 u8 outer_tag_reserved; 410 /* queue mapping section */ 411 __le16 mapping_flags; 412 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 413 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 414 __le16 q_mapping[16]; 415 #define ICE_AQ_VSI_Q_S 0 416 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 417 __le16 tc_mapping[8]; 418 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 419 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 420 #define ICE_AQ_VSI_TC_Q_NUM_S 11 421 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 422 /* queueing option section */ 423 u8 q_opt_rss; 424 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 425 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 426 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 427 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 428 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 429 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 430 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 431 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 432 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 433 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 434 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 435 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 436 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 437 u8 q_opt_tc; 438 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 439 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 440 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 441 u8 q_opt_flags; 442 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 443 u8 q_opt_reserved[3]; 444 /* outer up section */ 445 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 446 /* section 10 */ 447 __le16 sect_10_reserved; 448 /* flow director section */ 449 __le16 fd_options; 450 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 451 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 452 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 453 __le16 max_fd_fltr_dedicated; 454 __le16 max_fd_fltr_shared; 455 __le16 fd_def_q; 456 #define ICE_AQ_VSI_FD_DEF_Q_S 0 457 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 458 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 459 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 460 __le16 fd_report_opt; 461 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 462 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 463 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 464 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 465 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 466 /* PASID section */ 467 __le32 pasid_id; 468 #define ICE_AQ_VSI_PASID_ID_S 0 469 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 470 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 471 u8 reserved[24]; 472 }; 473 474 #define ICE_MAX_NUM_RECIPES 64 475 476 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 477 */ 478 struct ice_aqc_sw_rules { 479 /* ops: add switch rules, referring the number of rules. 480 * ops: update switch rules, referring the number of filters 481 * ops: remove switch rules, referring the entry index. 482 * ops: get switch rules, referring to the number of filters. 483 */ 484 __le16 num_rules_fltr_entry_index; 485 u8 reserved[6]; 486 __le32 addr_high; 487 __le32 addr_low; 488 }; 489 490 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 491 * This structures describes the lookup rules and associated actions. "index" 492 * is returned as part of a response to a successful Add command, and can be 493 * used to identify the rule for Update/Get/Remove commands. 494 */ 495 struct ice_sw_rule_lkup_rx_tx { 496 __le16 recipe_id; 497 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 498 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 499 __le16 src; 500 __le32 act; 501 502 /* Bit 0:1 - Action type */ 503 #define ICE_SINGLE_ACT_TYPE_S 0x00 504 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 505 506 /* Bit 2 - Loop back enable 507 * Bit 3 - LAN enable 508 */ 509 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 510 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 511 512 /* Action type = 0 - Forward to VSI or VSI list */ 513 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 514 515 #define ICE_SINGLE_ACT_VSI_ID_S 4 516 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 517 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 518 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 519 /* This bit needs to be set if action is forward to VSI list */ 520 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 521 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 522 #define ICE_SINGLE_ACT_DROP BIT(18) 523 524 /* Action type = 1 - Forward to Queue of Queue group */ 525 #define ICE_SINGLE_ACT_TO_Q 0x1 526 #define ICE_SINGLE_ACT_Q_INDEX_S 4 527 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 528 #define ICE_SINGLE_ACT_Q_REGION_S 15 529 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 530 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 531 532 /* Action type = 2 - Prune */ 533 #define ICE_SINGLE_ACT_PRUNE 0x2 534 #define ICE_SINGLE_ACT_EGRESS BIT(15) 535 #define ICE_SINGLE_ACT_INGRESS BIT(16) 536 #define ICE_SINGLE_ACT_PRUNET BIT(17) 537 /* Bit 18 should be set to 0 for this action */ 538 539 /* Action type = 2 - Pointer */ 540 #define ICE_SINGLE_ACT_PTR 0x2 541 #define ICE_SINGLE_ACT_PTR_VAL_S 4 542 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 543 /* Bit 18 should be set to 1 */ 544 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 545 546 /* Action type = 3 - Other actions. Last two bits 547 * are other action identifier 548 */ 549 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 550 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 551 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 552 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 553 554 /* Bit 17:18 - Defines other actions */ 555 /* Other action = 0 - Mirror VSI */ 556 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 557 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 558 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 559 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 560 561 /* Other action = 3 - Set Stat count */ 562 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 563 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 564 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 565 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 566 567 __le16 index; /* The index of the rule in the lookup table */ 568 /* Length and values of the header to be matched per recipe or 569 * lookup-type 570 */ 571 __le16 hdr_len; 572 u8 hdr[]; 573 }; 574 575 /* Add/Update/Remove large action command/response entry 576 * "index" is returned as part of a response to a successful Add command, and 577 * can be used to identify the action for Update/Get/Remove commands. 578 */ 579 struct ice_sw_rule_lg_act { 580 __le16 index; /* Index in large action table */ 581 __le16 size; 582 /* Max number of large actions */ 583 #define ICE_MAX_LG_ACT 4 584 /* Bit 0:1 - Action type */ 585 #define ICE_LG_ACT_TYPE_S 0 586 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 587 588 /* Action type = 0 - Forward to VSI or VSI list */ 589 #define ICE_LG_ACT_VSI_FORWARDING 0 590 #define ICE_LG_ACT_VSI_ID_S 3 591 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 592 #define ICE_LG_ACT_VSI_LIST_ID_S 3 593 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 594 /* This bit needs to be set if action is forward to VSI list */ 595 #define ICE_LG_ACT_VSI_LIST BIT(13) 596 597 #define ICE_LG_ACT_VALID_BIT BIT(16) 598 599 /* Action type = 1 - Forward to Queue of Queue group */ 600 #define ICE_LG_ACT_TO_Q 0x1 601 #define ICE_LG_ACT_Q_INDEX_S 3 602 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 603 #define ICE_LG_ACT_Q_REGION_S 14 604 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 605 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 606 607 /* Action type = 2 - Prune */ 608 #define ICE_LG_ACT_PRUNE 0x2 609 #define ICE_LG_ACT_EGRESS BIT(14) 610 #define ICE_LG_ACT_INGRESS BIT(15) 611 #define ICE_LG_ACT_PRUNET BIT(16) 612 613 /* Action type = 3 - Mirror VSI */ 614 #define ICE_LG_OTHER_ACT_MIRROR 0x3 615 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 616 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 617 618 /* Action type = 5 - Generic Value */ 619 #define ICE_LG_ACT_GENERIC 0x5 620 #define ICE_LG_ACT_GENERIC_VALUE_S 3 621 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 622 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 623 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 624 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 625 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 626 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 627 628 /* Action = 7 - Set Stat count */ 629 #define ICE_LG_ACT_STAT_COUNT 0x7 630 #define ICE_LG_ACT_STAT_COUNT_S 3 631 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 632 __le32 act[]; /* array of size for actions */ 633 }; 634 635 /* Add/Update/Remove VSI list command/response entry 636 * "index" is returned as part of a response to a successful Add command, and 637 * can be used to identify the VSI list for Update/Get/Remove commands. 638 */ 639 struct ice_sw_rule_vsi_list { 640 __le16 index; /* Index of VSI/Prune list */ 641 __le16 number_vsi; 642 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 643 }; 644 645 /* Query VSI list command/response entry */ 646 struct ice_sw_rule_vsi_list_query { 647 __le16 index; 648 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 649 } __packed; 650 651 /* Add switch rule response: 652 * Content of return buffer is same as the input buffer. The status field and 653 * LUT index are updated as part of the response 654 */ 655 struct ice_aqc_sw_rules_elem { 656 __le16 type; /* Switch rule type, one of T_... */ 657 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 658 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 659 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 660 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 661 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 662 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 663 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 664 __le16 status; 665 union { 666 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 667 struct ice_sw_rule_lg_act lg_act; 668 struct ice_sw_rule_vsi_list vsi_list; 669 struct ice_sw_rule_vsi_list_query vsi_list_query; 670 } __packed pdata; 671 }; 672 673 /* Get Default Topology (indirect 0x0400) */ 674 struct ice_aqc_get_topo { 675 u8 port_num; 676 u8 num_branches; 677 __le16 reserved1; 678 __le32 reserved2; 679 __le32 addr_high; 680 __le32 addr_low; 681 }; 682 683 /* Update TSE (indirect 0x0403) 684 * Get TSE (indirect 0x0404) 685 * Add TSE (indirect 0x0401) 686 * Delete TSE (indirect 0x040F) 687 * Move TSE (indirect 0x0408) 688 * Suspend Nodes (indirect 0x0409) 689 * Resume Nodes (indirect 0x040A) 690 */ 691 struct ice_aqc_sched_elem_cmd { 692 __le16 num_elem_req; /* Used by commands */ 693 __le16 num_elem_resp; /* Used by responses */ 694 __le32 reserved; 695 __le32 addr_high; 696 __le32 addr_low; 697 }; 698 699 struct ice_aqc_txsched_move_grp_info_hdr { 700 __le32 src_parent_teid; 701 __le32 dest_parent_teid; 702 __le16 num_elems; 703 __le16 reserved; 704 }; 705 706 struct ice_aqc_move_elem { 707 struct ice_aqc_txsched_move_grp_info_hdr hdr; 708 __le32 teid[]; 709 }; 710 711 struct ice_aqc_elem_info_bw { 712 __le16 bw_profile_idx; 713 __le16 bw_alloc; 714 }; 715 716 struct ice_aqc_txsched_elem { 717 u8 elem_type; /* Special field, reserved for some aq calls */ 718 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 719 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 720 #define ICE_AQC_ELEM_TYPE_TC 0x2 721 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 722 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 723 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 724 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 725 u8 valid_sections; 726 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 727 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 728 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 729 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 730 u8 generic; 731 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 732 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 733 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 734 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 735 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 736 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 737 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 738 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 739 u8 flags; /* Special field, reserved for some aq calls */ 740 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 741 struct ice_aqc_elem_info_bw cir_bw; 742 struct ice_aqc_elem_info_bw eir_bw; 743 __le16 srl_id; 744 __le16 reserved2; 745 }; 746 747 struct ice_aqc_txsched_elem_data { 748 __le32 parent_teid; 749 __le32 node_teid; 750 struct ice_aqc_txsched_elem data; 751 }; 752 753 struct ice_aqc_txsched_topo_grp_info_hdr { 754 __le32 parent_teid; 755 __le16 num_elems; 756 __le16 reserved2; 757 }; 758 759 struct ice_aqc_add_elem { 760 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 761 struct ice_aqc_txsched_elem_data generic[]; 762 }; 763 764 struct ice_aqc_get_topo_elem { 765 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 766 struct ice_aqc_txsched_elem_data 767 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 768 }; 769 770 struct ice_aqc_delete_elem { 771 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 772 __le32 teid[]; 773 }; 774 775 /* Query Port ETS (indirect 0x040E) 776 * 777 * This indirect command is used to query port TC node configuration. 778 */ 779 struct ice_aqc_query_port_ets { 780 __le32 port_teid; 781 __le32 reserved; 782 __le32 addr_high; 783 __le32 addr_low; 784 }; 785 786 struct ice_aqc_port_ets_elem { 787 u8 tc_valid_bits; 788 u8 reserved[3]; 789 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 790 __le32 up2tc; 791 u8 tc_bw_share[8]; 792 __le32 port_eir_prof_id; 793 __le32 port_cir_prof_id; 794 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 795 __le32 tc_node_prio; 796 #define ICE_TC_NODE_PRIO_S 0x4 797 u8 reserved1[4]; 798 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 799 }; 800 801 /* Rate limiting profile for 802 * Add RL profile (indirect 0x0410) 803 * Query RL profile (indirect 0x0411) 804 * Remove RL profile (indirect 0x0415) 805 * These indirect commands acts on single or multiple 806 * RL profiles with specified data. 807 */ 808 struct ice_aqc_rl_profile { 809 __le16 num_profiles; 810 __le16 num_processed; /* Only for response. Reserved in Command. */ 811 u8 reserved[4]; 812 __le32 addr_high; 813 __le32 addr_low; 814 }; 815 816 struct ice_aqc_rl_profile_elem { 817 u8 level; 818 u8 flags; 819 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 820 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 821 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 822 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 823 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 824 /* The following flag is used for Query RL Profile Data */ 825 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 826 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 827 828 __le16 profile_id; 829 __le16 max_burst_size; 830 __le16 rl_multiply; 831 __le16 wake_up_calc; 832 __le16 rl_encode; 833 }; 834 835 /* Query Scheduler Resource Allocation (indirect 0x0412) 836 * This indirect command retrieves the scheduler resources allocated by 837 * EMP Firmware to the given PF. 838 */ 839 struct ice_aqc_query_txsched_res { 840 u8 reserved[8]; 841 __le32 addr_high; 842 __le32 addr_low; 843 }; 844 845 struct ice_aqc_generic_sched_props { 846 __le16 phys_levels; 847 __le16 logical_levels; 848 u8 flattening_bitmap; 849 u8 max_device_cgds; 850 u8 max_pf_cgds; 851 u8 rsvd0; 852 __le16 rdma_qsets; 853 u8 rsvd1[22]; 854 }; 855 856 struct ice_aqc_layer_props { 857 u8 logical_layer; 858 u8 chunk_size; 859 __le16 max_device_nodes; 860 __le16 max_pf_nodes; 861 u8 rsvd0[4]; 862 __le16 max_sibl_grp_sz; 863 __le16 max_cir_rl_profiles; 864 __le16 max_eir_rl_profiles; 865 __le16 max_srl_profiles; 866 u8 rsvd1[14]; 867 }; 868 869 struct ice_aqc_query_txsched_res_resp { 870 struct ice_aqc_generic_sched_props sched_props; 871 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 872 }; 873 874 /* Get PHY capabilities (indirect 0x0600) */ 875 struct ice_aqc_get_phy_caps { 876 u8 lport_num; 877 u8 reserved; 878 __le16 param0; 879 /* 18.0 - Report qualified modules */ 880 #define ICE_AQC_GET_PHY_RQM BIT(0) 881 /* 18.1 - 18.3 : Report mode 882 * 000b - Report NVM capabilities 883 * 001b - Report topology capabilities 884 * 010b - Report SW configured 885 * 100b - Report default capabilities 886 */ 887 #define ICE_AQC_REPORT_MODE_S 1 888 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 889 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 890 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 891 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 892 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 893 __le32 reserved1; 894 __le32 addr_high; 895 __le32 addr_low; 896 }; 897 898 /* This is #define of PHY type (Extended): 899 * The first set of defines is for phy_type_low. 900 */ 901 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 902 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 903 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 904 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 905 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 906 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 907 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 908 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 909 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 910 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 911 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 912 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 913 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 914 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 915 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 916 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 917 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 918 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 919 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 920 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 921 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 922 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 923 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 924 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 925 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 926 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 927 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 928 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 929 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 930 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 931 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 932 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 933 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 934 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 935 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 936 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 937 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 938 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 939 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 940 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 941 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 942 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 943 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 944 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 945 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 946 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 947 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 948 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 949 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 950 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 951 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 952 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 953 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 954 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 955 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 956 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 957 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 958 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 959 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 960 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 961 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 962 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 963 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 964 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 965 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 966 /* The second set of defines is for phy_type_high. */ 967 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 968 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 969 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 970 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 971 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 972 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 973 974 struct ice_aqc_get_phy_caps_data { 975 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 976 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 977 u8 caps; 978 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 979 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 980 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 981 #define ICE_AQC_PHY_EN_LINK BIT(3) 982 #define ICE_AQC_PHY_AN_MODE BIT(4) 983 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 984 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 985 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 986 u8 low_power_ctrl_an; 987 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 988 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 989 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 990 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 991 __le16 eee_cap; 992 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 993 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 994 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 995 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 996 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 997 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 998 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 999 __le16 eeer_value; 1000 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1001 u8 phy_fw_ver[8]; 1002 u8 link_fec_options; 1003 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1004 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1005 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1006 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1007 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1008 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1009 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1010 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1011 u8 module_compliance_enforcement; 1012 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1013 u8 extended_compliance_code; 1014 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1015 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1016 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1017 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1018 #define ICE_AQC_MOD_TYPE_IDENT 1 1019 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1020 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1021 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1022 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1023 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1024 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1025 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1026 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1027 u8 qualified_module_count; 1028 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1029 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1030 struct { 1031 u8 v_oui[3]; 1032 u8 rsvd3; 1033 u8 v_part[16]; 1034 __le32 v_rev; 1035 __le64 rsvd4; 1036 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1037 }; 1038 1039 /* Set PHY capabilities (direct 0x0601) 1040 * NOTE: This command must be followed by setup link and restart auto-neg 1041 */ 1042 struct ice_aqc_set_phy_cfg { 1043 u8 lport_num; 1044 u8 reserved[7]; 1045 __le32 addr_high; 1046 __le32 addr_low; 1047 }; 1048 1049 /* Set PHY config command data structure */ 1050 struct ice_aqc_set_phy_cfg_data { 1051 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1052 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1053 u8 caps; 1054 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1055 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1056 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1057 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1058 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1059 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1060 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1061 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1062 u8 low_power_ctrl_an; 1063 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1064 __le16 eeer_value; 1065 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1066 u8 module_compliance_enforcement; 1067 }; 1068 1069 /* Set MAC Config command data structure (direct 0x0603) */ 1070 struct ice_aqc_set_mac_cfg { 1071 __le16 max_frame_size; 1072 u8 params; 1073 #define ICE_AQ_SET_MAC_PACE_S 3 1074 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1075 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1076 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1077 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1078 u8 tx_tmr_priority; 1079 __le16 tx_tmr_value; 1080 __le16 fc_refresh_threshold; 1081 u8 drop_opts; 1082 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1083 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1084 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1085 u8 reserved[7]; 1086 }; 1087 1088 /* Restart AN command data structure (direct 0x0605) 1089 * Also used for response, with only the lport_num field present. 1090 */ 1091 struct ice_aqc_restart_an { 1092 u8 lport_num; 1093 u8 reserved; 1094 u8 cmd_flags; 1095 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1096 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1097 u8 reserved2[13]; 1098 }; 1099 1100 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1101 struct ice_aqc_get_link_status { 1102 u8 lport_num; 1103 u8 reserved; 1104 __le16 cmd_flags; 1105 #define ICE_AQ_LSE_M 0x3 1106 #define ICE_AQ_LSE_NOP 0x0 1107 #define ICE_AQ_LSE_DIS 0x2 1108 #define ICE_AQ_LSE_ENA 0x3 1109 /* only response uses this flag */ 1110 #define ICE_AQ_LSE_IS_ENABLED 0x1 1111 __le32 reserved2; 1112 __le32 addr_high; 1113 __le32 addr_low; 1114 }; 1115 1116 /* Get link status response data structure, also used for Link Status Event */ 1117 struct ice_aqc_get_link_status_data { 1118 u8 topo_media_conflict; 1119 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1120 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1121 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1122 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1123 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1124 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1125 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1126 u8 link_cfg_err; 1127 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1128 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1129 u8 link_info; 1130 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1131 #define ICE_AQ_LINK_FAULT BIT(1) 1132 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1133 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1134 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1135 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1136 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1137 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1138 u8 an_info; 1139 #define ICE_AQ_AN_COMPLETED BIT(0) 1140 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1141 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1142 #define ICE_AQ_FEC_EN BIT(3) 1143 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1144 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1145 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1146 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1147 u8 ext_info; 1148 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1149 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1150 /* Port Tx Suspended */ 1151 #define ICE_AQ_LINK_TX_S 2 1152 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1153 #define ICE_AQ_LINK_TX_ACTIVE 0 1154 #define ICE_AQ_LINK_TX_DRAINED 1 1155 #define ICE_AQ_LINK_TX_FLUSHED 3 1156 u8 reserved2; 1157 __le16 max_frame_size; 1158 u8 cfg; 1159 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1160 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1161 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1162 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1163 /* Pacing Config */ 1164 #define ICE_AQ_CFG_PACING_S 3 1165 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1166 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1167 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1168 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1169 /* External Device Power Ability */ 1170 u8 power_desc; 1171 #define ICE_AQ_PWR_CLASS_M 0x3F 1172 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1173 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1174 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1175 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1176 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1177 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1178 __le16 link_speed; 1179 #define ICE_AQ_LINK_SPEED_M 0x7FF 1180 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1181 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1182 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1183 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1184 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1185 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1186 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1187 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1188 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1189 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1190 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1191 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1192 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1193 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1194 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1195 }; 1196 1197 /* Set event mask command (direct 0x0613) */ 1198 struct ice_aqc_set_event_mask { 1199 u8 lport_num; 1200 u8 reserved[7]; 1201 __le16 event_mask; 1202 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1203 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1204 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1205 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1206 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1207 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1208 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1209 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1210 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1211 u8 reserved1[6]; 1212 }; 1213 1214 /* Set MAC Loopback command (direct 0x0620) */ 1215 struct ice_aqc_set_mac_lb { 1216 u8 lb_mode; 1217 #define ICE_AQ_MAC_LB_EN BIT(0) 1218 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1219 u8 reserved[15]; 1220 }; 1221 1222 struct ice_aqc_link_topo_addr { 1223 u8 lport_num; 1224 u8 lport_num_valid; 1225 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1226 u8 node_type_ctx; 1227 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1228 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1229 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1230 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1231 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1232 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1233 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1234 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1235 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1236 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1237 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1238 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1239 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1240 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1241 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1242 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1243 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1244 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1245 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1246 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1247 u8 index; 1248 __le16 handle; 1249 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1250 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1251 /* Used to decode the handle field */ 1252 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1253 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1254 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1255 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1256 /* In case of a Mezzanine type */ 1257 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1258 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1259 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1260 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1261 /* In case of a LOM type */ 1262 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1263 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1264 }; 1265 1266 /* Get Link Topology Handle (direct, 0x06E0) */ 1267 struct ice_aqc_get_link_topo { 1268 struct ice_aqc_link_topo_addr addr; 1269 u8 node_part_num; 1270 u8 rsvd[9]; 1271 }; 1272 1273 /* Set Port Identification LED (direct, 0x06E9) */ 1274 struct ice_aqc_set_port_id_led { 1275 u8 lport_num; 1276 u8 lport_num_valid; 1277 u8 ident_mode; 1278 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1279 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1280 u8 rsvd[13]; 1281 }; 1282 1283 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1284 struct ice_aqc_sff_eeprom { 1285 u8 lport_num; 1286 u8 lport_num_valid; 1287 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1288 __le16 i2c_bus_addr; 1289 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1290 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1291 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1292 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1293 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1294 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1295 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1296 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1297 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1298 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1299 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1300 __le16 i2c_mem_addr; 1301 __le16 eeprom_page; 1302 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1303 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1304 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1305 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1306 __le32 addr_high; 1307 __le32 addr_low; 1308 }; 1309 1310 /* NVM Read command (indirect 0x0701) 1311 * NVM Erase commands (direct 0x0702) 1312 * NVM Update commands (indirect 0x0703) 1313 */ 1314 struct ice_aqc_nvm { 1315 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1316 __le16 offset_low; 1317 u8 offset_high; 1318 u8 cmd_flags; 1319 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1320 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1321 #define ICE_AQC_NVM_PRESERVATION_S 1 1322 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1323 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1324 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1325 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1326 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1327 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1328 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1329 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1330 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1331 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1332 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1333 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1334 __le16 module_typeid; 1335 __le16 length; 1336 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1337 __le32 addr_high; 1338 __le32 addr_low; 1339 }; 1340 1341 #define ICE_AQC_NVM_START_POINT 0 1342 1343 /* NVM Checksum Command (direct, 0x0706) */ 1344 struct ice_aqc_nvm_checksum { 1345 u8 flags; 1346 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1347 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1348 u8 rsvd; 1349 __le16 checksum; /* Used only by response */ 1350 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1351 u8 rsvd2[12]; 1352 }; 1353 1354 /* Used for NVM Set Package Data command - 0x070A */ 1355 struct ice_aqc_nvm_pkg_data { 1356 u8 reserved[3]; 1357 u8 cmd_flags; 1358 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1359 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1360 1361 u32 reserved1; 1362 __le32 addr_high; 1363 __le32 addr_low; 1364 }; 1365 1366 /* Used for Pass Component Table command - 0x070B */ 1367 struct ice_aqc_nvm_pass_comp_tbl { 1368 u8 component_response; /* Response only */ 1369 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1370 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1371 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1372 u8 component_response_code; /* Response only */ 1373 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1374 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1375 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1376 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1377 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1378 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1379 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1380 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1381 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1382 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1383 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1384 u8 reserved; 1385 u8 transfer_flag; 1386 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1387 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1388 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1389 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1390 __le32 reserved1; 1391 __le32 addr_high; 1392 __le32 addr_low; 1393 }; 1394 1395 struct ice_aqc_nvm_comp_tbl { 1396 __le16 comp_class; 1397 #define NVM_COMP_CLASS_ALL_FW 0x000A 1398 1399 __le16 comp_id; 1400 #define NVM_COMP_ID_OROM 0x5 1401 #define NVM_COMP_ID_NVM 0x6 1402 #define NVM_COMP_ID_NETLIST 0x8 1403 1404 u8 comp_class_idx; 1405 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1406 1407 __le32 comp_cmp_stamp; 1408 u8 cvs_type; 1409 #define NVM_CVS_TYPE_ASCII 0x1 1410 1411 u8 cvs_len; 1412 u8 cvs[]; /* Component Version String */ 1413 } __packed; 1414 1415 /* Send to PF command (indirect 0x0801) ID is only used by PF 1416 * 1417 * Send to VF command (indirect 0x0802) ID is only used by PF 1418 * 1419 */ 1420 struct ice_aqc_pf_vf_msg { 1421 __le32 id; 1422 u32 reserved; 1423 __le32 addr_high; 1424 __le32 addr_low; 1425 }; 1426 1427 /* Get LLDP MIB (indirect 0x0A00) 1428 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1429 * as the format is the same. 1430 */ 1431 struct ice_aqc_lldp_get_mib { 1432 u8 type; 1433 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1434 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1435 #define ICE_AQ_LLDP_MIB_LOCAL 0 1436 #define ICE_AQ_LLDP_MIB_REMOTE 1 1437 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1438 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1439 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1440 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1441 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1442 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1443 #define ICE_AQ_LLDP_TX_S 0x4 1444 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1445 #define ICE_AQ_LLDP_TX_ACTIVE 0 1446 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1447 #define ICE_AQ_LLDP_TX_FLUSHED 3 1448 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1449 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1450 * Get LLDP MIB (0x0A00) response only. 1451 */ 1452 u8 reserved1; 1453 __le16 local_len; 1454 __le16 remote_len; 1455 u8 reserved2[2]; 1456 __le32 addr_high; 1457 __le32 addr_low; 1458 }; 1459 1460 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1461 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1462 struct ice_aqc_lldp_set_mib_change { 1463 u8 command; 1464 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1465 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1466 u8 reserved[15]; 1467 }; 1468 1469 /* Stop LLDP (direct 0x0A05) */ 1470 struct ice_aqc_lldp_stop { 1471 u8 command; 1472 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1473 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1474 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1475 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1476 u8 reserved[15]; 1477 }; 1478 1479 /* Start LLDP (direct 0x0A06) */ 1480 struct ice_aqc_lldp_start { 1481 u8 command; 1482 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1483 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1484 u8 reserved[15]; 1485 }; 1486 1487 /* Get CEE DCBX Oper Config (0x0A07) 1488 * The command uses the generic descriptor struct and 1489 * returns the struct below as an indirect response. 1490 */ 1491 struct ice_aqc_get_cee_dcb_cfg_resp { 1492 u8 oper_num_tc; 1493 u8 oper_prio_tc[4]; 1494 u8 oper_tc_bw[8]; 1495 u8 oper_pfc_en; 1496 __le16 oper_app_prio; 1497 #define ICE_AQC_CEE_APP_FCOE_S 0 1498 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1499 #define ICE_AQC_CEE_APP_ISCSI_S 3 1500 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1501 #define ICE_AQC_CEE_APP_FIP_S 8 1502 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1503 __le32 tlv_status; 1504 #define ICE_AQC_CEE_PG_STATUS_S 0 1505 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1506 #define ICE_AQC_CEE_PFC_STATUS_S 3 1507 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1508 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1509 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1510 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1511 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1512 #define ICE_AQC_CEE_FIP_STATUS_S 16 1513 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1514 u8 reserved[12]; 1515 }; 1516 1517 /* Set Local LLDP MIB (indirect 0x0A08) 1518 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1519 */ 1520 struct ice_aqc_lldp_set_local_mib { 1521 u8 type; 1522 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1523 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1524 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1525 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1526 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1527 u8 reserved0; 1528 __le16 length; 1529 u8 reserved1[4]; 1530 __le32 addr_high; 1531 __le32 addr_low; 1532 }; 1533 1534 /* Stop/Start LLDP Agent (direct 0x0A09) 1535 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1536 * The same structure is used for the response, with the command field 1537 * being used as the status field. 1538 */ 1539 struct ice_aqc_lldp_stop_start_specific_agent { 1540 u8 command; 1541 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1542 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1543 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1544 u8 reserved[15]; 1545 }; 1546 1547 /* LLDP Filter Control (direct 0x0A0A) */ 1548 struct ice_aqc_lldp_filter_ctrl { 1549 u8 cmd_flags; 1550 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1551 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1552 u8 reserved1; 1553 __le16 vsi_num; 1554 u8 reserved2[12]; 1555 }; 1556 1557 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1558 struct ice_aqc_get_set_rss_key { 1559 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1560 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1561 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1562 __le16 vsi_id; 1563 u8 reserved[6]; 1564 __le32 addr_high; 1565 __le32 addr_low; 1566 }; 1567 1568 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1569 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1570 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1571 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1572 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1573 1574 struct ice_aqc_get_set_rss_keys { 1575 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1576 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1577 }; 1578 1579 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1580 struct ice_aqc_get_set_rss_lut { 1581 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1582 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1583 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1584 __le16 vsi_id; 1585 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1586 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1587 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1588 1589 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1590 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1591 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1592 1593 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1594 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1595 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1596 1597 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1598 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1599 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1600 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1601 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1602 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1603 1604 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1605 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1606 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1607 1608 __le16 flags; 1609 __le32 reserved; 1610 __le32 addr_high; 1611 __le32 addr_low; 1612 }; 1613 1614 /* Add Tx LAN Queues (indirect 0x0C30) */ 1615 struct ice_aqc_add_txqs { 1616 u8 num_qgrps; 1617 u8 reserved[3]; 1618 __le32 reserved1; 1619 __le32 addr_high; 1620 __le32 addr_low; 1621 }; 1622 1623 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1624 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1625 */ 1626 struct ice_aqc_add_txqs_perq { 1627 __le16 txq_id; 1628 u8 rsvd[2]; 1629 __le32 q_teid; 1630 u8 txq_ctx[22]; 1631 u8 rsvd2[2]; 1632 struct ice_aqc_txsched_elem info; 1633 }; 1634 1635 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1636 * is an array of the following structs. Please note that the length of 1637 * each struct ice_aqc_add_tx_qgrp is variable due 1638 * to the variable number of queues in each group! 1639 */ 1640 struct ice_aqc_add_tx_qgrp { 1641 __le32 parent_teid; 1642 u8 num_txqs; 1643 u8 rsvd[3]; 1644 struct ice_aqc_add_txqs_perq txqs[]; 1645 }; 1646 1647 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1648 struct ice_aqc_dis_txqs { 1649 u8 cmd_type; 1650 #define ICE_AQC_Q_DIS_CMD_S 0 1651 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1652 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1653 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1654 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1655 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1656 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1657 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1658 u8 num_entries; 1659 __le16 vmvf_and_timeout; 1660 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1661 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1662 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1663 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1664 __le32 blocked_cgds; 1665 __le32 addr_high; 1666 __le32 addr_low; 1667 }; 1668 1669 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1670 * contains the following structures, arrayed one after the 1671 * other. 1672 * Note: Since the q_id is 16 bits wide, if the 1673 * number of queues is even, then 2 bytes of alignment MUST be 1674 * added before the start of the next group, to allow correct 1675 * alignment of the parent_teid field. 1676 */ 1677 struct ice_aqc_dis_txq_item { 1678 __le32 parent_teid; 1679 u8 num_qs; 1680 u8 rsvd; 1681 /* The length of the q_id array varies according to num_qs */ 1682 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1683 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1684 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1685 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1686 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1687 __le16 q_id[]; 1688 } __packed; 1689 1690 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 1691 struct ice_aqc_add_rdma_qset { 1692 u8 num_qset_grps; 1693 u8 reserved[7]; 1694 __le32 addr_high; 1695 __le32 addr_low; 1696 }; 1697 1698 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 1699 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 1700 */ 1701 struct ice_aqc_add_tx_rdma_qset_entry { 1702 __le16 tx_qset_id; 1703 u8 rsvd[2]; 1704 __le32 qset_teid; 1705 struct ice_aqc_txsched_elem info; 1706 }; 1707 1708 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 1709 * is an array of the following structs. Please note that the length of 1710 * each struct ice_aqc_add_rdma_qset is variable due to the variable 1711 * number of queues in each group! 1712 */ 1713 struct ice_aqc_add_rdma_qset_data { 1714 __le32 parent_teid; 1715 __le16 num_qsets; 1716 u8 rsvd[2]; 1717 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 1718 }; 1719 1720 /* Configure Firmware Logging Command (indirect 0xFF09) 1721 * Logging Information Read Response (indirect 0xFF10) 1722 * Note: The 0xFF10 command has no input parameters. 1723 */ 1724 struct ice_aqc_fw_logging { 1725 u8 log_ctrl; 1726 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1727 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1728 u8 rsvd0; 1729 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1730 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1731 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1732 u8 rsvd1[5]; 1733 __le32 addr_high; 1734 __le32 addr_low; 1735 }; 1736 1737 enum ice_aqc_fw_logging_mod { 1738 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1739 ICE_AQC_FW_LOG_ID_CTRL, 1740 ICE_AQC_FW_LOG_ID_LINK, 1741 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1742 ICE_AQC_FW_LOG_ID_DNL, 1743 ICE_AQC_FW_LOG_ID_I2C, 1744 ICE_AQC_FW_LOG_ID_SDP, 1745 ICE_AQC_FW_LOG_ID_MDIO, 1746 ICE_AQC_FW_LOG_ID_ADMINQ, 1747 ICE_AQC_FW_LOG_ID_HDMA, 1748 ICE_AQC_FW_LOG_ID_LLDP, 1749 ICE_AQC_FW_LOG_ID_DCBX, 1750 ICE_AQC_FW_LOG_ID_DCB, 1751 ICE_AQC_FW_LOG_ID_NETPROXY, 1752 ICE_AQC_FW_LOG_ID_NVM, 1753 ICE_AQC_FW_LOG_ID_AUTH, 1754 ICE_AQC_FW_LOG_ID_VPD, 1755 ICE_AQC_FW_LOG_ID_IOSF, 1756 ICE_AQC_FW_LOG_ID_PARSER, 1757 ICE_AQC_FW_LOG_ID_SW, 1758 ICE_AQC_FW_LOG_ID_SCHEDULER, 1759 ICE_AQC_FW_LOG_ID_TXQ, 1760 ICE_AQC_FW_LOG_ID_RSVD, 1761 ICE_AQC_FW_LOG_ID_POST, 1762 ICE_AQC_FW_LOG_ID_WATCHDOG, 1763 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1764 ICE_AQC_FW_LOG_ID_MNG, 1765 ICE_AQC_FW_LOG_ID_MAX, 1766 }; 1767 1768 /* Defines for both above FW logging command/response buffers */ 1769 #define ICE_AQC_FW_LOG_ID_S 0 1770 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1771 1772 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1773 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1774 1775 #define ICE_AQC_FW_LOG_EN_S 12 1776 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1777 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1778 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1779 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1780 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1781 1782 /* Get/Clear FW Log (indirect 0xFF11) */ 1783 struct ice_aqc_get_clear_fw_log { 1784 u8 flags; 1785 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1786 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1787 u8 rsvd1[7]; 1788 __le32 addr_high; 1789 __le32 addr_low; 1790 }; 1791 1792 /* Download Package (indirect 0x0C40) */ 1793 /* Also used for Update Package (indirect 0x0C42) */ 1794 struct ice_aqc_download_pkg { 1795 u8 flags; 1796 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1797 u8 reserved[3]; 1798 __le32 reserved1; 1799 __le32 addr_high; 1800 __le32 addr_low; 1801 }; 1802 1803 struct ice_aqc_download_pkg_resp { 1804 __le32 error_offset; 1805 __le32 error_info; 1806 __le32 addr_high; 1807 __le32 addr_low; 1808 }; 1809 1810 /* Get Package Info List (indirect 0x0C43) */ 1811 struct ice_aqc_get_pkg_info_list { 1812 __le32 reserved1; 1813 __le32 reserved2; 1814 __le32 addr_high; 1815 __le32 addr_low; 1816 }; 1817 1818 /* Version format for packages */ 1819 struct ice_pkg_ver { 1820 u8 major; 1821 u8 minor; 1822 u8 update; 1823 u8 draft; 1824 }; 1825 1826 #define ICE_PKG_NAME_SIZE 32 1827 #define ICE_SEG_ID_SIZE 28 1828 #define ICE_SEG_NAME_SIZE 28 1829 1830 struct ice_aqc_get_pkg_info { 1831 struct ice_pkg_ver ver; 1832 char name[ICE_SEG_NAME_SIZE]; 1833 __le32 track_id; 1834 u8 is_in_nvm; 1835 u8 is_active; 1836 u8 is_active_at_boot; 1837 u8 is_modified; 1838 }; 1839 1840 /* Get Package Info List response buffer format (0x0C43) */ 1841 struct ice_aqc_get_pkg_info_resp { 1842 __le32 count; 1843 struct ice_aqc_get_pkg_info pkg_info[]; 1844 }; 1845 1846 /* Lan Queue Overflow Event (direct, 0x1001) */ 1847 struct ice_aqc_event_lan_overflow { 1848 __le32 prtdcb_ruptq; 1849 __le32 qtx_ctl; 1850 u8 reserved[8]; 1851 }; 1852 1853 /** 1854 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1855 * @flags: ICE_AQ_FLAG_* flags 1856 * @opcode: AQ command opcode 1857 * @datalen: length in bytes of indirect/external data buffer 1858 * @retval: return value from firmware 1859 * @cookie_high: opaque data high-half 1860 * @cookie_low: opaque data low-half 1861 * @params: command-specific parameters 1862 * 1863 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1864 * (ATQ). The firmware writes back onto the command descriptor and returns 1865 * the result of the command. Asynchronous events that are not an immediate 1866 * result of the command are written to the Admin Receive Queue (ARQ) using 1867 * the same descriptor format. Descriptors are in little-endian notation with 1868 * 32-bit words. 1869 */ 1870 struct ice_aq_desc { 1871 __le16 flags; 1872 __le16 opcode; 1873 __le16 datalen; 1874 __le16 retval; 1875 __le32 cookie_high; 1876 __le32 cookie_low; 1877 union { 1878 u8 raw[16]; 1879 struct ice_aqc_generic generic; 1880 struct ice_aqc_get_ver get_ver; 1881 struct ice_aqc_driver_ver driver_ver; 1882 struct ice_aqc_q_shutdown q_shutdown; 1883 struct ice_aqc_req_res res_owner; 1884 struct ice_aqc_manage_mac_read mac_read; 1885 struct ice_aqc_manage_mac_write mac_write; 1886 struct ice_aqc_clear_pxe clear_pxe; 1887 struct ice_aqc_list_caps get_cap; 1888 struct ice_aqc_get_phy_caps get_phy; 1889 struct ice_aqc_set_phy_cfg set_phy; 1890 struct ice_aqc_restart_an restart_an; 1891 struct ice_aqc_sff_eeprom read_write_sff_param; 1892 struct ice_aqc_set_port_id_led set_port_id_led; 1893 struct ice_aqc_get_sw_cfg get_sw_conf; 1894 struct ice_aqc_sw_rules sw_rules; 1895 struct ice_aqc_get_topo get_topo; 1896 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1897 struct ice_aqc_query_txsched_res query_sched_res; 1898 struct ice_aqc_query_port_ets port_ets; 1899 struct ice_aqc_rl_profile rl_profile; 1900 struct ice_aqc_nvm nvm; 1901 struct ice_aqc_nvm_checksum nvm_checksum; 1902 struct ice_aqc_nvm_pkg_data pkg_data; 1903 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 1904 struct ice_aqc_pf_vf_msg virt; 1905 struct ice_aqc_lldp_get_mib lldp_get_mib; 1906 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1907 struct ice_aqc_lldp_stop lldp_stop; 1908 struct ice_aqc_lldp_start lldp_start; 1909 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1910 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1911 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 1912 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1913 struct ice_aqc_get_set_rss_key get_set_rss_key; 1914 struct ice_aqc_add_txqs add_txqs; 1915 struct ice_aqc_dis_txqs dis_txqs; 1916 struct ice_aqc_add_rdma_qset add_rdma_qset; 1917 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1918 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1919 struct ice_aqc_fw_logging fw_logging; 1920 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1921 struct ice_aqc_download_pkg download_pkg; 1922 struct ice_aqc_set_mac_lb set_mac_lb; 1923 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1924 struct ice_aqc_set_mac_cfg set_mac_cfg; 1925 struct ice_aqc_set_event_mask set_event_mask; 1926 struct ice_aqc_get_link_status get_link_status; 1927 struct ice_aqc_event_lan_overflow lan_overflow; 1928 struct ice_aqc_get_link_topo get_link_topo; 1929 } params; 1930 }; 1931 1932 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1933 #define ICE_AQ_LG_BUF 512 1934 1935 #define ICE_AQ_FLAG_ERR_S 2 1936 #define ICE_AQ_FLAG_LB_S 9 1937 #define ICE_AQ_FLAG_RD_S 10 1938 #define ICE_AQ_FLAG_BUF_S 12 1939 #define ICE_AQ_FLAG_SI_S 13 1940 1941 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1942 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1943 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1944 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1945 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1946 1947 /* error codes */ 1948 enum ice_aq_err { 1949 ICE_AQ_RC_OK = 0, /* Success */ 1950 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1951 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1952 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1953 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1954 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1955 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1956 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1957 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1958 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1959 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1960 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1961 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1962 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1963 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 1964 }; 1965 1966 /* Admin Queue command opcodes */ 1967 enum ice_adminq_opc { 1968 /* AQ commands */ 1969 ice_aqc_opc_get_ver = 0x0001, 1970 ice_aqc_opc_driver_ver = 0x0002, 1971 ice_aqc_opc_q_shutdown = 0x0003, 1972 1973 /* resource ownership */ 1974 ice_aqc_opc_req_res = 0x0008, 1975 ice_aqc_opc_release_res = 0x0009, 1976 1977 /* device/function capabilities */ 1978 ice_aqc_opc_list_func_caps = 0x000A, 1979 ice_aqc_opc_list_dev_caps = 0x000B, 1980 1981 /* manage MAC address */ 1982 ice_aqc_opc_manage_mac_read = 0x0107, 1983 ice_aqc_opc_manage_mac_write = 0x0108, 1984 1985 /* PXE */ 1986 ice_aqc_opc_clear_pxe_mode = 0x0110, 1987 1988 /* internal switch commands */ 1989 ice_aqc_opc_get_sw_cfg = 0x0200, 1990 1991 /* Alloc/Free/Get Resources */ 1992 ice_aqc_opc_alloc_res = 0x0208, 1993 ice_aqc_opc_free_res = 0x0209, 1994 1995 /* VSI commands */ 1996 ice_aqc_opc_add_vsi = 0x0210, 1997 ice_aqc_opc_update_vsi = 0x0211, 1998 ice_aqc_opc_free_vsi = 0x0213, 1999 2000 /* switch rules population commands */ 2001 ice_aqc_opc_add_sw_rules = 0x02A0, 2002 ice_aqc_opc_update_sw_rules = 0x02A1, 2003 ice_aqc_opc_remove_sw_rules = 0x02A2, 2004 2005 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2006 2007 /* transmit scheduler commands */ 2008 ice_aqc_opc_get_dflt_topo = 0x0400, 2009 ice_aqc_opc_add_sched_elems = 0x0401, 2010 ice_aqc_opc_cfg_sched_elems = 0x0403, 2011 ice_aqc_opc_get_sched_elems = 0x0404, 2012 ice_aqc_opc_move_sched_elems = 0x0408, 2013 ice_aqc_opc_suspend_sched_elems = 0x0409, 2014 ice_aqc_opc_resume_sched_elems = 0x040A, 2015 ice_aqc_opc_query_port_ets = 0x040E, 2016 ice_aqc_opc_delete_sched_elems = 0x040F, 2017 ice_aqc_opc_add_rl_profiles = 0x0410, 2018 ice_aqc_opc_query_sched_res = 0x0412, 2019 ice_aqc_opc_remove_rl_profiles = 0x0415, 2020 2021 /* PHY commands */ 2022 ice_aqc_opc_get_phy_caps = 0x0600, 2023 ice_aqc_opc_set_phy_cfg = 0x0601, 2024 ice_aqc_opc_set_mac_cfg = 0x0603, 2025 ice_aqc_opc_restart_an = 0x0605, 2026 ice_aqc_opc_get_link_status = 0x0607, 2027 ice_aqc_opc_set_event_mask = 0x0613, 2028 ice_aqc_opc_set_mac_lb = 0x0620, 2029 ice_aqc_opc_get_link_topo = 0x06E0, 2030 ice_aqc_opc_set_port_id_led = 0x06E9, 2031 ice_aqc_opc_sff_eeprom = 0x06EE, 2032 2033 /* NVM commands */ 2034 ice_aqc_opc_nvm_read = 0x0701, 2035 ice_aqc_opc_nvm_erase = 0x0702, 2036 ice_aqc_opc_nvm_write = 0x0703, 2037 ice_aqc_opc_nvm_checksum = 0x0706, 2038 ice_aqc_opc_nvm_write_activate = 0x0707, 2039 ice_aqc_opc_nvm_update_empr = 0x0709, 2040 ice_aqc_opc_nvm_pkg_data = 0x070A, 2041 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2042 2043 /* PF/VF mailbox commands */ 2044 ice_mbx_opc_send_msg_to_pf = 0x0801, 2045 ice_mbx_opc_send_msg_to_vf = 0x0802, 2046 /* LLDP commands */ 2047 ice_aqc_opc_lldp_get_mib = 0x0A00, 2048 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2049 ice_aqc_opc_lldp_stop = 0x0A05, 2050 ice_aqc_opc_lldp_start = 0x0A06, 2051 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2052 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2053 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2054 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2055 2056 /* RSS commands */ 2057 ice_aqc_opc_set_rss_key = 0x0B02, 2058 ice_aqc_opc_set_rss_lut = 0x0B03, 2059 ice_aqc_opc_get_rss_key = 0x0B04, 2060 ice_aqc_opc_get_rss_lut = 0x0B05, 2061 2062 /* Tx queue handling commands/events */ 2063 ice_aqc_opc_add_txqs = 0x0C30, 2064 ice_aqc_opc_dis_txqs = 0x0C31, 2065 ice_aqc_opc_add_rdma_qset = 0x0C33, 2066 2067 /* package commands */ 2068 ice_aqc_opc_download_pkg = 0x0C40, 2069 ice_aqc_opc_update_pkg = 0x0C42, 2070 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2071 2072 /* Standalone Commands/Events */ 2073 ice_aqc_opc_event_lan_overflow = 0x1001, 2074 2075 /* debug commands */ 2076 ice_aqc_opc_fw_logging = 0xFF09, 2077 ice_aqc_opc_fw_logging_info = 0xFF10, 2078 }; 2079 2080 #endif /* _ICE_ADMINQ_CMD_H_ */ 2081